Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 8 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
9 | * |
10 | * Authors: | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * | |
14 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
15 | * the COPYING file in the top-level directory. | |
16 | * | |
17 | */ | |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
00b27a3e | 21 | #include "cpuid.h" |
d62caabb | 22 | #include "lapic.h" |
e495606d | 23 | |
edf88417 | 24 | #include <linux/kvm_host.h> |
6aa8b732 | 25 | #include <linux/module.h> |
9d8f549d | 26 | #include <linux/kernel.h> |
6aa8b732 AK |
27 | #include <linux/mm.h> |
28 | #include <linux/highmem.h> | |
e8edc6e0 | 29 | #include <linux/sched.h> |
c7addb90 | 30 | #include <linux/moduleparam.h> |
e9bda3b3 | 31 | #include <linux/mod_devicetable.h> |
af658dca | 32 | #include <linux/trace_events.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
cafd6659 | 34 | #include <linux/tboot.h> |
f4124500 | 35 | #include <linux/hrtimer.h> |
5fdbf976 | 36 | #include "kvm_cache_regs.h" |
35920a35 | 37 | #include "x86.h" |
e495606d | 38 | |
28b835d6 | 39 | #include <asm/cpu.h> |
6aa8b732 | 40 | #include <asm/io.h> |
3b3be0d1 | 41 | #include <asm/desc.h> |
13673a90 | 42 | #include <asm/vmx.h> |
6210e37b | 43 | #include <asm/virtext.h> |
a0861c02 | 44 | #include <asm/mce.h> |
952f07ec | 45 | #include <asm/fpu/internal.h> |
d7cd9796 | 46 | #include <asm/perf_event.h> |
81908bf4 | 47 | #include <asm/debugreg.h> |
8f536b76 | 48 | #include <asm/kexec.h> |
dab2087d | 49 | #include <asm/apic.h> |
efc64404 | 50 | #include <asm/irq_remapping.h> |
6aa8b732 | 51 | |
229456fc | 52 | #include "trace.h" |
25462f7f | 53 | #include "pmu.h" |
229456fc | 54 | |
4ecac3fd | 55 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
5e520e62 AK |
56 | #define __ex_clear(x, reg) \ |
57 | ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg) | |
4ecac3fd | 58 | |
6aa8b732 AK |
59 | MODULE_AUTHOR("Qumranet"); |
60 | MODULE_LICENSE("GPL"); | |
61 | ||
e9bda3b3 JT |
62 | static const struct x86_cpu_id vmx_cpu_id[] = { |
63 | X86_FEATURE_MATCH(X86_FEATURE_VMX), | |
64 | {} | |
65 | }; | |
66 | MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); | |
67 | ||
476bc001 | 68 | static bool __read_mostly enable_vpid = 1; |
736caefe | 69 | module_param_named(vpid, enable_vpid, bool, 0444); |
2384d2b3 | 70 | |
476bc001 | 71 | static bool __read_mostly flexpriority_enabled = 1; |
736caefe | 72 | module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); |
4c9fc8ef | 73 | |
476bc001 | 74 | static bool __read_mostly enable_ept = 1; |
736caefe | 75 | module_param_named(ept, enable_ept, bool, S_IRUGO); |
d56f546d | 76 | |
476bc001 | 77 | static bool __read_mostly enable_unrestricted_guest = 1; |
3a624e29 NK |
78 | module_param_named(unrestricted_guest, |
79 | enable_unrestricted_guest, bool, S_IRUGO); | |
80 | ||
83c3a331 XH |
81 | static bool __read_mostly enable_ept_ad_bits = 1; |
82 | module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); | |
83 | ||
a27685c3 | 84 | static bool __read_mostly emulate_invalid_guest_state = true; |
c1f8bc04 | 85 | module_param(emulate_invalid_guest_state, bool, S_IRUGO); |
04fa4d32 | 86 | |
476bc001 | 87 | static bool __read_mostly vmm_exclusive = 1; |
b923e62e DX |
88 | module_param(vmm_exclusive, bool, S_IRUGO); |
89 | ||
476bc001 | 90 | static bool __read_mostly fasteoi = 1; |
58fbbf26 KT |
91 | module_param(fasteoi, bool, S_IRUGO); |
92 | ||
5a71785d | 93 | static bool __read_mostly enable_apicv = 1; |
01e439be | 94 | module_param(enable_apicv, bool, S_IRUGO); |
83d4c286 | 95 | |
abc4fc58 AG |
96 | static bool __read_mostly enable_shadow_vmcs = 1; |
97 | module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO); | |
801d3424 NHE |
98 | /* |
99 | * If nested=1, nested virtualization is supported, i.e., guests may use | |
100 | * VMX and be a hypervisor for its own guests. If nested=0, guests may not | |
101 | * use VMX instructions. | |
102 | */ | |
476bc001 | 103 | static bool __read_mostly nested = 0; |
801d3424 NHE |
104 | module_param(nested, bool, S_IRUGO); |
105 | ||
20300099 WL |
106 | static u64 __read_mostly host_xss; |
107 | ||
843e4330 KH |
108 | static bool __read_mostly enable_pml = 1; |
109 | module_param_named(pml, enable_pml, bool, S_IRUGO); | |
110 | ||
64903d61 HZ |
111 | #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL |
112 | ||
64672c95 YJ |
113 | /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ |
114 | static int __read_mostly cpu_preemption_timer_multi; | |
115 | static bool __read_mostly enable_preemption_timer = 1; | |
116 | #ifdef CONFIG_X86_64 | |
117 | module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); | |
118 | #endif | |
119 | ||
5037878e GN |
120 | #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD) |
121 | #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE) | |
cdc0e244 AK |
122 | #define KVM_VM_CR0_ALWAYS_ON \ |
123 | (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) | |
4c38609a AK |
124 | #define KVM_CR4_GUEST_OWNED_BITS \ |
125 | (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
52ce3c21 | 126 | | X86_CR4_OSXMMEXCPT | X86_CR4_TSD) |
4c38609a | 127 | |
cdc0e244 AK |
128 | #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) |
129 | #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) | |
130 | ||
78ac8b47 AK |
131 | #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) |
132 | ||
f4124500 JK |
133 | #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5 |
134 | ||
bcdde302 JD |
135 | #define VMX_VPID_EXTENT_SUPPORTED_MASK \ |
136 | (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \ | |
137 | VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \ | |
138 | VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \ | |
139 | VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT) | |
140 | ||
4b8d54f9 ZE |
141 | /* |
142 | * These 2 parameters are used to config the controls for Pause-Loop Exiting: | |
143 | * ple_gap: upper bound on the amount of time between two successive | |
144 | * executions of PAUSE in a loop. Also indicate if ple enabled. | |
00c25bce | 145 | * According to test, this time is usually smaller than 128 cycles. |
4b8d54f9 ZE |
146 | * ple_window: upper bound on the amount of time a guest is allowed to execute |
147 | * in a PAUSE loop. Tests indicate that most spinlocks are held for | |
148 | * less than 2^12 cycles | |
149 | * Time is measured based on a counter that runs at the same rate as the TSC, | |
150 | * refer SDM volume 3b section 21.6.13 & 22.1.3. | |
151 | */ | |
b4a2d31d RK |
152 | #define KVM_VMX_DEFAULT_PLE_GAP 128 |
153 | #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 | |
154 | #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2 | |
155 | #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0 | |
156 | #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \ | |
157 | INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW | |
158 | ||
4b8d54f9 ZE |
159 | static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP; |
160 | module_param(ple_gap, int, S_IRUGO); | |
161 | ||
162 | static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; | |
163 | module_param(ple_window, int, S_IRUGO); | |
164 | ||
b4a2d31d RK |
165 | /* Default doubles per-vcpu window every exit. */ |
166 | static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW; | |
167 | module_param(ple_window_grow, int, S_IRUGO); | |
168 | ||
169 | /* Default resets per-vcpu window every exit to ple_window. */ | |
170 | static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK; | |
171 | module_param(ple_window_shrink, int, S_IRUGO); | |
172 | ||
173 | /* Default is to compute the maximum so we can never overflow. */ | |
174 | static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; | |
175 | static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; | |
176 | module_param(ple_window_max, int, S_IRUGO); | |
177 | ||
83287ea4 AK |
178 | extern const ulong vmx_return; |
179 | ||
8bf00a52 | 180 | #define NR_AUTOLOAD_MSRS 8 |
ff2f6fe9 | 181 | #define VMCS02_POOL_SIZE 1 |
61d2ef2c | 182 | |
a2fa3e9f GH |
183 | struct vmcs { |
184 | u32 revision_id; | |
185 | u32 abort; | |
186 | char data[0]; | |
187 | }; | |
188 | ||
d462b819 NHE |
189 | /* |
190 | * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also | |
191 | * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs | |
192 | * loaded on this CPU (so we can clear them if the CPU goes down). | |
193 | */ | |
194 | struct loaded_vmcs { | |
195 | struct vmcs *vmcs; | |
355f4fb1 | 196 | struct vmcs *shadow_vmcs; |
d462b819 NHE |
197 | int cpu; |
198 | int launched; | |
199 | struct list_head loaded_vmcss_on_cpu_link; | |
200 | }; | |
201 | ||
26bb0981 AK |
202 | struct shared_msr_entry { |
203 | unsigned index; | |
204 | u64 data; | |
d5696725 | 205 | u64 mask; |
26bb0981 AK |
206 | }; |
207 | ||
a9d30f33 NHE |
208 | /* |
209 | * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a | |
210 | * single nested guest (L2), hence the name vmcs12. Any VMX implementation has | |
211 | * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is | |
212 | * stored in guest memory specified by VMPTRLD, but is opaque to the guest, | |
213 | * which must access it using VMREAD/VMWRITE/VMCLEAR instructions. | |
214 | * More than one of these structures may exist, if L1 runs multiple L2 guests. | |
215 | * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the | |
216 | * underlying hardware which will be used to run L2. | |
217 | * This structure is packed to ensure that its layout is identical across | |
218 | * machines (necessary for live migration). | |
219 | * If there are changes in this struct, VMCS12_REVISION must be changed. | |
220 | */ | |
22bd0358 | 221 | typedef u64 natural_width; |
a9d30f33 NHE |
222 | struct __packed vmcs12 { |
223 | /* According to the Intel spec, a VMCS region must start with the | |
224 | * following two fields. Then follow implementation-specific data. | |
225 | */ | |
226 | u32 revision_id; | |
227 | u32 abort; | |
22bd0358 | 228 | |
27d6c865 NHE |
229 | u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */ |
230 | u32 padding[7]; /* room for future expansion */ | |
231 | ||
22bd0358 NHE |
232 | u64 io_bitmap_a; |
233 | u64 io_bitmap_b; | |
234 | u64 msr_bitmap; | |
235 | u64 vm_exit_msr_store_addr; | |
236 | u64 vm_exit_msr_load_addr; | |
237 | u64 vm_entry_msr_load_addr; | |
238 | u64 tsc_offset; | |
239 | u64 virtual_apic_page_addr; | |
240 | u64 apic_access_addr; | |
705699a1 | 241 | u64 posted_intr_desc_addr; |
22bd0358 | 242 | u64 ept_pointer; |
608406e2 WV |
243 | u64 eoi_exit_bitmap0; |
244 | u64 eoi_exit_bitmap1; | |
245 | u64 eoi_exit_bitmap2; | |
246 | u64 eoi_exit_bitmap3; | |
81dc01f7 | 247 | u64 xss_exit_bitmap; |
22bd0358 NHE |
248 | u64 guest_physical_address; |
249 | u64 vmcs_link_pointer; | |
250 | u64 guest_ia32_debugctl; | |
251 | u64 guest_ia32_pat; | |
252 | u64 guest_ia32_efer; | |
253 | u64 guest_ia32_perf_global_ctrl; | |
254 | u64 guest_pdptr0; | |
255 | u64 guest_pdptr1; | |
256 | u64 guest_pdptr2; | |
257 | u64 guest_pdptr3; | |
36be0b9d | 258 | u64 guest_bndcfgs; |
22bd0358 NHE |
259 | u64 host_ia32_pat; |
260 | u64 host_ia32_efer; | |
261 | u64 host_ia32_perf_global_ctrl; | |
262 | u64 padding64[8]; /* room for future expansion */ | |
263 | /* | |
264 | * To allow migration of L1 (complete with its L2 guests) between | |
265 | * machines of different natural widths (32 or 64 bit), we cannot have | |
266 | * unsigned long fields with no explict size. We use u64 (aliased | |
267 | * natural_width) instead. Luckily, x86 is little-endian. | |
268 | */ | |
269 | natural_width cr0_guest_host_mask; | |
270 | natural_width cr4_guest_host_mask; | |
271 | natural_width cr0_read_shadow; | |
272 | natural_width cr4_read_shadow; | |
273 | natural_width cr3_target_value0; | |
274 | natural_width cr3_target_value1; | |
275 | natural_width cr3_target_value2; | |
276 | natural_width cr3_target_value3; | |
277 | natural_width exit_qualification; | |
278 | natural_width guest_linear_address; | |
279 | natural_width guest_cr0; | |
280 | natural_width guest_cr3; | |
281 | natural_width guest_cr4; | |
282 | natural_width guest_es_base; | |
283 | natural_width guest_cs_base; | |
284 | natural_width guest_ss_base; | |
285 | natural_width guest_ds_base; | |
286 | natural_width guest_fs_base; | |
287 | natural_width guest_gs_base; | |
288 | natural_width guest_ldtr_base; | |
289 | natural_width guest_tr_base; | |
290 | natural_width guest_gdtr_base; | |
291 | natural_width guest_idtr_base; | |
292 | natural_width guest_dr7; | |
293 | natural_width guest_rsp; | |
294 | natural_width guest_rip; | |
295 | natural_width guest_rflags; | |
296 | natural_width guest_pending_dbg_exceptions; | |
297 | natural_width guest_sysenter_esp; | |
298 | natural_width guest_sysenter_eip; | |
299 | natural_width host_cr0; | |
300 | natural_width host_cr3; | |
301 | natural_width host_cr4; | |
302 | natural_width host_fs_base; | |
303 | natural_width host_gs_base; | |
304 | natural_width host_tr_base; | |
305 | natural_width host_gdtr_base; | |
306 | natural_width host_idtr_base; | |
307 | natural_width host_ia32_sysenter_esp; | |
308 | natural_width host_ia32_sysenter_eip; | |
309 | natural_width host_rsp; | |
310 | natural_width host_rip; | |
311 | natural_width paddingl[8]; /* room for future expansion */ | |
312 | u32 pin_based_vm_exec_control; | |
313 | u32 cpu_based_vm_exec_control; | |
314 | u32 exception_bitmap; | |
315 | u32 page_fault_error_code_mask; | |
316 | u32 page_fault_error_code_match; | |
317 | u32 cr3_target_count; | |
318 | u32 vm_exit_controls; | |
319 | u32 vm_exit_msr_store_count; | |
320 | u32 vm_exit_msr_load_count; | |
321 | u32 vm_entry_controls; | |
322 | u32 vm_entry_msr_load_count; | |
323 | u32 vm_entry_intr_info_field; | |
324 | u32 vm_entry_exception_error_code; | |
325 | u32 vm_entry_instruction_len; | |
326 | u32 tpr_threshold; | |
327 | u32 secondary_vm_exec_control; | |
328 | u32 vm_instruction_error; | |
329 | u32 vm_exit_reason; | |
330 | u32 vm_exit_intr_info; | |
331 | u32 vm_exit_intr_error_code; | |
332 | u32 idt_vectoring_info_field; | |
333 | u32 idt_vectoring_error_code; | |
334 | u32 vm_exit_instruction_len; | |
335 | u32 vmx_instruction_info; | |
336 | u32 guest_es_limit; | |
337 | u32 guest_cs_limit; | |
338 | u32 guest_ss_limit; | |
339 | u32 guest_ds_limit; | |
340 | u32 guest_fs_limit; | |
341 | u32 guest_gs_limit; | |
342 | u32 guest_ldtr_limit; | |
343 | u32 guest_tr_limit; | |
344 | u32 guest_gdtr_limit; | |
345 | u32 guest_idtr_limit; | |
346 | u32 guest_es_ar_bytes; | |
347 | u32 guest_cs_ar_bytes; | |
348 | u32 guest_ss_ar_bytes; | |
349 | u32 guest_ds_ar_bytes; | |
350 | u32 guest_fs_ar_bytes; | |
351 | u32 guest_gs_ar_bytes; | |
352 | u32 guest_ldtr_ar_bytes; | |
353 | u32 guest_tr_ar_bytes; | |
354 | u32 guest_interruptibility_info; | |
355 | u32 guest_activity_state; | |
356 | u32 guest_sysenter_cs; | |
357 | u32 host_ia32_sysenter_cs; | |
0238ea91 JK |
358 | u32 vmx_preemption_timer_value; |
359 | u32 padding32[7]; /* room for future expansion */ | |
22bd0358 | 360 | u16 virtual_processor_id; |
705699a1 | 361 | u16 posted_intr_nv; |
22bd0358 NHE |
362 | u16 guest_es_selector; |
363 | u16 guest_cs_selector; | |
364 | u16 guest_ss_selector; | |
365 | u16 guest_ds_selector; | |
366 | u16 guest_fs_selector; | |
367 | u16 guest_gs_selector; | |
368 | u16 guest_ldtr_selector; | |
369 | u16 guest_tr_selector; | |
608406e2 | 370 | u16 guest_intr_status; |
22bd0358 NHE |
371 | u16 host_es_selector; |
372 | u16 host_cs_selector; | |
373 | u16 host_ss_selector; | |
374 | u16 host_ds_selector; | |
375 | u16 host_fs_selector; | |
376 | u16 host_gs_selector; | |
377 | u16 host_tr_selector; | |
a9d30f33 NHE |
378 | }; |
379 | ||
380 | /* | |
381 | * VMCS12_REVISION is an arbitrary id that should be changed if the content or | |
382 | * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and | |
383 | * VMPTRLD verifies that the VMCS region that L1 is loading contains this id. | |
384 | */ | |
385 | #define VMCS12_REVISION 0x11e57ed0 | |
386 | ||
387 | /* | |
388 | * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region | |
389 | * and any VMCS region. Although only sizeof(struct vmcs12) are used by the | |
390 | * current implementation, 4K are reserved to avoid future complications. | |
391 | */ | |
392 | #define VMCS12_SIZE 0x1000 | |
393 | ||
ff2f6fe9 NHE |
394 | /* Used to remember the last vmcs02 used for some recently used vmcs12s */ |
395 | struct vmcs02_list { | |
396 | struct list_head list; | |
397 | gpa_t vmptr; | |
398 | struct loaded_vmcs vmcs02; | |
399 | }; | |
400 | ||
ec378aee NHE |
401 | /* |
402 | * The nested_vmx structure is part of vcpu_vmx, and holds information we need | |
403 | * for correct emulation of VMX (i.e., nested VMX) on this vcpu. | |
404 | */ | |
405 | struct nested_vmx { | |
406 | /* Has the level1 guest done vmxon? */ | |
407 | bool vmxon; | |
3573e22c | 408 | gpa_t vmxon_ptr; |
a9d30f33 NHE |
409 | |
410 | /* The guest-physical address of the current VMCS L1 keeps for L2 */ | |
411 | gpa_t current_vmptr; | |
412 | /* The host-usable pointer to the above */ | |
413 | struct page *current_vmcs12_page; | |
414 | struct vmcs12 *current_vmcs12; | |
4f2777bc DM |
415 | /* |
416 | * Cache of the guest's VMCS, existing outside of guest memory. | |
417 | * Loaded from guest memory during VMPTRLD. Flushed to guest | |
418 | * memory during VMXOFF, VMCLEAR, VMPTRLD. | |
419 | */ | |
420 | struct vmcs12 *cached_vmcs12; | |
012f83cb AG |
421 | /* |
422 | * Indicates if the shadow vmcs must be updated with the | |
423 | * data hold by vmcs12 | |
424 | */ | |
425 | bool sync_shadow_vmcs; | |
ff2f6fe9 NHE |
426 | |
427 | /* vmcs02_list cache of VMCSs recently used to run L2 guests */ | |
428 | struct list_head vmcs02_pool; | |
429 | int vmcs02_num; | |
dccbfcf5 | 430 | bool change_vmcs01_virtual_x2apic_mode; |
644d711a NHE |
431 | /* L2 must run next, and mustn't decide to exit to L1. */ |
432 | bool nested_run_pending; | |
fe3ef05c NHE |
433 | /* |
434 | * Guest pages referred to in vmcs02 with host-physical pointers, so | |
435 | * we must keep them pinned while L2 runs. | |
436 | */ | |
437 | struct page *apic_access_page; | |
a7c0b07d | 438 | struct page *virtual_apic_page; |
705699a1 WV |
439 | struct page *pi_desc_page; |
440 | struct pi_desc *pi_desc; | |
441 | bool pi_pending; | |
442 | u16 posted_intr_nv; | |
f4124500 | 443 | |
d048c098 RK |
444 | unsigned long *msr_bitmap; |
445 | ||
f4124500 JK |
446 | struct hrtimer preemption_timer; |
447 | bool preemption_timer_expired; | |
2996fca0 JK |
448 | |
449 | /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */ | |
450 | u64 vmcs01_debugctl; | |
b9c237bb | 451 | |
5c614b35 WL |
452 | u16 vpid02; |
453 | u16 last_vpid; | |
454 | ||
0115f9cb DM |
455 | /* |
456 | * We only store the "true" versions of the VMX capability MSRs. We | |
457 | * generate the "non-true" versions by setting the must-be-1 bits | |
458 | * according to the SDM. | |
459 | */ | |
b9c237bb WV |
460 | u32 nested_vmx_procbased_ctls_low; |
461 | u32 nested_vmx_procbased_ctls_high; | |
b9c237bb WV |
462 | u32 nested_vmx_secondary_ctls_low; |
463 | u32 nested_vmx_secondary_ctls_high; | |
464 | u32 nested_vmx_pinbased_ctls_low; | |
465 | u32 nested_vmx_pinbased_ctls_high; | |
466 | u32 nested_vmx_exit_ctls_low; | |
467 | u32 nested_vmx_exit_ctls_high; | |
b9c237bb WV |
468 | u32 nested_vmx_entry_ctls_low; |
469 | u32 nested_vmx_entry_ctls_high; | |
b9c237bb WV |
470 | u32 nested_vmx_misc_low; |
471 | u32 nested_vmx_misc_high; | |
472 | u32 nested_vmx_ept_caps; | |
99b83ac8 | 473 | u32 nested_vmx_vpid_caps; |
62cc6b9d DM |
474 | u64 nested_vmx_basic; |
475 | u64 nested_vmx_cr0_fixed0; | |
476 | u64 nested_vmx_cr0_fixed1; | |
477 | u64 nested_vmx_cr4_fixed0; | |
478 | u64 nested_vmx_cr4_fixed1; | |
479 | u64 nested_vmx_vmcs_enum; | |
ec378aee NHE |
480 | }; |
481 | ||
01e439be | 482 | #define POSTED_INTR_ON 0 |
ebbfc765 FW |
483 | #define POSTED_INTR_SN 1 |
484 | ||
01e439be YZ |
485 | /* Posted-Interrupt Descriptor */ |
486 | struct pi_desc { | |
487 | u32 pir[8]; /* Posted interrupt requested */ | |
6ef1522f FW |
488 | union { |
489 | struct { | |
490 | /* bit 256 - Outstanding Notification */ | |
491 | u16 on : 1, | |
492 | /* bit 257 - Suppress Notification */ | |
493 | sn : 1, | |
494 | /* bit 271:258 - Reserved */ | |
495 | rsvd_1 : 14; | |
496 | /* bit 279:272 - Notification Vector */ | |
497 | u8 nv; | |
498 | /* bit 287:280 - Reserved */ | |
499 | u8 rsvd_2; | |
500 | /* bit 319:288 - Notification Destination */ | |
501 | u32 ndst; | |
502 | }; | |
503 | u64 control; | |
504 | }; | |
505 | u32 rsvd[6]; | |
01e439be YZ |
506 | } __aligned(64); |
507 | ||
a20ed54d YZ |
508 | static bool pi_test_and_set_on(struct pi_desc *pi_desc) |
509 | { | |
510 | return test_and_set_bit(POSTED_INTR_ON, | |
511 | (unsigned long *)&pi_desc->control); | |
512 | } | |
513 | ||
514 | static bool pi_test_and_clear_on(struct pi_desc *pi_desc) | |
515 | { | |
516 | return test_and_clear_bit(POSTED_INTR_ON, | |
517 | (unsigned long *)&pi_desc->control); | |
518 | } | |
519 | ||
520 | static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc) | |
521 | { | |
522 | return test_and_set_bit(vector, (unsigned long *)pi_desc->pir); | |
523 | } | |
524 | ||
ebbfc765 FW |
525 | static inline void pi_clear_sn(struct pi_desc *pi_desc) |
526 | { | |
527 | return clear_bit(POSTED_INTR_SN, | |
528 | (unsigned long *)&pi_desc->control); | |
529 | } | |
530 | ||
531 | static inline void pi_set_sn(struct pi_desc *pi_desc) | |
532 | { | |
533 | return set_bit(POSTED_INTR_SN, | |
534 | (unsigned long *)&pi_desc->control); | |
535 | } | |
536 | ||
ad361091 PB |
537 | static inline void pi_clear_on(struct pi_desc *pi_desc) |
538 | { | |
539 | clear_bit(POSTED_INTR_ON, | |
540 | (unsigned long *)&pi_desc->control); | |
541 | } | |
542 | ||
ebbfc765 FW |
543 | static inline int pi_test_on(struct pi_desc *pi_desc) |
544 | { | |
545 | return test_bit(POSTED_INTR_ON, | |
546 | (unsigned long *)&pi_desc->control); | |
547 | } | |
548 | ||
549 | static inline int pi_test_sn(struct pi_desc *pi_desc) | |
550 | { | |
551 | return test_bit(POSTED_INTR_SN, | |
552 | (unsigned long *)&pi_desc->control); | |
553 | } | |
554 | ||
a2fa3e9f | 555 | struct vcpu_vmx { |
fb3f0f51 | 556 | struct kvm_vcpu vcpu; |
313dbd49 | 557 | unsigned long host_rsp; |
29bd8a78 | 558 | u8 fail; |
9d58b931 | 559 | bool nmi_known_unmasked; |
51aa01d1 | 560 | u32 exit_intr_info; |
1155f76a | 561 | u32 idt_vectoring_info; |
6de12732 | 562 | ulong rflags; |
26bb0981 | 563 | struct shared_msr_entry *guest_msrs; |
a2fa3e9f GH |
564 | int nmsrs; |
565 | int save_nmsrs; | |
a547c6db | 566 | unsigned long host_idt_base; |
a2fa3e9f | 567 | #ifdef CONFIG_X86_64 |
44ea2b17 AK |
568 | u64 msr_host_kernel_gs_base; |
569 | u64 msr_guest_kernel_gs_base; | |
a2fa3e9f | 570 | #endif |
2961e876 GN |
571 | u32 vm_entry_controls_shadow; |
572 | u32 vm_exit_controls_shadow; | |
d462b819 NHE |
573 | /* |
574 | * loaded_vmcs points to the VMCS currently used in this vcpu. For a | |
575 | * non-nested (L1) guest, it always points to vmcs01. For a nested | |
576 | * guest (L2), it points to a different VMCS. | |
577 | */ | |
578 | struct loaded_vmcs vmcs01; | |
579 | struct loaded_vmcs *loaded_vmcs; | |
580 | bool __launched; /* temporary, used in vmx_vcpu_run */ | |
61d2ef2c AK |
581 | struct msr_autoload { |
582 | unsigned nr; | |
583 | struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS]; | |
584 | struct vmx_msr_entry host[NR_AUTOLOAD_MSRS]; | |
585 | } msr_autoload; | |
a2fa3e9f GH |
586 | struct { |
587 | int loaded; | |
588 | u16 fs_sel, gs_sel, ldt_sel; | |
b2da15ac AK |
589 | #ifdef CONFIG_X86_64 |
590 | u16 ds_sel, es_sel; | |
591 | #endif | |
152d3f2f LV |
592 | int gs_ldt_reload_needed; |
593 | int fs_reload_needed; | |
da8999d3 | 594 | u64 msr_host_bndcfgs; |
d974baa3 | 595 | unsigned long vmcs_host_cr4; /* May not match real cr4 */ |
d77c26fc | 596 | } host_state; |
9c8cba37 | 597 | struct { |
7ffd92c5 | 598 | int vm86_active; |
78ac8b47 | 599 | ulong save_rflags; |
f5f7b2fe AK |
600 | struct kvm_segment segs[8]; |
601 | } rmode; | |
602 | struct { | |
603 | u32 bitmask; /* 4 bits per segment (1 bit per field) */ | |
7ffd92c5 AK |
604 | struct kvm_save_segment { |
605 | u16 selector; | |
606 | unsigned long base; | |
607 | u32 limit; | |
608 | u32 ar; | |
f5f7b2fe | 609 | } seg[8]; |
2fb92db1 | 610 | } segment_cache; |
2384d2b3 | 611 | int vpid; |
04fa4d32 | 612 | bool emulation_required; |
3b86cd99 JK |
613 | |
614 | /* Support for vnmi-less CPUs */ | |
615 | int soft_vnmi_blocked; | |
616 | ktime_t entry_time; | |
617 | s64 vnmi_blocked_time; | |
a0861c02 | 618 | u32 exit_reason; |
4e47c7a6 | 619 | |
01e439be YZ |
620 | /* Posted interrupt descriptor */ |
621 | struct pi_desc pi_desc; | |
622 | ||
ec378aee NHE |
623 | /* Support for a guest hypervisor (nested VMX) */ |
624 | struct nested_vmx nested; | |
a7653ecd RK |
625 | |
626 | /* Dynamic PLE window. */ | |
627 | int ple_window; | |
628 | bool ple_window_dirty; | |
843e4330 KH |
629 | |
630 | /* Support for PML */ | |
631 | #define PML_ENTITY_NUM 512 | |
632 | struct page *pml_pg; | |
2680d6da | 633 | |
64672c95 YJ |
634 | /* apic deadline value in host tsc */ |
635 | u64 hv_deadline_tsc; | |
636 | ||
2680d6da | 637 | u64 current_tsc_ratio; |
1be0e61c XG |
638 | |
639 | bool guest_pkru_valid; | |
640 | u32 guest_pkru; | |
641 | u32 host_pkru; | |
3b84080b | 642 | |
37e4c997 HZ |
643 | /* |
644 | * Only bits masked by msr_ia32_feature_control_valid_bits can be set in | |
645 | * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included | |
646 | * in msr_ia32_feature_control_valid_bits. | |
647 | */ | |
3b84080b | 648 | u64 msr_ia32_feature_control; |
37e4c997 | 649 | u64 msr_ia32_feature_control_valid_bits; |
a2fa3e9f GH |
650 | }; |
651 | ||
2fb92db1 AK |
652 | enum segment_cache_field { |
653 | SEG_FIELD_SEL = 0, | |
654 | SEG_FIELD_BASE = 1, | |
655 | SEG_FIELD_LIMIT = 2, | |
656 | SEG_FIELD_AR = 3, | |
657 | ||
658 | SEG_FIELD_NR = 4 | |
659 | }; | |
660 | ||
a2fa3e9f GH |
661 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) |
662 | { | |
fb3f0f51 | 663 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
664 | } |
665 | ||
efc64404 FW |
666 | static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu) |
667 | { | |
668 | return &(to_vmx(vcpu)->pi_desc); | |
669 | } | |
670 | ||
22bd0358 NHE |
671 | #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x) |
672 | #define FIELD(number, name) [number] = VMCS12_OFFSET(name) | |
673 | #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \ | |
674 | [number##_HIGH] = VMCS12_OFFSET(name)+4 | |
675 | ||
4607c2d7 | 676 | |
fe2b201b | 677 | static unsigned long shadow_read_only_fields[] = { |
4607c2d7 AG |
678 | /* |
679 | * We do NOT shadow fields that are modified when L0 | |
680 | * traps and emulates any vmx instruction (e.g. VMPTRLD, | |
681 | * VMXON...) executed by L1. | |
682 | * For example, VM_INSTRUCTION_ERROR is read | |
683 | * by L1 if a vmx instruction fails (part of the error path). | |
684 | * Note the code assumes this logic. If for some reason | |
685 | * we start shadowing these fields then we need to | |
686 | * force a shadow sync when L0 emulates vmx instructions | |
687 | * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified | |
688 | * by nested_vmx_failValid) | |
689 | */ | |
690 | VM_EXIT_REASON, | |
691 | VM_EXIT_INTR_INFO, | |
692 | VM_EXIT_INSTRUCTION_LEN, | |
693 | IDT_VECTORING_INFO_FIELD, | |
694 | IDT_VECTORING_ERROR_CODE, | |
695 | VM_EXIT_INTR_ERROR_CODE, | |
696 | EXIT_QUALIFICATION, | |
697 | GUEST_LINEAR_ADDRESS, | |
698 | GUEST_PHYSICAL_ADDRESS | |
699 | }; | |
fe2b201b | 700 | static int max_shadow_read_only_fields = |
4607c2d7 AG |
701 | ARRAY_SIZE(shadow_read_only_fields); |
702 | ||
fe2b201b | 703 | static unsigned long shadow_read_write_fields[] = { |
a7c0b07d | 704 | TPR_THRESHOLD, |
4607c2d7 AG |
705 | GUEST_RIP, |
706 | GUEST_RSP, | |
707 | GUEST_CR0, | |
708 | GUEST_CR3, | |
709 | GUEST_CR4, | |
710 | GUEST_INTERRUPTIBILITY_INFO, | |
711 | GUEST_RFLAGS, | |
712 | GUEST_CS_SELECTOR, | |
713 | GUEST_CS_AR_BYTES, | |
714 | GUEST_CS_LIMIT, | |
715 | GUEST_CS_BASE, | |
716 | GUEST_ES_BASE, | |
36be0b9d | 717 | GUEST_BNDCFGS, |
4607c2d7 AG |
718 | CR0_GUEST_HOST_MASK, |
719 | CR0_READ_SHADOW, | |
720 | CR4_READ_SHADOW, | |
721 | TSC_OFFSET, | |
722 | EXCEPTION_BITMAP, | |
723 | CPU_BASED_VM_EXEC_CONTROL, | |
724 | VM_ENTRY_EXCEPTION_ERROR_CODE, | |
725 | VM_ENTRY_INTR_INFO_FIELD, | |
726 | VM_ENTRY_INSTRUCTION_LEN, | |
727 | VM_ENTRY_EXCEPTION_ERROR_CODE, | |
728 | HOST_FS_BASE, | |
729 | HOST_GS_BASE, | |
730 | HOST_FS_SELECTOR, | |
731 | HOST_GS_SELECTOR | |
732 | }; | |
fe2b201b | 733 | static int max_shadow_read_write_fields = |
4607c2d7 AG |
734 | ARRAY_SIZE(shadow_read_write_fields); |
735 | ||
772e0318 | 736 | static const unsigned short vmcs_field_to_offset_table[] = { |
22bd0358 | 737 | FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id), |
705699a1 | 738 | FIELD(POSTED_INTR_NV, posted_intr_nv), |
22bd0358 NHE |
739 | FIELD(GUEST_ES_SELECTOR, guest_es_selector), |
740 | FIELD(GUEST_CS_SELECTOR, guest_cs_selector), | |
741 | FIELD(GUEST_SS_SELECTOR, guest_ss_selector), | |
742 | FIELD(GUEST_DS_SELECTOR, guest_ds_selector), | |
743 | FIELD(GUEST_FS_SELECTOR, guest_fs_selector), | |
744 | FIELD(GUEST_GS_SELECTOR, guest_gs_selector), | |
745 | FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector), | |
746 | FIELD(GUEST_TR_SELECTOR, guest_tr_selector), | |
608406e2 | 747 | FIELD(GUEST_INTR_STATUS, guest_intr_status), |
22bd0358 NHE |
748 | FIELD(HOST_ES_SELECTOR, host_es_selector), |
749 | FIELD(HOST_CS_SELECTOR, host_cs_selector), | |
750 | FIELD(HOST_SS_SELECTOR, host_ss_selector), | |
751 | FIELD(HOST_DS_SELECTOR, host_ds_selector), | |
752 | FIELD(HOST_FS_SELECTOR, host_fs_selector), | |
753 | FIELD(HOST_GS_SELECTOR, host_gs_selector), | |
754 | FIELD(HOST_TR_SELECTOR, host_tr_selector), | |
755 | FIELD64(IO_BITMAP_A, io_bitmap_a), | |
756 | FIELD64(IO_BITMAP_B, io_bitmap_b), | |
757 | FIELD64(MSR_BITMAP, msr_bitmap), | |
758 | FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr), | |
759 | FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr), | |
760 | FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr), | |
761 | FIELD64(TSC_OFFSET, tsc_offset), | |
762 | FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr), | |
763 | FIELD64(APIC_ACCESS_ADDR, apic_access_addr), | |
705699a1 | 764 | FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr), |
22bd0358 | 765 | FIELD64(EPT_POINTER, ept_pointer), |
608406e2 WV |
766 | FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0), |
767 | FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1), | |
768 | FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2), | |
769 | FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3), | |
81dc01f7 | 770 | FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap), |
22bd0358 NHE |
771 | FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address), |
772 | FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer), | |
773 | FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl), | |
774 | FIELD64(GUEST_IA32_PAT, guest_ia32_pat), | |
775 | FIELD64(GUEST_IA32_EFER, guest_ia32_efer), | |
776 | FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl), | |
777 | FIELD64(GUEST_PDPTR0, guest_pdptr0), | |
778 | FIELD64(GUEST_PDPTR1, guest_pdptr1), | |
779 | FIELD64(GUEST_PDPTR2, guest_pdptr2), | |
780 | FIELD64(GUEST_PDPTR3, guest_pdptr3), | |
36be0b9d | 781 | FIELD64(GUEST_BNDCFGS, guest_bndcfgs), |
22bd0358 NHE |
782 | FIELD64(HOST_IA32_PAT, host_ia32_pat), |
783 | FIELD64(HOST_IA32_EFER, host_ia32_efer), | |
784 | FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl), | |
785 | FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control), | |
786 | FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control), | |
787 | FIELD(EXCEPTION_BITMAP, exception_bitmap), | |
788 | FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask), | |
789 | FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match), | |
790 | FIELD(CR3_TARGET_COUNT, cr3_target_count), | |
791 | FIELD(VM_EXIT_CONTROLS, vm_exit_controls), | |
792 | FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count), | |
793 | FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count), | |
794 | FIELD(VM_ENTRY_CONTROLS, vm_entry_controls), | |
795 | FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count), | |
796 | FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field), | |
797 | FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code), | |
798 | FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len), | |
799 | FIELD(TPR_THRESHOLD, tpr_threshold), | |
800 | FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control), | |
801 | FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error), | |
802 | FIELD(VM_EXIT_REASON, vm_exit_reason), | |
803 | FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info), | |
804 | FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code), | |
805 | FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field), | |
806 | FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code), | |
807 | FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len), | |
808 | FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info), | |
809 | FIELD(GUEST_ES_LIMIT, guest_es_limit), | |
810 | FIELD(GUEST_CS_LIMIT, guest_cs_limit), | |
811 | FIELD(GUEST_SS_LIMIT, guest_ss_limit), | |
812 | FIELD(GUEST_DS_LIMIT, guest_ds_limit), | |
813 | FIELD(GUEST_FS_LIMIT, guest_fs_limit), | |
814 | FIELD(GUEST_GS_LIMIT, guest_gs_limit), | |
815 | FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit), | |
816 | FIELD(GUEST_TR_LIMIT, guest_tr_limit), | |
817 | FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit), | |
818 | FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit), | |
819 | FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes), | |
820 | FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes), | |
821 | FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes), | |
822 | FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes), | |
823 | FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes), | |
824 | FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes), | |
825 | FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes), | |
826 | FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes), | |
827 | FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info), | |
828 | FIELD(GUEST_ACTIVITY_STATE, guest_activity_state), | |
829 | FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs), | |
830 | FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs), | |
0238ea91 | 831 | FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value), |
22bd0358 NHE |
832 | FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask), |
833 | FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask), | |
834 | FIELD(CR0_READ_SHADOW, cr0_read_shadow), | |
835 | FIELD(CR4_READ_SHADOW, cr4_read_shadow), | |
836 | FIELD(CR3_TARGET_VALUE0, cr3_target_value0), | |
837 | FIELD(CR3_TARGET_VALUE1, cr3_target_value1), | |
838 | FIELD(CR3_TARGET_VALUE2, cr3_target_value2), | |
839 | FIELD(CR3_TARGET_VALUE3, cr3_target_value3), | |
840 | FIELD(EXIT_QUALIFICATION, exit_qualification), | |
841 | FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address), | |
842 | FIELD(GUEST_CR0, guest_cr0), | |
843 | FIELD(GUEST_CR3, guest_cr3), | |
844 | FIELD(GUEST_CR4, guest_cr4), | |
845 | FIELD(GUEST_ES_BASE, guest_es_base), | |
846 | FIELD(GUEST_CS_BASE, guest_cs_base), | |
847 | FIELD(GUEST_SS_BASE, guest_ss_base), | |
848 | FIELD(GUEST_DS_BASE, guest_ds_base), | |
849 | FIELD(GUEST_FS_BASE, guest_fs_base), | |
850 | FIELD(GUEST_GS_BASE, guest_gs_base), | |
851 | FIELD(GUEST_LDTR_BASE, guest_ldtr_base), | |
852 | FIELD(GUEST_TR_BASE, guest_tr_base), | |
853 | FIELD(GUEST_GDTR_BASE, guest_gdtr_base), | |
854 | FIELD(GUEST_IDTR_BASE, guest_idtr_base), | |
855 | FIELD(GUEST_DR7, guest_dr7), | |
856 | FIELD(GUEST_RSP, guest_rsp), | |
857 | FIELD(GUEST_RIP, guest_rip), | |
858 | FIELD(GUEST_RFLAGS, guest_rflags), | |
859 | FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions), | |
860 | FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp), | |
861 | FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip), | |
862 | FIELD(HOST_CR0, host_cr0), | |
863 | FIELD(HOST_CR3, host_cr3), | |
864 | FIELD(HOST_CR4, host_cr4), | |
865 | FIELD(HOST_FS_BASE, host_fs_base), | |
866 | FIELD(HOST_GS_BASE, host_gs_base), | |
867 | FIELD(HOST_TR_BASE, host_tr_base), | |
868 | FIELD(HOST_GDTR_BASE, host_gdtr_base), | |
869 | FIELD(HOST_IDTR_BASE, host_idtr_base), | |
870 | FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp), | |
871 | FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip), | |
872 | FIELD(HOST_RSP, host_rsp), | |
873 | FIELD(HOST_RIP, host_rip), | |
874 | }; | |
22bd0358 NHE |
875 | |
876 | static inline short vmcs_field_to_offset(unsigned long field) | |
877 | { | |
a2ae9df7 PB |
878 | BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX); |
879 | ||
880 | if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) || | |
881 | vmcs_field_to_offset_table[field] == 0) | |
882 | return -ENOENT; | |
883 | ||
22bd0358 NHE |
884 | return vmcs_field_to_offset_table[field]; |
885 | } | |
886 | ||
a9d30f33 NHE |
887 | static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu) |
888 | { | |
4f2777bc | 889 | return to_vmx(vcpu)->nested.cached_vmcs12; |
a9d30f33 NHE |
890 | } |
891 | ||
892 | static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr) | |
893 | { | |
54bf36aa | 894 | struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT); |
32cad84f | 895 | if (is_error_page(page)) |
a9d30f33 | 896 | return NULL; |
32cad84f | 897 | |
a9d30f33 NHE |
898 | return page; |
899 | } | |
900 | ||
901 | static void nested_release_page(struct page *page) | |
902 | { | |
903 | kvm_release_page_dirty(page); | |
904 | } | |
905 | ||
906 | static void nested_release_page_clean(struct page *page) | |
907 | { | |
908 | kvm_release_page_clean(page); | |
909 | } | |
910 | ||
bfd0a56b | 911 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu); |
4e1096d2 | 912 | static u64 construct_eptp(unsigned long root_hpa); |
4610c9cc DX |
913 | static void kvm_cpu_vmxon(u64 addr); |
914 | static void kvm_cpu_vmxoff(void); | |
f53cd63c | 915 | static bool vmx_xsaves_supported(void); |
776e58ea | 916 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr); |
b246dd5d OW |
917 | static void vmx_set_segment(struct kvm_vcpu *vcpu, |
918 | struct kvm_segment *var, int seg); | |
919 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
920 | struct kvm_segment *var, int seg); | |
d99e4152 GN |
921 | static bool guest_state_valid(struct kvm_vcpu *vcpu); |
922 | static u32 vmx_segment_access_rights(struct kvm_segment *var); | |
c3114420 | 923 | static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx); |
16f5b903 | 924 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx); |
a255d479 | 925 | static int alloc_identity_pagetable(struct kvm *kvm); |
75880a01 | 926 | |
6aa8b732 AK |
927 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
928 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
d462b819 NHE |
929 | /* |
930 | * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed | |
931 | * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. | |
932 | */ | |
933 | static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); | |
3444d7da | 934 | static DEFINE_PER_CPU(struct desc_ptr, host_gdt); |
6aa8b732 | 935 | |
bf9f6ac8 FW |
936 | /* |
937 | * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we | |
938 | * can find which vCPU should be waken up. | |
939 | */ | |
940 | static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); | |
941 | static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); | |
942 | ||
23611332 RK |
943 | enum { |
944 | VMX_IO_BITMAP_A, | |
945 | VMX_IO_BITMAP_B, | |
946 | VMX_MSR_BITMAP_LEGACY, | |
947 | VMX_MSR_BITMAP_LONGMODE, | |
948 | VMX_MSR_BITMAP_LEGACY_X2APIC_APICV, | |
949 | VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV, | |
950 | VMX_MSR_BITMAP_LEGACY_X2APIC, | |
951 | VMX_MSR_BITMAP_LONGMODE_X2APIC, | |
952 | VMX_VMREAD_BITMAP, | |
953 | VMX_VMWRITE_BITMAP, | |
954 | VMX_BITMAP_NR | |
955 | }; | |
956 | ||
957 | static unsigned long *vmx_bitmap[VMX_BITMAP_NR]; | |
958 | ||
959 | #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A]) | |
960 | #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B]) | |
961 | #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY]) | |
962 | #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE]) | |
963 | #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV]) | |
964 | #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV]) | |
965 | #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC]) | |
966 | #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC]) | |
967 | #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP]) | |
968 | #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP]) | |
fdef3ad1 | 969 | |
110312c8 | 970 | static bool cpu_has_load_ia32_efer; |
8bf00a52 | 971 | static bool cpu_has_load_perf_global_ctrl; |
110312c8 | 972 | |
2384d2b3 SY |
973 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
974 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
975 | ||
1c3d14fe | 976 | static struct vmcs_config { |
6aa8b732 AK |
977 | int size; |
978 | int order; | |
9ac7e3e8 | 979 | u32 basic_cap; |
6aa8b732 | 980 | u32 revision_id; |
1c3d14fe YS |
981 | u32 pin_based_exec_ctrl; |
982 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 983 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
984 | u32 vmexit_ctrl; |
985 | u32 vmentry_ctrl; | |
986 | } vmcs_config; | |
6aa8b732 | 987 | |
efff9e53 | 988 | static struct vmx_capability { |
d56f546d SY |
989 | u32 ept; |
990 | u32 vpid; | |
991 | } vmx_capability; | |
992 | ||
6aa8b732 AK |
993 | #define VMX_SEGMENT_FIELD(seg) \ |
994 | [VCPU_SREG_##seg] = { \ | |
995 | .selector = GUEST_##seg##_SELECTOR, \ | |
996 | .base = GUEST_##seg##_BASE, \ | |
997 | .limit = GUEST_##seg##_LIMIT, \ | |
998 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
999 | } | |
1000 | ||
772e0318 | 1001 | static const struct kvm_vmx_segment_field { |
6aa8b732 AK |
1002 | unsigned selector; |
1003 | unsigned base; | |
1004 | unsigned limit; | |
1005 | unsigned ar_bytes; | |
1006 | } kvm_vmx_segment_fields[] = { | |
1007 | VMX_SEGMENT_FIELD(CS), | |
1008 | VMX_SEGMENT_FIELD(DS), | |
1009 | VMX_SEGMENT_FIELD(ES), | |
1010 | VMX_SEGMENT_FIELD(FS), | |
1011 | VMX_SEGMENT_FIELD(GS), | |
1012 | VMX_SEGMENT_FIELD(SS), | |
1013 | VMX_SEGMENT_FIELD(TR), | |
1014 | VMX_SEGMENT_FIELD(LDTR), | |
1015 | }; | |
1016 | ||
26bb0981 AK |
1017 | static u64 host_efer; |
1018 | ||
6de4f3ad AK |
1019 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu); |
1020 | ||
4d56c8a7 | 1021 | /* |
8c06585d | 1022 | * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it |
4d56c8a7 AK |
1023 | * away by decrementing the array size. |
1024 | */ | |
6aa8b732 | 1025 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 1026 | #ifdef CONFIG_X86_64 |
44ea2b17 | 1027 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, |
6aa8b732 | 1028 | #endif |
8c06585d | 1029 | MSR_EFER, MSR_TSC_AUX, MSR_STAR, |
6aa8b732 | 1030 | }; |
6aa8b732 | 1031 | |
5bb16016 | 1032 | static inline bool is_exception_n(u32 intr_info, u8 vector) |
6aa8b732 AK |
1033 | { |
1034 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
1035 | INTR_INFO_VALID_MASK)) == | |
5bb16016 JK |
1036 | (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK); |
1037 | } | |
1038 | ||
6f05485d JK |
1039 | static inline bool is_debug(u32 intr_info) |
1040 | { | |
1041 | return is_exception_n(intr_info, DB_VECTOR); | |
1042 | } | |
1043 | ||
1044 | static inline bool is_breakpoint(u32 intr_info) | |
1045 | { | |
1046 | return is_exception_n(intr_info, BP_VECTOR); | |
1047 | } | |
1048 | ||
5bb16016 JK |
1049 | static inline bool is_page_fault(u32 intr_info) |
1050 | { | |
1051 | return is_exception_n(intr_info, PF_VECTOR); | |
6aa8b732 AK |
1052 | } |
1053 | ||
31299944 | 1054 | static inline bool is_no_device(u32 intr_info) |
2ab455cc | 1055 | { |
5bb16016 | 1056 | return is_exception_n(intr_info, NM_VECTOR); |
2ab455cc AL |
1057 | } |
1058 | ||
31299944 | 1059 | static inline bool is_invalid_opcode(u32 intr_info) |
7aa81cc0 | 1060 | { |
5bb16016 | 1061 | return is_exception_n(intr_info, UD_VECTOR); |
7aa81cc0 AL |
1062 | } |
1063 | ||
31299944 | 1064 | static inline bool is_external_interrupt(u32 intr_info) |
6aa8b732 AK |
1065 | { |
1066 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
1067 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
1068 | } | |
1069 | ||
31299944 | 1070 | static inline bool is_machine_check(u32 intr_info) |
a0861c02 AK |
1071 | { |
1072 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
1073 | INTR_INFO_VALID_MASK)) == | |
1074 | (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK); | |
1075 | } | |
1076 | ||
31299944 | 1077 | static inline bool cpu_has_vmx_msr_bitmap(void) |
25c5f225 | 1078 | { |
04547156 | 1079 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; |
25c5f225 SY |
1080 | } |
1081 | ||
31299944 | 1082 | static inline bool cpu_has_vmx_tpr_shadow(void) |
6e5d865c | 1083 | { |
04547156 | 1084 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; |
6e5d865c YS |
1085 | } |
1086 | ||
35754c98 | 1087 | static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu) |
6e5d865c | 1088 | { |
35754c98 | 1089 | return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu); |
6e5d865c YS |
1090 | } |
1091 | ||
31299944 | 1092 | static inline bool cpu_has_secondary_exec_ctrls(void) |
f78e0e2e | 1093 | { |
04547156 SY |
1094 | return vmcs_config.cpu_based_exec_ctrl & |
1095 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
f78e0e2e SY |
1096 | } |
1097 | ||
774ead3a | 1098 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 1099 | { |
04547156 SY |
1100 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1101 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
1102 | } | |
1103 | ||
8d14695f YZ |
1104 | static inline bool cpu_has_vmx_virtualize_x2apic_mode(void) |
1105 | { | |
1106 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1107 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
1108 | } | |
1109 | ||
83d4c286 YZ |
1110 | static inline bool cpu_has_vmx_apic_register_virt(void) |
1111 | { | |
1112 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1113 | SECONDARY_EXEC_APIC_REGISTER_VIRT; | |
1114 | } | |
1115 | ||
c7c9c56c YZ |
1116 | static inline bool cpu_has_vmx_virtual_intr_delivery(void) |
1117 | { | |
1118 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1119 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY; | |
1120 | } | |
1121 | ||
64672c95 YJ |
1122 | /* |
1123 | * Comment's format: document - errata name - stepping - processor name. | |
1124 | * Refer from | |
1125 | * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp | |
1126 | */ | |
1127 | static u32 vmx_preemption_cpu_tfms[] = { | |
1128 | /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ | |
1129 | 0x000206E6, | |
1130 | /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ | |
1131 | /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ | |
1132 | /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
1133 | 0x00020652, | |
1134 | /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
1135 | 0x00020655, | |
1136 | /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ | |
1137 | /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ | |
1138 | /* | |
1139 | * 320767.pdf - AAP86 - B1 - | |
1140 | * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile | |
1141 | */ | |
1142 | 0x000106E5, | |
1143 | /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ | |
1144 | 0x000106A0, | |
1145 | /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ | |
1146 | 0x000106A1, | |
1147 | /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ | |
1148 | 0x000106A4, | |
1149 | /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ | |
1150 | /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ | |
1151 | /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ | |
1152 | 0x000106A5, | |
1153 | }; | |
1154 | ||
1155 | static inline bool cpu_has_broken_vmx_preemption_timer(void) | |
1156 | { | |
1157 | u32 eax = cpuid_eax(0x00000001), i; | |
1158 | ||
1159 | /* Clear the reserved bits */ | |
1160 | eax &= ~(0x3U << 14 | 0xfU << 28); | |
03f6a22a | 1161 | for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) |
64672c95 YJ |
1162 | if (eax == vmx_preemption_cpu_tfms[i]) |
1163 | return true; | |
1164 | ||
1165 | return false; | |
1166 | } | |
1167 | ||
1168 | static inline bool cpu_has_vmx_preemption_timer(void) | |
1169 | { | |
64672c95 YJ |
1170 | return vmcs_config.pin_based_exec_ctrl & |
1171 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1172 | } | |
1173 | ||
01e439be YZ |
1174 | static inline bool cpu_has_vmx_posted_intr(void) |
1175 | { | |
d6a858d1 PB |
1176 | return IS_ENABLED(CONFIG_X86_LOCAL_APIC) && |
1177 | vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR; | |
01e439be YZ |
1178 | } |
1179 | ||
1180 | static inline bool cpu_has_vmx_apicv(void) | |
1181 | { | |
1182 | return cpu_has_vmx_apic_register_virt() && | |
1183 | cpu_has_vmx_virtual_intr_delivery() && | |
1184 | cpu_has_vmx_posted_intr(); | |
1185 | } | |
1186 | ||
04547156 SY |
1187 | static inline bool cpu_has_vmx_flexpriority(void) |
1188 | { | |
1189 | return cpu_has_vmx_tpr_shadow() && | |
1190 | cpu_has_vmx_virtualize_apic_accesses(); | |
f78e0e2e SY |
1191 | } |
1192 | ||
e799794e MT |
1193 | static inline bool cpu_has_vmx_ept_execute_only(void) |
1194 | { | |
31299944 | 1195 | return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT; |
e799794e MT |
1196 | } |
1197 | ||
e799794e MT |
1198 | static inline bool cpu_has_vmx_ept_2m_page(void) |
1199 | { | |
31299944 | 1200 | return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT; |
e799794e MT |
1201 | } |
1202 | ||
878403b7 SY |
1203 | static inline bool cpu_has_vmx_ept_1g_page(void) |
1204 | { | |
31299944 | 1205 | return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT; |
878403b7 SY |
1206 | } |
1207 | ||
4bc9b982 SY |
1208 | static inline bool cpu_has_vmx_ept_4levels(void) |
1209 | { | |
1210 | return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT; | |
1211 | } | |
1212 | ||
83c3a331 XH |
1213 | static inline bool cpu_has_vmx_ept_ad_bits(void) |
1214 | { | |
1215 | return vmx_capability.ept & VMX_EPT_AD_BIT; | |
1216 | } | |
1217 | ||
31299944 | 1218 | static inline bool cpu_has_vmx_invept_context(void) |
d56f546d | 1219 | { |
31299944 | 1220 | return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT; |
d56f546d SY |
1221 | } |
1222 | ||
31299944 | 1223 | static inline bool cpu_has_vmx_invept_global(void) |
d56f546d | 1224 | { |
31299944 | 1225 | return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; |
d56f546d SY |
1226 | } |
1227 | ||
518c8aee GJ |
1228 | static inline bool cpu_has_vmx_invvpid_single(void) |
1229 | { | |
1230 | return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT; | |
1231 | } | |
1232 | ||
b9d762fa GJ |
1233 | static inline bool cpu_has_vmx_invvpid_global(void) |
1234 | { | |
1235 | return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; | |
1236 | } | |
1237 | ||
31299944 | 1238 | static inline bool cpu_has_vmx_ept(void) |
d56f546d | 1239 | { |
04547156 SY |
1240 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1241 | SECONDARY_EXEC_ENABLE_EPT; | |
d56f546d SY |
1242 | } |
1243 | ||
31299944 | 1244 | static inline bool cpu_has_vmx_unrestricted_guest(void) |
3a624e29 NK |
1245 | { |
1246 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1247 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
1248 | } | |
1249 | ||
31299944 | 1250 | static inline bool cpu_has_vmx_ple(void) |
4b8d54f9 ZE |
1251 | { |
1252 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1253 | SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
1254 | } | |
1255 | ||
9ac7e3e8 JD |
1256 | static inline bool cpu_has_vmx_basic_inout(void) |
1257 | { | |
1258 | return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT); | |
1259 | } | |
1260 | ||
35754c98 | 1261 | static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) |
f78e0e2e | 1262 | { |
35754c98 | 1263 | return flexpriority_enabled && lapic_in_kernel(vcpu); |
f78e0e2e SY |
1264 | } |
1265 | ||
31299944 | 1266 | static inline bool cpu_has_vmx_vpid(void) |
2384d2b3 | 1267 | { |
04547156 SY |
1268 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1269 | SECONDARY_EXEC_ENABLE_VPID; | |
2384d2b3 SY |
1270 | } |
1271 | ||
31299944 | 1272 | static inline bool cpu_has_vmx_rdtscp(void) |
4e47c7a6 SY |
1273 | { |
1274 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1275 | SECONDARY_EXEC_RDTSCP; | |
1276 | } | |
1277 | ||
ad756a16 MJ |
1278 | static inline bool cpu_has_vmx_invpcid(void) |
1279 | { | |
1280 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1281 | SECONDARY_EXEC_ENABLE_INVPCID; | |
1282 | } | |
1283 | ||
31299944 | 1284 | static inline bool cpu_has_virtual_nmis(void) |
f08864b4 SY |
1285 | { |
1286 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; | |
1287 | } | |
1288 | ||
f5f48ee1 SY |
1289 | static inline bool cpu_has_vmx_wbinvd_exit(void) |
1290 | { | |
1291 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1292 | SECONDARY_EXEC_WBINVD_EXITING; | |
1293 | } | |
1294 | ||
abc4fc58 AG |
1295 | static inline bool cpu_has_vmx_shadow_vmcs(void) |
1296 | { | |
1297 | u64 vmx_msr; | |
1298 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
1299 | /* check if the cpu supports writing r/o exit information fields */ | |
1300 | if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) | |
1301 | return false; | |
1302 | ||
1303 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1304 | SECONDARY_EXEC_SHADOW_VMCS; | |
1305 | } | |
1306 | ||
843e4330 KH |
1307 | static inline bool cpu_has_vmx_pml(void) |
1308 | { | |
1309 | return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML; | |
1310 | } | |
1311 | ||
64903d61 HZ |
1312 | static inline bool cpu_has_vmx_tsc_scaling(void) |
1313 | { | |
1314 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1315 | SECONDARY_EXEC_TSC_SCALING; | |
1316 | } | |
1317 | ||
04547156 SY |
1318 | static inline bool report_flexpriority(void) |
1319 | { | |
1320 | return flexpriority_enabled; | |
1321 | } | |
1322 | ||
fe3ef05c NHE |
1323 | static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit) |
1324 | { | |
1325 | return vmcs12->cpu_based_vm_exec_control & bit; | |
1326 | } | |
1327 | ||
1328 | static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit) | |
1329 | { | |
1330 | return (vmcs12->cpu_based_vm_exec_control & | |
1331 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && | |
1332 | (vmcs12->secondary_vm_exec_control & bit); | |
1333 | } | |
1334 | ||
f5c4368f | 1335 | static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12) |
644d711a NHE |
1336 | { |
1337 | return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS; | |
1338 | } | |
1339 | ||
f4124500 JK |
1340 | static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12) |
1341 | { | |
1342 | return vmcs12->pin_based_vm_exec_control & | |
1343 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1344 | } | |
1345 | ||
155a97a3 NHE |
1346 | static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12) |
1347 | { | |
1348 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT); | |
1349 | } | |
1350 | ||
81dc01f7 WL |
1351 | static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12) |
1352 | { | |
1353 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) && | |
1354 | vmx_xsaves_supported(); | |
1355 | } | |
1356 | ||
f2b93280 WV |
1357 | static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12) |
1358 | { | |
1359 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); | |
1360 | } | |
1361 | ||
5c614b35 WL |
1362 | static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12) |
1363 | { | |
1364 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID); | |
1365 | } | |
1366 | ||
82f0dd4b WV |
1367 | static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12) |
1368 | { | |
1369 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT); | |
1370 | } | |
1371 | ||
608406e2 WV |
1372 | static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12) |
1373 | { | |
1374 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
1375 | } | |
1376 | ||
705699a1 WV |
1377 | static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12) |
1378 | { | |
1379 | return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR; | |
1380 | } | |
1381 | ||
644d711a NHE |
1382 | static inline bool is_exception(u32 intr_info) |
1383 | { | |
1384 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
1385 | == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK); | |
1386 | } | |
1387 | ||
533558bc JK |
1388 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
1389 | u32 exit_intr_info, | |
1390 | unsigned long exit_qualification); | |
7c177938 NHE |
1391 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, |
1392 | struct vmcs12 *vmcs12, | |
1393 | u32 reason, unsigned long qualification); | |
1394 | ||
8b9cf98c | 1395 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
1396 | { |
1397 | int i; | |
1398 | ||
a2fa3e9f | 1399 | for (i = 0; i < vmx->nmsrs; ++i) |
26bb0981 | 1400 | if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) |
a75beee6 ED |
1401 | return i; |
1402 | return -1; | |
1403 | } | |
1404 | ||
2384d2b3 SY |
1405 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
1406 | { | |
1407 | struct { | |
1408 | u64 vpid : 16; | |
1409 | u64 rsvd : 48; | |
1410 | u64 gva; | |
1411 | } operand = { vpid, 0, gva }; | |
1412 | ||
4ecac3fd | 1413 | asm volatile (__ex(ASM_VMX_INVVPID) |
2384d2b3 SY |
1414 | /* CF==1 or ZF==1 --> rc = -1 */ |
1415 | "; ja 1f ; ud2 ; 1:" | |
1416 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
1417 | } | |
1418 | ||
1439442c SY |
1419 | static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
1420 | { | |
1421 | struct { | |
1422 | u64 eptp, gpa; | |
1423 | } operand = {eptp, gpa}; | |
1424 | ||
4ecac3fd | 1425 | asm volatile (__ex(ASM_VMX_INVEPT) |
1439442c SY |
1426 | /* CF==1 or ZF==1 --> rc = -1 */ |
1427 | "; ja 1f ; ud2 ; 1:\n" | |
1428 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
1429 | } | |
1430 | ||
26bb0981 | 1431 | static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
1432 | { |
1433 | int i; | |
1434 | ||
8b9cf98c | 1435 | i = __find_msr_index(vmx, msr); |
a75beee6 | 1436 | if (i >= 0) |
a2fa3e9f | 1437 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 1438 | return NULL; |
7725f0ba AK |
1439 | } |
1440 | ||
6aa8b732 AK |
1441 | static void vmcs_clear(struct vmcs *vmcs) |
1442 | { | |
1443 | u64 phys_addr = __pa(vmcs); | |
1444 | u8 error; | |
1445 | ||
4ecac3fd | 1446 | asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
16d8f72f | 1447 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
6aa8b732 AK |
1448 | : "cc", "memory"); |
1449 | if (error) | |
1450 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
1451 | vmcs, phys_addr); | |
1452 | } | |
1453 | ||
d462b819 NHE |
1454 | static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) |
1455 | { | |
1456 | vmcs_clear(loaded_vmcs->vmcs); | |
355f4fb1 JM |
1457 | if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) |
1458 | vmcs_clear(loaded_vmcs->shadow_vmcs); | |
d462b819 NHE |
1459 | loaded_vmcs->cpu = -1; |
1460 | loaded_vmcs->launched = 0; | |
1461 | } | |
1462 | ||
7725b894 DX |
1463 | static void vmcs_load(struct vmcs *vmcs) |
1464 | { | |
1465 | u64 phys_addr = __pa(vmcs); | |
1466 | u8 error; | |
1467 | ||
1468 | asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" | |
16d8f72f | 1469 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
7725b894 DX |
1470 | : "cc", "memory"); |
1471 | if (error) | |
2844d849 | 1472 | printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n", |
7725b894 DX |
1473 | vmcs, phys_addr); |
1474 | } | |
1475 | ||
2965faa5 | 1476 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
1477 | /* |
1478 | * This bitmap is used to indicate whether the vmclear | |
1479 | * operation is enabled on all cpus. All disabled by | |
1480 | * default. | |
1481 | */ | |
1482 | static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE; | |
1483 | ||
1484 | static inline void crash_enable_local_vmclear(int cpu) | |
1485 | { | |
1486 | cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1487 | } | |
1488 | ||
1489 | static inline void crash_disable_local_vmclear(int cpu) | |
1490 | { | |
1491 | cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1492 | } | |
1493 | ||
1494 | static inline int crash_local_vmclear_enabled(int cpu) | |
1495 | { | |
1496 | return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1497 | } | |
1498 | ||
1499 | static void crash_vmclear_local_loaded_vmcss(void) | |
1500 | { | |
1501 | int cpu = raw_smp_processor_id(); | |
1502 | struct loaded_vmcs *v; | |
1503 | ||
1504 | if (!crash_local_vmclear_enabled(cpu)) | |
1505 | return; | |
1506 | ||
1507 | list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), | |
1508 | loaded_vmcss_on_cpu_link) | |
1509 | vmcs_clear(v->vmcs); | |
1510 | } | |
1511 | #else | |
1512 | static inline void crash_enable_local_vmclear(int cpu) { } | |
1513 | static inline void crash_disable_local_vmclear(int cpu) { } | |
2965faa5 | 1514 | #endif /* CONFIG_KEXEC_CORE */ |
8f536b76 | 1515 | |
d462b819 | 1516 | static void __loaded_vmcs_clear(void *arg) |
6aa8b732 | 1517 | { |
d462b819 | 1518 | struct loaded_vmcs *loaded_vmcs = arg; |
d3b2c338 | 1519 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 1520 | |
d462b819 NHE |
1521 | if (loaded_vmcs->cpu != cpu) |
1522 | return; /* vcpu migration can race with cpu offline */ | |
1523 | if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) | |
6aa8b732 | 1524 | per_cpu(current_vmcs, cpu) = NULL; |
8f536b76 | 1525 | crash_disable_local_vmclear(cpu); |
d462b819 | 1526 | list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); |
5a560f8b XG |
1527 | |
1528 | /* | |
1529 | * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link | |
1530 | * is before setting loaded_vmcs->vcpu to -1 which is done in | |
1531 | * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist | |
1532 | * then adds the vmcs into percpu list before it is deleted. | |
1533 | */ | |
1534 | smp_wmb(); | |
1535 | ||
d462b819 | 1536 | loaded_vmcs_init(loaded_vmcs); |
8f536b76 | 1537 | crash_enable_local_vmclear(cpu); |
6aa8b732 AK |
1538 | } |
1539 | ||
d462b819 | 1540 | static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) |
8d0be2b3 | 1541 | { |
e6c7d321 XG |
1542 | int cpu = loaded_vmcs->cpu; |
1543 | ||
1544 | if (cpu != -1) | |
1545 | smp_call_function_single(cpu, | |
1546 | __loaded_vmcs_clear, loaded_vmcs, 1); | |
8d0be2b3 AK |
1547 | } |
1548 | ||
dd5f5341 | 1549 | static inline void vpid_sync_vcpu_single(int vpid) |
2384d2b3 | 1550 | { |
dd5f5341 | 1551 | if (vpid == 0) |
2384d2b3 SY |
1552 | return; |
1553 | ||
518c8aee | 1554 | if (cpu_has_vmx_invvpid_single()) |
dd5f5341 | 1555 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0); |
2384d2b3 SY |
1556 | } |
1557 | ||
b9d762fa GJ |
1558 | static inline void vpid_sync_vcpu_global(void) |
1559 | { | |
1560 | if (cpu_has_vmx_invvpid_global()) | |
1561 | __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0); | |
1562 | } | |
1563 | ||
dd5f5341 | 1564 | static inline void vpid_sync_context(int vpid) |
b9d762fa GJ |
1565 | { |
1566 | if (cpu_has_vmx_invvpid_single()) | |
dd5f5341 | 1567 | vpid_sync_vcpu_single(vpid); |
b9d762fa GJ |
1568 | else |
1569 | vpid_sync_vcpu_global(); | |
1570 | } | |
1571 | ||
1439442c SY |
1572 | static inline void ept_sync_global(void) |
1573 | { | |
1574 | if (cpu_has_vmx_invept_global()) | |
1575 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); | |
1576 | } | |
1577 | ||
1578 | static inline void ept_sync_context(u64 eptp) | |
1579 | { | |
089d034e | 1580 | if (enable_ept) { |
1439442c SY |
1581 | if (cpu_has_vmx_invept_context()) |
1582 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
1583 | else | |
1584 | ept_sync_global(); | |
1585 | } | |
1586 | } | |
1587 | ||
8a86aea9 PB |
1588 | static __always_inline void vmcs_check16(unsigned long field) |
1589 | { | |
1590 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000, | |
1591 | "16-bit accessor invalid for 64-bit field"); | |
1592 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1593 | "16-bit accessor invalid for 64-bit high field"); | |
1594 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1595 | "16-bit accessor invalid for 32-bit high field"); | |
1596 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1597 | "16-bit accessor invalid for natural width field"); | |
1598 | } | |
1599 | ||
1600 | static __always_inline void vmcs_check32(unsigned long field) | |
1601 | { | |
1602 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1603 | "32-bit accessor invalid for 16-bit field"); | |
1604 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1605 | "32-bit accessor invalid for natural width field"); | |
1606 | } | |
1607 | ||
1608 | static __always_inline void vmcs_check64(unsigned long field) | |
1609 | { | |
1610 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1611 | "64-bit accessor invalid for 16-bit field"); | |
1612 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1613 | "64-bit accessor invalid for 64-bit high field"); | |
1614 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1615 | "64-bit accessor invalid for 32-bit field"); | |
1616 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1617 | "64-bit accessor invalid for natural width field"); | |
1618 | } | |
1619 | ||
1620 | static __always_inline void vmcs_checkl(unsigned long field) | |
1621 | { | |
1622 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1623 | "Natural width accessor invalid for 16-bit field"); | |
1624 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000, | |
1625 | "Natural width accessor invalid for 64-bit field"); | |
1626 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1627 | "Natural width accessor invalid for 64-bit high field"); | |
1628 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1629 | "Natural width accessor invalid for 32-bit field"); | |
1630 | } | |
1631 | ||
1632 | static __always_inline unsigned long __vmcs_readl(unsigned long field) | |
6aa8b732 | 1633 | { |
5e520e62 | 1634 | unsigned long value; |
6aa8b732 | 1635 | |
5e520e62 AK |
1636 | asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0") |
1637 | : "=a"(value) : "d"(field) : "cc"); | |
6aa8b732 AK |
1638 | return value; |
1639 | } | |
1640 | ||
96304217 | 1641 | static __always_inline u16 vmcs_read16(unsigned long field) |
6aa8b732 | 1642 | { |
8a86aea9 PB |
1643 | vmcs_check16(field); |
1644 | return __vmcs_readl(field); | |
6aa8b732 AK |
1645 | } |
1646 | ||
96304217 | 1647 | static __always_inline u32 vmcs_read32(unsigned long field) |
6aa8b732 | 1648 | { |
8a86aea9 PB |
1649 | vmcs_check32(field); |
1650 | return __vmcs_readl(field); | |
6aa8b732 AK |
1651 | } |
1652 | ||
96304217 | 1653 | static __always_inline u64 vmcs_read64(unsigned long field) |
6aa8b732 | 1654 | { |
8a86aea9 | 1655 | vmcs_check64(field); |
05b3e0c2 | 1656 | #ifdef CONFIG_X86_64 |
8a86aea9 | 1657 | return __vmcs_readl(field); |
6aa8b732 | 1658 | #else |
8a86aea9 | 1659 | return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32); |
6aa8b732 AK |
1660 | #endif |
1661 | } | |
1662 | ||
8a86aea9 PB |
1663 | static __always_inline unsigned long vmcs_readl(unsigned long field) |
1664 | { | |
1665 | vmcs_checkl(field); | |
1666 | return __vmcs_readl(field); | |
1667 | } | |
1668 | ||
e52de1b8 AK |
1669 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
1670 | { | |
1671 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
1672 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
1673 | dump_stack(); | |
1674 | } | |
1675 | ||
8a86aea9 | 1676 | static __always_inline void __vmcs_writel(unsigned long field, unsigned long value) |
6aa8b732 AK |
1677 | { |
1678 | u8 error; | |
1679 | ||
4ecac3fd | 1680 | asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
d77c26fc | 1681 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
1682 | if (unlikely(error)) |
1683 | vmwrite_error(field, value); | |
6aa8b732 AK |
1684 | } |
1685 | ||
8a86aea9 | 1686 | static __always_inline void vmcs_write16(unsigned long field, u16 value) |
6aa8b732 | 1687 | { |
8a86aea9 PB |
1688 | vmcs_check16(field); |
1689 | __vmcs_writel(field, value); | |
6aa8b732 AK |
1690 | } |
1691 | ||
8a86aea9 | 1692 | static __always_inline void vmcs_write32(unsigned long field, u32 value) |
6aa8b732 | 1693 | { |
8a86aea9 PB |
1694 | vmcs_check32(field); |
1695 | __vmcs_writel(field, value); | |
6aa8b732 AK |
1696 | } |
1697 | ||
8a86aea9 | 1698 | static __always_inline void vmcs_write64(unsigned long field, u64 value) |
6aa8b732 | 1699 | { |
8a86aea9 PB |
1700 | vmcs_check64(field); |
1701 | __vmcs_writel(field, value); | |
7682f2d0 | 1702 | #ifndef CONFIG_X86_64 |
6aa8b732 | 1703 | asm volatile (""); |
8a86aea9 | 1704 | __vmcs_writel(field+1, value >> 32); |
6aa8b732 AK |
1705 | #endif |
1706 | } | |
1707 | ||
8a86aea9 | 1708 | static __always_inline void vmcs_writel(unsigned long field, unsigned long value) |
2ab455cc | 1709 | { |
8a86aea9 PB |
1710 | vmcs_checkl(field); |
1711 | __vmcs_writel(field, value); | |
2ab455cc AL |
1712 | } |
1713 | ||
8a86aea9 | 1714 | static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask) |
2ab455cc | 1715 | { |
8a86aea9 PB |
1716 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000, |
1717 | "vmcs_clear_bits does not support 64-bit fields"); | |
1718 | __vmcs_writel(field, __vmcs_readl(field) & ~mask); | |
2ab455cc AL |
1719 | } |
1720 | ||
8a86aea9 | 1721 | static __always_inline void vmcs_set_bits(unsigned long field, u32 mask) |
2ab455cc | 1722 | { |
8a86aea9 PB |
1723 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000, |
1724 | "vmcs_set_bits does not support 64-bit fields"); | |
1725 | __vmcs_writel(field, __vmcs_readl(field) | mask); | |
2ab455cc AL |
1726 | } |
1727 | ||
8391ce44 PB |
1728 | static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx) |
1729 | { | |
1730 | vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS); | |
1731 | } | |
1732 | ||
2961e876 GN |
1733 | static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val) |
1734 | { | |
1735 | vmcs_write32(VM_ENTRY_CONTROLS, val); | |
1736 | vmx->vm_entry_controls_shadow = val; | |
1737 | } | |
1738 | ||
1739 | static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1740 | { | |
1741 | if (vmx->vm_entry_controls_shadow != val) | |
1742 | vm_entry_controls_init(vmx, val); | |
1743 | } | |
1744 | ||
1745 | static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx) | |
1746 | { | |
1747 | return vmx->vm_entry_controls_shadow; | |
1748 | } | |
1749 | ||
1750 | ||
1751 | static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1752 | { | |
1753 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val); | |
1754 | } | |
1755 | ||
1756 | static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1757 | { | |
1758 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val); | |
1759 | } | |
1760 | ||
8391ce44 PB |
1761 | static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx) |
1762 | { | |
1763 | vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS); | |
1764 | } | |
1765 | ||
2961e876 GN |
1766 | static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val) |
1767 | { | |
1768 | vmcs_write32(VM_EXIT_CONTROLS, val); | |
1769 | vmx->vm_exit_controls_shadow = val; | |
1770 | } | |
1771 | ||
1772 | static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1773 | { | |
1774 | if (vmx->vm_exit_controls_shadow != val) | |
1775 | vm_exit_controls_init(vmx, val); | |
1776 | } | |
1777 | ||
1778 | static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx) | |
1779 | { | |
1780 | return vmx->vm_exit_controls_shadow; | |
1781 | } | |
1782 | ||
1783 | ||
1784 | static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1785 | { | |
1786 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val); | |
1787 | } | |
1788 | ||
1789 | static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1790 | { | |
1791 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val); | |
1792 | } | |
1793 | ||
2fb92db1 AK |
1794 | static void vmx_segment_cache_clear(struct vcpu_vmx *vmx) |
1795 | { | |
1796 | vmx->segment_cache.bitmask = 0; | |
1797 | } | |
1798 | ||
1799 | static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, | |
1800 | unsigned field) | |
1801 | { | |
1802 | bool ret; | |
1803 | u32 mask = 1 << (seg * SEG_FIELD_NR + field); | |
1804 | ||
1805 | if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) { | |
1806 | vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS); | |
1807 | vmx->segment_cache.bitmask = 0; | |
1808 | } | |
1809 | ret = vmx->segment_cache.bitmask & mask; | |
1810 | vmx->segment_cache.bitmask |= mask; | |
1811 | return ret; | |
1812 | } | |
1813 | ||
1814 | static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) | |
1815 | { | |
1816 | u16 *p = &vmx->segment_cache.seg[seg].selector; | |
1817 | ||
1818 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) | |
1819 | *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); | |
1820 | return *p; | |
1821 | } | |
1822 | ||
1823 | static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) | |
1824 | { | |
1825 | ulong *p = &vmx->segment_cache.seg[seg].base; | |
1826 | ||
1827 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) | |
1828 | *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); | |
1829 | return *p; | |
1830 | } | |
1831 | ||
1832 | static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) | |
1833 | { | |
1834 | u32 *p = &vmx->segment_cache.seg[seg].limit; | |
1835 | ||
1836 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) | |
1837 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); | |
1838 | return *p; | |
1839 | } | |
1840 | ||
1841 | static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) | |
1842 | { | |
1843 | u32 *p = &vmx->segment_cache.seg[seg].ar; | |
1844 | ||
1845 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) | |
1846 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); | |
1847 | return *p; | |
1848 | } | |
1849 | ||
abd3f2d6 AK |
1850 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
1851 | { | |
1852 | u32 eb; | |
1853 | ||
fd7373cc | 1854 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | |
54a20552 | 1855 | (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR); |
fd7373cc JK |
1856 | if ((vcpu->guest_debug & |
1857 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == | |
1858 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) | |
1859 | eb |= 1u << BP_VECTOR; | |
7ffd92c5 | 1860 | if (to_vmx(vcpu)->rmode.vm86_active) |
abd3f2d6 | 1861 | eb = ~0; |
089d034e | 1862 | if (enable_ept) |
1439442c | 1863 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ |
02daab21 AK |
1864 | if (vcpu->fpu_active) |
1865 | eb &= ~(1u << NM_VECTOR); | |
36cf24e0 NHE |
1866 | |
1867 | /* When we are running a nested L2 guest and L1 specified for it a | |
1868 | * certain exception bitmap, we must trap the same exceptions and pass | |
1869 | * them to L1. When running L2, we will only handle the exceptions | |
1870 | * specified above if L1 did not want them. | |
1871 | */ | |
1872 | if (is_guest_mode(vcpu)) | |
1873 | eb |= get_vmcs12(vcpu)->exception_bitmap; | |
1874 | ||
abd3f2d6 AK |
1875 | vmcs_write32(EXCEPTION_BITMAP, eb); |
1876 | } | |
1877 | ||
2961e876 GN |
1878 | static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
1879 | unsigned long entry, unsigned long exit) | |
8bf00a52 | 1880 | { |
2961e876 GN |
1881 | vm_entry_controls_clearbit(vmx, entry); |
1882 | vm_exit_controls_clearbit(vmx, exit); | |
8bf00a52 GN |
1883 | } |
1884 | ||
61d2ef2c AK |
1885 | static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) |
1886 | { | |
1887 | unsigned i; | |
1888 | struct msr_autoload *m = &vmx->msr_autoload; | |
1889 | ||
8bf00a52 GN |
1890 | switch (msr) { |
1891 | case MSR_EFER: | |
1892 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
1893 | clear_atomic_switch_msr_special(vmx, |
1894 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
1895 | VM_EXIT_LOAD_IA32_EFER); |
1896 | return; | |
1897 | } | |
1898 | break; | |
1899 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
1900 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 1901 | clear_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
1902 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
1903 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
1904 | return; | |
1905 | } | |
1906 | break; | |
110312c8 AK |
1907 | } |
1908 | ||
61d2ef2c AK |
1909 | for (i = 0; i < m->nr; ++i) |
1910 | if (m->guest[i].index == msr) | |
1911 | break; | |
1912 | ||
1913 | if (i == m->nr) | |
1914 | return; | |
1915 | --m->nr; | |
1916 | m->guest[i] = m->guest[m->nr]; | |
1917 | m->host[i] = m->host[m->nr]; | |
1918 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
1919 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
1920 | } | |
1921 | ||
2961e876 GN |
1922 | static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
1923 | unsigned long entry, unsigned long exit, | |
1924 | unsigned long guest_val_vmcs, unsigned long host_val_vmcs, | |
1925 | u64 guest_val, u64 host_val) | |
8bf00a52 GN |
1926 | { |
1927 | vmcs_write64(guest_val_vmcs, guest_val); | |
1928 | vmcs_write64(host_val_vmcs, host_val); | |
2961e876 GN |
1929 | vm_entry_controls_setbit(vmx, entry); |
1930 | vm_exit_controls_setbit(vmx, exit); | |
8bf00a52 GN |
1931 | } |
1932 | ||
61d2ef2c AK |
1933 | static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, |
1934 | u64 guest_val, u64 host_val) | |
1935 | { | |
1936 | unsigned i; | |
1937 | struct msr_autoload *m = &vmx->msr_autoload; | |
1938 | ||
8bf00a52 GN |
1939 | switch (msr) { |
1940 | case MSR_EFER: | |
1941 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
1942 | add_atomic_switch_msr_special(vmx, |
1943 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
1944 | VM_EXIT_LOAD_IA32_EFER, |
1945 | GUEST_IA32_EFER, | |
1946 | HOST_IA32_EFER, | |
1947 | guest_val, host_val); | |
1948 | return; | |
1949 | } | |
1950 | break; | |
1951 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
1952 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 1953 | add_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
1954 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
1955 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, | |
1956 | GUEST_IA32_PERF_GLOBAL_CTRL, | |
1957 | HOST_IA32_PERF_GLOBAL_CTRL, | |
1958 | guest_val, host_val); | |
1959 | return; | |
1960 | } | |
1961 | break; | |
7099e2e1 RK |
1962 | case MSR_IA32_PEBS_ENABLE: |
1963 | /* PEBS needs a quiescent period after being disabled (to write | |
1964 | * a record). Disabling PEBS through VMX MSR swapping doesn't | |
1965 | * provide that period, so a CPU could write host's record into | |
1966 | * guest's memory. | |
1967 | */ | |
1968 | wrmsrl(MSR_IA32_PEBS_ENABLE, 0); | |
110312c8 AK |
1969 | } |
1970 | ||
61d2ef2c AK |
1971 | for (i = 0; i < m->nr; ++i) |
1972 | if (m->guest[i].index == msr) | |
1973 | break; | |
1974 | ||
e7fc6f93 | 1975 | if (i == NR_AUTOLOAD_MSRS) { |
60266204 | 1976 | printk_once(KERN_WARNING "Not enough msr switch entries. " |
e7fc6f93 GN |
1977 | "Can't add msr %x\n", msr); |
1978 | return; | |
1979 | } else if (i == m->nr) { | |
61d2ef2c AK |
1980 | ++m->nr; |
1981 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
1982 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
1983 | } | |
1984 | ||
1985 | m->guest[i].index = msr; | |
1986 | m->guest[i].value = guest_val; | |
1987 | m->host[i].index = msr; | |
1988 | m->host[i].value = host_val; | |
1989 | } | |
1990 | ||
33ed6329 AK |
1991 | static void reload_tss(void) |
1992 | { | |
33ed6329 AK |
1993 | /* |
1994 | * VT restores TR but not its size. Useless. | |
1995 | */ | |
89cbc767 | 1996 | struct desc_ptr *gdt = this_cpu_ptr(&host_gdt); |
a5f61300 | 1997 | struct desc_struct *descs; |
33ed6329 | 1998 | |
d359192f | 1999 | descs = (void *)gdt->address; |
33ed6329 AK |
2000 | descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ |
2001 | load_TR_desc(); | |
33ed6329 AK |
2002 | } |
2003 | ||
92c0d900 | 2004 | static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) |
2cc51560 | 2005 | { |
844a5fe2 PB |
2006 | u64 guest_efer = vmx->vcpu.arch.efer; |
2007 | u64 ignore_bits = 0; | |
2008 | ||
2009 | if (!enable_ept) { | |
2010 | /* | |
2011 | * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing | |
2012 | * host CPUID is more efficient than testing guest CPUID | |
2013 | * or CR4. Host SMEP is anyway a requirement for guest SMEP. | |
2014 | */ | |
2015 | if (boot_cpu_has(X86_FEATURE_SMEP)) | |
2016 | guest_efer |= EFER_NX; | |
2017 | else if (!(guest_efer & EFER_NX)) | |
2018 | ignore_bits |= EFER_NX; | |
2019 | } | |
3a34a881 | 2020 | |
51c6cf66 | 2021 | /* |
844a5fe2 | 2022 | * LMA and LME handled by hardware; SCE meaningless outside long mode. |
51c6cf66 | 2023 | */ |
844a5fe2 | 2024 | ignore_bits |= EFER_SCE; |
51c6cf66 AK |
2025 | #ifdef CONFIG_X86_64 |
2026 | ignore_bits |= EFER_LMA | EFER_LME; | |
2027 | /* SCE is meaningful only in long mode on Intel */ | |
2028 | if (guest_efer & EFER_LMA) | |
2029 | ignore_bits &= ~(u64)EFER_SCE; | |
2030 | #endif | |
84ad33ef AK |
2031 | |
2032 | clear_atomic_switch_msr(vmx, MSR_EFER); | |
f6577a5f AL |
2033 | |
2034 | /* | |
2035 | * On EPT, we can't emulate NX, so we must switch EFER atomically. | |
2036 | * On CPUs that support "load IA32_EFER", always switch EFER | |
2037 | * atomically, since it's faster than switching it manually. | |
2038 | */ | |
2039 | if (cpu_has_load_ia32_efer || | |
2040 | (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { | |
84ad33ef AK |
2041 | if (!(guest_efer & EFER_LMA)) |
2042 | guest_efer &= ~EFER_LME; | |
54b98bff AL |
2043 | if (guest_efer != host_efer) |
2044 | add_atomic_switch_msr(vmx, MSR_EFER, | |
2045 | guest_efer, host_efer); | |
84ad33ef | 2046 | return false; |
844a5fe2 PB |
2047 | } else { |
2048 | guest_efer &= ~ignore_bits; | |
2049 | guest_efer |= host_efer & ignore_bits; | |
2050 | ||
2051 | vmx->guest_msrs[efer_offset].data = guest_efer; | |
2052 | vmx->guest_msrs[efer_offset].mask = ~ignore_bits; | |
84ad33ef | 2053 | |
844a5fe2 PB |
2054 | return true; |
2055 | } | |
51c6cf66 AK |
2056 | } |
2057 | ||
2d49ec72 GN |
2058 | static unsigned long segment_base(u16 selector) |
2059 | { | |
89cbc767 | 2060 | struct desc_ptr *gdt = this_cpu_ptr(&host_gdt); |
2d49ec72 GN |
2061 | struct desc_struct *d; |
2062 | unsigned long table_base; | |
2063 | unsigned long v; | |
2064 | ||
2065 | if (!(selector & ~3)) | |
2066 | return 0; | |
2067 | ||
d359192f | 2068 | table_base = gdt->address; |
2d49ec72 GN |
2069 | |
2070 | if (selector & 4) { /* from ldt */ | |
2071 | u16 ldt_selector = kvm_read_ldt(); | |
2072 | ||
2073 | if (!(ldt_selector & ~3)) | |
2074 | return 0; | |
2075 | ||
2076 | table_base = segment_base(ldt_selector); | |
2077 | } | |
2078 | d = (struct desc_struct *)(table_base + (selector & ~7)); | |
2079 | v = get_desc_base(d); | |
2080 | #ifdef CONFIG_X86_64 | |
2081 | if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11)) | |
2082 | v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32; | |
2083 | #endif | |
2084 | return v; | |
2085 | } | |
2086 | ||
2087 | static inline unsigned long kvm_read_tr_base(void) | |
2088 | { | |
2089 | u16 tr; | |
2090 | asm("str %0" : "=g"(tr)); | |
2091 | return segment_base(tr); | |
2092 | } | |
2093 | ||
04d2cc77 | 2094 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 2095 | { |
04d2cc77 | 2096 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 2097 | int i; |
04d2cc77 | 2098 | |
a2fa3e9f | 2099 | if (vmx->host_state.loaded) |
33ed6329 AK |
2100 | return; |
2101 | ||
a2fa3e9f | 2102 | vmx->host_state.loaded = 1; |
33ed6329 AK |
2103 | /* |
2104 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
2105 | * allow segment selectors with cpl > 0 or ti == 1. | |
2106 | */ | |
d6e88aec | 2107 | vmx->host_state.ldt_sel = kvm_read_ldt(); |
152d3f2f | 2108 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
9581d442 | 2109 | savesegment(fs, vmx->host_state.fs_sel); |
152d3f2f | 2110 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 2111 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
2112 | vmx->host_state.fs_reload_needed = 0; |
2113 | } else { | |
33ed6329 | 2114 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 2115 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 2116 | } |
9581d442 | 2117 | savesegment(gs, vmx->host_state.gs_sel); |
a2fa3e9f GH |
2118 | if (!(vmx->host_state.gs_sel & 7)) |
2119 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
2120 | else { |
2121 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 2122 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
2123 | } |
2124 | ||
b2da15ac AK |
2125 | #ifdef CONFIG_X86_64 |
2126 | savesegment(ds, vmx->host_state.ds_sel); | |
2127 | savesegment(es, vmx->host_state.es_sel); | |
2128 | #endif | |
2129 | ||
33ed6329 AK |
2130 | #ifdef CONFIG_X86_64 |
2131 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
2132 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
2133 | #else | |
a2fa3e9f GH |
2134 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
2135 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 2136 | #endif |
707c0874 AK |
2137 | |
2138 | #ifdef CONFIG_X86_64 | |
c8770e7b AK |
2139 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
2140 | if (is_long_mode(&vmx->vcpu)) | |
44ea2b17 | 2141 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); |
707c0874 | 2142 | #endif |
da8999d3 LJ |
2143 | if (boot_cpu_has(X86_FEATURE_MPX)) |
2144 | rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
26bb0981 AK |
2145 | for (i = 0; i < vmx->save_nmsrs; ++i) |
2146 | kvm_set_shared_msr(vmx->guest_msrs[i].index, | |
d5696725 AK |
2147 | vmx->guest_msrs[i].data, |
2148 | vmx->guest_msrs[i].mask); | |
33ed6329 AK |
2149 | } |
2150 | ||
a9b21b62 | 2151 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 2152 | { |
a2fa3e9f | 2153 | if (!vmx->host_state.loaded) |
33ed6329 AK |
2154 | return; |
2155 | ||
e1beb1d3 | 2156 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 2157 | vmx->host_state.loaded = 0; |
c8770e7b AK |
2158 | #ifdef CONFIG_X86_64 |
2159 | if (is_long_mode(&vmx->vcpu)) | |
2160 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); | |
2161 | #endif | |
152d3f2f | 2162 | if (vmx->host_state.gs_ldt_reload_needed) { |
d6e88aec | 2163 | kvm_load_ldt(vmx->host_state.ldt_sel); |
33ed6329 | 2164 | #ifdef CONFIG_X86_64 |
9581d442 | 2165 | load_gs_index(vmx->host_state.gs_sel); |
9581d442 AK |
2166 | #else |
2167 | loadsegment(gs, vmx->host_state.gs_sel); | |
33ed6329 | 2168 | #endif |
33ed6329 | 2169 | } |
0a77fe4c AK |
2170 | if (vmx->host_state.fs_reload_needed) |
2171 | loadsegment(fs, vmx->host_state.fs_sel); | |
b2da15ac AK |
2172 | #ifdef CONFIG_X86_64 |
2173 | if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) { | |
2174 | loadsegment(ds, vmx->host_state.ds_sel); | |
2175 | loadsegment(es, vmx->host_state.es_sel); | |
2176 | } | |
b2da15ac | 2177 | #endif |
152d3f2f | 2178 | reload_tss(); |
44ea2b17 | 2179 | #ifdef CONFIG_X86_64 |
c8770e7b | 2180 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
44ea2b17 | 2181 | #endif |
da8999d3 LJ |
2182 | if (vmx->host_state.msr_host_bndcfgs) |
2183 | wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
b1a74bf8 SS |
2184 | /* |
2185 | * If the FPU is not active (through the host task or | |
2186 | * the guest vcpu), then restore the cr0.TS bit. | |
2187 | */ | |
3c6dffa9 | 2188 | if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded) |
b1a74bf8 | 2189 | stts(); |
89cbc767 | 2190 | load_gdt(this_cpu_ptr(&host_gdt)); |
33ed6329 AK |
2191 | } |
2192 | ||
a9b21b62 AK |
2193 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
2194 | { | |
2195 | preempt_disable(); | |
2196 | __vmx_load_host_state(vmx); | |
2197 | preempt_enable(); | |
2198 | } | |
2199 | ||
28b835d6 FW |
2200 | static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) |
2201 | { | |
2202 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
2203 | struct pi_desc old, new; | |
2204 | unsigned int dest; | |
2205 | ||
2206 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
2207 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
2208 | !kvm_vcpu_apicv_active(vcpu)) | |
28b835d6 FW |
2209 | return; |
2210 | ||
2211 | do { | |
2212 | old.control = new.control = pi_desc->control; | |
2213 | ||
2214 | /* | |
2215 | * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there | |
2216 | * are two possible cases: | |
2217 | * 1. After running 'pre_block', context switch | |
2218 | * happened. For this case, 'sn' was set in | |
2219 | * vmx_vcpu_put(), so we need to clear it here. | |
2220 | * 2. After running 'pre_block', we were blocked, | |
2221 | * and woken up by some other guy. For this case, | |
2222 | * we don't need to do anything, 'pi_post_block' | |
2223 | * will do everything for us. However, we cannot | |
2224 | * check whether it is case #1 or case #2 here | |
2225 | * (maybe, not needed), so we also clear sn here, | |
2226 | * I think it is not a big deal. | |
2227 | */ | |
2228 | if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) { | |
2229 | if (vcpu->cpu != cpu) { | |
2230 | dest = cpu_physical_id(cpu); | |
2231 | ||
2232 | if (x2apic_enabled()) | |
2233 | new.ndst = dest; | |
2234 | else | |
2235 | new.ndst = (dest << 8) & 0xFF00; | |
2236 | } | |
2237 | ||
2238 | /* set 'NV' to 'notification vector' */ | |
2239 | new.nv = POSTED_INTR_VECTOR; | |
2240 | } | |
2241 | ||
2242 | /* Allow posting non-urgent interrupts */ | |
2243 | new.sn = 0; | |
2244 | } while (cmpxchg(&pi_desc->control, old.control, | |
2245 | new.control) != old.control); | |
2246 | } | |
1be0e61c | 2247 | |
c95ba92a PF |
2248 | static void decache_tsc_multiplier(struct vcpu_vmx *vmx) |
2249 | { | |
2250 | vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio; | |
2251 | vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio); | |
2252 | } | |
2253 | ||
6aa8b732 AK |
2254 | /* |
2255 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
2256 | * vcpu mutex is already taken. | |
2257 | */ | |
15ad7146 | 2258 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 2259 | { |
a2fa3e9f | 2260 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4610c9cc | 2261 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); |
b80c76ec | 2262 | bool already_loaded = vmx->loaded_vmcs->cpu == cpu; |
6aa8b732 | 2263 | |
4610c9cc DX |
2264 | if (!vmm_exclusive) |
2265 | kvm_cpu_vmxon(phys_addr); | |
b80c76ec | 2266 | else if (!already_loaded) |
d462b819 | 2267 | loaded_vmcs_clear(vmx->loaded_vmcs); |
6aa8b732 | 2268 | |
b80c76ec | 2269 | if (!already_loaded) { |
92fe13be | 2270 | local_irq_disable(); |
8f536b76 | 2271 | crash_disable_local_vmclear(cpu); |
5a560f8b XG |
2272 | |
2273 | /* | |
2274 | * Read loaded_vmcs->cpu should be before fetching | |
2275 | * loaded_vmcs->loaded_vmcss_on_cpu_link. | |
2276 | * See the comments in __loaded_vmcs_clear(). | |
2277 | */ | |
2278 | smp_rmb(); | |
2279 | ||
d462b819 NHE |
2280 | list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, |
2281 | &per_cpu(loaded_vmcss_on_cpu, cpu)); | |
8f536b76 | 2282 | crash_enable_local_vmclear(cpu); |
92fe13be | 2283 | local_irq_enable(); |
b80c76ec JM |
2284 | } |
2285 | ||
2286 | if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { | |
2287 | per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; | |
2288 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
2289 | } | |
2290 | ||
2291 | if (!already_loaded) { | |
2292 | struct desc_ptr *gdt = this_cpu_ptr(&host_gdt); | |
2293 | unsigned long sysenter_esp; | |
2294 | ||
2295 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
92fe13be | 2296 | |
6aa8b732 AK |
2297 | /* |
2298 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
2299 | * processors. | |
2300 | */ | |
d6e88aec | 2301 | vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */ |
d359192f | 2302 | vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */ |
6aa8b732 AK |
2303 | |
2304 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
2305 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
ff2c3a18 | 2306 | |
d462b819 | 2307 | vmx->loaded_vmcs->cpu = cpu; |
6aa8b732 | 2308 | } |
28b835d6 | 2309 | |
2680d6da OH |
2310 | /* Setup TSC multiplier */ |
2311 | if (kvm_has_tsc_control && | |
c95ba92a PF |
2312 | vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) |
2313 | decache_tsc_multiplier(vmx); | |
2680d6da | 2314 | |
28b835d6 | 2315 | vmx_vcpu_pi_load(vcpu, cpu); |
1be0e61c | 2316 | vmx->host_pkru = read_pkru(); |
28b835d6 FW |
2317 | } |
2318 | ||
2319 | static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) | |
2320 | { | |
2321 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
2322 | ||
2323 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
2324 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
2325 | !kvm_vcpu_apicv_active(vcpu)) | |
28b835d6 FW |
2326 | return; |
2327 | ||
2328 | /* Set SN when the vCPU is preempted */ | |
2329 | if (vcpu->preempted) | |
2330 | pi_set_sn(pi_desc); | |
6aa8b732 AK |
2331 | } |
2332 | ||
2333 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
2334 | { | |
28b835d6 FW |
2335 | vmx_vcpu_pi_put(vcpu); |
2336 | ||
a9b21b62 | 2337 | __vmx_load_host_state(to_vmx(vcpu)); |
4610c9cc | 2338 | if (!vmm_exclusive) { |
d462b819 NHE |
2339 | __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs); |
2340 | vcpu->cpu = -1; | |
4610c9cc DX |
2341 | kvm_cpu_vmxoff(); |
2342 | } | |
6aa8b732 AK |
2343 | } |
2344 | ||
5fd86fcf AK |
2345 | static void vmx_fpu_activate(struct kvm_vcpu *vcpu) |
2346 | { | |
81231c69 AK |
2347 | ulong cr0; |
2348 | ||
5fd86fcf AK |
2349 | if (vcpu->fpu_active) |
2350 | return; | |
2351 | vcpu->fpu_active = 1; | |
81231c69 AK |
2352 | cr0 = vmcs_readl(GUEST_CR0); |
2353 | cr0 &= ~(X86_CR0_TS | X86_CR0_MP); | |
2354 | cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP); | |
2355 | vmcs_writel(GUEST_CR0, cr0); | |
5fd86fcf | 2356 | update_exception_bitmap(vcpu); |
edcafe3c | 2357 | vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS; |
36cf24e0 NHE |
2358 | if (is_guest_mode(vcpu)) |
2359 | vcpu->arch.cr0_guest_owned_bits &= | |
2360 | ~get_vmcs12(vcpu)->cr0_guest_host_mask; | |
edcafe3c | 2361 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); |
5fd86fcf AK |
2362 | } |
2363 | ||
edcafe3c AK |
2364 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); |
2365 | ||
fe3ef05c NHE |
2366 | /* |
2367 | * Return the cr0 value that a nested guest would read. This is a combination | |
2368 | * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by | |
2369 | * its hypervisor (cr0_read_shadow). | |
2370 | */ | |
2371 | static inline unsigned long nested_read_cr0(struct vmcs12 *fields) | |
2372 | { | |
2373 | return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) | | |
2374 | (fields->cr0_read_shadow & fields->cr0_guest_host_mask); | |
2375 | } | |
2376 | static inline unsigned long nested_read_cr4(struct vmcs12 *fields) | |
2377 | { | |
2378 | return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) | | |
2379 | (fields->cr4_read_shadow & fields->cr4_guest_host_mask); | |
2380 | } | |
2381 | ||
5fd86fcf AK |
2382 | static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu) |
2383 | { | |
36cf24e0 NHE |
2384 | /* Note that there is no vcpu->fpu_active = 0 here. The caller must |
2385 | * set this *before* calling this function. | |
2386 | */ | |
edcafe3c | 2387 | vmx_decache_cr0_guest_bits(vcpu); |
81231c69 | 2388 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP); |
5fd86fcf | 2389 | update_exception_bitmap(vcpu); |
edcafe3c AK |
2390 | vcpu->arch.cr0_guest_owned_bits = 0; |
2391 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
36cf24e0 NHE |
2392 | if (is_guest_mode(vcpu)) { |
2393 | /* | |
2394 | * L1's specified read shadow might not contain the TS bit, | |
2395 | * so now that we turned on shadowing of this bit, we need to | |
2396 | * set this bit of the shadow. Like in nested_vmx_run we need | |
2397 | * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet | |
2398 | * up-to-date here because we just decached cr0.TS (and we'll | |
2399 | * only update vmcs12->guest_cr0 on nested exit). | |
2400 | */ | |
2401 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
2402 | vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) | | |
2403 | (vcpu->arch.cr0 & X86_CR0_TS); | |
2404 | vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); | |
2405 | } else | |
2406 | vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0); | |
5fd86fcf AK |
2407 | } |
2408 | ||
6aa8b732 AK |
2409 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
2410 | { | |
78ac8b47 | 2411 | unsigned long rflags, save_rflags; |
345dcaa8 | 2412 | |
6de12732 AK |
2413 | if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) { |
2414 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); | |
2415 | rflags = vmcs_readl(GUEST_RFLAGS); | |
2416 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
2417 | rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; | |
2418 | save_rflags = to_vmx(vcpu)->rmode.save_rflags; | |
2419 | rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
2420 | } | |
2421 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 | 2422 | } |
6de12732 | 2423 | return to_vmx(vcpu)->rflags; |
6aa8b732 AK |
2424 | } |
2425 | ||
2426 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
2427 | { | |
6de12732 AK |
2428 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); |
2429 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 AK |
2430 | if (to_vmx(vcpu)->rmode.vm86_active) { |
2431 | to_vmx(vcpu)->rmode.save_rflags = rflags; | |
053de044 | 2432 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
78ac8b47 | 2433 | } |
6aa8b732 AK |
2434 | vmcs_writel(GUEST_RFLAGS, rflags); |
2435 | } | |
2436 | ||
be94f6b7 HH |
2437 | static u32 vmx_get_pkru(struct kvm_vcpu *vcpu) |
2438 | { | |
2439 | return to_vmx(vcpu)->guest_pkru; | |
2440 | } | |
2441 | ||
37ccdcbe | 2442 | static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
2443 | { |
2444 | u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2445 | int ret = 0; | |
2446 | ||
2447 | if (interruptibility & GUEST_INTR_STATE_STI) | |
48005f64 | 2448 | ret |= KVM_X86_SHADOW_INT_STI; |
2809f5d2 | 2449 | if (interruptibility & GUEST_INTR_STATE_MOV_SS) |
48005f64 | 2450 | ret |= KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 | 2451 | |
37ccdcbe | 2452 | return ret; |
2809f5d2 GC |
2453 | } |
2454 | ||
2455 | static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
2456 | { | |
2457 | u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2458 | u32 interruptibility = interruptibility_old; | |
2459 | ||
2460 | interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); | |
2461 | ||
48005f64 | 2462 | if (mask & KVM_X86_SHADOW_INT_MOV_SS) |
2809f5d2 | 2463 | interruptibility |= GUEST_INTR_STATE_MOV_SS; |
48005f64 | 2464 | else if (mask & KVM_X86_SHADOW_INT_STI) |
2809f5d2 GC |
2465 | interruptibility |= GUEST_INTR_STATE_STI; |
2466 | ||
2467 | if ((interruptibility != interruptibility_old)) | |
2468 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); | |
2469 | } | |
2470 | ||
6aa8b732 AK |
2471 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
2472 | { | |
2473 | unsigned long rip; | |
6aa8b732 | 2474 | |
5fdbf976 | 2475 | rip = kvm_rip_read(vcpu); |
6aa8b732 | 2476 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
5fdbf976 | 2477 | kvm_rip_write(vcpu, rip); |
6aa8b732 | 2478 | |
2809f5d2 GC |
2479 | /* skipping an emulated instruction also counts */ |
2480 | vmx_set_interrupt_shadow(vcpu, 0); | |
6aa8b732 AK |
2481 | } |
2482 | ||
0b6ac343 NHE |
2483 | /* |
2484 | * KVM wants to inject page-faults which it got to the guest. This function | |
2485 | * checks whether in a nested guest, we need to inject them to L1 or L2. | |
0b6ac343 | 2486 | */ |
e011c663 | 2487 | static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr) |
0b6ac343 NHE |
2488 | { |
2489 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
2490 | ||
e011c663 | 2491 | if (!(vmcs12->exception_bitmap & (1u << nr))) |
0b6ac343 NHE |
2492 | return 0; |
2493 | ||
533558bc JK |
2494 | nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason, |
2495 | vmcs_read32(VM_EXIT_INTR_INFO), | |
2496 | vmcs_readl(EXIT_QUALIFICATION)); | |
0b6ac343 NHE |
2497 | return 1; |
2498 | } | |
2499 | ||
298101da | 2500 | static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
2501 | bool has_error_code, u32 error_code, |
2502 | bool reinject) | |
298101da | 2503 | { |
77ab6db0 | 2504 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8ab2d2e2 | 2505 | u32 intr_info = nr | INTR_INFO_VALID_MASK; |
77ab6db0 | 2506 | |
e011c663 GN |
2507 | if (!reinject && is_guest_mode(vcpu) && |
2508 | nested_vmx_check_exception(vcpu, nr)) | |
0b6ac343 NHE |
2509 | return; |
2510 | ||
8ab2d2e2 | 2511 | if (has_error_code) { |
77ab6db0 | 2512 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); |
8ab2d2e2 JK |
2513 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; |
2514 | } | |
77ab6db0 | 2515 | |
7ffd92c5 | 2516 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
2517 | int inc_eip = 0; |
2518 | if (kvm_exception_is_soft(nr)) | |
2519 | inc_eip = vcpu->arch.event_exit_inst_len; | |
2520 | if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE) | |
a92601bb | 2521 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
77ab6db0 JK |
2522 | return; |
2523 | } | |
2524 | ||
66fd3f7f GN |
2525 | if (kvm_exception_is_soft(nr)) { |
2526 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
2527 | vmx->vcpu.arch.event_exit_inst_len); | |
8ab2d2e2 JK |
2528 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; |
2529 | } else | |
2530 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
2531 | ||
2532 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | |
298101da AK |
2533 | } |
2534 | ||
4e47c7a6 SY |
2535 | static bool vmx_rdtscp_supported(void) |
2536 | { | |
2537 | return cpu_has_vmx_rdtscp(); | |
2538 | } | |
2539 | ||
ad756a16 MJ |
2540 | static bool vmx_invpcid_supported(void) |
2541 | { | |
2542 | return cpu_has_vmx_invpcid() && enable_ept; | |
2543 | } | |
2544 | ||
a75beee6 ED |
2545 | /* |
2546 | * Swap MSR entry in host/guest MSR entry array. | |
2547 | */ | |
8b9cf98c | 2548 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 2549 | { |
26bb0981 | 2550 | struct shared_msr_entry tmp; |
a2fa3e9f GH |
2551 | |
2552 | tmp = vmx->guest_msrs[to]; | |
2553 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
2554 | vmx->guest_msrs[from] = tmp; | |
a75beee6 ED |
2555 | } |
2556 | ||
8d14695f YZ |
2557 | static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu) |
2558 | { | |
2559 | unsigned long *msr_bitmap; | |
2560 | ||
670125bd | 2561 | if (is_guest_mode(vcpu)) |
d048c098 | 2562 | msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap; |
3ce424e4 RK |
2563 | else if (cpu_has_secondary_exec_ctrls() && |
2564 | (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) & | |
2565 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { | |
f6e90f9e WL |
2566 | if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) { |
2567 | if (is_long_mode(vcpu)) | |
c63e4563 | 2568 | msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv; |
f6e90f9e | 2569 | else |
c63e4563 | 2570 | msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv; |
f6e90f9e WL |
2571 | } else { |
2572 | if (is_long_mode(vcpu)) | |
c63e4563 | 2573 | msr_bitmap = vmx_msr_bitmap_longmode_x2apic; |
f6e90f9e | 2574 | else |
c63e4563 | 2575 | msr_bitmap = vmx_msr_bitmap_legacy_x2apic; |
f6e90f9e | 2576 | } |
8d14695f YZ |
2577 | } else { |
2578 | if (is_long_mode(vcpu)) | |
2579 | msr_bitmap = vmx_msr_bitmap_longmode; | |
2580 | else | |
2581 | msr_bitmap = vmx_msr_bitmap_legacy; | |
2582 | } | |
2583 | ||
2584 | vmcs_write64(MSR_BITMAP, __pa(msr_bitmap)); | |
2585 | } | |
2586 | ||
e38aea3e AK |
2587 | /* |
2588 | * Set up the vmcs to automatically save and restore system | |
2589 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
2590 | * mode, as fiddling with msrs is very expensive. | |
2591 | */ | |
8b9cf98c | 2592 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 2593 | { |
26bb0981 | 2594 | int save_nmsrs, index; |
e38aea3e | 2595 | |
a75beee6 ED |
2596 | save_nmsrs = 0; |
2597 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 2598 | if (is_long_mode(&vmx->vcpu)) { |
8b9cf98c | 2599 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 2600 | if (index >= 0) |
8b9cf98c RR |
2601 | move_msr_up(vmx, index, save_nmsrs++); |
2602 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 2603 | if (index >= 0) |
8b9cf98c RR |
2604 | move_msr_up(vmx, index, save_nmsrs++); |
2605 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 2606 | if (index >= 0) |
8b9cf98c | 2607 | move_msr_up(vmx, index, save_nmsrs++); |
4e47c7a6 | 2608 | index = __find_msr_index(vmx, MSR_TSC_AUX); |
1cea0ce6 | 2609 | if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu)) |
4e47c7a6 | 2610 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 | 2611 | /* |
8c06585d | 2612 | * MSR_STAR is only needed on long mode guests, and only |
a75beee6 ED |
2613 | * if efer.sce is enabled. |
2614 | */ | |
8c06585d | 2615 | index = __find_msr_index(vmx, MSR_STAR); |
f6801dff | 2616 | if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE)) |
8b9cf98c | 2617 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
2618 | } |
2619 | #endif | |
92c0d900 AK |
2620 | index = __find_msr_index(vmx, MSR_EFER); |
2621 | if (index >= 0 && update_transition_efer(vmx, index)) | |
26bb0981 | 2622 | move_msr_up(vmx, index, save_nmsrs++); |
e38aea3e | 2623 | |
26bb0981 | 2624 | vmx->save_nmsrs = save_nmsrs; |
5897297b | 2625 | |
8d14695f YZ |
2626 | if (cpu_has_vmx_msr_bitmap()) |
2627 | vmx_set_msr_bitmap(&vmx->vcpu); | |
e38aea3e AK |
2628 | } |
2629 | ||
6aa8b732 AK |
2630 | /* |
2631 | * reads and returns guest's timestamp counter "register" | |
be7b263e HZ |
2632 | * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset |
2633 | * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3 | |
6aa8b732 | 2634 | */ |
be7b263e | 2635 | static u64 guest_read_tsc(struct kvm_vcpu *vcpu) |
6aa8b732 AK |
2636 | { |
2637 | u64 host_tsc, tsc_offset; | |
2638 | ||
4ea1636b | 2639 | host_tsc = rdtsc(); |
6aa8b732 | 2640 | tsc_offset = vmcs_read64(TSC_OFFSET); |
be7b263e | 2641 | return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset; |
6aa8b732 AK |
2642 | } |
2643 | ||
2644 | /* | |
99e3e30a | 2645 | * writes 'offset' into guest's timestamp counter offset register |
6aa8b732 | 2646 | */ |
99e3e30a | 2647 | static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
6aa8b732 | 2648 | { |
27fc51b2 | 2649 | if (is_guest_mode(vcpu)) { |
7991825b | 2650 | /* |
27fc51b2 NHE |
2651 | * We're here if L1 chose not to trap WRMSR to TSC. According |
2652 | * to the spec, this should set L1's TSC; The offset that L1 | |
2653 | * set for L2 remains unchanged, and still needs to be added | |
2654 | * to the newly set TSC to get L2's TSC. | |
7991825b | 2655 | */ |
27fc51b2 | 2656 | struct vmcs12 *vmcs12; |
27fc51b2 NHE |
2657 | /* recalculate vmcs02.TSC_OFFSET: */ |
2658 | vmcs12 = get_vmcs12(vcpu); | |
2659 | vmcs_write64(TSC_OFFSET, offset + | |
2660 | (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ? | |
2661 | vmcs12->tsc_offset : 0)); | |
2662 | } else { | |
489223ed YY |
2663 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, |
2664 | vmcs_read64(TSC_OFFSET), offset); | |
27fc51b2 NHE |
2665 | vmcs_write64(TSC_OFFSET, offset); |
2666 | } | |
6aa8b732 AK |
2667 | } |
2668 | ||
801d3424 NHE |
2669 | static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu) |
2670 | { | |
2671 | struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0); | |
2672 | return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31))); | |
2673 | } | |
2674 | ||
2675 | /* | |
2676 | * nested_vmx_allowed() checks whether a guest should be allowed to use VMX | |
2677 | * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for | |
2678 | * all guests if the "nested" module option is off, and can also be disabled | |
2679 | * for a single guest by disabling its VMX cpuid bit. | |
2680 | */ | |
2681 | static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu) | |
2682 | { | |
2683 | return nested && guest_cpuid_has_vmx(vcpu); | |
2684 | } | |
2685 | ||
b87a51ae NHE |
2686 | /* |
2687 | * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be | |
2688 | * returned for the various VMX controls MSRs when nested VMX is enabled. | |
2689 | * The same values should also be used to verify that vmcs12 control fields are | |
2690 | * valid during nested entry from L1 to L2. | |
2691 | * Each of these control msrs has a low and high 32-bit half: A low bit is on | |
2692 | * if the corresponding bit in the (32-bit) control field *must* be on, and a | |
2693 | * bit in the high half is on if the corresponding bit in the control field | |
2694 | * may be on. See also vmx_control_verify(). | |
b87a51ae | 2695 | */ |
b9c237bb | 2696 | static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx) |
b87a51ae NHE |
2697 | { |
2698 | /* | |
2699 | * Note that as a general rule, the high half of the MSRs (bits in | |
2700 | * the control fields which may be 1) should be initialized by the | |
2701 | * intersection of the underlying hardware's MSR (i.e., features which | |
2702 | * can be supported) and the list of features we want to expose - | |
2703 | * because they are known to be properly supported in our code. | |
2704 | * Also, usually, the low half of the MSRs (bits which must be 1) can | |
2705 | * be set to 0, meaning that L1 may turn off any of these bits. The | |
2706 | * reason is that if one of these bits is necessary, it will appear | |
2707 | * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control | |
2708 | * fields of vmcs01 and vmcs02, will turn these bits off - and | |
2709 | * nested_vmx_exit_handled() will not pass related exits to L1. | |
2710 | * These rules have exceptions below. | |
2711 | */ | |
2712 | ||
2713 | /* pin-based controls */ | |
eabeaacc | 2714 | rdmsr(MSR_IA32_VMX_PINBASED_CTLS, |
b9c237bb WV |
2715 | vmx->nested.nested_vmx_pinbased_ctls_low, |
2716 | vmx->nested.nested_vmx_pinbased_ctls_high); | |
2717 | vmx->nested.nested_vmx_pinbased_ctls_low |= | |
2718 | PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
2719 | vmx->nested.nested_vmx_pinbased_ctls_high &= | |
2720 | PIN_BASED_EXT_INTR_MASK | | |
2721 | PIN_BASED_NMI_EXITING | | |
2722 | PIN_BASED_VIRTUAL_NMIS; | |
2723 | vmx->nested.nested_vmx_pinbased_ctls_high |= | |
2724 | PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR | | |
0238ea91 | 2725 | PIN_BASED_VMX_PREEMPTION_TIMER; |
d62caabb | 2726 | if (kvm_vcpu_apicv_active(&vmx->vcpu)) |
705699a1 WV |
2727 | vmx->nested.nested_vmx_pinbased_ctls_high |= |
2728 | PIN_BASED_POSTED_INTR; | |
b87a51ae | 2729 | |
3dbcd8da | 2730 | /* exit controls */ |
c0dfee58 | 2731 | rdmsr(MSR_IA32_VMX_EXIT_CTLS, |
b9c237bb WV |
2732 | vmx->nested.nested_vmx_exit_ctls_low, |
2733 | vmx->nested.nested_vmx_exit_ctls_high); | |
2734 | vmx->nested.nested_vmx_exit_ctls_low = | |
2735 | VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; | |
e0ba1a6f | 2736 | |
b9c237bb | 2737 | vmx->nested.nested_vmx_exit_ctls_high &= |
b87a51ae | 2738 | #ifdef CONFIG_X86_64 |
c0dfee58 | 2739 | VM_EXIT_HOST_ADDR_SPACE_SIZE | |
b87a51ae | 2740 | #endif |
f4124500 | 2741 | VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT; |
b9c237bb WV |
2742 | vmx->nested.nested_vmx_exit_ctls_high |= |
2743 | VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR | | |
f4124500 | 2744 | VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER | |
e0ba1a6f BD |
2745 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT; |
2746 | ||
a87036ad | 2747 | if (kvm_mpx_supported()) |
b9c237bb | 2748 | vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; |
b87a51ae | 2749 | |
2996fca0 | 2750 | /* We support free control of debug control saving. */ |
0115f9cb | 2751 | vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS; |
2996fca0 | 2752 | |
b87a51ae NHE |
2753 | /* entry controls */ |
2754 | rdmsr(MSR_IA32_VMX_ENTRY_CTLS, | |
b9c237bb WV |
2755 | vmx->nested.nested_vmx_entry_ctls_low, |
2756 | vmx->nested.nested_vmx_entry_ctls_high); | |
2757 | vmx->nested.nested_vmx_entry_ctls_low = | |
2758 | VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; | |
2759 | vmx->nested.nested_vmx_entry_ctls_high &= | |
57435349 JK |
2760 | #ifdef CONFIG_X86_64 |
2761 | VM_ENTRY_IA32E_MODE | | |
2762 | #endif | |
2763 | VM_ENTRY_LOAD_IA32_PAT; | |
b9c237bb WV |
2764 | vmx->nested.nested_vmx_entry_ctls_high |= |
2765 | (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER); | |
a87036ad | 2766 | if (kvm_mpx_supported()) |
b9c237bb | 2767 | vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; |
57435349 | 2768 | |
2996fca0 | 2769 | /* We support free control of debug control loading. */ |
0115f9cb | 2770 | vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS; |
2996fca0 | 2771 | |
b87a51ae NHE |
2772 | /* cpu-based controls */ |
2773 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, | |
b9c237bb WV |
2774 | vmx->nested.nested_vmx_procbased_ctls_low, |
2775 | vmx->nested.nested_vmx_procbased_ctls_high); | |
2776 | vmx->nested.nested_vmx_procbased_ctls_low = | |
2777 | CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
2778 | vmx->nested.nested_vmx_procbased_ctls_high &= | |
a294c9bb JK |
2779 | CPU_BASED_VIRTUAL_INTR_PENDING | |
2780 | CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING | | |
b87a51ae NHE |
2781 | CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING | |
2782 | CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING | | |
2783 | CPU_BASED_CR3_STORE_EXITING | | |
2784 | #ifdef CONFIG_X86_64 | |
2785 | CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING | | |
2786 | #endif | |
2787 | CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING | | |
5f3d45e7 MD |
2788 | CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG | |
2789 | CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING | | |
2790 | CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING | | |
2791 | CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
b87a51ae NHE |
2792 | /* |
2793 | * We can allow some features even when not supported by the | |
2794 | * hardware. For example, L1 can specify an MSR bitmap - and we | |
2795 | * can use it to avoid exits to L1 - even when L0 runs L2 | |
2796 | * without MSR bitmaps. | |
2797 | */ | |
b9c237bb WV |
2798 | vmx->nested.nested_vmx_procbased_ctls_high |= |
2799 | CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR | | |
560b7ee1 | 2800 | CPU_BASED_USE_MSR_BITMAPS; |
b87a51ae | 2801 | |
3dcdf3ec | 2802 | /* We support free control of CR3 access interception. */ |
0115f9cb | 2803 | vmx->nested.nested_vmx_procbased_ctls_low &= |
3dcdf3ec JK |
2804 | ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING); |
2805 | ||
b87a51ae NHE |
2806 | /* secondary cpu-based controls */ |
2807 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, | |
b9c237bb WV |
2808 | vmx->nested.nested_vmx_secondary_ctls_low, |
2809 | vmx->nested.nested_vmx_secondary_ctls_high); | |
2810 | vmx->nested.nested_vmx_secondary_ctls_low = 0; | |
2811 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
d6851fbe | 2812 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
b3a2a907 | 2813 | SECONDARY_EXEC_RDTSCP | |
1b07304c | 2814 | SECONDARY_EXEC_DESC | |
f2b93280 | 2815 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
5c614b35 | 2816 | SECONDARY_EXEC_ENABLE_VPID | |
82f0dd4b | 2817 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
608406e2 | 2818 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
81dc01f7 | 2819 | SECONDARY_EXEC_WBINVD_EXITING | |
dfa169bb | 2820 | SECONDARY_EXEC_XSAVES; |
c18911a2 | 2821 | |
afa61f75 NHE |
2822 | if (enable_ept) { |
2823 | /* nested EPT: emulate EPT also to L1 */ | |
b9c237bb | 2824 | vmx->nested.nested_vmx_secondary_ctls_high |= |
0790ec17 | 2825 | SECONDARY_EXEC_ENABLE_EPT; |
b9c237bb | 2826 | vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT | |
d3134dbf JK |
2827 | VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT | |
2828 | VMX_EPT_INVEPT_BIT; | |
02120c45 BD |
2829 | if (cpu_has_vmx_ept_execute_only()) |
2830 | vmx->nested.nested_vmx_ept_caps |= | |
2831 | VMX_EPT_EXECUTE_ONLY_BIT; | |
b9c237bb | 2832 | vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept; |
45e11817 BD |
2833 | vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT | |
2834 | VMX_EPT_EXTENT_CONTEXT_BIT; | |
afa61f75 | 2835 | } else |
b9c237bb | 2836 | vmx->nested.nested_vmx_ept_caps = 0; |
afa61f75 | 2837 | |
ef697a71 PB |
2838 | /* |
2839 | * Old versions of KVM use the single-context version without | |
2840 | * checking for support, so declare that it is supported even | |
2841 | * though it is treated as global context. The alternative is | |
2842 | * not failing the single-context invvpid, and it is worse. | |
2843 | */ | |
089d7b6e WL |
2844 | if (enable_vpid) |
2845 | vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT | | |
bcdde302 | 2846 | VMX_VPID_EXTENT_SUPPORTED_MASK; |
089d7b6e WL |
2847 | else |
2848 | vmx->nested.nested_vmx_vpid_caps = 0; | |
99b83ac8 | 2849 | |
0790ec17 RK |
2850 | if (enable_unrestricted_guest) |
2851 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
2852 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
2853 | ||
c18911a2 | 2854 | /* miscellaneous data */ |
b9c237bb WV |
2855 | rdmsr(MSR_IA32_VMX_MISC, |
2856 | vmx->nested.nested_vmx_misc_low, | |
2857 | vmx->nested.nested_vmx_misc_high); | |
2858 | vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA; | |
2859 | vmx->nested.nested_vmx_misc_low |= | |
2860 | VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE | | |
f4124500 | 2861 | VMX_MISC_ACTIVITY_HLT; |
b9c237bb | 2862 | vmx->nested.nested_vmx_misc_high = 0; |
62cc6b9d DM |
2863 | |
2864 | /* | |
2865 | * This MSR reports some information about VMX support. We | |
2866 | * should return information about the VMX we emulate for the | |
2867 | * guest, and the VMCS structure we give it - not about the | |
2868 | * VMX support of the underlying hardware. | |
2869 | */ | |
2870 | vmx->nested.nested_vmx_basic = | |
2871 | VMCS12_REVISION | | |
2872 | VMX_BASIC_TRUE_CTLS | | |
2873 | ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) | | |
2874 | (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT); | |
2875 | ||
2876 | if (cpu_has_vmx_basic_inout()) | |
2877 | vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT; | |
2878 | ||
2879 | /* | |
8322ebbb | 2880 | * These MSRs specify bits which the guest must keep fixed on |
62cc6b9d DM |
2881 | * while L1 is in VMXON mode (in L1's root mode, or running an L2). |
2882 | * We picked the standard core2 setting. | |
2883 | */ | |
2884 | #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE) | |
2885 | #define VMXON_CR4_ALWAYSON X86_CR4_VMXE | |
2886 | vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON; | |
62cc6b9d | 2887 | vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON; |
8322ebbb DM |
2888 | |
2889 | /* These MSRs specify bits which the guest must keep fixed off. */ | |
2890 | rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1); | |
2891 | rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1); | |
62cc6b9d DM |
2892 | |
2893 | /* highest index: VMX_PREEMPTION_TIMER_VALUE */ | |
2894 | vmx->nested.nested_vmx_vmcs_enum = 0x2e; | |
b87a51ae NHE |
2895 | } |
2896 | ||
3899152c DM |
2897 | /* |
2898 | * if fixed0[i] == 1: val[i] must be 1 | |
2899 | * if fixed1[i] == 0: val[i] must be 0 | |
2900 | */ | |
2901 | static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1) | |
2902 | { | |
2903 | return ((val & fixed1) | fixed0) == val; | |
2904 | } | |
2905 | ||
b87a51ae NHE |
2906 | static inline bool vmx_control_verify(u32 control, u32 low, u32 high) |
2907 | { | |
3899152c | 2908 | return fixed_bits_valid(control, low, high); |
b87a51ae NHE |
2909 | } |
2910 | ||
2911 | static inline u64 vmx_control_msr(u32 low, u32 high) | |
2912 | { | |
2913 | return low | ((u64)high << 32); | |
2914 | } | |
2915 | ||
62cc6b9d DM |
2916 | static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask) |
2917 | { | |
2918 | superset &= mask; | |
2919 | subset &= mask; | |
2920 | ||
2921 | return (superset | subset) == superset; | |
2922 | } | |
2923 | ||
2924 | static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data) | |
2925 | { | |
2926 | const u64 feature_and_reserved = | |
2927 | /* feature (except bit 48; see below) */ | |
2928 | BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) | | |
2929 | /* reserved */ | |
2930 | BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56); | |
2931 | u64 vmx_basic = vmx->nested.nested_vmx_basic; | |
2932 | ||
2933 | if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved)) | |
2934 | return -EINVAL; | |
2935 | ||
2936 | /* | |
2937 | * KVM does not emulate a version of VMX that constrains physical | |
2938 | * addresses of VMX structures (e.g. VMCS) to 32-bits. | |
2939 | */ | |
2940 | if (data & BIT_ULL(48)) | |
2941 | return -EINVAL; | |
2942 | ||
2943 | if (vmx_basic_vmcs_revision_id(vmx_basic) != | |
2944 | vmx_basic_vmcs_revision_id(data)) | |
2945 | return -EINVAL; | |
2946 | ||
2947 | if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data)) | |
2948 | return -EINVAL; | |
2949 | ||
2950 | vmx->nested.nested_vmx_basic = data; | |
2951 | return 0; | |
2952 | } | |
2953 | ||
2954 | static int | |
2955 | vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) | |
2956 | { | |
2957 | u64 supported; | |
2958 | u32 *lowp, *highp; | |
2959 | ||
2960 | switch (msr_index) { | |
2961 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
2962 | lowp = &vmx->nested.nested_vmx_pinbased_ctls_low; | |
2963 | highp = &vmx->nested.nested_vmx_pinbased_ctls_high; | |
2964 | break; | |
2965 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
2966 | lowp = &vmx->nested.nested_vmx_procbased_ctls_low; | |
2967 | highp = &vmx->nested.nested_vmx_procbased_ctls_high; | |
2968 | break; | |
2969 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
2970 | lowp = &vmx->nested.nested_vmx_exit_ctls_low; | |
2971 | highp = &vmx->nested.nested_vmx_exit_ctls_high; | |
2972 | break; | |
2973 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
2974 | lowp = &vmx->nested.nested_vmx_entry_ctls_low; | |
2975 | highp = &vmx->nested.nested_vmx_entry_ctls_high; | |
2976 | break; | |
2977 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
2978 | lowp = &vmx->nested.nested_vmx_secondary_ctls_low; | |
2979 | highp = &vmx->nested.nested_vmx_secondary_ctls_high; | |
2980 | break; | |
2981 | default: | |
2982 | BUG(); | |
2983 | } | |
2984 | ||
2985 | supported = vmx_control_msr(*lowp, *highp); | |
2986 | ||
2987 | /* Check must-be-1 bits are still 1. */ | |
2988 | if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0))) | |
2989 | return -EINVAL; | |
2990 | ||
2991 | /* Check must-be-0 bits are still 0. */ | |
2992 | if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32))) | |
2993 | return -EINVAL; | |
2994 | ||
2995 | *lowp = data; | |
2996 | *highp = data >> 32; | |
2997 | return 0; | |
2998 | } | |
2999 | ||
3000 | static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data) | |
3001 | { | |
3002 | const u64 feature_and_reserved_bits = | |
3003 | /* feature */ | |
3004 | BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) | | |
3005 | BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) | | |
3006 | /* reserved */ | |
3007 | GENMASK_ULL(13, 9) | BIT_ULL(31); | |
3008 | u64 vmx_misc; | |
3009 | ||
3010 | vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low, | |
3011 | vmx->nested.nested_vmx_misc_high); | |
3012 | ||
3013 | if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits)) | |
3014 | return -EINVAL; | |
3015 | ||
3016 | if ((vmx->nested.nested_vmx_pinbased_ctls_high & | |
3017 | PIN_BASED_VMX_PREEMPTION_TIMER) && | |
3018 | vmx_misc_preemption_timer_rate(data) != | |
3019 | vmx_misc_preemption_timer_rate(vmx_misc)) | |
3020 | return -EINVAL; | |
3021 | ||
3022 | if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc)) | |
3023 | return -EINVAL; | |
3024 | ||
3025 | if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc)) | |
3026 | return -EINVAL; | |
3027 | ||
3028 | if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc)) | |
3029 | return -EINVAL; | |
3030 | ||
3031 | vmx->nested.nested_vmx_misc_low = data; | |
3032 | vmx->nested.nested_vmx_misc_high = data >> 32; | |
3033 | return 0; | |
3034 | } | |
3035 | ||
3036 | static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data) | |
3037 | { | |
3038 | u64 vmx_ept_vpid_cap; | |
3039 | ||
3040 | vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps, | |
3041 | vmx->nested.nested_vmx_vpid_caps); | |
3042 | ||
3043 | /* Every bit is either reserved or a feature bit. */ | |
3044 | if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL)) | |
3045 | return -EINVAL; | |
3046 | ||
3047 | vmx->nested.nested_vmx_ept_caps = data; | |
3048 | vmx->nested.nested_vmx_vpid_caps = data >> 32; | |
3049 | return 0; | |
3050 | } | |
3051 | ||
3052 | static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) | |
3053 | { | |
3054 | u64 *msr; | |
3055 | ||
3056 | switch (msr_index) { | |
3057 | case MSR_IA32_VMX_CR0_FIXED0: | |
3058 | msr = &vmx->nested.nested_vmx_cr0_fixed0; | |
3059 | break; | |
3060 | case MSR_IA32_VMX_CR4_FIXED0: | |
3061 | msr = &vmx->nested.nested_vmx_cr4_fixed0; | |
3062 | break; | |
3063 | default: | |
3064 | BUG(); | |
3065 | } | |
3066 | ||
3067 | /* | |
3068 | * 1 bits (which indicates bits which "must-be-1" during VMX operation) | |
3069 | * must be 1 in the restored value. | |
3070 | */ | |
3071 | if (!is_bitwise_subset(data, *msr, -1ULL)) | |
3072 | return -EINVAL; | |
3073 | ||
3074 | *msr = data; | |
3075 | return 0; | |
3076 | } | |
3077 | ||
3078 | /* | |
3079 | * Called when userspace is restoring VMX MSRs. | |
3080 | * | |
3081 | * Returns 0 on success, non-0 otherwise. | |
3082 | */ | |
3083 | static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
b87a51ae | 3084 | { |
b9c237bb WV |
3085 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3086 | ||
b87a51ae | 3087 | switch (msr_index) { |
b87a51ae | 3088 | case MSR_IA32_VMX_BASIC: |
62cc6b9d DM |
3089 | return vmx_restore_vmx_basic(vmx, data); |
3090 | case MSR_IA32_VMX_PINBASED_CTLS: | |
3091 | case MSR_IA32_VMX_PROCBASED_CTLS: | |
3092 | case MSR_IA32_VMX_EXIT_CTLS: | |
3093 | case MSR_IA32_VMX_ENTRY_CTLS: | |
b87a51ae | 3094 | /* |
62cc6b9d DM |
3095 | * The "non-true" VMX capability MSRs are generated from the |
3096 | * "true" MSRs, so we do not support restoring them directly. | |
3097 | * | |
3098 | * If userspace wants to emulate VMX_BASIC[55]=0, userspace | |
3099 | * should restore the "true" MSRs with the must-be-1 bits | |
3100 | * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND | |
3101 | * DEFAULT SETTINGS". | |
b87a51ae | 3102 | */ |
62cc6b9d DM |
3103 | return -EINVAL; |
3104 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
3105 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
3106 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
3107 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
3108 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
3109 | return vmx_restore_control_msr(vmx, msr_index, data); | |
3110 | case MSR_IA32_VMX_MISC: | |
3111 | return vmx_restore_vmx_misc(vmx, data); | |
3112 | case MSR_IA32_VMX_CR0_FIXED0: | |
3113 | case MSR_IA32_VMX_CR4_FIXED0: | |
3114 | return vmx_restore_fixed0_msr(vmx, msr_index, data); | |
3115 | case MSR_IA32_VMX_CR0_FIXED1: | |
3116 | case MSR_IA32_VMX_CR4_FIXED1: | |
3117 | /* | |
3118 | * These MSRs are generated based on the vCPU's CPUID, so we | |
3119 | * do not support restoring them directly. | |
3120 | */ | |
3121 | return -EINVAL; | |
3122 | case MSR_IA32_VMX_EPT_VPID_CAP: | |
3123 | return vmx_restore_vmx_ept_vpid_cap(vmx, data); | |
3124 | case MSR_IA32_VMX_VMCS_ENUM: | |
3125 | vmx->nested.nested_vmx_vmcs_enum = data; | |
3126 | return 0; | |
3127 | default: | |
3128 | /* | |
3129 | * The rest of the VMX capability MSRs do not support restore. | |
3130 | */ | |
3131 | return -EINVAL; | |
3132 | } | |
3133 | } | |
3134 | ||
3135 | /* Returns 0 on success, non-0 otherwise. */ | |
3136 | static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
3137 | { | |
3138 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
3139 | ||
3140 | switch (msr_index) { | |
3141 | case MSR_IA32_VMX_BASIC: | |
3142 | *pdata = vmx->nested.nested_vmx_basic; | |
b87a51ae NHE |
3143 | break; |
3144 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
3145 | case MSR_IA32_VMX_PINBASED_CTLS: | |
b9c237bb WV |
3146 | *pdata = vmx_control_msr( |
3147 | vmx->nested.nested_vmx_pinbased_ctls_low, | |
3148 | vmx->nested.nested_vmx_pinbased_ctls_high); | |
0115f9cb DM |
3149 | if (msr_index == MSR_IA32_VMX_PINBASED_CTLS) |
3150 | *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3151 | break; |
3152 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
3153 | case MSR_IA32_VMX_PROCBASED_CTLS: | |
b9c237bb WV |
3154 | *pdata = vmx_control_msr( |
3155 | vmx->nested.nested_vmx_procbased_ctls_low, | |
3156 | vmx->nested.nested_vmx_procbased_ctls_high); | |
0115f9cb DM |
3157 | if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS) |
3158 | *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3159 | break; |
3160 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
3161 | case MSR_IA32_VMX_EXIT_CTLS: | |
b9c237bb WV |
3162 | *pdata = vmx_control_msr( |
3163 | vmx->nested.nested_vmx_exit_ctls_low, | |
3164 | vmx->nested.nested_vmx_exit_ctls_high); | |
0115f9cb DM |
3165 | if (msr_index == MSR_IA32_VMX_EXIT_CTLS) |
3166 | *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3167 | break; |
3168 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
3169 | case MSR_IA32_VMX_ENTRY_CTLS: | |
b9c237bb WV |
3170 | *pdata = vmx_control_msr( |
3171 | vmx->nested.nested_vmx_entry_ctls_low, | |
3172 | vmx->nested.nested_vmx_entry_ctls_high); | |
0115f9cb DM |
3173 | if (msr_index == MSR_IA32_VMX_ENTRY_CTLS) |
3174 | *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3175 | break; |
3176 | case MSR_IA32_VMX_MISC: | |
b9c237bb WV |
3177 | *pdata = vmx_control_msr( |
3178 | vmx->nested.nested_vmx_misc_low, | |
3179 | vmx->nested.nested_vmx_misc_high); | |
b87a51ae | 3180 | break; |
b87a51ae | 3181 | case MSR_IA32_VMX_CR0_FIXED0: |
62cc6b9d | 3182 | *pdata = vmx->nested.nested_vmx_cr0_fixed0; |
b87a51ae NHE |
3183 | break; |
3184 | case MSR_IA32_VMX_CR0_FIXED1: | |
62cc6b9d | 3185 | *pdata = vmx->nested.nested_vmx_cr0_fixed1; |
b87a51ae NHE |
3186 | break; |
3187 | case MSR_IA32_VMX_CR4_FIXED0: | |
62cc6b9d | 3188 | *pdata = vmx->nested.nested_vmx_cr4_fixed0; |
b87a51ae NHE |
3189 | break; |
3190 | case MSR_IA32_VMX_CR4_FIXED1: | |
62cc6b9d | 3191 | *pdata = vmx->nested.nested_vmx_cr4_fixed1; |
b87a51ae NHE |
3192 | break; |
3193 | case MSR_IA32_VMX_VMCS_ENUM: | |
62cc6b9d | 3194 | *pdata = vmx->nested.nested_vmx_vmcs_enum; |
b87a51ae NHE |
3195 | break; |
3196 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
b9c237bb WV |
3197 | *pdata = vmx_control_msr( |
3198 | vmx->nested.nested_vmx_secondary_ctls_low, | |
3199 | vmx->nested.nested_vmx_secondary_ctls_high); | |
b87a51ae NHE |
3200 | break; |
3201 | case MSR_IA32_VMX_EPT_VPID_CAP: | |
089d7b6e WL |
3202 | *pdata = vmx->nested.nested_vmx_ept_caps | |
3203 | ((u64)vmx->nested.nested_vmx_vpid_caps << 32); | |
b87a51ae NHE |
3204 | break; |
3205 | default: | |
b87a51ae | 3206 | return 1; |
b3897a49 NHE |
3207 | } |
3208 | ||
b87a51ae NHE |
3209 | return 0; |
3210 | } | |
3211 | ||
37e4c997 HZ |
3212 | static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, |
3213 | uint64_t val) | |
3214 | { | |
3215 | uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; | |
3216 | ||
3217 | return !(val & ~valid_bits); | |
3218 | } | |
3219 | ||
6aa8b732 AK |
3220 | /* |
3221 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
3222 | * Returns 0 on success, non-0 otherwise. | |
3223 | * Assumes vcpu_load() was already called. | |
3224 | */ | |
609e36d3 | 3225 | static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3226 | { |
26bb0981 | 3227 | struct shared_msr_entry *msr; |
6aa8b732 | 3228 | |
609e36d3 | 3229 | switch (msr_info->index) { |
05b3e0c2 | 3230 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3231 | case MSR_FS_BASE: |
609e36d3 | 3232 | msr_info->data = vmcs_readl(GUEST_FS_BASE); |
6aa8b732 AK |
3233 | break; |
3234 | case MSR_GS_BASE: | |
609e36d3 | 3235 | msr_info->data = vmcs_readl(GUEST_GS_BASE); |
6aa8b732 | 3236 | break; |
44ea2b17 AK |
3237 | case MSR_KERNEL_GS_BASE: |
3238 | vmx_load_host_state(to_vmx(vcpu)); | |
609e36d3 | 3239 | msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base; |
44ea2b17 | 3240 | break; |
26bb0981 | 3241 | #endif |
6aa8b732 | 3242 | case MSR_EFER: |
609e36d3 | 3243 | return kvm_get_msr_common(vcpu, msr_info); |
af24a4e4 | 3244 | case MSR_IA32_TSC: |
be7b263e | 3245 | msr_info->data = guest_read_tsc(vcpu); |
6aa8b732 AK |
3246 | break; |
3247 | case MSR_IA32_SYSENTER_CS: | |
609e36d3 | 3248 | msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); |
6aa8b732 AK |
3249 | break; |
3250 | case MSR_IA32_SYSENTER_EIP: | |
609e36d3 | 3251 | msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
3252 | break; |
3253 | case MSR_IA32_SYSENTER_ESP: | |
609e36d3 | 3254 | msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 3255 | break; |
0dd376e7 | 3256 | case MSR_IA32_BNDCFGS: |
a87036ad | 3257 | if (!kvm_mpx_supported()) |
93c4adc7 | 3258 | return 1; |
609e36d3 | 3259 | msr_info->data = vmcs_read64(GUEST_BNDCFGS); |
0dd376e7 | 3260 | break; |
c45dcc71 AR |
3261 | case MSR_IA32_MCG_EXT_CTL: |
3262 | if (!msr_info->host_initiated && | |
3263 | !(to_vmx(vcpu)->msr_ia32_feature_control & | |
3264 | FEATURE_CONTROL_LMCE)) | |
cae50139 | 3265 | return 1; |
c45dcc71 AR |
3266 | msr_info->data = vcpu->arch.mcg_ext_ctl; |
3267 | break; | |
cae50139 | 3268 | case MSR_IA32_FEATURE_CONTROL: |
3b84080b | 3269 | msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control; |
cae50139 JK |
3270 | break; |
3271 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
3272 | if (!nested_vmx_allowed(vcpu)) | |
3273 | return 1; | |
609e36d3 | 3274 | return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data); |
20300099 WL |
3275 | case MSR_IA32_XSS: |
3276 | if (!vmx_xsaves_supported()) | |
3277 | return 1; | |
609e36d3 | 3278 | msr_info->data = vcpu->arch.ia32_xss; |
20300099 | 3279 | break; |
4e47c7a6 | 3280 | case MSR_TSC_AUX: |
81b1b9ca | 3281 | if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated) |
4e47c7a6 SY |
3282 | return 1; |
3283 | /* Otherwise falls through */ | |
6aa8b732 | 3284 | default: |
609e36d3 | 3285 | msr = find_msr_entry(to_vmx(vcpu), msr_info->index); |
3bab1f5d | 3286 | if (msr) { |
609e36d3 | 3287 | msr_info->data = msr->data; |
3bab1f5d | 3288 | break; |
6aa8b732 | 3289 | } |
609e36d3 | 3290 | return kvm_get_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3291 | } |
3292 | ||
6aa8b732 AK |
3293 | return 0; |
3294 | } | |
3295 | ||
cae50139 JK |
3296 | static void vmx_leave_nested(struct kvm_vcpu *vcpu); |
3297 | ||
6aa8b732 AK |
3298 | /* |
3299 | * Writes msr value into into the appropriate "register". | |
3300 | * Returns 0 on success, non-0 otherwise. | |
3301 | * Assumes vcpu_load() was already called. | |
3302 | */ | |
8fe8ab46 | 3303 | static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3304 | { |
a2fa3e9f | 3305 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 3306 | struct shared_msr_entry *msr; |
2cc51560 | 3307 | int ret = 0; |
8fe8ab46 WA |
3308 | u32 msr_index = msr_info->index; |
3309 | u64 data = msr_info->data; | |
2cc51560 | 3310 | |
6aa8b732 | 3311 | switch (msr_index) { |
3bab1f5d | 3312 | case MSR_EFER: |
8fe8ab46 | 3313 | ret = kvm_set_msr_common(vcpu, msr_info); |
2cc51560 | 3314 | break; |
16175a79 | 3315 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3316 | case MSR_FS_BASE: |
2fb92db1 | 3317 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
3318 | vmcs_writel(GUEST_FS_BASE, data); |
3319 | break; | |
3320 | case MSR_GS_BASE: | |
2fb92db1 | 3321 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
3322 | vmcs_writel(GUEST_GS_BASE, data); |
3323 | break; | |
44ea2b17 AK |
3324 | case MSR_KERNEL_GS_BASE: |
3325 | vmx_load_host_state(vmx); | |
3326 | vmx->msr_guest_kernel_gs_base = data; | |
3327 | break; | |
6aa8b732 AK |
3328 | #endif |
3329 | case MSR_IA32_SYSENTER_CS: | |
3330 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
3331 | break; | |
3332 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 3333 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
3334 | break; |
3335 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 3336 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 3337 | break; |
0dd376e7 | 3338 | case MSR_IA32_BNDCFGS: |
a87036ad | 3339 | if (!kvm_mpx_supported()) |
93c4adc7 | 3340 | return 1; |
0dd376e7 LJ |
3341 | vmcs_write64(GUEST_BNDCFGS, data); |
3342 | break; | |
af24a4e4 | 3343 | case MSR_IA32_TSC: |
8fe8ab46 | 3344 | kvm_write_tsc(vcpu, msr_info); |
6aa8b732 | 3345 | break; |
468d472f SY |
3346 | case MSR_IA32_CR_PAT: |
3347 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
4566654b NA |
3348 | if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data)) |
3349 | return 1; | |
468d472f SY |
3350 | vmcs_write64(GUEST_IA32_PAT, data); |
3351 | vcpu->arch.pat = data; | |
3352 | break; | |
3353 | } | |
8fe8ab46 | 3354 | ret = kvm_set_msr_common(vcpu, msr_info); |
4e47c7a6 | 3355 | break; |
ba904635 WA |
3356 | case MSR_IA32_TSC_ADJUST: |
3357 | ret = kvm_set_msr_common(vcpu, msr_info); | |
4e47c7a6 | 3358 | break; |
c45dcc71 AR |
3359 | case MSR_IA32_MCG_EXT_CTL: |
3360 | if ((!msr_info->host_initiated && | |
3361 | !(to_vmx(vcpu)->msr_ia32_feature_control & | |
3362 | FEATURE_CONTROL_LMCE)) || | |
3363 | (data & ~MCG_EXT_CTL_LMCE_EN)) | |
3364 | return 1; | |
3365 | vcpu->arch.mcg_ext_ctl = data; | |
3366 | break; | |
cae50139 | 3367 | case MSR_IA32_FEATURE_CONTROL: |
37e4c997 | 3368 | if (!vmx_feature_control_msr_valid(vcpu, data) || |
3b84080b | 3369 | (to_vmx(vcpu)->msr_ia32_feature_control & |
cae50139 JK |
3370 | FEATURE_CONTROL_LOCKED && !msr_info->host_initiated)) |
3371 | return 1; | |
3b84080b | 3372 | vmx->msr_ia32_feature_control = data; |
cae50139 JK |
3373 | if (msr_info->host_initiated && data == 0) |
3374 | vmx_leave_nested(vcpu); | |
3375 | break; | |
3376 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
62cc6b9d DM |
3377 | if (!msr_info->host_initiated) |
3378 | return 1; /* they are read-only */ | |
3379 | if (!nested_vmx_allowed(vcpu)) | |
3380 | return 1; | |
3381 | return vmx_set_vmx_msr(vcpu, msr_index, data); | |
20300099 WL |
3382 | case MSR_IA32_XSS: |
3383 | if (!vmx_xsaves_supported()) | |
3384 | return 1; | |
3385 | /* | |
3386 | * The only supported bit as of Skylake is bit 8, but | |
3387 | * it is not supported on KVM. | |
3388 | */ | |
3389 | if (data != 0) | |
3390 | return 1; | |
3391 | vcpu->arch.ia32_xss = data; | |
3392 | if (vcpu->arch.ia32_xss != host_xss) | |
3393 | add_atomic_switch_msr(vmx, MSR_IA32_XSS, | |
3394 | vcpu->arch.ia32_xss, host_xss); | |
3395 | else | |
3396 | clear_atomic_switch_msr(vmx, MSR_IA32_XSS); | |
3397 | break; | |
4e47c7a6 | 3398 | case MSR_TSC_AUX: |
81b1b9ca | 3399 | if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated) |
4e47c7a6 SY |
3400 | return 1; |
3401 | /* Check reserved bit, higher 32 bits should be zero */ | |
3402 | if ((data >> 32) != 0) | |
3403 | return 1; | |
3404 | /* Otherwise falls through */ | |
6aa8b732 | 3405 | default: |
8b9cf98c | 3406 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d | 3407 | if (msr) { |
8b3c3104 | 3408 | u64 old_msr_data = msr->data; |
3bab1f5d | 3409 | msr->data = data; |
2225fd56 AK |
3410 | if (msr - vmx->guest_msrs < vmx->save_nmsrs) { |
3411 | preempt_disable(); | |
8b3c3104 AH |
3412 | ret = kvm_set_shared_msr(msr->index, msr->data, |
3413 | msr->mask); | |
2225fd56 | 3414 | preempt_enable(); |
8b3c3104 AH |
3415 | if (ret) |
3416 | msr->data = old_msr_data; | |
2225fd56 | 3417 | } |
3bab1f5d | 3418 | break; |
6aa8b732 | 3419 | } |
8fe8ab46 | 3420 | ret = kvm_set_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3421 | } |
3422 | ||
2cc51560 | 3423 | return ret; |
6aa8b732 AK |
3424 | } |
3425 | ||
5fdbf976 | 3426 | static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
6aa8b732 | 3427 | { |
5fdbf976 MT |
3428 | __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); |
3429 | switch (reg) { | |
3430 | case VCPU_REGS_RSP: | |
3431 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
3432 | break; | |
3433 | case VCPU_REGS_RIP: | |
3434 | vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); | |
3435 | break; | |
6de4f3ad AK |
3436 | case VCPU_EXREG_PDPTR: |
3437 | if (enable_ept) | |
3438 | ept_save_pdptrs(vcpu); | |
3439 | break; | |
5fdbf976 MT |
3440 | default: |
3441 | break; | |
3442 | } | |
6aa8b732 AK |
3443 | } |
3444 | ||
6aa8b732 AK |
3445 | static __init int cpu_has_kvm_support(void) |
3446 | { | |
6210e37b | 3447 | return cpu_has_vmx(); |
6aa8b732 AK |
3448 | } |
3449 | ||
3450 | static __init int vmx_disabled_by_bios(void) | |
3451 | { | |
3452 | u64 msr; | |
3453 | ||
3454 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
cafd6659 | 3455 | if (msr & FEATURE_CONTROL_LOCKED) { |
23f3e991 | 3456 | /* launched w/ TXT and VMX disabled */ |
cafd6659 SW |
3457 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
3458 | && tboot_enabled()) | |
3459 | return 1; | |
23f3e991 | 3460 | /* launched w/o TXT and VMX only enabled w/ TXT */ |
cafd6659 | 3461 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) |
23f3e991 | 3462 | && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
f9335afe SW |
3463 | && !tboot_enabled()) { |
3464 | printk(KERN_WARNING "kvm: disable TXT in the BIOS or " | |
23f3e991 | 3465 | "activate TXT before enabling KVM\n"); |
cafd6659 | 3466 | return 1; |
f9335afe | 3467 | } |
23f3e991 JC |
3468 | /* launched w/o TXT and VMX disabled */ |
3469 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) | |
3470 | && !tboot_enabled()) | |
3471 | return 1; | |
cafd6659 SW |
3472 | } |
3473 | ||
3474 | return 0; | |
6aa8b732 AK |
3475 | } |
3476 | ||
7725b894 DX |
3477 | static void kvm_cpu_vmxon(u64 addr) |
3478 | { | |
1c5ac21a AS |
3479 | intel_pt_handle_vmx(1); |
3480 | ||
7725b894 DX |
3481 | asm volatile (ASM_VMX_VMXON_RAX |
3482 | : : "a"(&addr), "m"(addr) | |
3483 | : "memory", "cc"); | |
3484 | } | |
3485 | ||
13a34e06 | 3486 | static int hardware_enable(void) |
6aa8b732 AK |
3487 | { |
3488 | int cpu = raw_smp_processor_id(); | |
3489 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
cafd6659 | 3490 | u64 old, test_bits; |
6aa8b732 | 3491 | |
1e02ce4c | 3492 | if (cr4_read_shadow() & X86_CR4_VMXE) |
10474ae8 AG |
3493 | return -EBUSY; |
3494 | ||
d462b819 | 3495 | INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); |
bf9f6ac8 FW |
3496 | INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); |
3497 | spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
8f536b76 ZY |
3498 | |
3499 | /* | |
3500 | * Now we can enable the vmclear operation in kdump | |
3501 | * since the loaded_vmcss_on_cpu list on this cpu | |
3502 | * has been initialized. | |
3503 | * | |
3504 | * Though the cpu is not in VMX operation now, there | |
3505 | * is no problem to enable the vmclear operation | |
3506 | * for the loaded_vmcss_on_cpu list is empty! | |
3507 | */ | |
3508 | crash_enable_local_vmclear(cpu); | |
3509 | ||
6aa8b732 | 3510 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
cafd6659 SW |
3511 | |
3512 | test_bits = FEATURE_CONTROL_LOCKED; | |
3513 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
3514 | if (tboot_enabled()) | |
3515 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; | |
3516 | ||
3517 | if ((old & test_bits) != test_bits) { | |
6aa8b732 | 3518 | /* enable and lock */ |
cafd6659 SW |
3519 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); |
3520 | } | |
375074cc | 3521 | cr4_set_bits(X86_CR4_VMXE); |
10474ae8 | 3522 | |
4610c9cc DX |
3523 | if (vmm_exclusive) { |
3524 | kvm_cpu_vmxon(phys_addr); | |
3525 | ept_sync_global(); | |
3526 | } | |
10474ae8 | 3527 | |
89cbc767 | 3528 | native_store_gdt(this_cpu_ptr(&host_gdt)); |
3444d7da | 3529 | |
10474ae8 | 3530 | return 0; |
6aa8b732 AK |
3531 | } |
3532 | ||
d462b819 | 3533 | static void vmclear_local_loaded_vmcss(void) |
543e4243 AK |
3534 | { |
3535 | int cpu = raw_smp_processor_id(); | |
d462b819 | 3536 | struct loaded_vmcs *v, *n; |
543e4243 | 3537 | |
d462b819 NHE |
3538 | list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), |
3539 | loaded_vmcss_on_cpu_link) | |
3540 | __loaded_vmcs_clear(v); | |
543e4243 AK |
3541 | } |
3542 | ||
710ff4a8 EH |
3543 | |
3544 | /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() | |
3545 | * tricks. | |
3546 | */ | |
3547 | static void kvm_cpu_vmxoff(void) | |
6aa8b732 | 3548 | { |
4ecac3fd | 3549 | asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
1c5ac21a AS |
3550 | |
3551 | intel_pt_handle_vmx(0); | |
6aa8b732 AK |
3552 | } |
3553 | ||
13a34e06 | 3554 | static void hardware_disable(void) |
710ff4a8 | 3555 | { |
4610c9cc | 3556 | if (vmm_exclusive) { |
d462b819 | 3557 | vmclear_local_loaded_vmcss(); |
4610c9cc DX |
3558 | kvm_cpu_vmxoff(); |
3559 | } | |
375074cc | 3560 | cr4_clear_bits(X86_CR4_VMXE); |
710ff4a8 EH |
3561 | } |
3562 | ||
1c3d14fe | 3563 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 3564 | u32 msr, u32 *result) |
1c3d14fe YS |
3565 | { |
3566 | u32 vmx_msr_low, vmx_msr_high; | |
3567 | u32 ctl = ctl_min | ctl_opt; | |
3568 | ||
3569 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
3570 | ||
3571 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
3572 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
3573 | ||
3574 | /* Ensure minimum (required) set of control bits are supported. */ | |
3575 | if (ctl_min & ~ctl) | |
002c7f7c | 3576 | return -EIO; |
1c3d14fe YS |
3577 | |
3578 | *result = ctl; | |
3579 | return 0; | |
3580 | } | |
3581 | ||
110312c8 AK |
3582 | static __init bool allow_1_setting(u32 msr, u32 ctl) |
3583 | { | |
3584 | u32 vmx_msr_low, vmx_msr_high; | |
3585 | ||
3586 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
3587 | return vmx_msr_high & ctl; | |
3588 | } | |
3589 | ||
002c7f7c | 3590 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
3591 | { |
3592 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 3593 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
3594 | u32 _pin_based_exec_control = 0; |
3595 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 3596 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
3597 | u32 _vmexit_control = 0; |
3598 | u32 _vmentry_control = 0; | |
3599 | ||
10166744 | 3600 | min = CPU_BASED_HLT_EXITING | |
1c3d14fe YS |
3601 | #ifdef CONFIG_X86_64 |
3602 | CPU_BASED_CR8_LOAD_EXITING | | |
3603 | CPU_BASED_CR8_STORE_EXITING | | |
3604 | #endif | |
d56f546d SY |
3605 | CPU_BASED_CR3_LOAD_EXITING | |
3606 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
3607 | CPU_BASED_USE_IO_BITMAPS | |
3608 | CPU_BASED_MOV_DR_EXITING | | |
a7052897 | 3609 | CPU_BASED_USE_TSC_OFFSETING | |
59708670 SY |
3610 | CPU_BASED_MWAIT_EXITING | |
3611 | CPU_BASED_MONITOR_EXITING | | |
fee84b07 AK |
3612 | CPU_BASED_INVLPG_EXITING | |
3613 | CPU_BASED_RDPMC_EXITING; | |
443381a8 | 3614 | |
f78e0e2e | 3615 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 3616 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 3617 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
3618 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
3619 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 3620 | return -EIO; |
6e5d865c YS |
3621 | #ifdef CONFIG_X86_64 |
3622 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
3623 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
3624 | ~CPU_BASED_CR8_STORE_EXITING; | |
3625 | #endif | |
f78e0e2e | 3626 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
3627 | min2 = 0; |
3628 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
8d14695f | 3629 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
2384d2b3 | 3630 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d | 3631 | SECONDARY_EXEC_ENABLE_VPID | |
3a624e29 | 3632 | SECONDARY_EXEC_ENABLE_EPT | |
4b8d54f9 | 3633 | SECONDARY_EXEC_UNRESTRICTED_GUEST | |
4e47c7a6 | 3634 | SECONDARY_EXEC_PAUSE_LOOP_EXITING | |
ad756a16 | 3635 | SECONDARY_EXEC_RDTSCP | |
83d4c286 | 3636 | SECONDARY_EXEC_ENABLE_INVPCID | |
c7c9c56c | 3637 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
abc4fc58 | 3638 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
20300099 | 3639 | SECONDARY_EXEC_SHADOW_VMCS | |
843e4330 | 3640 | SECONDARY_EXEC_XSAVES | |
8b3e34e4 | 3641 | SECONDARY_EXEC_ENABLE_PML | |
64903d61 | 3642 | SECONDARY_EXEC_TSC_SCALING; |
d56f546d SY |
3643 | if (adjust_vmx_controls(min2, opt2, |
3644 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
3645 | &_cpu_based_2nd_exec_control) < 0) |
3646 | return -EIO; | |
3647 | } | |
3648 | #ifndef CONFIG_X86_64 | |
3649 | if (!(_cpu_based_2nd_exec_control & | |
3650 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
3651 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
3652 | #endif | |
83d4c286 YZ |
3653 | |
3654 | if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
3655 | _cpu_based_2nd_exec_control &= ~( | |
8d14695f | 3656 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
c7c9c56c YZ |
3657 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
3658 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
83d4c286 | 3659 | |
d56f546d | 3660 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
a7052897 MT |
3661 | /* CR3 accesses and invlpg don't need to cause VM Exits when EPT |
3662 | enabled */ | |
5fff7d27 GN |
3663 | _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | |
3664 | CPU_BASED_CR3_STORE_EXITING | | |
3665 | CPU_BASED_INVLPG_EXITING); | |
d56f546d SY |
3666 | rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, |
3667 | vmx_capability.ept, vmx_capability.vpid); | |
3668 | } | |
1c3d14fe | 3669 | |
91fa0f8e | 3670 | min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; |
1c3d14fe YS |
3671 | #ifdef CONFIG_X86_64 |
3672 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
3673 | #endif | |
a547c6db | 3674 | opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT | |
91fa0f8e | 3675 | VM_EXIT_CLEAR_BNDCFGS; |
1c3d14fe YS |
3676 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, |
3677 | &_vmexit_control) < 0) | |
002c7f7c | 3678 | return -EIO; |
1c3d14fe | 3679 | |
01e439be | 3680 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; |
64672c95 YJ |
3681 | opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | |
3682 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
3683 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
3684 | &_pin_based_exec_control) < 0) | |
3685 | return -EIO; | |
3686 | ||
1c17c3e6 PB |
3687 | if (cpu_has_broken_vmx_preemption_timer()) |
3688 | _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be | 3689 | if (!(_cpu_based_2nd_exec_control & |
91fa0f8e | 3690 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) |
01e439be YZ |
3691 | _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; |
3692 | ||
c845f9c6 | 3693 | min = VM_ENTRY_LOAD_DEBUG_CONTROLS; |
da8999d3 | 3694 | opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS; |
1c3d14fe YS |
3695 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, |
3696 | &_vmentry_control) < 0) | |
002c7f7c | 3697 | return -EIO; |
6aa8b732 | 3698 | |
c68876fd | 3699 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
3700 | |
3701 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
3702 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 3703 | return -EIO; |
1c3d14fe YS |
3704 | |
3705 | #ifdef CONFIG_X86_64 | |
3706 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
3707 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 3708 | return -EIO; |
1c3d14fe YS |
3709 | #endif |
3710 | ||
3711 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
3712 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 3713 | return -EIO; |
1c3d14fe | 3714 | |
002c7f7c | 3715 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
16cb0255 | 3716 | vmcs_conf->order = get_order(vmcs_conf->size); |
9ac7e3e8 | 3717 | vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; |
002c7f7c | 3718 | vmcs_conf->revision_id = vmx_msr_low; |
1c3d14fe | 3719 | |
002c7f7c YS |
3720 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
3721 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 3722 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
3723 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
3724 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe | 3725 | |
110312c8 AK |
3726 | cpu_has_load_ia32_efer = |
3727 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
3728 | VM_ENTRY_LOAD_IA32_EFER) | |
3729 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
3730 | VM_EXIT_LOAD_IA32_EFER); | |
3731 | ||
8bf00a52 GN |
3732 | cpu_has_load_perf_global_ctrl = |
3733 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
3734 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
3735 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
3736 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
3737 | ||
3738 | /* | |
3739 | * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL | |
bb3541f1 | 3740 | * but due to errata below it can't be used. Workaround is to use |
8bf00a52 GN |
3741 | * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL. |
3742 | * | |
3743 | * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32] | |
3744 | * | |
3745 | * AAK155 (model 26) | |
3746 | * AAP115 (model 30) | |
3747 | * AAT100 (model 37) | |
3748 | * BC86,AAY89,BD102 (model 44) | |
3749 | * BA97 (model 46) | |
3750 | * | |
3751 | */ | |
3752 | if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) { | |
3753 | switch (boot_cpu_data.x86_model) { | |
3754 | case 26: | |
3755 | case 30: | |
3756 | case 37: | |
3757 | case 44: | |
3758 | case 46: | |
3759 | cpu_has_load_perf_global_ctrl = false; | |
3760 | printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " | |
3761 | "does not work properly. Using workaround\n"); | |
3762 | break; | |
3763 | default: | |
3764 | break; | |
3765 | } | |
3766 | } | |
3767 | ||
782511b0 | 3768 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
20300099 WL |
3769 | rdmsrl(MSR_IA32_XSS, host_xss); |
3770 | ||
1c3d14fe | 3771 | return 0; |
c68876fd | 3772 | } |
6aa8b732 AK |
3773 | |
3774 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
3775 | { | |
3776 | int node = cpu_to_node(cpu); | |
3777 | struct page *pages; | |
3778 | struct vmcs *vmcs; | |
3779 | ||
96db800f | 3780 | pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
3781 | if (!pages) |
3782 | return NULL; | |
3783 | vmcs = page_address(pages); | |
1c3d14fe YS |
3784 | memset(vmcs, 0, vmcs_config.size); |
3785 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
3786 | return vmcs; |
3787 | } | |
3788 | ||
3789 | static struct vmcs *alloc_vmcs(void) | |
3790 | { | |
d3b2c338 | 3791 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
3792 | } |
3793 | ||
3794 | static void free_vmcs(struct vmcs *vmcs) | |
3795 | { | |
1c3d14fe | 3796 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
3797 | } |
3798 | ||
d462b819 NHE |
3799 | /* |
3800 | * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded | |
3801 | */ | |
3802 | static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) | |
3803 | { | |
3804 | if (!loaded_vmcs->vmcs) | |
3805 | return; | |
3806 | loaded_vmcs_clear(loaded_vmcs); | |
3807 | free_vmcs(loaded_vmcs->vmcs); | |
3808 | loaded_vmcs->vmcs = NULL; | |
355f4fb1 | 3809 | WARN_ON(loaded_vmcs->shadow_vmcs != NULL); |
d462b819 NHE |
3810 | } |
3811 | ||
39959588 | 3812 | static void free_kvm_area(void) |
6aa8b732 AK |
3813 | { |
3814 | int cpu; | |
3815 | ||
3230bb47 | 3816 | for_each_possible_cpu(cpu) { |
6aa8b732 | 3817 | free_vmcs(per_cpu(vmxarea, cpu)); |
3230bb47 ZA |
3818 | per_cpu(vmxarea, cpu) = NULL; |
3819 | } | |
6aa8b732 AK |
3820 | } |
3821 | ||
fe2b201b BD |
3822 | static void init_vmcs_shadow_fields(void) |
3823 | { | |
3824 | int i, j; | |
3825 | ||
3826 | /* No checks for read only fields yet */ | |
3827 | ||
3828 | for (i = j = 0; i < max_shadow_read_write_fields; i++) { | |
3829 | switch (shadow_read_write_fields[i]) { | |
3830 | case GUEST_BNDCFGS: | |
a87036ad | 3831 | if (!kvm_mpx_supported()) |
fe2b201b BD |
3832 | continue; |
3833 | break; | |
3834 | default: | |
3835 | break; | |
3836 | } | |
3837 | ||
3838 | if (j < i) | |
3839 | shadow_read_write_fields[j] = | |
3840 | shadow_read_write_fields[i]; | |
3841 | j++; | |
3842 | } | |
3843 | max_shadow_read_write_fields = j; | |
3844 | ||
3845 | /* shadowed fields guest access without vmexit */ | |
3846 | for (i = 0; i < max_shadow_read_write_fields; i++) { | |
3847 | clear_bit(shadow_read_write_fields[i], | |
3848 | vmx_vmwrite_bitmap); | |
3849 | clear_bit(shadow_read_write_fields[i], | |
3850 | vmx_vmread_bitmap); | |
3851 | } | |
3852 | for (i = 0; i < max_shadow_read_only_fields; i++) | |
3853 | clear_bit(shadow_read_only_fields[i], | |
3854 | vmx_vmread_bitmap); | |
3855 | } | |
3856 | ||
6aa8b732 AK |
3857 | static __init int alloc_kvm_area(void) |
3858 | { | |
3859 | int cpu; | |
3860 | ||
3230bb47 | 3861 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
3862 | struct vmcs *vmcs; |
3863 | ||
3864 | vmcs = alloc_vmcs_cpu(cpu); | |
3865 | if (!vmcs) { | |
3866 | free_kvm_area(); | |
3867 | return -ENOMEM; | |
3868 | } | |
3869 | ||
3870 | per_cpu(vmxarea, cpu) = vmcs; | |
3871 | } | |
3872 | return 0; | |
3873 | } | |
3874 | ||
14168786 GN |
3875 | static bool emulation_required(struct kvm_vcpu *vcpu) |
3876 | { | |
3877 | return emulate_invalid_guest_state && !guest_state_valid(vcpu); | |
3878 | } | |
3879 | ||
91b0aa2c | 3880 | static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, |
d99e4152 | 3881 | struct kvm_segment *save) |
6aa8b732 | 3882 | { |
d99e4152 GN |
3883 | if (!emulate_invalid_guest_state) { |
3884 | /* | |
3885 | * CS and SS RPL should be equal during guest entry according | |
3886 | * to VMX spec, but in reality it is not always so. Since vcpu | |
3887 | * is in the middle of the transition from real mode to | |
3888 | * protected mode it is safe to assume that RPL 0 is a good | |
3889 | * default value. | |
3890 | */ | |
3891 | if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) | |
b32a9918 NA |
3892 | save->selector &= ~SEGMENT_RPL_MASK; |
3893 | save->dpl = save->selector & SEGMENT_RPL_MASK; | |
d99e4152 | 3894 | save->s = 1; |
6aa8b732 | 3895 | } |
d99e4152 | 3896 | vmx_set_segment(vcpu, save, seg); |
6aa8b732 AK |
3897 | } |
3898 | ||
3899 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
3900 | { | |
3901 | unsigned long flags; | |
a89a8fb9 | 3902 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 3903 | |
d99e4152 GN |
3904 | /* |
3905 | * Update real mode segment cache. It may be not up-to-date if sement | |
3906 | * register was written while vcpu was in a guest mode. | |
3907 | */ | |
3908 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
3909 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
3910 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
3911 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
3912 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); | |
3913 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
3914 | ||
7ffd92c5 | 3915 | vmx->rmode.vm86_active = 0; |
6aa8b732 | 3916 | |
2fb92db1 AK |
3917 | vmx_segment_cache_clear(vmx); |
3918 | ||
f5f7b2fe | 3919 | vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
6aa8b732 AK |
3920 | |
3921 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 AK |
3922 | flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; |
3923 | flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
6aa8b732 AK |
3924 | vmcs_writel(GUEST_RFLAGS, flags); |
3925 | ||
66aee91a RR |
3926 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
3927 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
3928 | |
3929 | update_exception_bitmap(vcpu); | |
3930 | ||
91b0aa2c GN |
3931 | fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); |
3932 | fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); | |
3933 | fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
3934 | fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
3935 | fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
3936 | fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
6aa8b732 AK |
3937 | } |
3938 | ||
f5f7b2fe | 3939 | static void fix_rmode_seg(int seg, struct kvm_segment *save) |
6aa8b732 | 3940 | { |
772e0318 | 3941 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
d99e4152 GN |
3942 | struct kvm_segment var = *save; |
3943 | ||
3944 | var.dpl = 0x3; | |
3945 | if (seg == VCPU_SREG_CS) | |
3946 | var.type = 0x3; | |
3947 | ||
3948 | if (!emulate_invalid_guest_state) { | |
3949 | var.selector = var.base >> 4; | |
3950 | var.base = var.base & 0xffff0; | |
3951 | var.limit = 0xffff; | |
3952 | var.g = 0; | |
3953 | var.db = 0; | |
3954 | var.present = 1; | |
3955 | var.s = 1; | |
3956 | var.l = 0; | |
3957 | var.unusable = 0; | |
3958 | var.type = 0x3; | |
3959 | var.avl = 0; | |
3960 | if (save->base & 0xf) | |
3961 | printk_once(KERN_WARNING "kvm: segment base is not " | |
3962 | "paragraph aligned when entering " | |
3963 | "protected mode (seg=%d)", seg); | |
3964 | } | |
6aa8b732 | 3965 | |
d99e4152 GN |
3966 | vmcs_write16(sf->selector, var.selector); |
3967 | vmcs_write32(sf->base, var.base); | |
3968 | vmcs_write32(sf->limit, var.limit); | |
3969 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); | |
6aa8b732 AK |
3970 | } |
3971 | ||
3972 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
3973 | { | |
3974 | unsigned long flags; | |
a89a8fb9 | 3975 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 3976 | |
f5f7b2fe AK |
3977 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
3978 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
3979 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
3980 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
3981 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
c6ad1153 GN |
3982 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); |
3983 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
f5f7b2fe | 3984 | |
7ffd92c5 | 3985 | vmx->rmode.vm86_active = 1; |
6aa8b732 | 3986 | |
776e58ea GN |
3987 | /* |
3988 | * Very old userspace does not call KVM_SET_TSS_ADDR before entering | |
4918c6ca | 3989 | * vcpu. Warn the user that an update is overdue. |
776e58ea | 3990 | */ |
4918c6ca | 3991 | if (!vcpu->kvm->arch.tss_addr) |
776e58ea GN |
3992 | printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " |
3993 | "called before entering vcpu\n"); | |
776e58ea | 3994 | |
2fb92db1 AK |
3995 | vmx_segment_cache_clear(vmx); |
3996 | ||
4918c6ca | 3997 | vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr); |
6aa8b732 | 3998 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
6aa8b732 AK |
3999 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
4000 | ||
4001 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 | 4002 | vmx->rmode.save_rflags = flags; |
6aa8b732 | 4003 | |
053de044 | 4004 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
4005 | |
4006 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 4007 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
4008 | update_exception_bitmap(vcpu); |
4009 | ||
d99e4152 GN |
4010 | fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); |
4011 | fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); | |
4012 | fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
4013 | fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
4014 | fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
4015 | fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
b246dd5d | 4016 | |
8668a3c4 | 4017 | kvm_mmu_reset_context(vcpu); |
6aa8b732 AK |
4018 | } |
4019 | ||
401d10de AS |
4020 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
4021 | { | |
4022 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
26bb0981 AK |
4023 | struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); |
4024 | ||
4025 | if (!msr) | |
4026 | return; | |
401d10de | 4027 | |
44ea2b17 AK |
4028 | /* |
4029 | * Force kernel_gs_base reloading before EFER changes, as control | |
4030 | * of this msr depends on is_long_mode(). | |
4031 | */ | |
4032 | vmx_load_host_state(to_vmx(vcpu)); | |
f6801dff | 4033 | vcpu->arch.efer = efer; |
401d10de | 4034 | if (efer & EFER_LMA) { |
2961e876 | 4035 | vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
4036 | msr->data = efer; |
4037 | } else { | |
2961e876 | 4038 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
4039 | |
4040 | msr->data = efer & ~EFER_LME; | |
4041 | } | |
4042 | setup_msrs(vmx); | |
4043 | } | |
4044 | ||
05b3e0c2 | 4045 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
4046 | |
4047 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
4048 | { | |
4049 | u32 guest_tr_ar; | |
4050 | ||
2fb92db1 AK |
4051 | vmx_segment_cache_clear(to_vmx(vcpu)); |
4052 | ||
6aa8b732 | 4053 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); |
4d283ec9 | 4054 | if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { |
bd80158a JK |
4055 | pr_debug_ratelimited("%s: tss fixup for long mode. \n", |
4056 | __func__); | |
6aa8b732 | 4057 | vmcs_write32(GUEST_TR_AR_BYTES, |
4d283ec9 AL |
4058 | (guest_tr_ar & ~VMX_AR_TYPE_MASK) |
4059 | | VMX_AR_TYPE_BUSY_64_TSS); | |
6aa8b732 | 4060 | } |
da38f438 | 4061 | vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); |
6aa8b732 AK |
4062 | } |
4063 | ||
4064 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
4065 | { | |
2961e876 | 4066 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
da38f438 | 4067 | vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); |
6aa8b732 AK |
4068 | } |
4069 | ||
4070 | #endif | |
4071 | ||
dd5f5341 | 4072 | static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid) |
2384d2b3 | 4073 | { |
dd5f5341 | 4074 | vpid_sync_context(vpid); |
dd180b3e XG |
4075 | if (enable_ept) { |
4076 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
4077 | return; | |
4e1096d2 | 4078 | ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa)); |
dd180b3e | 4079 | } |
2384d2b3 SY |
4080 | } |
4081 | ||
dd5f5341 WL |
4082 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
4083 | { | |
4084 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid); | |
4085 | } | |
4086 | ||
e8467fda AK |
4087 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
4088 | { | |
4089 | ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; | |
4090 | ||
4091 | vcpu->arch.cr0 &= ~cr0_guest_owned_bits; | |
4092 | vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; | |
4093 | } | |
4094 | ||
aff48baa AK |
4095 | static void vmx_decache_cr3(struct kvm_vcpu *vcpu) |
4096 | { | |
4097 | if (enable_ept && is_paging(vcpu)) | |
4098 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); | |
4099 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
4100 | } | |
4101 | ||
25c4c276 | 4102 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 4103 | { |
fc78f519 AK |
4104 | ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; |
4105 | ||
4106 | vcpu->arch.cr4 &= ~cr4_guest_owned_bits; | |
4107 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; | |
399badf3 AK |
4108 | } |
4109 | ||
1439442c SY |
4110 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
4111 | { | |
d0d538b9 GN |
4112 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
4113 | ||
6de4f3ad AK |
4114 | if (!test_bit(VCPU_EXREG_PDPTR, |
4115 | (unsigned long *)&vcpu->arch.regs_dirty)) | |
4116 | return; | |
4117 | ||
1439442c | 4118 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
d0d538b9 GN |
4119 | vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); |
4120 | vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); | |
4121 | vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); | |
4122 | vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); | |
1439442c SY |
4123 | } |
4124 | } | |
4125 | ||
8f5d549f AK |
4126 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu) |
4127 | { | |
d0d538b9 GN |
4128 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
4129 | ||
8f5d549f | 4130 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
d0d538b9 GN |
4131 | mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); |
4132 | mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); | |
4133 | mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); | |
4134 | mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); | |
8f5d549f | 4135 | } |
6de4f3ad AK |
4136 | |
4137 | __set_bit(VCPU_EXREG_PDPTR, | |
4138 | (unsigned long *)&vcpu->arch.regs_avail); | |
4139 | __set_bit(VCPU_EXREG_PDPTR, | |
4140 | (unsigned long *)&vcpu->arch.regs_dirty); | |
8f5d549f AK |
4141 | } |
4142 | ||
3899152c DM |
4143 | static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) |
4144 | { | |
4145 | u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0; | |
4146 | u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1; | |
4147 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
4148 | ||
4149 | if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high & | |
4150 | SECONDARY_EXEC_UNRESTRICTED_GUEST && | |
4151 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST)) | |
4152 | fixed0 &= ~(X86_CR0_PE | X86_CR0_PG); | |
4153 | ||
4154 | return fixed_bits_valid(val, fixed0, fixed1); | |
4155 | } | |
4156 | ||
4157 | static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) | |
4158 | { | |
4159 | u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0; | |
4160 | u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1; | |
4161 | ||
4162 | return fixed_bits_valid(val, fixed0, fixed1); | |
4163 | } | |
4164 | ||
4165 | static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val) | |
4166 | { | |
4167 | u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0; | |
4168 | u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1; | |
4169 | ||
4170 | return fixed_bits_valid(val, fixed0, fixed1); | |
4171 | } | |
4172 | ||
4173 | /* No difference in the restrictions on guest and host CR4 in VMX operation. */ | |
4174 | #define nested_guest_cr4_valid nested_cr4_valid | |
4175 | #define nested_host_cr4_valid nested_cr4_valid | |
4176 | ||
5e1746d6 | 4177 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
1439442c SY |
4178 | |
4179 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
4180 | unsigned long cr0, | |
4181 | struct kvm_vcpu *vcpu) | |
4182 | { | |
5233dd51 MT |
4183 | if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) |
4184 | vmx_decache_cr3(vcpu); | |
1439442c SY |
4185 | if (!(cr0 & X86_CR0_PG)) { |
4186 | /* From paging/starting to nonpaging */ | |
4187 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 4188 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
1439442c SY |
4189 | (CPU_BASED_CR3_LOAD_EXITING | |
4190 | CPU_BASED_CR3_STORE_EXITING)); | |
4191 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 4192 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c SY |
4193 | } else if (!is_paging(vcpu)) { |
4194 | /* From nonpaging to paging */ | |
4195 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 4196 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
1439442c SY |
4197 | ~(CPU_BASED_CR3_LOAD_EXITING | |
4198 | CPU_BASED_CR3_STORE_EXITING)); | |
4199 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 4200 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c | 4201 | } |
95eb84a7 SY |
4202 | |
4203 | if (!(cr0 & X86_CR0_WP)) | |
4204 | *hw_cr0 &= ~X86_CR0_WP; | |
1439442c SY |
4205 | } |
4206 | ||
6aa8b732 AK |
4207 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
4208 | { | |
7ffd92c5 | 4209 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3a624e29 NK |
4210 | unsigned long hw_cr0; |
4211 | ||
5037878e | 4212 | hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK); |
3a624e29 | 4213 | if (enable_unrestricted_guest) |
5037878e | 4214 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; |
218e763f | 4215 | else { |
5037878e | 4216 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; |
1439442c | 4217 | |
218e763f GN |
4218 | if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) |
4219 | enter_pmode(vcpu); | |
6aa8b732 | 4220 | |
218e763f GN |
4221 | if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) |
4222 | enter_rmode(vcpu); | |
4223 | } | |
6aa8b732 | 4224 | |
05b3e0c2 | 4225 | #ifdef CONFIG_X86_64 |
f6801dff | 4226 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 4227 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 4228 | enter_lmode(vcpu); |
707d92fa | 4229 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
4230 | exit_lmode(vcpu); |
4231 | } | |
4232 | #endif | |
4233 | ||
089d034e | 4234 | if (enable_ept) |
1439442c SY |
4235 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); |
4236 | ||
02daab21 | 4237 | if (!vcpu->fpu_active) |
81231c69 | 4238 | hw_cr0 |= X86_CR0_TS | X86_CR0_MP; |
02daab21 | 4239 | |
6aa8b732 | 4240 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 4241 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 4242 | vcpu->arch.cr0 = cr0; |
14168786 GN |
4243 | |
4244 | /* depends on vcpu->arch.cr0 to be set to a new value */ | |
4245 | vmx->emulation_required = emulation_required(vcpu); | |
6aa8b732 AK |
4246 | } |
4247 | ||
1439442c SY |
4248 | static u64 construct_eptp(unsigned long root_hpa) |
4249 | { | |
4250 | u64 eptp; | |
4251 | ||
4252 | /* TODO write the value reading from MSR */ | |
4253 | eptp = VMX_EPT_DEFAULT_MT | | |
4254 | VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT; | |
b38f9934 XH |
4255 | if (enable_ept_ad_bits) |
4256 | eptp |= VMX_EPT_AD_ENABLE_BIT; | |
1439442c SY |
4257 | eptp |= (root_hpa & PAGE_MASK); |
4258 | ||
4259 | return eptp; | |
4260 | } | |
4261 | ||
6aa8b732 AK |
4262 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
4263 | { | |
1439442c SY |
4264 | unsigned long guest_cr3; |
4265 | u64 eptp; | |
4266 | ||
4267 | guest_cr3 = cr3; | |
089d034e | 4268 | if (enable_ept) { |
1439442c SY |
4269 | eptp = construct_eptp(cr3); |
4270 | vmcs_write64(EPT_POINTER, eptp); | |
59ab5a8f JK |
4271 | if (is_paging(vcpu) || is_guest_mode(vcpu)) |
4272 | guest_cr3 = kvm_read_cr3(vcpu); | |
4273 | else | |
4274 | guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr; | |
7c93be44 | 4275 | ept_load_pdptrs(vcpu); |
1439442c SY |
4276 | } |
4277 | ||
2384d2b3 | 4278 | vmx_flush_tlb(vcpu); |
1439442c | 4279 | vmcs_writel(GUEST_CR3, guest_cr3); |
6aa8b732 AK |
4280 | } |
4281 | ||
5e1746d6 | 4282 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 4283 | { |
085e68ee BS |
4284 | /* |
4285 | * Pass through host's Machine Check Enable value to hw_cr4, which | |
4286 | * is in force while we are in guest mode. Do not let guests control | |
4287 | * this bit, even if host CR4.MCE == 0. | |
4288 | */ | |
4289 | unsigned long hw_cr4 = | |
4290 | (cr4_read_shadow() & X86_CR4_MCE) | | |
4291 | (cr4 & ~X86_CR4_MCE) | | |
4292 | (to_vmx(vcpu)->rmode.vm86_active ? | |
4293 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); | |
1439442c | 4294 | |
5e1746d6 NHE |
4295 | if (cr4 & X86_CR4_VMXE) { |
4296 | /* | |
4297 | * To use VMXON (and later other VMX instructions), a guest | |
4298 | * must first be able to turn on cr4.VMXE (see handle_vmon()). | |
4299 | * So basically the check on whether to allow nested VMX | |
4300 | * is here. | |
4301 | */ | |
4302 | if (!nested_vmx_allowed(vcpu)) | |
4303 | return 1; | |
1a0d74e6 | 4304 | } |
3899152c DM |
4305 | |
4306 | if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) | |
5e1746d6 NHE |
4307 | return 1; |
4308 | ||
ad312c7c | 4309 | vcpu->arch.cr4 = cr4; |
bc23008b AK |
4310 | if (enable_ept) { |
4311 | if (!is_paging(vcpu)) { | |
4312 | hw_cr4 &= ~X86_CR4_PAE; | |
4313 | hw_cr4 |= X86_CR4_PSE; | |
4314 | } else if (!(cr4 & X86_CR4_PAE)) { | |
4315 | hw_cr4 &= ~X86_CR4_PAE; | |
4316 | } | |
4317 | } | |
1439442c | 4318 | |
656ec4a4 RK |
4319 | if (!enable_unrestricted_guest && !is_paging(vcpu)) |
4320 | /* | |
ddba2628 HH |
4321 | * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in |
4322 | * hardware. To emulate this behavior, SMEP/SMAP/PKU needs | |
4323 | * to be manually disabled when guest switches to non-paging | |
4324 | * mode. | |
4325 | * | |
4326 | * If !enable_unrestricted_guest, the CPU is always running | |
4327 | * with CR0.PG=1 and CR4 needs to be modified. | |
4328 | * If enable_unrestricted_guest, the CPU automatically | |
4329 | * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. | |
656ec4a4 | 4330 | */ |
ddba2628 | 4331 | hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); |
656ec4a4 | 4332 | |
1439442c SY |
4333 | vmcs_writel(CR4_READ_SHADOW, cr4); |
4334 | vmcs_writel(GUEST_CR4, hw_cr4); | |
5e1746d6 | 4335 | return 0; |
6aa8b732 AK |
4336 | } |
4337 | ||
6aa8b732 AK |
4338 | static void vmx_get_segment(struct kvm_vcpu *vcpu, |
4339 | struct kvm_segment *var, int seg) | |
4340 | { | |
a9179499 | 4341 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 AK |
4342 | u32 ar; |
4343 | ||
c6ad1153 | 4344 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
f5f7b2fe | 4345 | *var = vmx->rmode.segs[seg]; |
a9179499 | 4346 | if (seg == VCPU_SREG_TR |
2fb92db1 | 4347 | || var->selector == vmx_read_guest_seg_selector(vmx, seg)) |
f5f7b2fe | 4348 | return; |
1390a28b AK |
4349 | var->base = vmx_read_guest_seg_base(vmx, seg); |
4350 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
4351 | return; | |
a9179499 | 4352 | } |
2fb92db1 AK |
4353 | var->base = vmx_read_guest_seg_base(vmx, seg); |
4354 | var->limit = vmx_read_guest_seg_limit(vmx, seg); | |
4355 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
4356 | ar = vmx_read_guest_seg_ar(vmx, seg); | |
03617c18 | 4357 | var->unusable = (ar >> 16) & 1; |
6aa8b732 AK |
4358 | var->type = ar & 15; |
4359 | var->s = (ar >> 4) & 1; | |
4360 | var->dpl = (ar >> 5) & 3; | |
03617c18 GN |
4361 | /* |
4362 | * Some userspaces do not preserve unusable property. Since usable | |
4363 | * segment has to be present according to VMX spec we can use present | |
4364 | * property to amend userspace bug by making unusable segment always | |
4365 | * nonpresent. vmx_segment_access_rights() already marks nonpresent | |
4366 | * segment as unusable. | |
4367 | */ | |
4368 | var->present = !var->unusable; | |
6aa8b732 AK |
4369 | var->avl = (ar >> 12) & 1; |
4370 | var->l = (ar >> 13) & 1; | |
4371 | var->db = (ar >> 14) & 1; | |
4372 | var->g = (ar >> 15) & 1; | |
6aa8b732 AK |
4373 | } |
4374 | ||
a9179499 AK |
4375 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4376 | { | |
a9179499 AK |
4377 | struct kvm_segment s; |
4378 | ||
4379 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
4380 | vmx_get_segment(vcpu, &s, seg); | |
4381 | return s.base; | |
4382 | } | |
2fb92db1 | 4383 | return vmx_read_guest_seg_base(to_vmx(vcpu), seg); |
a9179499 AK |
4384 | } |
4385 | ||
b09408d0 | 4386 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
2e4d2653 | 4387 | { |
b09408d0 MT |
4388 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4389 | ||
ae9fedc7 | 4390 | if (unlikely(vmx->rmode.vm86_active)) |
2e4d2653 | 4391 | return 0; |
ae9fedc7 PB |
4392 | else { |
4393 | int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); | |
4d283ec9 | 4394 | return VMX_AR_DPL(ar); |
69c73028 | 4395 | } |
69c73028 AK |
4396 | } |
4397 | ||
653e3108 | 4398 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 4399 | { |
6aa8b732 AK |
4400 | u32 ar; |
4401 | ||
f0495f9b | 4402 | if (var->unusable || !var->present) |
6aa8b732 AK |
4403 | ar = 1 << 16; |
4404 | else { | |
4405 | ar = var->type & 15; | |
4406 | ar |= (var->s & 1) << 4; | |
4407 | ar |= (var->dpl & 3) << 5; | |
4408 | ar |= (var->present & 1) << 7; | |
4409 | ar |= (var->avl & 1) << 12; | |
4410 | ar |= (var->l & 1) << 13; | |
4411 | ar |= (var->db & 1) << 14; | |
4412 | ar |= (var->g & 1) << 15; | |
4413 | } | |
653e3108 AK |
4414 | |
4415 | return ar; | |
4416 | } | |
4417 | ||
4418 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
4419 | struct kvm_segment *var, int seg) | |
4420 | { | |
7ffd92c5 | 4421 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
772e0318 | 4422 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
653e3108 | 4423 | |
2fb92db1 AK |
4424 | vmx_segment_cache_clear(vmx); |
4425 | ||
1ecd50a9 GN |
4426 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
4427 | vmx->rmode.segs[seg] = *var; | |
4428 | if (seg == VCPU_SREG_TR) | |
4429 | vmcs_write16(sf->selector, var->selector); | |
4430 | else if (var->s) | |
4431 | fix_rmode_seg(seg, &vmx->rmode.segs[seg]); | |
d99e4152 | 4432 | goto out; |
653e3108 | 4433 | } |
1ecd50a9 | 4434 | |
653e3108 AK |
4435 | vmcs_writel(sf->base, var->base); |
4436 | vmcs_write32(sf->limit, var->limit); | |
4437 | vmcs_write16(sf->selector, var->selector); | |
3a624e29 NK |
4438 | |
4439 | /* | |
4440 | * Fix the "Accessed" bit in AR field of segment registers for older | |
4441 | * qemu binaries. | |
4442 | * IA32 arch specifies that at the time of processor reset the | |
4443 | * "Accessed" bit in the AR field of segment registers is 1. And qemu | |
0fa06071 | 4444 | * is setting it to 0 in the userland code. This causes invalid guest |
3a624e29 NK |
4445 | * state vmexit when "unrestricted guest" mode is turned on. |
4446 | * Fix for this setup issue in cpu_reset is being pushed in the qemu | |
4447 | * tree. Newer qemu binaries with that qemu fix would not need this | |
4448 | * kvm hack. | |
4449 | */ | |
4450 | if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) | |
f924d66d | 4451 | var->type |= 0x1; /* Accessed */ |
3a624e29 | 4452 | |
f924d66d | 4453 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); |
d99e4152 GN |
4454 | |
4455 | out: | |
98eb2f8b | 4456 | vmx->emulation_required = emulation_required(vcpu); |
6aa8b732 AK |
4457 | } |
4458 | ||
6aa8b732 AK |
4459 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
4460 | { | |
2fb92db1 | 4461 | u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); |
6aa8b732 AK |
4462 | |
4463 | *db = (ar >> 14) & 1; | |
4464 | *l = (ar >> 13) & 1; | |
4465 | } | |
4466 | ||
89a27f4d | 4467 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4468 | { |
89a27f4d GN |
4469 | dt->size = vmcs_read32(GUEST_IDTR_LIMIT); |
4470 | dt->address = vmcs_readl(GUEST_IDTR_BASE); | |
6aa8b732 AK |
4471 | } |
4472 | ||
89a27f4d | 4473 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4474 | { |
89a27f4d GN |
4475 | vmcs_write32(GUEST_IDTR_LIMIT, dt->size); |
4476 | vmcs_writel(GUEST_IDTR_BASE, dt->address); | |
6aa8b732 AK |
4477 | } |
4478 | ||
89a27f4d | 4479 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4480 | { |
89a27f4d GN |
4481 | dt->size = vmcs_read32(GUEST_GDTR_LIMIT); |
4482 | dt->address = vmcs_readl(GUEST_GDTR_BASE); | |
6aa8b732 AK |
4483 | } |
4484 | ||
89a27f4d | 4485 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4486 | { |
89a27f4d GN |
4487 | vmcs_write32(GUEST_GDTR_LIMIT, dt->size); |
4488 | vmcs_writel(GUEST_GDTR_BASE, dt->address); | |
6aa8b732 AK |
4489 | } |
4490 | ||
648dfaa7 MG |
4491 | static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) |
4492 | { | |
4493 | struct kvm_segment var; | |
4494 | u32 ar; | |
4495 | ||
4496 | vmx_get_segment(vcpu, &var, seg); | |
07f42f5f | 4497 | var.dpl = 0x3; |
0647f4aa GN |
4498 | if (seg == VCPU_SREG_CS) |
4499 | var.type = 0x3; | |
648dfaa7 MG |
4500 | ar = vmx_segment_access_rights(&var); |
4501 | ||
4502 | if (var.base != (var.selector << 4)) | |
4503 | return false; | |
89efbed0 | 4504 | if (var.limit != 0xffff) |
648dfaa7 | 4505 | return false; |
07f42f5f | 4506 | if (ar != 0xf3) |
648dfaa7 MG |
4507 | return false; |
4508 | ||
4509 | return true; | |
4510 | } | |
4511 | ||
4512 | static bool code_segment_valid(struct kvm_vcpu *vcpu) | |
4513 | { | |
4514 | struct kvm_segment cs; | |
4515 | unsigned int cs_rpl; | |
4516 | ||
4517 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
b32a9918 | 4518 | cs_rpl = cs.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4519 | |
1872a3f4 AK |
4520 | if (cs.unusable) |
4521 | return false; | |
4d283ec9 | 4522 | if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) |
648dfaa7 MG |
4523 | return false; |
4524 | if (!cs.s) | |
4525 | return false; | |
4d283ec9 | 4526 | if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { |
648dfaa7 MG |
4527 | if (cs.dpl > cs_rpl) |
4528 | return false; | |
1872a3f4 | 4529 | } else { |
648dfaa7 MG |
4530 | if (cs.dpl != cs_rpl) |
4531 | return false; | |
4532 | } | |
4533 | if (!cs.present) | |
4534 | return false; | |
4535 | ||
4536 | /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ | |
4537 | return true; | |
4538 | } | |
4539 | ||
4540 | static bool stack_segment_valid(struct kvm_vcpu *vcpu) | |
4541 | { | |
4542 | struct kvm_segment ss; | |
4543 | unsigned int ss_rpl; | |
4544 | ||
4545 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
b32a9918 | 4546 | ss_rpl = ss.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4547 | |
1872a3f4 AK |
4548 | if (ss.unusable) |
4549 | return true; | |
4550 | if (ss.type != 3 && ss.type != 7) | |
648dfaa7 MG |
4551 | return false; |
4552 | if (!ss.s) | |
4553 | return false; | |
4554 | if (ss.dpl != ss_rpl) /* DPL != RPL */ | |
4555 | return false; | |
4556 | if (!ss.present) | |
4557 | return false; | |
4558 | ||
4559 | return true; | |
4560 | } | |
4561 | ||
4562 | static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) | |
4563 | { | |
4564 | struct kvm_segment var; | |
4565 | unsigned int rpl; | |
4566 | ||
4567 | vmx_get_segment(vcpu, &var, seg); | |
b32a9918 | 4568 | rpl = var.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4569 | |
1872a3f4 AK |
4570 | if (var.unusable) |
4571 | return true; | |
648dfaa7 MG |
4572 | if (!var.s) |
4573 | return false; | |
4574 | if (!var.present) | |
4575 | return false; | |
4d283ec9 | 4576 | if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { |
648dfaa7 MG |
4577 | if (var.dpl < rpl) /* DPL < RPL */ |
4578 | return false; | |
4579 | } | |
4580 | ||
4581 | /* TODO: Add other members to kvm_segment_field to allow checking for other access | |
4582 | * rights flags | |
4583 | */ | |
4584 | return true; | |
4585 | } | |
4586 | ||
4587 | static bool tr_valid(struct kvm_vcpu *vcpu) | |
4588 | { | |
4589 | struct kvm_segment tr; | |
4590 | ||
4591 | vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); | |
4592 | ||
1872a3f4 AK |
4593 | if (tr.unusable) |
4594 | return false; | |
b32a9918 | 4595 | if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 | 4596 | return false; |
1872a3f4 | 4597 | if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ |
648dfaa7 MG |
4598 | return false; |
4599 | if (!tr.present) | |
4600 | return false; | |
4601 | ||
4602 | return true; | |
4603 | } | |
4604 | ||
4605 | static bool ldtr_valid(struct kvm_vcpu *vcpu) | |
4606 | { | |
4607 | struct kvm_segment ldtr; | |
4608 | ||
4609 | vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); | |
4610 | ||
1872a3f4 AK |
4611 | if (ldtr.unusable) |
4612 | return true; | |
b32a9918 | 4613 | if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 MG |
4614 | return false; |
4615 | if (ldtr.type != 2) | |
4616 | return false; | |
4617 | if (!ldtr.present) | |
4618 | return false; | |
4619 | ||
4620 | return true; | |
4621 | } | |
4622 | ||
4623 | static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) | |
4624 | { | |
4625 | struct kvm_segment cs, ss; | |
4626 | ||
4627 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
4628 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
4629 | ||
b32a9918 NA |
4630 | return ((cs.selector & SEGMENT_RPL_MASK) == |
4631 | (ss.selector & SEGMENT_RPL_MASK)); | |
648dfaa7 MG |
4632 | } |
4633 | ||
4634 | /* | |
4635 | * Check if guest state is valid. Returns true if valid, false if | |
4636 | * not. | |
4637 | * We assume that registers are always usable | |
4638 | */ | |
4639 | static bool guest_state_valid(struct kvm_vcpu *vcpu) | |
4640 | { | |
c5e97c80 GN |
4641 | if (enable_unrestricted_guest) |
4642 | return true; | |
4643 | ||
648dfaa7 | 4644 | /* real mode guest state checks */ |
f13882d8 | 4645 | if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { |
648dfaa7 MG |
4646 | if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) |
4647 | return false; | |
4648 | if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) | |
4649 | return false; | |
4650 | if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) | |
4651 | return false; | |
4652 | if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) | |
4653 | return false; | |
4654 | if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) | |
4655 | return false; | |
4656 | if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) | |
4657 | return false; | |
4658 | } else { | |
4659 | /* protected mode guest state checks */ | |
4660 | if (!cs_ss_rpl_check(vcpu)) | |
4661 | return false; | |
4662 | if (!code_segment_valid(vcpu)) | |
4663 | return false; | |
4664 | if (!stack_segment_valid(vcpu)) | |
4665 | return false; | |
4666 | if (!data_segment_valid(vcpu, VCPU_SREG_DS)) | |
4667 | return false; | |
4668 | if (!data_segment_valid(vcpu, VCPU_SREG_ES)) | |
4669 | return false; | |
4670 | if (!data_segment_valid(vcpu, VCPU_SREG_FS)) | |
4671 | return false; | |
4672 | if (!data_segment_valid(vcpu, VCPU_SREG_GS)) | |
4673 | return false; | |
4674 | if (!tr_valid(vcpu)) | |
4675 | return false; | |
4676 | if (!ldtr_valid(vcpu)) | |
4677 | return false; | |
4678 | } | |
4679 | /* TODO: | |
4680 | * - Add checks on RIP | |
4681 | * - Add checks on RFLAGS | |
4682 | */ | |
4683 | ||
4684 | return true; | |
4685 | } | |
4686 | ||
d77c26fc | 4687 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 4688 | { |
40dcaa9f | 4689 | gfn_t fn; |
195aefde | 4690 | u16 data = 0; |
1f755a82 | 4691 | int idx, r; |
6aa8b732 | 4692 | |
40dcaa9f | 4693 | idx = srcu_read_lock(&kvm->srcu); |
4918c6ca | 4694 | fn = kvm->arch.tss_addr >> PAGE_SHIFT; |
195aefde IE |
4695 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
4696 | if (r < 0) | |
10589a46 | 4697 | goto out; |
195aefde | 4698 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
464d17c8 SY |
4699 | r = kvm_write_guest_page(kvm, fn++, &data, |
4700 | TSS_IOPB_BASE_OFFSET, sizeof(u16)); | |
195aefde | 4701 | if (r < 0) |
10589a46 | 4702 | goto out; |
195aefde IE |
4703 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
4704 | if (r < 0) | |
10589a46 | 4705 | goto out; |
195aefde IE |
4706 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
4707 | if (r < 0) | |
10589a46 | 4708 | goto out; |
195aefde | 4709 | data = ~0; |
10589a46 MT |
4710 | r = kvm_write_guest_page(kvm, fn, &data, |
4711 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
4712 | sizeof(u8)); | |
10589a46 | 4713 | out: |
40dcaa9f | 4714 | srcu_read_unlock(&kvm->srcu, idx); |
1f755a82 | 4715 | return r; |
6aa8b732 AK |
4716 | } |
4717 | ||
b7ebfb05 SY |
4718 | static int init_rmode_identity_map(struct kvm *kvm) |
4719 | { | |
f51770ed | 4720 | int i, idx, r = 0; |
ba049e93 | 4721 | kvm_pfn_t identity_map_pfn; |
b7ebfb05 SY |
4722 | u32 tmp; |
4723 | ||
089d034e | 4724 | if (!enable_ept) |
f51770ed | 4725 | return 0; |
a255d479 TC |
4726 | |
4727 | /* Protect kvm->arch.ept_identity_pagetable_done. */ | |
4728 | mutex_lock(&kvm->slots_lock); | |
4729 | ||
f51770ed | 4730 | if (likely(kvm->arch.ept_identity_pagetable_done)) |
a255d479 | 4731 | goto out2; |
a255d479 | 4732 | |
b927a3ce | 4733 | identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT; |
a255d479 TC |
4734 | |
4735 | r = alloc_identity_pagetable(kvm); | |
f51770ed | 4736 | if (r < 0) |
a255d479 TC |
4737 | goto out2; |
4738 | ||
40dcaa9f | 4739 | idx = srcu_read_lock(&kvm->srcu); |
b7ebfb05 SY |
4740 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); |
4741 | if (r < 0) | |
4742 | goto out; | |
4743 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
4744 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
4745 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
4746 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
4747 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
4748 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
4749 | if (r < 0) | |
4750 | goto out; | |
4751 | } | |
4752 | kvm->arch.ept_identity_pagetable_done = true; | |
f51770ed | 4753 | |
b7ebfb05 | 4754 | out: |
40dcaa9f | 4755 | srcu_read_unlock(&kvm->srcu, idx); |
a255d479 TC |
4756 | |
4757 | out2: | |
4758 | mutex_unlock(&kvm->slots_lock); | |
f51770ed | 4759 | return r; |
b7ebfb05 SY |
4760 | } |
4761 | ||
6aa8b732 AK |
4762 | static void seg_setup(int seg) |
4763 | { | |
772e0318 | 4764 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
3a624e29 | 4765 | unsigned int ar; |
6aa8b732 AK |
4766 | |
4767 | vmcs_write16(sf->selector, 0); | |
4768 | vmcs_writel(sf->base, 0); | |
4769 | vmcs_write32(sf->limit, 0xffff); | |
d54d07b2 GN |
4770 | ar = 0x93; |
4771 | if (seg == VCPU_SREG_CS) | |
4772 | ar |= 0x08; /* code segment */ | |
3a624e29 NK |
4773 | |
4774 | vmcs_write32(sf->ar_bytes, ar); | |
6aa8b732 AK |
4775 | } |
4776 | ||
f78e0e2e SY |
4777 | static int alloc_apic_access_page(struct kvm *kvm) |
4778 | { | |
4484141a | 4779 | struct page *page; |
f78e0e2e SY |
4780 | int r = 0; |
4781 | ||
79fac95e | 4782 | mutex_lock(&kvm->slots_lock); |
c24ae0dc | 4783 | if (kvm->arch.apic_access_page_done) |
f78e0e2e | 4784 | goto out; |
1d8007bd PB |
4785 | r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, |
4786 | APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); | |
f78e0e2e SY |
4787 | if (r) |
4788 | goto out; | |
72dc67a6 | 4789 | |
73a6d941 | 4790 | page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
4484141a XG |
4791 | if (is_error_page(page)) { |
4792 | r = -EFAULT; | |
4793 | goto out; | |
4794 | } | |
4795 | ||
c24ae0dc TC |
4796 | /* |
4797 | * Do not pin the page in memory, so that memory hot-unplug | |
4798 | * is able to migrate it. | |
4799 | */ | |
4800 | put_page(page); | |
4801 | kvm->arch.apic_access_page_done = true; | |
f78e0e2e | 4802 | out: |
79fac95e | 4803 | mutex_unlock(&kvm->slots_lock); |
f78e0e2e SY |
4804 | return r; |
4805 | } | |
4806 | ||
b7ebfb05 SY |
4807 | static int alloc_identity_pagetable(struct kvm *kvm) |
4808 | { | |
a255d479 TC |
4809 | /* Called with kvm->slots_lock held. */ |
4810 | ||
b7ebfb05 SY |
4811 | int r = 0; |
4812 | ||
a255d479 TC |
4813 | BUG_ON(kvm->arch.ept_identity_pagetable_done); |
4814 | ||
1d8007bd PB |
4815 | r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, |
4816 | kvm->arch.ept_identity_map_addr, PAGE_SIZE); | |
b7ebfb05 | 4817 | |
b7ebfb05 SY |
4818 | return r; |
4819 | } | |
4820 | ||
991e7a0e | 4821 | static int allocate_vpid(void) |
2384d2b3 SY |
4822 | { |
4823 | int vpid; | |
4824 | ||
919818ab | 4825 | if (!enable_vpid) |
991e7a0e | 4826 | return 0; |
2384d2b3 SY |
4827 | spin_lock(&vmx_vpid_lock); |
4828 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
991e7a0e | 4829 | if (vpid < VMX_NR_VPIDS) |
2384d2b3 | 4830 | __set_bit(vpid, vmx_vpid_bitmap); |
991e7a0e WL |
4831 | else |
4832 | vpid = 0; | |
2384d2b3 | 4833 | spin_unlock(&vmx_vpid_lock); |
991e7a0e | 4834 | return vpid; |
2384d2b3 SY |
4835 | } |
4836 | ||
991e7a0e | 4837 | static void free_vpid(int vpid) |
cdbecfc3 | 4838 | { |
991e7a0e | 4839 | if (!enable_vpid || vpid == 0) |
cdbecfc3 LJ |
4840 | return; |
4841 | spin_lock(&vmx_vpid_lock); | |
991e7a0e | 4842 | __clear_bit(vpid, vmx_vpid_bitmap); |
cdbecfc3 LJ |
4843 | spin_unlock(&vmx_vpid_lock); |
4844 | } | |
4845 | ||
8d14695f YZ |
4846 | #define MSR_TYPE_R 1 |
4847 | #define MSR_TYPE_W 2 | |
4848 | static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, | |
4849 | u32 msr, int type) | |
25c5f225 | 4850 | { |
3e7c73e9 | 4851 | int f = sizeof(unsigned long); |
25c5f225 SY |
4852 | |
4853 | if (!cpu_has_vmx_msr_bitmap()) | |
4854 | return; | |
4855 | ||
4856 | /* | |
4857 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
4858 | * have the write-low and read-high bitmap offsets the wrong way round. | |
4859 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
4860 | */ | |
25c5f225 | 4861 | if (msr <= 0x1fff) { |
8d14695f YZ |
4862 | if (type & MSR_TYPE_R) |
4863 | /* read-low */ | |
4864 | __clear_bit(msr, msr_bitmap + 0x000 / f); | |
4865 | ||
4866 | if (type & MSR_TYPE_W) | |
4867 | /* write-low */ | |
4868 | __clear_bit(msr, msr_bitmap + 0x800 / f); | |
4869 | ||
25c5f225 SY |
4870 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { |
4871 | msr &= 0x1fff; | |
8d14695f YZ |
4872 | if (type & MSR_TYPE_R) |
4873 | /* read-high */ | |
4874 | __clear_bit(msr, msr_bitmap + 0x400 / f); | |
4875 | ||
4876 | if (type & MSR_TYPE_W) | |
4877 | /* write-high */ | |
4878 | __clear_bit(msr, msr_bitmap + 0xc00 / f); | |
4879 | ||
4880 | } | |
4881 | } | |
4882 | ||
f2b93280 WV |
4883 | /* |
4884 | * If a msr is allowed by L0, we should check whether it is allowed by L1. | |
4885 | * The corresponding bit will be cleared unless both of L0 and L1 allow it. | |
4886 | */ | |
4887 | static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1, | |
4888 | unsigned long *msr_bitmap_nested, | |
4889 | u32 msr, int type) | |
4890 | { | |
4891 | int f = sizeof(unsigned long); | |
4892 | ||
4893 | if (!cpu_has_vmx_msr_bitmap()) { | |
4894 | WARN_ON(1); | |
4895 | return; | |
4896 | } | |
4897 | ||
4898 | /* | |
4899 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
4900 | * have the write-low and read-high bitmap offsets the wrong way round. | |
4901 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
4902 | */ | |
4903 | if (msr <= 0x1fff) { | |
4904 | if (type & MSR_TYPE_R && | |
4905 | !test_bit(msr, msr_bitmap_l1 + 0x000 / f)) | |
4906 | /* read-low */ | |
4907 | __clear_bit(msr, msr_bitmap_nested + 0x000 / f); | |
4908 | ||
4909 | if (type & MSR_TYPE_W && | |
4910 | !test_bit(msr, msr_bitmap_l1 + 0x800 / f)) | |
4911 | /* write-low */ | |
4912 | __clear_bit(msr, msr_bitmap_nested + 0x800 / f); | |
4913 | ||
4914 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
4915 | msr &= 0x1fff; | |
4916 | if (type & MSR_TYPE_R && | |
4917 | !test_bit(msr, msr_bitmap_l1 + 0x400 / f)) | |
4918 | /* read-high */ | |
4919 | __clear_bit(msr, msr_bitmap_nested + 0x400 / f); | |
4920 | ||
4921 | if (type & MSR_TYPE_W && | |
4922 | !test_bit(msr, msr_bitmap_l1 + 0xc00 / f)) | |
4923 | /* write-high */ | |
4924 | __clear_bit(msr, msr_bitmap_nested + 0xc00 / f); | |
4925 | ||
4926 | } | |
4927 | } | |
4928 | ||
5897297b AK |
4929 | static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only) |
4930 | { | |
4931 | if (!longmode_only) | |
8d14695f YZ |
4932 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, |
4933 | msr, MSR_TYPE_R | MSR_TYPE_W); | |
4934 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, | |
4935 | msr, MSR_TYPE_R | MSR_TYPE_W); | |
4936 | } | |
4937 | ||
2e69f865 | 4938 | static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active) |
8d14695f | 4939 | { |
f6e90f9e | 4940 | if (apicv_active) { |
c63e4563 | 4941 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv, |
2e69f865 | 4942 | msr, type); |
c63e4563 | 4943 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv, |
2e69f865 | 4944 | msr, type); |
f6e90f9e | 4945 | } else { |
c63e4563 | 4946 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic, |
2e69f865 | 4947 | msr, type); |
c63e4563 | 4948 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic, |
2e69f865 | 4949 | msr, type); |
f6e90f9e | 4950 | } |
5897297b AK |
4951 | } |
4952 | ||
d62caabb | 4953 | static bool vmx_get_enable_apicv(void) |
d50ab6c1 | 4954 | { |
d62caabb | 4955 | return enable_apicv; |
d50ab6c1 PB |
4956 | } |
4957 | ||
705699a1 WV |
4958 | static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu) |
4959 | { | |
4960 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4961 | int max_irr; | |
4962 | void *vapic_page; | |
4963 | u16 status; | |
4964 | ||
4965 | if (vmx->nested.pi_desc && | |
4966 | vmx->nested.pi_pending) { | |
4967 | vmx->nested.pi_pending = false; | |
4968 | if (!pi_test_and_clear_on(vmx->nested.pi_desc)) | |
4969 | return 0; | |
4970 | ||
4971 | max_irr = find_last_bit( | |
4972 | (unsigned long *)vmx->nested.pi_desc->pir, 256); | |
4973 | ||
4974 | if (max_irr == 256) | |
4975 | return 0; | |
4976 | ||
4977 | vapic_page = kmap(vmx->nested.virtual_apic_page); | |
4978 | if (!vapic_page) { | |
4979 | WARN_ON(1); | |
4980 | return -ENOMEM; | |
4981 | } | |
4982 | __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page); | |
4983 | kunmap(vmx->nested.virtual_apic_page); | |
4984 | ||
4985 | status = vmcs_read16(GUEST_INTR_STATUS); | |
4986 | if ((u8)max_irr > ((u8)status & 0xff)) { | |
4987 | status &= ~0xff; | |
4988 | status |= (u8)max_irr; | |
4989 | vmcs_write16(GUEST_INTR_STATUS, status); | |
4990 | } | |
4991 | } | |
4992 | return 0; | |
4993 | } | |
4994 | ||
21bc8dc5 RK |
4995 | static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu) |
4996 | { | |
4997 | #ifdef CONFIG_SMP | |
4998 | if (vcpu->mode == IN_GUEST_MODE) { | |
28b835d6 FW |
4999 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
5000 | ||
5001 | /* | |
5002 | * Currently, we don't support urgent interrupt, | |
5003 | * all interrupts are recognized as non-urgent | |
5004 | * interrupt, so we cannot post interrupts when | |
5005 | * 'SN' is set. | |
5006 | * | |
5007 | * If the vcpu is in guest mode, it means it is | |
5008 | * running instead of being scheduled out and | |
5009 | * waiting in the run queue, and that's the only | |
5010 | * case when 'SN' is set currently, warning if | |
5011 | * 'SN' is set. | |
5012 | */ | |
5013 | WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc)); | |
5014 | ||
21bc8dc5 RK |
5015 | apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), |
5016 | POSTED_INTR_VECTOR); | |
5017 | return true; | |
5018 | } | |
5019 | #endif | |
5020 | return false; | |
5021 | } | |
5022 | ||
705699a1 WV |
5023 | static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, |
5024 | int vector) | |
5025 | { | |
5026 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5027 | ||
5028 | if (is_guest_mode(vcpu) && | |
5029 | vector == vmx->nested.posted_intr_nv) { | |
5030 | /* the PIR and ON have been set by L1. */ | |
21bc8dc5 | 5031 | kvm_vcpu_trigger_posted_interrupt(vcpu); |
705699a1 WV |
5032 | /* |
5033 | * If a posted intr is not recognized by hardware, | |
5034 | * we will accomplish it in the next vmentry. | |
5035 | */ | |
5036 | vmx->nested.pi_pending = true; | |
5037 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
5038 | return 0; | |
5039 | } | |
5040 | return -1; | |
5041 | } | |
a20ed54d YZ |
5042 | /* |
5043 | * Send interrupt to vcpu via posted interrupt way. | |
5044 | * 1. If target vcpu is running(non-root mode), send posted interrupt | |
5045 | * notification to vcpu and hardware will sync PIR to vIRR atomically. | |
5046 | * 2. If target vcpu isn't running(root mode), kick it to pick up the | |
5047 | * interrupt from PIR in next vmentry. | |
5048 | */ | |
5049 | static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) | |
5050 | { | |
5051 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5052 | int r; | |
5053 | ||
705699a1 WV |
5054 | r = vmx_deliver_nested_posted_interrupt(vcpu, vector); |
5055 | if (!r) | |
5056 | return; | |
5057 | ||
a20ed54d YZ |
5058 | if (pi_test_and_set_pir(vector, &vmx->pi_desc)) |
5059 | return; | |
5060 | ||
5061 | r = pi_test_and_set_on(&vmx->pi_desc); | |
5062 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
21bc8dc5 | 5063 | if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu)) |
a20ed54d YZ |
5064 | kvm_vcpu_kick(vcpu); |
5065 | } | |
5066 | ||
5067 | static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) | |
5068 | { | |
5069 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5070 | ||
ad361091 | 5071 | if (!pi_test_on(&vmx->pi_desc)) |
a20ed54d YZ |
5072 | return; |
5073 | ||
ad361091 PB |
5074 | pi_clear_on(&vmx->pi_desc); |
5075 | /* | |
5076 | * IOMMU can write to PIR.ON, so the barrier matters even on UP. | |
5077 | * But on x86 this is just a compiler barrier anyway. | |
5078 | */ | |
5079 | smp_mb__after_atomic(); | |
a20ed54d YZ |
5080 | kvm_apic_update_irr(vcpu, vmx->pi_desc.pir); |
5081 | } | |
5082 | ||
a3a8ff8e NHE |
5083 | /* |
5084 | * Set up the vmcs's constant host-state fields, i.e., host-state fields that | |
5085 | * will not change in the lifetime of the guest. | |
5086 | * Note that host-state that does change is set elsewhere. E.g., host-state | |
5087 | * that is set differently for each CPU is set in vmx_vcpu_load(), not here. | |
5088 | */ | |
a547c6db | 5089 | static void vmx_set_constant_host_state(struct vcpu_vmx *vmx) |
a3a8ff8e NHE |
5090 | { |
5091 | u32 low32, high32; | |
5092 | unsigned long tmpl; | |
5093 | struct desc_ptr dt; | |
d974baa3 | 5094 | unsigned long cr4; |
a3a8ff8e | 5095 | |
b1a74bf8 | 5096 | vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */ |
a3a8ff8e NHE |
5097 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ |
5098 | ||
d974baa3 | 5099 | /* Save the most likely value for this task's CR4 in the VMCS. */ |
1e02ce4c | 5100 | cr4 = cr4_read_shadow(); |
d974baa3 AL |
5101 | vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ |
5102 | vmx->host_state.vmcs_host_cr4 = cr4; | |
5103 | ||
a3a8ff8e | 5104 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ |
b2da15ac AK |
5105 | #ifdef CONFIG_X86_64 |
5106 | /* | |
5107 | * Load null selectors, so we can avoid reloading them in | |
5108 | * __vmx_load_host_state(), in case userspace uses the null selectors | |
5109 | * too (the expected case). | |
5110 | */ | |
5111 | vmcs_write16(HOST_DS_SELECTOR, 0); | |
5112 | vmcs_write16(HOST_ES_SELECTOR, 0); | |
5113 | #else | |
a3a8ff8e NHE |
5114 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
5115 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
b2da15ac | 5116 | #endif |
a3a8ff8e NHE |
5117 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
5118 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
5119 | ||
5120 | native_store_idt(&dt); | |
5121 | vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */ | |
a547c6db | 5122 | vmx->host_idt_base = dt.address; |
a3a8ff8e | 5123 | |
83287ea4 | 5124 | vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */ |
a3a8ff8e NHE |
5125 | |
5126 | rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); | |
5127 | vmcs_write32(HOST_IA32_SYSENTER_CS, low32); | |
5128 | rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); | |
5129 | vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ | |
5130 | ||
5131 | if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { | |
5132 | rdmsr(MSR_IA32_CR_PAT, low32, high32); | |
5133 | vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); | |
5134 | } | |
5135 | } | |
5136 | ||
bf8179a0 NHE |
5137 | static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) |
5138 | { | |
5139 | vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; | |
5140 | if (enable_ept) | |
5141 | vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; | |
fe3ef05c NHE |
5142 | if (is_guest_mode(&vmx->vcpu)) |
5143 | vmx->vcpu.arch.cr4_guest_owned_bits &= | |
5144 | ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; | |
bf8179a0 NHE |
5145 | vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); |
5146 | } | |
5147 | ||
01e439be YZ |
5148 | static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) |
5149 | { | |
5150 | u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; | |
5151 | ||
d62caabb | 5152 | if (!kvm_vcpu_apicv_active(&vmx->vcpu)) |
01e439be | 5153 | pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; |
64672c95 YJ |
5154 | /* Enable the preemption timer dynamically */ |
5155 | pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
5156 | return pin_based_exec_ctrl; |
5157 | } | |
5158 | ||
d62caabb AS |
5159 | static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) |
5160 | { | |
5161 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5162 | ||
5163 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); | |
3ce424e4 RK |
5164 | if (cpu_has_secondary_exec_ctrls()) { |
5165 | if (kvm_vcpu_apicv_active(vcpu)) | |
5166 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
5167 | SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
5168 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
5169 | else | |
5170 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, | |
5171 | SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
5172 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
5173 | } | |
5174 | ||
5175 | if (cpu_has_vmx_msr_bitmap()) | |
5176 | vmx_set_msr_bitmap(vcpu); | |
d62caabb AS |
5177 | } |
5178 | ||
bf8179a0 NHE |
5179 | static u32 vmx_exec_control(struct vcpu_vmx *vmx) |
5180 | { | |
5181 | u32 exec_control = vmcs_config.cpu_based_exec_ctrl; | |
d16c293e PB |
5182 | |
5183 | if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) | |
5184 | exec_control &= ~CPU_BASED_MOV_DR_EXITING; | |
5185 | ||
35754c98 | 5186 | if (!cpu_need_tpr_shadow(&vmx->vcpu)) { |
bf8179a0 NHE |
5187 | exec_control &= ~CPU_BASED_TPR_SHADOW; |
5188 | #ifdef CONFIG_X86_64 | |
5189 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
5190 | CPU_BASED_CR8_LOAD_EXITING; | |
5191 | #endif | |
5192 | } | |
5193 | if (!enable_ept) | |
5194 | exec_control |= CPU_BASED_CR3_STORE_EXITING | | |
5195 | CPU_BASED_CR3_LOAD_EXITING | | |
5196 | CPU_BASED_INVLPG_EXITING; | |
5197 | return exec_control; | |
5198 | } | |
5199 | ||
5200 | static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx) | |
5201 | { | |
5202 | u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; | |
35754c98 | 5203 | if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu)) |
bf8179a0 NHE |
5204 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; |
5205 | if (vmx->vpid == 0) | |
5206 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
5207 | if (!enable_ept) { | |
5208 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; | |
5209 | enable_unrestricted_guest = 0; | |
ad756a16 MJ |
5210 | /* Enable INVPCID for non-ept guests may cause performance regression. */ |
5211 | exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; | |
bf8179a0 NHE |
5212 | } |
5213 | if (!enable_unrestricted_guest) | |
5214 | exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
5215 | if (!ple_gap) | |
5216 | exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
d62caabb | 5217 | if (!kvm_vcpu_apicv_active(&vmx->vcpu)) |
c7c9c56c YZ |
5218 | exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | |
5219 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
8d14695f | 5220 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; |
abc4fc58 AG |
5221 | /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD |
5222 | (handle_vmptrld). | |
5223 | We can NOT enable shadow_vmcs here because we don't have yet | |
5224 | a current VMCS12 | |
5225 | */ | |
5226 | exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; | |
a3eaa864 KH |
5227 | |
5228 | if (!enable_pml) | |
5229 | exec_control &= ~SECONDARY_EXEC_ENABLE_PML; | |
843e4330 | 5230 | |
bf8179a0 NHE |
5231 | return exec_control; |
5232 | } | |
5233 | ||
ce88decf XG |
5234 | static void ept_set_mmio_spte_mask(void) |
5235 | { | |
5236 | /* | |
5237 | * EPT Misconfigurations can be generated if the value of bits 2:0 | |
5238 | * of an EPT paging-structure entry is 110b (write/execute). | |
885032b9 | 5239 | * Also, magic bits (0x3ull << 62) is set to quickly identify mmio |
ce88decf XG |
5240 | * spte. |
5241 | */ | |
885032b9 | 5242 | kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull); |
ce88decf XG |
5243 | } |
5244 | ||
f53cd63c | 5245 | #define VMX_XSS_EXIT_BITMAP 0 |
6aa8b732 AK |
5246 | /* |
5247 | * Sets up the vmcs for emulated real mode. | |
5248 | */ | |
8b9cf98c | 5249 | static int vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 | 5250 | { |
2e4ce7f5 | 5251 | #ifdef CONFIG_X86_64 |
6aa8b732 | 5252 | unsigned long a; |
2e4ce7f5 | 5253 | #endif |
6aa8b732 | 5254 | int i; |
6aa8b732 | 5255 | |
6aa8b732 | 5256 | /* I/O */ |
3e7c73e9 AK |
5257 | vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a)); |
5258 | vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b)); | |
6aa8b732 | 5259 | |
4607c2d7 AG |
5260 | if (enable_shadow_vmcs) { |
5261 | vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap)); | |
5262 | vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap)); | |
5263 | } | |
25c5f225 | 5264 | if (cpu_has_vmx_msr_bitmap()) |
5897297b | 5265 | vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy)); |
25c5f225 | 5266 | |
6aa8b732 AK |
5267 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
5268 | ||
6aa8b732 | 5269 | /* Control */ |
01e439be | 5270 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); |
64672c95 | 5271 | vmx->hv_deadline_tsc = -1; |
6e5d865c | 5272 | |
bf8179a0 | 5273 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx)); |
6aa8b732 | 5274 | |
dfa169bb | 5275 | if (cpu_has_secondary_exec_ctrls()) { |
bf8179a0 NHE |
5276 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, |
5277 | vmx_secondary_exec_control(vmx)); | |
dfa169bb | 5278 | } |
f78e0e2e | 5279 | |
d62caabb | 5280 | if (kvm_vcpu_apicv_active(&vmx->vcpu)) { |
c7c9c56c YZ |
5281 | vmcs_write64(EOI_EXIT_BITMAP0, 0); |
5282 | vmcs_write64(EOI_EXIT_BITMAP1, 0); | |
5283 | vmcs_write64(EOI_EXIT_BITMAP2, 0); | |
5284 | vmcs_write64(EOI_EXIT_BITMAP3, 0); | |
5285 | ||
5286 | vmcs_write16(GUEST_INTR_STATUS, 0); | |
01e439be | 5287 | |
0bcf261c | 5288 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); |
01e439be | 5289 | vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); |
c7c9c56c YZ |
5290 | } |
5291 | ||
4b8d54f9 ZE |
5292 | if (ple_gap) { |
5293 | vmcs_write32(PLE_GAP, ple_gap); | |
a7653ecd RK |
5294 | vmx->ple_window = ple_window; |
5295 | vmx->ple_window_dirty = true; | |
4b8d54f9 ZE |
5296 | } |
5297 | ||
c3707958 XG |
5298 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); |
5299 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); | |
6aa8b732 AK |
5300 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
5301 | ||
9581d442 AK |
5302 | vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ |
5303 | vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ | |
a547c6db | 5304 | vmx_set_constant_host_state(vmx); |
05b3e0c2 | 5305 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
5306 | rdmsrl(MSR_FS_BASE, a); |
5307 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
5308 | rdmsrl(MSR_GS_BASE, a); | |
5309 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
5310 | #else | |
5311 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
5312 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
5313 | #endif | |
5314 | ||
2cc51560 ED |
5315 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
5316 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
61d2ef2c | 5317 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host)); |
2cc51560 | 5318 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); |
61d2ef2c | 5319 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); |
6aa8b732 | 5320 | |
74545705 RK |
5321 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) |
5322 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); | |
468d472f | 5323 | |
03916db9 | 5324 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { |
6aa8b732 AK |
5325 | u32 index = vmx_msr_index[i]; |
5326 | u32 data_low, data_high; | |
a2fa3e9f | 5327 | int j = vmx->nmsrs; |
6aa8b732 AK |
5328 | |
5329 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
5330 | continue; | |
432bd6cb AK |
5331 | if (wrmsr_safe(index, data_low, data_high) < 0) |
5332 | continue; | |
26bb0981 AK |
5333 | vmx->guest_msrs[j].index = i; |
5334 | vmx->guest_msrs[j].data = 0; | |
d5696725 | 5335 | vmx->guest_msrs[j].mask = -1ull; |
a2fa3e9f | 5336 | ++vmx->nmsrs; |
6aa8b732 | 5337 | } |
6aa8b732 | 5338 | |
2961e876 GN |
5339 | |
5340 | vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl); | |
6aa8b732 AK |
5341 | |
5342 | /* 22.2.1, 20.8.1 */ | |
2961e876 | 5343 | vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl); |
1c3d14fe | 5344 | |
e00c8cf2 | 5345 | vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL); |
bf8179a0 | 5346 | set_cr4_guest_host_mask(vmx); |
e00c8cf2 | 5347 | |
f53cd63c WL |
5348 | if (vmx_xsaves_supported()) |
5349 | vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); | |
5350 | ||
4e59516a PF |
5351 | if (enable_pml) { |
5352 | ASSERT(vmx->pml_pg); | |
5353 | vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); | |
5354 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
5355 | } | |
5356 | ||
e00c8cf2 AK |
5357 | return 0; |
5358 | } | |
5359 | ||
d28bc9dd | 5360 | static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e00c8cf2 AK |
5361 | { |
5362 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
58cb628d | 5363 | struct msr_data apic_base_msr; |
d28bc9dd | 5364 | u64 cr0; |
e00c8cf2 | 5365 | |
7ffd92c5 | 5366 | vmx->rmode.vm86_active = 0; |
e00c8cf2 | 5367 | |
3b86cd99 JK |
5368 | vmx->soft_vnmi_blocked = 0; |
5369 | ||
ad312c7c | 5370 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
d28bc9dd NA |
5371 | kvm_set_cr8(vcpu, 0); |
5372 | ||
5373 | if (!init_event) { | |
5374 | apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | | |
5375 | MSR_IA32_APICBASE_ENABLE; | |
5376 | if (kvm_vcpu_is_reset_bsp(vcpu)) | |
5377 | apic_base_msr.data |= MSR_IA32_APICBASE_BSP; | |
5378 | apic_base_msr.host_initiated = true; | |
5379 | kvm_set_apic_base(vcpu, &apic_base_msr); | |
5380 | } | |
e00c8cf2 | 5381 | |
2fb92db1 AK |
5382 | vmx_segment_cache_clear(vmx); |
5383 | ||
5706be0d | 5384 | seg_setup(VCPU_SREG_CS); |
66450a21 | 5385 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); |
f3531054 | 5386 | vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); |
e00c8cf2 AK |
5387 | |
5388 | seg_setup(VCPU_SREG_DS); | |
5389 | seg_setup(VCPU_SREG_ES); | |
5390 | seg_setup(VCPU_SREG_FS); | |
5391 | seg_setup(VCPU_SREG_GS); | |
5392 | seg_setup(VCPU_SREG_SS); | |
5393 | ||
5394 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
5395 | vmcs_writel(GUEST_TR_BASE, 0); | |
5396 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
5397 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
5398 | ||
5399 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
5400 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
5401 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
5402 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
5403 | ||
d28bc9dd NA |
5404 | if (!init_event) { |
5405 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
5406 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
5407 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
5408 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
5409 | } | |
e00c8cf2 AK |
5410 | |
5411 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
66450a21 | 5412 | kvm_rip_write(vcpu, 0xfff0); |
e00c8cf2 | 5413 | |
e00c8cf2 AK |
5414 | vmcs_writel(GUEST_GDTR_BASE, 0); |
5415 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
5416 | ||
5417 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
5418 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
5419 | ||
443381a8 | 5420 | vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); |
e00c8cf2 | 5421 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); |
f3531054 | 5422 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); |
e00c8cf2 | 5423 | |
e00c8cf2 AK |
5424 | setup_msrs(vmx); |
5425 | ||
6aa8b732 AK |
5426 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
5427 | ||
d28bc9dd | 5428 | if (cpu_has_vmx_tpr_shadow() && !init_event) { |
f78e0e2e | 5429 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); |
35754c98 | 5430 | if (cpu_need_tpr_shadow(vcpu)) |
f78e0e2e | 5431 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, |
d28bc9dd | 5432 | __pa(vcpu->arch.apic->regs)); |
f78e0e2e SY |
5433 | vmcs_write32(TPR_THRESHOLD, 0); |
5434 | } | |
5435 | ||
a73896cb | 5436 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
6aa8b732 | 5437 | |
d62caabb | 5438 | if (kvm_vcpu_apicv_active(vcpu)) |
01e439be YZ |
5439 | memset(&vmx->pi_desc, 0, sizeof(struct pi_desc)); |
5440 | ||
2384d2b3 SY |
5441 | if (vmx->vpid != 0) |
5442 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
5443 | ||
d28bc9dd | 5444 | cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; |
d28bc9dd | 5445 | vmx->vcpu.arch.cr0 = cr0; |
f2463247 | 5446 | vmx_set_cr0(vcpu, cr0); /* enter rmode */ |
d28bc9dd | 5447 | vmx_set_cr4(vcpu, 0); |
5690891b | 5448 | vmx_set_efer(vcpu, 0); |
d28bc9dd NA |
5449 | vmx_fpu_activate(vcpu); |
5450 | update_exception_bitmap(vcpu); | |
6aa8b732 | 5451 | |
dd5f5341 | 5452 | vpid_sync_context(vmx->vpid); |
6aa8b732 AK |
5453 | } |
5454 | ||
b6f1250e NHE |
5455 | /* |
5456 | * In nested virtualization, check if L1 asked to exit on external interrupts. | |
5457 | * For most existing hypervisors, this will always return true. | |
5458 | */ | |
5459 | static bool nested_exit_on_intr(struct kvm_vcpu *vcpu) | |
5460 | { | |
5461 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
5462 | PIN_BASED_EXT_INTR_MASK; | |
5463 | } | |
5464 | ||
77b0f5d6 BD |
5465 | /* |
5466 | * In nested virtualization, check if L1 has set | |
5467 | * VM_EXIT_ACK_INTR_ON_EXIT | |
5468 | */ | |
5469 | static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu) | |
5470 | { | |
5471 | return get_vmcs12(vcpu)->vm_exit_controls & | |
5472 | VM_EXIT_ACK_INTR_ON_EXIT; | |
5473 | } | |
5474 | ||
ea8ceb83 JK |
5475 | static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu) |
5476 | { | |
5477 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
5478 | PIN_BASED_NMI_EXITING; | |
5479 | } | |
5480 | ||
c9a7953f | 5481 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
3b86cd99 JK |
5482 | { |
5483 | u32 cpu_based_vm_exec_control; | |
730dca42 | 5484 | |
3b86cd99 JK |
5485 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); |
5486 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; | |
5487 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
5488 | } | |
5489 | ||
c9a7953f | 5490 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
3b86cd99 JK |
5491 | { |
5492 | u32 cpu_based_vm_exec_control; | |
5493 | ||
c9a7953f JK |
5494 | if (!cpu_has_virtual_nmis() || |
5495 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { | |
5496 | enable_irq_window(vcpu); | |
5497 | return; | |
5498 | } | |
3b86cd99 JK |
5499 | |
5500 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
5501 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING; | |
5502 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
5503 | } | |
5504 | ||
66fd3f7f | 5505 | static void vmx_inject_irq(struct kvm_vcpu *vcpu) |
85f455f7 | 5506 | { |
9c8cba37 | 5507 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
66fd3f7f GN |
5508 | uint32_t intr; |
5509 | int irq = vcpu->arch.interrupt.nr; | |
9c8cba37 | 5510 | |
229456fc | 5511 | trace_kvm_inj_virq(irq); |
2714d1d3 | 5512 | |
fa89a817 | 5513 | ++vcpu->stat.irq_injections; |
7ffd92c5 | 5514 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
5515 | int inc_eip = 0; |
5516 | if (vcpu->arch.interrupt.soft) | |
5517 | inc_eip = vcpu->arch.event_exit_inst_len; | |
5518 | if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE) | |
a92601bb | 5519 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
85f455f7 ED |
5520 | return; |
5521 | } | |
66fd3f7f GN |
5522 | intr = irq | INTR_INFO_VALID_MASK; |
5523 | if (vcpu->arch.interrupt.soft) { | |
5524 | intr |= INTR_TYPE_SOFT_INTR; | |
5525 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
5526 | vmx->vcpu.arch.event_exit_inst_len); | |
5527 | } else | |
5528 | intr |= INTR_TYPE_EXT_INTR; | |
5529 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); | |
85f455f7 ED |
5530 | } |
5531 | ||
f08864b4 SY |
5532 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
5533 | { | |
66a5a347 JK |
5534 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
5535 | ||
c5a6d5f7 WL |
5536 | if (!is_guest_mode(vcpu)) { |
5537 | if (!cpu_has_virtual_nmis()) { | |
5538 | /* | |
5539 | * Tracking the NMI-blocked state in software is built upon | |
5540 | * finding the next open IRQ window. This, in turn, depends on | |
5541 | * well-behaving guests: They have to keep IRQs disabled at | |
5542 | * least as long as the NMI handler runs. Otherwise we may | |
5543 | * cause NMI nesting, maybe breaking the guest. But as this is | |
5544 | * highly unlikely, we can live with the residual risk. | |
5545 | */ | |
5546 | vmx->soft_vnmi_blocked = 1; | |
5547 | vmx->vnmi_blocked_time = 0; | |
5548 | } | |
0b6ac343 | 5549 | |
c5a6d5f7 WL |
5550 | ++vcpu->stat.nmi_injections; |
5551 | vmx->nmi_known_unmasked = false; | |
3b86cd99 JK |
5552 | } |
5553 | ||
7ffd92c5 | 5554 | if (vmx->rmode.vm86_active) { |
71f9833b | 5555 | if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE) |
a92601bb | 5556 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
66a5a347 JK |
5557 | return; |
5558 | } | |
c5a6d5f7 | 5559 | |
f08864b4 SY |
5560 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
5561 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
f08864b4 SY |
5562 | } |
5563 | ||
3cfc3092 JK |
5564 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) |
5565 | { | |
5566 | if (!cpu_has_virtual_nmis()) | |
5567 | return to_vmx(vcpu)->soft_vnmi_blocked; | |
9d58b931 AK |
5568 | if (to_vmx(vcpu)->nmi_known_unmasked) |
5569 | return false; | |
c332c83a | 5570 | return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; |
3cfc3092 JK |
5571 | } |
5572 | ||
5573 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
5574 | { | |
5575 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5576 | ||
5577 | if (!cpu_has_virtual_nmis()) { | |
5578 | if (vmx->soft_vnmi_blocked != masked) { | |
5579 | vmx->soft_vnmi_blocked = masked; | |
5580 | vmx->vnmi_blocked_time = 0; | |
5581 | } | |
5582 | } else { | |
9d58b931 | 5583 | vmx->nmi_known_unmasked = !masked; |
3cfc3092 JK |
5584 | if (masked) |
5585 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
5586 | GUEST_INTR_STATE_NMI); | |
5587 | else | |
5588 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
5589 | GUEST_INTR_STATE_NMI); | |
5590 | } | |
5591 | } | |
5592 | ||
2505dc9f JK |
5593 | static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) |
5594 | { | |
b6b8a145 JK |
5595 | if (to_vmx(vcpu)->nested.nested_run_pending) |
5596 | return 0; | |
ea8ceb83 | 5597 | |
2505dc9f JK |
5598 | if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked) |
5599 | return 0; | |
5600 | ||
5601 | return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & | |
5602 | (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI | |
5603 | | GUEST_INTR_STATE_NMI)); | |
5604 | } | |
5605 | ||
78646121 GN |
5606 | static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) |
5607 | { | |
b6b8a145 JK |
5608 | return (!to_vmx(vcpu)->nested.nested_run_pending && |
5609 | vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
c4282df9 GN |
5610 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
5611 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); | |
78646121 GN |
5612 | } |
5613 | ||
cbc94022 IE |
5614 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
5615 | { | |
5616 | int ret; | |
cbc94022 | 5617 | |
1d8007bd PB |
5618 | ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, |
5619 | PAGE_SIZE * 3); | |
cbc94022 IE |
5620 | if (ret) |
5621 | return ret; | |
bfc6d222 | 5622 | kvm->arch.tss_addr = addr; |
1f755a82 | 5623 | return init_rmode_tss(kvm); |
cbc94022 IE |
5624 | } |
5625 | ||
0ca1b4f4 | 5626 | static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) |
6aa8b732 | 5627 | { |
77ab6db0 | 5628 | switch (vec) { |
77ab6db0 | 5629 | case BP_VECTOR: |
c573cd22 JK |
5630 | /* |
5631 | * Update instruction length as we may reinject the exception | |
5632 | * from user space while in guest debugging mode. | |
5633 | */ | |
5634 | to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = | |
5635 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
d0bfb940 | 5636 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
0ca1b4f4 GN |
5637 | return false; |
5638 | /* fall through */ | |
5639 | case DB_VECTOR: | |
5640 | if (vcpu->guest_debug & | |
5641 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
5642 | return false; | |
d0bfb940 JK |
5643 | /* fall through */ |
5644 | case DE_VECTOR: | |
77ab6db0 JK |
5645 | case OF_VECTOR: |
5646 | case BR_VECTOR: | |
5647 | case UD_VECTOR: | |
5648 | case DF_VECTOR: | |
5649 | case SS_VECTOR: | |
5650 | case GP_VECTOR: | |
5651 | case MF_VECTOR: | |
0ca1b4f4 GN |
5652 | return true; |
5653 | break; | |
77ab6db0 | 5654 | } |
0ca1b4f4 GN |
5655 | return false; |
5656 | } | |
5657 | ||
5658 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
5659 | int vec, u32 err_code) | |
5660 | { | |
5661 | /* | |
5662 | * Instruction with address size override prefix opcode 0x67 | |
5663 | * Cause the #SS fault with 0 error code in VM86 mode. | |
5664 | */ | |
5665 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { | |
5666 | if (emulate_instruction(vcpu, 0) == EMULATE_DONE) { | |
5667 | if (vcpu->arch.halt_request) { | |
5668 | vcpu->arch.halt_request = 0; | |
5cb56059 | 5669 | return kvm_vcpu_halt(vcpu); |
0ca1b4f4 GN |
5670 | } |
5671 | return 1; | |
5672 | } | |
5673 | return 0; | |
5674 | } | |
5675 | ||
5676 | /* | |
5677 | * Forward all other exceptions that are valid in real mode. | |
5678 | * FIXME: Breaks guest debugging in real mode, needs to be fixed with | |
5679 | * the required debugging infrastructure rework. | |
5680 | */ | |
5681 | kvm_queue_exception(vcpu, vec); | |
5682 | return 1; | |
6aa8b732 AK |
5683 | } |
5684 | ||
a0861c02 AK |
5685 | /* |
5686 | * Trigger machine check on the host. We assume all the MSRs are already set up | |
5687 | * by the CPU and that we still run on the same CPU as the MCE occurred on. | |
5688 | * We pass a fake environment to the machine check handler because we want | |
5689 | * the guest to be always treated like user space, no matter what context | |
5690 | * it used internally. | |
5691 | */ | |
5692 | static void kvm_machine_check(void) | |
5693 | { | |
5694 | #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) | |
5695 | struct pt_regs regs = { | |
5696 | .cs = 3, /* Fake ring 3 no matter what the guest ran on */ | |
5697 | .flags = X86_EFLAGS_IF, | |
5698 | }; | |
5699 | ||
5700 | do_machine_check(®s, 0); | |
5701 | #endif | |
5702 | } | |
5703 | ||
851ba692 | 5704 | static int handle_machine_check(struct kvm_vcpu *vcpu) |
a0861c02 AK |
5705 | { |
5706 | /* already handled by vcpu_run */ | |
5707 | return 1; | |
5708 | } | |
5709 | ||
851ba692 | 5710 | static int handle_exception(struct kvm_vcpu *vcpu) |
6aa8b732 | 5711 | { |
1155f76a | 5712 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
851ba692 | 5713 | struct kvm_run *kvm_run = vcpu->run; |
d0bfb940 | 5714 | u32 intr_info, ex_no, error_code; |
42dbaa5a | 5715 | unsigned long cr2, rip, dr6; |
6aa8b732 AK |
5716 | u32 vect_info; |
5717 | enum emulation_result er; | |
5718 | ||
1155f76a | 5719 | vect_info = vmx->idt_vectoring_info; |
88786475 | 5720 | intr_info = vmx->exit_intr_info; |
6aa8b732 | 5721 | |
a0861c02 | 5722 | if (is_machine_check(intr_info)) |
851ba692 | 5723 | return handle_machine_check(vcpu); |
a0861c02 | 5724 | |
e4a41889 | 5725 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR) |
1b6269db | 5726 | return 1; /* already handled by vmx_vcpu_run() */ |
2ab455cc AL |
5727 | |
5728 | if (is_no_device(intr_info)) { | |
5fd86fcf | 5729 | vmx_fpu_activate(vcpu); |
2ab455cc AL |
5730 | return 1; |
5731 | } | |
5732 | ||
7aa81cc0 | 5733 | if (is_invalid_opcode(intr_info)) { |
ae1f5767 JK |
5734 | if (is_guest_mode(vcpu)) { |
5735 | kvm_queue_exception(vcpu, UD_VECTOR); | |
5736 | return 1; | |
5737 | } | |
51d8b661 | 5738 | er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 5739 | if (er != EMULATE_DONE) |
7ee5d940 | 5740 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
5741 | return 1; |
5742 | } | |
5743 | ||
6aa8b732 | 5744 | error_code = 0; |
2e11384c | 5745 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 | 5746 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
bf4ca23e XG |
5747 | |
5748 | /* | |
5749 | * The #PF with PFEC.RSVD = 1 indicates the guest is accessing | |
5750 | * MMIO, it is better to report an internal error. | |
5751 | * See the comments in vmx_handle_exit. | |
5752 | */ | |
5753 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
5754 | !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { | |
5755 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
5756 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; | |
80f0e95d | 5757 | vcpu->run->internal.ndata = 3; |
bf4ca23e XG |
5758 | vcpu->run->internal.data[0] = vect_info; |
5759 | vcpu->run->internal.data[1] = intr_info; | |
80f0e95d | 5760 | vcpu->run->internal.data[2] = error_code; |
bf4ca23e XG |
5761 | return 0; |
5762 | } | |
5763 | ||
6aa8b732 | 5764 | if (is_page_fault(intr_info)) { |
1439442c | 5765 | /* EPT won't cause page fault directly */ |
cf3ace79 | 5766 | BUG_ON(enable_ept); |
6aa8b732 | 5767 | cr2 = vmcs_readl(EXIT_QUALIFICATION); |
229456fc MT |
5768 | trace_kvm_page_fault(cr2, error_code); |
5769 | ||
3298b75c | 5770 | if (kvm_event_needs_reinjection(vcpu)) |
577bdc49 | 5771 | kvm_mmu_unprotect_page_virt(vcpu, cr2); |
dc25e89e | 5772 | return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0); |
6aa8b732 AK |
5773 | } |
5774 | ||
d0bfb940 | 5775 | ex_no = intr_info & INTR_INFO_VECTOR_MASK; |
0ca1b4f4 GN |
5776 | |
5777 | if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) | |
5778 | return handle_rmode_exception(vcpu, ex_no, error_code); | |
5779 | ||
42dbaa5a | 5780 | switch (ex_no) { |
54a20552 EN |
5781 | case AC_VECTOR: |
5782 | kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); | |
5783 | return 1; | |
42dbaa5a JK |
5784 | case DB_VECTOR: |
5785 | dr6 = vmcs_readl(EXIT_QUALIFICATION); | |
5786 | if (!(vcpu->guest_debug & | |
5787 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { | |
8246bf52 | 5788 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 5789 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
fd2a445a HD |
5790 | if (!(dr6 & ~DR6_RESERVED)) /* icebp */ |
5791 | skip_emulated_instruction(vcpu); | |
5792 | ||
42dbaa5a JK |
5793 | kvm_queue_exception(vcpu, DB_VECTOR); |
5794 | return 1; | |
5795 | } | |
5796 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; | |
5797 | kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); | |
5798 | /* fall through */ | |
5799 | case BP_VECTOR: | |
c573cd22 JK |
5800 | /* |
5801 | * Update instruction length as we may reinject #BP from | |
5802 | * user space while in guest debugging mode. Reading it for | |
5803 | * #DB as well causes no harm, it is not used in that case. | |
5804 | */ | |
5805 | vmx->vcpu.arch.event_exit_inst_len = | |
5806 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
6aa8b732 | 5807 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
0a434bb2 | 5808 | rip = kvm_rip_read(vcpu); |
d0bfb940 JK |
5809 | kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; |
5810 | kvm_run->debug.arch.exception = ex_no; | |
42dbaa5a JK |
5811 | break; |
5812 | default: | |
d0bfb940 JK |
5813 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; |
5814 | kvm_run->ex.exception = ex_no; | |
5815 | kvm_run->ex.error_code = error_code; | |
42dbaa5a | 5816 | break; |
6aa8b732 | 5817 | } |
6aa8b732 AK |
5818 | return 0; |
5819 | } | |
5820 | ||
851ba692 | 5821 | static int handle_external_interrupt(struct kvm_vcpu *vcpu) |
6aa8b732 | 5822 | { |
1165f5fe | 5823 | ++vcpu->stat.irq_exits; |
6aa8b732 AK |
5824 | return 1; |
5825 | } | |
5826 | ||
851ba692 | 5827 | static int handle_triple_fault(struct kvm_vcpu *vcpu) |
988ad74f | 5828 | { |
851ba692 | 5829 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
988ad74f AK |
5830 | return 0; |
5831 | } | |
6aa8b732 | 5832 | |
851ba692 | 5833 | static int handle_io(struct kvm_vcpu *vcpu) |
6aa8b732 | 5834 | { |
bfdaab09 | 5835 | unsigned long exit_qualification; |
6affcbed | 5836 | int size, in, string, ret; |
039576c0 | 5837 | unsigned port; |
6aa8b732 | 5838 | |
bfdaab09 | 5839 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 5840 | string = (exit_qualification & 16) != 0; |
cf8f70bf | 5841 | in = (exit_qualification & 8) != 0; |
e70669ab | 5842 | |
cf8f70bf | 5843 | ++vcpu->stat.io_exits; |
e70669ab | 5844 | |
cf8f70bf | 5845 | if (string || in) |
51d8b661 | 5846 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
e70669ab | 5847 | |
cf8f70bf GN |
5848 | port = exit_qualification >> 16; |
5849 | size = (exit_qualification & 7) + 1; | |
cf8f70bf | 5850 | |
6affcbed KH |
5851 | ret = kvm_skip_emulated_instruction(vcpu); |
5852 | ||
5853 | /* | |
5854 | * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered | |
5855 | * KVM_EXIT_DEBUG here. | |
5856 | */ | |
5857 | return kvm_fast_pio_out(vcpu, size, port) && ret; | |
6aa8b732 AK |
5858 | } |
5859 | ||
102d8325 IM |
5860 | static void |
5861 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
5862 | { | |
5863 | /* | |
5864 | * Patch in the VMCALL instruction: | |
5865 | */ | |
5866 | hypercall[0] = 0x0f; | |
5867 | hypercall[1] = 0x01; | |
5868 | hypercall[2] = 0xc1; | |
102d8325 IM |
5869 | } |
5870 | ||
0fa06071 | 5871 | /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ |
eeadf9e7 NHE |
5872 | static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) |
5873 | { | |
eeadf9e7 | 5874 | if (is_guest_mode(vcpu)) { |
1a0d74e6 JK |
5875 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
5876 | unsigned long orig_val = val; | |
5877 | ||
eeadf9e7 NHE |
5878 | /* |
5879 | * We get here when L2 changed cr0 in a way that did not change | |
5880 | * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), | |
1a0d74e6 JK |
5881 | * but did change L0 shadowed bits. So we first calculate the |
5882 | * effective cr0 value that L1 would like to write into the | |
5883 | * hardware. It consists of the L2-owned bits from the new | |
5884 | * value combined with the L1-owned bits from L1's guest_cr0. | |
eeadf9e7 | 5885 | */ |
1a0d74e6 JK |
5886 | val = (val & ~vmcs12->cr0_guest_host_mask) | |
5887 | (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); | |
5888 | ||
3899152c | 5889 | if (!nested_guest_cr0_valid(vcpu, val)) |
eeadf9e7 | 5890 | return 1; |
1a0d74e6 JK |
5891 | |
5892 | if (kvm_set_cr0(vcpu, val)) | |
5893 | return 1; | |
5894 | vmcs_writel(CR0_READ_SHADOW, orig_val); | |
eeadf9e7 | 5895 | return 0; |
1a0d74e6 JK |
5896 | } else { |
5897 | if (to_vmx(vcpu)->nested.vmxon && | |
3899152c | 5898 | !nested_host_cr0_valid(vcpu, val)) |
1a0d74e6 | 5899 | return 1; |
3899152c | 5900 | |
eeadf9e7 | 5901 | return kvm_set_cr0(vcpu, val); |
1a0d74e6 | 5902 | } |
eeadf9e7 NHE |
5903 | } |
5904 | ||
5905 | static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) | |
5906 | { | |
5907 | if (is_guest_mode(vcpu)) { | |
1a0d74e6 JK |
5908 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
5909 | unsigned long orig_val = val; | |
5910 | ||
5911 | /* analogously to handle_set_cr0 */ | |
5912 | val = (val & ~vmcs12->cr4_guest_host_mask) | | |
5913 | (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); | |
5914 | if (kvm_set_cr4(vcpu, val)) | |
eeadf9e7 | 5915 | return 1; |
1a0d74e6 | 5916 | vmcs_writel(CR4_READ_SHADOW, orig_val); |
eeadf9e7 NHE |
5917 | return 0; |
5918 | } else | |
5919 | return kvm_set_cr4(vcpu, val); | |
5920 | } | |
5921 | ||
6a6256f9 | 5922 | /* called to set cr0 as appropriate for clts instruction exit. */ |
eeadf9e7 NHE |
5923 | static void handle_clts(struct kvm_vcpu *vcpu) |
5924 | { | |
5925 | if (is_guest_mode(vcpu)) { | |
5926 | /* | |
5927 | * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS | |
5928 | * but we did (!fpu_active). We need to keep GUEST_CR0.TS on, | |
5929 | * just pretend it's off (also in arch.cr0 for fpu_activate). | |
5930 | */ | |
5931 | vmcs_writel(CR0_READ_SHADOW, | |
5932 | vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS); | |
5933 | vcpu->arch.cr0 &= ~X86_CR0_TS; | |
5934 | } else | |
5935 | vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); | |
5936 | } | |
5937 | ||
851ba692 | 5938 | static int handle_cr(struct kvm_vcpu *vcpu) |
6aa8b732 | 5939 | { |
229456fc | 5940 | unsigned long exit_qualification, val; |
6aa8b732 AK |
5941 | int cr; |
5942 | int reg; | |
49a9b07e | 5943 | int err; |
6affcbed | 5944 | int ret; |
6aa8b732 | 5945 | |
bfdaab09 | 5946 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
5947 | cr = exit_qualification & 15; |
5948 | reg = (exit_qualification >> 8) & 15; | |
5949 | switch ((exit_qualification >> 4) & 3) { | |
5950 | case 0: /* mov to cr */ | |
1e32c079 | 5951 | val = kvm_register_readl(vcpu, reg); |
229456fc | 5952 | trace_kvm_cr_write(cr, val); |
6aa8b732 AK |
5953 | switch (cr) { |
5954 | case 0: | |
eeadf9e7 | 5955 | err = handle_set_cr0(vcpu, val); |
6affcbed | 5956 | return kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 5957 | case 3: |
2390218b | 5958 | err = kvm_set_cr3(vcpu, val); |
6affcbed | 5959 | return kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 5960 | case 4: |
eeadf9e7 | 5961 | err = handle_set_cr4(vcpu, val); |
6affcbed | 5962 | return kvm_complete_insn_gp(vcpu, err); |
0a5fff19 GN |
5963 | case 8: { |
5964 | u8 cr8_prev = kvm_get_cr8(vcpu); | |
1e32c079 | 5965 | u8 cr8 = (u8)val; |
eea1cff9 | 5966 | err = kvm_set_cr8(vcpu, cr8); |
6affcbed | 5967 | ret = kvm_complete_insn_gp(vcpu, err); |
35754c98 | 5968 | if (lapic_in_kernel(vcpu)) |
6affcbed | 5969 | return ret; |
0a5fff19 | 5970 | if (cr8_prev <= cr8) |
6affcbed KH |
5971 | return ret; |
5972 | /* | |
5973 | * TODO: we might be squashing a | |
5974 | * KVM_GUESTDBG_SINGLESTEP-triggered | |
5975 | * KVM_EXIT_DEBUG here. | |
5976 | */ | |
851ba692 | 5977 | vcpu->run->exit_reason = KVM_EXIT_SET_TPR; |
0a5fff19 GN |
5978 | return 0; |
5979 | } | |
4b8073e4 | 5980 | } |
6aa8b732 | 5981 | break; |
25c4c276 | 5982 | case 2: /* clts */ |
eeadf9e7 | 5983 | handle_clts(vcpu); |
4d4ec087 | 5984 | trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); |
6b52d186 | 5985 | vmx_fpu_activate(vcpu); |
6affcbed | 5986 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
5987 | case 1: /*mov from cr*/ |
5988 | switch (cr) { | |
5989 | case 3: | |
9f8fe504 AK |
5990 | val = kvm_read_cr3(vcpu); |
5991 | kvm_register_write(vcpu, reg, val); | |
5992 | trace_kvm_cr_read(cr, val); | |
6affcbed | 5993 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 | 5994 | case 8: |
229456fc MT |
5995 | val = kvm_get_cr8(vcpu); |
5996 | kvm_register_write(vcpu, reg, val); | |
5997 | trace_kvm_cr_read(cr, val); | |
6affcbed | 5998 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
5999 | } |
6000 | break; | |
6001 | case 3: /* lmsw */ | |
a1f83a74 | 6002 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
4d4ec087 | 6003 | trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); |
a1f83a74 | 6004 | kvm_lmsw(vcpu, val); |
6aa8b732 | 6005 | |
6affcbed | 6006 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6007 | default: |
6008 | break; | |
6009 | } | |
851ba692 | 6010 | vcpu->run->exit_reason = 0; |
a737f256 | 6011 | vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
6012 | (int)(exit_qualification >> 4) & 3, cr); |
6013 | return 0; | |
6014 | } | |
6015 | ||
851ba692 | 6016 | static int handle_dr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6017 | { |
bfdaab09 | 6018 | unsigned long exit_qualification; |
16f8a6f9 NA |
6019 | int dr, dr7, reg; |
6020 | ||
6021 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6022 | dr = exit_qualification & DEBUG_REG_ACCESS_NUM; | |
6023 | ||
6024 | /* First, if DR does not exist, trigger UD */ | |
6025 | if (!kvm_require_dr(vcpu, dr)) | |
6026 | return 1; | |
6aa8b732 | 6027 | |
f2483415 | 6028 | /* Do not handle if the CPL > 0, will trigger GP on re-entry */ |
0a79b009 AK |
6029 | if (!kvm_require_cpl(vcpu, 0)) |
6030 | return 1; | |
16f8a6f9 NA |
6031 | dr7 = vmcs_readl(GUEST_DR7); |
6032 | if (dr7 & DR7_GD) { | |
42dbaa5a JK |
6033 | /* |
6034 | * As the vm-exit takes precedence over the debug trap, we | |
6035 | * need to emulate the latter, either for the host or the | |
6036 | * guest debugging itself. | |
6037 | */ | |
6038 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
851ba692 | 6039 | vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; |
16f8a6f9 | 6040 | vcpu->run->debug.arch.dr7 = dr7; |
82b32774 | 6041 | vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
851ba692 AK |
6042 | vcpu->run->debug.arch.exception = DB_VECTOR; |
6043 | vcpu->run->exit_reason = KVM_EXIT_DEBUG; | |
42dbaa5a JK |
6044 | return 0; |
6045 | } else { | |
7305eb5d | 6046 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 6047 | vcpu->arch.dr6 |= DR6_BD | DR6_RTM; |
42dbaa5a JK |
6048 | kvm_queue_exception(vcpu, DB_VECTOR); |
6049 | return 1; | |
6050 | } | |
6051 | } | |
6052 | ||
81908bf4 | 6053 | if (vcpu->guest_debug == 0) { |
8f22372f PB |
6054 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
6055 | CPU_BASED_MOV_DR_EXITING); | |
81908bf4 PB |
6056 | |
6057 | /* | |
6058 | * No more DR vmexits; force a reload of the debug registers | |
6059 | * and reenter on this instruction. The next vmexit will | |
6060 | * retrieve the full state of the debug registers. | |
6061 | */ | |
6062 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
6063 | return 1; | |
6064 | } | |
6065 | ||
42dbaa5a JK |
6066 | reg = DEBUG_REG_ACCESS_REG(exit_qualification); |
6067 | if (exit_qualification & TYPE_MOV_FROM_DR) { | |
020df079 | 6068 | unsigned long val; |
4c4d563b JK |
6069 | |
6070 | if (kvm_get_dr(vcpu, dr, &val)) | |
6071 | return 1; | |
6072 | kvm_register_write(vcpu, reg, val); | |
020df079 | 6073 | } else |
5777392e | 6074 | if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) |
4c4d563b JK |
6075 | return 1; |
6076 | ||
6affcbed | 6077 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6078 | } |
6079 | ||
73aaf249 JK |
6080 | static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) |
6081 | { | |
6082 | return vcpu->arch.dr6; | |
6083 | } | |
6084 | ||
6085 | static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) | |
6086 | { | |
6087 | } | |
6088 | ||
81908bf4 PB |
6089 | static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
6090 | { | |
81908bf4 PB |
6091 | get_debugreg(vcpu->arch.db[0], 0); |
6092 | get_debugreg(vcpu->arch.db[1], 1); | |
6093 | get_debugreg(vcpu->arch.db[2], 2); | |
6094 | get_debugreg(vcpu->arch.db[3], 3); | |
6095 | get_debugreg(vcpu->arch.dr6, 6); | |
6096 | vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); | |
6097 | ||
6098 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
8f22372f | 6099 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING); |
81908bf4 PB |
6100 | } |
6101 | ||
020df079 GN |
6102 | static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) |
6103 | { | |
6104 | vmcs_writel(GUEST_DR7, val); | |
6105 | } | |
6106 | ||
851ba692 | 6107 | static int handle_cpuid(struct kvm_vcpu *vcpu) |
6aa8b732 | 6108 | { |
6a908b62 | 6109 | return kvm_emulate_cpuid(vcpu); |
6aa8b732 AK |
6110 | } |
6111 | ||
851ba692 | 6112 | static int handle_rdmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6113 | { |
ad312c7c | 6114 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
609e36d3 | 6115 | struct msr_data msr_info; |
6aa8b732 | 6116 | |
609e36d3 PB |
6117 | msr_info.index = ecx; |
6118 | msr_info.host_initiated = false; | |
6119 | if (vmx_get_msr(vcpu, &msr_info)) { | |
59200273 | 6120 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 6121 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
6122 | return 1; |
6123 | } | |
6124 | ||
609e36d3 | 6125 | trace_kvm_msr_read(ecx, msr_info.data); |
2714d1d3 | 6126 | |
6aa8b732 | 6127 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
609e36d3 PB |
6128 | vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u; |
6129 | vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u; | |
6affcbed | 6130 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6131 | } |
6132 | ||
851ba692 | 6133 | static int handle_wrmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6134 | { |
8fe8ab46 | 6135 | struct msr_data msr; |
ad312c7c ZX |
6136 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
6137 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
6138 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 | 6139 | |
8fe8ab46 WA |
6140 | msr.data = data; |
6141 | msr.index = ecx; | |
6142 | msr.host_initiated = false; | |
854e8bb1 | 6143 | if (kvm_set_msr(vcpu, &msr) != 0) { |
59200273 | 6144 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 6145 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
6146 | return 1; |
6147 | } | |
6148 | ||
59200273 | 6149 | trace_kvm_msr_write(ecx, data); |
6affcbed | 6150 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6151 | } |
6152 | ||
851ba692 | 6153 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) |
6e5d865c | 6154 | { |
3842d135 | 6155 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6e5d865c YS |
6156 | return 1; |
6157 | } | |
6158 | ||
851ba692 | 6159 | static int handle_interrupt_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 6160 | { |
85f455f7 ED |
6161 | u32 cpu_based_vm_exec_control; |
6162 | ||
6163 | /* clear pending irq */ | |
6164 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
6165 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
6166 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2714d1d3 | 6167 | |
3842d135 AK |
6168 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6169 | ||
a26bf12a | 6170 | ++vcpu->stat.irq_window_exits; |
6aa8b732 AK |
6171 | return 1; |
6172 | } | |
6173 | ||
851ba692 | 6174 | static int handle_halt(struct kvm_vcpu *vcpu) |
6aa8b732 | 6175 | { |
d3bef15f | 6176 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
6177 | } |
6178 | ||
851ba692 | 6179 | static int handle_vmcall(struct kvm_vcpu *vcpu) |
c21415e8 | 6180 | { |
0d9c055e | 6181 | return kvm_emulate_hypercall(vcpu); |
c21415e8 IM |
6182 | } |
6183 | ||
ec25d5e6 GN |
6184 | static int handle_invd(struct kvm_vcpu *vcpu) |
6185 | { | |
51d8b661 | 6186 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
ec25d5e6 GN |
6187 | } |
6188 | ||
851ba692 | 6189 | static int handle_invlpg(struct kvm_vcpu *vcpu) |
a7052897 | 6190 | { |
f9c617f6 | 6191 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
a7052897 MT |
6192 | |
6193 | kvm_mmu_invlpg(vcpu, exit_qualification); | |
6affcbed | 6194 | return kvm_skip_emulated_instruction(vcpu); |
a7052897 MT |
6195 | } |
6196 | ||
fee84b07 AK |
6197 | static int handle_rdpmc(struct kvm_vcpu *vcpu) |
6198 | { | |
6199 | int err; | |
6200 | ||
6201 | err = kvm_rdpmc(vcpu); | |
6affcbed | 6202 | return kvm_complete_insn_gp(vcpu, err); |
fee84b07 AK |
6203 | } |
6204 | ||
851ba692 | 6205 | static int handle_wbinvd(struct kvm_vcpu *vcpu) |
e5edaa01 | 6206 | { |
6affcbed | 6207 | return kvm_emulate_wbinvd(vcpu); |
e5edaa01 ED |
6208 | } |
6209 | ||
2acf923e DC |
6210 | static int handle_xsetbv(struct kvm_vcpu *vcpu) |
6211 | { | |
6212 | u64 new_bv = kvm_read_edx_eax(vcpu); | |
6213 | u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
6214 | ||
6215 | if (kvm_set_xcr(vcpu, index, new_bv) == 0) | |
6affcbed | 6216 | return kvm_skip_emulated_instruction(vcpu); |
2acf923e DC |
6217 | return 1; |
6218 | } | |
6219 | ||
f53cd63c WL |
6220 | static int handle_xsaves(struct kvm_vcpu *vcpu) |
6221 | { | |
6affcbed | 6222 | kvm_skip_emulated_instruction(vcpu); |
f53cd63c WL |
6223 | WARN(1, "this should never happen\n"); |
6224 | return 1; | |
6225 | } | |
6226 | ||
6227 | static int handle_xrstors(struct kvm_vcpu *vcpu) | |
6228 | { | |
6affcbed | 6229 | kvm_skip_emulated_instruction(vcpu); |
f53cd63c WL |
6230 | WARN(1, "this should never happen\n"); |
6231 | return 1; | |
6232 | } | |
6233 | ||
851ba692 | 6234 | static int handle_apic_access(struct kvm_vcpu *vcpu) |
f78e0e2e | 6235 | { |
58fbbf26 KT |
6236 | if (likely(fasteoi)) { |
6237 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6238 | int access_type, offset; | |
6239 | ||
6240 | access_type = exit_qualification & APIC_ACCESS_TYPE; | |
6241 | offset = exit_qualification & APIC_ACCESS_OFFSET; | |
6242 | /* | |
6243 | * Sane guest uses MOV to write EOI, with written value | |
6244 | * not cared. So make a short-circuit here by avoiding | |
6245 | * heavy instruction emulation. | |
6246 | */ | |
6247 | if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && | |
6248 | (offset == APIC_EOI)) { | |
6249 | kvm_lapic_set_eoi(vcpu); | |
6affcbed | 6250 | return kvm_skip_emulated_instruction(vcpu); |
58fbbf26 KT |
6251 | } |
6252 | } | |
51d8b661 | 6253 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
f78e0e2e SY |
6254 | } |
6255 | ||
c7c9c56c YZ |
6256 | static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) |
6257 | { | |
6258 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6259 | int vector = exit_qualification & 0xff; | |
6260 | ||
6261 | /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ | |
6262 | kvm_apic_set_eoi_accelerated(vcpu, vector); | |
6263 | return 1; | |
6264 | } | |
6265 | ||
83d4c286 YZ |
6266 | static int handle_apic_write(struct kvm_vcpu *vcpu) |
6267 | { | |
6268 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6269 | u32 offset = exit_qualification & 0xfff; | |
6270 | ||
6271 | /* APIC-write VM exit is trap-like and thus no need to adjust IP */ | |
6272 | kvm_apic_write_nodecode(vcpu, offset); | |
6273 | return 1; | |
6274 | } | |
6275 | ||
851ba692 | 6276 | static int handle_task_switch(struct kvm_vcpu *vcpu) |
37817f29 | 6277 | { |
60637aac | 6278 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
37817f29 | 6279 | unsigned long exit_qualification; |
e269fb21 JK |
6280 | bool has_error_code = false; |
6281 | u32 error_code = 0; | |
37817f29 | 6282 | u16 tss_selector; |
7f3d35fd | 6283 | int reason, type, idt_v, idt_index; |
64a7ec06 GN |
6284 | |
6285 | idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | |
7f3d35fd | 6286 | idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); |
64a7ec06 | 6287 | type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); |
37817f29 IE |
6288 | |
6289 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6290 | ||
6291 | reason = (u32)exit_qualification >> 30; | |
64a7ec06 GN |
6292 | if (reason == TASK_SWITCH_GATE && idt_v) { |
6293 | switch (type) { | |
6294 | case INTR_TYPE_NMI_INTR: | |
6295 | vcpu->arch.nmi_injected = false; | |
654f06fc | 6296 | vmx_set_nmi_mask(vcpu, true); |
64a7ec06 GN |
6297 | break; |
6298 | case INTR_TYPE_EXT_INTR: | |
66fd3f7f | 6299 | case INTR_TYPE_SOFT_INTR: |
64a7ec06 GN |
6300 | kvm_clear_interrupt_queue(vcpu); |
6301 | break; | |
6302 | case INTR_TYPE_HARD_EXCEPTION: | |
e269fb21 JK |
6303 | if (vmx->idt_vectoring_info & |
6304 | VECTORING_INFO_DELIVER_CODE_MASK) { | |
6305 | has_error_code = true; | |
6306 | error_code = | |
6307 | vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
6308 | } | |
6309 | /* fall through */ | |
64a7ec06 GN |
6310 | case INTR_TYPE_SOFT_EXCEPTION: |
6311 | kvm_clear_exception_queue(vcpu); | |
6312 | break; | |
6313 | default: | |
6314 | break; | |
6315 | } | |
60637aac | 6316 | } |
37817f29 IE |
6317 | tss_selector = exit_qualification; |
6318 | ||
64a7ec06 GN |
6319 | if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && |
6320 | type != INTR_TYPE_EXT_INTR && | |
6321 | type != INTR_TYPE_NMI_INTR)) | |
6322 | skip_emulated_instruction(vcpu); | |
6323 | ||
7f3d35fd KW |
6324 | if (kvm_task_switch(vcpu, tss_selector, |
6325 | type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason, | |
6326 | has_error_code, error_code) == EMULATE_FAIL) { | |
acb54517 GN |
6327 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
6328 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6329 | vcpu->run->internal.ndata = 0; | |
42dbaa5a | 6330 | return 0; |
acb54517 | 6331 | } |
42dbaa5a | 6332 | |
42dbaa5a JK |
6333 | /* |
6334 | * TODO: What about debug traps on tss switch? | |
6335 | * Are we supposed to inject them and update dr6? | |
6336 | */ | |
6337 | ||
6338 | return 1; | |
37817f29 IE |
6339 | } |
6340 | ||
851ba692 | 6341 | static int handle_ept_violation(struct kvm_vcpu *vcpu) |
1439442c | 6342 | { |
f9c617f6 | 6343 | unsigned long exit_qualification; |
1439442c | 6344 | gpa_t gpa; |
4f5982a5 | 6345 | u32 error_code; |
1439442c | 6346 | int gla_validity; |
1439442c | 6347 | |
f9c617f6 | 6348 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
1439442c | 6349 | |
1439442c | 6350 | gla_validity = (exit_qualification >> 7) & 0x3; |
72e0ae58 | 6351 | if (gla_validity == 0x2) { |
1439442c SY |
6352 | printk(KERN_ERR "EPT: Handling EPT violation failed!\n"); |
6353 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | |
6354 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | |
f9c617f6 | 6355 | vmcs_readl(GUEST_LINEAR_ADDRESS)); |
1439442c SY |
6356 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", |
6357 | (long unsigned int)exit_qualification); | |
851ba692 AK |
6358 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
6359 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION; | |
596ae895 | 6360 | return 0; |
1439442c SY |
6361 | } |
6362 | ||
0be9c7a8 GN |
6363 | /* |
6364 | * EPT violation happened while executing iret from NMI, | |
6365 | * "blocked by NMI" bit has to be set before next VM entry. | |
6366 | * There are errata that may cause this bit to not be set: | |
6367 | * AAK134, BY25. | |
6368 | */ | |
bcd1c294 GN |
6369 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && |
6370 | cpu_has_virtual_nmis() && | |
6371 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) | |
0be9c7a8 GN |
6372 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); |
6373 | ||
1439442c | 6374 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); |
229456fc | 6375 | trace_kvm_page_fault(gpa, exit_qualification); |
4f5982a5 | 6376 | |
d95c5568 BD |
6377 | /* it is a read fault? */ |
6378 | error_code = (exit_qualification << 2) & PFERR_USER_MASK; | |
6379 | /* it is a write fault? */ | |
6380 | error_code |= exit_qualification & PFERR_WRITE_MASK; | |
25d92081 | 6381 | /* It is a fetch fault? */ |
81ed33e4 | 6382 | error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK; |
4f5982a5 | 6383 | /* ept page table is present? */ |
d95c5568 | 6384 | error_code |= (exit_qualification & 0x38) != 0; |
4f5982a5 | 6385 | |
25d92081 YZ |
6386 | vcpu->arch.exit_qualification = exit_qualification; |
6387 | ||
4f5982a5 | 6388 | return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); |
1439442c SY |
6389 | } |
6390 | ||
851ba692 | 6391 | static int handle_ept_misconfig(struct kvm_vcpu *vcpu) |
68f89400 | 6392 | { |
f735d4af | 6393 | int ret; |
68f89400 MT |
6394 | gpa_t gpa; |
6395 | ||
6396 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
e32edf4f | 6397 | if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { |
931c33b1 | 6398 | trace_kvm_fast_mmio(gpa); |
6affcbed | 6399 | return kvm_skip_emulated_instruction(vcpu); |
68c3b4d1 | 6400 | } |
68f89400 | 6401 | |
450869d6 | 6402 | ret = handle_mmio_page_fault(vcpu, gpa, true); |
b37fbea6 | 6403 | if (likely(ret == RET_MMIO_PF_EMULATE)) |
ce88decf XG |
6404 | return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) == |
6405 | EMULATE_DONE; | |
f8f55942 XG |
6406 | |
6407 | if (unlikely(ret == RET_MMIO_PF_INVALID)) | |
6408 | return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0); | |
6409 | ||
b37fbea6 | 6410 | if (unlikely(ret == RET_MMIO_PF_RETRY)) |
ce88decf XG |
6411 | return 1; |
6412 | ||
6413 | /* It is the real ept misconfig */ | |
f735d4af | 6414 | WARN_ON(1); |
68f89400 | 6415 | |
851ba692 AK |
6416 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
6417 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG; | |
68f89400 MT |
6418 | |
6419 | return 0; | |
6420 | } | |
6421 | ||
851ba692 | 6422 | static int handle_nmi_window(struct kvm_vcpu *vcpu) |
f08864b4 SY |
6423 | { |
6424 | u32 cpu_based_vm_exec_control; | |
6425 | ||
6426 | /* clear pending NMI */ | |
6427 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
6428 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
6429 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
6430 | ++vcpu->stat.nmi_window_exits; | |
3842d135 | 6431 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f08864b4 SY |
6432 | |
6433 | return 1; | |
6434 | } | |
6435 | ||
80ced186 | 6436 | static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) |
ea953ef0 | 6437 | { |
8b3079a5 AK |
6438 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6439 | enum emulation_result err = EMULATE_DONE; | |
80ced186 | 6440 | int ret = 1; |
49e9d557 AK |
6441 | u32 cpu_exec_ctrl; |
6442 | bool intr_window_requested; | |
b8405c18 | 6443 | unsigned count = 130; |
49e9d557 AK |
6444 | |
6445 | cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
6446 | intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING; | |
ea953ef0 | 6447 | |
98eb2f8b | 6448 | while (vmx->emulation_required && count-- != 0) { |
bdea48e3 | 6449 | if (intr_window_requested && vmx_interrupt_allowed(vcpu)) |
49e9d557 AK |
6450 | return handle_interrupt_window(&vmx->vcpu); |
6451 | ||
de87dcdd AK |
6452 | if (test_bit(KVM_REQ_EVENT, &vcpu->requests)) |
6453 | return 1; | |
6454 | ||
991eebf9 | 6455 | err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE); |
ea953ef0 | 6456 | |
ac0a48c3 | 6457 | if (err == EMULATE_USER_EXIT) { |
94452b9e | 6458 | ++vcpu->stat.mmio_exits; |
80ced186 MG |
6459 | ret = 0; |
6460 | goto out; | |
6461 | } | |
1d5a4d9b | 6462 | |
de5f70e0 AK |
6463 | if (err != EMULATE_DONE) { |
6464 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
6465 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6466 | vcpu->run->internal.ndata = 0; | |
6d77dbfc | 6467 | return 0; |
de5f70e0 | 6468 | } |
ea953ef0 | 6469 | |
8d76c49e GN |
6470 | if (vcpu->arch.halt_request) { |
6471 | vcpu->arch.halt_request = 0; | |
5cb56059 | 6472 | ret = kvm_vcpu_halt(vcpu); |
8d76c49e GN |
6473 | goto out; |
6474 | } | |
6475 | ||
ea953ef0 | 6476 | if (signal_pending(current)) |
80ced186 | 6477 | goto out; |
ea953ef0 MG |
6478 | if (need_resched()) |
6479 | schedule(); | |
6480 | } | |
6481 | ||
80ced186 MG |
6482 | out: |
6483 | return ret; | |
ea953ef0 MG |
6484 | } |
6485 | ||
b4a2d31d RK |
6486 | static int __grow_ple_window(int val) |
6487 | { | |
6488 | if (ple_window_grow < 1) | |
6489 | return ple_window; | |
6490 | ||
6491 | val = min(val, ple_window_actual_max); | |
6492 | ||
6493 | if (ple_window_grow < ple_window) | |
6494 | val *= ple_window_grow; | |
6495 | else | |
6496 | val += ple_window_grow; | |
6497 | ||
6498 | return val; | |
6499 | } | |
6500 | ||
6501 | static int __shrink_ple_window(int val, int modifier, int minimum) | |
6502 | { | |
6503 | if (modifier < 1) | |
6504 | return ple_window; | |
6505 | ||
6506 | if (modifier < ple_window) | |
6507 | val /= modifier; | |
6508 | else | |
6509 | val -= modifier; | |
6510 | ||
6511 | return max(val, minimum); | |
6512 | } | |
6513 | ||
6514 | static void grow_ple_window(struct kvm_vcpu *vcpu) | |
6515 | { | |
6516 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6517 | int old = vmx->ple_window; | |
6518 | ||
6519 | vmx->ple_window = __grow_ple_window(old); | |
6520 | ||
6521 | if (vmx->ple_window != old) | |
6522 | vmx->ple_window_dirty = true; | |
7b46268d RK |
6523 | |
6524 | trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
6525 | } |
6526 | ||
6527 | static void shrink_ple_window(struct kvm_vcpu *vcpu) | |
6528 | { | |
6529 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6530 | int old = vmx->ple_window; | |
6531 | ||
6532 | vmx->ple_window = __shrink_ple_window(old, | |
6533 | ple_window_shrink, ple_window); | |
6534 | ||
6535 | if (vmx->ple_window != old) | |
6536 | vmx->ple_window_dirty = true; | |
7b46268d RK |
6537 | |
6538 | trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
6539 | } |
6540 | ||
6541 | /* | |
6542 | * ple_window_actual_max is computed to be one grow_ple_window() below | |
6543 | * ple_window_max. (See __grow_ple_window for the reason.) | |
6544 | * This prevents overflows, because ple_window_max is int. | |
6545 | * ple_window_max effectively rounded down to a multiple of ple_window_grow in | |
6546 | * this process. | |
6547 | * ple_window_max is also prevented from setting vmx->ple_window < ple_window. | |
6548 | */ | |
6549 | static void update_ple_window_actual_max(void) | |
6550 | { | |
6551 | ple_window_actual_max = | |
6552 | __shrink_ple_window(max(ple_window_max, ple_window), | |
6553 | ple_window_grow, INT_MIN); | |
6554 | } | |
6555 | ||
bf9f6ac8 FW |
6556 | /* |
6557 | * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. | |
6558 | */ | |
6559 | static void wakeup_handler(void) | |
6560 | { | |
6561 | struct kvm_vcpu *vcpu; | |
6562 | int cpu = smp_processor_id(); | |
6563 | ||
6564 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
6565 | list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), | |
6566 | blocked_vcpu_list) { | |
6567 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
6568 | ||
6569 | if (pi_test_on(pi_desc) == 1) | |
6570 | kvm_vcpu_kick(vcpu); | |
6571 | } | |
6572 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
6573 | } | |
6574 | ||
f2c7648d TC |
6575 | static __init int hardware_setup(void) |
6576 | { | |
34a1cd60 TC |
6577 | int r = -ENOMEM, i, msr; |
6578 | ||
6579 | rdmsrl_safe(MSR_EFER, &host_efer); | |
6580 | ||
6581 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) | |
6582 | kvm_define_shared_msr(i, vmx_msr_index[i]); | |
6583 | ||
23611332 RK |
6584 | for (i = 0; i < VMX_BITMAP_NR; i++) { |
6585 | vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL); | |
6586 | if (!vmx_bitmap[i]) | |
6587 | goto out; | |
6588 | } | |
34a1cd60 TC |
6589 | |
6590 | vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL); | |
34a1cd60 TC |
6591 | memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE); |
6592 | memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE); | |
6593 | ||
6594 | /* | |
6595 | * Allow direct access to the PC debug port (it is often used for I/O | |
6596 | * delays, but the vmexits simply slow things down). | |
6597 | */ | |
6598 | memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE); | |
6599 | clear_bit(0x80, vmx_io_bitmap_a); | |
6600 | ||
6601 | memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE); | |
6602 | ||
6603 | memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE); | |
6604 | memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE); | |
6605 | ||
34a1cd60 TC |
6606 | if (setup_vmcs_config(&vmcs_config) < 0) { |
6607 | r = -EIO; | |
23611332 | 6608 | goto out; |
baa03522 | 6609 | } |
f2c7648d TC |
6610 | |
6611 | if (boot_cpu_has(X86_FEATURE_NX)) | |
6612 | kvm_enable_efer_bits(EFER_NX); | |
6613 | ||
6614 | if (!cpu_has_vmx_vpid()) | |
6615 | enable_vpid = 0; | |
6616 | if (!cpu_has_vmx_shadow_vmcs()) | |
6617 | enable_shadow_vmcs = 0; | |
6618 | if (enable_shadow_vmcs) | |
6619 | init_vmcs_shadow_fields(); | |
6620 | ||
6621 | if (!cpu_has_vmx_ept() || | |
6622 | !cpu_has_vmx_ept_4levels()) { | |
6623 | enable_ept = 0; | |
6624 | enable_unrestricted_guest = 0; | |
6625 | enable_ept_ad_bits = 0; | |
6626 | } | |
6627 | ||
6628 | if (!cpu_has_vmx_ept_ad_bits()) | |
6629 | enable_ept_ad_bits = 0; | |
6630 | ||
6631 | if (!cpu_has_vmx_unrestricted_guest()) | |
6632 | enable_unrestricted_guest = 0; | |
6633 | ||
ad15a296 | 6634 | if (!cpu_has_vmx_flexpriority()) |
f2c7648d TC |
6635 | flexpriority_enabled = 0; |
6636 | ||
ad15a296 PB |
6637 | /* |
6638 | * set_apic_access_page_addr() is used to reload apic access | |
6639 | * page upon invalidation. No need to do anything if not | |
6640 | * using the APIC_ACCESS_ADDR VMCS field. | |
6641 | */ | |
6642 | if (!flexpriority_enabled) | |
f2c7648d | 6643 | kvm_x86_ops->set_apic_access_page_addr = NULL; |
f2c7648d TC |
6644 | |
6645 | if (!cpu_has_vmx_tpr_shadow()) | |
6646 | kvm_x86_ops->update_cr8_intercept = NULL; | |
6647 | ||
6648 | if (enable_ept && !cpu_has_vmx_ept_2m_page()) | |
6649 | kvm_disable_largepages(); | |
6650 | ||
6651 | if (!cpu_has_vmx_ple()) | |
6652 | ple_gap = 0; | |
6653 | ||
6654 | if (!cpu_has_vmx_apicv()) | |
6655 | enable_apicv = 0; | |
6656 | ||
64903d61 HZ |
6657 | if (cpu_has_vmx_tsc_scaling()) { |
6658 | kvm_has_tsc_control = true; | |
6659 | kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; | |
6660 | kvm_tsc_scaling_ratio_frac_bits = 48; | |
6661 | } | |
6662 | ||
baa03522 TC |
6663 | vmx_disable_intercept_for_msr(MSR_FS_BASE, false); |
6664 | vmx_disable_intercept_for_msr(MSR_GS_BASE, false); | |
6665 | vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true); | |
6666 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false); | |
6667 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false); | |
6668 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false); | |
6669 | vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true); | |
6670 | ||
c63e4563 | 6671 | memcpy(vmx_msr_bitmap_legacy_x2apic_apicv, |
baa03522 | 6672 | vmx_msr_bitmap_legacy, PAGE_SIZE); |
c63e4563 | 6673 | memcpy(vmx_msr_bitmap_longmode_x2apic_apicv, |
baa03522 | 6674 | vmx_msr_bitmap_longmode, PAGE_SIZE); |
c63e4563 | 6675 | memcpy(vmx_msr_bitmap_legacy_x2apic, |
f6e90f9e | 6676 | vmx_msr_bitmap_legacy, PAGE_SIZE); |
c63e4563 | 6677 | memcpy(vmx_msr_bitmap_longmode_x2apic, |
f6e90f9e | 6678 | vmx_msr_bitmap_longmode, PAGE_SIZE); |
baa03522 | 6679 | |
04bb92e4 WL |
6680 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
6681 | ||
40d8338d RK |
6682 | for (msr = 0x800; msr <= 0x8ff; msr++) { |
6683 | if (msr == 0x839 /* TMCCT */) | |
6684 | continue; | |
2e69f865 | 6685 | vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true); |
40d8338d | 6686 | } |
3ce424e4 | 6687 | |
f6e90f9e | 6688 | /* |
2e69f865 RK |
6689 | * TPR reads and writes can be virtualized even if virtual interrupt |
6690 | * delivery is not in use. | |
f6e90f9e | 6691 | */ |
2e69f865 RK |
6692 | vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true); |
6693 | vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false); | |
6694 | ||
6695 | /* EOI */ | |
6696 | vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true); | |
6697 | /* SELF-IPI */ | |
6698 | vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true); | |
baa03522 TC |
6699 | |
6700 | if (enable_ept) { | |
d95c5568 | 6701 | kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, |
baa03522 TC |
6702 | (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull, |
6703 | (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull, | |
d95c5568 BD |
6704 | 0ull, VMX_EPT_EXECUTABLE_MASK, |
6705 | cpu_has_vmx_ept_execute_only() ? | |
6706 | 0ull : VMX_EPT_READABLE_MASK); | |
baa03522 TC |
6707 | ept_set_mmio_spte_mask(); |
6708 | kvm_enable_tdp(); | |
6709 | } else | |
6710 | kvm_disable_tdp(); | |
6711 | ||
6712 | update_ple_window_actual_max(); | |
6713 | ||
843e4330 KH |
6714 | /* |
6715 | * Only enable PML when hardware supports PML feature, and both EPT | |
6716 | * and EPT A/D bit features are enabled -- PML depends on them to work. | |
6717 | */ | |
6718 | if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) | |
6719 | enable_pml = 0; | |
6720 | ||
6721 | if (!enable_pml) { | |
6722 | kvm_x86_ops->slot_enable_log_dirty = NULL; | |
6723 | kvm_x86_ops->slot_disable_log_dirty = NULL; | |
6724 | kvm_x86_ops->flush_log_dirty = NULL; | |
6725 | kvm_x86_ops->enable_log_dirty_pt_masked = NULL; | |
6726 | } | |
6727 | ||
64672c95 YJ |
6728 | if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) { |
6729 | u64 vmx_msr; | |
6730 | ||
6731 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
6732 | cpu_preemption_timer_multi = | |
6733 | vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; | |
6734 | } else { | |
6735 | kvm_x86_ops->set_hv_timer = NULL; | |
6736 | kvm_x86_ops->cancel_hv_timer = NULL; | |
6737 | } | |
6738 | ||
bf9f6ac8 FW |
6739 | kvm_set_posted_intr_wakeup_handler(wakeup_handler); |
6740 | ||
c45dcc71 AR |
6741 | kvm_mce_cap_supported |= MCG_LMCE_P; |
6742 | ||
f2c7648d | 6743 | return alloc_kvm_area(); |
34a1cd60 | 6744 | |
34a1cd60 | 6745 | out: |
23611332 RK |
6746 | for (i = 0; i < VMX_BITMAP_NR; i++) |
6747 | free_page((unsigned long)vmx_bitmap[i]); | |
34a1cd60 TC |
6748 | |
6749 | return r; | |
f2c7648d TC |
6750 | } |
6751 | ||
6752 | static __exit void hardware_unsetup(void) | |
6753 | { | |
23611332 RK |
6754 | int i; |
6755 | ||
6756 | for (i = 0; i < VMX_BITMAP_NR; i++) | |
6757 | free_page((unsigned long)vmx_bitmap[i]); | |
34a1cd60 | 6758 | |
f2c7648d TC |
6759 | free_kvm_area(); |
6760 | } | |
6761 | ||
4b8d54f9 ZE |
6762 | /* |
6763 | * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE | |
6764 | * exiting, so only get here on cpu with PAUSE-Loop-Exiting. | |
6765 | */ | |
9fb41ba8 | 6766 | static int handle_pause(struct kvm_vcpu *vcpu) |
4b8d54f9 | 6767 | { |
b4a2d31d RK |
6768 | if (ple_gap) |
6769 | grow_ple_window(vcpu); | |
6770 | ||
4b8d54f9 | 6771 | kvm_vcpu_on_spin(vcpu); |
6affcbed | 6772 | return kvm_skip_emulated_instruction(vcpu); |
4b8d54f9 ZE |
6773 | } |
6774 | ||
87c00572 | 6775 | static int handle_nop(struct kvm_vcpu *vcpu) |
59708670 | 6776 | { |
6affcbed | 6777 | return kvm_skip_emulated_instruction(vcpu); |
59708670 SY |
6778 | } |
6779 | ||
87c00572 GS |
6780 | static int handle_mwait(struct kvm_vcpu *vcpu) |
6781 | { | |
6782 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
6783 | return handle_nop(vcpu); | |
6784 | } | |
6785 | ||
5f3d45e7 MD |
6786 | static int handle_monitor_trap(struct kvm_vcpu *vcpu) |
6787 | { | |
6788 | return 1; | |
6789 | } | |
6790 | ||
87c00572 GS |
6791 | static int handle_monitor(struct kvm_vcpu *vcpu) |
6792 | { | |
6793 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
6794 | return handle_nop(vcpu); | |
6795 | } | |
6796 | ||
ff2f6fe9 NHE |
6797 | /* |
6798 | * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12. | |
6799 | * We could reuse a single VMCS for all the L2 guests, but we also want the | |
6800 | * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this | |
6801 | * allows keeping them loaded on the processor, and in the future will allow | |
6802 | * optimizations where prepare_vmcs02 doesn't need to set all the fields on | |
6803 | * every entry if they never change. | |
6804 | * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE | |
6805 | * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first. | |
6806 | * | |
6807 | * The following functions allocate and free a vmcs02 in this pool. | |
6808 | */ | |
6809 | ||
6810 | /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */ | |
6811 | static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx) | |
6812 | { | |
6813 | struct vmcs02_list *item; | |
6814 | list_for_each_entry(item, &vmx->nested.vmcs02_pool, list) | |
6815 | if (item->vmptr == vmx->nested.current_vmptr) { | |
6816 | list_move(&item->list, &vmx->nested.vmcs02_pool); | |
6817 | return &item->vmcs02; | |
6818 | } | |
6819 | ||
6820 | if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) { | |
6821 | /* Recycle the least recently used VMCS. */ | |
d74c0e6b GT |
6822 | item = list_last_entry(&vmx->nested.vmcs02_pool, |
6823 | struct vmcs02_list, list); | |
ff2f6fe9 NHE |
6824 | item->vmptr = vmx->nested.current_vmptr; |
6825 | list_move(&item->list, &vmx->nested.vmcs02_pool); | |
6826 | return &item->vmcs02; | |
6827 | } | |
6828 | ||
6829 | /* Create a new VMCS */ | |
0fa24ce3 | 6830 | item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL); |
ff2f6fe9 NHE |
6831 | if (!item) |
6832 | return NULL; | |
6833 | item->vmcs02.vmcs = alloc_vmcs(); | |
355f4fb1 | 6834 | item->vmcs02.shadow_vmcs = NULL; |
ff2f6fe9 NHE |
6835 | if (!item->vmcs02.vmcs) { |
6836 | kfree(item); | |
6837 | return NULL; | |
6838 | } | |
6839 | loaded_vmcs_init(&item->vmcs02); | |
6840 | item->vmptr = vmx->nested.current_vmptr; | |
6841 | list_add(&(item->list), &(vmx->nested.vmcs02_pool)); | |
6842 | vmx->nested.vmcs02_num++; | |
6843 | return &item->vmcs02; | |
6844 | } | |
6845 | ||
6846 | /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */ | |
6847 | static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr) | |
6848 | { | |
6849 | struct vmcs02_list *item; | |
6850 | list_for_each_entry(item, &vmx->nested.vmcs02_pool, list) | |
6851 | if (item->vmptr == vmptr) { | |
6852 | free_loaded_vmcs(&item->vmcs02); | |
6853 | list_del(&item->list); | |
6854 | kfree(item); | |
6855 | vmx->nested.vmcs02_num--; | |
6856 | return; | |
6857 | } | |
6858 | } | |
6859 | ||
6860 | /* | |
6861 | * Free all VMCSs saved for this vcpu, except the one pointed by | |
4fa7734c PB |
6862 | * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs |
6863 | * must be &vmx->vmcs01. | |
ff2f6fe9 NHE |
6864 | */ |
6865 | static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx) | |
6866 | { | |
6867 | struct vmcs02_list *item, *n; | |
4fa7734c PB |
6868 | |
6869 | WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01); | |
ff2f6fe9 | 6870 | list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) { |
4fa7734c PB |
6871 | /* |
6872 | * Something will leak if the above WARN triggers. Better than | |
6873 | * a use-after-free. | |
6874 | */ | |
6875 | if (vmx->loaded_vmcs == &item->vmcs02) | |
6876 | continue; | |
6877 | ||
6878 | free_loaded_vmcs(&item->vmcs02); | |
ff2f6fe9 NHE |
6879 | list_del(&item->list); |
6880 | kfree(item); | |
4fa7734c | 6881 | vmx->nested.vmcs02_num--; |
ff2f6fe9 | 6882 | } |
ff2f6fe9 NHE |
6883 | } |
6884 | ||
0658fbaa ACL |
6885 | /* |
6886 | * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(), | |
6887 | * set the success or error code of an emulated VMX instruction, as specified | |
6888 | * by Vol 2B, VMX Instruction Reference, "Conventions". | |
6889 | */ | |
6890 | static void nested_vmx_succeed(struct kvm_vcpu *vcpu) | |
6891 | { | |
6892 | vmx_set_rflags(vcpu, vmx_get_rflags(vcpu) | |
6893 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
6894 | X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF)); | |
6895 | } | |
6896 | ||
6897 | static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu) | |
6898 | { | |
6899 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
6900 | & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | | |
6901 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
6902 | | X86_EFLAGS_CF); | |
6903 | } | |
6904 | ||
145c28dd | 6905 | static void nested_vmx_failValid(struct kvm_vcpu *vcpu, |
0658fbaa ACL |
6906 | u32 vm_instruction_error) |
6907 | { | |
6908 | if (to_vmx(vcpu)->nested.current_vmptr == -1ull) { | |
6909 | /* | |
6910 | * failValid writes the error number to the current VMCS, which | |
6911 | * can't be done there isn't a current VMCS. | |
6912 | */ | |
6913 | nested_vmx_failInvalid(vcpu); | |
6914 | return; | |
6915 | } | |
6916 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
6917 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
6918 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
6919 | | X86_EFLAGS_ZF); | |
6920 | get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error; | |
6921 | /* | |
6922 | * We don't need to force a shadow sync because | |
6923 | * VM_INSTRUCTION_ERROR is not shadowed | |
6924 | */ | |
6925 | } | |
145c28dd | 6926 | |
ff651cb6 WV |
6927 | static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator) |
6928 | { | |
6929 | /* TODO: not to reset guest simply here. */ | |
6930 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
bbe41b95 | 6931 | pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator); |
ff651cb6 WV |
6932 | } |
6933 | ||
f4124500 JK |
6934 | static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer) |
6935 | { | |
6936 | struct vcpu_vmx *vmx = | |
6937 | container_of(timer, struct vcpu_vmx, nested.preemption_timer); | |
6938 | ||
6939 | vmx->nested.preemption_timer_expired = true; | |
6940 | kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu); | |
6941 | kvm_vcpu_kick(&vmx->vcpu); | |
6942 | ||
6943 | return HRTIMER_NORESTART; | |
6944 | } | |
6945 | ||
19677e32 BD |
6946 | /* |
6947 | * Decode the memory-address operand of a vmx instruction, as recorded on an | |
6948 | * exit caused by such an instruction (run by a guest hypervisor). | |
6949 | * On success, returns 0. When the operand is invalid, returns 1 and throws | |
6950 | * #UD or #GP. | |
6951 | */ | |
6952 | static int get_vmx_mem_address(struct kvm_vcpu *vcpu, | |
6953 | unsigned long exit_qualification, | |
f9eb4af6 | 6954 | u32 vmx_instruction_info, bool wr, gva_t *ret) |
19677e32 | 6955 | { |
f9eb4af6 EK |
6956 | gva_t off; |
6957 | bool exn; | |
6958 | struct kvm_segment s; | |
6959 | ||
19677e32 BD |
6960 | /* |
6961 | * According to Vol. 3B, "Information for VM Exits Due to Instruction | |
6962 | * Execution", on an exit, vmx_instruction_info holds most of the | |
6963 | * addressing components of the operand. Only the displacement part | |
6964 | * is put in exit_qualification (see 3B, "Basic VM-Exit Information"). | |
6965 | * For how an actual address is calculated from all these components, | |
6966 | * refer to Vol. 1, "Operand Addressing". | |
6967 | */ | |
6968 | int scaling = vmx_instruction_info & 3; | |
6969 | int addr_size = (vmx_instruction_info >> 7) & 7; | |
6970 | bool is_reg = vmx_instruction_info & (1u << 10); | |
6971 | int seg_reg = (vmx_instruction_info >> 15) & 7; | |
6972 | int index_reg = (vmx_instruction_info >> 18) & 0xf; | |
6973 | bool index_is_valid = !(vmx_instruction_info & (1u << 22)); | |
6974 | int base_reg = (vmx_instruction_info >> 23) & 0xf; | |
6975 | bool base_is_valid = !(vmx_instruction_info & (1u << 27)); | |
6976 | ||
6977 | if (is_reg) { | |
6978 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6979 | return 1; | |
6980 | } | |
6981 | ||
6982 | /* Addr = segment_base + offset */ | |
6983 | /* offset = base + [index * scale] + displacement */ | |
f9eb4af6 | 6984 | off = exit_qualification; /* holds the displacement */ |
19677e32 | 6985 | if (base_is_valid) |
f9eb4af6 | 6986 | off += kvm_register_read(vcpu, base_reg); |
19677e32 | 6987 | if (index_is_valid) |
f9eb4af6 EK |
6988 | off += kvm_register_read(vcpu, index_reg)<<scaling; |
6989 | vmx_get_segment(vcpu, &s, seg_reg); | |
6990 | *ret = s.base + off; | |
19677e32 BD |
6991 | |
6992 | if (addr_size == 1) /* 32 bit */ | |
6993 | *ret &= 0xffffffff; | |
6994 | ||
f9eb4af6 EK |
6995 | /* Checks for #GP/#SS exceptions. */ |
6996 | exn = false; | |
ff30ef40 QC |
6997 | if (is_long_mode(vcpu)) { |
6998 | /* Long mode: #GP(0)/#SS(0) if the memory address is in a | |
6999 | * non-canonical form. This is the only check on the memory | |
7000 | * destination for long mode! | |
7001 | */ | |
7002 | exn = is_noncanonical_address(*ret); | |
7003 | } else if (is_protmode(vcpu)) { | |
f9eb4af6 EK |
7004 | /* Protected mode: apply checks for segment validity in the |
7005 | * following order: | |
7006 | * - segment type check (#GP(0) may be thrown) | |
7007 | * - usability check (#GP(0)/#SS(0)) | |
7008 | * - limit check (#GP(0)/#SS(0)) | |
7009 | */ | |
7010 | if (wr) | |
7011 | /* #GP(0) if the destination operand is located in a | |
7012 | * read-only data segment or any code segment. | |
7013 | */ | |
7014 | exn = ((s.type & 0xa) == 0 || (s.type & 8)); | |
7015 | else | |
7016 | /* #GP(0) if the source operand is located in an | |
7017 | * execute-only code segment | |
7018 | */ | |
7019 | exn = ((s.type & 0xa) == 8); | |
ff30ef40 QC |
7020 | if (exn) { |
7021 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
7022 | return 1; | |
7023 | } | |
f9eb4af6 EK |
7024 | /* Protected mode: #GP(0)/#SS(0) if the segment is unusable. |
7025 | */ | |
7026 | exn = (s.unusable != 0); | |
7027 | /* Protected mode: #GP(0)/#SS(0) if the memory | |
7028 | * operand is outside the segment limit. | |
7029 | */ | |
7030 | exn = exn || (off + sizeof(u64) > s.limit); | |
7031 | } | |
7032 | if (exn) { | |
7033 | kvm_queue_exception_e(vcpu, | |
7034 | seg_reg == VCPU_SREG_SS ? | |
7035 | SS_VECTOR : GP_VECTOR, | |
7036 | 0); | |
7037 | return 1; | |
7038 | } | |
7039 | ||
19677e32 BD |
7040 | return 0; |
7041 | } | |
7042 | ||
3573e22c BD |
7043 | /* |
7044 | * This function performs the various checks including | |
7045 | * - if it's 4KB aligned | |
7046 | * - No bits beyond the physical address width are set | |
7047 | * - Returns 0 on success or else 1 | |
4291b588 | 7048 | * (Intel SDM Section 30.3) |
3573e22c | 7049 | */ |
4291b588 BD |
7050 | static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason, |
7051 | gpa_t *vmpointer) | |
3573e22c BD |
7052 | { |
7053 | gva_t gva; | |
7054 | gpa_t vmptr; | |
7055 | struct x86_exception e; | |
7056 | struct page *page; | |
7057 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7058 | int maxphyaddr = cpuid_maxphyaddr(vcpu); | |
7059 | ||
7060 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
f9eb4af6 | 7061 | vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva)) |
3573e22c BD |
7062 | return 1; |
7063 | ||
7064 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr, | |
7065 | sizeof(vmptr), &e)) { | |
7066 | kvm_inject_page_fault(vcpu, &e); | |
7067 | return 1; | |
7068 | } | |
7069 | ||
7070 | switch (exit_reason) { | |
7071 | case EXIT_REASON_VMON: | |
7072 | /* | |
7073 | * SDM 3: 24.11.5 | |
7074 | * The first 4 bytes of VMXON region contain the supported | |
7075 | * VMCS revision identifier | |
7076 | * | |
7077 | * Note - IA32_VMX_BASIC[48] will never be 1 | |
7078 | * for the nested case; | |
7079 | * which replaces physical address width with 32 | |
7080 | * | |
7081 | */ | |
bc39c4db | 7082 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) { |
3573e22c | 7083 | nested_vmx_failInvalid(vcpu); |
6affcbed | 7084 | return kvm_skip_emulated_instruction(vcpu); |
3573e22c BD |
7085 | } |
7086 | ||
7087 | page = nested_get_page(vcpu, vmptr); | |
7088 | if (page == NULL || | |
7089 | *(u32 *)kmap(page) != VMCS12_REVISION) { | |
7090 | nested_vmx_failInvalid(vcpu); | |
7091 | kunmap(page); | |
6affcbed | 7092 | return kvm_skip_emulated_instruction(vcpu); |
3573e22c BD |
7093 | } |
7094 | kunmap(page); | |
7095 | vmx->nested.vmxon_ptr = vmptr; | |
7096 | break; | |
4291b588 | 7097 | case EXIT_REASON_VMCLEAR: |
bc39c4db | 7098 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) { |
4291b588 BD |
7099 | nested_vmx_failValid(vcpu, |
7100 | VMXERR_VMCLEAR_INVALID_ADDRESS); | |
6affcbed | 7101 | return kvm_skip_emulated_instruction(vcpu); |
4291b588 BD |
7102 | } |
7103 | ||
7104 | if (vmptr == vmx->nested.vmxon_ptr) { | |
7105 | nested_vmx_failValid(vcpu, | |
7106 | VMXERR_VMCLEAR_VMXON_POINTER); | |
6affcbed | 7107 | return kvm_skip_emulated_instruction(vcpu); |
4291b588 BD |
7108 | } |
7109 | break; | |
7110 | case EXIT_REASON_VMPTRLD: | |
bc39c4db | 7111 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) { |
4291b588 BD |
7112 | nested_vmx_failValid(vcpu, |
7113 | VMXERR_VMPTRLD_INVALID_ADDRESS); | |
6affcbed | 7114 | return kvm_skip_emulated_instruction(vcpu); |
4291b588 | 7115 | } |
3573e22c | 7116 | |
4291b588 BD |
7117 | if (vmptr == vmx->nested.vmxon_ptr) { |
7118 | nested_vmx_failValid(vcpu, | |
7119 | VMXERR_VMCLEAR_VMXON_POINTER); | |
6affcbed | 7120 | return kvm_skip_emulated_instruction(vcpu); |
4291b588 BD |
7121 | } |
7122 | break; | |
3573e22c BD |
7123 | default: |
7124 | return 1; /* shouldn't happen */ | |
7125 | } | |
7126 | ||
4291b588 BD |
7127 | if (vmpointer) |
7128 | *vmpointer = vmptr; | |
3573e22c BD |
7129 | return 0; |
7130 | } | |
7131 | ||
ec378aee NHE |
7132 | /* |
7133 | * Emulate the VMXON instruction. | |
7134 | * Currently, we just remember that VMX is active, and do not save or even | |
7135 | * inspect the argument to VMXON (the so-called "VMXON pointer") because we | |
7136 | * do not currently need to store anything in that guest-allocated memory | |
7137 | * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their | |
7138 | * argument is different from the VMXON pointer (which the spec says they do). | |
7139 | */ | |
7140 | static int handle_vmon(struct kvm_vcpu *vcpu) | |
7141 | { | |
7142 | struct kvm_segment cs; | |
7143 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8de48833 | 7144 | struct vmcs *shadow_vmcs; |
b3897a49 NHE |
7145 | const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED |
7146 | | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
ec378aee NHE |
7147 | |
7148 | /* The Intel VMX Instruction Reference lists a bunch of bits that | |
7149 | * are prerequisite to running VMXON, most notably cr4.VMXE must be | |
7150 | * set to 1 (see vmx_set_cr4() for when we allow the guest to set this). | |
7151 | * Otherwise, we should fail with #UD. We test these now: | |
7152 | */ | |
7153 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) || | |
7154 | !kvm_read_cr0_bits(vcpu, X86_CR0_PE) || | |
7155 | (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { | |
7156 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7157 | return 1; | |
7158 | } | |
7159 | ||
7160 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
7161 | if (is_long_mode(vcpu) && !cs.l) { | |
7162 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7163 | return 1; | |
7164 | } | |
7165 | ||
7166 | if (vmx_get_cpl(vcpu)) { | |
7167 | kvm_inject_gp(vcpu, 0); | |
7168 | return 1; | |
7169 | } | |
3573e22c | 7170 | |
4291b588 | 7171 | if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL)) |
3573e22c BD |
7172 | return 1; |
7173 | ||
145c28dd AG |
7174 | if (vmx->nested.vmxon) { |
7175 | nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION); | |
6affcbed | 7176 | return kvm_skip_emulated_instruction(vcpu); |
145c28dd | 7177 | } |
b3897a49 | 7178 | |
3b84080b | 7179 | if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES) |
b3897a49 NHE |
7180 | != VMXON_NEEDED_FEATURES) { |
7181 | kvm_inject_gp(vcpu, 0); | |
7182 | return 1; | |
7183 | } | |
7184 | ||
d048c098 RK |
7185 | if (cpu_has_vmx_msr_bitmap()) { |
7186 | vmx->nested.msr_bitmap = | |
7187 | (unsigned long *)__get_free_page(GFP_KERNEL); | |
7188 | if (!vmx->nested.msr_bitmap) | |
7189 | goto out_msr_bitmap; | |
7190 | } | |
7191 | ||
4f2777bc DM |
7192 | vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL); |
7193 | if (!vmx->nested.cached_vmcs12) | |
d048c098 | 7194 | goto out_cached_vmcs12; |
4f2777bc | 7195 | |
8de48833 AG |
7196 | if (enable_shadow_vmcs) { |
7197 | shadow_vmcs = alloc_vmcs(); | |
d048c098 RK |
7198 | if (!shadow_vmcs) |
7199 | goto out_shadow_vmcs; | |
8de48833 AG |
7200 | /* mark vmcs as shadow */ |
7201 | shadow_vmcs->revision_id |= (1u << 31); | |
7202 | /* init shadow vmcs */ | |
7203 | vmcs_clear(shadow_vmcs); | |
355f4fb1 | 7204 | vmx->vmcs01.shadow_vmcs = shadow_vmcs; |
8de48833 | 7205 | } |
ec378aee | 7206 | |
ff2f6fe9 NHE |
7207 | INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool)); |
7208 | vmx->nested.vmcs02_num = 0; | |
7209 | ||
f4124500 | 7210 | hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC, |
f15a75ee | 7211 | HRTIMER_MODE_REL_PINNED); |
f4124500 JK |
7212 | vmx->nested.preemption_timer.function = vmx_preemption_timer_fn; |
7213 | ||
ec378aee NHE |
7214 | vmx->nested.vmxon = true; |
7215 | ||
a25eb114 | 7216 | nested_vmx_succeed(vcpu); |
6affcbed | 7217 | return kvm_skip_emulated_instruction(vcpu); |
d048c098 RK |
7218 | |
7219 | out_shadow_vmcs: | |
7220 | kfree(vmx->nested.cached_vmcs12); | |
7221 | ||
7222 | out_cached_vmcs12: | |
7223 | free_page((unsigned long)vmx->nested.msr_bitmap); | |
7224 | ||
7225 | out_msr_bitmap: | |
7226 | return -ENOMEM; | |
ec378aee NHE |
7227 | } |
7228 | ||
7229 | /* | |
7230 | * Intel's VMX Instruction Reference specifies a common set of prerequisites | |
7231 | * for running VMX instructions (except VMXON, whose prerequisites are | |
7232 | * slightly different). It also specifies what exception to inject otherwise. | |
7233 | */ | |
7234 | static int nested_vmx_check_permission(struct kvm_vcpu *vcpu) | |
7235 | { | |
7236 | struct kvm_segment cs; | |
7237 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7238 | ||
7239 | if (!vmx->nested.vmxon) { | |
7240 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7241 | return 0; | |
7242 | } | |
7243 | ||
7244 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
7245 | if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) || | |
7246 | (is_long_mode(vcpu) && !cs.l)) { | |
7247 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7248 | return 0; | |
7249 | } | |
7250 | ||
7251 | if (vmx_get_cpl(vcpu)) { | |
7252 | kvm_inject_gp(vcpu, 0); | |
7253 | return 0; | |
7254 | } | |
7255 | ||
7256 | return 1; | |
7257 | } | |
7258 | ||
e7953d7f AG |
7259 | static inline void nested_release_vmcs12(struct vcpu_vmx *vmx) |
7260 | { | |
9a2a05b9 PB |
7261 | if (vmx->nested.current_vmptr == -1ull) |
7262 | return; | |
7263 | ||
7264 | /* current_vmptr and current_vmcs12 are always set/reset together */ | |
7265 | if (WARN_ON(vmx->nested.current_vmcs12 == NULL)) | |
7266 | return; | |
7267 | ||
012f83cb | 7268 | if (enable_shadow_vmcs) { |
9a2a05b9 PB |
7269 | /* copy to memory all shadowed fields in case |
7270 | they were modified */ | |
7271 | copy_shadow_to_vmcs12(vmx); | |
7272 | vmx->nested.sync_shadow_vmcs = false; | |
7ec36296 XG |
7273 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, |
7274 | SECONDARY_EXEC_SHADOW_VMCS); | |
9a2a05b9 | 7275 | vmcs_write64(VMCS_LINK_POINTER, -1ull); |
012f83cb | 7276 | } |
705699a1 | 7277 | vmx->nested.posted_intr_nv = -1; |
4f2777bc DM |
7278 | |
7279 | /* Flush VMCS12 to guest memory */ | |
7280 | memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12, | |
7281 | VMCS12_SIZE); | |
7282 | ||
e7953d7f AG |
7283 | kunmap(vmx->nested.current_vmcs12_page); |
7284 | nested_release_page(vmx->nested.current_vmcs12_page); | |
9a2a05b9 PB |
7285 | vmx->nested.current_vmptr = -1ull; |
7286 | vmx->nested.current_vmcs12 = NULL; | |
e7953d7f AG |
7287 | } |
7288 | ||
ec378aee NHE |
7289 | /* |
7290 | * Free whatever needs to be freed from vmx->nested when L1 goes down, or | |
7291 | * just stops using VMX. | |
7292 | */ | |
7293 | static void free_nested(struct vcpu_vmx *vmx) | |
7294 | { | |
7295 | if (!vmx->nested.vmxon) | |
7296 | return; | |
9a2a05b9 | 7297 | |
ec378aee | 7298 | vmx->nested.vmxon = false; |
5c614b35 | 7299 | free_vpid(vmx->nested.vpid02); |
9a2a05b9 | 7300 | nested_release_vmcs12(vmx); |
d048c098 RK |
7301 | if (vmx->nested.msr_bitmap) { |
7302 | free_page((unsigned long)vmx->nested.msr_bitmap); | |
7303 | vmx->nested.msr_bitmap = NULL; | |
7304 | } | |
355f4fb1 JM |
7305 | if (enable_shadow_vmcs) { |
7306 | vmcs_clear(vmx->vmcs01.shadow_vmcs); | |
7307 | free_vmcs(vmx->vmcs01.shadow_vmcs); | |
7308 | vmx->vmcs01.shadow_vmcs = NULL; | |
7309 | } | |
4f2777bc | 7310 | kfree(vmx->nested.cached_vmcs12); |
fe3ef05c NHE |
7311 | /* Unpin physical memory we referred to in current vmcs02 */ |
7312 | if (vmx->nested.apic_access_page) { | |
7313 | nested_release_page(vmx->nested.apic_access_page); | |
48d89b92 | 7314 | vmx->nested.apic_access_page = NULL; |
fe3ef05c | 7315 | } |
a7c0b07d WL |
7316 | if (vmx->nested.virtual_apic_page) { |
7317 | nested_release_page(vmx->nested.virtual_apic_page); | |
48d89b92 | 7318 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 7319 | } |
705699a1 WV |
7320 | if (vmx->nested.pi_desc_page) { |
7321 | kunmap(vmx->nested.pi_desc_page); | |
7322 | nested_release_page(vmx->nested.pi_desc_page); | |
7323 | vmx->nested.pi_desc_page = NULL; | |
7324 | vmx->nested.pi_desc = NULL; | |
7325 | } | |
ff2f6fe9 NHE |
7326 | |
7327 | nested_free_all_saved_vmcss(vmx); | |
ec378aee NHE |
7328 | } |
7329 | ||
7330 | /* Emulate the VMXOFF instruction */ | |
7331 | static int handle_vmoff(struct kvm_vcpu *vcpu) | |
7332 | { | |
7333 | if (!nested_vmx_check_permission(vcpu)) | |
7334 | return 1; | |
7335 | free_nested(to_vmx(vcpu)); | |
a25eb114 | 7336 | nested_vmx_succeed(vcpu); |
6affcbed | 7337 | return kvm_skip_emulated_instruction(vcpu); |
ec378aee NHE |
7338 | } |
7339 | ||
27d6c865 NHE |
7340 | /* Emulate the VMCLEAR instruction */ |
7341 | static int handle_vmclear(struct kvm_vcpu *vcpu) | |
7342 | { | |
7343 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
27d6c865 NHE |
7344 | gpa_t vmptr; |
7345 | struct vmcs12 *vmcs12; | |
7346 | struct page *page; | |
27d6c865 NHE |
7347 | |
7348 | if (!nested_vmx_check_permission(vcpu)) | |
7349 | return 1; | |
7350 | ||
4291b588 | 7351 | if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr)) |
27d6c865 | 7352 | return 1; |
27d6c865 | 7353 | |
9a2a05b9 | 7354 | if (vmptr == vmx->nested.current_vmptr) |
e7953d7f | 7355 | nested_release_vmcs12(vmx); |
27d6c865 NHE |
7356 | |
7357 | page = nested_get_page(vcpu, vmptr); | |
7358 | if (page == NULL) { | |
7359 | /* | |
7360 | * For accurate processor emulation, VMCLEAR beyond available | |
7361 | * physical memory should do nothing at all. However, it is | |
7362 | * possible that a nested vmx bug, not a guest hypervisor bug, | |
7363 | * resulted in this case, so let's shut down before doing any | |
7364 | * more damage: | |
7365 | */ | |
7366 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
7367 | return 1; | |
7368 | } | |
7369 | vmcs12 = kmap(page); | |
7370 | vmcs12->launch_state = 0; | |
7371 | kunmap(page); | |
7372 | nested_release_page(page); | |
7373 | ||
7374 | nested_free_vmcs02(vmx, vmptr); | |
7375 | ||
27d6c865 | 7376 | nested_vmx_succeed(vcpu); |
6affcbed | 7377 | return kvm_skip_emulated_instruction(vcpu); |
27d6c865 NHE |
7378 | } |
7379 | ||
cd232ad0 NHE |
7380 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch); |
7381 | ||
7382 | /* Emulate the VMLAUNCH instruction */ | |
7383 | static int handle_vmlaunch(struct kvm_vcpu *vcpu) | |
7384 | { | |
7385 | return nested_vmx_run(vcpu, true); | |
7386 | } | |
7387 | ||
7388 | /* Emulate the VMRESUME instruction */ | |
7389 | static int handle_vmresume(struct kvm_vcpu *vcpu) | |
7390 | { | |
7391 | ||
7392 | return nested_vmx_run(vcpu, false); | |
7393 | } | |
7394 | ||
49f705c5 NHE |
7395 | enum vmcs_field_type { |
7396 | VMCS_FIELD_TYPE_U16 = 0, | |
7397 | VMCS_FIELD_TYPE_U64 = 1, | |
7398 | VMCS_FIELD_TYPE_U32 = 2, | |
7399 | VMCS_FIELD_TYPE_NATURAL_WIDTH = 3 | |
7400 | }; | |
7401 | ||
7402 | static inline int vmcs_field_type(unsigned long field) | |
7403 | { | |
7404 | if (0x1 & field) /* the *_HIGH fields are all 32 bit */ | |
7405 | return VMCS_FIELD_TYPE_U32; | |
7406 | return (field >> 13) & 0x3 ; | |
7407 | } | |
7408 | ||
7409 | static inline int vmcs_field_readonly(unsigned long field) | |
7410 | { | |
7411 | return (((field >> 10) & 0x3) == 1); | |
7412 | } | |
7413 | ||
7414 | /* | |
7415 | * Read a vmcs12 field. Since these can have varying lengths and we return | |
7416 | * one type, we chose the biggest type (u64) and zero-extend the return value | |
7417 | * to that size. Note that the caller, handle_vmread, might need to use only | |
7418 | * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of | |
7419 | * 64-bit fields are to be returned). | |
7420 | */ | |
a2ae9df7 PB |
7421 | static inline int vmcs12_read_any(struct kvm_vcpu *vcpu, |
7422 | unsigned long field, u64 *ret) | |
49f705c5 NHE |
7423 | { |
7424 | short offset = vmcs_field_to_offset(field); | |
7425 | char *p; | |
7426 | ||
7427 | if (offset < 0) | |
a2ae9df7 | 7428 | return offset; |
49f705c5 NHE |
7429 | |
7430 | p = ((char *)(get_vmcs12(vcpu))) + offset; | |
7431 | ||
7432 | switch (vmcs_field_type(field)) { | |
7433 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7434 | *ret = *((natural_width *)p); | |
a2ae9df7 | 7435 | return 0; |
49f705c5 NHE |
7436 | case VMCS_FIELD_TYPE_U16: |
7437 | *ret = *((u16 *)p); | |
a2ae9df7 | 7438 | return 0; |
49f705c5 NHE |
7439 | case VMCS_FIELD_TYPE_U32: |
7440 | *ret = *((u32 *)p); | |
a2ae9df7 | 7441 | return 0; |
49f705c5 NHE |
7442 | case VMCS_FIELD_TYPE_U64: |
7443 | *ret = *((u64 *)p); | |
a2ae9df7 | 7444 | return 0; |
49f705c5 | 7445 | default: |
a2ae9df7 PB |
7446 | WARN_ON(1); |
7447 | return -ENOENT; | |
49f705c5 NHE |
7448 | } |
7449 | } | |
7450 | ||
20b97fea | 7451 | |
a2ae9df7 PB |
7452 | static inline int vmcs12_write_any(struct kvm_vcpu *vcpu, |
7453 | unsigned long field, u64 field_value){ | |
20b97fea AG |
7454 | short offset = vmcs_field_to_offset(field); |
7455 | char *p = ((char *) get_vmcs12(vcpu)) + offset; | |
7456 | if (offset < 0) | |
a2ae9df7 | 7457 | return offset; |
20b97fea AG |
7458 | |
7459 | switch (vmcs_field_type(field)) { | |
7460 | case VMCS_FIELD_TYPE_U16: | |
7461 | *(u16 *)p = field_value; | |
a2ae9df7 | 7462 | return 0; |
20b97fea AG |
7463 | case VMCS_FIELD_TYPE_U32: |
7464 | *(u32 *)p = field_value; | |
a2ae9df7 | 7465 | return 0; |
20b97fea AG |
7466 | case VMCS_FIELD_TYPE_U64: |
7467 | *(u64 *)p = field_value; | |
a2ae9df7 | 7468 | return 0; |
20b97fea AG |
7469 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: |
7470 | *(natural_width *)p = field_value; | |
a2ae9df7 | 7471 | return 0; |
20b97fea | 7472 | default: |
a2ae9df7 PB |
7473 | WARN_ON(1); |
7474 | return -ENOENT; | |
20b97fea AG |
7475 | } |
7476 | ||
7477 | } | |
7478 | ||
16f5b903 AG |
7479 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx) |
7480 | { | |
7481 | int i; | |
7482 | unsigned long field; | |
7483 | u64 field_value; | |
355f4fb1 | 7484 | struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; |
c2bae893 MK |
7485 | const unsigned long *fields = shadow_read_write_fields; |
7486 | const int num_fields = max_shadow_read_write_fields; | |
16f5b903 | 7487 | |
282da870 JK |
7488 | preempt_disable(); |
7489 | ||
16f5b903 AG |
7490 | vmcs_load(shadow_vmcs); |
7491 | ||
7492 | for (i = 0; i < num_fields; i++) { | |
7493 | field = fields[i]; | |
7494 | switch (vmcs_field_type(field)) { | |
7495 | case VMCS_FIELD_TYPE_U16: | |
7496 | field_value = vmcs_read16(field); | |
7497 | break; | |
7498 | case VMCS_FIELD_TYPE_U32: | |
7499 | field_value = vmcs_read32(field); | |
7500 | break; | |
7501 | case VMCS_FIELD_TYPE_U64: | |
7502 | field_value = vmcs_read64(field); | |
7503 | break; | |
7504 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7505 | field_value = vmcs_readl(field); | |
7506 | break; | |
a2ae9df7 PB |
7507 | default: |
7508 | WARN_ON(1); | |
7509 | continue; | |
16f5b903 AG |
7510 | } |
7511 | vmcs12_write_any(&vmx->vcpu, field, field_value); | |
7512 | } | |
7513 | ||
7514 | vmcs_clear(shadow_vmcs); | |
7515 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
282da870 JK |
7516 | |
7517 | preempt_enable(); | |
16f5b903 AG |
7518 | } |
7519 | ||
c3114420 AG |
7520 | static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx) |
7521 | { | |
c2bae893 MK |
7522 | const unsigned long *fields[] = { |
7523 | shadow_read_write_fields, | |
7524 | shadow_read_only_fields | |
c3114420 | 7525 | }; |
c2bae893 | 7526 | const int max_fields[] = { |
c3114420 AG |
7527 | max_shadow_read_write_fields, |
7528 | max_shadow_read_only_fields | |
7529 | }; | |
7530 | int i, q; | |
7531 | unsigned long field; | |
7532 | u64 field_value = 0; | |
355f4fb1 | 7533 | struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; |
c3114420 AG |
7534 | |
7535 | vmcs_load(shadow_vmcs); | |
7536 | ||
c2bae893 | 7537 | for (q = 0; q < ARRAY_SIZE(fields); q++) { |
c3114420 AG |
7538 | for (i = 0; i < max_fields[q]; i++) { |
7539 | field = fields[q][i]; | |
7540 | vmcs12_read_any(&vmx->vcpu, field, &field_value); | |
7541 | ||
7542 | switch (vmcs_field_type(field)) { | |
7543 | case VMCS_FIELD_TYPE_U16: | |
7544 | vmcs_write16(field, (u16)field_value); | |
7545 | break; | |
7546 | case VMCS_FIELD_TYPE_U32: | |
7547 | vmcs_write32(field, (u32)field_value); | |
7548 | break; | |
7549 | case VMCS_FIELD_TYPE_U64: | |
7550 | vmcs_write64(field, (u64)field_value); | |
7551 | break; | |
7552 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7553 | vmcs_writel(field, (long)field_value); | |
7554 | break; | |
a2ae9df7 PB |
7555 | default: |
7556 | WARN_ON(1); | |
7557 | break; | |
c3114420 AG |
7558 | } |
7559 | } | |
7560 | } | |
7561 | ||
7562 | vmcs_clear(shadow_vmcs); | |
7563 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
7564 | } | |
7565 | ||
49f705c5 NHE |
7566 | /* |
7567 | * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was | |
7568 | * used before) all generate the same failure when it is missing. | |
7569 | */ | |
7570 | static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu) | |
7571 | { | |
7572 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7573 | if (vmx->nested.current_vmptr == -1ull) { | |
7574 | nested_vmx_failInvalid(vcpu); | |
49f705c5 NHE |
7575 | return 0; |
7576 | } | |
7577 | return 1; | |
7578 | } | |
7579 | ||
7580 | static int handle_vmread(struct kvm_vcpu *vcpu) | |
7581 | { | |
7582 | unsigned long field; | |
7583 | u64 field_value; | |
7584 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7585 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7586 | gva_t gva = 0; | |
7587 | ||
eb277562 KH |
7588 | if (!nested_vmx_check_permission(vcpu)) |
7589 | return 1; | |
7590 | ||
6affcbed KH |
7591 | if (!nested_vmx_check_vmcs12(vcpu)) |
7592 | return kvm_skip_emulated_instruction(vcpu); | |
49f705c5 NHE |
7593 | |
7594 | /* Decode instruction info and find the field to read */ | |
27e6fb5d | 7595 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 | 7596 | /* Read the field, zero-extended to a u64 field_value */ |
a2ae9df7 | 7597 | if (vmcs12_read_any(vcpu, field, &field_value) < 0) { |
49f705c5 | 7598 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
6affcbed | 7599 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7600 | } |
7601 | /* | |
7602 | * Now copy part of this value to register or memory, as requested. | |
7603 | * Note that the number of bits actually copied is 32 or 64 depending | |
7604 | * on the guest's mode (32 or 64 bit), not on the given field's length. | |
7605 | */ | |
7606 | if (vmx_instruction_info & (1u << 10)) { | |
27e6fb5d | 7607 | kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf), |
49f705c5 NHE |
7608 | field_value); |
7609 | } else { | |
7610 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7611 | vmx_instruction_info, true, &gva)) |
49f705c5 NHE |
7612 | return 1; |
7613 | /* _system ok, as nested_vmx_check_permission verified cpl=0 */ | |
7614 | kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva, | |
7615 | &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL); | |
7616 | } | |
7617 | ||
7618 | nested_vmx_succeed(vcpu); | |
6affcbed | 7619 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7620 | } |
7621 | ||
7622 | ||
7623 | static int handle_vmwrite(struct kvm_vcpu *vcpu) | |
7624 | { | |
7625 | unsigned long field; | |
7626 | gva_t gva; | |
7627 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7628 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
49f705c5 NHE |
7629 | /* The value to write might be 32 or 64 bits, depending on L1's long |
7630 | * mode, and eventually we need to write that into a field of several | |
7631 | * possible lengths. The code below first zero-extends the value to 64 | |
6a6256f9 | 7632 | * bit (field_value), and then copies only the appropriate number of |
49f705c5 NHE |
7633 | * bits into the vmcs12 field. |
7634 | */ | |
7635 | u64 field_value = 0; | |
7636 | struct x86_exception e; | |
7637 | ||
eb277562 | 7638 | if (!nested_vmx_check_permission(vcpu)) |
49f705c5 NHE |
7639 | return 1; |
7640 | ||
6affcbed KH |
7641 | if (!nested_vmx_check_vmcs12(vcpu)) |
7642 | return kvm_skip_emulated_instruction(vcpu); | |
eb277562 | 7643 | |
49f705c5 | 7644 | if (vmx_instruction_info & (1u << 10)) |
27e6fb5d | 7645 | field_value = kvm_register_readl(vcpu, |
49f705c5 NHE |
7646 | (((vmx_instruction_info) >> 3) & 0xf)); |
7647 | else { | |
7648 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7649 | vmx_instruction_info, false, &gva)) |
49f705c5 NHE |
7650 | return 1; |
7651 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, | |
27e6fb5d | 7652 | &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) { |
49f705c5 NHE |
7653 | kvm_inject_page_fault(vcpu, &e); |
7654 | return 1; | |
7655 | } | |
7656 | } | |
7657 | ||
7658 | ||
27e6fb5d | 7659 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 NHE |
7660 | if (vmcs_field_readonly(field)) { |
7661 | nested_vmx_failValid(vcpu, | |
7662 | VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT); | |
6affcbed | 7663 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7664 | } |
7665 | ||
a2ae9df7 | 7666 | if (vmcs12_write_any(vcpu, field, field_value) < 0) { |
49f705c5 | 7667 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
6affcbed | 7668 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7669 | } |
7670 | ||
7671 | nested_vmx_succeed(vcpu); | |
6affcbed | 7672 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7673 | } |
7674 | ||
63846663 NHE |
7675 | /* Emulate the VMPTRLD instruction */ |
7676 | static int handle_vmptrld(struct kvm_vcpu *vcpu) | |
7677 | { | |
7678 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
63846663 | 7679 | gpa_t vmptr; |
63846663 NHE |
7680 | |
7681 | if (!nested_vmx_check_permission(vcpu)) | |
7682 | return 1; | |
7683 | ||
4291b588 | 7684 | if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr)) |
63846663 | 7685 | return 1; |
63846663 NHE |
7686 | |
7687 | if (vmx->nested.current_vmptr != vmptr) { | |
7688 | struct vmcs12 *new_vmcs12; | |
7689 | struct page *page; | |
7690 | page = nested_get_page(vcpu, vmptr); | |
7691 | if (page == NULL) { | |
7692 | nested_vmx_failInvalid(vcpu); | |
6affcbed | 7693 | return kvm_skip_emulated_instruction(vcpu); |
63846663 NHE |
7694 | } |
7695 | new_vmcs12 = kmap(page); | |
7696 | if (new_vmcs12->revision_id != VMCS12_REVISION) { | |
7697 | kunmap(page); | |
7698 | nested_release_page_clean(page); | |
7699 | nested_vmx_failValid(vcpu, | |
7700 | VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID); | |
6affcbed | 7701 | return kvm_skip_emulated_instruction(vcpu); |
63846663 | 7702 | } |
63846663 | 7703 | |
9a2a05b9 | 7704 | nested_release_vmcs12(vmx); |
63846663 NHE |
7705 | vmx->nested.current_vmptr = vmptr; |
7706 | vmx->nested.current_vmcs12 = new_vmcs12; | |
7707 | vmx->nested.current_vmcs12_page = page; | |
4f2777bc DM |
7708 | /* |
7709 | * Load VMCS12 from guest memory since it is not already | |
7710 | * cached. | |
7711 | */ | |
7712 | memcpy(vmx->nested.cached_vmcs12, | |
7713 | vmx->nested.current_vmcs12, VMCS12_SIZE); | |
7714 | ||
012f83cb | 7715 | if (enable_shadow_vmcs) { |
7ec36296 XG |
7716 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, |
7717 | SECONDARY_EXEC_SHADOW_VMCS); | |
8a1b9dd0 | 7718 | vmcs_write64(VMCS_LINK_POINTER, |
355f4fb1 | 7719 | __pa(vmx->vmcs01.shadow_vmcs)); |
012f83cb AG |
7720 | vmx->nested.sync_shadow_vmcs = true; |
7721 | } | |
63846663 NHE |
7722 | } |
7723 | ||
7724 | nested_vmx_succeed(vcpu); | |
6affcbed | 7725 | return kvm_skip_emulated_instruction(vcpu); |
63846663 NHE |
7726 | } |
7727 | ||
6a4d7550 NHE |
7728 | /* Emulate the VMPTRST instruction */ |
7729 | static int handle_vmptrst(struct kvm_vcpu *vcpu) | |
7730 | { | |
7731 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7732 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7733 | gva_t vmcs_gva; | |
7734 | struct x86_exception e; | |
7735 | ||
7736 | if (!nested_vmx_check_permission(vcpu)) | |
7737 | return 1; | |
7738 | ||
7739 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7740 | vmx_instruction_info, true, &vmcs_gva)) |
6a4d7550 NHE |
7741 | return 1; |
7742 | /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */ | |
7743 | if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva, | |
7744 | (void *)&to_vmx(vcpu)->nested.current_vmptr, | |
7745 | sizeof(u64), &e)) { | |
7746 | kvm_inject_page_fault(vcpu, &e); | |
7747 | return 1; | |
7748 | } | |
7749 | nested_vmx_succeed(vcpu); | |
6affcbed | 7750 | return kvm_skip_emulated_instruction(vcpu); |
6a4d7550 NHE |
7751 | } |
7752 | ||
bfd0a56b NHE |
7753 | /* Emulate the INVEPT instruction */ |
7754 | static int handle_invept(struct kvm_vcpu *vcpu) | |
7755 | { | |
b9c237bb | 7756 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
bfd0a56b NHE |
7757 | u32 vmx_instruction_info, types; |
7758 | unsigned long type; | |
7759 | gva_t gva; | |
7760 | struct x86_exception e; | |
7761 | struct { | |
7762 | u64 eptp, gpa; | |
7763 | } operand; | |
bfd0a56b | 7764 | |
b9c237bb WV |
7765 | if (!(vmx->nested.nested_vmx_secondary_ctls_high & |
7766 | SECONDARY_EXEC_ENABLE_EPT) || | |
7767 | !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) { | |
bfd0a56b NHE |
7768 | kvm_queue_exception(vcpu, UD_VECTOR); |
7769 | return 1; | |
7770 | } | |
7771 | ||
7772 | if (!nested_vmx_check_permission(vcpu)) | |
7773 | return 1; | |
7774 | ||
7775 | if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) { | |
7776 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7777 | return 1; | |
7778 | } | |
7779 | ||
7780 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
27e6fb5d | 7781 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); |
bfd0a56b | 7782 | |
b9c237bb | 7783 | types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6; |
bfd0a56b | 7784 | |
85c856b3 | 7785 | if (type >= 32 || !(types & (1 << type))) { |
bfd0a56b NHE |
7786 | nested_vmx_failValid(vcpu, |
7787 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 7788 | return kvm_skip_emulated_instruction(vcpu); |
bfd0a56b NHE |
7789 | } |
7790 | ||
7791 | /* According to the Intel VMX instruction reference, the memory | |
7792 | * operand is read even if it isn't needed (e.g., for type==global) | |
7793 | */ | |
7794 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
f9eb4af6 | 7795 | vmx_instruction_info, false, &gva)) |
bfd0a56b NHE |
7796 | return 1; |
7797 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand, | |
7798 | sizeof(operand), &e)) { | |
7799 | kvm_inject_page_fault(vcpu, &e); | |
7800 | return 1; | |
7801 | } | |
7802 | ||
7803 | switch (type) { | |
bfd0a56b | 7804 | case VMX_EPT_EXTENT_GLOBAL: |
45e11817 BD |
7805 | /* |
7806 | * TODO: track mappings and invalidate | |
7807 | * single context requests appropriately | |
7808 | */ | |
7809 | case VMX_EPT_EXTENT_CONTEXT: | |
bfd0a56b | 7810 | kvm_mmu_sync_roots(vcpu); |
77c3913b | 7811 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
bfd0a56b NHE |
7812 | nested_vmx_succeed(vcpu); |
7813 | break; | |
7814 | default: | |
7815 | BUG_ON(1); | |
7816 | break; | |
7817 | } | |
7818 | ||
6affcbed | 7819 | return kvm_skip_emulated_instruction(vcpu); |
bfd0a56b NHE |
7820 | } |
7821 | ||
a642fc30 PM |
7822 | static int handle_invvpid(struct kvm_vcpu *vcpu) |
7823 | { | |
99b83ac8 WL |
7824 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
7825 | u32 vmx_instruction_info; | |
7826 | unsigned long type, types; | |
7827 | gva_t gva; | |
7828 | struct x86_exception e; | |
7829 | int vpid; | |
7830 | ||
7831 | if (!(vmx->nested.nested_vmx_secondary_ctls_high & | |
7832 | SECONDARY_EXEC_ENABLE_VPID) || | |
7833 | !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) { | |
7834 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7835 | return 1; | |
7836 | } | |
7837 | ||
7838 | if (!nested_vmx_check_permission(vcpu)) | |
7839 | return 1; | |
7840 | ||
7841 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7842 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); | |
7843 | ||
bcdde302 JD |
7844 | types = (vmx->nested.nested_vmx_vpid_caps & |
7845 | VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8; | |
99b83ac8 | 7846 | |
85c856b3 | 7847 | if (type >= 32 || !(types & (1 << type))) { |
99b83ac8 WL |
7848 | nested_vmx_failValid(vcpu, |
7849 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 7850 | return kvm_skip_emulated_instruction(vcpu); |
99b83ac8 WL |
7851 | } |
7852 | ||
7853 | /* according to the intel vmx instruction reference, the memory | |
7854 | * operand is read even if it isn't needed (e.g., for type==global) | |
7855 | */ | |
7856 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
7857 | vmx_instruction_info, false, &gva)) | |
7858 | return 1; | |
7859 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid, | |
7860 | sizeof(u32), &e)) { | |
7861 | kvm_inject_page_fault(vcpu, &e); | |
7862 | return 1; | |
7863 | } | |
7864 | ||
7865 | switch (type) { | |
bcdde302 | 7866 | case VMX_VPID_EXTENT_INDIVIDUAL_ADDR: |
ef697a71 | 7867 | case VMX_VPID_EXTENT_SINGLE_CONTEXT: |
bcdde302 JD |
7868 | case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL: |
7869 | if (!vpid) { | |
7870 | nested_vmx_failValid(vcpu, | |
7871 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 7872 | return kvm_skip_emulated_instruction(vcpu); |
bcdde302 JD |
7873 | } |
7874 | break; | |
99b83ac8 | 7875 | case VMX_VPID_EXTENT_ALL_CONTEXT: |
99b83ac8 WL |
7876 | break; |
7877 | default: | |
bcdde302 | 7878 | WARN_ON_ONCE(1); |
6affcbed | 7879 | return kvm_skip_emulated_instruction(vcpu); |
99b83ac8 WL |
7880 | } |
7881 | ||
bcdde302 JD |
7882 | __vmx_flush_tlb(vcpu, vmx->nested.vpid02); |
7883 | nested_vmx_succeed(vcpu); | |
7884 | ||
6affcbed | 7885 | return kvm_skip_emulated_instruction(vcpu); |
a642fc30 PM |
7886 | } |
7887 | ||
843e4330 KH |
7888 | static int handle_pml_full(struct kvm_vcpu *vcpu) |
7889 | { | |
7890 | unsigned long exit_qualification; | |
7891 | ||
7892 | trace_kvm_pml_full(vcpu->vcpu_id); | |
7893 | ||
7894 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7895 | ||
7896 | /* | |
7897 | * PML buffer FULL happened while executing iret from NMI, | |
7898 | * "blocked by NMI" bit has to be set before next VM entry. | |
7899 | */ | |
7900 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && | |
7901 | cpu_has_virtual_nmis() && | |
7902 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) | |
7903 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
7904 | GUEST_INTR_STATE_NMI); | |
7905 | ||
7906 | /* | |
7907 | * PML buffer already flushed at beginning of VMEXIT. Nothing to do | |
7908 | * here.., and there's no userspace involvement needed for PML. | |
7909 | */ | |
7910 | return 1; | |
7911 | } | |
7912 | ||
64672c95 YJ |
7913 | static int handle_preemption_timer(struct kvm_vcpu *vcpu) |
7914 | { | |
7915 | kvm_lapic_expired_hv_timer(vcpu); | |
7916 | return 1; | |
7917 | } | |
7918 | ||
6aa8b732 AK |
7919 | /* |
7920 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
7921 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
7922 | * to be done to userspace and return 0. | |
7923 | */ | |
772e0318 | 7924 | static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { |
6aa8b732 AK |
7925 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, |
7926 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 7927 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
f08864b4 | 7928 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, |
6aa8b732 | 7929 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
7930 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
7931 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
7932 | [EXIT_REASON_CPUID] = handle_cpuid, | |
7933 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
7934 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
7935 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
7936 | [EXIT_REASON_HLT] = handle_halt, | |
ec25d5e6 | 7937 | [EXIT_REASON_INVD] = handle_invd, |
a7052897 | 7938 | [EXIT_REASON_INVLPG] = handle_invlpg, |
fee84b07 | 7939 | [EXIT_REASON_RDPMC] = handle_rdpmc, |
c21415e8 | 7940 | [EXIT_REASON_VMCALL] = handle_vmcall, |
27d6c865 | 7941 | [EXIT_REASON_VMCLEAR] = handle_vmclear, |
cd232ad0 | 7942 | [EXIT_REASON_VMLAUNCH] = handle_vmlaunch, |
63846663 | 7943 | [EXIT_REASON_VMPTRLD] = handle_vmptrld, |
6a4d7550 | 7944 | [EXIT_REASON_VMPTRST] = handle_vmptrst, |
49f705c5 | 7945 | [EXIT_REASON_VMREAD] = handle_vmread, |
cd232ad0 | 7946 | [EXIT_REASON_VMRESUME] = handle_vmresume, |
49f705c5 | 7947 | [EXIT_REASON_VMWRITE] = handle_vmwrite, |
ec378aee NHE |
7948 | [EXIT_REASON_VMOFF] = handle_vmoff, |
7949 | [EXIT_REASON_VMON] = handle_vmon, | |
f78e0e2e SY |
7950 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
7951 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
83d4c286 | 7952 | [EXIT_REASON_APIC_WRITE] = handle_apic_write, |
c7c9c56c | 7953 | [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, |
e5edaa01 | 7954 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
2acf923e | 7955 | [EXIT_REASON_XSETBV] = handle_xsetbv, |
37817f29 | 7956 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
a0861c02 | 7957 | [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, |
68f89400 MT |
7958 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
7959 | [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, | |
4b8d54f9 | 7960 | [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, |
87c00572 | 7961 | [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, |
5f3d45e7 | 7962 | [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, |
87c00572 | 7963 | [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, |
bfd0a56b | 7964 | [EXIT_REASON_INVEPT] = handle_invept, |
a642fc30 | 7965 | [EXIT_REASON_INVVPID] = handle_invvpid, |
f53cd63c WL |
7966 | [EXIT_REASON_XSAVES] = handle_xsaves, |
7967 | [EXIT_REASON_XRSTORS] = handle_xrstors, | |
843e4330 | 7968 | [EXIT_REASON_PML_FULL] = handle_pml_full, |
64672c95 | 7969 | [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, |
6aa8b732 AK |
7970 | }; |
7971 | ||
7972 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 7973 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 | 7974 | |
908a7bdd JK |
7975 | static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu, |
7976 | struct vmcs12 *vmcs12) | |
7977 | { | |
7978 | unsigned long exit_qualification; | |
7979 | gpa_t bitmap, last_bitmap; | |
7980 | unsigned int port; | |
7981 | int size; | |
7982 | u8 b; | |
7983 | ||
908a7bdd | 7984 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) |
2f0a6397 | 7985 | return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING); |
908a7bdd JK |
7986 | |
7987 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7988 | ||
7989 | port = exit_qualification >> 16; | |
7990 | size = (exit_qualification & 7) + 1; | |
7991 | ||
7992 | last_bitmap = (gpa_t)-1; | |
7993 | b = -1; | |
7994 | ||
7995 | while (size > 0) { | |
7996 | if (port < 0x8000) | |
7997 | bitmap = vmcs12->io_bitmap_a; | |
7998 | else if (port < 0x10000) | |
7999 | bitmap = vmcs12->io_bitmap_b; | |
8000 | else | |
1d804d07 | 8001 | return true; |
908a7bdd JK |
8002 | bitmap += (port & 0x7fff) / 8; |
8003 | ||
8004 | if (last_bitmap != bitmap) | |
54bf36aa | 8005 | if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1)) |
1d804d07 | 8006 | return true; |
908a7bdd | 8007 | if (b & (1 << (port & 7))) |
1d804d07 | 8008 | return true; |
908a7bdd JK |
8009 | |
8010 | port++; | |
8011 | size--; | |
8012 | last_bitmap = bitmap; | |
8013 | } | |
8014 | ||
1d804d07 | 8015 | return false; |
908a7bdd JK |
8016 | } |
8017 | ||
644d711a NHE |
8018 | /* |
8019 | * Return 1 if we should exit from L2 to L1 to handle an MSR access access, | |
8020 | * rather than handle it ourselves in L0. I.e., check whether L1 expressed | |
8021 | * disinterest in the current event (read or write a specific MSR) by using an | |
8022 | * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps. | |
8023 | */ | |
8024 | static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu, | |
8025 | struct vmcs12 *vmcs12, u32 exit_reason) | |
8026 | { | |
8027 | u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX]; | |
8028 | gpa_t bitmap; | |
8029 | ||
cbd29cb6 | 8030 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) |
1d804d07 | 8031 | return true; |
644d711a NHE |
8032 | |
8033 | /* | |
8034 | * The MSR_BITMAP page is divided into four 1024-byte bitmaps, | |
8035 | * for the four combinations of read/write and low/high MSR numbers. | |
8036 | * First we need to figure out which of the four to use: | |
8037 | */ | |
8038 | bitmap = vmcs12->msr_bitmap; | |
8039 | if (exit_reason == EXIT_REASON_MSR_WRITE) | |
8040 | bitmap += 2048; | |
8041 | if (msr_index >= 0xc0000000) { | |
8042 | msr_index -= 0xc0000000; | |
8043 | bitmap += 1024; | |
8044 | } | |
8045 | ||
8046 | /* Then read the msr_index'th bit from this bitmap: */ | |
8047 | if (msr_index < 1024*8) { | |
8048 | unsigned char b; | |
54bf36aa | 8049 | if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1)) |
1d804d07 | 8050 | return true; |
644d711a NHE |
8051 | return 1 & (b >> (msr_index & 7)); |
8052 | } else | |
1d804d07 | 8053 | return true; /* let L1 handle the wrong parameter */ |
644d711a NHE |
8054 | } |
8055 | ||
8056 | /* | |
8057 | * Return 1 if we should exit from L2 to L1 to handle a CR access exit, | |
8058 | * rather than handle it ourselves in L0. I.e., check if L1 wanted to | |
8059 | * intercept (via guest_host_mask etc.) the current event. | |
8060 | */ | |
8061 | static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu, | |
8062 | struct vmcs12 *vmcs12) | |
8063 | { | |
8064 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
8065 | int cr = exit_qualification & 15; | |
8066 | int reg = (exit_qualification >> 8) & 15; | |
1e32c079 | 8067 | unsigned long val = kvm_register_readl(vcpu, reg); |
644d711a NHE |
8068 | |
8069 | switch ((exit_qualification >> 4) & 3) { | |
8070 | case 0: /* mov to cr */ | |
8071 | switch (cr) { | |
8072 | case 0: | |
8073 | if (vmcs12->cr0_guest_host_mask & | |
8074 | (val ^ vmcs12->cr0_read_shadow)) | |
1d804d07 | 8075 | return true; |
644d711a NHE |
8076 | break; |
8077 | case 3: | |
8078 | if ((vmcs12->cr3_target_count >= 1 && | |
8079 | vmcs12->cr3_target_value0 == val) || | |
8080 | (vmcs12->cr3_target_count >= 2 && | |
8081 | vmcs12->cr3_target_value1 == val) || | |
8082 | (vmcs12->cr3_target_count >= 3 && | |
8083 | vmcs12->cr3_target_value2 == val) || | |
8084 | (vmcs12->cr3_target_count >= 4 && | |
8085 | vmcs12->cr3_target_value3 == val)) | |
1d804d07 | 8086 | return false; |
644d711a | 8087 | if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING)) |
1d804d07 | 8088 | return true; |
644d711a NHE |
8089 | break; |
8090 | case 4: | |
8091 | if (vmcs12->cr4_guest_host_mask & | |
8092 | (vmcs12->cr4_read_shadow ^ val)) | |
1d804d07 | 8093 | return true; |
644d711a NHE |
8094 | break; |
8095 | case 8: | |
8096 | if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING)) | |
1d804d07 | 8097 | return true; |
644d711a NHE |
8098 | break; |
8099 | } | |
8100 | break; | |
8101 | case 2: /* clts */ | |
8102 | if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) && | |
8103 | (vmcs12->cr0_read_shadow & X86_CR0_TS)) | |
1d804d07 | 8104 | return true; |
644d711a NHE |
8105 | break; |
8106 | case 1: /* mov from cr */ | |
8107 | switch (cr) { | |
8108 | case 3: | |
8109 | if (vmcs12->cpu_based_vm_exec_control & | |
8110 | CPU_BASED_CR3_STORE_EXITING) | |
1d804d07 | 8111 | return true; |
644d711a NHE |
8112 | break; |
8113 | case 8: | |
8114 | if (vmcs12->cpu_based_vm_exec_control & | |
8115 | CPU_BASED_CR8_STORE_EXITING) | |
1d804d07 | 8116 | return true; |
644d711a NHE |
8117 | break; |
8118 | } | |
8119 | break; | |
8120 | case 3: /* lmsw */ | |
8121 | /* | |
8122 | * lmsw can change bits 1..3 of cr0, and only set bit 0 of | |
8123 | * cr0. Other attempted changes are ignored, with no exit. | |
8124 | */ | |
8125 | if (vmcs12->cr0_guest_host_mask & 0xe & | |
8126 | (val ^ vmcs12->cr0_read_shadow)) | |
1d804d07 | 8127 | return true; |
644d711a NHE |
8128 | if ((vmcs12->cr0_guest_host_mask & 0x1) && |
8129 | !(vmcs12->cr0_read_shadow & 0x1) && | |
8130 | (val & 0x1)) | |
1d804d07 | 8131 | return true; |
644d711a NHE |
8132 | break; |
8133 | } | |
1d804d07 | 8134 | return false; |
644d711a NHE |
8135 | } |
8136 | ||
8137 | /* | |
8138 | * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we | |
8139 | * should handle it ourselves in L0 (and then continue L2). Only call this | |
8140 | * when in is_guest_mode (L2). | |
8141 | */ | |
8142 | static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu) | |
8143 | { | |
644d711a NHE |
8144 | u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
8145 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8146 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
957c897e | 8147 | u32 exit_reason = vmx->exit_reason; |
644d711a | 8148 | |
542060ea JK |
8149 | trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason, |
8150 | vmcs_readl(EXIT_QUALIFICATION), | |
8151 | vmx->idt_vectoring_info, | |
8152 | intr_info, | |
8153 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
8154 | KVM_ISA_VMX); | |
8155 | ||
644d711a | 8156 | if (vmx->nested.nested_run_pending) |
1d804d07 | 8157 | return false; |
644d711a NHE |
8158 | |
8159 | if (unlikely(vmx->fail)) { | |
bd80158a JK |
8160 | pr_info_ratelimited("%s failed vm entry %x\n", __func__, |
8161 | vmcs_read32(VM_INSTRUCTION_ERROR)); | |
1d804d07 | 8162 | return true; |
644d711a NHE |
8163 | } |
8164 | ||
8165 | switch (exit_reason) { | |
8166 | case EXIT_REASON_EXCEPTION_NMI: | |
8167 | if (!is_exception(intr_info)) | |
1d804d07 | 8168 | return false; |
644d711a NHE |
8169 | else if (is_page_fault(intr_info)) |
8170 | return enable_ept; | |
e504c909 | 8171 | else if (is_no_device(intr_info) && |
ccf9844e | 8172 | !(vmcs12->guest_cr0 & X86_CR0_TS)) |
1d804d07 | 8173 | return false; |
6f05485d JK |
8174 | else if (is_debug(intr_info) && |
8175 | vcpu->guest_debug & | |
8176 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
8177 | return false; | |
8178 | else if (is_breakpoint(intr_info) && | |
8179 | vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) | |
8180 | return false; | |
644d711a NHE |
8181 | return vmcs12->exception_bitmap & |
8182 | (1u << (intr_info & INTR_INFO_VECTOR_MASK)); | |
8183 | case EXIT_REASON_EXTERNAL_INTERRUPT: | |
1d804d07 | 8184 | return false; |
644d711a | 8185 | case EXIT_REASON_TRIPLE_FAULT: |
1d804d07 | 8186 | return true; |
644d711a | 8187 | case EXIT_REASON_PENDING_INTERRUPT: |
3b656cf7 | 8188 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING); |
644d711a | 8189 | case EXIT_REASON_NMI_WINDOW: |
3b656cf7 | 8190 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING); |
644d711a | 8191 | case EXIT_REASON_TASK_SWITCH: |
1d804d07 | 8192 | return true; |
644d711a | 8193 | case EXIT_REASON_CPUID: |
bc613494 | 8194 | if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa) |
1d804d07 JP |
8195 | return false; |
8196 | return true; | |
644d711a NHE |
8197 | case EXIT_REASON_HLT: |
8198 | return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING); | |
8199 | case EXIT_REASON_INVD: | |
1d804d07 | 8200 | return true; |
644d711a NHE |
8201 | case EXIT_REASON_INVLPG: |
8202 | return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); | |
8203 | case EXIT_REASON_RDPMC: | |
8204 | return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING); | |
b3a2a907 | 8205 | case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP: |
644d711a NHE |
8206 | return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING); |
8207 | case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR: | |
8208 | case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD: | |
8209 | case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD: | |
8210 | case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE: | |
8211 | case EXIT_REASON_VMOFF: case EXIT_REASON_VMON: | |
a642fc30 | 8212 | case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID: |
644d711a NHE |
8213 | /* |
8214 | * VMX instructions trap unconditionally. This allows L1 to | |
8215 | * emulate them for its L2 guest, i.e., allows 3-level nesting! | |
8216 | */ | |
1d804d07 | 8217 | return true; |
644d711a NHE |
8218 | case EXIT_REASON_CR_ACCESS: |
8219 | return nested_vmx_exit_handled_cr(vcpu, vmcs12); | |
8220 | case EXIT_REASON_DR_ACCESS: | |
8221 | return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING); | |
8222 | case EXIT_REASON_IO_INSTRUCTION: | |
908a7bdd | 8223 | return nested_vmx_exit_handled_io(vcpu, vmcs12); |
1b07304c PB |
8224 | case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR: |
8225 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC); | |
644d711a NHE |
8226 | case EXIT_REASON_MSR_READ: |
8227 | case EXIT_REASON_MSR_WRITE: | |
8228 | return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason); | |
8229 | case EXIT_REASON_INVALID_STATE: | |
1d804d07 | 8230 | return true; |
644d711a NHE |
8231 | case EXIT_REASON_MWAIT_INSTRUCTION: |
8232 | return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING); | |
5f3d45e7 MD |
8233 | case EXIT_REASON_MONITOR_TRAP_FLAG: |
8234 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG); | |
644d711a NHE |
8235 | case EXIT_REASON_MONITOR_INSTRUCTION: |
8236 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING); | |
8237 | case EXIT_REASON_PAUSE_INSTRUCTION: | |
8238 | return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) || | |
8239 | nested_cpu_has2(vmcs12, | |
8240 | SECONDARY_EXEC_PAUSE_LOOP_EXITING); | |
8241 | case EXIT_REASON_MCE_DURING_VMENTRY: | |
1d804d07 | 8242 | return false; |
644d711a | 8243 | case EXIT_REASON_TPR_BELOW_THRESHOLD: |
a7c0b07d | 8244 | return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW); |
644d711a NHE |
8245 | case EXIT_REASON_APIC_ACCESS: |
8246 | return nested_cpu_has2(vmcs12, | |
8247 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
82f0dd4b | 8248 | case EXIT_REASON_APIC_WRITE: |
608406e2 WV |
8249 | case EXIT_REASON_EOI_INDUCED: |
8250 | /* apic_write and eoi_induced should exit unconditionally. */ | |
1d804d07 | 8251 | return true; |
644d711a | 8252 | case EXIT_REASON_EPT_VIOLATION: |
2b1be677 NHE |
8253 | /* |
8254 | * L0 always deals with the EPT violation. If nested EPT is | |
8255 | * used, and the nested mmu code discovers that the address is | |
8256 | * missing in the guest EPT table (EPT12), the EPT violation | |
8257 | * will be injected with nested_ept_inject_page_fault() | |
8258 | */ | |
1d804d07 | 8259 | return false; |
644d711a | 8260 | case EXIT_REASON_EPT_MISCONFIG: |
2b1be677 NHE |
8261 | /* |
8262 | * L2 never uses directly L1's EPT, but rather L0's own EPT | |
8263 | * table (shadow on EPT) or a merged EPT table that L0 built | |
8264 | * (EPT on EPT). So any problems with the structure of the | |
8265 | * table is L0's fault. | |
8266 | */ | |
1d804d07 | 8267 | return false; |
644d711a NHE |
8268 | case EXIT_REASON_WBINVD: |
8269 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING); | |
8270 | case EXIT_REASON_XSETBV: | |
1d804d07 | 8271 | return true; |
81dc01f7 WL |
8272 | case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS: |
8273 | /* | |
8274 | * This should never happen, since it is not possible to | |
8275 | * set XSS to a non-zero value---neither in L1 nor in L2. | |
8276 | * If if it were, XSS would have to be checked against | |
8277 | * the XSS exit bitmap in vmcs12. | |
8278 | */ | |
8279 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES); | |
55123e3c WL |
8280 | case EXIT_REASON_PREEMPTION_TIMER: |
8281 | return false; | |
644d711a | 8282 | default: |
1d804d07 | 8283 | return true; |
644d711a NHE |
8284 | } |
8285 | } | |
8286 | ||
586f9607 AK |
8287 | static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
8288 | { | |
8289 | *info1 = vmcs_readl(EXIT_QUALIFICATION); | |
8290 | *info2 = vmcs_read32(VM_EXIT_INTR_INFO); | |
8291 | } | |
8292 | ||
a3eaa864 | 8293 | static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) |
843e4330 | 8294 | { |
a3eaa864 KH |
8295 | if (vmx->pml_pg) { |
8296 | __free_page(vmx->pml_pg); | |
8297 | vmx->pml_pg = NULL; | |
8298 | } | |
843e4330 KH |
8299 | } |
8300 | ||
54bf36aa | 8301 | static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) |
843e4330 | 8302 | { |
54bf36aa | 8303 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
843e4330 KH |
8304 | u64 *pml_buf; |
8305 | u16 pml_idx; | |
8306 | ||
8307 | pml_idx = vmcs_read16(GUEST_PML_INDEX); | |
8308 | ||
8309 | /* Do nothing if PML buffer is empty */ | |
8310 | if (pml_idx == (PML_ENTITY_NUM - 1)) | |
8311 | return; | |
8312 | ||
8313 | /* PML index always points to next available PML buffer entity */ | |
8314 | if (pml_idx >= PML_ENTITY_NUM) | |
8315 | pml_idx = 0; | |
8316 | else | |
8317 | pml_idx++; | |
8318 | ||
8319 | pml_buf = page_address(vmx->pml_pg); | |
8320 | for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { | |
8321 | u64 gpa; | |
8322 | ||
8323 | gpa = pml_buf[pml_idx]; | |
8324 | WARN_ON(gpa & (PAGE_SIZE - 1)); | |
54bf36aa | 8325 | kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); |
843e4330 KH |
8326 | } |
8327 | ||
8328 | /* reset PML index */ | |
8329 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
8330 | } | |
8331 | ||
8332 | /* | |
8333 | * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. | |
8334 | * Called before reporting dirty_bitmap to userspace. | |
8335 | */ | |
8336 | static void kvm_flush_pml_buffers(struct kvm *kvm) | |
8337 | { | |
8338 | int i; | |
8339 | struct kvm_vcpu *vcpu; | |
8340 | /* | |
8341 | * We only need to kick vcpu out of guest mode here, as PML buffer | |
8342 | * is flushed at beginning of all VMEXITs, and it's obvious that only | |
8343 | * vcpus running in guest are possible to have unflushed GPAs in PML | |
8344 | * buffer. | |
8345 | */ | |
8346 | kvm_for_each_vcpu(i, vcpu, kvm) | |
8347 | kvm_vcpu_kick(vcpu); | |
8348 | } | |
8349 | ||
4eb64dce PB |
8350 | static void vmx_dump_sel(char *name, uint32_t sel) |
8351 | { | |
8352 | pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", | |
8353 | name, vmcs_read32(sel), | |
8354 | vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), | |
8355 | vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), | |
8356 | vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); | |
8357 | } | |
8358 | ||
8359 | static void vmx_dump_dtsel(char *name, uint32_t limit) | |
8360 | { | |
8361 | pr_err("%s limit=0x%08x, base=0x%016lx\n", | |
8362 | name, vmcs_read32(limit), | |
8363 | vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); | |
8364 | } | |
8365 | ||
8366 | static void dump_vmcs(void) | |
8367 | { | |
8368 | u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); | |
8369 | u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); | |
8370 | u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
8371 | u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); | |
8372 | u32 secondary_exec_control = 0; | |
8373 | unsigned long cr4 = vmcs_readl(GUEST_CR4); | |
f3531054 | 8374 | u64 efer = vmcs_read64(GUEST_IA32_EFER); |
4eb64dce PB |
8375 | int i, n; |
8376 | ||
8377 | if (cpu_has_secondary_exec_ctrls()) | |
8378 | secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
8379 | ||
8380 | pr_err("*** Guest State ***\n"); | |
8381 | pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
8382 | vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), | |
8383 | vmcs_readl(CR0_GUEST_HOST_MASK)); | |
8384 | pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
8385 | cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); | |
8386 | pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); | |
8387 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && | |
8388 | (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) | |
8389 | { | |
845c5b40 PB |
8390 | pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", |
8391 | vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); | |
8392 | pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", | |
8393 | vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); | |
4eb64dce PB |
8394 | } |
8395 | pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", | |
8396 | vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); | |
8397 | pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", | |
8398 | vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); | |
8399 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
8400 | vmcs_readl(GUEST_SYSENTER_ESP), | |
8401 | vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); | |
8402 | vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); | |
8403 | vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); | |
8404 | vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); | |
8405 | vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); | |
8406 | vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); | |
8407 | vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); | |
8408 | vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); | |
8409 | vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); | |
8410 | vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); | |
8411 | vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); | |
8412 | if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || | |
8413 | (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) | |
845c5b40 PB |
8414 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", |
8415 | efer, vmcs_read64(GUEST_IA32_PAT)); | |
8416 | pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", | |
8417 | vmcs_read64(GUEST_IA32_DEBUGCTL), | |
4eb64dce PB |
8418 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); |
8419 | if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
845c5b40 PB |
8420 | pr_err("PerfGlobCtl = 0x%016llx\n", |
8421 | vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); | |
4eb64dce | 8422 | if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) |
845c5b40 | 8423 | pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); |
4eb64dce PB |
8424 | pr_err("Interruptibility = %08x ActivityState = %08x\n", |
8425 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), | |
8426 | vmcs_read32(GUEST_ACTIVITY_STATE)); | |
8427 | if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) | |
8428 | pr_err("InterruptStatus = %04x\n", | |
8429 | vmcs_read16(GUEST_INTR_STATUS)); | |
8430 | ||
8431 | pr_err("*** Host State ***\n"); | |
8432 | pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", | |
8433 | vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); | |
8434 | pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", | |
8435 | vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), | |
8436 | vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), | |
8437 | vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), | |
8438 | vmcs_read16(HOST_TR_SELECTOR)); | |
8439 | pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", | |
8440 | vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), | |
8441 | vmcs_readl(HOST_TR_BASE)); | |
8442 | pr_err("GDTBase=%016lx IDTBase=%016lx\n", | |
8443 | vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); | |
8444 | pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", | |
8445 | vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), | |
8446 | vmcs_readl(HOST_CR4)); | |
8447 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
8448 | vmcs_readl(HOST_IA32_SYSENTER_ESP), | |
8449 | vmcs_read32(HOST_IA32_SYSENTER_CS), | |
8450 | vmcs_readl(HOST_IA32_SYSENTER_EIP)); | |
8451 | if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) | |
845c5b40 PB |
8452 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", |
8453 | vmcs_read64(HOST_IA32_EFER), | |
8454 | vmcs_read64(HOST_IA32_PAT)); | |
4eb64dce | 8455 | if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) |
845c5b40 PB |
8456 | pr_err("PerfGlobCtl = 0x%016llx\n", |
8457 | vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); | |
4eb64dce PB |
8458 | |
8459 | pr_err("*** Control State ***\n"); | |
8460 | pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", | |
8461 | pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); | |
8462 | pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); | |
8463 | pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", | |
8464 | vmcs_read32(EXCEPTION_BITMAP), | |
8465 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), | |
8466 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); | |
8467 | pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", | |
8468 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), | |
8469 | vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), | |
8470 | vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); | |
8471 | pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", | |
8472 | vmcs_read32(VM_EXIT_INTR_INFO), | |
8473 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
8474 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); | |
8475 | pr_err(" reason=%08x qualification=%016lx\n", | |
8476 | vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); | |
8477 | pr_err("IDTVectoring: info=%08x errcode=%08x\n", | |
8478 | vmcs_read32(IDT_VECTORING_INFO_FIELD), | |
8479 | vmcs_read32(IDT_VECTORING_ERROR_CODE)); | |
845c5b40 | 8480 | pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); |
8cfe9866 | 8481 | if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) |
845c5b40 PB |
8482 | pr_err("TSC Multiplier = 0x%016llx\n", |
8483 | vmcs_read64(TSC_MULTIPLIER)); | |
4eb64dce PB |
8484 | if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) |
8485 | pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); | |
8486 | if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) | |
8487 | pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); | |
8488 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) | |
845c5b40 | 8489 | pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); |
4eb64dce PB |
8490 | n = vmcs_read32(CR3_TARGET_COUNT); |
8491 | for (i = 0; i + 1 < n; i += 4) | |
8492 | pr_err("CR3 target%u=%016lx target%u=%016lx\n", | |
8493 | i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), | |
8494 | i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); | |
8495 | if (i < n) | |
8496 | pr_err("CR3 target%u=%016lx\n", | |
8497 | i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); | |
8498 | if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) | |
8499 | pr_err("PLE Gap=%08x Window=%08x\n", | |
8500 | vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); | |
8501 | if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) | |
8502 | pr_err("Virtual processor ID = 0x%04x\n", | |
8503 | vmcs_read16(VIRTUAL_PROCESSOR_ID)); | |
8504 | } | |
8505 | ||
6aa8b732 AK |
8506 | /* |
8507 | * The guest has exited. See if we can fix it or if we need userspace | |
8508 | * assistance. | |
8509 | */ | |
851ba692 | 8510 | static int vmx_handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 8511 | { |
29bd8a78 | 8512 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
a0861c02 | 8513 | u32 exit_reason = vmx->exit_reason; |
1155f76a | 8514 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 8515 | |
8b89fe1f PB |
8516 | trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); |
8517 | ||
843e4330 KH |
8518 | /* |
8519 | * Flush logged GPAs PML buffer, this will make dirty_bitmap more | |
8520 | * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before | |
8521 | * querying dirty_bitmap, we only need to kick all vcpus out of guest | |
8522 | * mode as if vcpus is in root mode, the PML buffer must has been | |
8523 | * flushed already. | |
8524 | */ | |
8525 | if (enable_pml) | |
54bf36aa | 8526 | vmx_flush_pml_buffer(vcpu); |
843e4330 | 8527 | |
80ced186 | 8528 | /* If guest state is invalid, start emulating */ |
14168786 | 8529 | if (vmx->emulation_required) |
80ced186 | 8530 | return handle_invalid_guest_state(vcpu); |
1d5a4d9b | 8531 | |
644d711a | 8532 | if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) { |
533558bc JK |
8533 | nested_vmx_vmexit(vcpu, exit_reason, |
8534 | vmcs_read32(VM_EXIT_INTR_INFO), | |
8535 | vmcs_readl(EXIT_QUALIFICATION)); | |
644d711a NHE |
8536 | return 1; |
8537 | } | |
8538 | ||
5120702e | 8539 | if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { |
4eb64dce | 8540 | dump_vmcs(); |
5120702e MG |
8541 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
8542 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
8543 | = exit_reason; | |
8544 | return 0; | |
8545 | } | |
8546 | ||
29bd8a78 | 8547 | if (unlikely(vmx->fail)) { |
851ba692 AK |
8548 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
8549 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
29bd8a78 AK |
8550 | = vmcs_read32(VM_INSTRUCTION_ERROR); |
8551 | return 0; | |
8552 | } | |
6aa8b732 | 8553 | |
b9bf6882 XG |
8554 | /* |
8555 | * Note: | |
8556 | * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by | |
8557 | * delivery event since it indicates guest is accessing MMIO. | |
8558 | * The vm-exit can be triggered again after return to guest that | |
8559 | * will cause infinite loop. | |
8560 | */ | |
d77c26fc | 8561 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c | 8562 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
60637aac | 8563 | exit_reason != EXIT_REASON_EPT_VIOLATION && |
b244c9fc | 8564 | exit_reason != EXIT_REASON_PML_FULL && |
b9bf6882 XG |
8565 | exit_reason != EXIT_REASON_TASK_SWITCH)) { |
8566 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
8567 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; | |
8568 | vcpu->run->internal.ndata = 2; | |
8569 | vcpu->run->internal.data[0] = vectoring_info; | |
8570 | vcpu->run->internal.data[1] = exit_reason; | |
8571 | return 0; | |
8572 | } | |
3b86cd99 | 8573 | |
644d711a NHE |
8574 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked && |
8575 | !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis( | |
f5c4368f | 8576 | get_vmcs12(vcpu))))) { |
c4282df9 | 8577 | if (vmx_interrupt_allowed(vcpu)) { |
3b86cd99 | 8578 | vmx->soft_vnmi_blocked = 0; |
3b86cd99 | 8579 | } else if (vmx->vnmi_blocked_time > 1000000000LL && |
4531220b | 8580 | vcpu->arch.nmi_pending) { |
3b86cd99 JK |
8581 | /* |
8582 | * This CPU don't support us in finding the end of an | |
8583 | * NMI-blocked window if the guest runs with IRQs | |
8584 | * disabled. So we pull the trigger after 1 s of | |
8585 | * futile waiting, but inform the user about this. | |
8586 | */ | |
8587 | printk(KERN_WARNING "%s: Breaking out of NMI-blocked " | |
8588 | "state on VCPU %d after 1 s timeout\n", | |
8589 | __func__, vcpu->vcpu_id); | |
8590 | vmx->soft_vnmi_blocked = 0; | |
3b86cd99 | 8591 | } |
3b86cd99 JK |
8592 | } |
8593 | ||
6aa8b732 AK |
8594 | if (exit_reason < kvm_vmx_max_exit_handlers |
8595 | && kvm_vmx_exit_handlers[exit_reason]) | |
851ba692 | 8596 | return kvm_vmx_exit_handlers[exit_reason](vcpu); |
6aa8b732 | 8597 | else { |
2bc19dc3 MT |
8598 | WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason); |
8599 | kvm_queue_exception(vcpu, UD_VECTOR); | |
8600 | return 1; | |
6aa8b732 | 8601 | } |
6aa8b732 AK |
8602 | } |
8603 | ||
95ba8273 | 8604 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
6e5d865c | 8605 | { |
a7c0b07d WL |
8606 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
8607 | ||
8608 | if (is_guest_mode(vcpu) && | |
8609 | nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
8610 | return; | |
8611 | ||
95ba8273 | 8612 | if (irr == -1 || tpr < irr) { |
6e5d865c YS |
8613 | vmcs_write32(TPR_THRESHOLD, 0); |
8614 | return; | |
8615 | } | |
8616 | ||
95ba8273 | 8617 | vmcs_write32(TPR_THRESHOLD, irr); |
6e5d865c YS |
8618 | } |
8619 | ||
8d14695f YZ |
8620 | static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) |
8621 | { | |
8622 | u32 sec_exec_control; | |
8623 | ||
dccbfcf5 RK |
8624 | /* Postpone execution until vmcs01 is the current VMCS. */ |
8625 | if (is_guest_mode(vcpu)) { | |
8626 | to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true; | |
8627 | return; | |
8628 | } | |
8629 | ||
f6e90f9e | 8630 | if (!cpu_has_vmx_virtualize_x2apic_mode()) |
8d14695f YZ |
8631 | return; |
8632 | ||
35754c98 | 8633 | if (!cpu_need_tpr_shadow(vcpu)) |
8d14695f YZ |
8634 | return; |
8635 | ||
8636 | sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
8637 | ||
8638 | if (set) { | |
8639 | sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
8640 | sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
8641 | } else { | |
8642 | sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
8643 | sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
8644 | } | |
8645 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control); | |
8646 | ||
8647 | vmx_set_msr_bitmap(vcpu); | |
8648 | } | |
8649 | ||
38b99173 TC |
8650 | static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) |
8651 | { | |
8652 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8653 | ||
8654 | /* | |
8655 | * Currently we do not handle the nested case where L2 has an | |
8656 | * APIC access page of its own; that page is still pinned. | |
8657 | * Hence, we skip the case where the VCPU is in guest mode _and_ | |
8658 | * L1 prepared an APIC access page for L2. | |
8659 | * | |
8660 | * For the case where L1 and L2 share the same APIC access page | |
8661 | * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear | |
8662 | * in the vmcs12), this function will only update either the vmcs01 | |
8663 | * or the vmcs02. If the former, the vmcs02 will be updated by | |
8664 | * prepare_vmcs02. If the latter, the vmcs01 will be updated in | |
8665 | * the next L2->L1 exit. | |
8666 | */ | |
8667 | if (!is_guest_mode(vcpu) || | |
4f2777bc | 8668 | !nested_cpu_has2(get_vmcs12(&vmx->vcpu), |
38b99173 TC |
8669 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) |
8670 | vmcs_write64(APIC_ACCESS_ADDR, hpa); | |
8671 | } | |
8672 | ||
67c9dddc | 8673 | static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) |
c7c9c56c YZ |
8674 | { |
8675 | u16 status; | |
8676 | u8 old; | |
8677 | ||
67c9dddc PB |
8678 | if (max_isr == -1) |
8679 | max_isr = 0; | |
c7c9c56c YZ |
8680 | |
8681 | status = vmcs_read16(GUEST_INTR_STATUS); | |
8682 | old = status >> 8; | |
67c9dddc | 8683 | if (max_isr != old) { |
c7c9c56c | 8684 | status &= 0xff; |
67c9dddc | 8685 | status |= max_isr << 8; |
c7c9c56c YZ |
8686 | vmcs_write16(GUEST_INTR_STATUS, status); |
8687 | } | |
8688 | } | |
8689 | ||
8690 | static void vmx_set_rvi(int vector) | |
8691 | { | |
8692 | u16 status; | |
8693 | u8 old; | |
8694 | ||
4114c27d WW |
8695 | if (vector == -1) |
8696 | vector = 0; | |
8697 | ||
c7c9c56c YZ |
8698 | status = vmcs_read16(GUEST_INTR_STATUS); |
8699 | old = (u8)status & 0xff; | |
8700 | if ((u8)vector != old) { | |
8701 | status &= ~0xff; | |
8702 | status |= (u8)vector; | |
8703 | vmcs_write16(GUEST_INTR_STATUS, status); | |
8704 | } | |
8705 | } | |
8706 | ||
8707 | static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) | |
8708 | { | |
4114c27d WW |
8709 | if (!is_guest_mode(vcpu)) { |
8710 | vmx_set_rvi(max_irr); | |
8711 | return; | |
8712 | } | |
8713 | ||
c7c9c56c YZ |
8714 | if (max_irr == -1) |
8715 | return; | |
8716 | ||
963fee16 | 8717 | /* |
4114c27d WW |
8718 | * In guest mode. If a vmexit is needed, vmx_check_nested_events |
8719 | * handles it. | |
963fee16 | 8720 | */ |
4114c27d | 8721 | if (nested_exit_on_intr(vcpu)) |
963fee16 WL |
8722 | return; |
8723 | ||
963fee16 | 8724 | /* |
4114c27d | 8725 | * Else, fall back to pre-APICv interrupt injection since L2 |
963fee16 WL |
8726 | * is run without virtual interrupt delivery. |
8727 | */ | |
8728 | if (!kvm_event_needs_reinjection(vcpu) && | |
8729 | vmx_interrupt_allowed(vcpu)) { | |
8730 | kvm_queue_interrupt(vcpu, max_irr, false); | |
8731 | vmx_inject_irq(vcpu); | |
8732 | } | |
c7c9c56c YZ |
8733 | } |
8734 | ||
6308630b | 8735 | static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
c7c9c56c | 8736 | { |
d62caabb | 8737 | if (!kvm_vcpu_apicv_active(vcpu)) |
3d81bc7e YZ |
8738 | return; |
8739 | ||
c7c9c56c YZ |
8740 | vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); |
8741 | vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); | |
8742 | vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); | |
8743 | vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); | |
8744 | } | |
8745 | ||
51aa01d1 | 8746 | static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx) |
cf393f75 | 8747 | { |
00eba012 AK |
8748 | u32 exit_intr_info; |
8749 | ||
8750 | if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY | |
8751 | || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)) | |
8752 | return; | |
8753 | ||
c5ca8e57 | 8754 | vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
00eba012 | 8755 | exit_intr_info = vmx->exit_intr_info; |
a0861c02 AK |
8756 | |
8757 | /* Handle machine checks before interrupts are enabled */ | |
00eba012 | 8758 | if (is_machine_check(exit_intr_info)) |
a0861c02 AK |
8759 | kvm_machine_check(); |
8760 | ||
20f65983 | 8761 | /* We need to handle NMIs before interrupts are enabled */ |
00eba012 | 8762 | if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR && |
ff9d07a0 ZY |
8763 | (exit_intr_info & INTR_INFO_VALID_MASK)) { |
8764 | kvm_before_handle_nmi(&vmx->vcpu); | |
20f65983 | 8765 | asm("int $2"); |
ff9d07a0 ZY |
8766 | kvm_after_handle_nmi(&vmx->vcpu); |
8767 | } | |
51aa01d1 | 8768 | } |
20f65983 | 8769 | |
a547c6db YZ |
8770 | static void vmx_handle_external_intr(struct kvm_vcpu *vcpu) |
8771 | { | |
8772 | u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
3f62de5f | 8773 | register void *__sp asm(_ASM_SP); |
a547c6db | 8774 | |
a547c6db YZ |
8775 | if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK)) |
8776 | == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) { | |
8777 | unsigned int vector; | |
8778 | unsigned long entry; | |
8779 | gate_desc *desc; | |
8780 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8781 | #ifdef CONFIG_X86_64 | |
8782 | unsigned long tmp; | |
8783 | #endif | |
8784 | ||
8785 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
8786 | desc = (gate_desc *)vmx->host_idt_base + vector; | |
8787 | entry = gate_offset(*desc); | |
8788 | asm volatile( | |
8789 | #ifdef CONFIG_X86_64 | |
8790 | "mov %%" _ASM_SP ", %[sp]\n\t" | |
8791 | "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" | |
8792 | "push $%c[ss]\n\t" | |
8793 | "push %[sp]\n\t" | |
8794 | #endif | |
8795 | "pushf\n\t" | |
a547c6db YZ |
8796 | __ASM_SIZE(push) " $%c[cs]\n\t" |
8797 | "call *%[entry]\n\t" | |
8798 | : | |
8799 | #ifdef CONFIG_X86_64 | |
3f62de5f | 8800 | [sp]"=&r"(tmp), |
a547c6db | 8801 | #endif |
3f62de5f | 8802 | "+r"(__sp) |
a547c6db YZ |
8803 | : |
8804 | [entry]"r"(entry), | |
8805 | [ss]"i"(__KERNEL_DS), | |
8806 | [cs]"i"(__KERNEL_CS) | |
8807 | ); | |
f2485b3e | 8808 | } |
a547c6db YZ |
8809 | } |
8810 | ||
6d396b55 PB |
8811 | static bool vmx_has_high_real_mode_segbase(void) |
8812 | { | |
8813 | return enable_unrestricted_guest || emulate_invalid_guest_state; | |
8814 | } | |
8815 | ||
da8999d3 LJ |
8816 | static bool vmx_mpx_supported(void) |
8817 | { | |
8818 | return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) && | |
8819 | (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS); | |
8820 | } | |
8821 | ||
55412b2e WL |
8822 | static bool vmx_xsaves_supported(void) |
8823 | { | |
8824 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
8825 | SECONDARY_EXEC_XSAVES; | |
8826 | } | |
8827 | ||
51aa01d1 AK |
8828 | static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) |
8829 | { | |
c5ca8e57 | 8830 | u32 exit_intr_info; |
51aa01d1 AK |
8831 | bool unblock_nmi; |
8832 | u8 vector; | |
8833 | bool idtv_info_valid; | |
8834 | ||
8835 | idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
20f65983 | 8836 | |
cf393f75 | 8837 | if (cpu_has_virtual_nmis()) { |
9d58b931 AK |
8838 | if (vmx->nmi_known_unmasked) |
8839 | return; | |
c5ca8e57 AK |
8840 | /* |
8841 | * Can't use vmx->exit_intr_info since we're not sure what | |
8842 | * the exit reason is. | |
8843 | */ | |
8844 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
cf393f75 AK |
8845 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; |
8846 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
8847 | /* | |
7b4a25cb | 8848 | * SDM 3: 27.7.1.2 (September 2008) |
cf393f75 AK |
8849 | * Re-set bit "block by NMI" before VM entry if vmexit caused by |
8850 | * a guest IRET fault. | |
7b4a25cb GN |
8851 | * SDM 3: 23.2.2 (September 2008) |
8852 | * Bit 12 is undefined in any of the following cases: | |
8853 | * If the VM exit sets the valid bit in the IDT-vectoring | |
8854 | * information field. | |
8855 | * If the VM exit is due to a double fault. | |
cf393f75 | 8856 | */ |
7b4a25cb GN |
8857 | if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && |
8858 | vector != DF_VECTOR && !idtv_info_valid) | |
cf393f75 AK |
8859 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, |
8860 | GUEST_INTR_STATE_NMI); | |
9d58b931 AK |
8861 | else |
8862 | vmx->nmi_known_unmasked = | |
8863 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) | |
8864 | & GUEST_INTR_STATE_NMI); | |
3b86cd99 JK |
8865 | } else if (unlikely(vmx->soft_vnmi_blocked)) |
8866 | vmx->vnmi_blocked_time += | |
8867 | ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time)); | |
51aa01d1 AK |
8868 | } |
8869 | ||
3ab66e8a | 8870 | static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, |
83422e17 AK |
8871 | u32 idt_vectoring_info, |
8872 | int instr_len_field, | |
8873 | int error_code_field) | |
51aa01d1 | 8874 | { |
51aa01d1 AK |
8875 | u8 vector; |
8876 | int type; | |
8877 | bool idtv_info_valid; | |
8878 | ||
8879 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
668f612f | 8880 | |
3ab66e8a JK |
8881 | vcpu->arch.nmi_injected = false; |
8882 | kvm_clear_exception_queue(vcpu); | |
8883 | kvm_clear_interrupt_queue(vcpu); | |
37b96e98 GN |
8884 | |
8885 | if (!idtv_info_valid) | |
8886 | return; | |
8887 | ||
3ab66e8a | 8888 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3842d135 | 8889 | |
668f612f AK |
8890 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; |
8891 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | |
37b96e98 | 8892 | |
64a7ec06 | 8893 | switch (type) { |
37b96e98 | 8894 | case INTR_TYPE_NMI_INTR: |
3ab66e8a | 8895 | vcpu->arch.nmi_injected = true; |
668f612f | 8896 | /* |
7b4a25cb | 8897 | * SDM 3: 27.7.1.2 (September 2008) |
37b96e98 GN |
8898 | * Clear bit "block by NMI" before VM entry if a NMI |
8899 | * delivery faulted. | |
668f612f | 8900 | */ |
3ab66e8a | 8901 | vmx_set_nmi_mask(vcpu, false); |
37b96e98 | 8902 | break; |
37b96e98 | 8903 | case INTR_TYPE_SOFT_EXCEPTION: |
3ab66e8a | 8904 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f GN |
8905 | /* fall through */ |
8906 | case INTR_TYPE_HARD_EXCEPTION: | |
35920a35 | 8907 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { |
83422e17 | 8908 | u32 err = vmcs_read32(error_code_field); |
851eb667 | 8909 | kvm_requeue_exception_e(vcpu, vector, err); |
35920a35 | 8910 | } else |
851eb667 | 8911 | kvm_requeue_exception(vcpu, vector); |
37b96e98 | 8912 | break; |
66fd3f7f | 8913 | case INTR_TYPE_SOFT_INTR: |
3ab66e8a | 8914 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f | 8915 | /* fall through */ |
37b96e98 | 8916 | case INTR_TYPE_EXT_INTR: |
3ab66e8a | 8917 | kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); |
37b96e98 GN |
8918 | break; |
8919 | default: | |
8920 | break; | |
f7d9238f | 8921 | } |
cf393f75 AK |
8922 | } |
8923 | ||
83422e17 AK |
8924 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
8925 | { | |
3ab66e8a | 8926 | __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, |
83422e17 AK |
8927 | VM_EXIT_INSTRUCTION_LEN, |
8928 | IDT_VECTORING_ERROR_CODE); | |
8929 | } | |
8930 | ||
b463a6f7 AK |
8931 | static void vmx_cancel_injection(struct kvm_vcpu *vcpu) |
8932 | { | |
3ab66e8a | 8933 | __vmx_complete_interrupts(vcpu, |
b463a6f7 AK |
8934 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), |
8935 | VM_ENTRY_INSTRUCTION_LEN, | |
8936 | VM_ENTRY_EXCEPTION_ERROR_CODE); | |
8937 | ||
8938 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); | |
8939 | } | |
8940 | ||
d7cd9796 GN |
8941 | static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) |
8942 | { | |
8943 | int i, nr_msrs; | |
8944 | struct perf_guest_switch_msr *msrs; | |
8945 | ||
8946 | msrs = perf_guest_get_msrs(&nr_msrs); | |
8947 | ||
8948 | if (!msrs) | |
8949 | return; | |
8950 | ||
8951 | for (i = 0; i < nr_msrs; i++) | |
8952 | if (msrs[i].host == msrs[i].guest) | |
8953 | clear_atomic_switch_msr(vmx, msrs[i].msr); | |
8954 | else | |
8955 | add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, | |
8956 | msrs[i].host); | |
8957 | } | |
8958 | ||
33365e7a | 8959 | static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu) |
64672c95 YJ |
8960 | { |
8961 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8962 | u64 tscl; | |
8963 | u32 delta_tsc; | |
8964 | ||
8965 | if (vmx->hv_deadline_tsc == -1) | |
8966 | return; | |
8967 | ||
8968 | tscl = rdtsc(); | |
8969 | if (vmx->hv_deadline_tsc > tscl) | |
8970 | /* sure to be 32 bit only because checked on set_hv_timer */ | |
8971 | delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> | |
8972 | cpu_preemption_timer_multi); | |
8973 | else | |
8974 | delta_tsc = 0; | |
8975 | ||
8976 | vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); | |
8977 | } | |
8978 | ||
a3b5ba49 | 8979 | static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 8980 | { |
a2fa3e9f | 8981 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
d974baa3 | 8982 | unsigned long debugctlmsr, cr4; |
104f226b AK |
8983 | |
8984 | /* Record the guest's net vcpu time for enforced NMI injections. */ | |
8985 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) | |
8986 | vmx->entry_time = ktime_get(); | |
8987 | ||
8988 | /* Don't enter VMX if guest state is invalid, let the exit handler | |
8989 | start emulation until we arrive back to a valid state */ | |
14168786 | 8990 | if (vmx->emulation_required) |
104f226b AK |
8991 | return; |
8992 | ||
a7653ecd RK |
8993 | if (vmx->ple_window_dirty) { |
8994 | vmx->ple_window_dirty = false; | |
8995 | vmcs_write32(PLE_WINDOW, vmx->ple_window); | |
8996 | } | |
8997 | ||
012f83cb AG |
8998 | if (vmx->nested.sync_shadow_vmcs) { |
8999 | copy_vmcs12_to_shadow(vmx); | |
9000 | vmx->nested.sync_shadow_vmcs = false; | |
9001 | } | |
9002 | ||
104f226b AK |
9003 | if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) |
9004 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); | |
9005 | if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
9006 | vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); | |
9007 | ||
1e02ce4c | 9008 | cr4 = cr4_read_shadow(); |
d974baa3 AL |
9009 | if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) { |
9010 | vmcs_writel(HOST_CR4, cr4); | |
9011 | vmx->host_state.vmcs_host_cr4 = cr4; | |
9012 | } | |
9013 | ||
104f226b AK |
9014 | /* When single-stepping over STI and MOV SS, we must clear the |
9015 | * corresponding interruptibility bits in the guest state. Otherwise | |
9016 | * vmentry fails as it then expects bit 14 (BS) in pending debug | |
9017 | * exceptions being set, but that's not correct for the guest debugging | |
9018 | * case. */ | |
9019 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
9020 | vmx_set_interrupt_shadow(vcpu, 0); | |
9021 | ||
1be0e61c XG |
9022 | if (vmx->guest_pkru_valid) |
9023 | __write_pkru(vmx->guest_pkru); | |
9024 | ||
d7cd9796 | 9025 | atomic_switch_perf_msrs(vmx); |
2a7921b7 | 9026 | debugctlmsr = get_debugctlmsr(); |
d7cd9796 | 9027 | |
64672c95 YJ |
9028 | vmx_arm_hv_timer(vcpu); |
9029 | ||
d462b819 | 9030 | vmx->__launched = vmx->loaded_vmcs->launched; |
104f226b | 9031 | asm( |
6aa8b732 | 9032 | /* Store host registers */ |
b188c81f AK |
9033 | "push %%" _ASM_DX "; push %%" _ASM_BP ";" |
9034 | "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */ | |
9035 | "push %%" _ASM_CX " \n\t" | |
9036 | "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t" | |
313dbd49 | 9037 | "je 1f \n\t" |
b188c81f | 9038 | "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t" |
4ecac3fd | 9039 | __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t" |
313dbd49 | 9040 | "1: \n\t" |
d3edefc0 | 9041 | /* Reload cr2 if changed */ |
b188c81f AK |
9042 | "mov %c[cr2](%0), %%" _ASM_AX " \n\t" |
9043 | "mov %%cr2, %%" _ASM_DX " \n\t" | |
9044 | "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t" | |
d3edefc0 | 9045 | "je 2f \n\t" |
b188c81f | 9046 | "mov %%" _ASM_AX", %%cr2 \n\t" |
d3edefc0 | 9047 | "2: \n\t" |
6aa8b732 | 9048 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 9049 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 9050 | /* Load guest registers. Don't clobber flags. */ |
b188c81f AK |
9051 | "mov %c[rax](%0), %%" _ASM_AX " \n\t" |
9052 | "mov %c[rbx](%0), %%" _ASM_BX " \n\t" | |
9053 | "mov %c[rdx](%0), %%" _ASM_DX " \n\t" | |
9054 | "mov %c[rsi](%0), %%" _ASM_SI " \n\t" | |
9055 | "mov %c[rdi](%0), %%" _ASM_DI " \n\t" | |
9056 | "mov %c[rbp](%0), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 9057 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
9058 | "mov %c[r8](%0), %%r8 \n\t" |
9059 | "mov %c[r9](%0), %%r9 \n\t" | |
9060 | "mov %c[r10](%0), %%r10 \n\t" | |
9061 | "mov %c[r11](%0), %%r11 \n\t" | |
9062 | "mov %c[r12](%0), %%r12 \n\t" | |
9063 | "mov %c[r13](%0), %%r13 \n\t" | |
9064 | "mov %c[r14](%0), %%r14 \n\t" | |
9065 | "mov %c[r15](%0), %%r15 \n\t" | |
6aa8b732 | 9066 | #endif |
b188c81f | 9067 | "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */ |
c801949d | 9068 | |
6aa8b732 | 9069 | /* Enter guest mode */ |
83287ea4 | 9070 | "jne 1f \n\t" |
4ecac3fd | 9071 | __ex(ASM_VMX_VMLAUNCH) "\n\t" |
83287ea4 AK |
9072 | "jmp 2f \n\t" |
9073 | "1: " __ex(ASM_VMX_VMRESUME) "\n\t" | |
9074 | "2: " | |
6aa8b732 | 9075 | /* Save guest registers, load host registers, keep flags */ |
b188c81f | 9076 | "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t" |
40712fae | 9077 | "pop %0 \n\t" |
b188c81f AK |
9078 | "mov %%" _ASM_AX ", %c[rax](%0) \n\t" |
9079 | "mov %%" _ASM_BX ", %c[rbx](%0) \n\t" | |
9080 | __ASM_SIZE(pop) " %c[rcx](%0) \n\t" | |
9081 | "mov %%" _ASM_DX ", %c[rdx](%0) \n\t" | |
9082 | "mov %%" _ASM_SI ", %c[rsi](%0) \n\t" | |
9083 | "mov %%" _ASM_DI ", %c[rdi](%0) \n\t" | |
9084 | "mov %%" _ASM_BP ", %c[rbp](%0) \n\t" | |
05b3e0c2 | 9085 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
9086 | "mov %%r8, %c[r8](%0) \n\t" |
9087 | "mov %%r9, %c[r9](%0) \n\t" | |
9088 | "mov %%r10, %c[r10](%0) \n\t" | |
9089 | "mov %%r11, %c[r11](%0) \n\t" | |
9090 | "mov %%r12, %c[r12](%0) \n\t" | |
9091 | "mov %%r13, %c[r13](%0) \n\t" | |
9092 | "mov %%r14, %c[r14](%0) \n\t" | |
9093 | "mov %%r15, %c[r15](%0) \n\t" | |
6aa8b732 | 9094 | #endif |
b188c81f AK |
9095 | "mov %%cr2, %%" _ASM_AX " \n\t" |
9096 | "mov %%" _ASM_AX ", %c[cr2](%0) \n\t" | |
c801949d | 9097 | |
b188c81f | 9098 | "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t" |
e08aa78a | 9099 | "setbe %c[fail](%0) \n\t" |
83287ea4 AK |
9100 | ".pushsection .rodata \n\t" |
9101 | ".global vmx_return \n\t" | |
9102 | "vmx_return: " _ASM_PTR " 2b \n\t" | |
9103 | ".popsection" | |
e08aa78a | 9104 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), |
d462b819 | 9105 | [launched]"i"(offsetof(struct vcpu_vmx, __launched)), |
e08aa78a | 9106 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), |
313dbd49 | 9107 | [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)), |
ad312c7c ZX |
9108 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
9109 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
9110 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
9111 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
9112 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
9113 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
9114 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 9115 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
9116 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
9117 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
9118 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
9119 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
9120 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
9121 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
9122 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
9123 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 9124 | #endif |
40712fae AK |
9125 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)), |
9126 | [wordsize]"i"(sizeof(ulong)) | |
c2036300 LV |
9127 | : "cc", "memory" |
9128 | #ifdef CONFIG_X86_64 | |
b188c81f | 9129 | , "rax", "rbx", "rdi", "rsi" |
c2036300 | 9130 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
b188c81f AK |
9131 | #else |
9132 | , "eax", "ebx", "edi", "esi" | |
c2036300 LV |
9133 | #endif |
9134 | ); | |
6aa8b732 | 9135 | |
2a7921b7 GN |
9136 | /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ |
9137 | if (debugctlmsr) | |
9138 | update_debugctlmsr(debugctlmsr); | |
9139 | ||
aa67f609 AK |
9140 | #ifndef CONFIG_X86_64 |
9141 | /* | |
9142 | * The sysexit path does not restore ds/es, so we must set them to | |
9143 | * a reasonable value ourselves. | |
9144 | * | |
9145 | * We can't defer this to vmx_load_host_state() since that function | |
9146 | * may be executed in interrupt context, which saves and restore segments | |
9147 | * around it, nullifying its effect. | |
9148 | */ | |
9149 | loadsegment(ds, __USER_DS); | |
9150 | loadsegment(es, __USER_DS); | |
9151 | #endif | |
9152 | ||
6de4f3ad | 9153 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) |
6de12732 | 9154 | | (1 << VCPU_EXREG_RFLAGS) |
aff48baa | 9155 | | (1 << VCPU_EXREG_PDPTR) |
2fb92db1 | 9156 | | (1 << VCPU_EXREG_SEGMENTS) |
aff48baa | 9157 | | (1 << VCPU_EXREG_CR3)); |
5fdbf976 MT |
9158 | vcpu->arch.regs_dirty = 0; |
9159 | ||
1155f76a AK |
9160 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); |
9161 | ||
d462b819 | 9162 | vmx->loaded_vmcs->launched = 1; |
1b6269db | 9163 | |
51aa01d1 | 9164 | vmx->exit_reason = vmcs_read32(VM_EXIT_REASON); |
51aa01d1 | 9165 | |
1be0e61c XG |
9166 | /* |
9167 | * eager fpu is enabled if PKEY is supported and CR4 is switched | |
9168 | * back on host, so it is safe to read guest PKRU from current | |
9169 | * XSAVE. | |
9170 | */ | |
9171 | if (boot_cpu_has(X86_FEATURE_OSPKE)) { | |
9172 | vmx->guest_pkru = __read_pkru(); | |
9173 | if (vmx->guest_pkru != vmx->host_pkru) { | |
9174 | vmx->guest_pkru_valid = true; | |
9175 | __write_pkru(vmx->host_pkru); | |
9176 | } else | |
9177 | vmx->guest_pkru_valid = false; | |
9178 | } | |
9179 | ||
e0b890d3 GN |
9180 | /* |
9181 | * the KVM_REQ_EVENT optimization bit is only on for one entry, and if | |
9182 | * we did not inject a still-pending event to L1 now because of | |
9183 | * nested_run_pending, we need to re-enable this bit. | |
9184 | */ | |
9185 | if (vmx->nested.nested_run_pending) | |
9186 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
9187 | ||
9188 | vmx->nested.nested_run_pending = 0; | |
9189 | ||
51aa01d1 AK |
9190 | vmx_complete_atomic_exit(vmx); |
9191 | vmx_recover_nmi_blocking(vmx); | |
cf393f75 | 9192 | vmx_complete_interrupts(vmx); |
6aa8b732 AK |
9193 | } |
9194 | ||
4fa7734c PB |
9195 | static void vmx_load_vmcs01(struct kvm_vcpu *vcpu) |
9196 | { | |
9197 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9198 | int cpu; | |
9199 | ||
9200 | if (vmx->loaded_vmcs == &vmx->vmcs01) | |
9201 | return; | |
9202 | ||
9203 | cpu = get_cpu(); | |
9204 | vmx->loaded_vmcs = &vmx->vmcs01; | |
9205 | vmx_vcpu_put(vcpu); | |
9206 | vmx_vcpu_load(vcpu, cpu); | |
9207 | vcpu->cpu = cpu; | |
9208 | put_cpu(); | |
9209 | } | |
9210 | ||
2f1fe811 JM |
9211 | /* |
9212 | * Ensure that the current vmcs of the logical processor is the | |
9213 | * vmcs01 of the vcpu before calling free_nested(). | |
9214 | */ | |
9215 | static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu) | |
9216 | { | |
9217 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9218 | int r; | |
9219 | ||
9220 | r = vcpu_load(vcpu); | |
9221 | BUG_ON(r); | |
9222 | vmx_load_vmcs01(vcpu); | |
9223 | free_nested(vmx); | |
9224 | vcpu_put(vcpu); | |
9225 | } | |
9226 | ||
6aa8b732 AK |
9227 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) |
9228 | { | |
fb3f0f51 RR |
9229 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
9230 | ||
843e4330 | 9231 | if (enable_pml) |
a3eaa864 | 9232 | vmx_destroy_pml_buffer(vmx); |
991e7a0e | 9233 | free_vpid(vmx->vpid); |
4fa7734c | 9234 | leave_guest_mode(vcpu); |
2f1fe811 | 9235 | vmx_free_vcpu_nested(vcpu); |
4fa7734c | 9236 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 RR |
9237 | kfree(vmx->guest_msrs); |
9238 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 9239 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
9240 | } |
9241 | ||
fb3f0f51 | 9242 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 9243 | { |
fb3f0f51 | 9244 | int err; |
c16f862d | 9245 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
15ad7146 | 9246 | int cpu; |
6aa8b732 | 9247 | |
a2fa3e9f | 9248 | if (!vmx) |
fb3f0f51 RR |
9249 | return ERR_PTR(-ENOMEM); |
9250 | ||
991e7a0e | 9251 | vmx->vpid = allocate_vpid(); |
2384d2b3 | 9252 | |
fb3f0f51 RR |
9253 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
9254 | if (err) | |
9255 | goto free_vcpu; | |
965b58a5 | 9256 | |
4e59516a PF |
9257 | err = -ENOMEM; |
9258 | ||
9259 | /* | |
9260 | * If PML is turned on, failure on enabling PML just results in failure | |
9261 | * of creating the vcpu, therefore we can simplify PML logic (by | |
9262 | * avoiding dealing with cases, such as enabling PML partially on vcpus | |
9263 | * for the guest, etc. | |
9264 | */ | |
9265 | if (enable_pml) { | |
9266 | vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
9267 | if (!vmx->pml_pg) | |
9268 | goto uninit_vcpu; | |
9269 | } | |
9270 | ||
a2fa3e9f | 9271 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
03916db9 PB |
9272 | BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0]) |
9273 | > PAGE_SIZE); | |
0123be42 | 9274 | |
4e59516a PF |
9275 | if (!vmx->guest_msrs) |
9276 | goto free_pml; | |
965b58a5 | 9277 | |
d462b819 NHE |
9278 | vmx->loaded_vmcs = &vmx->vmcs01; |
9279 | vmx->loaded_vmcs->vmcs = alloc_vmcs(); | |
355f4fb1 | 9280 | vmx->loaded_vmcs->shadow_vmcs = NULL; |
d462b819 | 9281 | if (!vmx->loaded_vmcs->vmcs) |
fb3f0f51 | 9282 | goto free_msrs; |
d462b819 NHE |
9283 | if (!vmm_exclusive) |
9284 | kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id()))); | |
9285 | loaded_vmcs_init(vmx->loaded_vmcs); | |
9286 | if (!vmm_exclusive) | |
9287 | kvm_cpu_vmxoff(); | |
a2fa3e9f | 9288 | |
15ad7146 AK |
9289 | cpu = get_cpu(); |
9290 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
e48672fa | 9291 | vmx->vcpu.cpu = cpu; |
8b9cf98c | 9292 | err = vmx_vcpu_setup(vmx); |
fb3f0f51 | 9293 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 9294 | put_cpu(); |
fb3f0f51 RR |
9295 | if (err) |
9296 | goto free_vmcs; | |
35754c98 | 9297 | if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { |
be6d05cf JK |
9298 | err = alloc_apic_access_page(kvm); |
9299 | if (err) | |
5e4a0b3c | 9300 | goto free_vmcs; |
a63cb560 | 9301 | } |
fb3f0f51 | 9302 | |
b927a3ce SY |
9303 | if (enable_ept) { |
9304 | if (!kvm->arch.ept_identity_map_addr) | |
9305 | kvm->arch.ept_identity_map_addr = | |
9306 | VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
f51770ed TC |
9307 | err = init_rmode_identity_map(kvm); |
9308 | if (err) | |
93ea5388 | 9309 | goto free_vmcs; |
b927a3ce | 9310 | } |
b7ebfb05 | 9311 | |
5c614b35 | 9312 | if (nested) { |
b9c237bb | 9313 | nested_vmx_setup_ctls_msrs(vmx); |
5c614b35 WL |
9314 | vmx->nested.vpid02 = allocate_vpid(); |
9315 | } | |
b9c237bb | 9316 | |
705699a1 | 9317 | vmx->nested.posted_intr_nv = -1; |
a9d30f33 NHE |
9318 | vmx->nested.current_vmptr = -1ull; |
9319 | vmx->nested.current_vmcs12 = NULL; | |
9320 | ||
37e4c997 HZ |
9321 | vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED; |
9322 | ||
fb3f0f51 RR |
9323 | return &vmx->vcpu; |
9324 | ||
9325 | free_vmcs: | |
5c614b35 | 9326 | free_vpid(vmx->nested.vpid02); |
5f3fbc34 | 9327 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 | 9328 | free_msrs: |
fb3f0f51 | 9329 | kfree(vmx->guest_msrs); |
4e59516a PF |
9330 | free_pml: |
9331 | vmx_destroy_pml_buffer(vmx); | |
fb3f0f51 RR |
9332 | uninit_vcpu: |
9333 | kvm_vcpu_uninit(&vmx->vcpu); | |
9334 | free_vcpu: | |
991e7a0e | 9335 | free_vpid(vmx->vpid); |
a4770347 | 9336 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 9337 | return ERR_PTR(err); |
6aa8b732 AK |
9338 | } |
9339 | ||
002c7f7c YS |
9340 | static void __init vmx_check_processor_compat(void *rtn) |
9341 | { | |
9342 | struct vmcs_config vmcs_conf; | |
9343 | ||
9344 | *(int *)rtn = 0; | |
9345 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
9346 | *(int *)rtn = -EIO; | |
9347 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
9348 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
9349 | smp_processor_id()); | |
9350 | *(int *)rtn = -EIO; | |
9351 | } | |
9352 | } | |
9353 | ||
67253af5 SY |
9354 | static int get_ept_level(void) |
9355 | { | |
9356 | return VMX_EPT_DEFAULT_GAW + 1; | |
9357 | } | |
9358 | ||
4b12f0de | 9359 | static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 | 9360 | { |
b18d5431 XG |
9361 | u8 cache; |
9362 | u64 ipat = 0; | |
4b12f0de | 9363 | |
522c68c4 | 9364 | /* For VT-d and EPT combination |
606decd6 | 9365 | * 1. MMIO: always map as UC |
522c68c4 SY |
9366 | * 2. EPT with VT-d: |
9367 | * a. VT-d without snooping control feature: can't guarantee the | |
606decd6 | 9368 | * result, try to trust guest. |
522c68c4 SY |
9369 | * b. VT-d with snooping control feature: snooping control feature of |
9370 | * VT-d engine can guarantee the cache correctness. Just set it | |
9371 | * to WB to keep consistent with host. So the same as item 3. | |
a19a6d11 | 9372 | * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep |
522c68c4 SY |
9373 | * consistent with host MTRR |
9374 | */ | |
606decd6 PB |
9375 | if (is_mmio) { |
9376 | cache = MTRR_TYPE_UNCACHABLE; | |
9377 | goto exit; | |
9378 | } | |
9379 | ||
9380 | if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { | |
b18d5431 XG |
9381 | ipat = VMX_EPT_IPAT_BIT; |
9382 | cache = MTRR_TYPE_WRBACK; | |
9383 | goto exit; | |
9384 | } | |
9385 | ||
9386 | if (kvm_read_cr0(vcpu) & X86_CR0_CD) { | |
9387 | ipat = VMX_EPT_IPAT_BIT; | |
0da029ed | 9388 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) |
fb279950 XG |
9389 | cache = MTRR_TYPE_WRBACK; |
9390 | else | |
9391 | cache = MTRR_TYPE_UNCACHABLE; | |
b18d5431 XG |
9392 | goto exit; |
9393 | } | |
9394 | ||
ff53604b | 9395 | cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); |
b18d5431 XG |
9396 | |
9397 | exit: | |
9398 | return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; | |
64d4d521 SY |
9399 | } |
9400 | ||
17cc3935 | 9401 | static int vmx_get_lpage_level(void) |
344f414f | 9402 | { |
878403b7 SY |
9403 | if (enable_ept && !cpu_has_vmx_ept_1g_page()) |
9404 | return PT_DIRECTORY_LEVEL; | |
9405 | else | |
9406 | /* For shadow and EPT supported 1GB page */ | |
9407 | return PT_PDPE_LEVEL; | |
344f414f JR |
9408 | } |
9409 | ||
feda805f XG |
9410 | static void vmcs_set_secondary_exec_control(u32 new_ctl) |
9411 | { | |
9412 | /* | |
9413 | * These bits in the secondary execution controls field | |
9414 | * are dynamic, the others are mostly based on the hypervisor | |
9415 | * architecture and the guest's CPUID. Do not touch the | |
9416 | * dynamic bits. | |
9417 | */ | |
9418 | u32 mask = | |
9419 | SECONDARY_EXEC_SHADOW_VMCS | | |
9420 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | | |
9421 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
9422 | ||
9423 | u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
9424 | ||
9425 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, | |
9426 | (new_ctl & ~mask) | (cur_ctl & mask)); | |
9427 | } | |
9428 | ||
8322ebbb DM |
9429 | /* |
9430 | * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits | |
9431 | * (indicating "allowed-1") if they are supported in the guest's CPUID. | |
9432 | */ | |
9433 | static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) | |
9434 | { | |
9435 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9436 | struct kvm_cpuid_entry2 *entry; | |
9437 | ||
9438 | vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff; | |
9439 | vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE; | |
9440 | ||
9441 | #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ | |
9442 | if (entry && (entry->_reg & (_cpuid_mask))) \ | |
9443 | vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \ | |
9444 | } while (0) | |
9445 | ||
9446 | entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); | |
9447 | cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME)); | |
9448 | cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME)); | |
9449 | cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC)); | |
9450 | cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE)); | |
9451 | cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE)); | |
9452 | cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE)); | |
9453 | cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE)); | |
9454 | cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE)); | |
9455 | cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR)); | |
9456 | cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM)); | |
9457 | cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX)); | |
9458 | cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX)); | |
9459 | cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID)); | |
9460 | cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE)); | |
9461 | ||
9462 | entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); | |
9463 | cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE)); | |
9464 | cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP)); | |
9465 | cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP)); | |
9466 | cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU)); | |
9467 | /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */ | |
9468 | cr4_fixed1_update(bit(11), ecx, bit(2)); | |
9469 | ||
9470 | #undef cr4_fixed1_update | |
9471 | } | |
9472 | ||
0e851880 SY |
9473 | static void vmx_cpuid_update(struct kvm_vcpu *vcpu) |
9474 | { | |
4e47c7a6 SY |
9475 | struct kvm_cpuid_entry2 *best; |
9476 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
feda805f | 9477 | u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx); |
4e47c7a6 | 9478 | |
4e47c7a6 | 9479 | if (vmx_rdtscp_supported()) { |
1cea0ce6 XG |
9480 | bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu); |
9481 | if (!rdtscp_enabled) | |
feda805f | 9482 | secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP; |
f36201e5 | 9483 | |
8b97265a | 9484 | if (nested) { |
1cea0ce6 | 9485 | if (rdtscp_enabled) |
8b97265a PB |
9486 | vmx->nested.nested_vmx_secondary_ctls_high |= |
9487 | SECONDARY_EXEC_RDTSCP; | |
9488 | else | |
9489 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
9490 | ~SECONDARY_EXEC_RDTSCP; | |
9491 | } | |
4e47c7a6 | 9492 | } |
ad756a16 | 9493 | |
ad756a16 MJ |
9494 | /* Exposing INVPCID only when PCID is exposed */ |
9495 | best = kvm_find_cpuid_entry(vcpu, 0x7, 0); | |
9496 | if (vmx_invpcid_supported() && | |
29541bb8 XG |
9497 | (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) || |
9498 | !guest_cpuid_has_pcid(vcpu))) { | |
feda805f | 9499 | secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID; |
29541bb8 | 9500 | |
ad756a16 | 9501 | if (best) |
4f977045 | 9502 | best->ebx &= ~bit(X86_FEATURE_INVPCID); |
ad756a16 | 9503 | } |
8b3e34e4 | 9504 | |
45bdbcfd HH |
9505 | if (cpu_has_secondary_exec_ctrls()) |
9506 | vmcs_set_secondary_exec_control(secondary_exec_ctl); | |
feda805f | 9507 | |
37e4c997 HZ |
9508 | if (nested_vmx_allowed(vcpu)) |
9509 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= | |
9510 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
9511 | else | |
9512 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= | |
9513 | ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
8322ebbb DM |
9514 | |
9515 | if (nested_vmx_allowed(vcpu)) | |
9516 | nested_vmx_cr_fixed1_bits_update(vcpu); | |
0e851880 SY |
9517 | } |
9518 | ||
d4330ef2 JR |
9519 | static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
9520 | { | |
7b8050f5 NHE |
9521 | if (func == 1 && nested) |
9522 | entry->ecx |= bit(X86_FEATURE_VMX); | |
d4330ef2 JR |
9523 | } |
9524 | ||
25d92081 YZ |
9525 | static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu, |
9526 | struct x86_exception *fault) | |
9527 | { | |
533558bc JK |
9528 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
9529 | u32 exit_reason; | |
25d92081 YZ |
9530 | |
9531 | if (fault->error_code & PFERR_RSVD_MASK) | |
533558bc | 9532 | exit_reason = EXIT_REASON_EPT_MISCONFIG; |
25d92081 | 9533 | else |
533558bc JK |
9534 | exit_reason = EXIT_REASON_EPT_VIOLATION; |
9535 | nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification); | |
25d92081 YZ |
9536 | vmcs12->guest_physical_address = fault->address; |
9537 | } | |
9538 | ||
155a97a3 NHE |
9539 | /* Callbacks for nested_ept_init_mmu_context: */ |
9540 | ||
9541 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu) | |
9542 | { | |
9543 | /* return the page table to be shadowed - in our case, EPT12 */ | |
9544 | return get_vmcs12(vcpu)->ept_pointer; | |
9545 | } | |
9546 | ||
8a3c1a33 | 9547 | static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu) |
155a97a3 | 9548 | { |
ad896af0 PB |
9549 | WARN_ON(mmu_is_nested(vcpu)); |
9550 | kvm_init_shadow_ept_mmu(vcpu, | |
b9c237bb WV |
9551 | to_vmx(vcpu)->nested.nested_vmx_ept_caps & |
9552 | VMX_EPT_EXECUTE_ONLY_BIT); | |
155a97a3 NHE |
9553 | vcpu->arch.mmu.set_cr3 = vmx_set_cr3; |
9554 | vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3; | |
9555 | vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault; | |
9556 | ||
9557 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
155a97a3 NHE |
9558 | } |
9559 | ||
9560 | static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
9561 | { | |
9562 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
9563 | } | |
9564 | ||
19d5f10b EK |
9565 | static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, |
9566 | u16 error_code) | |
9567 | { | |
9568 | bool inequality, bit; | |
9569 | ||
9570 | bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0; | |
9571 | inequality = | |
9572 | (error_code & vmcs12->page_fault_error_code_mask) != | |
9573 | vmcs12->page_fault_error_code_match; | |
9574 | return inequality ^ bit; | |
9575 | } | |
9576 | ||
feaf0c7d GN |
9577 | static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu, |
9578 | struct x86_exception *fault) | |
9579 | { | |
9580 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
9581 | ||
9582 | WARN_ON(!is_guest_mode(vcpu)); | |
9583 | ||
19d5f10b | 9584 | if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code)) |
533558bc JK |
9585 | nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason, |
9586 | vmcs_read32(VM_EXIT_INTR_INFO), | |
9587 | vmcs_readl(EXIT_QUALIFICATION)); | |
feaf0c7d GN |
9588 | else |
9589 | kvm_inject_page_fault(vcpu, fault); | |
9590 | } | |
9591 | ||
a2bcba50 WL |
9592 | static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu, |
9593 | struct vmcs12 *vmcs12) | |
9594 | { | |
9595 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9090422f | 9596 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
a2bcba50 WL |
9597 | |
9598 | if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
9090422f EK |
9599 | if (!PAGE_ALIGNED(vmcs12->apic_access_addr) || |
9600 | vmcs12->apic_access_addr >> maxphyaddr) | |
a2bcba50 WL |
9601 | return false; |
9602 | ||
9603 | /* | |
9604 | * Translate L1 physical address to host physical | |
9605 | * address for vmcs02. Keep the page pinned, so this | |
9606 | * physical address remains valid. We keep a reference | |
9607 | * to it so we can release it later. | |
9608 | */ | |
9609 | if (vmx->nested.apic_access_page) /* shouldn't happen */ | |
9610 | nested_release_page(vmx->nested.apic_access_page); | |
9611 | vmx->nested.apic_access_page = | |
9612 | nested_get_page(vcpu, vmcs12->apic_access_addr); | |
9613 | } | |
a7c0b07d WL |
9614 | |
9615 | if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { | |
9090422f EK |
9616 | if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) || |
9617 | vmcs12->virtual_apic_page_addr >> maxphyaddr) | |
a7c0b07d WL |
9618 | return false; |
9619 | ||
9620 | if (vmx->nested.virtual_apic_page) /* shouldn't happen */ | |
9621 | nested_release_page(vmx->nested.virtual_apic_page); | |
9622 | vmx->nested.virtual_apic_page = | |
9623 | nested_get_page(vcpu, vmcs12->virtual_apic_page_addr); | |
9624 | ||
9625 | /* | |
9626 | * Failing the vm entry is _not_ what the processor does | |
9627 | * but it's basically the only possibility we have. | |
9628 | * We could still enter the guest if CR8 load exits are | |
9629 | * enabled, CR8 store exits are enabled, and virtualize APIC | |
9630 | * access is disabled; in this case the processor would never | |
9631 | * use the TPR shadow and we could simply clear the bit from | |
9632 | * the execution control. But such a configuration is useless, | |
9633 | * so let's keep the code simple. | |
9634 | */ | |
9635 | if (!vmx->nested.virtual_apic_page) | |
9636 | return false; | |
9637 | } | |
9638 | ||
705699a1 | 9639 | if (nested_cpu_has_posted_intr(vmcs12)) { |
9090422f EK |
9640 | if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) || |
9641 | vmcs12->posted_intr_desc_addr >> maxphyaddr) | |
705699a1 WV |
9642 | return false; |
9643 | ||
9644 | if (vmx->nested.pi_desc_page) { /* shouldn't happen */ | |
9645 | kunmap(vmx->nested.pi_desc_page); | |
9646 | nested_release_page(vmx->nested.pi_desc_page); | |
9647 | } | |
9648 | vmx->nested.pi_desc_page = | |
9649 | nested_get_page(vcpu, vmcs12->posted_intr_desc_addr); | |
9650 | if (!vmx->nested.pi_desc_page) | |
9651 | return false; | |
9652 | ||
9653 | vmx->nested.pi_desc = | |
9654 | (struct pi_desc *)kmap(vmx->nested.pi_desc_page); | |
9655 | if (!vmx->nested.pi_desc) { | |
9656 | nested_release_page_clean(vmx->nested.pi_desc_page); | |
9657 | return false; | |
9658 | } | |
9659 | vmx->nested.pi_desc = | |
9660 | (struct pi_desc *)((void *)vmx->nested.pi_desc + | |
9661 | (unsigned long)(vmcs12->posted_intr_desc_addr & | |
9662 | (PAGE_SIZE - 1))); | |
9663 | } | |
9664 | ||
a2bcba50 WL |
9665 | return true; |
9666 | } | |
9667 | ||
f4124500 JK |
9668 | static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu) |
9669 | { | |
9670 | u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value; | |
9671 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9672 | ||
9673 | if (vcpu->arch.virtual_tsc_khz == 0) | |
9674 | return; | |
9675 | ||
9676 | /* Make sure short timeouts reliably trigger an immediate vmexit. | |
9677 | * hrtimer_start does not guarantee this. */ | |
9678 | if (preemption_timeout <= 1) { | |
9679 | vmx_preemption_timer_fn(&vmx->nested.preemption_timer); | |
9680 | return; | |
9681 | } | |
9682 | ||
9683 | preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
9684 | preemption_timeout *= 1000000; | |
9685 | do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz); | |
9686 | hrtimer_start(&vmx->nested.preemption_timer, | |
9687 | ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL); | |
9688 | } | |
9689 | ||
3af18d9c WV |
9690 | static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, |
9691 | struct vmcs12 *vmcs12) | |
9692 | { | |
9693 | int maxphyaddr; | |
9694 | u64 addr; | |
9695 | ||
9696 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) | |
9697 | return 0; | |
9698 | ||
9699 | if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) { | |
9700 | WARN_ON(1); | |
9701 | return -EINVAL; | |
9702 | } | |
9703 | maxphyaddr = cpuid_maxphyaddr(vcpu); | |
9704 | ||
9705 | if (!PAGE_ALIGNED(vmcs12->msr_bitmap) || | |
9706 | ((addr + PAGE_SIZE) >> maxphyaddr)) | |
9707 | return -EINVAL; | |
9708 | ||
9709 | return 0; | |
9710 | } | |
9711 | ||
9712 | /* | |
9713 | * Merge L0's and L1's MSR bitmap, return false to indicate that | |
9714 | * we do not use the hardware. | |
9715 | */ | |
9716 | static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu, | |
9717 | struct vmcs12 *vmcs12) | |
9718 | { | |
82f0dd4b | 9719 | int msr; |
f2b93280 | 9720 | struct page *page; |
d048c098 RK |
9721 | unsigned long *msr_bitmap_l1; |
9722 | unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap; | |
f2b93280 | 9723 | |
d048c098 | 9724 | /* This shortcut is ok because we support only x2APIC MSRs so far. */ |
f2b93280 WV |
9725 | if (!nested_cpu_has_virt_x2apic_mode(vmcs12)) |
9726 | return false; | |
9727 | ||
9728 | page = nested_get_page(vcpu, vmcs12->msr_bitmap); | |
9729 | if (!page) { | |
9730 | WARN_ON(1); | |
9731 | return false; | |
9732 | } | |
d048c098 RK |
9733 | msr_bitmap_l1 = (unsigned long *)kmap(page); |
9734 | if (!msr_bitmap_l1) { | |
f2b93280 WV |
9735 | nested_release_page_clean(page); |
9736 | WARN_ON(1); | |
9737 | return false; | |
9738 | } | |
9739 | ||
d048c098 RK |
9740 | memset(msr_bitmap_l0, 0xff, PAGE_SIZE); |
9741 | ||
f2b93280 | 9742 | if (nested_cpu_has_virt_x2apic_mode(vmcs12)) { |
82f0dd4b WV |
9743 | if (nested_cpu_has_apic_reg_virt(vmcs12)) |
9744 | for (msr = 0x800; msr <= 0x8ff; msr++) | |
9745 | nested_vmx_disable_intercept_for_msr( | |
d048c098 | 9746 | msr_bitmap_l1, msr_bitmap_l0, |
82f0dd4b | 9747 | msr, MSR_TYPE_R); |
d048c098 RK |
9748 | |
9749 | nested_vmx_disable_intercept_for_msr( | |
9750 | msr_bitmap_l1, msr_bitmap_l0, | |
f2b93280 WV |
9751 | APIC_BASE_MSR + (APIC_TASKPRI >> 4), |
9752 | MSR_TYPE_R | MSR_TYPE_W); | |
d048c098 | 9753 | |
608406e2 | 9754 | if (nested_cpu_has_vid(vmcs12)) { |
608406e2 | 9755 | nested_vmx_disable_intercept_for_msr( |
d048c098 | 9756 | msr_bitmap_l1, msr_bitmap_l0, |
608406e2 WV |
9757 | APIC_BASE_MSR + (APIC_EOI >> 4), |
9758 | MSR_TYPE_W); | |
9759 | nested_vmx_disable_intercept_for_msr( | |
d048c098 | 9760 | msr_bitmap_l1, msr_bitmap_l0, |
608406e2 WV |
9761 | APIC_BASE_MSR + (APIC_SELF_IPI >> 4), |
9762 | MSR_TYPE_W); | |
9763 | } | |
82f0dd4b | 9764 | } |
f2b93280 WV |
9765 | kunmap(page); |
9766 | nested_release_page_clean(page); | |
9767 | ||
9768 | return true; | |
9769 | } | |
9770 | ||
9771 | static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu, | |
9772 | struct vmcs12 *vmcs12) | |
9773 | { | |
82f0dd4b | 9774 | if (!nested_cpu_has_virt_x2apic_mode(vmcs12) && |
608406e2 | 9775 | !nested_cpu_has_apic_reg_virt(vmcs12) && |
705699a1 WV |
9776 | !nested_cpu_has_vid(vmcs12) && |
9777 | !nested_cpu_has_posted_intr(vmcs12)) | |
f2b93280 WV |
9778 | return 0; |
9779 | ||
9780 | /* | |
9781 | * If virtualize x2apic mode is enabled, | |
9782 | * virtualize apic access must be disabled. | |
9783 | */ | |
82f0dd4b WV |
9784 | if (nested_cpu_has_virt_x2apic_mode(vmcs12) && |
9785 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
f2b93280 WV |
9786 | return -EINVAL; |
9787 | ||
608406e2 WV |
9788 | /* |
9789 | * If virtual interrupt delivery is enabled, | |
9790 | * we must exit on external interrupts. | |
9791 | */ | |
9792 | if (nested_cpu_has_vid(vmcs12) && | |
9793 | !nested_exit_on_intr(vcpu)) | |
9794 | return -EINVAL; | |
9795 | ||
705699a1 WV |
9796 | /* |
9797 | * bits 15:8 should be zero in posted_intr_nv, | |
9798 | * the descriptor address has been already checked | |
9799 | * in nested_get_vmcs12_pages. | |
9800 | */ | |
9801 | if (nested_cpu_has_posted_intr(vmcs12) && | |
9802 | (!nested_cpu_has_vid(vmcs12) || | |
9803 | !nested_exit_intr_ack_set(vcpu) || | |
9804 | vmcs12->posted_intr_nv & 0xff00)) | |
9805 | return -EINVAL; | |
9806 | ||
f2b93280 WV |
9807 | /* tpr shadow is needed by all apicv features. */ |
9808 | if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
9809 | return -EINVAL; | |
9810 | ||
9811 | return 0; | |
3af18d9c WV |
9812 | } |
9813 | ||
e9ac033e EK |
9814 | static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu, |
9815 | unsigned long count_field, | |
92d71bc6 | 9816 | unsigned long addr_field) |
ff651cb6 | 9817 | { |
92d71bc6 | 9818 | int maxphyaddr; |
e9ac033e EK |
9819 | u64 count, addr; |
9820 | ||
9821 | if (vmcs12_read_any(vcpu, count_field, &count) || | |
9822 | vmcs12_read_any(vcpu, addr_field, &addr)) { | |
9823 | WARN_ON(1); | |
9824 | return -EINVAL; | |
9825 | } | |
9826 | if (count == 0) | |
9827 | return 0; | |
92d71bc6 | 9828 | maxphyaddr = cpuid_maxphyaddr(vcpu); |
e9ac033e EK |
9829 | if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr || |
9830 | (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) { | |
bbe41b95 | 9831 | pr_debug_ratelimited( |
e9ac033e EK |
9832 | "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)", |
9833 | addr_field, maxphyaddr, count, addr); | |
9834 | return -EINVAL; | |
9835 | } | |
9836 | return 0; | |
9837 | } | |
9838 | ||
9839 | static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu, | |
9840 | struct vmcs12 *vmcs12) | |
9841 | { | |
e9ac033e EK |
9842 | if (vmcs12->vm_exit_msr_load_count == 0 && |
9843 | vmcs12->vm_exit_msr_store_count == 0 && | |
9844 | vmcs12->vm_entry_msr_load_count == 0) | |
9845 | return 0; /* Fast path */ | |
e9ac033e | 9846 | if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT, |
92d71bc6 | 9847 | VM_EXIT_MSR_LOAD_ADDR) || |
e9ac033e | 9848 | nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT, |
92d71bc6 | 9849 | VM_EXIT_MSR_STORE_ADDR) || |
e9ac033e | 9850 | nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT, |
92d71bc6 | 9851 | VM_ENTRY_MSR_LOAD_ADDR)) |
e9ac033e EK |
9852 | return -EINVAL; |
9853 | return 0; | |
9854 | } | |
9855 | ||
9856 | static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu, | |
9857 | struct vmx_msr_entry *e) | |
9858 | { | |
9859 | /* x2APIC MSR accesses are not allowed */ | |
8a9781f7 | 9860 | if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8) |
e9ac033e EK |
9861 | return -EINVAL; |
9862 | if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */ | |
9863 | e->index == MSR_IA32_UCODE_REV) | |
9864 | return -EINVAL; | |
9865 | if (e->reserved != 0) | |
ff651cb6 WV |
9866 | return -EINVAL; |
9867 | return 0; | |
9868 | } | |
9869 | ||
e9ac033e EK |
9870 | static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu, |
9871 | struct vmx_msr_entry *e) | |
ff651cb6 WV |
9872 | { |
9873 | if (e->index == MSR_FS_BASE || | |
9874 | e->index == MSR_GS_BASE || | |
e9ac033e EK |
9875 | e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */ |
9876 | nested_vmx_msr_check_common(vcpu, e)) | |
9877 | return -EINVAL; | |
9878 | return 0; | |
9879 | } | |
9880 | ||
9881 | static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu, | |
9882 | struct vmx_msr_entry *e) | |
9883 | { | |
9884 | if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */ | |
9885 | nested_vmx_msr_check_common(vcpu, e)) | |
ff651cb6 WV |
9886 | return -EINVAL; |
9887 | return 0; | |
9888 | } | |
9889 | ||
9890 | /* | |
9891 | * Load guest's/host's msr at nested entry/exit. | |
9892 | * return 0 for success, entry index for failure. | |
9893 | */ | |
9894 | static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) | |
9895 | { | |
9896 | u32 i; | |
9897 | struct vmx_msr_entry e; | |
9898 | struct msr_data msr; | |
9899 | ||
9900 | msr.host_initiated = false; | |
9901 | for (i = 0; i < count; i++) { | |
54bf36aa PB |
9902 | if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e), |
9903 | &e, sizeof(e))) { | |
bbe41b95 | 9904 | pr_debug_ratelimited( |
e9ac033e EK |
9905 | "%s cannot read MSR entry (%u, 0x%08llx)\n", |
9906 | __func__, i, gpa + i * sizeof(e)); | |
ff651cb6 | 9907 | goto fail; |
e9ac033e EK |
9908 | } |
9909 | if (nested_vmx_load_msr_check(vcpu, &e)) { | |
bbe41b95 | 9910 | pr_debug_ratelimited( |
e9ac033e EK |
9911 | "%s check failed (%u, 0x%x, 0x%x)\n", |
9912 | __func__, i, e.index, e.reserved); | |
9913 | goto fail; | |
9914 | } | |
ff651cb6 WV |
9915 | msr.index = e.index; |
9916 | msr.data = e.value; | |
e9ac033e | 9917 | if (kvm_set_msr(vcpu, &msr)) { |
bbe41b95 | 9918 | pr_debug_ratelimited( |
e9ac033e EK |
9919 | "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", |
9920 | __func__, i, e.index, e.value); | |
ff651cb6 | 9921 | goto fail; |
e9ac033e | 9922 | } |
ff651cb6 WV |
9923 | } |
9924 | return 0; | |
9925 | fail: | |
9926 | return i + 1; | |
9927 | } | |
9928 | ||
9929 | static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) | |
9930 | { | |
9931 | u32 i; | |
9932 | struct vmx_msr_entry e; | |
9933 | ||
9934 | for (i = 0; i < count; i++) { | |
609e36d3 | 9935 | struct msr_data msr_info; |
54bf36aa PB |
9936 | if (kvm_vcpu_read_guest(vcpu, |
9937 | gpa + i * sizeof(e), | |
9938 | &e, 2 * sizeof(u32))) { | |
bbe41b95 | 9939 | pr_debug_ratelimited( |
e9ac033e EK |
9940 | "%s cannot read MSR entry (%u, 0x%08llx)\n", |
9941 | __func__, i, gpa + i * sizeof(e)); | |
ff651cb6 | 9942 | return -EINVAL; |
e9ac033e EK |
9943 | } |
9944 | if (nested_vmx_store_msr_check(vcpu, &e)) { | |
bbe41b95 | 9945 | pr_debug_ratelimited( |
e9ac033e EK |
9946 | "%s check failed (%u, 0x%x, 0x%x)\n", |
9947 | __func__, i, e.index, e.reserved); | |
ff651cb6 | 9948 | return -EINVAL; |
e9ac033e | 9949 | } |
609e36d3 PB |
9950 | msr_info.host_initiated = false; |
9951 | msr_info.index = e.index; | |
9952 | if (kvm_get_msr(vcpu, &msr_info)) { | |
bbe41b95 | 9953 | pr_debug_ratelimited( |
e9ac033e EK |
9954 | "%s cannot read MSR (%u, 0x%x)\n", |
9955 | __func__, i, e.index); | |
9956 | return -EINVAL; | |
9957 | } | |
54bf36aa PB |
9958 | if (kvm_vcpu_write_guest(vcpu, |
9959 | gpa + i * sizeof(e) + | |
9960 | offsetof(struct vmx_msr_entry, value), | |
9961 | &msr_info.data, sizeof(msr_info.data))) { | |
bbe41b95 | 9962 | pr_debug_ratelimited( |
e9ac033e | 9963 | "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", |
609e36d3 | 9964 | __func__, i, e.index, msr_info.data); |
e9ac033e EK |
9965 | return -EINVAL; |
9966 | } | |
ff651cb6 WV |
9967 | } |
9968 | return 0; | |
9969 | } | |
9970 | ||
9ed38ffa LP |
9971 | /* |
9972 | * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are | |
9973 | * emulating VM entry into a guest with EPT enabled. | |
9974 | * Returns 0 on success, 1 on failure. Invalid state exit qualification code | |
9975 | * is assigned to entry_failure_code on failure. | |
9976 | */ | |
9977 | static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept, | |
9978 | unsigned long *entry_failure_code) | |
9979 | { | |
9980 | unsigned long invalid_mask; | |
9981 | ||
9982 | if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) { | |
9983 | invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu); | |
9984 | if (cr3 & invalid_mask) { | |
9985 | *entry_failure_code = ENTRY_FAIL_DEFAULT; | |
9986 | return 1; | |
9987 | } | |
9988 | ||
9989 | /* | |
9990 | * If PAE paging and EPT are both on, CR3 is not used by the CPU and | |
9991 | * must not be dereferenced. | |
9992 | */ | |
9993 | if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) && | |
9994 | !nested_ept) { | |
9995 | if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) { | |
9996 | *entry_failure_code = ENTRY_FAIL_PDPTE; | |
9997 | return 1; | |
9998 | } | |
9999 | } | |
10000 | ||
10001 | vcpu->arch.cr3 = cr3; | |
10002 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
10003 | } | |
10004 | ||
10005 | kvm_mmu_reset_context(vcpu); | |
10006 | return 0; | |
10007 | } | |
10008 | ||
fe3ef05c NHE |
10009 | /* |
10010 | * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested | |
10011 | * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it | |
b4619660 | 10012 | * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2 |
fe3ef05c NHE |
10013 | * guest in a way that will both be appropriate to L1's requests, and our |
10014 | * needs. In addition to modifying the active vmcs (which is vmcs02), this | |
10015 | * function also has additional necessary side-effects, like setting various | |
10016 | * vcpu->arch fields. | |
ee146c1c LP |
10017 | * Returns 0 on success, 1 on failure. Invalid state exit qualification code |
10018 | * is assigned to entry_failure_code on failure. | |
fe3ef05c | 10019 | */ |
ee146c1c LP |
10020 | static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, |
10021 | unsigned long *entry_failure_code) | |
fe3ef05c NHE |
10022 | { |
10023 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10024 | u32 exec_control; | |
7ca29de2 | 10025 | bool nested_ept_enabled = false; |
fe3ef05c NHE |
10026 | |
10027 | vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector); | |
10028 | vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector); | |
10029 | vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector); | |
10030 | vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector); | |
10031 | vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector); | |
10032 | vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector); | |
10033 | vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector); | |
10034 | vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector); | |
10035 | vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit); | |
10036 | vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit); | |
10037 | vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit); | |
10038 | vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit); | |
10039 | vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit); | |
10040 | vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit); | |
10041 | vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit); | |
10042 | vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit); | |
10043 | vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit); | |
10044 | vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit); | |
10045 | vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes); | |
10046 | vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes); | |
10047 | vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes); | |
10048 | vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes); | |
10049 | vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes); | |
10050 | vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes); | |
10051 | vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes); | |
10052 | vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes); | |
10053 | vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base); | |
10054 | vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base); | |
10055 | vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base); | |
10056 | vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base); | |
10057 | vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base); | |
10058 | vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base); | |
10059 | vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base); | |
10060 | vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base); | |
10061 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base); | |
10062 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base); | |
10063 | ||
2996fca0 JK |
10064 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) { |
10065 | kvm_set_dr(vcpu, 7, vmcs12->guest_dr7); | |
10066 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl); | |
10067 | } else { | |
10068 | kvm_set_dr(vcpu, 7, vcpu->arch.dr7); | |
10069 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl); | |
10070 | } | |
fe3ef05c NHE |
10071 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
10072 | vmcs12->vm_entry_intr_info_field); | |
10073 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, | |
10074 | vmcs12->vm_entry_exception_error_code); | |
10075 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
10076 | vmcs12->vm_entry_instruction_len); | |
10077 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
10078 | vmcs12->guest_interruptibility_info); | |
fe3ef05c | 10079 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs); |
63fbf59f | 10080 | vmx_set_rflags(vcpu, vmcs12->guest_rflags); |
fe3ef05c NHE |
10081 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, |
10082 | vmcs12->guest_pending_dbg_exceptions); | |
10083 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp); | |
10084 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip); | |
10085 | ||
81dc01f7 WL |
10086 | if (nested_cpu_has_xsaves(vmcs12)) |
10087 | vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap); | |
fe3ef05c NHE |
10088 | vmcs_write64(VMCS_LINK_POINTER, -1ull); |
10089 | ||
f4124500 | 10090 | exec_control = vmcs12->pin_based_vm_exec_control; |
9314006d PB |
10091 | |
10092 | /* Preemption timer setting is only taken from vmcs01. */ | |
705699a1 | 10093 | exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; |
9314006d PB |
10094 | exec_control |= vmcs_config.pin_based_exec_ctrl; |
10095 | if (vmx->hv_deadline_tsc == -1) | |
10096 | exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
705699a1 | 10097 | |
9314006d | 10098 | /* Posted interrupts setting is only taken from vmcs12. */ |
705699a1 WV |
10099 | if (nested_cpu_has_posted_intr(vmcs12)) { |
10100 | /* | |
10101 | * Note that we use L0's vector here and in | |
10102 | * vmx_deliver_nested_posted_interrupt. | |
10103 | */ | |
10104 | vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv; | |
10105 | vmx->nested.pi_pending = false; | |
0bcf261c | 10106 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); |
705699a1 WV |
10107 | vmcs_write64(POSTED_INTR_DESC_ADDR, |
10108 | page_to_phys(vmx->nested.pi_desc_page) + | |
10109 | (unsigned long)(vmcs12->posted_intr_desc_addr & | |
10110 | (PAGE_SIZE - 1))); | |
10111 | } else | |
10112 | exec_control &= ~PIN_BASED_POSTED_INTR; | |
10113 | ||
f4124500 | 10114 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control); |
fe3ef05c | 10115 | |
f4124500 JK |
10116 | vmx->nested.preemption_timer_expired = false; |
10117 | if (nested_cpu_has_preemption_timer(vmcs12)) | |
10118 | vmx_start_preemption_timer(vcpu); | |
0238ea91 | 10119 | |
fe3ef05c NHE |
10120 | /* |
10121 | * Whether page-faults are trapped is determined by a combination of | |
10122 | * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF. | |
10123 | * If enable_ept, L0 doesn't care about page faults and we should | |
10124 | * set all of these to L1's desires. However, if !enable_ept, L0 does | |
10125 | * care about (at least some) page faults, and because it is not easy | |
10126 | * (if at all possible?) to merge L0 and L1's desires, we simply ask | |
10127 | * to exit on each and every L2 page fault. This is done by setting | |
10128 | * MASK=MATCH=0 and (see below) EB.PF=1. | |
10129 | * Note that below we don't need special code to set EB.PF beyond the | |
10130 | * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept, | |
10131 | * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when | |
10132 | * !enable_ept, EB.PF is 1, so the "or" will always be 1. | |
10133 | * | |
10134 | * A problem with this approach (when !enable_ept) is that L1 may be | |
10135 | * injected with more page faults than it asked for. This could have | |
10136 | * caused problems, but in practice existing hypervisors don't care. | |
10137 | * To fix this, we will need to emulate the PFEC checking (on the L1 | |
10138 | * page tables), using walk_addr(), when injecting PFs to L1. | |
10139 | */ | |
10140 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, | |
10141 | enable_ept ? vmcs12->page_fault_error_code_mask : 0); | |
10142 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, | |
10143 | enable_ept ? vmcs12->page_fault_error_code_match : 0); | |
10144 | ||
10145 | if (cpu_has_secondary_exec_ctrls()) { | |
f4124500 | 10146 | exec_control = vmx_secondary_exec_control(vmx); |
e2821620 | 10147 | |
fe3ef05c | 10148 | /* Take the following fields only from vmcs12 */ |
696dfd95 | 10149 | exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
b3a2a907 | 10150 | SECONDARY_EXEC_RDTSCP | |
696dfd95 | 10151 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
dfa169bb | 10152 | SECONDARY_EXEC_APIC_REGISTER_VIRT); |
fe3ef05c NHE |
10153 | if (nested_cpu_has(vmcs12, |
10154 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) | |
10155 | exec_control |= vmcs12->secondary_vm_exec_control; | |
10156 | ||
10157 | if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) { | |
fe3ef05c NHE |
10158 | /* |
10159 | * If translation failed, no matter: This feature asks | |
10160 | * to exit when accessing the given address, and if it | |
10161 | * can never be accessed, this feature won't do | |
10162 | * anything anyway. | |
10163 | */ | |
10164 | if (!vmx->nested.apic_access_page) | |
10165 | exec_control &= | |
10166 | ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
10167 | else | |
10168 | vmcs_write64(APIC_ACCESS_ADDR, | |
10169 | page_to_phys(vmx->nested.apic_access_page)); | |
f2b93280 | 10170 | } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) && |
35754c98 | 10171 | cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { |
ca3f257a JK |
10172 | exec_control |= |
10173 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
38b99173 | 10174 | kvm_vcpu_reload_apic_access_page(vcpu); |
fe3ef05c NHE |
10175 | } |
10176 | ||
608406e2 WV |
10177 | if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { |
10178 | vmcs_write64(EOI_EXIT_BITMAP0, | |
10179 | vmcs12->eoi_exit_bitmap0); | |
10180 | vmcs_write64(EOI_EXIT_BITMAP1, | |
10181 | vmcs12->eoi_exit_bitmap1); | |
10182 | vmcs_write64(EOI_EXIT_BITMAP2, | |
10183 | vmcs12->eoi_exit_bitmap2); | |
10184 | vmcs_write64(EOI_EXIT_BITMAP3, | |
10185 | vmcs12->eoi_exit_bitmap3); | |
10186 | vmcs_write16(GUEST_INTR_STATUS, | |
10187 | vmcs12->guest_intr_status); | |
10188 | } | |
10189 | ||
7ca29de2 | 10190 | nested_ept_enabled = (exec_control & SECONDARY_EXEC_ENABLE_EPT) != 0; |
fe3ef05c NHE |
10191 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
10192 | } | |
10193 | ||
10194 | ||
10195 | /* | |
10196 | * Set host-state according to L0's settings (vmcs12 is irrelevant here) | |
10197 | * Some constant fields are set here by vmx_set_constant_host_state(). | |
10198 | * Other fields are different per CPU, and will be set later when | |
10199 | * vmx_vcpu_load() is called, and when vmx_save_host_state() is called. | |
10200 | */ | |
a547c6db | 10201 | vmx_set_constant_host_state(vmx); |
fe3ef05c | 10202 | |
83bafef1 JM |
10203 | /* |
10204 | * Set the MSR load/store lists to match L0's settings. | |
10205 | */ | |
10206 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); | |
10207 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr); | |
10208 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host)); | |
10209 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr); | |
10210 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); | |
10211 | ||
fe3ef05c NHE |
10212 | /* |
10213 | * HOST_RSP is normally set correctly in vmx_vcpu_run() just before | |
10214 | * entry, but only if the current (host) sp changed from the value | |
10215 | * we wrote last (vmx->host_rsp). This cache is no longer relevant | |
10216 | * if we switch vmcs, and rather than hold a separate cache per vmcs, | |
10217 | * here we just force the write to happen on entry. | |
10218 | */ | |
10219 | vmx->host_rsp = 0; | |
10220 | ||
10221 | exec_control = vmx_exec_control(vmx); /* L0's desires */ | |
10222 | exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
10223 | exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
10224 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
10225 | exec_control |= vmcs12->cpu_based_vm_exec_control; | |
a7c0b07d WL |
10226 | |
10227 | if (exec_control & CPU_BASED_TPR_SHADOW) { | |
10228 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, | |
10229 | page_to_phys(vmx->nested.virtual_apic_page)); | |
10230 | vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold); | |
10231 | } | |
10232 | ||
3af18d9c | 10233 | if (cpu_has_vmx_msr_bitmap() && |
d048c098 RK |
10234 | exec_control & CPU_BASED_USE_MSR_BITMAPS && |
10235 | nested_vmx_merge_msr_bitmap(vcpu, vmcs12)) | |
10236 | ; /* MSR_BITMAP will be set by following vmx_set_efer. */ | |
10237 | else | |
3af18d9c WV |
10238 | exec_control &= ~CPU_BASED_USE_MSR_BITMAPS; |
10239 | ||
fe3ef05c | 10240 | /* |
3af18d9c | 10241 | * Merging of IO bitmap not currently supported. |
fe3ef05c NHE |
10242 | * Rather, exit every time. |
10243 | */ | |
fe3ef05c NHE |
10244 | exec_control &= ~CPU_BASED_USE_IO_BITMAPS; |
10245 | exec_control |= CPU_BASED_UNCOND_IO_EXITING; | |
10246 | ||
10247 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); | |
10248 | ||
10249 | /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the | |
10250 | * bitwise-or of what L1 wants to trap for L2, and what we want to | |
10251 | * trap. Note that CR0.TS also needs updating - we do this later. | |
10252 | */ | |
10253 | update_exception_bitmap(vcpu); | |
10254 | vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask; | |
10255 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
10256 | ||
8049d651 NHE |
10257 | /* L2->L1 exit controls are emulated - the hardware exit is to L0 so |
10258 | * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER | |
10259 | * bits are further modified by vmx_set_efer() below. | |
10260 | */ | |
f4124500 | 10261 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
8049d651 NHE |
10262 | |
10263 | /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are | |
10264 | * emulated by vmx_set_efer(), below. | |
10265 | */ | |
2961e876 | 10266 | vm_entry_controls_init(vmx, |
8049d651 NHE |
10267 | (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER & |
10268 | ~VM_ENTRY_IA32E_MODE) | | |
fe3ef05c NHE |
10269 | (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE)); |
10270 | ||
44811c02 | 10271 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) { |
fe3ef05c | 10272 | vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat); |
44811c02 JK |
10273 | vcpu->arch.pat = vmcs12->guest_ia32_pat; |
10274 | } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) | |
fe3ef05c NHE |
10275 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); |
10276 | ||
10277 | ||
10278 | set_cr4_guest_host_mask(vmx); | |
10279 | ||
36be0b9d PB |
10280 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) |
10281 | vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs); | |
10282 | ||
27fc51b2 NHE |
10283 | if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING) |
10284 | vmcs_write64(TSC_OFFSET, | |
ea26e4ec | 10285 | vcpu->arch.tsc_offset + vmcs12->tsc_offset); |
27fc51b2 | 10286 | else |
ea26e4ec | 10287 | vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); |
c95ba92a PF |
10288 | if (kvm_has_tsc_control) |
10289 | decache_tsc_multiplier(vmx); | |
fe3ef05c NHE |
10290 | |
10291 | if (enable_vpid) { | |
10292 | /* | |
5c614b35 WL |
10293 | * There is no direct mapping between vpid02 and vpid12, the |
10294 | * vpid02 is per-vCPU for L0 and reused while the value of | |
10295 | * vpid12 is changed w/ one invvpid during nested vmentry. | |
10296 | * The vpid12 is allocated by L1 for L2, so it will not | |
10297 | * influence global bitmap(for vpid01 and vpid02 allocation) | |
10298 | * even if spawn a lot of nested vCPUs. | |
fe3ef05c | 10299 | */ |
5c614b35 WL |
10300 | if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) { |
10301 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02); | |
10302 | if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) { | |
10303 | vmx->nested.last_vpid = vmcs12->virtual_processor_id; | |
10304 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02); | |
10305 | } | |
10306 | } else { | |
10307 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
10308 | vmx_flush_tlb(vcpu); | |
10309 | } | |
10310 | ||
fe3ef05c NHE |
10311 | } |
10312 | ||
155a97a3 NHE |
10313 | if (nested_cpu_has_ept(vmcs12)) { |
10314 | kvm_mmu_unload(vcpu); | |
10315 | nested_ept_init_mmu_context(vcpu); | |
10316 | } | |
10317 | ||
fe3ef05c NHE |
10318 | /* |
10319 | * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified | |
10320 | * TS bit (for lazy fpu) and bits which we consider mandatory enabled. | |
10321 | * The CR0_READ_SHADOW is what L2 should have expected to read given | |
10322 | * the specifications by L1; It's not enough to take | |
10323 | * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we | |
10324 | * have more bits than L1 expected. | |
10325 | */ | |
10326 | vmx_set_cr0(vcpu, vmcs12->guest_cr0); | |
10327 | vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); | |
10328 | ||
10329 | vmx_set_cr4(vcpu, vmcs12->guest_cr4); | |
10330 | vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12)); | |
10331 | ||
5a6a9748 DM |
10332 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) |
10333 | vcpu->arch.efer = vmcs12->guest_ia32_efer; | |
10334 | else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) | |
10335 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); | |
10336 | else | |
10337 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
10338 | /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */ | |
10339 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
10340 | ||
9ed38ffa LP |
10341 | /* Shadow page tables on either EPT or shadow page tables. */ |
10342 | if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_ept_enabled, | |
10343 | entry_failure_code)) | |
10344 | return 1; | |
7ca29de2 | 10345 | |
fe3ef05c NHE |
10346 | kvm_mmu_reset_context(vcpu); |
10347 | ||
feaf0c7d GN |
10348 | if (!enable_ept) |
10349 | vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested; | |
10350 | ||
3633cfc3 NHE |
10351 | /* |
10352 | * L1 may access the L2's PDPTR, so save them to construct vmcs12 | |
10353 | */ | |
10354 | if (enable_ept) { | |
10355 | vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0); | |
10356 | vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1); | |
10357 | vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2); | |
10358 | vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3); | |
10359 | } | |
10360 | ||
fe3ef05c NHE |
10361 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp); |
10362 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip); | |
ee146c1c | 10363 | return 0; |
fe3ef05c NHE |
10364 | } |
10365 | ||
cd232ad0 NHE |
10366 | /* |
10367 | * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1 | |
10368 | * for running an L2 nested guest. | |
10369 | */ | |
10370 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch) | |
10371 | { | |
10372 | struct vmcs12 *vmcs12; | |
10373 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10374 | int cpu; | |
10375 | struct loaded_vmcs *vmcs02; | |
384bb783 | 10376 | bool ia32e; |
ff651cb6 | 10377 | u32 msr_entry_idx; |
ee146c1c | 10378 | unsigned long exit_qualification; |
cd232ad0 | 10379 | |
eb277562 | 10380 | if (!nested_vmx_check_permission(vcpu)) |
cd232ad0 NHE |
10381 | return 1; |
10382 | ||
eb277562 KH |
10383 | if (!nested_vmx_check_vmcs12(vcpu)) |
10384 | goto out; | |
10385 | ||
cd232ad0 NHE |
10386 | vmcs12 = get_vmcs12(vcpu); |
10387 | ||
012f83cb AG |
10388 | if (enable_shadow_vmcs) |
10389 | copy_shadow_to_vmcs12(vmx); | |
10390 | ||
7c177938 NHE |
10391 | /* |
10392 | * The nested entry process starts with enforcing various prerequisites | |
10393 | * on vmcs12 as required by the Intel SDM, and act appropriately when | |
10394 | * they fail: As the SDM explains, some conditions should cause the | |
10395 | * instruction to fail, while others will cause the instruction to seem | |
10396 | * to succeed, but return an EXIT_REASON_INVALID_STATE. | |
10397 | * To speed up the normal (success) code path, we should avoid checking | |
10398 | * for misconfigurations which will anyway be caught by the processor | |
10399 | * when using the merged vmcs02. | |
10400 | */ | |
10401 | if (vmcs12->launch_state == launch) { | |
10402 | nested_vmx_failValid(vcpu, | |
10403 | launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS | |
10404 | : VMXERR_VMRESUME_NONLAUNCHED_VMCS); | |
eb277562 | 10405 | goto out; |
7c177938 NHE |
10406 | } |
10407 | ||
6dfacadd JK |
10408 | if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE && |
10409 | vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) { | |
26539bd0 | 10410 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); |
eb277562 | 10411 | goto out; |
26539bd0 PB |
10412 | } |
10413 | ||
3af18d9c | 10414 | if (!nested_get_vmcs12_pages(vcpu, vmcs12)) { |
7c177938 | 10415 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); |
eb277562 | 10416 | goto out; |
7c177938 NHE |
10417 | } |
10418 | ||
3af18d9c | 10419 | if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) { |
7c177938 | 10420 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); |
eb277562 | 10421 | goto out; |
7c177938 NHE |
10422 | } |
10423 | ||
f2b93280 WV |
10424 | if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) { |
10425 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
eb277562 | 10426 | goto out; |
f2b93280 WV |
10427 | } |
10428 | ||
e9ac033e EK |
10429 | if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) { |
10430 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
eb277562 | 10431 | goto out; |
e9ac033e EK |
10432 | } |
10433 | ||
7c177938 | 10434 | if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control, |
0115f9cb | 10435 | vmx->nested.nested_vmx_procbased_ctls_low, |
b9c237bb | 10436 | vmx->nested.nested_vmx_procbased_ctls_high) || |
7c177938 | 10437 | !vmx_control_verify(vmcs12->secondary_vm_exec_control, |
b9c237bb WV |
10438 | vmx->nested.nested_vmx_secondary_ctls_low, |
10439 | vmx->nested.nested_vmx_secondary_ctls_high) || | |
7c177938 | 10440 | !vmx_control_verify(vmcs12->pin_based_vm_exec_control, |
b9c237bb WV |
10441 | vmx->nested.nested_vmx_pinbased_ctls_low, |
10442 | vmx->nested.nested_vmx_pinbased_ctls_high) || | |
7c177938 | 10443 | !vmx_control_verify(vmcs12->vm_exit_controls, |
0115f9cb | 10444 | vmx->nested.nested_vmx_exit_ctls_low, |
b9c237bb | 10445 | vmx->nested.nested_vmx_exit_ctls_high) || |
7c177938 | 10446 | !vmx_control_verify(vmcs12->vm_entry_controls, |
0115f9cb | 10447 | vmx->nested.nested_vmx_entry_ctls_low, |
b9c237bb | 10448 | vmx->nested.nested_vmx_entry_ctls_high)) |
7c177938 NHE |
10449 | { |
10450 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
eb277562 | 10451 | goto out; |
7c177938 NHE |
10452 | } |
10453 | ||
3899152c DM |
10454 | if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) || |
10455 | !nested_host_cr4_valid(vcpu, vmcs12->host_cr4)) { | |
7c177938 NHE |
10456 | nested_vmx_failValid(vcpu, |
10457 | VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); | |
eb277562 | 10458 | goto out; |
7c177938 NHE |
10459 | } |
10460 | ||
3899152c DM |
10461 | if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) || |
10462 | !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4)) { | |
7c177938 NHE |
10463 | nested_vmx_entry_failure(vcpu, vmcs12, |
10464 | EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT); | |
eb277562 | 10465 | goto out; |
7c177938 NHE |
10466 | } |
10467 | if (vmcs12->vmcs_link_pointer != -1ull) { | |
10468 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10469 | EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR); | |
eb277562 | 10470 | goto out; |
7c177938 NHE |
10471 | } |
10472 | ||
384bb783 | 10473 | /* |
cb0c8cda | 10474 | * If the load IA32_EFER VM-entry control is 1, the following checks |
384bb783 JK |
10475 | * are performed on the field for the IA32_EFER MSR: |
10476 | * - Bits reserved in the IA32_EFER MSR must be 0. | |
10477 | * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of | |
10478 | * the IA-32e mode guest VM-exit control. It must also be identical | |
10479 | * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to | |
10480 | * CR0.PG) is 1. | |
10481 | */ | |
10482 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) { | |
10483 | ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0; | |
10484 | if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) || | |
10485 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) || | |
10486 | ((vmcs12->guest_cr0 & X86_CR0_PG) && | |
10487 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) { | |
10488 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10489 | EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT); | |
eb277562 | 10490 | goto out; |
384bb783 JK |
10491 | } |
10492 | } | |
10493 | ||
10494 | /* | |
10495 | * If the load IA32_EFER VM-exit control is 1, bits reserved in the | |
10496 | * IA32_EFER MSR must be 0 in the field for that register. In addition, | |
10497 | * the values of the LMA and LME bits in the field must each be that of | |
10498 | * the host address-space size VM-exit control. | |
10499 | */ | |
10500 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) { | |
10501 | ia32e = (vmcs12->vm_exit_controls & | |
10502 | VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0; | |
10503 | if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) || | |
10504 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) || | |
10505 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) { | |
10506 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10507 | EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT); | |
eb277562 | 10508 | goto out; |
384bb783 JK |
10509 | } |
10510 | } | |
10511 | ||
7c177938 NHE |
10512 | /* |
10513 | * We're finally done with prerequisite checking, and can start with | |
10514 | * the nested entry. | |
10515 | */ | |
10516 | ||
cd232ad0 NHE |
10517 | vmcs02 = nested_get_current_vmcs02(vmx); |
10518 | if (!vmcs02) | |
10519 | return -ENOMEM; | |
10520 | ||
6affcbed KH |
10521 | /* |
10522 | * After this point, the trap flag no longer triggers a singlestep trap | |
10523 | * on the vm entry instructions. Don't call | |
10524 | * kvm_skip_emulated_instruction. | |
10525 | */ | |
eb277562 | 10526 | skip_emulated_instruction(vcpu); |
cd232ad0 NHE |
10527 | enter_guest_mode(vcpu); |
10528 | ||
2996fca0 JK |
10529 | if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) |
10530 | vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
10531 | ||
cd232ad0 NHE |
10532 | cpu = get_cpu(); |
10533 | vmx->loaded_vmcs = vmcs02; | |
10534 | vmx_vcpu_put(vcpu); | |
10535 | vmx_vcpu_load(vcpu, cpu); | |
10536 | vcpu->cpu = cpu; | |
10537 | put_cpu(); | |
10538 | ||
36c3cc42 JK |
10539 | vmx_segment_cache_clear(vmx); |
10540 | ||
ee146c1c LP |
10541 | if (prepare_vmcs02(vcpu, vmcs12, &exit_qualification)) { |
10542 | leave_guest_mode(vcpu); | |
10543 | vmx_load_vmcs01(vcpu); | |
10544 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10545 | EXIT_REASON_INVALID_STATE, exit_qualification); | |
10546 | return 1; | |
10547 | } | |
cd232ad0 | 10548 | |
ff651cb6 WV |
10549 | msr_entry_idx = nested_vmx_load_msr(vcpu, |
10550 | vmcs12->vm_entry_msr_load_addr, | |
10551 | vmcs12->vm_entry_msr_load_count); | |
10552 | if (msr_entry_idx) { | |
10553 | leave_guest_mode(vcpu); | |
10554 | vmx_load_vmcs01(vcpu); | |
10555 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10556 | EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx); | |
10557 | return 1; | |
10558 | } | |
10559 | ||
10560 | vmcs12->launch_state = 1; | |
10561 | ||
6dfacadd | 10562 | if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) |
5cb56059 | 10563 | return kvm_vcpu_halt(vcpu); |
6dfacadd | 10564 | |
7af40ad3 JK |
10565 | vmx->nested.nested_run_pending = 1; |
10566 | ||
cd232ad0 NHE |
10567 | /* |
10568 | * Note no nested_vmx_succeed or nested_vmx_fail here. At this point | |
10569 | * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet | |
10570 | * returned as far as L1 is concerned. It will only return (and set | |
10571 | * the success flag) when L2 exits (see nested_vmx_vmexit()). | |
10572 | */ | |
10573 | return 1; | |
eb277562 KH |
10574 | |
10575 | out: | |
6affcbed | 10576 | return kvm_skip_emulated_instruction(vcpu); |
cd232ad0 NHE |
10577 | } |
10578 | ||
4704d0be NHE |
10579 | /* |
10580 | * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date | |
10581 | * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK). | |
10582 | * This function returns the new value we should put in vmcs12.guest_cr0. | |
10583 | * It's not enough to just return the vmcs02 GUEST_CR0. Rather, | |
10584 | * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now | |
10585 | * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0 | |
10586 | * didn't trap the bit, because if L1 did, so would L0). | |
10587 | * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have | |
10588 | * been modified by L2, and L1 knows it. So just leave the old value of | |
10589 | * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0 | |
10590 | * isn't relevant, because if L0 traps this bit it can set it to anything. | |
10591 | * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have | |
10592 | * changed these bits, and therefore they need to be updated, but L0 | |
10593 | * didn't necessarily allow them to be changed in GUEST_CR0 - and rather | |
10594 | * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there. | |
10595 | */ | |
10596 | static inline unsigned long | |
10597 | vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
10598 | { | |
10599 | return | |
10600 | /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) | | |
10601 | /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) | | |
10602 | /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask | | |
10603 | vcpu->arch.cr0_guest_owned_bits)); | |
10604 | } | |
10605 | ||
10606 | static inline unsigned long | |
10607 | vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
10608 | { | |
10609 | return | |
10610 | /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) | | |
10611 | /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) | | |
10612 | /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask | | |
10613 | vcpu->arch.cr4_guest_owned_bits)); | |
10614 | } | |
10615 | ||
5f3d5799 JK |
10616 | static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu, |
10617 | struct vmcs12 *vmcs12) | |
10618 | { | |
10619 | u32 idt_vectoring; | |
10620 | unsigned int nr; | |
10621 | ||
851eb667 | 10622 | if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) { |
5f3d5799 JK |
10623 | nr = vcpu->arch.exception.nr; |
10624 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
10625 | ||
10626 | if (kvm_exception_is_soft(nr)) { | |
10627 | vmcs12->vm_exit_instruction_len = | |
10628 | vcpu->arch.event_exit_inst_len; | |
10629 | idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION; | |
10630 | } else | |
10631 | idt_vectoring |= INTR_TYPE_HARD_EXCEPTION; | |
10632 | ||
10633 | if (vcpu->arch.exception.has_error_code) { | |
10634 | idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK; | |
10635 | vmcs12->idt_vectoring_error_code = | |
10636 | vcpu->arch.exception.error_code; | |
10637 | } | |
10638 | ||
10639 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
cd2633c5 | 10640 | } else if (vcpu->arch.nmi_injected) { |
5f3d5799 JK |
10641 | vmcs12->idt_vectoring_info_field = |
10642 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR; | |
10643 | } else if (vcpu->arch.interrupt.pending) { | |
10644 | nr = vcpu->arch.interrupt.nr; | |
10645 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
10646 | ||
10647 | if (vcpu->arch.interrupt.soft) { | |
10648 | idt_vectoring |= INTR_TYPE_SOFT_INTR; | |
10649 | vmcs12->vm_entry_instruction_len = | |
10650 | vcpu->arch.event_exit_inst_len; | |
10651 | } else | |
10652 | idt_vectoring |= INTR_TYPE_EXT_INTR; | |
10653 | ||
10654 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
10655 | } | |
10656 | } | |
10657 | ||
b6b8a145 JK |
10658 | static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr) |
10659 | { | |
10660 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10661 | ||
f4124500 JK |
10662 | if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) && |
10663 | vmx->nested.preemption_timer_expired) { | |
10664 | if (vmx->nested.nested_run_pending) | |
10665 | return -EBUSY; | |
10666 | nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0); | |
10667 | return 0; | |
10668 | } | |
10669 | ||
b6b8a145 | 10670 | if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) { |
220c5672 JK |
10671 | if (vmx->nested.nested_run_pending || |
10672 | vcpu->arch.interrupt.pending) | |
b6b8a145 JK |
10673 | return -EBUSY; |
10674 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, | |
10675 | NMI_VECTOR | INTR_TYPE_NMI_INTR | | |
10676 | INTR_INFO_VALID_MASK, 0); | |
10677 | /* | |
10678 | * The NMI-triggered VM exit counts as injection: | |
10679 | * clear this one and block further NMIs. | |
10680 | */ | |
10681 | vcpu->arch.nmi_pending = 0; | |
10682 | vmx_set_nmi_mask(vcpu, true); | |
10683 | return 0; | |
10684 | } | |
10685 | ||
10686 | if ((kvm_cpu_has_interrupt(vcpu) || external_intr) && | |
10687 | nested_exit_on_intr(vcpu)) { | |
10688 | if (vmx->nested.nested_run_pending) | |
10689 | return -EBUSY; | |
10690 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0); | |
705699a1 | 10691 | return 0; |
b6b8a145 JK |
10692 | } |
10693 | ||
705699a1 | 10694 | return vmx_complete_nested_posted_interrupt(vcpu); |
b6b8a145 JK |
10695 | } |
10696 | ||
f4124500 JK |
10697 | static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu) |
10698 | { | |
10699 | ktime_t remaining = | |
10700 | hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer); | |
10701 | u64 value; | |
10702 | ||
10703 | if (ktime_to_ns(remaining) <= 0) | |
10704 | return 0; | |
10705 | ||
10706 | value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz; | |
10707 | do_div(value, 1000000); | |
10708 | return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
10709 | } | |
10710 | ||
4704d0be NHE |
10711 | /* |
10712 | * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits | |
10713 | * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12), | |
10714 | * and this function updates it to reflect the changes to the guest state while | |
10715 | * L2 was running (and perhaps made some exits which were handled directly by L0 | |
10716 | * without going back to L1), and to reflect the exit reason. | |
10717 | * Note that we do not have to copy here all VMCS fields, just those that | |
10718 | * could have changed by the L2 guest or the exit - i.e., the guest-state and | |
10719 | * exit-information fields only. Other fields are modified by L1 with VMWRITE, | |
10720 | * which already writes to vmcs12 directly. | |
10721 | */ | |
533558bc JK |
10722 | static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, |
10723 | u32 exit_reason, u32 exit_intr_info, | |
10724 | unsigned long exit_qualification) | |
4704d0be NHE |
10725 | { |
10726 | /* update guest state fields: */ | |
10727 | vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12); | |
10728 | vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12); | |
10729 | ||
4704d0be NHE |
10730 | vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); |
10731 | vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP); | |
10732 | vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS); | |
10733 | ||
10734 | vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR); | |
10735 | vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR); | |
10736 | vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR); | |
10737 | vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR); | |
10738 | vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR); | |
10739 | vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR); | |
10740 | vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR); | |
10741 | vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR); | |
10742 | vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT); | |
10743 | vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT); | |
10744 | vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT); | |
10745 | vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT); | |
10746 | vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT); | |
10747 | vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT); | |
10748 | vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT); | |
10749 | vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT); | |
10750 | vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
10751 | vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
10752 | vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES); | |
10753 | vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES); | |
10754 | vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES); | |
10755 | vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES); | |
10756 | vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES); | |
10757 | vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES); | |
10758 | vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES); | |
10759 | vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES); | |
10760 | vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE); | |
10761 | vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE); | |
10762 | vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE); | |
10763 | vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE); | |
10764 | vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE); | |
10765 | vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE); | |
10766 | vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE); | |
10767 | vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE); | |
10768 | vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE); | |
10769 | vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE); | |
10770 | ||
4704d0be NHE |
10771 | vmcs12->guest_interruptibility_info = |
10772 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
10773 | vmcs12->guest_pending_dbg_exceptions = | |
10774 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS); | |
3edf1e69 JK |
10775 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) |
10776 | vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT; | |
10777 | else | |
10778 | vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE; | |
4704d0be | 10779 | |
f4124500 JK |
10780 | if (nested_cpu_has_preemption_timer(vmcs12)) { |
10781 | if (vmcs12->vm_exit_controls & | |
10782 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER) | |
10783 | vmcs12->vmx_preemption_timer_value = | |
10784 | vmx_get_preemption_timer_value(vcpu); | |
10785 | hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer); | |
10786 | } | |
7854cbca | 10787 | |
3633cfc3 NHE |
10788 | /* |
10789 | * In some cases (usually, nested EPT), L2 is allowed to change its | |
10790 | * own CR3 without exiting. If it has changed it, we must keep it. | |
10791 | * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined | |
10792 | * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12. | |
10793 | * | |
10794 | * Additionally, restore L2's PDPTR to vmcs12. | |
10795 | */ | |
10796 | if (enable_ept) { | |
f3531054 | 10797 | vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3); |
3633cfc3 NHE |
10798 | vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0); |
10799 | vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1); | |
10800 | vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2); | |
10801 | vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3); | |
10802 | } | |
10803 | ||
119a9c01 JD |
10804 | if (nested_cpu_has_ept(vmcs12)) |
10805 | vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS); | |
10806 | ||
608406e2 WV |
10807 | if (nested_cpu_has_vid(vmcs12)) |
10808 | vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS); | |
10809 | ||
c18911a2 JK |
10810 | vmcs12->vm_entry_controls = |
10811 | (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) | | |
2961e876 | 10812 | (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE); |
c18911a2 | 10813 | |
2996fca0 JK |
10814 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) { |
10815 | kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7); | |
10816 | vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
10817 | } | |
10818 | ||
4704d0be NHE |
10819 | /* TODO: These cannot have changed unless we have MSR bitmaps and |
10820 | * the relevant bit asks not to trap the change */ | |
b8c07d55 | 10821 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) |
4704d0be | 10822 | vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT); |
10ba54a5 JK |
10823 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER) |
10824 | vmcs12->guest_ia32_efer = vcpu->arch.efer; | |
4704d0be NHE |
10825 | vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS); |
10826 | vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP); | |
10827 | vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP); | |
a87036ad | 10828 | if (kvm_mpx_supported()) |
36be0b9d | 10829 | vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS); |
81dc01f7 WL |
10830 | if (nested_cpu_has_xsaves(vmcs12)) |
10831 | vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP); | |
4704d0be NHE |
10832 | |
10833 | /* update exit information fields: */ | |
10834 | ||
533558bc JK |
10835 | vmcs12->vm_exit_reason = exit_reason; |
10836 | vmcs12->exit_qualification = exit_qualification; | |
4704d0be | 10837 | |
533558bc | 10838 | vmcs12->vm_exit_intr_info = exit_intr_info; |
c0d1c770 JK |
10839 | if ((vmcs12->vm_exit_intr_info & |
10840 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) == | |
10841 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) | |
10842 | vmcs12->vm_exit_intr_error_code = | |
10843 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE); | |
5f3d5799 | 10844 | vmcs12->idt_vectoring_info_field = 0; |
4704d0be NHE |
10845 | vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
10846 | vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
10847 | ||
5f3d5799 JK |
10848 | if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) { |
10849 | /* vm_entry_intr_info_field is cleared on exit. Emulate this | |
10850 | * instead of reading the real value. */ | |
4704d0be | 10851 | vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK; |
5f3d5799 JK |
10852 | |
10853 | /* | |
10854 | * Transfer the event that L0 or L1 may wanted to inject into | |
10855 | * L2 to IDT_VECTORING_INFO_FIELD. | |
10856 | */ | |
10857 | vmcs12_save_pending_event(vcpu, vmcs12); | |
10858 | } | |
10859 | ||
10860 | /* | |
10861 | * Drop what we picked up for L2 via vmx_complete_interrupts. It is | |
10862 | * preserved above and would only end up incorrectly in L1. | |
10863 | */ | |
10864 | vcpu->arch.nmi_injected = false; | |
10865 | kvm_clear_exception_queue(vcpu); | |
10866 | kvm_clear_interrupt_queue(vcpu); | |
4704d0be NHE |
10867 | } |
10868 | ||
10869 | /* | |
10870 | * A part of what we need to when the nested L2 guest exits and we want to | |
10871 | * run its L1 parent, is to reset L1's guest state to the host state specified | |
10872 | * in vmcs12. | |
10873 | * This function is to be called not only on normal nested exit, but also on | |
10874 | * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry | |
10875 | * Failures During or After Loading Guest State"). | |
10876 | * This function should be called when the active VMCS is L1's (vmcs01). | |
10877 | */ | |
733568f9 JK |
10878 | static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, |
10879 | struct vmcs12 *vmcs12) | |
4704d0be | 10880 | { |
21feb4eb ACL |
10881 | struct kvm_segment seg; |
10882 | ||
4704d0be NHE |
10883 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) |
10884 | vcpu->arch.efer = vmcs12->host_ia32_efer; | |
d1fa0352 | 10885 | else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) |
4704d0be NHE |
10886 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); |
10887 | else | |
10888 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
10889 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
10890 | ||
10891 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp); | |
10892 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip); | |
1adfa76a | 10893 | vmx_set_rflags(vcpu, X86_EFLAGS_FIXED); |
4704d0be NHE |
10894 | /* |
10895 | * Note that calling vmx_set_cr0 is important, even if cr0 hasn't | |
10896 | * actually changed, because it depends on the current state of | |
10897 | * fpu_active (which may have changed). | |
10898 | * Note that vmx_set_cr0 refers to efer set above. | |
10899 | */ | |
9e3e4dbf | 10900 | vmx_set_cr0(vcpu, vmcs12->host_cr0); |
4704d0be NHE |
10901 | /* |
10902 | * If we did fpu_activate()/fpu_deactivate() during L2's run, we need | |
10903 | * to apply the same changes to L1's vmcs. We just set cr0 correctly, | |
10904 | * but we also need to update cr0_guest_host_mask and exception_bitmap. | |
10905 | */ | |
10906 | update_exception_bitmap(vcpu); | |
10907 | vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0); | |
10908 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
10909 | ||
10910 | /* | |
10911 | * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01 | |
10912 | * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask(); | |
10913 | */ | |
10914 | vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK); | |
10915 | kvm_set_cr4(vcpu, vmcs12->host_cr4); | |
10916 | ||
29bf08f1 | 10917 | nested_ept_uninit_mmu_context(vcpu); |
155a97a3 | 10918 | |
4704d0be NHE |
10919 | kvm_set_cr3(vcpu, vmcs12->host_cr3); |
10920 | kvm_mmu_reset_context(vcpu); | |
10921 | ||
feaf0c7d GN |
10922 | if (!enable_ept) |
10923 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; | |
10924 | ||
4704d0be NHE |
10925 | if (enable_vpid) { |
10926 | /* | |
10927 | * Trivially support vpid by letting L2s share their parent | |
10928 | * L1's vpid. TODO: move to a more elaborate solution, giving | |
10929 | * each L2 its own vpid and exposing the vpid feature to L1. | |
10930 | */ | |
10931 | vmx_flush_tlb(vcpu); | |
10932 | } | |
10933 | ||
10934 | ||
10935 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs); | |
10936 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp); | |
10937 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip); | |
10938 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base); | |
10939 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base); | |
4704d0be | 10940 | |
36be0b9d PB |
10941 | /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */ |
10942 | if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS) | |
10943 | vmcs_write64(GUEST_BNDCFGS, 0); | |
10944 | ||
44811c02 | 10945 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) { |
4704d0be | 10946 | vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat); |
44811c02 JK |
10947 | vcpu->arch.pat = vmcs12->host_ia32_pat; |
10948 | } | |
4704d0be NHE |
10949 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) |
10950 | vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL, | |
10951 | vmcs12->host_ia32_perf_global_ctrl); | |
503cd0c5 | 10952 | |
21feb4eb ACL |
10953 | /* Set L1 segment info according to Intel SDM |
10954 | 27.5.2 Loading Host Segment and Descriptor-Table Registers */ | |
10955 | seg = (struct kvm_segment) { | |
10956 | .base = 0, | |
10957 | .limit = 0xFFFFFFFF, | |
10958 | .selector = vmcs12->host_cs_selector, | |
10959 | .type = 11, | |
10960 | .present = 1, | |
10961 | .s = 1, | |
10962 | .g = 1 | |
10963 | }; | |
10964 | if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) | |
10965 | seg.l = 1; | |
10966 | else | |
10967 | seg.db = 1; | |
10968 | vmx_set_segment(vcpu, &seg, VCPU_SREG_CS); | |
10969 | seg = (struct kvm_segment) { | |
10970 | .base = 0, | |
10971 | .limit = 0xFFFFFFFF, | |
10972 | .type = 3, | |
10973 | .present = 1, | |
10974 | .s = 1, | |
10975 | .db = 1, | |
10976 | .g = 1 | |
10977 | }; | |
10978 | seg.selector = vmcs12->host_ds_selector; | |
10979 | vmx_set_segment(vcpu, &seg, VCPU_SREG_DS); | |
10980 | seg.selector = vmcs12->host_es_selector; | |
10981 | vmx_set_segment(vcpu, &seg, VCPU_SREG_ES); | |
10982 | seg.selector = vmcs12->host_ss_selector; | |
10983 | vmx_set_segment(vcpu, &seg, VCPU_SREG_SS); | |
10984 | seg.selector = vmcs12->host_fs_selector; | |
10985 | seg.base = vmcs12->host_fs_base; | |
10986 | vmx_set_segment(vcpu, &seg, VCPU_SREG_FS); | |
10987 | seg.selector = vmcs12->host_gs_selector; | |
10988 | seg.base = vmcs12->host_gs_base; | |
10989 | vmx_set_segment(vcpu, &seg, VCPU_SREG_GS); | |
10990 | seg = (struct kvm_segment) { | |
205befd9 | 10991 | .base = vmcs12->host_tr_base, |
21feb4eb ACL |
10992 | .limit = 0x67, |
10993 | .selector = vmcs12->host_tr_selector, | |
10994 | .type = 11, | |
10995 | .present = 1 | |
10996 | }; | |
10997 | vmx_set_segment(vcpu, &seg, VCPU_SREG_TR); | |
10998 | ||
503cd0c5 JK |
10999 | kvm_set_dr(vcpu, 7, 0x400); |
11000 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
ff651cb6 | 11001 | |
3af18d9c WV |
11002 | if (cpu_has_vmx_msr_bitmap()) |
11003 | vmx_set_msr_bitmap(vcpu); | |
11004 | ||
ff651cb6 WV |
11005 | if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr, |
11006 | vmcs12->vm_exit_msr_load_count)) | |
11007 | nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL); | |
4704d0be NHE |
11008 | } |
11009 | ||
11010 | /* | |
11011 | * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1 | |
11012 | * and modify vmcs12 to make it see what it would expect to see there if | |
11013 | * L2 was its real guest. Must only be called when in L2 (is_guest_mode()) | |
11014 | */ | |
533558bc JK |
11015 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
11016 | u32 exit_intr_info, | |
11017 | unsigned long exit_qualification) | |
4704d0be NHE |
11018 | { |
11019 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4704d0be | 11020 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
cf3215d9 | 11021 | u32 vm_inst_error = 0; |
4704d0be | 11022 | |
5f3d5799 JK |
11023 | /* trying to cancel vmlaunch/vmresume is a bug */ |
11024 | WARN_ON_ONCE(vmx->nested.nested_run_pending); | |
11025 | ||
4704d0be | 11026 | leave_guest_mode(vcpu); |
533558bc JK |
11027 | prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info, |
11028 | exit_qualification); | |
4704d0be | 11029 | |
ff651cb6 WV |
11030 | if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr, |
11031 | vmcs12->vm_exit_msr_store_count)) | |
11032 | nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL); | |
11033 | ||
cf3215d9 JM |
11034 | if (unlikely(vmx->fail)) |
11035 | vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR); | |
11036 | ||
f3380ca5 WL |
11037 | vmx_load_vmcs01(vcpu); |
11038 | ||
77b0f5d6 BD |
11039 | if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) |
11040 | && nested_exit_intr_ack_set(vcpu)) { | |
11041 | int irq = kvm_cpu_get_interrupt(vcpu); | |
11042 | WARN_ON(irq < 0); | |
11043 | vmcs12->vm_exit_intr_info = irq | | |
11044 | INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR; | |
11045 | } | |
11046 | ||
542060ea JK |
11047 | trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason, |
11048 | vmcs12->exit_qualification, | |
11049 | vmcs12->idt_vectoring_info_field, | |
11050 | vmcs12->vm_exit_intr_info, | |
11051 | vmcs12->vm_exit_intr_error_code, | |
11052 | KVM_ISA_VMX); | |
4704d0be | 11053 | |
8391ce44 PB |
11054 | vm_entry_controls_reset_shadow(vmx); |
11055 | vm_exit_controls_reset_shadow(vmx); | |
36c3cc42 JK |
11056 | vmx_segment_cache_clear(vmx); |
11057 | ||
4704d0be NHE |
11058 | /* if no vmcs02 cache requested, remove the one we used */ |
11059 | if (VMCS02_POOL_SIZE == 0) | |
11060 | nested_free_vmcs02(vmx, vmx->nested.current_vmptr); | |
11061 | ||
11062 | load_vmcs12_host_state(vcpu, vmcs12); | |
11063 | ||
9314006d | 11064 | /* Update any VMCS fields that might have changed while L2 ran */ |
83bafef1 JM |
11065 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr); |
11066 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr); | |
ea26e4ec | 11067 | vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); |
9314006d PB |
11068 | if (vmx->hv_deadline_tsc == -1) |
11069 | vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL, | |
11070 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
11071 | else | |
11072 | vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL, | |
11073 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
c95ba92a PF |
11074 | if (kvm_has_tsc_control) |
11075 | decache_tsc_multiplier(vmx); | |
4704d0be | 11076 | |
dccbfcf5 RK |
11077 | if (vmx->nested.change_vmcs01_virtual_x2apic_mode) { |
11078 | vmx->nested.change_vmcs01_virtual_x2apic_mode = false; | |
11079 | vmx_set_virtual_x2apic_mode(vcpu, | |
11080 | vcpu->arch.apic_base & X2APIC_ENABLE); | |
11081 | } | |
4704d0be NHE |
11082 | |
11083 | /* This is needed for same reason as it was needed in prepare_vmcs02 */ | |
11084 | vmx->host_rsp = 0; | |
11085 | ||
11086 | /* Unpin physical memory we referred to in vmcs02 */ | |
11087 | if (vmx->nested.apic_access_page) { | |
11088 | nested_release_page(vmx->nested.apic_access_page); | |
48d89b92 | 11089 | vmx->nested.apic_access_page = NULL; |
4704d0be | 11090 | } |
a7c0b07d WL |
11091 | if (vmx->nested.virtual_apic_page) { |
11092 | nested_release_page(vmx->nested.virtual_apic_page); | |
48d89b92 | 11093 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 11094 | } |
705699a1 WV |
11095 | if (vmx->nested.pi_desc_page) { |
11096 | kunmap(vmx->nested.pi_desc_page); | |
11097 | nested_release_page(vmx->nested.pi_desc_page); | |
11098 | vmx->nested.pi_desc_page = NULL; | |
11099 | vmx->nested.pi_desc = NULL; | |
11100 | } | |
4704d0be | 11101 | |
38b99173 TC |
11102 | /* |
11103 | * We are now running in L2, mmu_notifier will force to reload the | |
11104 | * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1. | |
11105 | */ | |
c83b6d15 | 11106 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
38b99173 | 11107 | |
4704d0be NHE |
11108 | /* |
11109 | * Exiting from L2 to L1, we're now back to L1 which thinks it just | |
11110 | * finished a VMLAUNCH or VMRESUME instruction, so we need to set the | |
11111 | * success or failure flag accordingly. | |
11112 | */ | |
11113 | if (unlikely(vmx->fail)) { | |
11114 | vmx->fail = 0; | |
cf3215d9 | 11115 | nested_vmx_failValid(vcpu, vm_inst_error); |
4704d0be NHE |
11116 | } else |
11117 | nested_vmx_succeed(vcpu); | |
012f83cb AG |
11118 | if (enable_shadow_vmcs) |
11119 | vmx->nested.sync_shadow_vmcs = true; | |
b6b8a145 JK |
11120 | |
11121 | /* in case we halted in L2 */ | |
11122 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
4704d0be NHE |
11123 | } |
11124 | ||
42124925 JK |
11125 | /* |
11126 | * Forcibly leave nested mode in order to be able to reset the VCPU later on. | |
11127 | */ | |
11128 | static void vmx_leave_nested(struct kvm_vcpu *vcpu) | |
11129 | { | |
11130 | if (is_guest_mode(vcpu)) | |
533558bc | 11131 | nested_vmx_vmexit(vcpu, -1, 0, 0); |
42124925 JK |
11132 | free_nested(to_vmx(vcpu)); |
11133 | } | |
11134 | ||
7c177938 NHE |
11135 | /* |
11136 | * L1's failure to enter L2 is a subset of a normal exit, as explained in | |
11137 | * 23.7 "VM-entry failures during or after loading guest state" (this also | |
11138 | * lists the acceptable exit-reason and exit-qualification parameters). | |
11139 | * It should only be called before L2 actually succeeded to run, and when | |
11140 | * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss). | |
11141 | */ | |
11142 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, | |
11143 | struct vmcs12 *vmcs12, | |
11144 | u32 reason, unsigned long qualification) | |
11145 | { | |
11146 | load_vmcs12_host_state(vcpu, vmcs12); | |
11147 | vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY; | |
11148 | vmcs12->exit_qualification = qualification; | |
11149 | nested_vmx_succeed(vcpu); | |
012f83cb AG |
11150 | if (enable_shadow_vmcs) |
11151 | to_vmx(vcpu)->nested.sync_shadow_vmcs = true; | |
7c177938 NHE |
11152 | } |
11153 | ||
8a76d7f2 JR |
11154 | static int vmx_check_intercept(struct kvm_vcpu *vcpu, |
11155 | struct x86_instruction_info *info, | |
11156 | enum x86_intercept_stage stage) | |
11157 | { | |
11158 | return X86EMUL_CONTINUE; | |
11159 | } | |
11160 | ||
64672c95 YJ |
11161 | #ifdef CONFIG_X86_64 |
11162 | /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ | |
11163 | static inline int u64_shl_div_u64(u64 a, unsigned int shift, | |
11164 | u64 divisor, u64 *result) | |
11165 | { | |
11166 | u64 low = a << shift, high = a >> (64 - shift); | |
11167 | ||
11168 | /* To avoid the overflow on divq */ | |
11169 | if (high >= divisor) | |
11170 | return 1; | |
11171 | ||
11172 | /* Low hold the result, high hold rem which is discarded */ | |
11173 | asm("divq %2\n\t" : "=a" (low), "=d" (high) : | |
11174 | "rm" (divisor), "0" (low), "1" (high)); | |
11175 | *result = low; | |
11176 | ||
11177 | return 0; | |
11178 | } | |
11179 | ||
11180 | static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc) | |
11181 | { | |
11182 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9175d2e9 PB |
11183 | u64 tscl = rdtsc(); |
11184 | u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); | |
11185 | u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; | |
64672c95 YJ |
11186 | |
11187 | /* Convert to host delta tsc if tsc scaling is enabled */ | |
11188 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && | |
11189 | u64_shl_div_u64(delta_tsc, | |
11190 | kvm_tsc_scaling_ratio_frac_bits, | |
11191 | vcpu->arch.tsc_scaling_ratio, | |
11192 | &delta_tsc)) | |
11193 | return -ERANGE; | |
11194 | ||
11195 | /* | |
11196 | * If the delta tsc can't fit in the 32 bit after the multi shift, | |
11197 | * we can't use the preemption timer. | |
11198 | * It's possible that it fits on later vmentries, but checking | |
11199 | * on every vmentry is costly so we just use an hrtimer. | |
11200 | */ | |
11201 | if (delta_tsc >> (cpu_preemption_timer_multi + 32)) | |
11202 | return -ERANGE; | |
11203 | ||
11204 | vmx->hv_deadline_tsc = tscl + delta_tsc; | |
11205 | vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL, | |
11206 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
11207 | return 0; | |
11208 | } | |
11209 | ||
11210 | static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) | |
11211 | { | |
11212 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
11213 | vmx->hv_deadline_tsc = -1; | |
11214 | vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL, | |
11215 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
11216 | } | |
11217 | #endif | |
11218 | ||
48d89b92 | 11219 | static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) |
ae97a3b8 | 11220 | { |
b4a2d31d RK |
11221 | if (ple_gap) |
11222 | shrink_ple_window(vcpu); | |
ae97a3b8 RK |
11223 | } |
11224 | ||
843e4330 KH |
11225 | static void vmx_slot_enable_log_dirty(struct kvm *kvm, |
11226 | struct kvm_memory_slot *slot) | |
11227 | { | |
11228 | kvm_mmu_slot_leaf_clear_dirty(kvm, slot); | |
11229 | kvm_mmu_slot_largepage_remove_write_access(kvm, slot); | |
11230 | } | |
11231 | ||
11232 | static void vmx_slot_disable_log_dirty(struct kvm *kvm, | |
11233 | struct kvm_memory_slot *slot) | |
11234 | { | |
11235 | kvm_mmu_slot_set_dirty(kvm, slot); | |
11236 | } | |
11237 | ||
11238 | static void vmx_flush_log_dirty(struct kvm *kvm) | |
11239 | { | |
11240 | kvm_flush_pml_buffers(kvm); | |
11241 | } | |
11242 | ||
11243 | static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, | |
11244 | struct kvm_memory_slot *memslot, | |
11245 | gfn_t offset, unsigned long mask) | |
11246 | { | |
11247 | kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); | |
11248 | } | |
11249 | ||
bf9f6ac8 FW |
11250 | /* |
11251 | * This routine does the following things for vCPU which is going | |
11252 | * to be blocked if VT-d PI is enabled. | |
11253 | * - Store the vCPU to the wakeup list, so when interrupts happen | |
11254 | * we can find the right vCPU to wake up. | |
11255 | * - Change the Posted-interrupt descriptor as below: | |
11256 | * 'NDST' <-- vcpu->pre_pcpu | |
11257 | * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR | |
11258 | * - If 'ON' is set during this process, which means at least one | |
11259 | * interrupt is posted for this vCPU, we cannot block it, in | |
11260 | * this case, return 1, otherwise, return 0. | |
11261 | * | |
11262 | */ | |
bc22512b | 11263 | static int pi_pre_block(struct kvm_vcpu *vcpu) |
bf9f6ac8 FW |
11264 | { |
11265 | unsigned long flags; | |
11266 | unsigned int dest; | |
11267 | struct pi_desc old, new; | |
11268 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
11269 | ||
11270 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
11271 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
11272 | !kvm_vcpu_apicv_active(vcpu)) | |
bf9f6ac8 FW |
11273 | return 0; |
11274 | ||
11275 | vcpu->pre_pcpu = vcpu->cpu; | |
11276 | spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock, | |
11277 | vcpu->pre_pcpu), flags); | |
11278 | list_add_tail(&vcpu->blocked_vcpu_list, | |
11279 | &per_cpu(blocked_vcpu_on_cpu, | |
11280 | vcpu->pre_pcpu)); | |
11281 | spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock, | |
11282 | vcpu->pre_pcpu), flags); | |
11283 | ||
11284 | do { | |
11285 | old.control = new.control = pi_desc->control; | |
11286 | ||
11287 | /* | |
11288 | * We should not block the vCPU if | |
11289 | * an interrupt is posted for it. | |
11290 | */ | |
11291 | if (pi_test_on(pi_desc) == 1) { | |
11292 | spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock, | |
11293 | vcpu->pre_pcpu), flags); | |
11294 | list_del(&vcpu->blocked_vcpu_list); | |
11295 | spin_unlock_irqrestore( | |
11296 | &per_cpu(blocked_vcpu_on_cpu_lock, | |
11297 | vcpu->pre_pcpu), flags); | |
11298 | vcpu->pre_pcpu = -1; | |
11299 | ||
11300 | return 1; | |
11301 | } | |
11302 | ||
11303 | WARN((pi_desc->sn == 1), | |
11304 | "Warning: SN field of posted-interrupts " | |
11305 | "is set before blocking\n"); | |
11306 | ||
11307 | /* | |
11308 | * Since vCPU can be preempted during this process, | |
11309 | * vcpu->cpu could be different with pre_pcpu, we | |
11310 | * need to set pre_pcpu as the destination of wakeup | |
11311 | * notification event, then we can find the right vCPU | |
11312 | * to wakeup in wakeup handler if interrupts happen | |
11313 | * when the vCPU is in blocked state. | |
11314 | */ | |
11315 | dest = cpu_physical_id(vcpu->pre_pcpu); | |
11316 | ||
11317 | if (x2apic_enabled()) | |
11318 | new.ndst = dest; | |
11319 | else | |
11320 | new.ndst = (dest << 8) & 0xFF00; | |
11321 | ||
11322 | /* set 'NV' to 'wakeup vector' */ | |
11323 | new.nv = POSTED_INTR_WAKEUP_VECTOR; | |
11324 | } while (cmpxchg(&pi_desc->control, old.control, | |
11325 | new.control) != old.control); | |
11326 | ||
11327 | return 0; | |
11328 | } | |
11329 | ||
bc22512b YJ |
11330 | static int vmx_pre_block(struct kvm_vcpu *vcpu) |
11331 | { | |
11332 | if (pi_pre_block(vcpu)) | |
11333 | return 1; | |
11334 | ||
64672c95 YJ |
11335 | if (kvm_lapic_hv_timer_in_use(vcpu)) |
11336 | kvm_lapic_switch_to_sw_timer(vcpu); | |
11337 | ||
bc22512b YJ |
11338 | return 0; |
11339 | } | |
11340 | ||
11341 | static void pi_post_block(struct kvm_vcpu *vcpu) | |
bf9f6ac8 FW |
11342 | { |
11343 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
11344 | struct pi_desc old, new; | |
11345 | unsigned int dest; | |
11346 | unsigned long flags; | |
11347 | ||
11348 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
11349 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
11350 | !kvm_vcpu_apicv_active(vcpu)) | |
bf9f6ac8 FW |
11351 | return; |
11352 | ||
11353 | do { | |
11354 | old.control = new.control = pi_desc->control; | |
11355 | ||
11356 | dest = cpu_physical_id(vcpu->cpu); | |
11357 | ||
11358 | if (x2apic_enabled()) | |
11359 | new.ndst = dest; | |
11360 | else | |
11361 | new.ndst = (dest << 8) & 0xFF00; | |
11362 | ||
11363 | /* Allow posting non-urgent interrupts */ | |
11364 | new.sn = 0; | |
11365 | ||
11366 | /* set 'NV' to 'notification vector' */ | |
11367 | new.nv = POSTED_INTR_VECTOR; | |
11368 | } while (cmpxchg(&pi_desc->control, old.control, | |
11369 | new.control) != old.control); | |
11370 | ||
11371 | if(vcpu->pre_pcpu != -1) { | |
11372 | spin_lock_irqsave( | |
11373 | &per_cpu(blocked_vcpu_on_cpu_lock, | |
11374 | vcpu->pre_pcpu), flags); | |
11375 | list_del(&vcpu->blocked_vcpu_list); | |
11376 | spin_unlock_irqrestore( | |
11377 | &per_cpu(blocked_vcpu_on_cpu_lock, | |
11378 | vcpu->pre_pcpu), flags); | |
11379 | vcpu->pre_pcpu = -1; | |
11380 | } | |
11381 | } | |
11382 | ||
bc22512b YJ |
11383 | static void vmx_post_block(struct kvm_vcpu *vcpu) |
11384 | { | |
64672c95 YJ |
11385 | if (kvm_x86_ops->set_hv_timer) |
11386 | kvm_lapic_switch_to_hv_timer(vcpu); | |
11387 | ||
bc22512b YJ |
11388 | pi_post_block(vcpu); |
11389 | } | |
11390 | ||
efc64404 FW |
11391 | /* |
11392 | * vmx_update_pi_irte - set IRTE for Posted-Interrupts | |
11393 | * | |
11394 | * @kvm: kvm | |
11395 | * @host_irq: host irq of the interrupt | |
11396 | * @guest_irq: gsi of the interrupt | |
11397 | * @set: set or unset PI | |
11398 | * returns 0 on success, < 0 on failure | |
11399 | */ | |
11400 | static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, | |
11401 | uint32_t guest_irq, bool set) | |
11402 | { | |
11403 | struct kvm_kernel_irq_routing_entry *e; | |
11404 | struct kvm_irq_routing_table *irq_rt; | |
11405 | struct kvm_lapic_irq irq; | |
11406 | struct kvm_vcpu *vcpu; | |
11407 | struct vcpu_data vcpu_info; | |
11408 | int idx, ret = -EINVAL; | |
11409 | ||
11410 | if (!kvm_arch_has_assigned_device(kvm) || | |
a0052191 YZ |
11411 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
11412 | !kvm_vcpu_apicv_active(kvm->vcpus[0])) | |
efc64404 FW |
11413 | return 0; |
11414 | ||
11415 | idx = srcu_read_lock(&kvm->irq_srcu); | |
11416 | irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); | |
11417 | BUG_ON(guest_irq >= irq_rt->nr_rt_entries); | |
11418 | ||
11419 | hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { | |
11420 | if (e->type != KVM_IRQ_ROUTING_MSI) | |
11421 | continue; | |
11422 | /* | |
11423 | * VT-d PI cannot support posting multicast/broadcast | |
11424 | * interrupts to a vCPU, we still use interrupt remapping | |
11425 | * for these kind of interrupts. | |
11426 | * | |
11427 | * For lowest-priority interrupts, we only support | |
11428 | * those with single CPU as the destination, e.g. user | |
11429 | * configures the interrupts via /proc/irq or uses | |
11430 | * irqbalance to make the interrupts single-CPU. | |
11431 | * | |
11432 | * We will support full lowest-priority interrupt later. | |
11433 | */ | |
11434 | ||
37131313 | 11435 | kvm_set_msi_irq(kvm, e, &irq); |
23a1c257 FW |
11436 | if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) { |
11437 | /* | |
11438 | * Make sure the IRTE is in remapped mode if | |
11439 | * we don't handle it in posted mode. | |
11440 | */ | |
11441 | ret = irq_set_vcpu_affinity(host_irq, NULL); | |
11442 | if (ret < 0) { | |
11443 | printk(KERN_INFO | |
11444 | "failed to back to remapped mode, irq: %u\n", | |
11445 | host_irq); | |
11446 | goto out; | |
11447 | } | |
11448 | ||
efc64404 | 11449 | continue; |
23a1c257 | 11450 | } |
efc64404 FW |
11451 | |
11452 | vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); | |
11453 | vcpu_info.vector = irq.vector; | |
11454 | ||
b6ce9780 | 11455 | trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi, |
efc64404 FW |
11456 | vcpu_info.vector, vcpu_info.pi_desc_addr, set); |
11457 | ||
11458 | if (set) | |
11459 | ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); | |
11460 | else { | |
11461 | /* suppress notification event before unposting */ | |
11462 | pi_set_sn(vcpu_to_pi_desc(vcpu)); | |
11463 | ret = irq_set_vcpu_affinity(host_irq, NULL); | |
11464 | pi_clear_sn(vcpu_to_pi_desc(vcpu)); | |
11465 | } | |
11466 | ||
11467 | if (ret < 0) { | |
11468 | printk(KERN_INFO "%s: failed to update PI IRTE\n", | |
11469 | __func__); | |
11470 | goto out; | |
11471 | } | |
11472 | } | |
11473 | ||
11474 | ret = 0; | |
11475 | out: | |
11476 | srcu_read_unlock(&kvm->irq_srcu, idx); | |
11477 | return ret; | |
11478 | } | |
11479 | ||
c45dcc71 AR |
11480 | static void vmx_setup_mce(struct kvm_vcpu *vcpu) |
11481 | { | |
11482 | if (vcpu->arch.mcg_cap & MCG_LMCE_P) | |
11483 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= | |
11484 | FEATURE_CONTROL_LMCE; | |
11485 | else | |
11486 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= | |
11487 | ~FEATURE_CONTROL_LMCE; | |
11488 | } | |
11489 | ||
404f6aac | 11490 | static struct kvm_x86_ops vmx_x86_ops __ro_after_init = { |
6aa8b732 AK |
11491 | .cpu_has_kvm_support = cpu_has_kvm_support, |
11492 | .disabled_by_bios = vmx_disabled_by_bios, | |
11493 | .hardware_setup = hardware_setup, | |
11494 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 11495 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
11496 | .hardware_enable = hardware_enable, |
11497 | .hardware_disable = hardware_disable, | |
04547156 | 11498 | .cpu_has_accelerated_tpr = report_flexpriority, |
6d396b55 | 11499 | .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase, |
6aa8b732 AK |
11500 | |
11501 | .vcpu_create = vmx_create_vcpu, | |
11502 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 11503 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 11504 | |
04d2cc77 | 11505 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
11506 | .vcpu_load = vmx_vcpu_load, |
11507 | .vcpu_put = vmx_vcpu_put, | |
11508 | ||
a96036b8 | 11509 | .update_bp_intercept = update_exception_bitmap, |
6aa8b732 AK |
11510 | .get_msr = vmx_get_msr, |
11511 | .set_msr = vmx_set_msr, | |
11512 | .get_segment_base = vmx_get_segment_base, | |
11513 | .get_segment = vmx_get_segment, | |
11514 | .set_segment = vmx_set_segment, | |
2e4d2653 | 11515 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 11516 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
e8467fda | 11517 | .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, |
aff48baa | 11518 | .decache_cr3 = vmx_decache_cr3, |
25c4c276 | 11519 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 11520 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
11521 | .set_cr3 = vmx_set_cr3, |
11522 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 11523 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
11524 | .get_idt = vmx_get_idt, |
11525 | .set_idt = vmx_set_idt, | |
11526 | .get_gdt = vmx_get_gdt, | |
11527 | .set_gdt = vmx_set_gdt, | |
73aaf249 JK |
11528 | .get_dr6 = vmx_get_dr6, |
11529 | .set_dr6 = vmx_set_dr6, | |
020df079 | 11530 | .set_dr7 = vmx_set_dr7, |
81908bf4 | 11531 | .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, |
5fdbf976 | 11532 | .cache_reg = vmx_cache_reg, |
6aa8b732 AK |
11533 | .get_rflags = vmx_get_rflags, |
11534 | .set_rflags = vmx_set_rflags, | |
be94f6b7 HH |
11535 | |
11536 | .get_pkru = vmx_get_pkru, | |
11537 | ||
0fdd74f7 | 11538 | .fpu_activate = vmx_fpu_activate, |
02daab21 | 11539 | .fpu_deactivate = vmx_fpu_deactivate, |
6aa8b732 AK |
11540 | |
11541 | .tlb_flush = vmx_flush_tlb, | |
6aa8b732 | 11542 | |
6aa8b732 | 11543 | .run = vmx_vcpu_run, |
6062d012 | 11544 | .handle_exit = vmx_handle_exit, |
6aa8b732 | 11545 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
11546 | .set_interrupt_shadow = vmx_set_interrupt_shadow, |
11547 | .get_interrupt_shadow = vmx_get_interrupt_shadow, | |
102d8325 | 11548 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 | 11549 | .set_irq = vmx_inject_irq, |
95ba8273 | 11550 | .set_nmi = vmx_inject_nmi, |
298101da | 11551 | .queue_exception = vmx_queue_exception, |
b463a6f7 | 11552 | .cancel_injection = vmx_cancel_injection, |
78646121 | 11553 | .interrupt_allowed = vmx_interrupt_allowed, |
95ba8273 | 11554 | .nmi_allowed = vmx_nmi_allowed, |
3cfc3092 JK |
11555 | .get_nmi_mask = vmx_get_nmi_mask, |
11556 | .set_nmi_mask = vmx_set_nmi_mask, | |
95ba8273 GN |
11557 | .enable_nmi_window = enable_nmi_window, |
11558 | .enable_irq_window = enable_irq_window, | |
11559 | .update_cr8_intercept = update_cr8_intercept, | |
8d14695f | 11560 | .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode, |
38b99173 | 11561 | .set_apic_access_page_addr = vmx_set_apic_access_page_addr, |
d62caabb AS |
11562 | .get_enable_apicv = vmx_get_enable_apicv, |
11563 | .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, | |
c7c9c56c YZ |
11564 | .load_eoi_exitmap = vmx_load_eoi_exitmap, |
11565 | .hwapic_irr_update = vmx_hwapic_irr_update, | |
11566 | .hwapic_isr_update = vmx_hwapic_isr_update, | |
a20ed54d YZ |
11567 | .sync_pir_to_irr = vmx_sync_pir_to_irr, |
11568 | .deliver_posted_interrupt = vmx_deliver_posted_interrupt, | |
95ba8273 | 11569 | |
cbc94022 | 11570 | .set_tss_addr = vmx_set_tss_addr, |
67253af5 | 11571 | .get_tdp_level = get_ept_level, |
4b12f0de | 11572 | .get_mt_mask = vmx_get_mt_mask, |
229456fc | 11573 | |
586f9607 | 11574 | .get_exit_info = vmx_get_exit_info, |
586f9607 | 11575 | |
17cc3935 | 11576 | .get_lpage_level = vmx_get_lpage_level, |
0e851880 SY |
11577 | |
11578 | .cpuid_update = vmx_cpuid_update, | |
4e47c7a6 SY |
11579 | |
11580 | .rdtscp_supported = vmx_rdtscp_supported, | |
ad756a16 | 11581 | .invpcid_supported = vmx_invpcid_supported, |
d4330ef2 JR |
11582 | |
11583 | .set_supported_cpuid = vmx_set_supported_cpuid, | |
f5f48ee1 SY |
11584 | |
11585 | .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, | |
99e3e30a ZA |
11586 | |
11587 | .write_tsc_offset = vmx_write_tsc_offset, | |
1c97f0a0 JR |
11588 | |
11589 | .set_tdp_cr3 = vmx_set_cr3, | |
8a76d7f2 JR |
11590 | |
11591 | .check_intercept = vmx_check_intercept, | |
a547c6db | 11592 | .handle_external_intr = vmx_handle_external_intr, |
da8999d3 | 11593 | .mpx_supported = vmx_mpx_supported, |
55412b2e | 11594 | .xsaves_supported = vmx_xsaves_supported, |
b6b8a145 JK |
11595 | |
11596 | .check_nested_events = vmx_check_nested_events, | |
ae97a3b8 RK |
11597 | |
11598 | .sched_in = vmx_sched_in, | |
843e4330 KH |
11599 | |
11600 | .slot_enable_log_dirty = vmx_slot_enable_log_dirty, | |
11601 | .slot_disable_log_dirty = vmx_slot_disable_log_dirty, | |
11602 | .flush_log_dirty = vmx_flush_log_dirty, | |
11603 | .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, | |
25462f7f | 11604 | |
bf9f6ac8 FW |
11605 | .pre_block = vmx_pre_block, |
11606 | .post_block = vmx_post_block, | |
11607 | ||
25462f7f | 11608 | .pmu_ops = &intel_pmu_ops, |
efc64404 FW |
11609 | |
11610 | .update_pi_irte = vmx_update_pi_irte, | |
64672c95 YJ |
11611 | |
11612 | #ifdef CONFIG_X86_64 | |
11613 | .set_hv_timer = vmx_set_hv_timer, | |
11614 | .cancel_hv_timer = vmx_cancel_hv_timer, | |
11615 | #endif | |
c45dcc71 AR |
11616 | |
11617 | .setup_mce = vmx_setup_mce, | |
6aa8b732 AK |
11618 | }; |
11619 | ||
11620 | static int __init vmx_init(void) | |
11621 | { | |
34a1cd60 TC |
11622 | int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), |
11623 | __alignof__(struct vcpu_vmx), THIS_MODULE); | |
fdef3ad1 | 11624 | if (r) |
34a1cd60 | 11625 | return r; |
25c5f225 | 11626 | |
2965faa5 | 11627 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
11628 | rcu_assign_pointer(crash_vmclear_loaded_vmcss, |
11629 | crash_vmclear_local_loaded_vmcss); | |
11630 | #endif | |
11631 | ||
fdef3ad1 | 11632 | return 0; |
6aa8b732 AK |
11633 | } |
11634 | ||
11635 | static void __exit vmx_exit(void) | |
11636 | { | |
2965faa5 | 11637 | #ifdef CONFIG_KEXEC_CORE |
3b63a43f | 11638 | RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); |
8f536b76 ZY |
11639 | synchronize_rcu(); |
11640 | #endif | |
11641 | ||
cb498ea2 | 11642 | kvm_exit(); |
6aa8b732 AK |
11643 | } |
11644 | ||
11645 | module_init(vmx_init) | |
11646 | module_exit(vmx_exit) |