Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 8 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
9 | * |
10 | * Authors: | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * | |
14 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
15 | * the COPYING file in the top-level directory. | |
16 | * | |
17 | */ | |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
00b27a3e | 21 | #include "cpuid.h" |
d62caabb | 22 | #include "lapic.h" |
e495606d | 23 | |
edf88417 | 24 | #include <linux/kvm_host.h> |
6aa8b732 | 25 | #include <linux/module.h> |
9d8f549d | 26 | #include <linux/kernel.h> |
6aa8b732 AK |
27 | #include <linux/mm.h> |
28 | #include <linux/highmem.h> | |
e8edc6e0 | 29 | #include <linux/sched.h> |
c7addb90 | 30 | #include <linux/moduleparam.h> |
e9bda3b3 | 31 | #include <linux/mod_devicetable.h> |
af658dca | 32 | #include <linux/trace_events.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
cafd6659 | 34 | #include <linux/tboot.h> |
f4124500 | 35 | #include <linux/hrtimer.h> |
5fdbf976 | 36 | #include "kvm_cache_regs.h" |
35920a35 | 37 | #include "x86.h" |
e495606d | 38 | |
28b835d6 | 39 | #include <asm/cpu.h> |
6aa8b732 | 40 | #include <asm/io.h> |
3b3be0d1 | 41 | #include <asm/desc.h> |
13673a90 | 42 | #include <asm/vmx.h> |
6210e37b | 43 | #include <asm/virtext.h> |
a0861c02 | 44 | #include <asm/mce.h> |
952f07ec | 45 | #include <asm/fpu/internal.h> |
d7cd9796 | 46 | #include <asm/perf_event.h> |
81908bf4 | 47 | #include <asm/debugreg.h> |
8f536b76 | 48 | #include <asm/kexec.h> |
dab2087d | 49 | #include <asm/apic.h> |
efc64404 | 50 | #include <asm/irq_remapping.h> |
6aa8b732 | 51 | |
229456fc | 52 | #include "trace.h" |
25462f7f | 53 | #include "pmu.h" |
229456fc | 54 | |
4ecac3fd | 55 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
5e520e62 AK |
56 | #define __ex_clear(x, reg) \ |
57 | ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg) | |
4ecac3fd | 58 | |
6aa8b732 AK |
59 | MODULE_AUTHOR("Qumranet"); |
60 | MODULE_LICENSE("GPL"); | |
61 | ||
e9bda3b3 JT |
62 | static const struct x86_cpu_id vmx_cpu_id[] = { |
63 | X86_FEATURE_MATCH(X86_FEATURE_VMX), | |
64 | {} | |
65 | }; | |
66 | MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); | |
67 | ||
476bc001 | 68 | static bool __read_mostly enable_vpid = 1; |
736caefe | 69 | module_param_named(vpid, enable_vpid, bool, 0444); |
2384d2b3 | 70 | |
476bc001 | 71 | static bool __read_mostly flexpriority_enabled = 1; |
736caefe | 72 | module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); |
4c9fc8ef | 73 | |
476bc001 | 74 | static bool __read_mostly enable_ept = 1; |
736caefe | 75 | module_param_named(ept, enable_ept, bool, S_IRUGO); |
d56f546d | 76 | |
476bc001 | 77 | static bool __read_mostly enable_unrestricted_guest = 1; |
3a624e29 NK |
78 | module_param_named(unrestricted_guest, |
79 | enable_unrestricted_guest, bool, S_IRUGO); | |
80 | ||
83c3a331 XH |
81 | static bool __read_mostly enable_ept_ad_bits = 1; |
82 | module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); | |
83 | ||
a27685c3 | 84 | static bool __read_mostly emulate_invalid_guest_state = true; |
c1f8bc04 | 85 | module_param(emulate_invalid_guest_state, bool, S_IRUGO); |
04fa4d32 | 86 | |
476bc001 | 87 | static bool __read_mostly vmm_exclusive = 1; |
b923e62e DX |
88 | module_param(vmm_exclusive, bool, S_IRUGO); |
89 | ||
476bc001 | 90 | static bool __read_mostly fasteoi = 1; |
58fbbf26 KT |
91 | module_param(fasteoi, bool, S_IRUGO); |
92 | ||
5a71785d | 93 | static bool __read_mostly enable_apicv = 1; |
01e439be | 94 | module_param(enable_apicv, bool, S_IRUGO); |
83d4c286 | 95 | |
abc4fc58 AG |
96 | static bool __read_mostly enable_shadow_vmcs = 1; |
97 | module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO); | |
801d3424 NHE |
98 | /* |
99 | * If nested=1, nested virtualization is supported, i.e., guests may use | |
100 | * VMX and be a hypervisor for its own guests. If nested=0, guests may not | |
101 | * use VMX instructions. | |
102 | */ | |
476bc001 | 103 | static bool __read_mostly nested = 0; |
801d3424 NHE |
104 | module_param(nested, bool, S_IRUGO); |
105 | ||
20300099 WL |
106 | static u64 __read_mostly host_xss; |
107 | ||
843e4330 KH |
108 | static bool __read_mostly enable_pml = 1; |
109 | module_param_named(pml, enable_pml, bool, S_IRUGO); | |
110 | ||
64903d61 HZ |
111 | #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL |
112 | ||
64672c95 YJ |
113 | /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ |
114 | static int __read_mostly cpu_preemption_timer_multi; | |
115 | static bool __read_mostly enable_preemption_timer = 1; | |
116 | #ifdef CONFIG_X86_64 | |
117 | module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); | |
118 | #endif | |
119 | ||
5037878e GN |
120 | #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD) |
121 | #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE) | |
cdc0e244 AK |
122 | #define KVM_VM_CR0_ALWAYS_ON \ |
123 | (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) | |
4c38609a AK |
124 | #define KVM_CR4_GUEST_OWNED_BITS \ |
125 | (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
52ce3c21 | 126 | | X86_CR4_OSXMMEXCPT | X86_CR4_TSD) |
4c38609a | 127 | |
cdc0e244 AK |
128 | #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) |
129 | #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) | |
130 | ||
78ac8b47 AK |
131 | #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) |
132 | ||
f4124500 JK |
133 | #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5 |
134 | ||
4b8d54f9 ZE |
135 | /* |
136 | * These 2 parameters are used to config the controls for Pause-Loop Exiting: | |
137 | * ple_gap: upper bound on the amount of time between two successive | |
138 | * executions of PAUSE in a loop. Also indicate if ple enabled. | |
00c25bce | 139 | * According to test, this time is usually smaller than 128 cycles. |
4b8d54f9 ZE |
140 | * ple_window: upper bound on the amount of time a guest is allowed to execute |
141 | * in a PAUSE loop. Tests indicate that most spinlocks are held for | |
142 | * less than 2^12 cycles | |
143 | * Time is measured based on a counter that runs at the same rate as the TSC, | |
144 | * refer SDM volume 3b section 21.6.13 & 22.1.3. | |
145 | */ | |
b4a2d31d RK |
146 | #define KVM_VMX_DEFAULT_PLE_GAP 128 |
147 | #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 | |
148 | #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2 | |
149 | #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0 | |
150 | #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \ | |
151 | INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW | |
152 | ||
4b8d54f9 ZE |
153 | static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP; |
154 | module_param(ple_gap, int, S_IRUGO); | |
155 | ||
156 | static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; | |
157 | module_param(ple_window, int, S_IRUGO); | |
158 | ||
b4a2d31d RK |
159 | /* Default doubles per-vcpu window every exit. */ |
160 | static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW; | |
161 | module_param(ple_window_grow, int, S_IRUGO); | |
162 | ||
163 | /* Default resets per-vcpu window every exit to ple_window. */ | |
164 | static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK; | |
165 | module_param(ple_window_shrink, int, S_IRUGO); | |
166 | ||
167 | /* Default is to compute the maximum so we can never overflow. */ | |
168 | static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; | |
169 | static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; | |
170 | module_param(ple_window_max, int, S_IRUGO); | |
171 | ||
83287ea4 AK |
172 | extern const ulong vmx_return; |
173 | ||
8bf00a52 | 174 | #define NR_AUTOLOAD_MSRS 8 |
ff2f6fe9 | 175 | #define VMCS02_POOL_SIZE 1 |
61d2ef2c | 176 | |
a2fa3e9f GH |
177 | struct vmcs { |
178 | u32 revision_id; | |
179 | u32 abort; | |
180 | char data[0]; | |
181 | }; | |
182 | ||
d462b819 NHE |
183 | /* |
184 | * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also | |
185 | * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs | |
186 | * loaded on this CPU (so we can clear them if the CPU goes down). | |
187 | */ | |
188 | struct loaded_vmcs { | |
189 | struct vmcs *vmcs; | |
190 | int cpu; | |
191 | int launched; | |
192 | struct list_head loaded_vmcss_on_cpu_link; | |
193 | }; | |
194 | ||
26bb0981 AK |
195 | struct shared_msr_entry { |
196 | unsigned index; | |
197 | u64 data; | |
d5696725 | 198 | u64 mask; |
26bb0981 AK |
199 | }; |
200 | ||
a9d30f33 NHE |
201 | /* |
202 | * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a | |
203 | * single nested guest (L2), hence the name vmcs12. Any VMX implementation has | |
204 | * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is | |
205 | * stored in guest memory specified by VMPTRLD, but is opaque to the guest, | |
206 | * which must access it using VMREAD/VMWRITE/VMCLEAR instructions. | |
207 | * More than one of these structures may exist, if L1 runs multiple L2 guests. | |
208 | * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the | |
209 | * underlying hardware which will be used to run L2. | |
210 | * This structure is packed to ensure that its layout is identical across | |
211 | * machines (necessary for live migration). | |
212 | * If there are changes in this struct, VMCS12_REVISION must be changed. | |
213 | */ | |
22bd0358 | 214 | typedef u64 natural_width; |
a9d30f33 NHE |
215 | struct __packed vmcs12 { |
216 | /* According to the Intel spec, a VMCS region must start with the | |
217 | * following two fields. Then follow implementation-specific data. | |
218 | */ | |
219 | u32 revision_id; | |
220 | u32 abort; | |
22bd0358 | 221 | |
27d6c865 NHE |
222 | u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */ |
223 | u32 padding[7]; /* room for future expansion */ | |
224 | ||
22bd0358 NHE |
225 | u64 io_bitmap_a; |
226 | u64 io_bitmap_b; | |
227 | u64 msr_bitmap; | |
228 | u64 vm_exit_msr_store_addr; | |
229 | u64 vm_exit_msr_load_addr; | |
230 | u64 vm_entry_msr_load_addr; | |
231 | u64 tsc_offset; | |
232 | u64 virtual_apic_page_addr; | |
233 | u64 apic_access_addr; | |
705699a1 | 234 | u64 posted_intr_desc_addr; |
22bd0358 | 235 | u64 ept_pointer; |
608406e2 WV |
236 | u64 eoi_exit_bitmap0; |
237 | u64 eoi_exit_bitmap1; | |
238 | u64 eoi_exit_bitmap2; | |
239 | u64 eoi_exit_bitmap3; | |
81dc01f7 | 240 | u64 xss_exit_bitmap; |
22bd0358 NHE |
241 | u64 guest_physical_address; |
242 | u64 vmcs_link_pointer; | |
243 | u64 guest_ia32_debugctl; | |
244 | u64 guest_ia32_pat; | |
245 | u64 guest_ia32_efer; | |
246 | u64 guest_ia32_perf_global_ctrl; | |
247 | u64 guest_pdptr0; | |
248 | u64 guest_pdptr1; | |
249 | u64 guest_pdptr2; | |
250 | u64 guest_pdptr3; | |
36be0b9d | 251 | u64 guest_bndcfgs; |
22bd0358 NHE |
252 | u64 host_ia32_pat; |
253 | u64 host_ia32_efer; | |
254 | u64 host_ia32_perf_global_ctrl; | |
255 | u64 padding64[8]; /* room for future expansion */ | |
256 | /* | |
257 | * To allow migration of L1 (complete with its L2 guests) between | |
258 | * machines of different natural widths (32 or 64 bit), we cannot have | |
259 | * unsigned long fields with no explict size. We use u64 (aliased | |
260 | * natural_width) instead. Luckily, x86 is little-endian. | |
261 | */ | |
262 | natural_width cr0_guest_host_mask; | |
263 | natural_width cr4_guest_host_mask; | |
264 | natural_width cr0_read_shadow; | |
265 | natural_width cr4_read_shadow; | |
266 | natural_width cr3_target_value0; | |
267 | natural_width cr3_target_value1; | |
268 | natural_width cr3_target_value2; | |
269 | natural_width cr3_target_value3; | |
270 | natural_width exit_qualification; | |
271 | natural_width guest_linear_address; | |
272 | natural_width guest_cr0; | |
273 | natural_width guest_cr3; | |
274 | natural_width guest_cr4; | |
275 | natural_width guest_es_base; | |
276 | natural_width guest_cs_base; | |
277 | natural_width guest_ss_base; | |
278 | natural_width guest_ds_base; | |
279 | natural_width guest_fs_base; | |
280 | natural_width guest_gs_base; | |
281 | natural_width guest_ldtr_base; | |
282 | natural_width guest_tr_base; | |
283 | natural_width guest_gdtr_base; | |
284 | natural_width guest_idtr_base; | |
285 | natural_width guest_dr7; | |
286 | natural_width guest_rsp; | |
287 | natural_width guest_rip; | |
288 | natural_width guest_rflags; | |
289 | natural_width guest_pending_dbg_exceptions; | |
290 | natural_width guest_sysenter_esp; | |
291 | natural_width guest_sysenter_eip; | |
292 | natural_width host_cr0; | |
293 | natural_width host_cr3; | |
294 | natural_width host_cr4; | |
295 | natural_width host_fs_base; | |
296 | natural_width host_gs_base; | |
297 | natural_width host_tr_base; | |
298 | natural_width host_gdtr_base; | |
299 | natural_width host_idtr_base; | |
300 | natural_width host_ia32_sysenter_esp; | |
301 | natural_width host_ia32_sysenter_eip; | |
302 | natural_width host_rsp; | |
303 | natural_width host_rip; | |
304 | natural_width paddingl[8]; /* room for future expansion */ | |
305 | u32 pin_based_vm_exec_control; | |
306 | u32 cpu_based_vm_exec_control; | |
307 | u32 exception_bitmap; | |
308 | u32 page_fault_error_code_mask; | |
309 | u32 page_fault_error_code_match; | |
310 | u32 cr3_target_count; | |
311 | u32 vm_exit_controls; | |
312 | u32 vm_exit_msr_store_count; | |
313 | u32 vm_exit_msr_load_count; | |
314 | u32 vm_entry_controls; | |
315 | u32 vm_entry_msr_load_count; | |
316 | u32 vm_entry_intr_info_field; | |
317 | u32 vm_entry_exception_error_code; | |
318 | u32 vm_entry_instruction_len; | |
319 | u32 tpr_threshold; | |
320 | u32 secondary_vm_exec_control; | |
321 | u32 vm_instruction_error; | |
322 | u32 vm_exit_reason; | |
323 | u32 vm_exit_intr_info; | |
324 | u32 vm_exit_intr_error_code; | |
325 | u32 idt_vectoring_info_field; | |
326 | u32 idt_vectoring_error_code; | |
327 | u32 vm_exit_instruction_len; | |
328 | u32 vmx_instruction_info; | |
329 | u32 guest_es_limit; | |
330 | u32 guest_cs_limit; | |
331 | u32 guest_ss_limit; | |
332 | u32 guest_ds_limit; | |
333 | u32 guest_fs_limit; | |
334 | u32 guest_gs_limit; | |
335 | u32 guest_ldtr_limit; | |
336 | u32 guest_tr_limit; | |
337 | u32 guest_gdtr_limit; | |
338 | u32 guest_idtr_limit; | |
339 | u32 guest_es_ar_bytes; | |
340 | u32 guest_cs_ar_bytes; | |
341 | u32 guest_ss_ar_bytes; | |
342 | u32 guest_ds_ar_bytes; | |
343 | u32 guest_fs_ar_bytes; | |
344 | u32 guest_gs_ar_bytes; | |
345 | u32 guest_ldtr_ar_bytes; | |
346 | u32 guest_tr_ar_bytes; | |
347 | u32 guest_interruptibility_info; | |
348 | u32 guest_activity_state; | |
349 | u32 guest_sysenter_cs; | |
350 | u32 host_ia32_sysenter_cs; | |
0238ea91 JK |
351 | u32 vmx_preemption_timer_value; |
352 | u32 padding32[7]; /* room for future expansion */ | |
22bd0358 | 353 | u16 virtual_processor_id; |
705699a1 | 354 | u16 posted_intr_nv; |
22bd0358 NHE |
355 | u16 guest_es_selector; |
356 | u16 guest_cs_selector; | |
357 | u16 guest_ss_selector; | |
358 | u16 guest_ds_selector; | |
359 | u16 guest_fs_selector; | |
360 | u16 guest_gs_selector; | |
361 | u16 guest_ldtr_selector; | |
362 | u16 guest_tr_selector; | |
608406e2 | 363 | u16 guest_intr_status; |
22bd0358 NHE |
364 | u16 host_es_selector; |
365 | u16 host_cs_selector; | |
366 | u16 host_ss_selector; | |
367 | u16 host_ds_selector; | |
368 | u16 host_fs_selector; | |
369 | u16 host_gs_selector; | |
370 | u16 host_tr_selector; | |
a9d30f33 NHE |
371 | }; |
372 | ||
373 | /* | |
374 | * VMCS12_REVISION is an arbitrary id that should be changed if the content or | |
375 | * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and | |
376 | * VMPTRLD verifies that the VMCS region that L1 is loading contains this id. | |
377 | */ | |
378 | #define VMCS12_REVISION 0x11e57ed0 | |
379 | ||
380 | /* | |
381 | * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region | |
382 | * and any VMCS region. Although only sizeof(struct vmcs12) are used by the | |
383 | * current implementation, 4K are reserved to avoid future complications. | |
384 | */ | |
385 | #define VMCS12_SIZE 0x1000 | |
386 | ||
ff2f6fe9 NHE |
387 | /* Used to remember the last vmcs02 used for some recently used vmcs12s */ |
388 | struct vmcs02_list { | |
389 | struct list_head list; | |
390 | gpa_t vmptr; | |
391 | struct loaded_vmcs vmcs02; | |
392 | }; | |
393 | ||
ec378aee NHE |
394 | /* |
395 | * The nested_vmx structure is part of vcpu_vmx, and holds information we need | |
396 | * for correct emulation of VMX (i.e., nested VMX) on this vcpu. | |
397 | */ | |
398 | struct nested_vmx { | |
399 | /* Has the level1 guest done vmxon? */ | |
400 | bool vmxon; | |
3573e22c | 401 | gpa_t vmxon_ptr; |
a9d30f33 NHE |
402 | |
403 | /* The guest-physical address of the current VMCS L1 keeps for L2 */ | |
404 | gpa_t current_vmptr; | |
405 | /* The host-usable pointer to the above */ | |
406 | struct page *current_vmcs12_page; | |
407 | struct vmcs12 *current_vmcs12; | |
4f2777bc DM |
408 | /* |
409 | * Cache of the guest's VMCS, existing outside of guest memory. | |
410 | * Loaded from guest memory during VMPTRLD. Flushed to guest | |
411 | * memory during VMXOFF, VMCLEAR, VMPTRLD. | |
412 | */ | |
413 | struct vmcs12 *cached_vmcs12; | |
8de48833 | 414 | struct vmcs *current_shadow_vmcs; |
012f83cb AG |
415 | /* |
416 | * Indicates if the shadow vmcs must be updated with the | |
417 | * data hold by vmcs12 | |
418 | */ | |
419 | bool sync_shadow_vmcs; | |
ff2f6fe9 NHE |
420 | |
421 | /* vmcs02_list cache of VMCSs recently used to run L2 guests */ | |
422 | struct list_head vmcs02_pool; | |
423 | int vmcs02_num; | |
fe3ef05c | 424 | u64 vmcs01_tsc_offset; |
644d711a NHE |
425 | /* L2 must run next, and mustn't decide to exit to L1. */ |
426 | bool nested_run_pending; | |
fe3ef05c NHE |
427 | /* |
428 | * Guest pages referred to in vmcs02 with host-physical pointers, so | |
429 | * we must keep them pinned while L2 runs. | |
430 | */ | |
431 | struct page *apic_access_page; | |
a7c0b07d | 432 | struct page *virtual_apic_page; |
705699a1 WV |
433 | struct page *pi_desc_page; |
434 | struct pi_desc *pi_desc; | |
435 | bool pi_pending; | |
436 | u16 posted_intr_nv; | |
f4124500 JK |
437 | |
438 | struct hrtimer preemption_timer; | |
439 | bool preemption_timer_expired; | |
2996fca0 JK |
440 | |
441 | /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */ | |
442 | u64 vmcs01_debugctl; | |
b9c237bb | 443 | |
5c614b35 WL |
444 | u16 vpid02; |
445 | u16 last_vpid; | |
446 | ||
b9c237bb WV |
447 | u32 nested_vmx_procbased_ctls_low; |
448 | u32 nested_vmx_procbased_ctls_high; | |
449 | u32 nested_vmx_true_procbased_ctls_low; | |
450 | u32 nested_vmx_secondary_ctls_low; | |
451 | u32 nested_vmx_secondary_ctls_high; | |
452 | u32 nested_vmx_pinbased_ctls_low; | |
453 | u32 nested_vmx_pinbased_ctls_high; | |
454 | u32 nested_vmx_exit_ctls_low; | |
455 | u32 nested_vmx_exit_ctls_high; | |
456 | u32 nested_vmx_true_exit_ctls_low; | |
457 | u32 nested_vmx_entry_ctls_low; | |
458 | u32 nested_vmx_entry_ctls_high; | |
459 | u32 nested_vmx_true_entry_ctls_low; | |
460 | u32 nested_vmx_misc_low; | |
461 | u32 nested_vmx_misc_high; | |
462 | u32 nested_vmx_ept_caps; | |
99b83ac8 | 463 | u32 nested_vmx_vpid_caps; |
ec378aee NHE |
464 | }; |
465 | ||
01e439be | 466 | #define POSTED_INTR_ON 0 |
ebbfc765 FW |
467 | #define POSTED_INTR_SN 1 |
468 | ||
01e439be YZ |
469 | /* Posted-Interrupt Descriptor */ |
470 | struct pi_desc { | |
471 | u32 pir[8]; /* Posted interrupt requested */ | |
6ef1522f FW |
472 | union { |
473 | struct { | |
474 | /* bit 256 - Outstanding Notification */ | |
475 | u16 on : 1, | |
476 | /* bit 257 - Suppress Notification */ | |
477 | sn : 1, | |
478 | /* bit 271:258 - Reserved */ | |
479 | rsvd_1 : 14; | |
480 | /* bit 279:272 - Notification Vector */ | |
481 | u8 nv; | |
482 | /* bit 287:280 - Reserved */ | |
483 | u8 rsvd_2; | |
484 | /* bit 319:288 - Notification Destination */ | |
485 | u32 ndst; | |
486 | }; | |
487 | u64 control; | |
488 | }; | |
489 | u32 rsvd[6]; | |
01e439be YZ |
490 | } __aligned(64); |
491 | ||
a20ed54d YZ |
492 | static bool pi_test_and_set_on(struct pi_desc *pi_desc) |
493 | { | |
494 | return test_and_set_bit(POSTED_INTR_ON, | |
495 | (unsigned long *)&pi_desc->control); | |
496 | } | |
497 | ||
498 | static bool pi_test_and_clear_on(struct pi_desc *pi_desc) | |
499 | { | |
500 | return test_and_clear_bit(POSTED_INTR_ON, | |
501 | (unsigned long *)&pi_desc->control); | |
502 | } | |
503 | ||
504 | static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc) | |
505 | { | |
506 | return test_and_set_bit(vector, (unsigned long *)pi_desc->pir); | |
507 | } | |
508 | ||
ebbfc765 FW |
509 | static inline void pi_clear_sn(struct pi_desc *pi_desc) |
510 | { | |
511 | return clear_bit(POSTED_INTR_SN, | |
512 | (unsigned long *)&pi_desc->control); | |
513 | } | |
514 | ||
515 | static inline void pi_set_sn(struct pi_desc *pi_desc) | |
516 | { | |
517 | return set_bit(POSTED_INTR_SN, | |
518 | (unsigned long *)&pi_desc->control); | |
519 | } | |
520 | ||
521 | static inline int pi_test_on(struct pi_desc *pi_desc) | |
522 | { | |
523 | return test_bit(POSTED_INTR_ON, | |
524 | (unsigned long *)&pi_desc->control); | |
525 | } | |
526 | ||
527 | static inline int pi_test_sn(struct pi_desc *pi_desc) | |
528 | { | |
529 | return test_bit(POSTED_INTR_SN, | |
530 | (unsigned long *)&pi_desc->control); | |
531 | } | |
532 | ||
a2fa3e9f | 533 | struct vcpu_vmx { |
fb3f0f51 | 534 | struct kvm_vcpu vcpu; |
313dbd49 | 535 | unsigned long host_rsp; |
29bd8a78 | 536 | u8 fail; |
9d58b931 | 537 | bool nmi_known_unmasked; |
51aa01d1 | 538 | u32 exit_intr_info; |
1155f76a | 539 | u32 idt_vectoring_info; |
6de12732 | 540 | ulong rflags; |
26bb0981 | 541 | struct shared_msr_entry *guest_msrs; |
a2fa3e9f GH |
542 | int nmsrs; |
543 | int save_nmsrs; | |
a547c6db | 544 | unsigned long host_idt_base; |
a2fa3e9f | 545 | #ifdef CONFIG_X86_64 |
44ea2b17 AK |
546 | u64 msr_host_kernel_gs_base; |
547 | u64 msr_guest_kernel_gs_base; | |
a2fa3e9f | 548 | #endif |
2961e876 GN |
549 | u32 vm_entry_controls_shadow; |
550 | u32 vm_exit_controls_shadow; | |
d462b819 NHE |
551 | /* |
552 | * loaded_vmcs points to the VMCS currently used in this vcpu. For a | |
553 | * non-nested (L1) guest, it always points to vmcs01. For a nested | |
554 | * guest (L2), it points to a different VMCS. | |
555 | */ | |
556 | struct loaded_vmcs vmcs01; | |
557 | struct loaded_vmcs *loaded_vmcs; | |
558 | bool __launched; /* temporary, used in vmx_vcpu_run */ | |
61d2ef2c AK |
559 | struct msr_autoload { |
560 | unsigned nr; | |
561 | struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS]; | |
562 | struct vmx_msr_entry host[NR_AUTOLOAD_MSRS]; | |
563 | } msr_autoload; | |
a2fa3e9f GH |
564 | struct { |
565 | int loaded; | |
566 | u16 fs_sel, gs_sel, ldt_sel; | |
b2da15ac AK |
567 | #ifdef CONFIG_X86_64 |
568 | u16 ds_sel, es_sel; | |
569 | #endif | |
152d3f2f LV |
570 | int gs_ldt_reload_needed; |
571 | int fs_reload_needed; | |
da8999d3 | 572 | u64 msr_host_bndcfgs; |
d974baa3 | 573 | unsigned long vmcs_host_cr4; /* May not match real cr4 */ |
d77c26fc | 574 | } host_state; |
9c8cba37 | 575 | struct { |
7ffd92c5 | 576 | int vm86_active; |
78ac8b47 | 577 | ulong save_rflags; |
f5f7b2fe AK |
578 | struct kvm_segment segs[8]; |
579 | } rmode; | |
580 | struct { | |
581 | u32 bitmask; /* 4 bits per segment (1 bit per field) */ | |
7ffd92c5 AK |
582 | struct kvm_save_segment { |
583 | u16 selector; | |
584 | unsigned long base; | |
585 | u32 limit; | |
586 | u32 ar; | |
f5f7b2fe | 587 | } seg[8]; |
2fb92db1 | 588 | } segment_cache; |
2384d2b3 | 589 | int vpid; |
04fa4d32 | 590 | bool emulation_required; |
3b86cd99 JK |
591 | |
592 | /* Support for vnmi-less CPUs */ | |
593 | int soft_vnmi_blocked; | |
594 | ktime_t entry_time; | |
595 | s64 vnmi_blocked_time; | |
a0861c02 | 596 | u32 exit_reason; |
4e47c7a6 | 597 | |
01e439be YZ |
598 | /* Posted interrupt descriptor */ |
599 | struct pi_desc pi_desc; | |
600 | ||
ec378aee NHE |
601 | /* Support for a guest hypervisor (nested VMX) */ |
602 | struct nested_vmx nested; | |
a7653ecd RK |
603 | |
604 | /* Dynamic PLE window. */ | |
605 | int ple_window; | |
606 | bool ple_window_dirty; | |
843e4330 KH |
607 | |
608 | /* Support for PML */ | |
609 | #define PML_ENTITY_NUM 512 | |
610 | struct page *pml_pg; | |
2680d6da | 611 | |
64672c95 YJ |
612 | /* apic deadline value in host tsc */ |
613 | u64 hv_deadline_tsc; | |
614 | ||
2680d6da | 615 | u64 current_tsc_ratio; |
1be0e61c XG |
616 | |
617 | bool guest_pkru_valid; | |
618 | u32 guest_pkru; | |
619 | u32 host_pkru; | |
3b84080b | 620 | |
37e4c997 HZ |
621 | /* |
622 | * Only bits masked by msr_ia32_feature_control_valid_bits can be set in | |
623 | * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included | |
624 | * in msr_ia32_feature_control_valid_bits. | |
625 | */ | |
3b84080b | 626 | u64 msr_ia32_feature_control; |
37e4c997 | 627 | u64 msr_ia32_feature_control_valid_bits; |
a2fa3e9f GH |
628 | }; |
629 | ||
2fb92db1 AK |
630 | enum segment_cache_field { |
631 | SEG_FIELD_SEL = 0, | |
632 | SEG_FIELD_BASE = 1, | |
633 | SEG_FIELD_LIMIT = 2, | |
634 | SEG_FIELD_AR = 3, | |
635 | ||
636 | SEG_FIELD_NR = 4 | |
637 | }; | |
638 | ||
a2fa3e9f GH |
639 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) |
640 | { | |
fb3f0f51 | 641 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
642 | } |
643 | ||
efc64404 FW |
644 | static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu) |
645 | { | |
646 | return &(to_vmx(vcpu)->pi_desc); | |
647 | } | |
648 | ||
22bd0358 NHE |
649 | #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x) |
650 | #define FIELD(number, name) [number] = VMCS12_OFFSET(name) | |
651 | #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \ | |
652 | [number##_HIGH] = VMCS12_OFFSET(name)+4 | |
653 | ||
4607c2d7 | 654 | |
fe2b201b | 655 | static unsigned long shadow_read_only_fields[] = { |
4607c2d7 AG |
656 | /* |
657 | * We do NOT shadow fields that are modified when L0 | |
658 | * traps and emulates any vmx instruction (e.g. VMPTRLD, | |
659 | * VMXON...) executed by L1. | |
660 | * For example, VM_INSTRUCTION_ERROR is read | |
661 | * by L1 if a vmx instruction fails (part of the error path). | |
662 | * Note the code assumes this logic. If for some reason | |
663 | * we start shadowing these fields then we need to | |
664 | * force a shadow sync when L0 emulates vmx instructions | |
665 | * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified | |
666 | * by nested_vmx_failValid) | |
667 | */ | |
668 | VM_EXIT_REASON, | |
669 | VM_EXIT_INTR_INFO, | |
670 | VM_EXIT_INSTRUCTION_LEN, | |
671 | IDT_VECTORING_INFO_FIELD, | |
672 | IDT_VECTORING_ERROR_CODE, | |
673 | VM_EXIT_INTR_ERROR_CODE, | |
674 | EXIT_QUALIFICATION, | |
675 | GUEST_LINEAR_ADDRESS, | |
676 | GUEST_PHYSICAL_ADDRESS | |
677 | }; | |
fe2b201b | 678 | static int max_shadow_read_only_fields = |
4607c2d7 AG |
679 | ARRAY_SIZE(shadow_read_only_fields); |
680 | ||
fe2b201b | 681 | static unsigned long shadow_read_write_fields[] = { |
a7c0b07d | 682 | TPR_THRESHOLD, |
4607c2d7 AG |
683 | GUEST_RIP, |
684 | GUEST_RSP, | |
685 | GUEST_CR0, | |
686 | GUEST_CR3, | |
687 | GUEST_CR4, | |
688 | GUEST_INTERRUPTIBILITY_INFO, | |
689 | GUEST_RFLAGS, | |
690 | GUEST_CS_SELECTOR, | |
691 | GUEST_CS_AR_BYTES, | |
692 | GUEST_CS_LIMIT, | |
693 | GUEST_CS_BASE, | |
694 | GUEST_ES_BASE, | |
36be0b9d | 695 | GUEST_BNDCFGS, |
4607c2d7 AG |
696 | CR0_GUEST_HOST_MASK, |
697 | CR0_READ_SHADOW, | |
698 | CR4_READ_SHADOW, | |
699 | TSC_OFFSET, | |
700 | EXCEPTION_BITMAP, | |
701 | CPU_BASED_VM_EXEC_CONTROL, | |
702 | VM_ENTRY_EXCEPTION_ERROR_CODE, | |
703 | VM_ENTRY_INTR_INFO_FIELD, | |
704 | VM_ENTRY_INSTRUCTION_LEN, | |
705 | VM_ENTRY_EXCEPTION_ERROR_CODE, | |
706 | HOST_FS_BASE, | |
707 | HOST_GS_BASE, | |
708 | HOST_FS_SELECTOR, | |
709 | HOST_GS_SELECTOR | |
710 | }; | |
fe2b201b | 711 | static int max_shadow_read_write_fields = |
4607c2d7 AG |
712 | ARRAY_SIZE(shadow_read_write_fields); |
713 | ||
772e0318 | 714 | static const unsigned short vmcs_field_to_offset_table[] = { |
22bd0358 | 715 | FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id), |
705699a1 | 716 | FIELD(POSTED_INTR_NV, posted_intr_nv), |
22bd0358 NHE |
717 | FIELD(GUEST_ES_SELECTOR, guest_es_selector), |
718 | FIELD(GUEST_CS_SELECTOR, guest_cs_selector), | |
719 | FIELD(GUEST_SS_SELECTOR, guest_ss_selector), | |
720 | FIELD(GUEST_DS_SELECTOR, guest_ds_selector), | |
721 | FIELD(GUEST_FS_SELECTOR, guest_fs_selector), | |
722 | FIELD(GUEST_GS_SELECTOR, guest_gs_selector), | |
723 | FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector), | |
724 | FIELD(GUEST_TR_SELECTOR, guest_tr_selector), | |
608406e2 | 725 | FIELD(GUEST_INTR_STATUS, guest_intr_status), |
22bd0358 NHE |
726 | FIELD(HOST_ES_SELECTOR, host_es_selector), |
727 | FIELD(HOST_CS_SELECTOR, host_cs_selector), | |
728 | FIELD(HOST_SS_SELECTOR, host_ss_selector), | |
729 | FIELD(HOST_DS_SELECTOR, host_ds_selector), | |
730 | FIELD(HOST_FS_SELECTOR, host_fs_selector), | |
731 | FIELD(HOST_GS_SELECTOR, host_gs_selector), | |
732 | FIELD(HOST_TR_SELECTOR, host_tr_selector), | |
733 | FIELD64(IO_BITMAP_A, io_bitmap_a), | |
734 | FIELD64(IO_BITMAP_B, io_bitmap_b), | |
735 | FIELD64(MSR_BITMAP, msr_bitmap), | |
736 | FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr), | |
737 | FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr), | |
738 | FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr), | |
739 | FIELD64(TSC_OFFSET, tsc_offset), | |
740 | FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr), | |
741 | FIELD64(APIC_ACCESS_ADDR, apic_access_addr), | |
705699a1 | 742 | FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr), |
22bd0358 | 743 | FIELD64(EPT_POINTER, ept_pointer), |
608406e2 WV |
744 | FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0), |
745 | FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1), | |
746 | FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2), | |
747 | FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3), | |
81dc01f7 | 748 | FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap), |
22bd0358 NHE |
749 | FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address), |
750 | FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer), | |
751 | FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl), | |
752 | FIELD64(GUEST_IA32_PAT, guest_ia32_pat), | |
753 | FIELD64(GUEST_IA32_EFER, guest_ia32_efer), | |
754 | FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl), | |
755 | FIELD64(GUEST_PDPTR0, guest_pdptr0), | |
756 | FIELD64(GUEST_PDPTR1, guest_pdptr1), | |
757 | FIELD64(GUEST_PDPTR2, guest_pdptr2), | |
758 | FIELD64(GUEST_PDPTR3, guest_pdptr3), | |
36be0b9d | 759 | FIELD64(GUEST_BNDCFGS, guest_bndcfgs), |
22bd0358 NHE |
760 | FIELD64(HOST_IA32_PAT, host_ia32_pat), |
761 | FIELD64(HOST_IA32_EFER, host_ia32_efer), | |
762 | FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl), | |
763 | FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control), | |
764 | FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control), | |
765 | FIELD(EXCEPTION_BITMAP, exception_bitmap), | |
766 | FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask), | |
767 | FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match), | |
768 | FIELD(CR3_TARGET_COUNT, cr3_target_count), | |
769 | FIELD(VM_EXIT_CONTROLS, vm_exit_controls), | |
770 | FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count), | |
771 | FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count), | |
772 | FIELD(VM_ENTRY_CONTROLS, vm_entry_controls), | |
773 | FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count), | |
774 | FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field), | |
775 | FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code), | |
776 | FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len), | |
777 | FIELD(TPR_THRESHOLD, tpr_threshold), | |
778 | FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control), | |
779 | FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error), | |
780 | FIELD(VM_EXIT_REASON, vm_exit_reason), | |
781 | FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info), | |
782 | FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code), | |
783 | FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field), | |
784 | FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code), | |
785 | FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len), | |
786 | FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info), | |
787 | FIELD(GUEST_ES_LIMIT, guest_es_limit), | |
788 | FIELD(GUEST_CS_LIMIT, guest_cs_limit), | |
789 | FIELD(GUEST_SS_LIMIT, guest_ss_limit), | |
790 | FIELD(GUEST_DS_LIMIT, guest_ds_limit), | |
791 | FIELD(GUEST_FS_LIMIT, guest_fs_limit), | |
792 | FIELD(GUEST_GS_LIMIT, guest_gs_limit), | |
793 | FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit), | |
794 | FIELD(GUEST_TR_LIMIT, guest_tr_limit), | |
795 | FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit), | |
796 | FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit), | |
797 | FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes), | |
798 | FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes), | |
799 | FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes), | |
800 | FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes), | |
801 | FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes), | |
802 | FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes), | |
803 | FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes), | |
804 | FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes), | |
805 | FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info), | |
806 | FIELD(GUEST_ACTIVITY_STATE, guest_activity_state), | |
807 | FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs), | |
808 | FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs), | |
0238ea91 | 809 | FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value), |
22bd0358 NHE |
810 | FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask), |
811 | FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask), | |
812 | FIELD(CR0_READ_SHADOW, cr0_read_shadow), | |
813 | FIELD(CR4_READ_SHADOW, cr4_read_shadow), | |
814 | FIELD(CR3_TARGET_VALUE0, cr3_target_value0), | |
815 | FIELD(CR3_TARGET_VALUE1, cr3_target_value1), | |
816 | FIELD(CR3_TARGET_VALUE2, cr3_target_value2), | |
817 | FIELD(CR3_TARGET_VALUE3, cr3_target_value3), | |
818 | FIELD(EXIT_QUALIFICATION, exit_qualification), | |
819 | FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address), | |
820 | FIELD(GUEST_CR0, guest_cr0), | |
821 | FIELD(GUEST_CR3, guest_cr3), | |
822 | FIELD(GUEST_CR4, guest_cr4), | |
823 | FIELD(GUEST_ES_BASE, guest_es_base), | |
824 | FIELD(GUEST_CS_BASE, guest_cs_base), | |
825 | FIELD(GUEST_SS_BASE, guest_ss_base), | |
826 | FIELD(GUEST_DS_BASE, guest_ds_base), | |
827 | FIELD(GUEST_FS_BASE, guest_fs_base), | |
828 | FIELD(GUEST_GS_BASE, guest_gs_base), | |
829 | FIELD(GUEST_LDTR_BASE, guest_ldtr_base), | |
830 | FIELD(GUEST_TR_BASE, guest_tr_base), | |
831 | FIELD(GUEST_GDTR_BASE, guest_gdtr_base), | |
832 | FIELD(GUEST_IDTR_BASE, guest_idtr_base), | |
833 | FIELD(GUEST_DR7, guest_dr7), | |
834 | FIELD(GUEST_RSP, guest_rsp), | |
835 | FIELD(GUEST_RIP, guest_rip), | |
836 | FIELD(GUEST_RFLAGS, guest_rflags), | |
837 | FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions), | |
838 | FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp), | |
839 | FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip), | |
840 | FIELD(HOST_CR0, host_cr0), | |
841 | FIELD(HOST_CR3, host_cr3), | |
842 | FIELD(HOST_CR4, host_cr4), | |
843 | FIELD(HOST_FS_BASE, host_fs_base), | |
844 | FIELD(HOST_GS_BASE, host_gs_base), | |
845 | FIELD(HOST_TR_BASE, host_tr_base), | |
846 | FIELD(HOST_GDTR_BASE, host_gdtr_base), | |
847 | FIELD(HOST_IDTR_BASE, host_idtr_base), | |
848 | FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp), | |
849 | FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip), | |
850 | FIELD(HOST_RSP, host_rsp), | |
851 | FIELD(HOST_RIP, host_rip), | |
852 | }; | |
22bd0358 NHE |
853 | |
854 | static inline short vmcs_field_to_offset(unsigned long field) | |
855 | { | |
a2ae9df7 PB |
856 | BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX); |
857 | ||
858 | if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) || | |
859 | vmcs_field_to_offset_table[field] == 0) | |
860 | return -ENOENT; | |
861 | ||
22bd0358 NHE |
862 | return vmcs_field_to_offset_table[field]; |
863 | } | |
864 | ||
a9d30f33 NHE |
865 | static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu) |
866 | { | |
4f2777bc | 867 | return to_vmx(vcpu)->nested.cached_vmcs12; |
a9d30f33 NHE |
868 | } |
869 | ||
870 | static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr) | |
871 | { | |
54bf36aa | 872 | struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT); |
32cad84f | 873 | if (is_error_page(page)) |
a9d30f33 | 874 | return NULL; |
32cad84f | 875 | |
a9d30f33 NHE |
876 | return page; |
877 | } | |
878 | ||
879 | static void nested_release_page(struct page *page) | |
880 | { | |
881 | kvm_release_page_dirty(page); | |
882 | } | |
883 | ||
884 | static void nested_release_page_clean(struct page *page) | |
885 | { | |
886 | kvm_release_page_clean(page); | |
887 | } | |
888 | ||
bfd0a56b | 889 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu); |
4e1096d2 | 890 | static u64 construct_eptp(unsigned long root_hpa); |
4610c9cc DX |
891 | static void kvm_cpu_vmxon(u64 addr); |
892 | static void kvm_cpu_vmxoff(void); | |
f53cd63c | 893 | static bool vmx_xsaves_supported(void); |
776e58ea | 894 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr); |
b246dd5d OW |
895 | static void vmx_set_segment(struct kvm_vcpu *vcpu, |
896 | struct kvm_segment *var, int seg); | |
897 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
898 | struct kvm_segment *var, int seg); | |
d99e4152 GN |
899 | static bool guest_state_valid(struct kvm_vcpu *vcpu); |
900 | static u32 vmx_segment_access_rights(struct kvm_segment *var); | |
c3114420 | 901 | static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx); |
16f5b903 | 902 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx); |
a255d479 | 903 | static int alloc_identity_pagetable(struct kvm *kvm); |
75880a01 | 904 | |
6aa8b732 AK |
905 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
906 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
d462b819 NHE |
907 | /* |
908 | * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed | |
909 | * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. | |
910 | */ | |
911 | static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); | |
3444d7da | 912 | static DEFINE_PER_CPU(struct desc_ptr, host_gdt); |
6aa8b732 | 913 | |
bf9f6ac8 FW |
914 | /* |
915 | * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we | |
916 | * can find which vCPU should be waken up. | |
917 | */ | |
918 | static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); | |
919 | static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); | |
920 | ||
3e7c73e9 AK |
921 | static unsigned long *vmx_io_bitmap_a; |
922 | static unsigned long *vmx_io_bitmap_b; | |
5897297b AK |
923 | static unsigned long *vmx_msr_bitmap_legacy; |
924 | static unsigned long *vmx_msr_bitmap_longmode; | |
8d14695f YZ |
925 | static unsigned long *vmx_msr_bitmap_legacy_x2apic; |
926 | static unsigned long *vmx_msr_bitmap_longmode_x2apic; | |
3af18d9c | 927 | static unsigned long *vmx_msr_bitmap_nested; |
4607c2d7 AG |
928 | static unsigned long *vmx_vmread_bitmap; |
929 | static unsigned long *vmx_vmwrite_bitmap; | |
fdef3ad1 | 930 | |
110312c8 | 931 | static bool cpu_has_load_ia32_efer; |
8bf00a52 | 932 | static bool cpu_has_load_perf_global_ctrl; |
110312c8 | 933 | |
2384d2b3 SY |
934 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
935 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
936 | ||
1c3d14fe | 937 | static struct vmcs_config { |
6aa8b732 AK |
938 | int size; |
939 | int order; | |
940 | u32 revision_id; | |
1c3d14fe YS |
941 | u32 pin_based_exec_ctrl; |
942 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 943 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
944 | u32 vmexit_ctrl; |
945 | u32 vmentry_ctrl; | |
946 | } vmcs_config; | |
6aa8b732 | 947 | |
efff9e53 | 948 | static struct vmx_capability { |
d56f546d SY |
949 | u32 ept; |
950 | u32 vpid; | |
951 | } vmx_capability; | |
952 | ||
6aa8b732 AK |
953 | #define VMX_SEGMENT_FIELD(seg) \ |
954 | [VCPU_SREG_##seg] = { \ | |
955 | .selector = GUEST_##seg##_SELECTOR, \ | |
956 | .base = GUEST_##seg##_BASE, \ | |
957 | .limit = GUEST_##seg##_LIMIT, \ | |
958 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
959 | } | |
960 | ||
772e0318 | 961 | static const struct kvm_vmx_segment_field { |
6aa8b732 AK |
962 | unsigned selector; |
963 | unsigned base; | |
964 | unsigned limit; | |
965 | unsigned ar_bytes; | |
966 | } kvm_vmx_segment_fields[] = { | |
967 | VMX_SEGMENT_FIELD(CS), | |
968 | VMX_SEGMENT_FIELD(DS), | |
969 | VMX_SEGMENT_FIELD(ES), | |
970 | VMX_SEGMENT_FIELD(FS), | |
971 | VMX_SEGMENT_FIELD(GS), | |
972 | VMX_SEGMENT_FIELD(SS), | |
973 | VMX_SEGMENT_FIELD(TR), | |
974 | VMX_SEGMENT_FIELD(LDTR), | |
975 | }; | |
976 | ||
26bb0981 AK |
977 | static u64 host_efer; |
978 | ||
6de4f3ad AK |
979 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu); |
980 | ||
4d56c8a7 | 981 | /* |
8c06585d | 982 | * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it |
4d56c8a7 AK |
983 | * away by decrementing the array size. |
984 | */ | |
6aa8b732 | 985 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 986 | #ifdef CONFIG_X86_64 |
44ea2b17 | 987 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, |
6aa8b732 | 988 | #endif |
8c06585d | 989 | MSR_EFER, MSR_TSC_AUX, MSR_STAR, |
6aa8b732 | 990 | }; |
6aa8b732 | 991 | |
5bb16016 | 992 | static inline bool is_exception_n(u32 intr_info, u8 vector) |
6aa8b732 AK |
993 | { |
994 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
995 | INTR_INFO_VALID_MASK)) == | |
5bb16016 JK |
996 | (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK); |
997 | } | |
998 | ||
6f05485d JK |
999 | static inline bool is_debug(u32 intr_info) |
1000 | { | |
1001 | return is_exception_n(intr_info, DB_VECTOR); | |
1002 | } | |
1003 | ||
1004 | static inline bool is_breakpoint(u32 intr_info) | |
1005 | { | |
1006 | return is_exception_n(intr_info, BP_VECTOR); | |
1007 | } | |
1008 | ||
5bb16016 JK |
1009 | static inline bool is_page_fault(u32 intr_info) |
1010 | { | |
1011 | return is_exception_n(intr_info, PF_VECTOR); | |
6aa8b732 AK |
1012 | } |
1013 | ||
31299944 | 1014 | static inline bool is_no_device(u32 intr_info) |
2ab455cc | 1015 | { |
5bb16016 | 1016 | return is_exception_n(intr_info, NM_VECTOR); |
2ab455cc AL |
1017 | } |
1018 | ||
31299944 | 1019 | static inline bool is_invalid_opcode(u32 intr_info) |
7aa81cc0 | 1020 | { |
5bb16016 | 1021 | return is_exception_n(intr_info, UD_VECTOR); |
7aa81cc0 AL |
1022 | } |
1023 | ||
31299944 | 1024 | static inline bool is_external_interrupt(u32 intr_info) |
6aa8b732 AK |
1025 | { |
1026 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
1027 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
1028 | } | |
1029 | ||
31299944 | 1030 | static inline bool is_machine_check(u32 intr_info) |
a0861c02 AK |
1031 | { |
1032 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
1033 | INTR_INFO_VALID_MASK)) == | |
1034 | (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK); | |
1035 | } | |
1036 | ||
31299944 | 1037 | static inline bool cpu_has_vmx_msr_bitmap(void) |
25c5f225 | 1038 | { |
04547156 | 1039 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; |
25c5f225 SY |
1040 | } |
1041 | ||
31299944 | 1042 | static inline bool cpu_has_vmx_tpr_shadow(void) |
6e5d865c | 1043 | { |
04547156 | 1044 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; |
6e5d865c YS |
1045 | } |
1046 | ||
35754c98 | 1047 | static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu) |
6e5d865c | 1048 | { |
35754c98 | 1049 | return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu); |
6e5d865c YS |
1050 | } |
1051 | ||
31299944 | 1052 | static inline bool cpu_has_secondary_exec_ctrls(void) |
f78e0e2e | 1053 | { |
04547156 SY |
1054 | return vmcs_config.cpu_based_exec_ctrl & |
1055 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
f78e0e2e SY |
1056 | } |
1057 | ||
774ead3a | 1058 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 1059 | { |
04547156 SY |
1060 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1061 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
1062 | } | |
1063 | ||
8d14695f YZ |
1064 | static inline bool cpu_has_vmx_virtualize_x2apic_mode(void) |
1065 | { | |
1066 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1067 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
1068 | } | |
1069 | ||
83d4c286 YZ |
1070 | static inline bool cpu_has_vmx_apic_register_virt(void) |
1071 | { | |
1072 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1073 | SECONDARY_EXEC_APIC_REGISTER_VIRT; | |
1074 | } | |
1075 | ||
c7c9c56c YZ |
1076 | static inline bool cpu_has_vmx_virtual_intr_delivery(void) |
1077 | { | |
1078 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1079 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY; | |
1080 | } | |
1081 | ||
64672c95 YJ |
1082 | /* |
1083 | * Comment's format: document - errata name - stepping - processor name. | |
1084 | * Refer from | |
1085 | * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp | |
1086 | */ | |
1087 | static u32 vmx_preemption_cpu_tfms[] = { | |
1088 | /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ | |
1089 | 0x000206E6, | |
1090 | /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ | |
1091 | /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ | |
1092 | /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
1093 | 0x00020652, | |
1094 | /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
1095 | 0x00020655, | |
1096 | /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ | |
1097 | /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ | |
1098 | /* | |
1099 | * 320767.pdf - AAP86 - B1 - | |
1100 | * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile | |
1101 | */ | |
1102 | 0x000106E5, | |
1103 | /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ | |
1104 | 0x000106A0, | |
1105 | /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ | |
1106 | 0x000106A1, | |
1107 | /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ | |
1108 | 0x000106A4, | |
1109 | /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ | |
1110 | /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ | |
1111 | /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ | |
1112 | 0x000106A5, | |
1113 | }; | |
1114 | ||
1115 | static inline bool cpu_has_broken_vmx_preemption_timer(void) | |
1116 | { | |
1117 | u32 eax = cpuid_eax(0x00000001), i; | |
1118 | ||
1119 | /* Clear the reserved bits */ | |
1120 | eax &= ~(0x3U << 14 | 0xfU << 28); | |
03f6a22a | 1121 | for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) |
64672c95 YJ |
1122 | if (eax == vmx_preemption_cpu_tfms[i]) |
1123 | return true; | |
1124 | ||
1125 | return false; | |
1126 | } | |
1127 | ||
1128 | static inline bool cpu_has_vmx_preemption_timer(void) | |
1129 | { | |
64672c95 YJ |
1130 | return vmcs_config.pin_based_exec_ctrl & |
1131 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1132 | } | |
1133 | ||
01e439be YZ |
1134 | static inline bool cpu_has_vmx_posted_intr(void) |
1135 | { | |
d6a858d1 PB |
1136 | return IS_ENABLED(CONFIG_X86_LOCAL_APIC) && |
1137 | vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR; | |
01e439be YZ |
1138 | } |
1139 | ||
1140 | static inline bool cpu_has_vmx_apicv(void) | |
1141 | { | |
1142 | return cpu_has_vmx_apic_register_virt() && | |
1143 | cpu_has_vmx_virtual_intr_delivery() && | |
1144 | cpu_has_vmx_posted_intr(); | |
1145 | } | |
1146 | ||
04547156 SY |
1147 | static inline bool cpu_has_vmx_flexpriority(void) |
1148 | { | |
1149 | return cpu_has_vmx_tpr_shadow() && | |
1150 | cpu_has_vmx_virtualize_apic_accesses(); | |
f78e0e2e SY |
1151 | } |
1152 | ||
e799794e MT |
1153 | static inline bool cpu_has_vmx_ept_execute_only(void) |
1154 | { | |
31299944 | 1155 | return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT; |
e799794e MT |
1156 | } |
1157 | ||
e799794e MT |
1158 | static inline bool cpu_has_vmx_ept_2m_page(void) |
1159 | { | |
31299944 | 1160 | return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT; |
e799794e MT |
1161 | } |
1162 | ||
878403b7 SY |
1163 | static inline bool cpu_has_vmx_ept_1g_page(void) |
1164 | { | |
31299944 | 1165 | return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT; |
878403b7 SY |
1166 | } |
1167 | ||
4bc9b982 SY |
1168 | static inline bool cpu_has_vmx_ept_4levels(void) |
1169 | { | |
1170 | return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT; | |
1171 | } | |
1172 | ||
83c3a331 XH |
1173 | static inline bool cpu_has_vmx_ept_ad_bits(void) |
1174 | { | |
1175 | return vmx_capability.ept & VMX_EPT_AD_BIT; | |
1176 | } | |
1177 | ||
31299944 | 1178 | static inline bool cpu_has_vmx_invept_context(void) |
d56f546d | 1179 | { |
31299944 | 1180 | return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT; |
d56f546d SY |
1181 | } |
1182 | ||
31299944 | 1183 | static inline bool cpu_has_vmx_invept_global(void) |
d56f546d | 1184 | { |
31299944 | 1185 | return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; |
d56f546d SY |
1186 | } |
1187 | ||
518c8aee GJ |
1188 | static inline bool cpu_has_vmx_invvpid_single(void) |
1189 | { | |
1190 | return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT; | |
1191 | } | |
1192 | ||
b9d762fa GJ |
1193 | static inline bool cpu_has_vmx_invvpid_global(void) |
1194 | { | |
1195 | return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; | |
1196 | } | |
1197 | ||
31299944 | 1198 | static inline bool cpu_has_vmx_ept(void) |
d56f546d | 1199 | { |
04547156 SY |
1200 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1201 | SECONDARY_EXEC_ENABLE_EPT; | |
d56f546d SY |
1202 | } |
1203 | ||
31299944 | 1204 | static inline bool cpu_has_vmx_unrestricted_guest(void) |
3a624e29 NK |
1205 | { |
1206 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1207 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
1208 | } | |
1209 | ||
31299944 | 1210 | static inline bool cpu_has_vmx_ple(void) |
4b8d54f9 ZE |
1211 | { |
1212 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1213 | SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
1214 | } | |
1215 | ||
35754c98 | 1216 | static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) |
f78e0e2e | 1217 | { |
35754c98 | 1218 | return flexpriority_enabled && lapic_in_kernel(vcpu); |
f78e0e2e SY |
1219 | } |
1220 | ||
31299944 | 1221 | static inline bool cpu_has_vmx_vpid(void) |
2384d2b3 | 1222 | { |
04547156 SY |
1223 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1224 | SECONDARY_EXEC_ENABLE_VPID; | |
2384d2b3 SY |
1225 | } |
1226 | ||
31299944 | 1227 | static inline bool cpu_has_vmx_rdtscp(void) |
4e47c7a6 SY |
1228 | { |
1229 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1230 | SECONDARY_EXEC_RDTSCP; | |
1231 | } | |
1232 | ||
ad756a16 MJ |
1233 | static inline bool cpu_has_vmx_invpcid(void) |
1234 | { | |
1235 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1236 | SECONDARY_EXEC_ENABLE_INVPCID; | |
1237 | } | |
1238 | ||
31299944 | 1239 | static inline bool cpu_has_virtual_nmis(void) |
f08864b4 SY |
1240 | { |
1241 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; | |
1242 | } | |
1243 | ||
f5f48ee1 SY |
1244 | static inline bool cpu_has_vmx_wbinvd_exit(void) |
1245 | { | |
1246 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1247 | SECONDARY_EXEC_WBINVD_EXITING; | |
1248 | } | |
1249 | ||
abc4fc58 AG |
1250 | static inline bool cpu_has_vmx_shadow_vmcs(void) |
1251 | { | |
1252 | u64 vmx_msr; | |
1253 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
1254 | /* check if the cpu supports writing r/o exit information fields */ | |
1255 | if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) | |
1256 | return false; | |
1257 | ||
1258 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1259 | SECONDARY_EXEC_SHADOW_VMCS; | |
1260 | } | |
1261 | ||
843e4330 KH |
1262 | static inline bool cpu_has_vmx_pml(void) |
1263 | { | |
1264 | return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML; | |
1265 | } | |
1266 | ||
64903d61 HZ |
1267 | static inline bool cpu_has_vmx_tsc_scaling(void) |
1268 | { | |
1269 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1270 | SECONDARY_EXEC_TSC_SCALING; | |
1271 | } | |
1272 | ||
04547156 SY |
1273 | static inline bool report_flexpriority(void) |
1274 | { | |
1275 | return flexpriority_enabled; | |
1276 | } | |
1277 | ||
fe3ef05c NHE |
1278 | static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit) |
1279 | { | |
1280 | return vmcs12->cpu_based_vm_exec_control & bit; | |
1281 | } | |
1282 | ||
1283 | static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit) | |
1284 | { | |
1285 | return (vmcs12->cpu_based_vm_exec_control & | |
1286 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && | |
1287 | (vmcs12->secondary_vm_exec_control & bit); | |
1288 | } | |
1289 | ||
f5c4368f | 1290 | static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12) |
644d711a NHE |
1291 | { |
1292 | return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS; | |
1293 | } | |
1294 | ||
f4124500 JK |
1295 | static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12) |
1296 | { | |
1297 | return vmcs12->pin_based_vm_exec_control & | |
1298 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1299 | } | |
1300 | ||
155a97a3 NHE |
1301 | static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12) |
1302 | { | |
1303 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT); | |
1304 | } | |
1305 | ||
81dc01f7 WL |
1306 | static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12) |
1307 | { | |
1308 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) && | |
1309 | vmx_xsaves_supported(); | |
1310 | } | |
1311 | ||
f2b93280 WV |
1312 | static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12) |
1313 | { | |
1314 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); | |
1315 | } | |
1316 | ||
5c614b35 WL |
1317 | static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12) |
1318 | { | |
1319 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID); | |
1320 | } | |
1321 | ||
82f0dd4b WV |
1322 | static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12) |
1323 | { | |
1324 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT); | |
1325 | } | |
1326 | ||
608406e2 WV |
1327 | static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12) |
1328 | { | |
1329 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
1330 | } | |
1331 | ||
705699a1 WV |
1332 | static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12) |
1333 | { | |
1334 | return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR; | |
1335 | } | |
1336 | ||
644d711a NHE |
1337 | static inline bool is_exception(u32 intr_info) |
1338 | { | |
1339 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
1340 | == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK); | |
1341 | } | |
1342 | ||
533558bc JK |
1343 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
1344 | u32 exit_intr_info, | |
1345 | unsigned long exit_qualification); | |
7c177938 NHE |
1346 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, |
1347 | struct vmcs12 *vmcs12, | |
1348 | u32 reason, unsigned long qualification); | |
1349 | ||
8b9cf98c | 1350 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
1351 | { |
1352 | int i; | |
1353 | ||
a2fa3e9f | 1354 | for (i = 0; i < vmx->nmsrs; ++i) |
26bb0981 | 1355 | if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) |
a75beee6 ED |
1356 | return i; |
1357 | return -1; | |
1358 | } | |
1359 | ||
2384d2b3 SY |
1360 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
1361 | { | |
1362 | struct { | |
1363 | u64 vpid : 16; | |
1364 | u64 rsvd : 48; | |
1365 | u64 gva; | |
1366 | } operand = { vpid, 0, gva }; | |
1367 | ||
4ecac3fd | 1368 | asm volatile (__ex(ASM_VMX_INVVPID) |
2384d2b3 SY |
1369 | /* CF==1 or ZF==1 --> rc = -1 */ |
1370 | "; ja 1f ; ud2 ; 1:" | |
1371 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
1372 | } | |
1373 | ||
1439442c SY |
1374 | static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
1375 | { | |
1376 | struct { | |
1377 | u64 eptp, gpa; | |
1378 | } operand = {eptp, gpa}; | |
1379 | ||
4ecac3fd | 1380 | asm volatile (__ex(ASM_VMX_INVEPT) |
1439442c SY |
1381 | /* CF==1 or ZF==1 --> rc = -1 */ |
1382 | "; ja 1f ; ud2 ; 1:\n" | |
1383 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
1384 | } | |
1385 | ||
26bb0981 | 1386 | static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
1387 | { |
1388 | int i; | |
1389 | ||
8b9cf98c | 1390 | i = __find_msr_index(vmx, msr); |
a75beee6 | 1391 | if (i >= 0) |
a2fa3e9f | 1392 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 1393 | return NULL; |
7725f0ba AK |
1394 | } |
1395 | ||
6aa8b732 AK |
1396 | static void vmcs_clear(struct vmcs *vmcs) |
1397 | { | |
1398 | u64 phys_addr = __pa(vmcs); | |
1399 | u8 error; | |
1400 | ||
4ecac3fd | 1401 | asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
16d8f72f | 1402 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
6aa8b732 AK |
1403 | : "cc", "memory"); |
1404 | if (error) | |
1405 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
1406 | vmcs, phys_addr); | |
1407 | } | |
1408 | ||
d462b819 NHE |
1409 | static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) |
1410 | { | |
1411 | vmcs_clear(loaded_vmcs->vmcs); | |
1412 | loaded_vmcs->cpu = -1; | |
1413 | loaded_vmcs->launched = 0; | |
1414 | } | |
1415 | ||
7725b894 DX |
1416 | static void vmcs_load(struct vmcs *vmcs) |
1417 | { | |
1418 | u64 phys_addr = __pa(vmcs); | |
1419 | u8 error; | |
1420 | ||
1421 | asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" | |
16d8f72f | 1422 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
7725b894 DX |
1423 | : "cc", "memory"); |
1424 | if (error) | |
2844d849 | 1425 | printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n", |
7725b894 DX |
1426 | vmcs, phys_addr); |
1427 | } | |
1428 | ||
2965faa5 | 1429 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
1430 | /* |
1431 | * This bitmap is used to indicate whether the vmclear | |
1432 | * operation is enabled on all cpus. All disabled by | |
1433 | * default. | |
1434 | */ | |
1435 | static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE; | |
1436 | ||
1437 | static inline void crash_enable_local_vmclear(int cpu) | |
1438 | { | |
1439 | cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1440 | } | |
1441 | ||
1442 | static inline void crash_disable_local_vmclear(int cpu) | |
1443 | { | |
1444 | cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1445 | } | |
1446 | ||
1447 | static inline int crash_local_vmclear_enabled(int cpu) | |
1448 | { | |
1449 | return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1450 | } | |
1451 | ||
1452 | static void crash_vmclear_local_loaded_vmcss(void) | |
1453 | { | |
1454 | int cpu = raw_smp_processor_id(); | |
1455 | struct loaded_vmcs *v; | |
1456 | ||
1457 | if (!crash_local_vmclear_enabled(cpu)) | |
1458 | return; | |
1459 | ||
1460 | list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), | |
1461 | loaded_vmcss_on_cpu_link) | |
1462 | vmcs_clear(v->vmcs); | |
1463 | } | |
1464 | #else | |
1465 | static inline void crash_enable_local_vmclear(int cpu) { } | |
1466 | static inline void crash_disable_local_vmclear(int cpu) { } | |
2965faa5 | 1467 | #endif /* CONFIG_KEXEC_CORE */ |
8f536b76 | 1468 | |
d462b819 | 1469 | static void __loaded_vmcs_clear(void *arg) |
6aa8b732 | 1470 | { |
d462b819 | 1471 | struct loaded_vmcs *loaded_vmcs = arg; |
d3b2c338 | 1472 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 1473 | |
d462b819 NHE |
1474 | if (loaded_vmcs->cpu != cpu) |
1475 | return; /* vcpu migration can race with cpu offline */ | |
1476 | if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) | |
6aa8b732 | 1477 | per_cpu(current_vmcs, cpu) = NULL; |
8f536b76 | 1478 | crash_disable_local_vmclear(cpu); |
d462b819 | 1479 | list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); |
5a560f8b XG |
1480 | |
1481 | /* | |
1482 | * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link | |
1483 | * is before setting loaded_vmcs->vcpu to -1 which is done in | |
1484 | * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist | |
1485 | * then adds the vmcs into percpu list before it is deleted. | |
1486 | */ | |
1487 | smp_wmb(); | |
1488 | ||
d462b819 | 1489 | loaded_vmcs_init(loaded_vmcs); |
8f536b76 | 1490 | crash_enable_local_vmclear(cpu); |
6aa8b732 AK |
1491 | } |
1492 | ||
d462b819 | 1493 | static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) |
8d0be2b3 | 1494 | { |
e6c7d321 XG |
1495 | int cpu = loaded_vmcs->cpu; |
1496 | ||
1497 | if (cpu != -1) | |
1498 | smp_call_function_single(cpu, | |
1499 | __loaded_vmcs_clear, loaded_vmcs, 1); | |
8d0be2b3 AK |
1500 | } |
1501 | ||
dd5f5341 | 1502 | static inline void vpid_sync_vcpu_single(int vpid) |
2384d2b3 | 1503 | { |
dd5f5341 | 1504 | if (vpid == 0) |
2384d2b3 SY |
1505 | return; |
1506 | ||
518c8aee | 1507 | if (cpu_has_vmx_invvpid_single()) |
dd5f5341 | 1508 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0); |
2384d2b3 SY |
1509 | } |
1510 | ||
b9d762fa GJ |
1511 | static inline void vpid_sync_vcpu_global(void) |
1512 | { | |
1513 | if (cpu_has_vmx_invvpid_global()) | |
1514 | __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0); | |
1515 | } | |
1516 | ||
dd5f5341 | 1517 | static inline void vpid_sync_context(int vpid) |
b9d762fa GJ |
1518 | { |
1519 | if (cpu_has_vmx_invvpid_single()) | |
dd5f5341 | 1520 | vpid_sync_vcpu_single(vpid); |
b9d762fa GJ |
1521 | else |
1522 | vpid_sync_vcpu_global(); | |
1523 | } | |
1524 | ||
1439442c SY |
1525 | static inline void ept_sync_global(void) |
1526 | { | |
1527 | if (cpu_has_vmx_invept_global()) | |
1528 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); | |
1529 | } | |
1530 | ||
1531 | static inline void ept_sync_context(u64 eptp) | |
1532 | { | |
089d034e | 1533 | if (enable_ept) { |
1439442c SY |
1534 | if (cpu_has_vmx_invept_context()) |
1535 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
1536 | else | |
1537 | ept_sync_global(); | |
1538 | } | |
1539 | } | |
1540 | ||
8a86aea9 PB |
1541 | static __always_inline void vmcs_check16(unsigned long field) |
1542 | { | |
1543 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000, | |
1544 | "16-bit accessor invalid for 64-bit field"); | |
1545 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1546 | "16-bit accessor invalid for 64-bit high field"); | |
1547 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1548 | "16-bit accessor invalid for 32-bit high field"); | |
1549 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1550 | "16-bit accessor invalid for natural width field"); | |
1551 | } | |
1552 | ||
1553 | static __always_inline void vmcs_check32(unsigned long field) | |
1554 | { | |
1555 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1556 | "32-bit accessor invalid for 16-bit field"); | |
1557 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1558 | "32-bit accessor invalid for natural width field"); | |
1559 | } | |
1560 | ||
1561 | static __always_inline void vmcs_check64(unsigned long field) | |
1562 | { | |
1563 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1564 | "64-bit accessor invalid for 16-bit field"); | |
1565 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1566 | "64-bit accessor invalid for 64-bit high field"); | |
1567 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1568 | "64-bit accessor invalid for 32-bit field"); | |
1569 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1570 | "64-bit accessor invalid for natural width field"); | |
1571 | } | |
1572 | ||
1573 | static __always_inline void vmcs_checkl(unsigned long field) | |
1574 | { | |
1575 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1576 | "Natural width accessor invalid for 16-bit field"); | |
1577 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000, | |
1578 | "Natural width accessor invalid for 64-bit field"); | |
1579 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1580 | "Natural width accessor invalid for 64-bit high field"); | |
1581 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1582 | "Natural width accessor invalid for 32-bit field"); | |
1583 | } | |
1584 | ||
1585 | static __always_inline unsigned long __vmcs_readl(unsigned long field) | |
6aa8b732 | 1586 | { |
5e520e62 | 1587 | unsigned long value; |
6aa8b732 | 1588 | |
5e520e62 AK |
1589 | asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0") |
1590 | : "=a"(value) : "d"(field) : "cc"); | |
6aa8b732 AK |
1591 | return value; |
1592 | } | |
1593 | ||
96304217 | 1594 | static __always_inline u16 vmcs_read16(unsigned long field) |
6aa8b732 | 1595 | { |
8a86aea9 PB |
1596 | vmcs_check16(field); |
1597 | return __vmcs_readl(field); | |
6aa8b732 AK |
1598 | } |
1599 | ||
96304217 | 1600 | static __always_inline u32 vmcs_read32(unsigned long field) |
6aa8b732 | 1601 | { |
8a86aea9 PB |
1602 | vmcs_check32(field); |
1603 | return __vmcs_readl(field); | |
6aa8b732 AK |
1604 | } |
1605 | ||
96304217 | 1606 | static __always_inline u64 vmcs_read64(unsigned long field) |
6aa8b732 | 1607 | { |
8a86aea9 | 1608 | vmcs_check64(field); |
05b3e0c2 | 1609 | #ifdef CONFIG_X86_64 |
8a86aea9 | 1610 | return __vmcs_readl(field); |
6aa8b732 | 1611 | #else |
8a86aea9 | 1612 | return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32); |
6aa8b732 AK |
1613 | #endif |
1614 | } | |
1615 | ||
8a86aea9 PB |
1616 | static __always_inline unsigned long vmcs_readl(unsigned long field) |
1617 | { | |
1618 | vmcs_checkl(field); | |
1619 | return __vmcs_readl(field); | |
1620 | } | |
1621 | ||
e52de1b8 AK |
1622 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
1623 | { | |
1624 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
1625 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
1626 | dump_stack(); | |
1627 | } | |
1628 | ||
8a86aea9 | 1629 | static __always_inline void __vmcs_writel(unsigned long field, unsigned long value) |
6aa8b732 AK |
1630 | { |
1631 | u8 error; | |
1632 | ||
4ecac3fd | 1633 | asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
d77c26fc | 1634 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
1635 | if (unlikely(error)) |
1636 | vmwrite_error(field, value); | |
6aa8b732 AK |
1637 | } |
1638 | ||
8a86aea9 | 1639 | static __always_inline void vmcs_write16(unsigned long field, u16 value) |
6aa8b732 | 1640 | { |
8a86aea9 PB |
1641 | vmcs_check16(field); |
1642 | __vmcs_writel(field, value); | |
6aa8b732 AK |
1643 | } |
1644 | ||
8a86aea9 | 1645 | static __always_inline void vmcs_write32(unsigned long field, u32 value) |
6aa8b732 | 1646 | { |
8a86aea9 PB |
1647 | vmcs_check32(field); |
1648 | __vmcs_writel(field, value); | |
6aa8b732 AK |
1649 | } |
1650 | ||
8a86aea9 | 1651 | static __always_inline void vmcs_write64(unsigned long field, u64 value) |
6aa8b732 | 1652 | { |
8a86aea9 PB |
1653 | vmcs_check64(field); |
1654 | __vmcs_writel(field, value); | |
7682f2d0 | 1655 | #ifndef CONFIG_X86_64 |
6aa8b732 | 1656 | asm volatile (""); |
8a86aea9 | 1657 | __vmcs_writel(field+1, value >> 32); |
6aa8b732 AK |
1658 | #endif |
1659 | } | |
1660 | ||
8a86aea9 | 1661 | static __always_inline void vmcs_writel(unsigned long field, unsigned long value) |
2ab455cc | 1662 | { |
8a86aea9 PB |
1663 | vmcs_checkl(field); |
1664 | __vmcs_writel(field, value); | |
2ab455cc AL |
1665 | } |
1666 | ||
8a86aea9 | 1667 | static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask) |
2ab455cc | 1668 | { |
8a86aea9 PB |
1669 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000, |
1670 | "vmcs_clear_bits does not support 64-bit fields"); | |
1671 | __vmcs_writel(field, __vmcs_readl(field) & ~mask); | |
2ab455cc AL |
1672 | } |
1673 | ||
8a86aea9 | 1674 | static __always_inline void vmcs_set_bits(unsigned long field, u32 mask) |
2ab455cc | 1675 | { |
8a86aea9 PB |
1676 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000, |
1677 | "vmcs_set_bits does not support 64-bit fields"); | |
1678 | __vmcs_writel(field, __vmcs_readl(field) | mask); | |
2ab455cc AL |
1679 | } |
1680 | ||
8391ce44 PB |
1681 | static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx) |
1682 | { | |
1683 | vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS); | |
1684 | } | |
1685 | ||
2961e876 GN |
1686 | static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val) |
1687 | { | |
1688 | vmcs_write32(VM_ENTRY_CONTROLS, val); | |
1689 | vmx->vm_entry_controls_shadow = val; | |
1690 | } | |
1691 | ||
1692 | static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1693 | { | |
1694 | if (vmx->vm_entry_controls_shadow != val) | |
1695 | vm_entry_controls_init(vmx, val); | |
1696 | } | |
1697 | ||
1698 | static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx) | |
1699 | { | |
1700 | return vmx->vm_entry_controls_shadow; | |
1701 | } | |
1702 | ||
1703 | ||
1704 | static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1705 | { | |
1706 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val); | |
1707 | } | |
1708 | ||
1709 | static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1710 | { | |
1711 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val); | |
1712 | } | |
1713 | ||
8391ce44 PB |
1714 | static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx) |
1715 | { | |
1716 | vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS); | |
1717 | } | |
1718 | ||
2961e876 GN |
1719 | static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val) |
1720 | { | |
1721 | vmcs_write32(VM_EXIT_CONTROLS, val); | |
1722 | vmx->vm_exit_controls_shadow = val; | |
1723 | } | |
1724 | ||
1725 | static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1726 | { | |
1727 | if (vmx->vm_exit_controls_shadow != val) | |
1728 | vm_exit_controls_init(vmx, val); | |
1729 | } | |
1730 | ||
1731 | static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx) | |
1732 | { | |
1733 | return vmx->vm_exit_controls_shadow; | |
1734 | } | |
1735 | ||
1736 | ||
1737 | static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1738 | { | |
1739 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val); | |
1740 | } | |
1741 | ||
1742 | static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1743 | { | |
1744 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val); | |
1745 | } | |
1746 | ||
2fb92db1 AK |
1747 | static void vmx_segment_cache_clear(struct vcpu_vmx *vmx) |
1748 | { | |
1749 | vmx->segment_cache.bitmask = 0; | |
1750 | } | |
1751 | ||
1752 | static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, | |
1753 | unsigned field) | |
1754 | { | |
1755 | bool ret; | |
1756 | u32 mask = 1 << (seg * SEG_FIELD_NR + field); | |
1757 | ||
1758 | if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) { | |
1759 | vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS); | |
1760 | vmx->segment_cache.bitmask = 0; | |
1761 | } | |
1762 | ret = vmx->segment_cache.bitmask & mask; | |
1763 | vmx->segment_cache.bitmask |= mask; | |
1764 | return ret; | |
1765 | } | |
1766 | ||
1767 | static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) | |
1768 | { | |
1769 | u16 *p = &vmx->segment_cache.seg[seg].selector; | |
1770 | ||
1771 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) | |
1772 | *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); | |
1773 | return *p; | |
1774 | } | |
1775 | ||
1776 | static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) | |
1777 | { | |
1778 | ulong *p = &vmx->segment_cache.seg[seg].base; | |
1779 | ||
1780 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) | |
1781 | *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); | |
1782 | return *p; | |
1783 | } | |
1784 | ||
1785 | static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) | |
1786 | { | |
1787 | u32 *p = &vmx->segment_cache.seg[seg].limit; | |
1788 | ||
1789 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) | |
1790 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); | |
1791 | return *p; | |
1792 | } | |
1793 | ||
1794 | static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) | |
1795 | { | |
1796 | u32 *p = &vmx->segment_cache.seg[seg].ar; | |
1797 | ||
1798 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) | |
1799 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); | |
1800 | return *p; | |
1801 | } | |
1802 | ||
abd3f2d6 AK |
1803 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
1804 | { | |
1805 | u32 eb; | |
1806 | ||
fd7373cc | 1807 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | |
54a20552 | 1808 | (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR); |
fd7373cc JK |
1809 | if ((vcpu->guest_debug & |
1810 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == | |
1811 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) | |
1812 | eb |= 1u << BP_VECTOR; | |
7ffd92c5 | 1813 | if (to_vmx(vcpu)->rmode.vm86_active) |
abd3f2d6 | 1814 | eb = ~0; |
089d034e | 1815 | if (enable_ept) |
1439442c | 1816 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ |
02daab21 AK |
1817 | if (vcpu->fpu_active) |
1818 | eb &= ~(1u << NM_VECTOR); | |
36cf24e0 NHE |
1819 | |
1820 | /* When we are running a nested L2 guest and L1 specified for it a | |
1821 | * certain exception bitmap, we must trap the same exceptions and pass | |
1822 | * them to L1. When running L2, we will only handle the exceptions | |
1823 | * specified above if L1 did not want them. | |
1824 | */ | |
1825 | if (is_guest_mode(vcpu)) | |
1826 | eb |= get_vmcs12(vcpu)->exception_bitmap; | |
1827 | ||
abd3f2d6 AK |
1828 | vmcs_write32(EXCEPTION_BITMAP, eb); |
1829 | } | |
1830 | ||
2961e876 GN |
1831 | static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
1832 | unsigned long entry, unsigned long exit) | |
8bf00a52 | 1833 | { |
2961e876 GN |
1834 | vm_entry_controls_clearbit(vmx, entry); |
1835 | vm_exit_controls_clearbit(vmx, exit); | |
8bf00a52 GN |
1836 | } |
1837 | ||
61d2ef2c AK |
1838 | static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) |
1839 | { | |
1840 | unsigned i; | |
1841 | struct msr_autoload *m = &vmx->msr_autoload; | |
1842 | ||
8bf00a52 GN |
1843 | switch (msr) { |
1844 | case MSR_EFER: | |
1845 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
1846 | clear_atomic_switch_msr_special(vmx, |
1847 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
1848 | VM_EXIT_LOAD_IA32_EFER); |
1849 | return; | |
1850 | } | |
1851 | break; | |
1852 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
1853 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 1854 | clear_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
1855 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
1856 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
1857 | return; | |
1858 | } | |
1859 | break; | |
110312c8 AK |
1860 | } |
1861 | ||
61d2ef2c AK |
1862 | for (i = 0; i < m->nr; ++i) |
1863 | if (m->guest[i].index == msr) | |
1864 | break; | |
1865 | ||
1866 | if (i == m->nr) | |
1867 | return; | |
1868 | --m->nr; | |
1869 | m->guest[i] = m->guest[m->nr]; | |
1870 | m->host[i] = m->host[m->nr]; | |
1871 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
1872 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
1873 | } | |
1874 | ||
2961e876 GN |
1875 | static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
1876 | unsigned long entry, unsigned long exit, | |
1877 | unsigned long guest_val_vmcs, unsigned long host_val_vmcs, | |
1878 | u64 guest_val, u64 host_val) | |
8bf00a52 GN |
1879 | { |
1880 | vmcs_write64(guest_val_vmcs, guest_val); | |
1881 | vmcs_write64(host_val_vmcs, host_val); | |
2961e876 GN |
1882 | vm_entry_controls_setbit(vmx, entry); |
1883 | vm_exit_controls_setbit(vmx, exit); | |
8bf00a52 GN |
1884 | } |
1885 | ||
61d2ef2c AK |
1886 | static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, |
1887 | u64 guest_val, u64 host_val) | |
1888 | { | |
1889 | unsigned i; | |
1890 | struct msr_autoload *m = &vmx->msr_autoload; | |
1891 | ||
8bf00a52 GN |
1892 | switch (msr) { |
1893 | case MSR_EFER: | |
1894 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
1895 | add_atomic_switch_msr_special(vmx, |
1896 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
1897 | VM_EXIT_LOAD_IA32_EFER, |
1898 | GUEST_IA32_EFER, | |
1899 | HOST_IA32_EFER, | |
1900 | guest_val, host_val); | |
1901 | return; | |
1902 | } | |
1903 | break; | |
1904 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
1905 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 1906 | add_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
1907 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
1908 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, | |
1909 | GUEST_IA32_PERF_GLOBAL_CTRL, | |
1910 | HOST_IA32_PERF_GLOBAL_CTRL, | |
1911 | guest_val, host_val); | |
1912 | return; | |
1913 | } | |
1914 | break; | |
7099e2e1 RK |
1915 | case MSR_IA32_PEBS_ENABLE: |
1916 | /* PEBS needs a quiescent period after being disabled (to write | |
1917 | * a record). Disabling PEBS through VMX MSR swapping doesn't | |
1918 | * provide that period, so a CPU could write host's record into | |
1919 | * guest's memory. | |
1920 | */ | |
1921 | wrmsrl(MSR_IA32_PEBS_ENABLE, 0); | |
110312c8 AK |
1922 | } |
1923 | ||
61d2ef2c AK |
1924 | for (i = 0; i < m->nr; ++i) |
1925 | if (m->guest[i].index == msr) | |
1926 | break; | |
1927 | ||
e7fc6f93 | 1928 | if (i == NR_AUTOLOAD_MSRS) { |
60266204 | 1929 | printk_once(KERN_WARNING "Not enough msr switch entries. " |
e7fc6f93 GN |
1930 | "Can't add msr %x\n", msr); |
1931 | return; | |
1932 | } else if (i == m->nr) { | |
61d2ef2c AK |
1933 | ++m->nr; |
1934 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
1935 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
1936 | } | |
1937 | ||
1938 | m->guest[i].index = msr; | |
1939 | m->guest[i].value = guest_val; | |
1940 | m->host[i].index = msr; | |
1941 | m->host[i].value = host_val; | |
1942 | } | |
1943 | ||
33ed6329 AK |
1944 | static void reload_tss(void) |
1945 | { | |
33ed6329 AK |
1946 | /* |
1947 | * VT restores TR but not its size. Useless. | |
1948 | */ | |
89cbc767 | 1949 | struct desc_ptr *gdt = this_cpu_ptr(&host_gdt); |
a5f61300 | 1950 | struct desc_struct *descs; |
33ed6329 | 1951 | |
d359192f | 1952 | descs = (void *)gdt->address; |
33ed6329 AK |
1953 | descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ |
1954 | load_TR_desc(); | |
33ed6329 AK |
1955 | } |
1956 | ||
92c0d900 | 1957 | static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) |
2cc51560 | 1958 | { |
844a5fe2 PB |
1959 | u64 guest_efer = vmx->vcpu.arch.efer; |
1960 | u64 ignore_bits = 0; | |
1961 | ||
1962 | if (!enable_ept) { | |
1963 | /* | |
1964 | * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing | |
1965 | * host CPUID is more efficient than testing guest CPUID | |
1966 | * or CR4. Host SMEP is anyway a requirement for guest SMEP. | |
1967 | */ | |
1968 | if (boot_cpu_has(X86_FEATURE_SMEP)) | |
1969 | guest_efer |= EFER_NX; | |
1970 | else if (!(guest_efer & EFER_NX)) | |
1971 | ignore_bits |= EFER_NX; | |
1972 | } | |
3a34a881 | 1973 | |
51c6cf66 | 1974 | /* |
844a5fe2 | 1975 | * LMA and LME handled by hardware; SCE meaningless outside long mode. |
51c6cf66 | 1976 | */ |
844a5fe2 | 1977 | ignore_bits |= EFER_SCE; |
51c6cf66 AK |
1978 | #ifdef CONFIG_X86_64 |
1979 | ignore_bits |= EFER_LMA | EFER_LME; | |
1980 | /* SCE is meaningful only in long mode on Intel */ | |
1981 | if (guest_efer & EFER_LMA) | |
1982 | ignore_bits &= ~(u64)EFER_SCE; | |
1983 | #endif | |
84ad33ef AK |
1984 | |
1985 | clear_atomic_switch_msr(vmx, MSR_EFER); | |
f6577a5f AL |
1986 | |
1987 | /* | |
1988 | * On EPT, we can't emulate NX, so we must switch EFER atomically. | |
1989 | * On CPUs that support "load IA32_EFER", always switch EFER | |
1990 | * atomically, since it's faster than switching it manually. | |
1991 | */ | |
1992 | if (cpu_has_load_ia32_efer || | |
1993 | (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { | |
84ad33ef AK |
1994 | if (!(guest_efer & EFER_LMA)) |
1995 | guest_efer &= ~EFER_LME; | |
54b98bff AL |
1996 | if (guest_efer != host_efer) |
1997 | add_atomic_switch_msr(vmx, MSR_EFER, | |
1998 | guest_efer, host_efer); | |
84ad33ef | 1999 | return false; |
844a5fe2 PB |
2000 | } else { |
2001 | guest_efer &= ~ignore_bits; | |
2002 | guest_efer |= host_efer & ignore_bits; | |
2003 | ||
2004 | vmx->guest_msrs[efer_offset].data = guest_efer; | |
2005 | vmx->guest_msrs[efer_offset].mask = ~ignore_bits; | |
84ad33ef | 2006 | |
844a5fe2 PB |
2007 | return true; |
2008 | } | |
51c6cf66 AK |
2009 | } |
2010 | ||
2d49ec72 GN |
2011 | static unsigned long segment_base(u16 selector) |
2012 | { | |
89cbc767 | 2013 | struct desc_ptr *gdt = this_cpu_ptr(&host_gdt); |
2d49ec72 GN |
2014 | struct desc_struct *d; |
2015 | unsigned long table_base; | |
2016 | unsigned long v; | |
2017 | ||
2018 | if (!(selector & ~3)) | |
2019 | return 0; | |
2020 | ||
d359192f | 2021 | table_base = gdt->address; |
2d49ec72 GN |
2022 | |
2023 | if (selector & 4) { /* from ldt */ | |
2024 | u16 ldt_selector = kvm_read_ldt(); | |
2025 | ||
2026 | if (!(ldt_selector & ~3)) | |
2027 | return 0; | |
2028 | ||
2029 | table_base = segment_base(ldt_selector); | |
2030 | } | |
2031 | d = (struct desc_struct *)(table_base + (selector & ~7)); | |
2032 | v = get_desc_base(d); | |
2033 | #ifdef CONFIG_X86_64 | |
2034 | if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11)) | |
2035 | v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32; | |
2036 | #endif | |
2037 | return v; | |
2038 | } | |
2039 | ||
2040 | static inline unsigned long kvm_read_tr_base(void) | |
2041 | { | |
2042 | u16 tr; | |
2043 | asm("str %0" : "=g"(tr)); | |
2044 | return segment_base(tr); | |
2045 | } | |
2046 | ||
04d2cc77 | 2047 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 2048 | { |
04d2cc77 | 2049 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 2050 | int i; |
04d2cc77 | 2051 | |
a2fa3e9f | 2052 | if (vmx->host_state.loaded) |
33ed6329 AK |
2053 | return; |
2054 | ||
a2fa3e9f | 2055 | vmx->host_state.loaded = 1; |
33ed6329 AK |
2056 | /* |
2057 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
2058 | * allow segment selectors with cpl > 0 or ti == 1. | |
2059 | */ | |
d6e88aec | 2060 | vmx->host_state.ldt_sel = kvm_read_ldt(); |
152d3f2f | 2061 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
9581d442 | 2062 | savesegment(fs, vmx->host_state.fs_sel); |
152d3f2f | 2063 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 2064 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
2065 | vmx->host_state.fs_reload_needed = 0; |
2066 | } else { | |
33ed6329 | 2067 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 2068 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 2069 | } |
9581d442 | 2070 | savesegment(gs, vmx->host_state.gs_sel); |
a2fa3e9f GH |
2071 | if (!(vmx->host_state.gs_sel & 7)) |
2072 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
2073 | else { |
2074 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 2075 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
2076 | } |
2077 | ||
b2da15ac AK |
2078 | #ifdef CONFIG_X86_64 |
2079 | savesegment(ds, vmx->host_state.ds_sel); | |
2080 | savesegment(es, vmx->host_state.es_sel); | |
2081 | #endif | |
2082 | ||
33ed6329 AK |
2083 | #ifdef CONFIG_X86_64 |
2084 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
2085 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
2086 | #else | |
a2fa3e9f GH |
2087 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
2088 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 2089 | #endif |
707c0874 AK |
2090 | |
2091 | #ifdef CONFIG_X86_64 | |
c8770e7b AK |
2092 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
2093 | if (is_long_mode(&vmx->vcpu)) | |
44ea2b17 | 2094 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); |
707c0874 | 2095 | #endif |
da8999d3 LJ |
2096 | if (boot_cpu_has(X86_FEATURE_MPX)) |
2097 | rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
26bb0981 AK |
2098 | for (i = 0; i < vmx->save_nmsrs; ++i) |
2099 | kvm_set_shared_msr(vmx->guest_msrs[i].index, | |
d5696725 AK |
2100 | vmx->guest_msrs[i].data, |
2101 | vmx->guest_msrs[i].mask); | |
33ed6329 AK |
2102 | } |
2103 | ||
a9b21b62 | 2104 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 2105 | { |
a2fa3e9f | 2106 | if (!vmx->host_state.loaded) |
33ed6329 AK |
2107 | return; |
2108 | ||
e1beb1d3 | 2109 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 2110 | vmx->host_state.loaded = 0; |
c8770e7b AK |
2111 | #ifdef CONFIG_X86_64 |
2112 | if (is_long_mode(&vmx->vcpu)) | |
2113 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); | |
2114 | #endif | |
152d3f2f | 2115 | if (vmx->host_state.gs_ldt_reload_needed) { |
d6e88aec | 2116 | kvm_load_ldt(vmx->host_state.ldt_sel); |
33ed6329 | 2117 | #ifdef CONFIG_X86_64 |
9581d442 | 2118 | load_gs_index(vmx->host_state.gs_sel); |
9581d442 AK |
2119 | #else |
2120 | loadsegment(gs, vmx->host_state.gs_sel); | |
33ed6329 | 2121 | #endif |
33ed6329 | 2122 | } |
0a77fe4c AK |
2123 | if (vmx->host_state.fs_reload_needed) |
2124 | loadsegment(fs, vmx->host_state.fs_sel); | |
b2da15ac AK |
2125 | #ifdef CONFIG_X86_64 |
2126 | if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) { | |
2127 | loadsegment(ds, vmx->host_state.ds_sel); | |
2128 | loadsegment(es, vmx->host_state.es_sel); | |
2129 | } | |
b2da15ac | 2130 | #endif |
152d3f2f | 2131 | reload_tss(); |
44ea2b17 | 2132 | #ifdef CONFIG_X86_64 |
c8770e7b | 2133 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
44ea2b17 | 2134 | #endif |
da8999d3 LJ |
2135 | if (vmx->host_state.msr_host_bndcfgs) |
2136 | wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
b1a74bf8 SS |
2137 | /* |
2138 | * If the FPU is not active (through the host task or | |
2139 | * the guest vcpu), then restore the cr0.TS bit. | |
2140 | */ | |
3c6dffa9 | 2141 | if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded) |
b1a74bf8 | 2142 | stts(); |
89cbc767 | 2143 | load_gdt(this_cpu_ptr(&host_gdt)); |
33ed6329 AK |
2144 | } |
2145 | ||
a9b21b62 AK |
2146 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
2147 | { | |
2148 | preempt_disable(); | |
2149 | __vmx_load_host_state(vmx); | |
2150 | preempt_enable(); | |
2151 | } | |
2152 | ||
28b835d6 FW |
2153 | static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) |
2154 | { | |
2155 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
2156 | struct pi_desc old, new; | |
2157 | unsigned int dest; | |
2158 | ||
2159 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
2160 | !irq_remapping_cap(IRQ_POSTING_CAP)) | |
2161 | return; | |
2162 | ||
2163 | do { | |
2164 | old.control = new.control = pi_desc->control; | |
2165 | ||
2166 | /* | |
2167 | * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there | |
2168 | * are two possible cases: | |
2169 | * 1. After running 'pre_block', context switch | |
2170 | * happened. For this case, 'sn' was set in | |
2171 | * vmx_vcpu_put(), so we need to clear it here. | |
2172 | * 2. After running 'pre_block', we were blocked, | |
2173 | * and woken up by some other guy. For this case, | |
2174 | * we don't need to do anything, 'pi_post_block' | |
2175 | * will do everything for us. However, we cannot | |
2176 | * check whether it is case #1 or case #2 here | |
2177 | * (maybe, not needed), so we also clear sn here, | |
2178 | * I think it is not a big deal. | |
2179 | */ | |
2180 | if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) { | |
2181 | if (vcpu->cpu != cpu) { | |
2182 | dest = cpu_physical_id(cpu); | |
2183 | ||
2184 | if (x2apic_enabled()) | |
2185 | new.ndst = dest; | |
2186 | else | |
2187 | new.ndst = (dest << 8) & 0xFF00; | |
2188 | } | |
2189 | ||
2190 | /* set 'NV' to 'notification vector' */ | |
2191 | new.nv = POSTED_INTR_VECTOR; | |
2192 | } | |
2193 | ||
2194 | /* Allow posting non-urgent interrupts */ | |
2195 | new.sn = 0; | |
2196 | } while (cmpxchg(&pi_desc->control, old.control, | |
2197 | new.control) != old.control); | |
2198 | } | |
1be0e61c | 2199 | |
6aa8b732 AK |
2200 | /* |
2201 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
2202 | * vcpu mutex is already taken. | |
2203 | */ | |
15ad7146 | 2204 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 2205 | { |
a2fa3e9f | 2206 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4610c9cc | 2207 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); |
6aa8b732 | 2208 | |
4610c9cc DX |
2209 | if (!vmm_exclusive) |
2210 | kvm_cpu_vmxon(phys_addr); | |
d462b819 NHE |
2211 | else if (vmx->loaded_vmcs->cpu != cpu) |
2212 | loaded_vmcs_clear(vmx->loaded_vmcs); | |
6aa8b732 | 2213 | |
d462b819 NHE |
2214 | if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { |
2215 | per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; | |
2216 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
6aa8b732 AK |
2217 | } |
2218 | ||
d462b819 | 2219 | if (vmx->loaded_vmcs->cpu != cpu) { |
89cbc767 | 2220 | struct desc_ptr *gdt = this_cpu_ptr(&host_gdt); |
6aa8b732 AK |
2221 | unsigned long sysenter_esp; |
2222 | ||
a8eeb04a | 2223 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
92fe13be | 2224 | local_irq_disable(); |
8f536b76 | 2225 | crash_disable_local_vmclear(cpu); |
5a560f8b XG |
2226 | |
2227 | /* | |
2228 | * Read loaded_vmcs->cpu should be before fetching | |
2229 | * loaded_vmcs->loaded_vmcss_on_cpu_link. | |
2230 | * See the comments in __loaded_vmcs_clear(). | |
2231 | */ | |
2232 | smp_rmb(); | |
2233 | ||
d462b819 NHE |
2234 | list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, |
2235 | &per_cpu(loaded_vmcss_on_cpu, cpu)); | |
8f536b76 | 2236 | crash_enable_local_vmclear(cpu); |
92fe13be DX |
2237 | local_irq_enable(); |
2238 | ||
6aa8b732 AK |
2239 | /* |
2240 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
2241 | * processors. | |
2242 | */ | |
d6e88aec | 2243 | vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */ |
d359192f | 2244 | vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */ |
6aa8b732 AK |
2245 | |
2246 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
2247 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
ff2c3a18 | 2248 | |
d462b819 | 2249 | vmx->loaded_vmcs->cpu = cpu; |
6aa8b732 | 2250 | } |
28b835d6 | 2251 | |
2680d6da OH |
2252 | /* Setup TSC multiplier */ |
2253 | if (kvm_has_tsc_control && | |
2254 | vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) { | |
2255 | vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio; | |
2256 | vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio); | |
2257 | } | |
2258 | ||
28b835d6 | 2259 | vmx_vcpu_pi_load(vcpu, cpu); |
1be0e61c | 2260 | vmx->host_pkru = read_pkru(); |
28b835d6 FW |
2261 | } |
2262 | ||
2263 | static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) | |
2264 | { | |
2265 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
2266 | ||
2267 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
2268 | !irq_remapping_cap(IRQ_POSTING_CAP)) | |
2269 | return; | |
2270 | ||
2271 | /* Set SN when the vCPU is preempted */ | |
2272 | if (vcpu->preempted) | |
2273 | pi_set_sn(pi_desc); | |
6aa8b732 AK |
2274 | } |
2275 | ||
2276 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
2277 | { | |
28b835d6 FW |
2278 | vmx_vcpu_pi_put(vcpu); |
2279 | ||
a9b21b62 | 2280 | __vmx_load_host_state(to_vmx(vcpu)); |
4610c9cc | 2281 | if (!vmm_exclusive) { |
d462b819 NHE |
2282 | __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs); |
2283 | vcpu->cpu = -1; | |
4610c9cc DX |
2284 | kvm_cpu_vmxoff(); |
2285 | } | |
6aa8b732 AK |
2286 | } |
2287 | ||
5fd86fcf AK |
2288 | static void vmx_fpu_activate(struct kvm_vcpu *vcpu) |
2289 | { | |
81231c69 AK |
2290 | ulong cr0; |
2291 | ||
5fd86fcf AK |
2292 | if (vcpu->fpu_active) |
2293 | return; | |
2294 | vcpu->fpu_active = 1; | |
81231c69 AK |
2295 | cr0 = vmcs_readl(GUEST_CR0); |
2296 | cr0 &= ~(X86_CR0_TS | X86_CR0_MP); | |
2297 | cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP); | |
2298 | vmcs_writel(GUEST_CR0, cr0); | |
5fd86fcf | 2299 | update_exception_bitmap(vcpu); |
edcafe3c | 2300 | vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS; |
36cf24e0 NHE |
2301 | if (is_guest_mode(vcpu)) |
2302 | vcpu->arch.cr0_guest_owned_bits &= | |
2303 | ~get_vmcs12(vcpu)->cr0_guest_host_mask; | |
edcafe3c | 2304 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); |
5fd86fcf AK |
2305 | } |
2306 | ||
edcafe3c AK |
2307 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); |
2308 | ||
fe3ef05c NHE |
2309 | /* |
2310 | * Return the cr0 value that a nested guest would read. This is a combination | |
2311 | * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by | |
2312 | * its hypervisor (cr0_read_shadow). | |
2313 | */ | |
2314 | static inline unsigned long nested_read_cr0(struct vmcs12 *fields) | |
2315 | { | |
2316 | return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) | | |
2317 | (fields->cr0_read_shadow & fields->cr0_guest_host_mask); | |
2318 | } | |
2319 | static inline unsigned long nested_read_cr4(struct vmcs12 *fields) | |
2320 | { | |
2321 | return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) | | |
2322 | (fields->cr4_read_shadow & fields->cr4_guest_host_mask); | |
2323 | } | |
2324 | ||
5fd86fcf AK |
2325 | static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu) |
2326 | { | |
36cf24e0 NHE |
2327 | /* Note that there is no vcpu->fpu_active = 0 here. The caller must |
2328 | * set this *before* calling this function. | |
2329 | */ | |
edcafe3c | 2330 | vmx_decache_cr0_guest_bits(vcpu); |
81231c69 | 2331 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP); |
5fd86fcf | 2332 | update_exception_bitmap(vcpu); |
edcafe3c AK |
2333 | vcpu->arch.cr0_guest_owned_bits = 0; |
2334 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
36cf24e0 NHE |
2335 | if (is_guest_mode(vcpu)) { |
2336 | /* | |
2337 | * L1's specified read shadow might not contain the TS bit, | |
2338 | * so now that we turned on shadowing of this bit, we need to | |
2339 | * set this bit of the shadow. Like in nested_vmx_run we need | |
2340 | * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet | |
2341 | * up-to-date here because we just decached cr0.TS (and we'll | |
2342 | * only update vmcs12->guest_cr0 on nested exit). | |
2343 | */ | |
2344 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
2345 | vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) | | |
2346 | (vcpu->arch.cr0 & X86_CR0_TS); | |
2347 | vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); | |
2348 | } else | |
2349 | vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0); | |
5fd86fcf AK |
2350 | } |
2351 | ||
6aa8b732 AK |
2352 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
2353 | { | |
78ac8b47 | 2354 | unsigned long rflags, save_rflags; |
345dcaa8 | 2355 | |
6de12732 AK |
2356 | if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) { |
2357 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); | |
2358 | rflags = vmcs_readl(GUEST_RFLAGS); | |
2359 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
2360 | rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; | |
2361 | save_rflags = to_vmx(vcpu)->rmode.save_rflags; | |
2362 | rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
2363 | } | |
2364 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 | 2365 | } |
6de12732 | 2366 | return to_vmx(vcpu)->rflags; |
6aa8b732 AK |
2367 | } |
2368 | ||
2369 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
2370 | { | |
6de12732 AK |
2371 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); |
2372 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 AK |
2373 | if (to_vmx(vcpu)->rmode.vm86_active) { |
2374 | to_vmx(vcpu)->rmode.save_rflags = rflags; | |
053de044 | 2375 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
78ac8b47 | 2376 | } |
6aa8b732 AK |
2377 | vmcs_writel(GUEST_RFLAGS, rflags); |
2378 | } | |
2379 | ||
be94f6b7 HH |
2380 | static u32 vmx_get_pkru(struct kvm_vcpu *vcpu) |
2381 | { | |
2382 | return to_vmx(vcpu)->guest_pkru; | |
2383 | } | |
2384 | ||
37ccdcbe | 2385 | static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
2386 | { |
2387 | u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2388 | int ret = 0; | |
2389 | ||
2390 | if (interruptibility & GUEST_INTR_STATE_STI) | |
48005f64 | 2391 | ret |= KVM_X86_SHADOW_INT_STI; |
2809f5d2 | 2392 | if (interruptibility & GUEST_INTR_STATE_MOV_SS) |
48005f64 | 2393 | ret |= KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 | 2394 | |
37ccdcbe | 2395 | return ret; |
2809f5d2 GC |
2396 | } |
2397 | ||
2398 | static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
2399 | { | |
2400 | u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2401 | u32 interruptibility = interruptibility_old; | |
2402 | ||
2403 | interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); | |
2404 | ||
48005f64 | 2405 | if (mask & KVM_X86_SHADOW_INT_MOV_SS) |
2809f5d2 | 2406 | interruptibility |= GUEST_INTR_STATE_MOV_SS; |
48005f64 | 2407 | else if (mask & KVM_X86_SHADOW_INT_STI) |
2809f5d2 GC |
2408 | interruptibility |= GUEST_INTR_STATE_STI; |
2409 | ||
2410 | if ((interruptibility != interruptibility_old)) | |
2411 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); | |
2412 | } | |
2413 | ||
6aa8b732 AK |
2414 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
2415 | { | |
2416 | unsigned long rip; | |
6aa8b732 | 2417 | |
5fdbf976 | 2418 | rip = kvm_rip_read(vcpu); |
6aa8b732 | 2419 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
5fdbf976 | 2420 | kvm_rip_write(vcpu, rip); |
6aa8b732 | 2421 | |
2809f5d2 GC |
2422 | /* skipping an emulated instruction also counts */ |
2423 | vmx_set_interrupt_shadow(vcpu, 0); | |
6aa8b732 AK |
2424 | } |
2425 | ||
0b6ac343 NHE |
2426 | /* |
2427 | * KVM wants to inject page-faults which it got to the guest. This function | |
2428 | * checks whether in a nested guest, we need to inject them to L1 or L2. | |
0b6ac343 | 2429 | */ |
e011c663 | 2430 | static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr) |
0b6ac343 NHE |
2431 | { |
2432 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
2433 | ||
e011c663 | 2434 | if (!(vmcs12->exception_bitmap & (1u << nr))) |
0b6ac343 NHE |
2435 | return 0; |
2436 | ||
533558bc JK |
2437 | nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason, |
2438 | vmcs_read32(VM_EXIT_INTR_INFO), | |
2439 | vmcs_readl(EXIT_QUALIFICATION)); | |
0b6ac343 NHE |
2440 | return 1; |
2441 | } | |
2442 | ||
298101da | 2443 | static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
2444 | bool has_error_code, u32 error_code, |
2445 | bool reinject) | |
298101da | 2446 | { |
77ab6db0 | 2447 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8ab2d2e2 | 2448 | u32 intr_info = nr | INTR_INFO_VALID_MASK; |
77ab6db0 | 2449 | |
e011c663 GN |
2450 | if (!reinject && is_guest_mode(vcpu) && |
2451 | nested_vmx_check_exception(vcpu, nr)) | |
0b6ac343 NHE |
2452 | return; |
2453 | ||
8ab2d2e2 | 2454 | if (has_error_code) { |
77ab6db0 | 2455 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); |
8ab2d2e2 JK |
2456 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; |
2457 | } | |
77ab6db0 | 2458 | |
7ffd92c5 | 2459 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
2460 | int inc_eip = 0; |
2461 | if (kvm_exception_is_soft(nr)) | |
2462 | inc_eip = vcpu->arch.event_exit_inst_len; | |
2463 | if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE) | |
a92601bb | 2464 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
77ab6db0 JK |
2465 | return; |
2466 | } | |
2467 | ||
66fd3f7f GN |
2468 | if (kvm_exception_is_soft(nr)) { |
2469 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
2470 | vmx->vcpu.arch.event_exit_inst_len); | |
8ab2d2e2 JK |
2471 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; |
2472 | } else | |
2473 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
2474 | ||
2475 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | |
298101da AK |
2476 | } |
2477 | ||
4e47c7a6 SY |
2478 | static bool vmx_rdtscp_supported(void) |
2479 | { | |
2480 | return cpu_has_vmx_rdtscp(); | |
2481 | } | |
2482 | ||
ad756a16 MJ |
2483 | static bool vmx_invpcid_supported(void) |
2484 | { | |
2485 | return cpu_has_vmx_invpcid() && enable_ept; | |
2486 | } | |
2487 | ||
a75beee6 ED |
2488 | /* |
2489 | * Swap MSR entry in host/guest MSR entry array. | |
2490 | */ | |
8b9cf98c | 2491 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 2492 | { |
26bb0981 | 2493 | struct shared_msr_entry tmp; |
a2fa3e9f GH |
2494 | |
2495 | tmp = vmx->guest_msrs[to]; | |
2496 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
2497 | vmx->guest_msrs[from] = tmp; | |
a75beee6 ED |
2498 | } |
2499 | ||
8d14695f YZ |
2500 | static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu) |
2501 | { | |
2502 | unsigned long *msr_bitmap; | |
2503 | ||
670125bd WV |
2504 | if (is_guest_mode(vcpu)) |
2505 | msr_bitmap = vmx_msr_bitmap_nested; | |
3ce424e4 RK |
2506 | else if (cpu_has_secondary_exec_ctrls() && |
2507 | (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) & | |
2508 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { | |
8d14695f YZ |
2509 | if (is_long_mode(vcpu)) |
2510 | msr_bitmap = vmx_msr_bitmap_longmode_x2apic; | |
2511 | else | |
2512 | msr_bitmap = vmx_msr_bitmap_legacy_x2apic; | |
2513 | } else { | |
2514 | if (is_long_mode(vcpu)) | |
2515 | msr_bitmap = vmx_msr_bitmap_longmode; | |
2516 | else | |
2517 | msr_bitmap = vmx_msr_bitmap_legacy; | |
2518 | } | |
2519 | ||
2520 | vmcs_write64(MSR_BITMAP, __pa(msr_bitmap)); | |
2521 | } | |
2522 | ||
e38aea3e AK |
2523 | /* |
2524 | * Set up the vmcs to automatically save and restore system | |
2525 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
2526 | * mode, as fiddling with msrs is very expensive. | |
2527 | */ | |
8b9cf98c | 2528 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 2529 | { |
26bb0981 | 2530 | int save_nmsrs, index; |
e38aea3e | 2531 | |
a75beee6 ED |
2532 | save_nmsrs = 0; |
2533 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 2534 | if (is_long_mode(&vmx->vcpu)) { |
8b9cf98c | 2535 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 2536 | if (index >= 0) |
8b9cf98c RR |
2537 | move_msr_up(vmx, index, save_nmsrs++); |
2538 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 2539 | if (index >= 0) |
8b9cf98c RR |
2540 | move_msr_up(vmx, index, save_nmsrs++); |
2541 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 2542 | if (index >= 0) |
8b9cf98c | 2543 | move_msr_up(vmx, index, save_nmsrs++); |
4e47c7a6 | 2544 | index = __find_msr_index(vmx, MSR_TSC_AUX); |
1cea0ce6 | 2545 | if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu)) |
4e47c7a6 | 2546 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 | 2547 | /* |
8c06585d | 2548 | * MSR_STAR is only needed on long mode guests, and only |
a75beee6 ED |
2549 | * if efer.sce is enabled. |
2550 | */ | |
8c06585d | 2551 | index = __find_msr_index(vmx, MSR_STAR); |
f6801dff | 2552 | if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE)) |
8b9cf98c | 2553 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
2554 | } |
2555 | #endif | |
92c0d900 AK |
2556 | index = __find_msr_index(vmx, MSR_EFER); |
2557 | if (index >= 0 && update_transition_efer(vmx, index)) | |
26bb0981 | 2558 | move_msr_up(vmx, index, save_nmsrs++); |
e38aea3e | 2559 | |
26bb0981 | 2560 | vmx->save_nmsrs = save_nmsrs; |
5897297b | 2561 | |
8d14695f YZ |
2562 | if (cpu_has_vmx_msr_bitmap()) |
2563 | vmx_set_msr_bitmap(&vmx->vcpu); | |
e38aea3e AK |
2564 | } |
2565 | ||
6aa8b732 AK |
2566 | /* |
2567 | * reads and returns guest's timestamp counter "register" | |
be7b263e HZ |
2568 | * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset |
2569 | * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3 | |
6aa8b732 | 2570 | */ |
be7b263e | 2571 | static u64 guest_read_tsc(struct kvm_vcpu *vcpu) |
6aa8b732 AK |
2572 | { |
2573 | u64 host_tsc, tsc_offset; | |
2574 | ||
4ea1636b | 2575 | host_tsc = rdtsc(); |
6aa8b732 | 2576 | tsc_offset = vmcs_read64(TSC_OFFSET); |
be7b263e | 2577 | return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset; |
6aa8b732 AK |
2578 | } |
2579 | ||
d5c1785d NHE |
2580 | /* |
2581 | * Like guest_read_tsc, but always returns L1's notion of the timestamp | |
2582 | * counter, even if a nested guest (L2) is currently running. | |
2583 | */ | |
48d89b92 | 2584 | static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
d5c1785d | 2585 | { |
886b470c | 2586 | u64 tsc_offset; |
d5c1785d | 2587 | |
d5c1785d NHE |
2588 | tsc_offset = is_guest_mode(vcpu) ? |
2589 | to_vmx(vcpu)->nested.vmcs01_tsc_offset : | |
2590 | vmcs_read64(TSC_OFFSET); | |
2591 | return host_tsc + tsc_offset; | |
2592 | } | |
2593 | ||
ba904635 WA |
2594 | static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu) |
2595 | { | |
2596 | return vmcs_read64(TSC_OFFSET); | |
2597 | } | |
2598 | ||
6aa8b732 | 2599 | /* |
99e3e30a | 2600 | * writes 'offset' into guest's timestamp counter offset register |
6aa8b732 | 2601 | */ |
99e3e30a | 2602 | static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
6aa8b732 | 2603 | { |
27fc51b2 | 2604 | if (is_guest_mode(vcpu)) { |
7991825b | 2605 | /* |
27fc51b2 NHE |
2606 | * We're here if L1 chose not to trap WRMSR to TSC. According |
2607 | * to the spec, this should set L1's TSC; The offset that L1 | |
2608 | * set for L2 remains unchanged, and still needs to be added | |
2609 | * to the newly set TSC to get L2's TSC. | |
7991825b | 2610 | */ |
27fc51b2 NHE |
2611 | struct vmcs12 *vmcs12; |
2612 | to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset; | |
2613 | /* recalculate vmcs02.TSC_OFFSET: */ | |
2614 | vmcs12 = get_vmcs12(vcpu); | |
2615 | vmcs_write64(TSC_OFFSET, offset + | |
2616 | (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ? | |
2617 | vmcs12->tsc_offset : 0)); | |
2618 | } else { | |
489223ed YY |
2619 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, |
2620 | vmcs_read64(TSC_OFFSET), offset); | |
27fc51b2 NHE |
2621 | vmcs_write64(TSC_OFFSET, offset); |
2622 | } | |
6aa8b732 AK |
2623 | } |
2624 | ||
58ea6767 | 2625 | static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment) |
e48672fa ZA |
2626 | { |
2627 | u64 offset = vmcs_read64(TSC_OFFSET); | |
489223ed | 2628 | |
e48672fa | 2629 | vmcs_write64(TSC_OFFSET, offset + adjustment); |
7991825b NHE |
2630 | if (is_guest_mode(vcpu)) { |
2631 | /* Even when running L2, the adjustment needs to apply to L1 */ | |
2632 | to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment; | |
489223ed YY |
2633 | } else |
2634 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset, | |
2635 | offset + adjustment); | |
e48672fa ZA |
2636 | } |
2637 | ||
801d3424 NHE |
2638 | static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu) |
2639 | { | |
2640 | struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0); | |
2641 | return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31))); | |
2642 | } | |
2643 | ||
2644 | /* | |
2645 | * nested_vmx_allowed() checks whether a guest should be allowed to use VMX | |
2646 | * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for | |
2647 | * all guests if the "nested" module option is off, and can also be disabled | |
2648 | * for a single guest by disabling its VMX cpuid bit. | |
2649 | */ | |
2650 | static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu) | |
2651 | { | |
2652 | return nested && guest_cpuid_has_vmx(vcpu); | |
2653 | } | |
2654 | ||
b87a51ae NHE |
2655 | /* |
2656 | * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be | |
2657 | * returned for the various VMX controls MSRs when nested VMX is enabled. | |
2658 | * The same values should also be used to verify that vmcs12 control fields are | |
2659 | * valid during nested entry from L1 to L2. | |
2660 | * Each of these control msrs has a low and high 32-bit half: A low bit is on | |
2661 | * if the corresponding bit in the (32-bit) control field *must* be on, and a | |
2662 | * bit in the high half is on if the corresponding bit in the control field | |
2663 | * may be on. See also vmx_control_verify(). | |
b87a51ae | 2664 | */ |
b9c237bb | 2665 | static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx) |
b87a51ae NHE |
2666 | { |
2667 | /* | |
2668 | * Note that as a general rule, the high half of the MSRs (bits in | |
2669 | * the control fields which may be 1) should be initialized by the | |
2670 | * intersection of the underlying hardware's MSR (i.e., features which | |
2671 | * can be supported) and the list of features we want to expose - | |
2672 | * because they are known to be properly supported in our code. | |
2673 | * Also, usually, the low half of the MSRs (bits which must be 1) can | |
2674 | * be set to 0, meaning that L1 may turn off any of these bits. The | |
2675 | * reason is that if one of these bits is necessary, it will appear | |
2676 | * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control | |
2677 | * fields of vmcs01 and vmcs02, will turn these bits off - and | |
2678 | * nested_vmx_exit_handled() will not pass related exits to L1. | |
2679 | * These rules have exceptions below. | |
2680 | */ | |
2681 | ||
2682 | /* pin-based controls */ | |
eabeaacc | 2683 | rdmsr(MSR_IA32_VMX_PINBASED_CTLS, |
b9c237bb WV |
2684 | vmx->nested.nested_vmx_pinbased_ctls_low, |
2685 | vmx->nested.nested_vmx_pinbased_ctls_high); | |
2686 | vmx->nested.nested_vmx_pinbased_ctls_low |= | |
2687 | PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
2688 | vmx->nested.nested_vmx_pinbased_ctls_high &= | |
2689 | PIN_BASED_EXT_INTR_MASK | | |
2690 | PIN_BASED_NMI_EXITING | | |
2691 | PIN_BASED_VIRTUAL_NMIS; | |
2692 | vmx->nested.nested_vmx_pinbased_ctls_high |= | |
2693 | PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR | | |
0238ea91 | 2694 | PIN_BASED_VMX_PREEMPTION_TIMER; |
d62caabb | 2695 | if (kvm_vcpu_apicv_active(&vmx->vcpu)) |
705699a1 WV |
2696 | vmx->nested.nested_vmx_pinbased_ctls_high |= |
2697 | PIN_BASED_POSTED_INTR; | |
b87a51ae | 2698 | |
3dbcd8da | 2699 | /* exit controls */ |
c0dfee58 | 2700 | rdmsr(MSR_IA32_VMX_EXIT_CTLS, |
b9c237bb WV |
2701 | vmx->nested.nested_vmx_exit_ctls_low, |
2702 | vmx->nested.nested_vmx_exit_ctls_high); | |
2703 | vmx->nested.nested_vmx_exit_ctls_low = | |
2704 | VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; | |
e0ba1a6f | 2705 | |
b9c237bb | 2706 | vmx->nested.nested_vmx_exit_ctls_high &= |
b87a51ae | 2707 | #ifdef CONFIG_X86_64 |
c0dfee58 | 2708 | VM_EXIT_HOST_ADDR_SPACE_SIZE | |
b87a51ae | 2709 | #endif |
f4124500 | 2710 | VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT; |
b9c237bb WV |
2711 | vmx->nested.nested_vmx_exit_ctls_high |= |
2712 | VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR | | |
f4124500 | 2713 | VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER | |
e0ba1a6f BD |
2714 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT; |
2715 | ||
a87036ad | 2716 | if (kvm_mpx_supported()) |
b9c237bb | 2717 | vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; |
b87a51ae | 2718 | |
2996fca0 | 2719 | /* We support free control of debug control saving. */ |
b9c237bb WV |
2720 | vmx->nested.nested_vmx_true_exit_ctls_low = |
2721 | vmx->nested.nested_vmx_exit_ctls_low & | |
2996fca0 JK |
2722 | ~VM_EXIT_SAVE_DEBUG_CONTROLS; |
2723 | ||
b87a51ae NHE |
2724 | /* entry controls */ |
2725 | rdmsr(MSR_IA32_VMX_ENTRY_CTLS, | |
b9c237bb WV |
2726 | vmx->nested.nested_vmx_entry_ctls_low, |
2727 | vmx->nested.nested_vmx_entry_ctls_high); | |
2728 | vmx->nested.nested_vmx_entry_ctls_low = | |
2729 | VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; | |
2730 | vmx->nested.nested_vmx_entry_ctls_high &= | |
57435349 JK |
2731 | #ifdef CONFIG_X86_64 |
2732 | VM_ENTRY_IA32E_MODE | | |
2733 | #endif | |
2734 | VM_ENTRY_LOAD_IA32_PAT; | |
b9c237bb WV |
2735 | vmx->nested.nested_vmx_entry_ctls_high |= |
2736 | (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER); | |
a87036ad | 2737 | if (kvm_mpx_supported()) |
b9c237bb | 2738 | vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; |
57435349 | 2739 | |
2996fca0 | 2740 | /* We support free control of debug control loading. */ |
b9c237bb WV |
2741 | vmx->nested.nested_vmx_true_entry_ctls_low = |
2742 | vmx->nested.nested_vmx_entry_ctls_low & | |
2996fca0 JK |
2743 | ~VM_ENTRY_LOAD_DEBUG_CONTROLS; |
2744 | ||
b87a51ae NHE |
2745 | /* cpu-based controls */ |
2746 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, | |
b9c237bb WV |
2747 | vmx->nested.nested_vmx_procbased_ctls_low, |
2748 | vmx->nested.nested_vmx_procbased_ctls_high); | |
2749 | vmx->nested.nested_vmx_procbased_ctls_low = | |
2750 | CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
2751 | vmx->nested.nested_vmx_procbased_ctls_high &= | |
a294c9bb JK |
2752 | CPU_BASED_VIRTUAL_INTR_PENDING | |
2753 | CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING | | |
b87a51ae NHE |
2754 | CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING | |
2755 | CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING | | |
2756 | CPU_BASED_CR3_STORE_EXITING | | |
2757 | #ifdef CONFIG_X86_64 | |
2758 | CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING | | |
2759 | #endif | |
2760 | CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING | | |
5f3d45e7 MD |
2761 | CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG | |
2762 | CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING | | |
2763 | CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING | | |
2764 | CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
b87a51ae NHE |
2765 | /* |
2766 | * We can allow some features even when not supported by the | |
2767 | * hardware. For example, L1 can specify an MSR bitmap - and we | |
2768 | * can use it to avoid exits to L1 - even when L0 runs L2 | |
2769 | * without MSR bitmaps. | |
2770 | */ | |
b9c237bb WV |
2771 | vmx->nested.nested_vmx_procbased_ctls_high |= |
2772 | CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR | | |
560b7ee1 | 2773 | CPU_BASED_USE_MSR_BITMAPS; |
b87a51ae | 2774 | |
3dcdf3ec | 2775 | /* We support free control of CR3 access interception. */ |
b9c237bb WV |
2776 | vmx->nested.nested_vmx_true_procbased_ctls_low = |
2777 | vmx->nested.nested_vmx_procbased_ctls_low & | |
3dcdf3ec JK |
2778 | ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING); |
2779 | ||
b87a51ae NHE |
2780 | /* secondary cpu-based controls */ |
2781 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, | |
b9c237bb WV |
2782 | vmx->nested.nested_vmx_secondary_ctls_low, |
2783 | vmx->nested.nested_vmx_secondary_ctls_high); | |
2784 | vmx->nested.nested_vmx_secondary_ctls_low = 0; | |
2785 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
d6851fbe | 2786 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
b3a2a907 | 2787 | SECONDARY_EXEC_RDTSCP | |
f2b93280 | 2788 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
5c614b35 | 2789 | SECONDARY_EXEC_ENABLE_VPID | |
82f0dd4b | 2790 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
608406e2 | 2791 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
81dc01f7 | 2792 | SECONDARY_EXEC_WBINVD_EXITING | |
8b3e34e4 XG |
2793 | SECONDARY_EXEC_XSAVES | |
2794 | SECONDARY_EXEC_PCOMMIT; | |
c18911a2 | 2795 | |
afa61f75 NHE |
2796 | if (enable_ept) { |
2797 | /* nested EPT: emulate EPT also to L1 */ | |
b9c237bb | 2798 | vmx->nested.nested_vmx_secondary_ctls_high |= |
0790ec17 | 2799 | SECONDARY_EXEC_ENABLE_EPT; |
b9c237bb | 2800 | vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT | |
d3134dbf JK |
2801 | VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT | |
2802 | VMX_EPT_INVEPT_BIT; | |
02120c45 BD |
2803 | if (cpu_has_vmx_ept_execute_only()) |
2804 | vmx->nested.nested_vmx_ept_caps |= | |
2805 | VMX_EPT_EXECUTE_ONLY_BIT; | |
b9c237bb | 2806 | vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept; |
afa61f75 | 2807 | /* |
4b855078 BD |
2808 | * For nested guests, we don't do anything specific |
2809 | * for single context invalidation. Hence, only advertise | |
2810 | * support for global context invalidation. | |
afa61f75 | 2811 | */ |
b9c237bb | 2812 | vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT; |
afa61f75 | 2813 | } else |
b9c237bb | 2814 | vmx->nested.nested_vmx_ept_caps = 0; |
afa61f75 | 2815 | |
ef697a71 PB |
2816 | /* |
2817 | * Old versions of KVM use the single-context version without | |
2818 | * checking for support, so declare that it is supported even | |
2819 | * though it is treated as global context. The alternative is | |
2820 | * not failing the single-context invvpid, and it is worse. | |
2821 | */ | |
089d7b6e WL |
2822 | if (enable_vpid) |
2823 | vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT | | |
ef697a71 | 2824 | VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | |
089d7b6e WL |
2825 | VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; |
2826 | else | |
2827 | vmx->nested.nested_vmx_vpid_caps = 0; | |
99b83ac8 | 2828 | |
0790ec17 RK |
2829 | if (enable_unrestricted_guest) |
2830 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
2831 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
2832 | ||
c18911a2 | 2833 | /* miscellaneous data */ |
b9c237bb WV |
2834 | rdmsr(MSR_IA32_VMX_MISC, |
2835 | vmx->nested.nested_vmx_misc_low, | |
2836 | vmx->nested.nested_vmx_misc_high); | |
2837 | vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA; | |
2838 | vmx->nested.nested_vmx_misc_low |= | |
2839 | VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE | | |
f4124500 | 2840 | VMX_MISC_ACTIVITY_HLT; |
b9c237bb | 2841 | vmx->nested.nested_vmx_misc_high = 0; |
b87a51ae NHE |
2842 | } |
2843 | ||
2844 | static inline bool vmx_control_verify(u32 control, u32 low, u32 high) | |
2845 | { | |
2846 | /* | |
2847 | * Bits 0 in high must be 0, and bits 1 in low must be 1. | |
2848 | */ | |
2849 | return ((control & high) | low) == control; | |
2850 | } | |
2851 | ||
2852 | static inline u64 vmx_control_msr(u32 low, u32 high) | |
2853 | { | |
2854 | return low | ((u64)high << 32); | |
2855 | } | |
2856 | ||
cae50139 | 2857 | /* Returns 0 on success, non-0 otherwise. */ |
b87a51ae NHE |
2858 | static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) |
2859 | { | |
b9c237bb WV |
2860 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2861 | ||
b87a51ae | 2862 | switch (msr_index) { |
b87a51ae NHE |
2863 | case MSR_IA32_VMX_BASIC: |
2864 | /* | |
2865 | * This MSR reports some information about VMX support. We | |
2866 | * should return information about the VMX we emulate for the | |
2867 | * guest, and the VMCS structure we give it - not about the | |
2868 | * VMX support of the underlying hardware. | |
2869 | */ | |
3dbcd8da | 2870 | *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS | |
b87a51ae NHE |
2871 | ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) | |
2872 | (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT); | |
2873 | break; | |
2874 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
2875 | case MSR_IA32_VMX_PINBASED_CTLS: | |
b9c237bb WV |
2876 | *pdata = vmx_control_msr( |
2877 | vmx->nested.nested_vmx_pinbased_ctls_low, | |
2878 | vmx->nested.nested_vmx_pinbased_ctls_high); | |
b87a51ae NHE |
2879 | break; |
2880 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
b9c237bb WV |
2881 | *pdata = vmx_control_msr( |
2882 | vmx->nested.nested_vmx_true_procbased_ctls_low, | |
2883 | vmx->nested.nested_vmx_procbased_ctls_high); | |
3dcdf3ec | 2884 | break; |
b87a51ae | 2885 | case MSR_IA32_VMX_PROCBASED_CTLS: |
b9c237bb WV |
2886 | *pdata = vmx_control_msr( |
2887 | vmx->nested.nested_vmx_procbased_ctls_low, | |
2888 | vmx->nested.nested_vmx_procbased_ctls_high); | |
b87a51ae NHE |
2889 | break; |
2890 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
b9c237bb WV |
2891 | *pdata = vmx_control_msr( |
2892 | vmx->nested.nested_vmx_true_exit_ctls_low, | |
2893 | vmx->nested.nested_vmx_exit_ctls_high); | |
2996fca0 | 2894 | break; |
b87a51ae | 2895 | case MSR_IA32_VMX_EXIT_CTLS: |
b9c237bb WV |
2896 | *pdata = vmx_control_msr( |
2897 | vmx->nested.nested_vmx_exit_ctls_low, | |
2898 | vmx->nested.nested_vmx_exit_ctls_high); | |
b87a51ae NHE |
2899 | break; |
2900 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
b9c237bb WV |
2901 | *pdata = vmx_control_msr( |
2902 | vmx->nested.nested_vmx_true_entry_ctls_low, | |
2903 | vmx->nested.nested_vmx_entry_ctls_high); | |
2996fca0 | 2904 | break; |
b87a51ae | 2905 | case MSR_IA32_VMX_ENTRY_CTLS: |
b9c237bb WV |
2906 | *pdata = vmx_control_msr( |
2907 | vmx->nested.nested_vmx_entry_ctls_low, | |
2908 | vmx->nested.nested_vmx_entry_ctls_high); | |
b87a51ae NHE |
2909 | break; |
2910 | case MSR_IA32_VMX_MISC: | |
b9c237bb WV |
2911 | *pdata = vmx_control_msr( |
2912 | vmx->nested.nested_vmx_misc_low, | |
2913 | vmx->nested.nested_vmx_misc_high); | |
b87a51ae NHE |
2914 | break; |
2915 | /* | |
2916 | * These MSRs specify bits which the guest must keep fixed (on or off) | |
2917 | * while L1 is in VMXON mode (in L1's root mode, or running an L2). | |
2918 | * We picked the standard core2 setting. | |
2919 | */ | |
2920 | #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE) | |
2921 | #define VMXON_CR4_ALWAYSON X86_CR4_VMXE | |
2922 | case MSR_IA32_VMX_CR0_FIXED0: | |
2923 | *pdata = VMXON_CR0_ALWAYSON; | |
2924 | break; | |
2925 | case MSR_IA32_VMX_CR0_FIXED1: | |
2926 | *pdata = -1ULL; | |
2927 | break; | |
2928 | case MSR_IA32_VMX_CR4_FIXED0: | |
2929 | *pdata = VMXON_CR4_ALWAYSON; | |
2930 | break; | |
2931 | case MSR_IA32_VMX_CR4_FIXED1: | |
2932 | *pdata = -1ULL; | |
2933 | break; | |
2934 | case MSR_IA32_VMX_VMCS_ENUM: | |
5381417f | 2935 | *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */ |
b87a51ae NHE |
2936 | break; |
2937 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
b9c237bb WV |
2938 | *pdata = vmx_control_msr( |
2939 | vmx->nested.nested_vmx_secondary_ctls_low, | |
2940 | vmx->nested.nested_vmx_secondary_ctls_high); | |
b87a51ae NHE |
2941 | break; |
2942 | case MSR_IA32_VMX_EPT_VPID_CAP: | |
afa61f75 | 2943 | /* Currently, no nested vpid support */ |
089d7b6e WL |
2944 | *pdata = vmx->nested.nested_vmx_ept_caps | |
2945 | ((u64)vmx->nested.nested_vmx_vpid_caps << 32); | |
b87a51ae NHE |
2946 | break; |
2947 | default: | |
b87a51ae | 2948 | return 1; |
b3897a49 NHE |
2949 | } |
2950 | ||
b87a51ae NHE |
2951 | return 0; |
2952 | } | |
2953 | ||
37e4c997 HZ |
2954 | static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, |
2955 | uint64_t val) | |
2956 | { | |
2957 | uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; | |
2958 | ||
2959 | return !(val & ~valid_bits); | |
2960 | } | |
2961 | ||
6aa8b732 AK |
2962 | /* |
2963 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
2964 | * Returns 0 on success, non-0 otherwise. | |
2965 | * Assumes vcpu_load() was already called. | |
2966 | */ | |
609e36d3 | 2967 | static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 2968 | { |
26bb0981 | 2969 | struct shared_msr_entry *msr; |
6aa8b732 | 2970 | |
609e36d3 | 2971 | switch (msr_info->index) { |
05b3e0c2 | 2972 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2973 | case MSR_FS_BASE: |
609e36d3 | 2974 | msr_info->data = vmcs_readl(GUEST_FS_BASE); |
6aa8b732 AK |
2975 | break; |
2976 | case MSR_GS_BASE: | |
609e36d3 | 2977 | msr_info->data = vmcs_readl(GUEST_GS_BASE); |
6aa8b732 | 2978 | break; |
44ea2b17 AK |
2979 | case MSR_KERNEL_GS_BASE: |
2980 | vmx_load_host_state(to_vmx(vcpu)); | |
609e36d3 | 2981 | msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base; |
44ea2b17 | 2982 | break; |
26bb0981 | 2983 | #endif |
6aa8b732 | 2984 | case MSR_EFER: |
609e36d3 | 2985 | return kvm_get_msr_common(vcpu, msr_info); |
af24a4e4 | 2986 | case MSR_IA32_TSC: |
be7b263e | 2987 | msr_info->data = guest_read_tsc(vcpu); |
6aa8b732 AK |
2988 | break; |
2989 | case MSR_IA32_SYSENTER_CS: | |
609e36d3 | 2990 | msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); |
6aa8b732 AK |
2991 | break; |
2992 | case MSR_IA32_SYSENTER_EIP: | |
609e36d3 | 2993 | msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
2994 | break; |
2995 | case MSR_IA32_SYSENTER_ESP: | |
609e36d3 | 2996 | msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 2997 | break; |
0dd376e7 | 2998 | case MSR_IA32_BNDCFGS: |
a87036ad | 2999 | if (!kvm_mpx_supported()) |
93c4adc7 | 3000 | return 1; |
609e36d3 | 3001 | msr_info->data = vmcs_read64(GUEST_BNDCFGS); |
0dd376e7 | 3002 | break; |
c45dcc71 AR |
3003 | case MSR_IA32_MCG_EXT_CTL: |
3004 | if (!msr_info->host_initiated && | |
3005 | !(to_vmx(vcpu)->msr_ia32_feature_control & | |
3006 | FEATURE_CONTROL_LMCE)) | |
3007 | return 1; | |
3008 | msr_info->data = vcpu->arch.mcg_ext_ctl; | |
3009 | break; | |
cae50139 | 3010 | case MSR_IA32_FEATURE_CONTROL: |
3b84080b | 3011 | msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control; |
cae50139 JK |
3012 | break; |
3013 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
3014 | if (!nested_vmx_allowed(vcpu)) | |
3015 | return 1; | |
609e36d3 | 3016 | return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data); |
20300099 WL |
3017 | case MSR_IA32_XSS: |
3018 | if (!vmx_xsaves_supported()) | |
3019 | return 1; | |
609e36d3 | 3020 | msr_info->data = vcpu->arch.ia32_xss; |
20300099 | 3021 | break; |
4e47c7a6 | 3022 | case MSR_TSC_AUX: |
81b1b9ca | 3023 | if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated) |
4e47c7a6 SY |
3024 | return 1; |
3025 | /* Otherwise falls through */ | |
6aa8b732 | 3026 | default: |
609e36d3 | 3027 | msr = find_msr_entry(to_vmx(vcpu), msr_info->index); |
3bab1f5d | 3028 | if (msr) { |
609e36d3 | 3029 | msr_info->data = msr->data; |
3bab1f5d | 3030 | break; |
6aa8b732 | 3031 | } |
609e36d3 | 3032 | return kvm_get_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3033 | } |
3034 | ||
6aa8b732 AK |
3035 | return 0; |
3036 | } | |
3037 | ||
cae50139 JK |
3038 | static void vmx_leave_nested(struct kvm_vcpu *vcpu); |
3039 | ||
6aa8b732 AK |
3040 | /* |
3041 | * Writes msr value into into the appropriate "register". | |
3042 | * Returns 0 on success, non-0 otherwise. | |
3043 | * Assumes vcpu_load() was already called. | |
3044 | */ | |
8fe8ab46 | 3045 | static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3046 | { |
a2fa3e9f | 3047 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 3048 | struct shared_msr_entry *msr; |
2cc51560 | 3049 | int ret = 0; |
8fe8ab46 WA |
3050 | u32 msr_index = msr_info->index; |
3051 | u64 data = msr_info->data; | |
2cc51560 | 3052 | |
6aa8b732 | 3053 | switch (msr_index) { |
3bab1f5d | 3054 | case MSR_EFER: |
8fe8ab46 | 3055 | ret = kvm_set_msr_common(vcpu, msr_info); |
2cc51560 | 3056 | break; |
16175a79 | 3057 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3058 | case MSR_FS_BASE: |
2fb92db1 | 3059 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
3060 | vmcs_writel(GUEST_FS_BASE, data); |
3061 | break; | |
3062 | case MSR_GS_BASE: | |
2fb92db1 | 3063 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
3064 | vmcs_writel(GUEST_GS_BASE, data); |
3065 | break; | |
44ea2b17 AK |
3066 | case MSR_KERNEL_GS_BASE: |
3067 | vmx_load_host_state(vmx); | |
3068 | vmx->msr_guest_kernel_gs_base = data; | |
3069 | break; | |
6aa8b732 AK |
3070 | #endif |
3071 | case MSR_IA32_SYSENTER_CS: | |
3072 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
3073 | break; | |
3074 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 3075 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
3076 | break; |
3077 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 3078 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 3079 | break; |
0dd376e7 | 3080 | case MSR_IA32_BNDCFGS: |
a87036ad | 3081 | if (!kvm_mpx_supported()) |
93c4adc7 | 3082 | return 1; |
0dd376e7 LJ |
3083 | vmcs_write64(GUEST_BNDCFGS, data); |
3084 | break; | |
af24a4e4 | 3085 | case MSR_IA32_TSC: |
8fe8ab46 | 3086 | kvm_write_tsc(vcpu, msr_info); |
6aa8b732 | 3087 | break; |
468d472f SY |
3088 | case MSR_IA32_CR_PAT: |
3089 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
4566654b NA |
3090 | if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data)) |
3091 | return 1; | |
468d472f SY |
3092 | vmcs_write64(GUEST_IA32_PAT, data); |
3093 | vcpu->arch.pat = data; | |
3094 | break; | |
3095 | } | |
8fe8ab46 | 3096 | ret = kvm_set_msr_common(vcpu, msr_info); |
4e47c7a6 | 3097 | break; |
ba904635 WA |
3098 | case MSR_IA32_TSC_ADJUST: |
3099 | ret = kvm_set_msr_common(vcpu, msr_info); | |
4e47c7a6 | 3100 | break; |
c45dcc71 AR |
3101 | case MSR_IA32_MCG_EXT_CTL: |
3102 | if ((!msr_info->host_initiated && | |
3103 | !(to_vmx(vcpu)->msr_ia32_feature_control & | |
3104 | FEATURE_CONTROL_LMCE)) || | |
3105 | (data & ~MCG_EXT_CTL_LMCE_EN)) | |
3106 | return 1; | |
3107 | vcpu->arch.mcg_ext_ctl = data; | |
3108 | break; | |
cae50139 | 3109 | case MSR_IA32_FEATURE_CONTROL: |
37e4c997 | 3110 | if (!vmx_feature_control_msr_valid(vcpu, data) || |
3b84080b | 3111 | (to_vmx(vcpu)->msr_ia32_feature_control & |
cae50139 JK |
3112 | FEATURE_CONTROL_LOCKED && !msr_info->host_initiated)) |
3113 | return 1; | |
3b84080b | 3114 | vmx->msr_ia32_feature_control = data; |
cae50139 JK |
3115 | if (msr_info->host_initiated && data == 0) |
3116 | vmx_leave_nested(vcpu); | |
3117 | break; | |
3118 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
3119 | return 1; /* they are read-only */ | |
20300099 WL |
3120 | case MSR_IA32_XSS: |
3121 | if (!vmx_xsaves_supported()) | |
3122 | return 1; | |
3123 | /* | |
3124 | * The only supported bit as of Skylake is bit 8, but | |
3125 | * it is not supported on KVM. | |
3126 | */ | |
3127 | if (data != 0) | |
3128 | return 1; | |
3129 | vcpu->arch.ia32_xss = data; | |
3130 | if (vcpu->arch.ia32_xss != host_xss) | |
3131 | add_atomic_switch_msr(vmx, MSR_IA32_XSS, | |
3132 | vcpu->arch.ia32_xss, host_xss); | |
3133 | else | |
3134 | clear_atomic_switch_msr(vmx, MSR_IA32_XSS); | |
3135 | break; | |
4e47c7a6 | 3136 | case MSR_TSC_AUX: |
81b1b9ca | 3137 | if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated) |
4e47c7a6 SY |
3138 | return 1; |
3139 | /* Check reserved bit, higher 32 bits should be zero */ | |
3140 | if ((data >> 32) != 0) | |
3141 | return 1; | |
3142 | /* Otherwise falls through */ | |
6aa8b732 | 3143 | default: |
8b9cf98c | 3144 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d | 3145 | if (msr) { |
8b3c3104 | 3146 | u64 old_msr_data = msr->data; |
3bab1f5d | 3147 | msr->data = data; |
2225fd56 AK |
3148 | if (msr - vmx->guest_msrs < vmx->save_nmsrs) { |
3149 | preempt_disable(); | |
8b3c3104 AH |
3150 | ret = kvm_set_shared_msr(msr->index, msr->data, |
3151 | msr->mask); | |
2225fd56 | 3152 | preempt_enable(); |
8b3c3104 AH |
3153 | if (ret) |
3154 | msr->data = old_msr_data; | |
2225fd56 | 3155 | } |
3bab1f5d | 3156 | break; |
6aa8b732 | 3157 | } |
8fe8ab46 | 3158 | ret = kvm_set_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3159 | } |
3160 | ||
2cc51560 | 3161 | return ret; |
6aa8b732 AK |
3162 | } |
3163 | ||
5fdbf976 | 3164 | static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
6aa8b732 | 3165 | { |
5fdbf976 MT |
3166 | __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); |
3167 | switch (reg) { | |
3168 | case VCPU_REGS_RSP: | |
3169 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
3170 | break; | |
3171 | case VCPU_REGS_RIP: | |
3172 | vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); | |
3173 | break; | |
6de4f3ad AK |
3174 | case VCPU_EXREG_PDPTR: |
3175 | if (enable_ept) | |
3176 | ept_save_pdptrs(vcpu); | |
3177 | break; | |
5fdbf976 MT |
3178 | default: |
3179 | break; | |
3180 | } | |
6aa8b732 AK |
3181 | } |
3182 | ||
6aa8b732 AK |
3183 | static __init int cpu_has_kvm_support(void) |
3184 | { | |
6210e37b | 3185 | return cpu_has_vmx(); |
6aa8b732 AK |
3186 | } |
3187 | ||
3188 | static __init int vmx_disabled_by_bios(void) | |
3189 | { | |
3190 | u64 msr; | |
3191 | ||
3192 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
cafd6659 | 3193 | if (msr & FEATURE_CONTROL_LOCKED) { |
23f3e991 | 3194 | /* launched w/ TXT and VMX disabled */ |
cafd6659 SW |
3195 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
3196 | && tboot_enabled()) | |
3197 | return 1; | |
23f3e991 | 3198 | /* launched w/o TXT and VMX only enabled w/ TXT */ |
cafd6659 | 3199 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) |
23f3e991 | 3200 | && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
f9335afe SW |
3201 | && !tboot_enabled()) { |
3202 | printk(KERN_WARNING "kvm: disable TXT in the BIOS or " | |
23f3e991 | 3203 | "activate TXT before enabling KVM\n"); |
cafd6659 | 3204 | return 1; |
f9335afe | 3205 | } |
23f3e991 JC |
3206 | /* launched w/o TXT and VMX disabled */ |
3207 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) | |
3208 | && !tboot_enabled()) | |
3209 | return 1; | |
cafd6659 SW |
3210 | } |
3211 | ||
3212 | return 0; | |
6aa8b732 AK |
3213 | } |
3214 | ||
7725b894 DX |
3215 | static void kvm_cpu_vmxon(u64 addr) |
3216 | { | |
1c5ac21a AS |
3217 | intel_pt_handle_vmx(1); |
3218 | ||
7725b894 DX |
3219 | asm volatile (ASM_VMX_VMXON_RAX |
3220 | : : "a"(&addr), "m"(addr) | |
3221 | : "memory", "cc"); | |
3222 | } | |
3223 | ||
13a34e06 | 3224 | static int hardware_enable(void) |
6aa8b732 AK |
3225 | { |
3226 | int cpu = raw_smp_processor_id(); | |
3227 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
cafd6659 | 3228 | u64 old, test_bits; |
6aa8b732 | 3229 | |
1e02ce4c | 3230 | if (cr4_read_shadow() & X86_CR4_VMXE) |
10474ae8 AG |
3231 | return -EBUSY; |
3232 | ||
d462b819 | 3233 | INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); |
bf9f6ac8 FW |
3234 | INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); |
3235 | spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
8f536b76 ZY |
3236 | |
3237 | /* | |
3238 | * Now we can enable the vmclear operation in kdump | |
3239 | * since the loaded_vmcss_on_cpu list on this cpu | |
3240 | * has been initialized. | |
3241 | * | |
3242 | * Though the cpu is not in VMX operation now, there | |
3243 | * is no problem to enable the vmclear operation | |
3244 | * for the loaded_vmcss_on_cpu list is empty! | |
3245 | */ | |
3246 | crash_enable_local_vmclear(cpu); | |
3247 | ||
6aa8b732 | 3248 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
cafd6659 SW |
3249 | |
3250 | test_bits = FEATURE_CONTROL_LOCKED; | |
3251 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
3252 | if (tboot_enabled()) | |
3253 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; | |
3254 | ||
3255 | if ((old & test_bits) != test_bits) { | |
6aa8b732 | 3256 | /* enable and lock */ |
cafd6659 SW |
3257 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); |
3258 | } | |
375074cc | 3259 | cr4_set_bits(X86_CR4_VMXE); |
10474ae8 | 3260 | |
4610c9cc DX |
3261 | if (vmm_exclusive) { |
3262 | kvm_cpu_vmxon(phys_addr); | |
3263 | ept_sync_global(); | |
3264 | } | |
10474ae8 | 3265 | |
89cbc767 | 3266 | native_store_gdt(this_cpu_ptr(&host_gdt)); |
3444d7da | 3267 | |
10474ae8 | 3268 | return 0; |
6aa8b732 AK |
3269 | } |
3270 | ||
d462b819 | 3271 | static void vmclear_local_loaded_vmcss(void) |
543e4243 AK |
3272 | { |
3273 | int cpu = raw_smp_processor_id(); | |
d462b819 | 3274 | struct loaded_vmcs *v, *n; |
543e4243 | 3275 | |
d462b819 NHE |
3276 | list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), |
3277 | loaded_vmcss_on_cpu_link) | |
3278 | __loaded_vmcs_clear(v); | |
543e4243 AK |
3279 | } |
3280 | ||
710ff4a8 EH |
3281 | |
3282 | /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() | |
3283 | * tricks. | |
3284 | */ | |
3285 | static void kvm_cpu_vmxoff(void) | |
6aa8b732 | 3286 | { |
4ecac3fd | 3287 | asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
1c5ac21a AS |
3288 | |
3289 | intel_pt_handle_vmx(0); | |
6aa8b732 AK |
3290 | } |
3291 | ||
13a34e06 | 3292 | static void hardware_disable(void) |
710ff4a8 | 3293 | { |
4610c9cc | 3294 | if (vmm_exclusive) { |
d462b819 | 3295 | vmclear_local_loaded_vmcss(); |
4610c9cc DX |
3296 | kvm_cpu_vmxoff(); |
3297 | } | |
375074cc | 3298 | cr4_clear_bits(X86_CR4_VMXE); |
710ff4a8 EH |
3299 | } |
3300 | ||
1c3d14fe | 3301 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 3302 | u32 msr, u32 *result) |
1c3d14fe YS |
3303 | { |
3304 | u32 vmx_msr_low, vmx_msr_high; | |
3305 | u32 ctl = ctl_min | ctl_opt; | |
3306 | ||
3307 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
3308 | ||
3309 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
3310 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
3311 | ||
3312 | /* Ensure minimum (required) set of control bits are supported. */ | |
3313 | if (ctl_min & ~ctl) | |
002c7f7c | 3314 | return -EIO; |
1c3d14fe YS |
3315 | |
3316 | *result = ctl; | |
3317 | return 0; | |
3318 | } | |
3319 | ||
110312c8 AK |
3320 | static __init bool allow_1_setting(u32 msr, u32 ctl) |
3321 | { | |
3322 | u32 vmx_msr_low, vmx_msr_high; | |
3323 | ||
3324 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
3325 | return vmx_msr_high & ctl; | |
3326 | } | |
3327 | ||
002c7f7c | 3328 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
3329 | { |
3330 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 3331 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
3332 | u32 _pin_based_exec_control = 0; |
3333 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 3334 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
3335 | u32 _vmexit_control = 0; |
3336 | u32 _vmentry_control = 0; | |
3337 | ||
10166744 | 3338 | min = CPU_BASED_HLT_EXITING | |
1c3d14fe YS |
3339 | #ifdef CONFIG_X86_64 |
3340 | CPU_BASED_CR8_LOAD_EXITING | | |
3341 | CPU_BASED_CR8_STORE_EXITING | | |
3342 | #endif | |
d56f546d SY |
3343 | CPU_BASED_CR3_LOAD_EXITING | |
3344 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
3345 | CPU_BASED_USE_IO_BITMAPS | |
3346 | CPU_BASED_MOV_DR_EXITING | | |
a7052897 | 3347 | CPU_BASED_USE_TSC_OFFSETING | |
59708670 SY |
3348 | CPU_BASED_MWAIT_EXITING | |
3349 | CPU_BASED_MONITOR_EXITING | | |
fee84b07 AK |
3350 | CPU_BASED_INVLPG_EXITING | |
3351 | CPU_BASED_RDPMC_EXITING; | |
443381a8 | 3352 | |
f78e0e2e | 3353 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 3354 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 3355 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
3356 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
3357 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 3358 | return -EIO; |
6e5d865c YS |
3359 | #ifdef CONFIG_X86_64 |
3360 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
3361 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
3362 | ~CPU_BASED_CR8_STORE_EXITING; | |
3363 | #endif | |
f78e0e2e | 3364 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
3365 | min2 = 0; |
3366 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
8d14695f | 3367 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
2384d2b3 | 3368 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d | 3369 | SECONDARY_EXEC_ENABLE_VPID | |
3a624e29 | 3370 | SECONDARY_EXEC_ENABLE_EPT | |
4b8d54f9 | 3371 | SECONDARY_EXEC_UNRESTRICTED_GUEST | |
4e47c7a6 | 3372 | SECONDARY_EXEC_PAUSE_LOOP_EXITING | |
ad756a16 | 3373 | SECONDARY_EXEC_RDTSCP | |
83d4c286 | 3374 | SECONDARY_EXEC_ENABLE_INVPCID | |
c7c9c56c | 3375 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
abc4fc58 | 3376 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
20300099 | 3377 | SECONDARY_EXEC_SHADOW_VMCS | |
843e4330 | 3378 | SECONDARY_EXEC_XSAVES | |
8b3e34e4 | 3379 | SECONDARY_EXEC_ENABLE_PML | |
64903d61 HZ |
3380 | SECONDARY_EXEC_PCOMMIT | |
3381 | SECONDARY_EXEC_TSC_SCALING; | |
d56f546d SY |
3382 | if (adjust_vmx_controls(min2, opt2, |
3383 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
3384 | &_cpu_based_2nd_exec_control) < 0) |
3385 | return -EIO; | |
3386 | } | |
3387 | #ifndef CONFIG_X86_64 | |
3388 | if (!(_cpu_based_2nd_exec_control & | |
3389 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
3390 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
3391 | #endif | |
83d4c286 YZ |
3392 | |
3393 | if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
3394 | _cpu_based_2nd_exec_control &= ~( | |
8d14695f | 3395 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
c7c9c56c YZ |
3396 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
3397 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
83d4c286 | 3398 | |
d56f546d | 3399 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
a7052897 MT |
3400 | /* CR3 accesses and invlpg don't need to cause VM Exits when EPT |
3401 | enabled */ | |
5fff7d27 GN |
3402 | _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | |
3403 | CPU_BASED_CR3_STORE_EXITING | | |
3404 | CPU_BASED_INVLPG_EXITING); | |
d56f546d SY |
3405 | rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, |
3406 | vmx_capability.ept, vmx_capability.vpid); | |
3407 | } | |
1c3d14fe | 3408 | |
91fa0f8e | 3409 | min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; |
1c3d14fe YS |
3410 | #ifdef CONFIG_X86_64 |
3411 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
3412 | #endif | |
a547c6db | 3413 | opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT | |
91fa0f8e | 3414 | VM_EXIT_CLEAR_BNDCFGS; |
1c3d14fe YS |
3415 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, |
3416 | &_vmexit_control) < 0) | |
002c7f7c | 3417 | return -EIO; |
1c3d14fe | 3418 | |
01e439be | 3419 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; |
64672c95 YJ |
3420 | opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | |
3421 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
3422 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
3423 | &_pin_based_exec_control) < 0) | |
3424 | return -EIO; | |
3425 | ||
1c17c3e6 PB |
3426 | if (cpu_has_broken_vmx_preemption_timer()) |
3427 | _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be | 3428 | if (!(_cpu_based_2nd_exec_control & |
91fa0f8e | 3429 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) |
01e439be YZ |
3430 | _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; |
3431 | ||
c845f9c6 | 3432 | min = VM_ENTRY_LOAD_DEBUG_CONTROLS; |
da8999d3 | 3433 | opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS; |
1c3d14fe YS |
3434 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, |
3435 | &_vmentry_control) < 0) | |
002c7f7c | 3436 | return -EIO; |
6aa8b732 | 3437 | |
c68876fd | 3438 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
3439 | |
3440 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
3441 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 3442 | return -EIO; |
1c3d14fe YS |
3443 | |
3444 | #ifdef CONFIG_X86_64 | |
3445 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
3446 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 3447 | return -EIO; |
1c3d14fe YS |
3448 | #endif |
3449 | ||
3450 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
3451 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 3452 | return -EIO; |
1c3d14fe | 3453 | |
002c7f7c YS |
3454 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
3455 | vmcs_conf->order = get_order(vmcs_config.size); | |
3456 | vmcs_conf->revision_id = vmx_msr_low; | |
1c3d14fe | 3457 | |
002c7f7c YS |
3458 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
3459 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 3460 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
3461 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
3462 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe | 3463 | |
110312c8 AK |
3464 | cpu_has_load_ia32_efer = |
3465 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
3466 | VM_ENTRY_LOAD_IA32_EFER) | |
3467 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
3468 | VM_EXIT_LOAD_IA32_EFER); | |
3469 | ||
8bf00a52 GN |
3470 | cpu_has_load_perf_global_ctrl = |
3471 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
3472 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
3473 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
3474 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
3475 | ||
3476 | /* | |
3477 | * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL | |
bb3541f1 | 3478 | * but due to errata below it can't be used. Workaround is to use |
8bf00a52 GN |
3479 | * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL. |
3480 | * | |
3481 | * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32] | |
3482 | * | |
3483 | * AAK155 (model 26) | |
3484 | * AAP115 (model 30) | |
3485 | * AAT100 (model 37) | |
3486 | * BC86,AAY89,BD102 (model 44) | |
3487 | * BA97 (model 46) | |
3488 | * | |
3489 | */ | |
3490 | if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) { | |
3491 | switch (boot_cpu_data.x86_model) { | |
3492 | case 26: | |
3493 | case 30: | |
3494 | case 37: | |
3495 | case 44: | |
3496 | case 46: | |
3497 | cpu_has_load_perf_global_ctrl = false; | |
3498 | printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " | |
3499 | "does not work properly. Using workaround\n"); | |
3500 | break; | |
3501 | default: | |
3502 | break; | |
3503 | } | |
3504 | } | |
3505 | ||
782511b0 | 3506 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
20300099 WL |
3507 | rdmsrl(MSR_IA32_XSS, host_xss); |
3508 | ||
1c3d14fe | 3509 | return 0; |
c68876fd | 3510 | } |
6aa8b732 AK |
3511 | |
3512 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
3513 | { | |
3514 | int node = cpu_to_node(cpu); | |
3515 | struct page *pages; | |
3516 | struct vmcs *vmcs; | |
3517 | ||
96db800f | 3518 | pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
3519 | if (!pages) |
3520 | return NULL; | |
3521 | vmcs = page_address(pages); | |
1c3d14fe YS |
3522 | memset(vmcs, 0, vmcs_config.size); |
3523 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
3524 | return vmcs; |
3525 | } | |
3526 | ||
3527 | static struct vmcs *alloc_vmcs(void) | |
3528 | { | |
d3b2c338 | 3529 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
3530 | } |
3531 | ||
3532 | static void free_vmcs(struct vmcs *vmcs) | |
3533 | { | |
1c3d14fe | 3534 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
3535 | } |
3536 | ||
d462b819 NHE |
3537 | /* |
3538 | * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded | |
3539 | */ | |
3540 | static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) | |
3541 | { | |
3542 | if (!loaded_vmcs->vmcs) | |
3543 | return; | |
3544 | loaded_vmcs_clear(loaded_vmcs); | |
3545 | free_vmcs(loaded_vmcs->vmcs); | |
3546 | loaded_vmcs->vmcs = NULL; | |
3547 | } | |
3548 | ||
39959588 | 3549 | static void free_kvm_area(void) |
6aa8b732 AK |
3550 | { |
3551 | int cpu; | |
3552 | ||
3230bb47 | 3553 | for_each_possible_cpu(cpu) { |
6aa8b732 | 3554 | free_vmcs(per_cpu(vmxarea, cpu)); |
3230bb47 ZA |
3555 | per_cpu(vmxarea, cpu) = NULL; |
3556 | } | |
6aa8b732 AK |
3557 | } |
3558 | ||
fe2b201b BD |
3559 | static void init_vmcs_shadow_fields(void) |
3560 | { | |
3561 | int i, j; | |
3562 | ||
3563 | /* No checks for read only fields yet */ | |
3564 | ||
3565 | for (i = j = 0; i < max_shadow_read_write_fields; i++) { | |
3566 | switch (shadow_read_write_fields[i]) { | |
3567 | case GUEST_BNDCFGS: | |
a87036ad | 3568 | if (!kvm_mpx_supported()) |
fe2b201b BD |
3569 | continue; |
3570 | break; | |
3571 | default: | |
3572 | break; | |
3573 | } | |
3574 | ||
3575 | if (j < i) | |
3576 | shadow_read_write_fields[j] = | |
3577 | shadow_read_write_fields[i]; | |
3578 | j++; | |
3579 | } | |
3580 | max_shadow_read_write_fields = j; | |
3581 | ||
3582 | /* shadowed fields guest access without vmexit */ | |
3583 | for (i = 0; i < max_shadow_read_write_fields; i++) { | |
3584 | clear_bit(shadow_read_write_fields[i], | |
3585 | vmx_vmwrite_bitmap); | |
3586 | clear_bit(shadow_read_write_fields[i], | |
3587 | vmx_vmread_bitmap); | |
3588 | } | |
3589 | for (i = 0; i < max_shadow_read_only_fields; i++) | |
3590 | clear_bit(shadow_read_only_fields[i], | |
3591 | vmx_vmread_bitmap); | |
3592 | } | |
3593 | ||
6aa8b732 AK |
3594 | static __init int alloc_kvm_area(void) |
3595 | { | |
3596 | int cpu; | |
3597 | ||
3230bb47 | 3598 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
3599 | struct vmcs *vmcs; |
3600 | ||
3601 | vmcs = alloc_vmcs_cpu(cpu); | |
3602 | if (!vmcs) { | |
3603 | free_kvm_area(); | |
3604 | return -ENOMEM; | |
3605 | } | |
3606 | ||
3607 | per_cpu(vmxarea, cpu) = vmcs; | |
3608 | } | |
3609 | return 0; | |
3610 | } | |
3611 | ||
14168786 GN |
3612 | static bool emulation_required(struct kvm_vcpu *vcpu) |
3613 | { | |
3614 | return emulate_invalid_guest_state && !guest_state_valid(vcpu); | |
3615 | } | |
3616 | ||
91b0aa2c | 3617 | static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, |
d99e4152 | 3618 | struct kvm_segment *save) |
6aa8b732 | 3619 | { |
d99e4152 GN |
3620 | if (!emulate_invalid_guest_state) { |
3621 | /* | |
3622 | * CS and SS RPL should be equal during guest entry according | |
3623 | * to VMX spec, but in reality it is not always so. Since vcpu | |
3624 | * is in the middle of the transition from real mode to | |
3625 | * protected mode it is safe to assume that RPL 0 is a good | |
3626 | * default value. | |
3627 | */ | |
3628 | if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) | |
b32a9918 NA |
3629 | save->selector &= ~SEGMENT_RPL_MASK; |
3630 | save->dpl = save->selector & SEGMENT_RPL_MASK; | |
d99e4152 | 3631 | save->s = 1; |
6aa8b732 | 3632 | } |
d99e4152 | 3633 | vmx_set_segment(vcpu, save, seg); |
6aa8b732 AK |
3634 | } |
3635 | ||
3636 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
3637 | { | |
3638 | unsigned long flags; | |
a89a8fb9 | 3639 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 3640 | |
d99e4152 GN |
3641 | /* |
3642 | * Update real mode segment cache. It may be not up-to-date if sement | |
3643 | * register was written while vcpu was in a guest mode. | |
3644 | */ | |
3645 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
3646 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
3647 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
3648 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
3649 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); | |
3650 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
3651 | ||
7ffd92c5 | 3652 | vmx->rmode.vm86_active = 0; |
6aa8b732 | 3653 | |
2fb92db1 AK |
3654 | vmx_segment_cache_clear(vmx); |
3655 | ||
f5f7b2fe | 3656 | vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
6aa8b732 AK |
3657 | |
3658 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 AK |
3659 | flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; |
3660 | flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
6aa8b732 AK |
3661 | vmcs_writel(GUEST_RFLAGS, flags); |
3662 | ||
66aee91a RR |
3663 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
3664 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
3665 | |
3666 | update_exception_bitmap(vcpu); | |
3667 | ||
91b0aa2c GN |
3668 | fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); |
3669 | fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); | |
3670 | fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
3671 | fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
3672 | fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
3673 | fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
6aa8b732 AK |
3674 | } |
3675 | ||
f5f7b2fe | 3676 | static void fix_rmode_seg(int seg, struct kvm_segment *save) |
6aa8b732 | 3677 | { |
772e0318 | 3678 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
d99e4152 GN |
3679 | struct kvm_segment var = *save; |
3680 | ||
3681 | var.dpl = 0x3; | |
3682 | if (seg == VCPU_SREG_CS) | |
3683 | var.type = 0x3; | |
3684 | ||
3685 | if (!emulate_invalid_guest_state) { | |
3686 | var.selector = var.base >> 4; | |
3687 | var.base = var.base & 0xffff0; | |
3688 | var.limit = 0xffff; | |
3689 | var.g = 0; | |
3690 | var.db = 0; | |
3691 | var.present = 1; | |
3692 | var.s = 1; | |
3693 | var.l = 0; | |
3694 | var.unusable = 0; | |
3695 | var.type = 0x3; | |
3696 | var.avl = 0; | |
3697 | if (save->base & 0xf) | |
3698 | printk_once(KERN_WARNING "kvm: segment base is not " | |
3699 | "paragraph aligned when entering " | |
3700 | "protected mode (seg=%d)", seg); | |
3701 | } | |
6aa8b732 | 3702 | |
d99e4152 GN |
3703 | vmcs_write16(sf->selector, var.selector); |
3704 | vmcs_write32(sf->base, var.base); | |
3705 | vmcs_write32(sf->limit, var.limit); | |
3706 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); | |
6aa8b732 AK |
3707 | } |
3708 | ||
3709 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
3710 | { | |
3711 | unsigned long flags; | |
a89a8fb9 | 3712 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 3713 | |
f5f7b2fe AK |
3714 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
3715 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
3716 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
3717 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
3718 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
c6ad1153 GN |
3719 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); |
3720 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
f5f7b2fe | 3721 | |
7ffd92c5 | 3722 | vmx->rmode.vm86_active = 1; |
6aa8b732 | 3723 | |
776e58ea GN |
3724 | /* |
3725 | * Very old userspace does not call KVM_SET_TSS_ADDR before entering | |
4918c6ca | 3726 | * vcpu. Warn the user that an update is overdue. |
776e58ea | 3727 | */ |
4918c6ca | 3728 | if (!vcpu->kvm->arch.tss_addr) |
776e58ea GN |
3729 | printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " |
3730 | "called before entering vcpu\n"); | |
776e58ea | 3731 | |
2fb92db1 AK |
3732 | vmx_segment_cache_clear(vmx); |
3733 | ||
4918c6ca | 3734 | vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr); |
6aa8b732 | 3735 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
6aa8b732 AK |
3736 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
3737 | ||
3738 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 | 3739 | vmx->rmode.save_rflags = flags; |
6aa8b732 | 3740 | |
053de044 | 3741 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
3742 | |
3743 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 3744 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
3745 | update_exception_bitmap(vcpu); |
3746 | ||
d99e4152 GN |
3747 | fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); |
3748 | fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); | |
3749 | fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
3750 | fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
3751 | fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
3752 | fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
b246dd5d | 3753 | |
8668a3c4 | 3754 | kvm_mmu_reset_context(vcpu); |
6aa8b732 AK |
3755 | } |
3756 | ||
401d10de AS |
3757 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
3758 | { | |
3759 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
26bb0981 AK |
3760 | struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); |
3761 | ||
3762 | if (!msr) | |
3763 | return; | |
401d10de | 3764 | |
44ea2b17 AK |
3765 | /* |
3766 | * Force kernel_gs_base reloading before EFER changes, as control | |
3767 | * of this msr depends on is_long_mode(). | |
3768 | */ | |
3769 | vmx_load_host_state(to_vmx(vcpu)); | |
f6801dff | 3770 | vcpu->arch.efer = efer; |
401d10de | 3771 | if (efer & EFER_LMA) { |
2961e876 | 3772 | vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
3773 | msr->data = efer; |
3774 | } else { | |
2961e876 | 3775 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
3776 | |
3777 | msr->data = efer & ~EFER_LME; | |
3778 | } | |
3779 | setup_msrs(vmx); | |
3780 | } | |
3781 | ||
05b3e0c2 | 3782 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
3783 | |
3784 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
3785 | { | |
3786 | u32 guest_tr_ar; | |
3787 | ||
2fb92db1 AK |
3788 | vmx_segment_cache_clear(to_vmx(vcpu)); |
3789 | ||
6aa8b732 | 3790 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); |
4d283ec9 | 3791 | if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { |
bd80158a JK |
3792 | pr_debug_ratelimited("%s: tss fixup for long mode. \n", |
3793 | __func__); | |
6aa8b732 | 3794 | vmcs_write32(GUEST_TR_AR_BYTES, |
4d283ec9 AL |
3795 | (guest_tr_ar & ~VMX_AR_TYPE_MASK) |
3796 | | VMX_AR_TYPE_BUSY_64_TSS); | |
6aa8b732 | 3797 | } |
da38f438 | 3798 | vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); |
6aa8b732 AK |
3799 | } |
3800 | ||
3801 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
3802 | { | |
2961e876 | 3803 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
da38f438 | 3804 | vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); |
6aa8b732 AK |
3805 | } |
3806 | ||
3807 | #endif | |
3808 | ||
dd5f5341 | 3809 | static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid) |
2384d2b3 | 3810 | { |
dd5f5341 | 3811 | vpid_sync_context(vpid); |
dd180b3e XG |
3812 | if (enable_ept) { |
3813 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
3814 | return; | |
4e1096d2 | 3815 | ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa)); |
dd180b3e | 3816 | } |
2384d2b3 SY |
3817 | } |
3818 | ||
dd5f5341 WL |
3819 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
3820 | { | |
3821 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid); | |
3822 | } | |
3823 | ||
e8467fda AK |
3824 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
3825 | { | |
3826 | ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; | |
3827 | ||
3828 | vcpu->arch.cr0 &= ~cr0_guest_owned_bits; | |
3829 | vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; | |
3830 | } | |
3831 | ||
aff48baa AK |
3832 | static void vmx_decache_cr3(struct kvm_vcpu *vcpu) |
3833 | { | |
3834 | if (enable_ept && is_paging(vcpu)) | |
3835 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); | |
3836 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
3837 | } | |
3838 | ||
25c4c276 | 3839 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 3840 | { |
fc78f519 AK |
3841 | ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; |
3842 | ||
3843 | vcpu->arch.cr4 &= ~cr4_guest_owned_bits; | |
3844 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; | |
399badf3 AK |
3845 | } |
3846 | ||
1439442c SY |
3847 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
3848 | { | |
d0d538b9 GN |
3849 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
3850 | ||
6de4f3ad AK |
3851 | if (!test_bit(VCPU_EXREG_PDPTR, |
3852 | (unsigned long *)&vcpu->arch.regs_dirty)) | |
3853 | return; | |
3854 | ||
1439442c | 3855 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
d0d538b9 GN |
3856 | vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); |
3857 | vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); | |
3858 | vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); | |
3859 | vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); | |
1439442c SY |
3860 | } |
3861 | } | |
3862 | ||
8f5d549f AK |
3863 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu) |
3864 | { | |
d0d538b9 GN |
3865 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
3866 | ||
8f5d549f | 3867 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
d0d538b9 GN |
3868 | mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); |
3869 | mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); | |
3870 | mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); | |
3871 | mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); | |
8f5d549f | 3872 | } |
6de4f3ad AK |
3873 | |
3874 | __set_bit(VCPU_EXREG_PDPTR, | |
3875 | (unsigned long *)&vcpu->arch.regs_avail); | |
3876 | __set_bit(VCPU_EXREG_PDPTR, | |
3877 | (unsigned long *)&vcpu->arch.regs_dirty); | |
8f5d549f AK |
3878 | } |
3879 | ||
5e1746d6 | 3880 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
1439442c SY |
3881 | |
3882 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
3883 | unsigned long cr0, | |
3884 | struct kvm_vcpu *vcpu) | |
3885 | { | |
5233dd51 MT |
3886 | if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) |
3887 | vmx_decache_cr3(vcpu); | |
1439442c SY |
3888 | if (!(cr0 & X86_CR0_PG)) { |
3889 | /* From paging/starting to nonpaging */ | |
3890 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 3891 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
1439442c SY |
3892 | (CPU_BASED_CR3_LOAD_EXITING | |
3893 | CPU_BASED_CR3_STORE_EXITING)); | |
3894 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 3895 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c SY |
3896 | } else if (!is_paging(vcpu)) { |
3897 | /* From nonpaging to paging */ | |
3898 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 3899 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
1439442c SY |
3900 | ~(CPU_BASED_CR3_LOAD_EXITING | |
3901 | CPU_BASED_CR3_STORE_EXITING)); | |
3902 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 3903 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c | 3904 | } |
95eb84a7 SY |
3905 | |
3906 | if (!(cr0 & X86_CR0_WP)) | |
3907 | *hw_cr0 &= ~X86_CR0_WP; | |
1439442c SY |
3908 | } |
3909 | ||
6aa8b732 AK |
3910 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
3911 | { | |
7ffd92c5 | 3912 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3a624e29 NK |
3913 | unsigned long hw_cr0; |
3914 | ||
5037878e | 3915 | hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK); |
3a624e29 | 3916 | if (enable_unrestricted_guest) |
5037878e | 3917 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; |
218e763f | 3918 | else { |
5037878e | 3919 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; |
1439442c | 3920 | |
218e763f GN |
3921 | if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) |
3922 | enter_pmode(vcpu); | |
6aa8b732 | 3923 | |
218e763f GN |
3924 | if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) |
3925 | enter_rmode(vcpu); | |
3926 | } | |
6aa8b732 | 3927 | |
05b3e0c2 | 3928 | #ifdef CONFIG_X86_64 |
f6801dff | 3929 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 3930 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 3931 | enter_lmode(vcpu); |
707d92fa | 3932 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
3933 | exit_lmode(vcpu); |
3934 | } | |
3935 | #endif | |
3936 | ||
089d034e | 3937 | if (enable_ept) |
1439442c SY |
3938 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); |
3939 | ||
02daab21 | 3940 | if (!vcpu->fpu_active) |
81231c69 | 3941 | hw_cr0 |= X86_CR0_TS | X86_CR0_MP; |
02daab21 | 3942 | |
6aa8b732 | 3943 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 3944 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 3945 | vcpu->arch.cr0 = cr0; |
14168786 GN |
3946 | |
3947 | /* depends on vcpu->arch.cr0 to be set to a new value */ | |
3948 | vmx->emulation_required = emulation_required(vcpu); | |
6aa8b732 AK |
3949 | } |
3950 | ||
1439442c SY |
3951 | static u64 construct_eptp(unsigned long root_hpa) |
3952 | { | |
3953 | u64 eptp; | |
3954 | ||
3955 | /* TODO write the value reading from MSR */ | |
3956 | eptp = VMX_EPT_DEFAULT_MT | | |
3957 | VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT; | |
b38f9934 XH |
3958 | if (enable_ept_ad_bits) |
3959 | eptp |= VMX_EPT_AD_ENABLE_BIT; | |
1439442c SY |
3960 | eptp |= (root_hpa & PAGE_MASK); |
3961 | ||
3962 | return eptp; | |
3963 | } | |
3964 | ||
6aa8b732 AK |
3965 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
3966 | { | |
1439442c SY |
3967 | unsigned long guest_cr3; |
3968 | u64 eptp; | |
3969 | ||
3970 | guest_cr3 = cr3; | |
089d034e | 3971 | if (enable_ept) { |
1439442c SY |
3972 | eptp = construct_eptp(cr3); |
3973 | vmcs_write64(EPT_POINTER, eptp); | |
59ab5a8f JK |
3974 | if (is_paging(vcpu) || is_guest_mode(vcpu)) |
3975 | guest_cr3 = kvm_read_cr3(vcpu); | |
3976 | else | |
3977 | guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr; | |
7c93be44 | 3978 | ept_load_pdptrs(vcpu); |
1439442c SY |
3979 | } |
3980 | ||
2384d2b3 | 3981 | vmx_flush_tlb(vcpu); |
1439442c | 3982 | vmcs_writel(GUEST_CR3, guest_cr3); |
6aa8b732 AK |
3983 | } |
3984 | ||
5e1746d6 | 3985 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 3986 | { |
085e68ee BS |
3987 | /* |
3988 | * Pass through host's Machine Check Enable value to hw_cr4, which | |
3989 | * is in force while we are in guest mode. Do not let guests control | |
3990 | * this bit, even if host CR4.MCE == 0. | |
3991 | */ | |
3992 | unsigned long hw_cr4 = | |
3993 | (cr4_read_shadow() & X86_CR4_MCE) | | |
3994 | (cr4 & ~X86_CR4_MCE) | | |
3995 | (to_vmx(vcpu)->rmode.vm86_active ? | |
3996 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); | |
1439442c | 3997 | |
5e1746d6 NHE |
3998 | if (cr4 & X86_CR4_VMXE) { |
3999 | /* | |
4000 | * To use VMXON (and later other VMX instructions), a guest | |
4001 | * must first be able to turn on cr4.VMXE (see handle_vmon()). | |
4002 | * So basically the check on whether to allow nested VMX | |
4003 | * is here. | |
4004 | */ | |
4005 | if (!nested_vmx_allowed(vcpu)) | |
4006 | return 1; | |
1a0d74e6 JK |
4007 | } |
4008 | if (to_vmx(vcpu)->nested.vmxon && | |
4009 | ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) | |
5e1746d6 NHE |
4010 | return 1; |
4011 | ||
ad312c7c | 4012 | vcpu->arch.cr4 = cr4; |
bc23008b AK |
4013 | if (enable_ept) { |
4014 | if (!is_paging(vcpu)) { | |
4015 | hw_cr4 &= ~X86_CR4_PAE; | |
4016 | hw_cr4 |= X86_CR4_PSE; | |
4017 | } else if (!(cr4 & X86_CR4_PAE)) { | |
4018 | hw_cr4 &= ~X86_CR4_PAE; | |
4019 | } | |
4020 | } | |
1439442c | 4021 | |
656ec4a4 RK |
4022 | if (!enable_unrestricted_guest && !is_paging(vcpu)) |
4023 | /* | |
ddba2628 HH |
4024 | * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in |
4025 | * hardware. To emulate this behavior, SMEP/SMAP/PKU needs | |
4026 | * to be manually disabled when guest switches to non-paging | |
4027 | * mode. | |
4028 | * | |
4029 | * If !enable_unrestricted_guest, the CPU is always running | |
4030 | * with CR0.PG=1 and CR4 needs to be modified. | |
4031 | * If enable_unrestricted_guest, the CPU automatically | |
4032 | * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. | |
656ec4a4 | 4033 | */ |
ddba2628 | 4034 | hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); |
656ec4a4 | 4035 | |
1439442c SY |
4036 | vmcs_writel(CR4_READ_SHADOW, cr4); |
4037 | vmcs_writel(GUEST_CR4, hw_cr4); | |
5e1746d6 | 4038 | return 0; |
6aa8b732 AK |
4039 | } |
4040 | ||
6aa8b732 AK |
4041 | static void vmx_get_segment(struct kvm_vcpu *vcpu, |
4042 | struct kvm_segment *var, int seg) | |
4043 | { | |
a9179499 | 4044 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 AK |
4045 | u32 ar; |
4046 | ||
c6ad1153 | 4047 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
f5f7b2fe | 4048 | *var = vmx->rmode.segs[seg]; |
a9179499 | 4049 | if (seg == VCPU_SREG_TR |
2fb92db1 | 4050 | || var->selector == vmx_read_guest_seg_selector(vmx, seg)) |
f5f7b2fe | 4051 | return; |
1390a28b AK |
4052 | var->base = vmx_read_guest_seg_base(vmx, seg); |
4053 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
4054 | return; | |
a9179499 | 4055 | } |
2fb92db1 AK |
4056 | var->base = vmx_read_guest_seg_base(vmx, seg); |
4057 | var->limit = vmx_read_guest_seg_limit(vmx, seg); | |
4058 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
4059 | ar = vmx_read_guest_seg_ar(vmx, seg); | |
03617c18 | 4060 | var->unusable = (ar >> 16) & 1; |
6aa8b732 AK |
4061 | var->type = ar & 15; |
4062 | var->s = (ar >> 4) & 1; | |
4063 | var->dpl = (ar >> 5) & 3; | |
03617c18 GN |
4064 | /* |
4065 | * Some userspaces do not preserve unusable property. Since usable | |
4066 | * segment has to be present according to VMX spec we can use present | |
4067 | * property to amend userspace bug by making unusable segment always | |
4068 | * nonpresent. vmx_segment_access_rights() already marks nonpresent | |
4069 | * segment as unusable. | |
4070 | */ | |
4071 | var->present = !var->unusable; | |
6aa8b732 AK |
4072 | var->avl = (ar >> 12) & 1; |
4073 | var->l = (ar >> 13) & 1; | |
4074 | var->db = (ar >> 14) & 1; | |
4075 | var->g = (ar >> 15) & 1; | |
6aa8b732 AK |
4076 | } |
4077 | ||
a9179499 AK |
4078 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4079 | { | |
a9179499 AK |
4080 | struct kvm_segment s; |
4081 | ||
4082 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
4083 | vmx_get_segment(vcpu, &s, seg); | |
4084 | return s.base; | |
4085 | } | |
2fb92db1 | 4086 | return vmx_read_guest_seg_base(to_vmx(vcpu), seg); |
a9179499 AK |
4087 | } |
4088 | ||
b09408d0 | 4089 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
2e4d2653 | 4090 | { |
b09408d0 MT |
4091 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4092 | ||
ae9fedc7 | 4093 | if (unlikely(vmx->rmode.vm86_active)) |
2e4d2653 | 4094 | return 0; |
ae9fedc7 PB |
4095 | else { |
4096 | int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); | |
4d283ec9 | 4097 | return VMX_AR_DPL(ar); |
69c73028 | 4098 | } |
69c73028 AK |
4099 | } |
4100 | ||
653e3108 | 4101 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 4102 | { |
6aa8b732 AK |
4103 | u32 ar; |
4104 | ||
f0495f9b | 4105 | if (var->unusable || !var->present) |
6aa8b732 AK |
4106 | ar = 1 << 16; |
4107 | else { | |
4108 | ar = var->type & 15; | |
4109 | ar |= (var->s & 1) << 4; | |
4110 | ar |= (var->dpl & 3) << 5; | |
4111 | ar |= (var->present & 1) << 7; | |
4112 | ar |= (var->avl & 1) << 12; | |
4113 | ar |= (var->l & 1) << 13; | |
4114 | ar |= (var->db & 1) << 14; | |
4115 | ar |= (var->g & 1) << 15; | |
4116 | } | |
653e3108 AK |
4117 | |
4118 | return ar; | |
4119 | } | |
4120 | ||
4121 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
4122 | struct kvm_segment *var, int seg) | |
4123 | { | |
7ffd92c5 | 4124 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
772e0318 | 4125 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
653e3108 | 4126 | |
2fb92db1 AK |
4127 | vmx_segment_cache_clear(vmx); |
4128 | ||
1ecd50a9 GN |
4129 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
4130 | vmx->rmode.segs[seg] = *var; | |
4131 | if (seg == VCPU_SREG_TR) | |
4132 | vmcs_write16(sf->selector, var->selector); | |
4133 | else if (var->s) | |
4134 | fix_rmode_seg(seg, &vmx->rmode.segs[seg]); | |
d99e4152 | 4135 | goto out; |
653e3108 | 4136 | } |
1ecd50a9 | 4137 | |
653e3108 AK |
4138 | vmcs_writel(sf->base, var->base); |
4139 | vmcs_write32(sf->limit, var->limit); | |
4140 | vmcs_write16(sf->selector, var->selector); | |
3a624e29 NK |
4141 | |
4142 | /* | |
4143 | * Fix the "Accessed" bit in AR field of segment registers for older | |
4144 | * qemu binaries. | |
4145 | * IA32 arch specifies that at the time of processor reset the | |
4146 | * "Accessed" bit in the AR field of segment registers is 1. And qemu | |
0fa06071 | 4147 | * is setting it to 0 in the userland code. This causes invalid guest |
3a624e29 NK |
4148 | * state vmexit when "unrestricted guest" mode is turned on. |
4149 | * Fix for this setup issue in cpu_reset is being pushed in the qemu | |
4150 | * tree. Newer qemu binaries with that qemu fix would not need this | |
4151 | * kvm hack. | |
4152 | */ | |
4153 | if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) | |
f924d66d | 4154 | var->type |= 0x1; /* Accessed */ |
3a624e29 | 4155 | |
f924d66d | 4156 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); |
d99e4152 GN |
4157 | |
4158 | out: | |
98eb2f8b | 4159 | vmx->emulation_required = emulation_required(vcpu); |
6aa8b732 AK |
4160 | } |
4161 | ||
6aa8b732 AK |
4162 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
4163 | { | |
2fb92db1 | 4164 | u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); |
6aa8b732 AK |
4165 | |
4166 | *db = (ar >> 14) & 1; | |
4167 | *l = (ar >> 13) & 1; | |
4168 | } | |
4169 | ||
89a27f4d | 4170 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4171 | { |
89a27f4d GN |
4172 | dt->size = vmcs_read32(GUEST_IDTR_LIMIT); |
4173 | dt->address = vmcs_readl(GUEST_IDTR_BASE); | |
6aa8b732 AK |
4174 | } |
4175 | ||
89a27f4d | 4176 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4177 | { |
89a27f4d GN |
4178 | vmcs_write32(GUEST_IDTR_LIMIT, dt->size); |
4179 | vmcs_writel(GUEST_IDTR_BASE, dt->address); | |
6aa8b732 AK |
4180 | } |
4181 | ||
89a27f4d | 4182 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4183 | { |
89a27f4d GN |
4184 | dt->size = vmcs_read32(GUEST_GDTR_LIMIT); |
4185 | dt->address = vmcs_readl(GUEST_GDTR_BASE); | |
6aa8b732 AK |
4186 | } |
4187 | ||
89a27f4d | 4188 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4189 | { |
89a27f4d GN |
4190 | vmcs_write32(GUEST_GDTR_LIMIT, dt->size); |
4191 | vmcs_writel(GUEST_GDTR_BASE, dt->address); | |
6aa8b732 AK |
4192 | } |
4193 | ||
648dfaa7 MG |
4194 | static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) |
4195 | { | |
4196 | struct kvm_segment var; | |
4197 | u32 ar; | |
4198 | ||
4199 | vmx_get_segment(vcpu, &var, seg); | |
07f42f5f | 4200 | var.dpl = 0x3; |
0647f4aa GN |
4201 | if (seg == VCPU_SREG_CS) |
4202 | var.type = 0x3; | |
648dfaa7 MG |
4203 | ar = vmx_segment_access_rights(&var); |
4204 | ||
4205 | if (var.base != (var.selector << 4)) | |
4206 | return false; | |
89efbed0 | 4207 | if (var.limit != 0xffff) |
648dfaa7 | 4208 | return false; |
07f42f5f | 4209 | if (ar != 0xf3) |
648dfaa7 MG |
4210 | return false; |
4211 | ||
4212 | return true; | |
4213 | } | |
4214 | ||
4215 | static bool code_segment_valid(struct kvm_vcpu *vcpu) | |
4216 | { | |
4217 | struct kvm_segment cs; | |
4218 | unsigned int cs_rpl; | |
4219 | ||
4220 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
b32a9918 | 4221 | cs_rpl = cs.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4222 | |
1872a3f4 AK |
4223 | if (cs.unusable) |
4224 | return false; | |
4d283ec9 | 4225 | if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) |
648dfaa7 MG |
4226 | return false; |
4227 | if (!cs.s) | |
4228 | return false; | |
4d283ec9 | 4229 | if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { |
648dfaa7 MG |
4230 | if (cs.dpl > cs_rpl) |
4231 | return false; | |
1872a3f4 | 4232 | } else { |
648dfaa7 MG |
4233 | if (cs.dpl != cs_rpl) |
4234 | return false; | |
4235 | } | |
4236 | if (!cs.present) | |
4237 | return false; | |
4238 | ||
4239 | /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ | |
4240 | return true; | |
4241 | } | |
4242 | ||
4243 | static bool stack_segment_valid(struct kvm_vcpu *vcpu) | |
4244 | { | |
4245 | struct kvm_segment ss; | |
4246 | unsigned int ss_rpl; | |
4247 | ||
4248 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
b32a9918 | 4249 | ss_rpl = ss.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4250 | |
1872a3f4 AK |
4251 | if (ss.unusable) |
4252 | return true; | |
4253 | if (ss.type != 3 && ss.type != 7) | |
648dfaa7 MG |
4254 | return false; |
4255 | if (!ss.s) | |
4256 | return false; | |
4257 | if (ss.dpl != ss_rpl) /* DPL != RPL */ | |
4258 | return false; | |
4259 | if (!ss.present) | |
4260 | return false; | |
4261 | ||
4262 | return true; | |
4263 | } | |
4264 | ||
4265 | static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) | |
4266 | { | |
4267 | struct kvm_segment var; | |
4268 | unsigned int rpl; | |
4269 | ||
4270 | vmx_get_segment(vcpu, &var, seg); | |
b32a9918 | 4271 | rpl = var.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4272 | |
1872a3f4 AK |
4273 | if (var.unusable) |
4274 | return true; | |
648dfaa7 MG |
4275 | if (!var.s) |
4276 | return false; | |
4277 | if (!var.present) | |
4278 | return false; | |
4d283ec9 | 4279 | if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { |
648dfaa7 MG |
4280 | if (var.dpl < rpl) /* DPL < RPL */ |
4281 | return false; | |
4282 | } | |
4283 | ||
4284 | /* TODO: Add other members to kvm_segment_field to allow checking for other access | |
4285 | * rights flags | |
4286 | */ | |
4287 | return true; | |
4288 | } | |
4289 | ||
4290 | static bool tr_valid(struct kvm_vcpu *vcpu) | |
4291 | { | |
4292 | struct kvm_segment tr; | |
4293 | ||
4294 | vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); | |
4295 | ||
1872a3f4 AK |
4296 | if (tr.unusable) |
4297 | return false; | |
b32a9918 | 4298 | if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 | 4299 | return false; |
1872a3f4 | 4300 | if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ |
648dfaa7 MG |
4301 | return false; |
4302 | if (!tr.present) | |
4303 | return false; | |
4304 | ||
4305 | return true; | |
4306 | } | |
4307 | ||
4308 | static bool ldtr_valid(struct kvm_vcpu *vcpu) | |
4309 | { | |
4310 | struct kvm_segment ldtr; | |
4311 | ||
4312 | vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); | |
4313 | ||
1872a3f4 AK |
4314 | if (ldtr.unusable) |
4315 | return true; | |
b32a9918 | 4316 | if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 MG |
4317 | return false; |
4318 | if (ldtr.type != 2) | |
4319 | return false; | |
4320 | if (!ldtr.present) | |
4321 | return false; | |
4322 | ||
4323 | return true; | |
4324 | } | |
4325 | ||
4326 | static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) | |
4327 | { | |
4328 | struct kvm_segment cs, ss; | |
4329 | ||
4330 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
4331 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
4332 | ||
b32a9918 NA |
4333 | return ((cs.selector & SEGMENT_RPL_MASK) == |
4334 | (ss.selector & SEGMENT_RPL_MASK)); | |
648dfaa7 MG |
4335 | } |
4336 | ||
4337 | /* | |
4338 | * Check if guest state is valid. Returns true if valid, false if | |
4339 | * not. | |
4340 | * We assume that registers are always usable | |
4341 | */ | |
4342 | static bool guest_state_valid(struct kvm_vcpu *vcpu) | |
4343 | { | |
c5e97c80 GN |
4344 | if (enable_unrestricted_guest) |
4345 | return true; | |
4346 | ||
648dfaa7 | 4347 | /* real mode guest state checks */ |
f13882d8 | 4348 | if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { |
648dfaa7 MG |
4349 | if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) |
4350 | return false; | |
4351 | if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) | |
4352 | return false; | |
4353 | if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) | |
4354 | return false; | |
4355 | if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) | |
4356 | return false; | |
4357 | if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) | |
4358 | return false; | |
4359 | if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) | |
4360 | return false; | |
4361 | } else { | |
4362 | /* protected mode guest state checks */ | |
4363 | if (!cs_ss_rpl_check(vcpu)) | |
4364 | return false; | |
4365 | if (!code_segment_valid(vcpu)) | |
4366 | return false; | |
4367 | if (!stack_segment_valid(vcpu)) | |
4368 | return false; | |
4369 | if (!data_segment_valid(vcpu, VCPU_SREG_DS)) | |
4370 | return false; | |
4371 | if (!data_segment_valid(vcpu, VCPU_SREG_ES)) | |
4372 | return false; | |
4373 | if (!data_segment_valid(vcpu, VCPU_SREG_FS)) | |
4374 | return false; | |
4375 | if (!data_segment_valid(vcpu, VCPU_SREG_GS)) | |
4376 | return false; | |
4377 | if (!tr_valid(vcpu)) | |
4378 | return false; | |
4379 | if (!ldtr_valid(vcpu)) | |
4380 | return false; | |
4381 | } | |
4382 | /* TODO: | |
4383 | * - Add checks on RIP | |
4384 | * - Add checks on RFLAGS | |
4385 | */ | |
4386 | ||
4387 | return true; | |
4388 | } | |
4389 | ||
d77c26fc | 4390 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 4391 | { |
40dcaa9f | 4392 | gfn_t fn; |
195aefde | 4393 | u16 data = 0; |
1f755a82 | 4394 | int idx, r; |
6aa8b732 | 4395 | |
40dcaa9f | 4396 | idx = srcu_read_lock(&kvm->srcu); |
4918c6ca | 4397 | fn = kvm->arch.tss_addr >> PAGE_SHIFT; |
195aefde IE |
4398 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
4399 | if (r < 0) | |
10589a46 | 4400 | goto out; |
195aefde | 4401 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
464d17c8 SY |
4402 | r = kvm_write_guest_page(kvm, fn++, &data, |
4403 | TSS_IOPB_BASE_OFFSET, sizeof(u16)); | |
195aefde | 4404 | if (r < 0) |
10589a46 | 4405 | goto out; |
195aefde IE |
4406 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
4407 | if (r < 0) | |
10589a46 | 4408 | goto out; |
195aefde IE |
4409 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
4410 | if (r < 0) | |
10589a46 | 4411 | goto out; |
195aefde | 4412 | data = ~0; |
10589a46 MT |
4413 | r = kvm_write_guest_page(kvm, fn, &data, |
4414 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
4415 | sizeof(u8)); | |
10589a46 | 4416 | out: |
40dcaa9f | 4417 | srcu_read_unlock(&kvm->srcu, idx); |
1f755a82 | 4418 | return r; |
6aa8b732 AK |
4419 | } |
4420 | ||
b7ebfb05 SY |
4421 | static int init_rmode_identity_map(struct kvm *kvm) |
4422 | { | |
f51770ed | 4423 | int i, idx, r = 0; |
ba049e93 | 4424 | kvm_pfn_t identity_map_pfn; |
b7ebfb05 SY |
4425 | u32 tmp; |
4426 | ||
089d034e | 4427 | if (!enable_ept) |
f51770ed | 4428 | return 0; |
a255d479 TC |
4429 | |
4430 | /* Protect kvm->arch.ept_identity_pagetable_done. */ | |
4431 | mutex_lock(&kvm->slots_lock); | |
4432 | ||
f51770ed | 4433 | if (likely(kvm->arch.ept_identity_pagetable_done)) |
a255d479 | 4434 | goto out2; |
a255d479 | 4435 | |
b927a3ce | 4436 | identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT; |
a255d479 TC |
4437 | |
4438 | r = alloc_identity_pagetable(kvm); | |
f51770ed | 4439 | if (r < 0) |
a255d479 TC |
4440 | goto out2; |
4441 | ||
40dcaa9f | 4442 | idx = srcu_read_lock(&kvm->srcu); |
b7ebfb05 SY |
4443 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); |
4444 | if (r < 0) | |
4445 | goto out; | |
4446 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
4447 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
4448 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
4449 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
4450 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
4451 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
4452 | if (r < 0) | |
4453 | goto out; | |
4454 | } | |
4455 | kvm->arch.ept_identity_pagetable_done = true; | |
f51770ed | 4456 | |
b7ebfb05 | 4457 | out: |
40dcaa9f | 4458 | srcu_read_unlock(&kvm->srcu, idx); |
a255d479 TC |
4459 | |
4460 | out2: | |
4461 | mutex_unlock(&kvm->slots_lock); | |
f51770ed | 4462 | return r; |
b7ebfb05 SY |
4463 | } |
4464 | ||
6aa8b732 AK |
4465 | static void seg_setup(int seg) |
4466 | { | |
772e0318 | 4467 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
3a624e29 | 4468 | unsigned int ar; |
6aa8b732 AK |
4469 | |
4470 | vmcs_write16(sf->selector, 0); | |
4471 | vmcs_writel(sf->base, 0); | |
4472 | vmcs_write32(sf->limit, 0xffff); | |
d54d07b2 GN |
4473 | ar = 0x93; |
4474 | if (seg == VCPU_SREG_CS) | |
4475 | ar |= 0x08; /* code segment */ | |
3a624e29 NK |
4476 | |
4477 | vmcs_write32(sf->ar_bytes, ar); | |
6aa8b732 AK |
4478 | } |
4479 | ||
f78e0e2e SY |
4480 | static int alloc_apic_access_page(struct kvm *kvm) |
4481 | { | |
4484141a | 4482 | struct page *page; |
f78e0e2e SY |
4483 | int r = 0; |
4484 | ||
79fac95e | 4485 | mutex_lock(&kvm->slots_lock); |
c24ae0dc | 4486 | if (kvm->arch.apic_access_page_done) |
f78e0e2e | 4487 | goto out; |
1d8007bd PB |
4488 | r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, |
4489 | APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); | |
f78e0e2e SY |
4490 | if (r) |
4491 | goto out; | |
72dc67a6 | 4492 | |
73a6d941 | 4493 | page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
4484141a XG |
4494 | if (is_error_page(page)) { |
4495 | r = -EFAULT; | |
4496 | goto out; | |
4497 | } | |
4498 | ||
c24ae0dc TC |
4499 | /* |
4500 | * Do not pin the page in memory, so that memory hot-unplug | |
4501 | * is able to migrate it. | |
4502 | */ | |
4503 | put_page(page); | |
4504 | kvm->arch.apic_access_page_done = true; | |
f78e0e2e | 4505 | out: |
79fac95e | 4506 | mutex_unlock(&kvm->slots_lock); |
f78e0e2e SY |
4507 | return r; |
4508 | } | |
4509 | ||
b7ebfb05 SY |
4510 | static int alloc_identity_pagetable(struct kvm *kvm) |
4511 | { | |
a255d479 TC |
4512 | /* Called with kvm->slots_lock held. */ |
4513 | ||
b7ebfb05 SY |
4514 | int r = 0; |
4515 | ||
a255d479 TC |
4516 | BUG_ON(kvm->arch.ept_identity_pagetable_done); |
4517 | ||
1d8007bd PB |
4518 | r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, |
4519 | kvm->arch.ept_identity_map_addr, PAGE_SIZE); | |
b7ebfb05 | 4520 | |
b7ebfb05 SY |
4521 | return r; |
4522 | } | |
4523 | ||
991e7a0e | 4524 | static int allocate_vpid(void) |
2384d2b3 SY |
4525 | { |
4526 | int vpid; | |
4527 | ||
919818ab | 4528 | if (!enable_vpid) |
991e7a0e | 4529 | return 0; |
2384d2b3 SY |
4530 | spin_lock(&vmx_vpid_lock); |
4531 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
991e7a0e | 4532 | if (vpid < VMX_NR_VPIDS) |
2384d2b3 | 4533 | __set_bit(vpid, vmx_vpid_bitmap); |
991e7a0e WL |
4534 | else |
4535 | vpid = 0; | |
2384d2b3 | 4536 | spin_unlock(&vmx_vpid_lock); |
991e7a0e | 4537 | return vpid; |
2384d2b3 SY |
4538 | } |
4539 | ||
991e7a0e | 4540 | static void free_vpid(int vpid) |
cdbecfc3 | 4541 | { |
991e7a0e | 4542 | if (!enable_vpid || vpid == 0) |
cdbecfc3 LJ |
4543 | return; |
4544 | spin_lock(&vmx_vpid_lock); | |
991e7a0e | 4545 | __clear_bit(vpid, vmx_vpid_bitmap); |
cdbecfc3 LJ |
4546 | spin_unlock(&vmx_vpid_lock); |
4547 | } | |
4548 | ||
8d14695f YZ |
4549 | #define MSR_TYPE_R 1 |
4550 | #define MSR_TYPE_W 2 | |
4551 | static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, | |
4552 | u32 msr, int type) | |
25c5f225 | 4553 | { |
3e7c73e9 | 4554 | int f = sizeof(unsigned long); |
25c5f225 SY |
4555 | |
4556 | if (!cpu_has_vmx_msr_bitmap()) | |
4557 | return; | |
4558 | ||
4559 | /* | |
4560 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
4561 | * have the write-low and read-high bitmap offsets the wrong way round. | |
4562 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
4563 | */ | |
25c5f225 | 4564 | if (msr <= 0x1fff) { |
8d14695f YZ |
4565 | if (type & MSR_TYPE_R) |
4566 | /* read-low */ | |
4567 | __clear_bit(msr, msr_bitmap + 0x000 / f); | |
4568 | ||
4569 | if (type & MSR_TYPE_W) | |
4570 | /* write-low */ | |
4571 | __clear_bit(msr, msr_bitmap + 0x800 / f); | |
4572 | ||
25c5f225 SY |
4573 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { |
4574 | msr &= 0x1fff; | |
8d14695f YZ |
4575 | if (type & MSR_TYPE_R) |
4576 | /* read-high */ | |
4577 | __clear_bit(msr, msr_bitmap + 0x400 / f); | |
4578 | ||
4579 | if (type & MSR_TYPE_W) | |
4580 | /* write-high */ | |
4581 | __clear_bit(msr, msr_bitmap + 0xc00 / f); | |
4582 | ||
4583 | } | |
4584 | } | |
4585 | ||
4586 | static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, | |
4587 | u32 msr, int type) | |
4588 | { | |
4589 | int f = sizeof(unsigned long); | |
4590 | ||
4591 | if (!cpu_has_vmx_msr_bitmap()) | |
4592 | return; | |
4593 | ||
4594 | /* | |
4595 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
4596 | * have the write-low and read-high bitmap offsets the wrong way round. | |
4597 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
4598 | */ | |
4599 | if (msr <= 0x1fff) { | |
4600 | if (type & MSR_TYPE_R) | |
4601 | /* read-low */ | |
4602 | __set_bit(msr, msr_bitmap + 0x000 / f); | |
4603 | ||
4604 | if (type & MSR_TYPE_W) | |
4605 | /* write-low */ | |
4606 | __set_bit(msr, msr_bitmap + 0x800 / f); | |
4607 | ||
4608 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
4609 | msr &= 0x1fff; | |
4610 | if (type & MSR_TYPE_R) | |
4611 | /* read-high */ | |
4612 | __set_bit(msr, msr_bitmap + 0x400 / f); | |
4613 | ||
4614 | if (type & MSR_TYPE_W) | |
4615 | /* write-high */ | |
4616 | __set_bit(msr, msr_bitmap + 0xc00 / f); | |
4617 | ||
25c5f225 | 4618 | } |
25c5f225 SY |
4619 | } |
4620 | ||
f2b93280 WV |
4621 | /* |
4622 | * If a msr is allowed by L0, we should check whether it is allowed by L1. | |
4623 | * The corresponding bit will be cleared unless both of L0 and L1 allow it. | |
4624 | */ | |
4625 | static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1, | |
4626 | unsigned long *msr_bitmap_nested, | |
4627 | u32 msr, int type) | |
4628 | { | |
4629 | int f = sizeof(unsigned long); | |
4630 | ||
4631 | if (!cpu_has_vmx_msr_bitmap()) { | |
4632 | WARN_ON(1); | |
4633 | return; | |
4634 | } | |
4635 | ||
4636 | /* | |
4637 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
4638 | * have the write-low and read-high bitmap offsets the wrong way round. | |
4639 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
4640 | */ | |
4641 | if (msr <= 0x1fff) { | |
4642 | if (type & MSR_TYPE_R && | |
4643 | !test_bit(msr, msr_bitmap_l1 + 0x000 / f)) | |
4644 | /* read-low */ | |
4645 | __clear_bit(msr, msr_bitmap_nested + 0x000 / f); | |
4646 | ||
4647 | if (type & MSR_TYPE_W && | |
4648 | !test_bit(msr, msr_bitmap_l1 + 0x800 / f)) | |
4649 | /* write-low */ | |
4650 | __clear_bit(msr, msr_bitmap_nested + 0x800 / f); | |
4651 | ||
4652 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
4653 | msr &= 0x1fff; | |
4654 | if (type & MSR_TYPE_R && | |
4655 | !test_bit(msr, msr_bitmap_l1 + 0x400 / f)) | |
4656 | /* read-high */ | |
4657 | __clear_bit(msr, msr_bitmap_nested + 0x400 / f); | |
4658 | ||
4659 | if (type & MSR_TYPE_W && | |
4660 | !test_bit(msr, msr_bitmap_l1 + 0xc00 / f)) | |
4661 | /* write-high */ | |
4662 | __clear_bit(msr, msr_bitmap_nested + 0xc00 / f); | |
4663 | ||
4664 | } | |
4665 | } | |
4666 | ||
5897297b AK |
4667 | static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only) |
4668 | { | |
4669 | if (!longmode_only) | |
8d14695f YZ |
4670 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, |
4671 | msr, MSR_TYPE_R | MSR_TYPE_W); | |
4672 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, | |
4673 | msr, MSR_TYPE_R | MSR_TYPE_W); | |
4674 | } | |
4675 | ||
4676 | static void vmx_enable_intercept_msr_read_x2apic(u32 msr) | |
4677 | { | |
4678 | __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic, | |
4679 | msr, MSR_TYPE_R); | |
4680 | __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic, | |
4681 | msr, MSR_TYPE_R); | |
4682 | } | |
4683 | ||
4684 | static void vmx_disable_intercept_msr_read_x2apic(u32 msr) | |
4685 | { | |
4686 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic, | |
4687 | msr, MSR_TYPE_R); | |
4688 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic, | |
4689 | msr, MSR_TYPE_R); | |
4690 | } | |
4691 | ||
4692 | static void vmx_disable_intercept_msr_write_x2apic(u32 msr) | |
4693 | { | |
4694 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic, | |
4695 | msr, MSR_TYPE_W); | |
4696 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic, | |
4697 | msr, MSR_TYPE_W); | |
5897297b AK |
4698 | } |
4699 | ||
d62caabb | 4700 | static bool vmx_get_enable_apicv(void) |
d50ab6c1 | 4701 | { |
d62caabb | 4702 | return enable_apicv; |
d50ab6c1 PB |
4703 | } |
4704 | ||
705699a1 WV |
4705 | static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu) |
4706 | { | |
4707 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4708 | int max_irr; | |
4709 | void *vapic_page; | |
4710 | u16 status; | |
4711 | ||
4712 | if (vmx->nested.pi_desc && | |
4713 | vmx->nested.pi_pending) { | |
4714 | vmx->nested.pi_pending = false; | |
4715 | if (!pi_test_and_clear_on(vmx->nested.pi_desc)) | |
4716 | return 0; | |
4717 | ||
4718 | max_irr = find_last_bit( | |
4719 | (unsigned long *)vmx->nested.pi_desc->pir, 256); | |
4720 | ||
4721 | if (max_irr == 256) | |
4722 | return 0; | |
4723 | ||
4724 | vapic_page = kmap(vmx->nested.virtual_apic_page); | |
4725 | if (!vapic_page) { | |
4726 | WARN_ON(1); | |
4727 | return -ENOMEM; | |
4728 | } | |
4729 | __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page); | |
4730 | kunmap(vmx->nested.virtual_apic_page); | |
4731 | ||
4732 | status = vmcs_read16(GUEST_INTR_STATUS); | |
4733 | if ((u8)max_irr > ((u8)status & 0xff)) { | |
4734 | status &= ~0xff; | |
4735 | status |= (u8)max_irr; | |
4736 | vmcs_write16(GUEST_INTR_STATUS, status); | |
4737 | } | |
4738 | } | |
4739 | return 0; | |
4740 | } | |
4741 | ||
21bc8dc5 RK |
4742 | static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu) |
4743 | { | |
4744 | #ifdef CONFIG_SMP | |
4745 | if (vcpu->mode == IN_GUEST_MODE) { | |
28b835d6 FW |
4746 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4747 | ||
4748 | /* | |
4749 | * Currently, we don't support urgent interrupt, | |
4750 | * all interrupts are recognized as non-urgent | |
4751 | * interrupt, so we cannot post interrupts when | |
4752 | * 'SN' is set. | |
4753 | * | |
4754 | * If the vcpu is in guest mode, it means it is | |
4755 | * running instead of being scheduled out and | |
4756 | * waiting in the run queue, and that's the only | |
4757 | * case when 'SN' is set currently, warning if | |
4758 | * 'SN' is set. | |
4759 | */ | |
4760 | WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc)); | |
4761 | ||
21bc8dc5 RK |
4762 | apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), |
4763 | POSTED_INTR_VECTOR); | |
4764 | return true; | |
4765 | } | |
4766 | #endif | |
4767 | return false; | |
4768 | } | |
4769 | ||
705699a1 WV |
4770 | static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, |
4771 | int vector) | |
4772 | { | |
4773 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4774 | ||
4775 | if (is_guest_mode(vcpu) && | |
4776 | vector == vmx->nested.posted_intr_nv) { | |
4777 | /* the PIR and ON have been set by L1. */ | |
21bc8dc5 | 4778 | kvm_vcpu_trigger_posted_interrupt(vcpu); |
705699a1 WV |
4779 | /* |
4780 | * If a posted intr is not recognized by hardware, | |
4781 | * we will accomplish it in the next vmentry. | |
4782 | */ | |
4783 | vmx->nested.pi_pending = true; | |
4784 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
4785 | return 0; | |
4786 | } | |
4787 | return -1; | |
4788 | } | |
a20ed54d YZ |
4789 | /* |
4790 | * Send interrupt to vcpu via posted interrupt way. | |
4791 | * 1. If target vcpu is running(non-root mode), send posted interrupt | |
4792 | * notification to vcpu and hardware will sync PIR to vIRR atomically. | |
4793 | * 2. If target vcpu isn't running(root mode), kick it to pick up the | |
4794 | * interrupt from PIR in next vmentry. | |
4795 | */ | |
4796 | static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) | |
4797 | { | |
4798 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4799 | int r; | |
4800 | ||
705699a1 WV |
4801 | r = vmx_deliver_nested_posted_interrupt(vcpu, vector); |
4802 | if (!r) | |
4803 | return; | |
4804 | ||
a20ed54d YZ |
4805 | if (pi_test_and_set_pir(vector, &vmx->pi_desc)) |
4806 | return; | |
4807 | ||
4808 | r = pi_test_and_set_on(&vmx->pi_desc); | |
4809 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
21bc8dc5 | 4810 | if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu)) |
a20ed54d YZ |
4811 | kvm_vcpu_kick(vcpu); |
4812 | } | |
4813 | ||
4814 | static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) | |
4815 | { | |
4816 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4817 | ||
4818 | if (!pi_test_and_clear_on(&vmx->pi_desc)) | |
4819 | return; | |
4820 | ||
4821 | kvm_apic_update_irr(vcpu, vmx->pi_desc.pir); | |
4822 | } | |
4823 | ||
a3a8ff8e NHE |
4824 | /* |
4825 | * Set up the vmcs's constant host-state fields, i.e., host-state fields that | |
4826 | * will not change in the lifetime of the guest. | |
4827 | * Note that host-state that does change is set elsewhere. E.g., host-state | |
4828 | * that is set differently for each CPU is set in vmx_vcpu_load(), not here. | |
4829 | */ | |
a547c6db | 4830 | static void vmx_set_constant_host_state(struct vcpu_vmx *vmx) |
a3a8ff8e NHE |
4831 | { |
4832 | u32 low32, high32; | |
4833 | unsigned long tmpl; | |
4834 | struct desc_ptr dt; | |
d974baa3 | 4835 | unsigned long cr4; |
a3a8ff8e | 4836 | |
b1a74bf8 | 4837 | vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */ |
a3a8ff8e NHE |
4838 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ |
4839 | ||
d974baa3 | 4840 | /* Save the most likely value for this task's CR4 in the VMCS. */ |
1e02ce4c | 4841 | cr4 = cr4_read_shadow(); |
d974baa3 AL |
4842 | vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ |
4843 | vmx->host_state.vmcs_host_cr4 = cr4; | |
4844 | ||
a3a8ff8e | 4845 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ |
b2da15ac AK |
4846 | #ifdef CONFIG_X86_64 |
4847 | /* | |
4848 | * Load null selectors, so we can avoid reloading them in | |
4849 | * __vmx_load_host_state(), in case userspace uses the null selectors | |
4850 | * too (the expected case). | |
4851 | */ | |
4852 | vmcs_write16(HOST_DS_SELECTOR, 0); | |
4853 | vmcs_write16(HOST_ES_SELECTOR, 0); | |
4854 | #else | |
a3a8ff8e NHE |
4855 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
4856 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
b2da15ac | 4857 | #endif |
a3a8ff8e NHE |
4858 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
4859 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
4860 | ||
4861 | native_store_idt(&dt); | |
4862 | vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */ | |
a547c6db | 4863 | vmx->host_idt_base = dt.address; |
a3a8ff8e | 4864 | |
83287ea4 | 4865 | vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */ |
a3a8ff8e NHE |
4866 | |
4867 | rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); | |
4868 | vmcs_write32(HOST_IA32_SYSENTER_CS, low32); | |
4869 | rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); | |
4870 | vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ | |
4871 | ||
4872 | if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { | |
4873 | rdmsr(MSR_IA32_CR_PAT, low32, high32); | |
4874 | vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); | |
4875 | } | |
4876 | } | |
4877 | ||
bf8179a0 NHE |
4878 | static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) |
4879 | { | |
4880 | vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; | |
4881 | if (enable_ept) | |
4882 | vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; | |
fe3ef05c NHE |
4883 | if (is_guest_mode(&vmx->vcpu)) |
4884 | vmx->vcpu.arch.cr4_guest_owned_bits &= | |
4885 | ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; | |
bf8179a0 NHE |
4886 | vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); |
4887 | } | |
4888 | ||
01e439be YZ |
4889 | static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) |
4890 | { | |
4891 | u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; | |
4892 | ||
d62caabb | 4893 | if (!kvm_vcpu_apicv_active(&vmx->vcpu)) |
01e439be | 4894 | pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; |
64672c95 YJ |
4895 | /* Enable the preemption timer dynamically */ |
4896 | pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
4897 | return pin_based_exec_ctrl; |
4898 | } | |
4899 | ||
d62caabb AS |
4900 | static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) |
4901 | { | |
4902 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4903 | ||
4904 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); | |
3ce424e4 RK |
4905 | if (cpu_has_secondary_exec_ctrls()) { |
4906 | if (kvm_vcpu_apicv_active(vcpu)) | |
4907 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
4908 | SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
4909 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
4910 | else | |
4911 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, | |
4912 | SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
4913 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
4914 | } | |
4915 | ||
4916 | if (cpu_has_vmx_msr_bitmap()) | |
4917 | vmx_set_msr_bitmap(vcpu); | |
d62caabb AS |
4918 | } |
4919 | ||
bf8179a0 NHE |
4920 | static u32 vmx_exec_control(struct vcpu_vmx *vmx) |
4921 | { | |
4922 | u32 exec_control = vmcs_config.cpu_based_exec_ctrl; | |
d16c293e PB |
4923 | |
4924 | if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) | |
4925 | exec_control &= ~CPU_BASED_MOV_DR_EXITING; | |
4926 | ||
35754c98 | 4927 | if (!cpu_need_tpr_shadow(&vmx->vcpu)) { |
bf8179a0 NHE |
4928 | exec_control &= ~CPU_BASED_TPR_SHADOW; |
4929 | #ifdef CONFIG_X86_64 | |
4930 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
4931 | CPU_BASED_CR8_LOAD_EXITING; | |
4932 | #endif | |
4933 | } | |
4934 | if (!enable_ept) | |
4935 | exec_control |= CPU_BASED_CR3_STORE_EXITING | | |
4936 | CPU_BASED_CR3_LOAD_EXITING | | |
4937 | CPU_BASED_INVLPG_EXITING; | |
4938 | return exec_control; | |
4939 | } | |
4940 | ||
4941 | static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx) | |
4942 | { | |
4943 | u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; | |
35754c98 | 4944 | if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu)) |
bf8179a0 NHE |
4945 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; |
4946 | if (vmx->vpid == 0) | |
4947 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
4948 | if (!enable_ept) { | |
4949 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; | |
4950 | enable_unrestricted_guest = 0; | |
ad756a16 MJ |
4951 | /* Enable INVPCID for non-ept guests may cause performance regression. */ |
4952 | exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; | |
bf8179a0 NHE |
4953 | } |
4954 | if (!enable_unrestricted_guest) | |
4955 | exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
4956 | if (!ple_gap) | |
4957 | exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
d62caabb | 4958 | if (!kvm_vcpu_apicv_active(&vmx->vcpu)) |
c7c9c56c YZ |
4959 | exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | |
4960 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
8d14695f | 4961 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; |
abc4fc58 AG |
4962 | /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD |
4963 | (handle_vmptrld). | |
4964 | We can NOT enable shadow_vmcs here because we don't have yet | |
4965 | a current VMCS12 | |
4966 | */ | |
4967 | exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; | |
a3eaa864 KH |
4968 | |
4969 | if (!enable_pml) | |
4970 | exec_control &= ~SECONDARY_EXEC_ENABLE_PML; | |
843e4330 | 4971 | |
8b3e34e4 XG |
4972 | /* Currently, we allow L1 guest to directly run pcommit instruction. */ |
4973 | exec_control &= ~SECONDARY_EXEC_PCOMMIT; | |
4974 | ||
bf8179a0 NHE |
4975 | return exec_control; |
4976 | } | |
4977 | ||
ce88decf XG |
4978 | static void ept_set_mmio_spte_mask(void) |
4979 | { | |
4980 | /* | |
4981 | * EPT Misconfigurations can be generated if the value of bits 2:0 | |
4982 | * of an EPT paging-structure entry is 110b (write/execute). | |
885032b9 | 4983 | * Also, magic bits (0x3ull << 62) is set to quickly identify mmio |
ce88decf XG |
4984 | * spte. |
4985 | */ | |
885032b9 | 4986 | kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull); |
ce88decf XG |
4987 | } |
4988 | ||
f53cd63c | 4989 | #define VMX_XSS_EXIT_BITMAP 0 |
6aa8b732 AK |
4990 | /* |
4991 | * Sets up the vmcs for emulated real mode. | |
4992 | */ | |
8b9cf98c | 4993 | static int vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 | 4994 | { |
2e4ce7f5 | 4995 | #ifdef CONFIG_X86_64 |
6aa8b732 | 4996 | unsigned long a; |
2e4ce7f5 | 4997 | #endif |
6aa8b732 | 4998 | int i; |
6aa8b732 | 4999 | |
6aa8b732 | 5000 | /* I/O */ |
3e7c73e9 AK |
5001 | vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a)); |
5002 | vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b)); | |
6aa8b732 | 5003 | |
4607c2d7 AG |
5004 | if (enable_shadow_vmcs) { |
5005 | vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap)); | |
5006 | vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap)); | |
5007 | } | |
25c5f225 | 5008 | if (cpu_has_vmx_msr_bitmap()) |
5897297b | 5009 | vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy)); |
25c5f225 | 5010 | |
6aa8b732 AK |
5011 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
5012 | ||
6aa8b732 | 5013 | /* Control */ |
01e439be | 5014 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); |
64672c95 | 5015 | vmx->hv_deadline_tsc = -1; |
6e5d865c | 5016 | |
bf8179a0 | 5017 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx)); |
6aa8b732 | 5018 | |
8b3e34e4 | 5019 | if (cpu_has_secondary_exec_ctrls()) |
bf8179a0 NHE |
5020 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, |
5021 | vmx_secondary_exec_control(vmx)); | |
f78e0e2e | 5022 | |
d62caabb | 5023 | if (kvm_vcpu_apicv_active(&vmx->vcpu)) { |
c7c9c56c YZ |
5024 | vmcs_write64(EOI_EXIT_BITMAP0, 0); |
5025 | vmcs_write64(EOI_EXIT_BITMAP1, 0); | |
5026 | vmcs_write64(EOI_EXIT_BITMAP2, 0); | |
5027 | vmcs_write64(EOI_EXIT_BITMAP3, 0); | |
5028 | ||
5029 | vmcs_write16(GUEST_INTR_STATUS, 0); | |
01e439be | 5030 | |
0bcf261c | 5031 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); |
01e439be | 5032 | vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); |
c7c9c56c YZ |
5033 | } |
5034 | ||
4b8d54f9 ZE |
5035 | if (ple_gap) { |
5036 | vmcs_write32(PLE_GAP, ple_gap); | |
a7653ecd RK |
5037 | vmx->ple_window = ple_window; |
5038 | vmx->ple_window_dirty = true; | |
4b8d54f9 ZE |
5039 | } |
5040 | ||
c3707958 XG |
5041 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); |
5042 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); | |
6aa8b732 AK |
5043 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
5044 | ||
9581d442 AK |
5045 | vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ |
5046 | vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ | |
a547c6db | 5047 | vmx_set_constant_host_state(vmx); |
05b3e0c2 | 5048 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
5049 | rdmsrl(MSR_FS_BASE, a); |
5050 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
5051 | rdmsrl(MSR_GS_BASE, a); | |
5052 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
5053 | #else | |
5054 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
5055 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
5056 | #endif | |
5057 | ||
2cc51560 ED |
5058 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
5059 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
61d2ef2c | 5060 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host)); |
2cc51560 | 5061 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); |
61d2ef2c | 5062 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); |
6aa8b732 | 5063 | |
74545705 RK |
5064 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) |
5065 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); | |
468d472f | 5066 | |
03916db9 | 5067 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { |
6aa8b732 AK |
5068 | u32 index = vmx_msr_index[i]; |
5069 | u32 data_low, data_high; | |
a2fa3e9f | 5070 | int j = vmx->nmsrs; |
6aa8b732 AK |
5071 | |
5072 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
5073 | continue; | |
432bd6cb AK |
5074 | if (wrmsr_safe(index, data_low, data_high) < 0) |
5075 | continue; | |
26bb0981 AK |
5076 | vmx->guest_msrs[j].index = i; |
5077 | vmx->guest_msrs[j].data = 0; | |
d5696725 | 5078 | vmx->guest_msrs[j].mask = -1ull; |
a2fa3e9f | 5079 | ++vmx->nmsrs; |
6aa8b732 | 5080 | } |
6aa8b732 | 5081 | |
2961e876 GN |
5082 | |
5083 | vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl); | |
6aa8b732 AK |
5084 | |
5085 | /* 22.2.1, 20.8.1 */ | |
2961e876 | 5086 | vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl); |
1c3d14fe | 5087 | |
e00c8cf2 | 5088 | vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL); |
bf8179a0 | 5089 | set_cr4_guest_host_mask(vmx); |
e00c8cf2 | 5090 | |
f53cd63c WL |
5091 | if (vmx_xsaves_supported()) |
5092 | vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); | |
5093 | ||
e00c8cf2 AK |
5094 | return 0; |
5095 | } | |
5096 | ||
d28bc9dd | 5097 | static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e00c8cf2 AK |
5098 | { |
5099 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
58cb628d | 5100 | struct msr_data apic_base_msr; |
d28bc9dd | 5101 | u64 cr0; |
e00c8cf2 | 5102 | |
7ffd92c5 | 5103 | vmx->rmode.vm86_active = 0; |
e00c8cf2 | 5104 | |
3b86cd99 JK |
5105 | vmx->soft_vnmi_blocked = 0; |
5106 | ||
ad312c7c | 5107 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
d28bc9dd NA |
5108 | kvm_set_cr8(vcpu, 0); |
5109 | ||
5110 | if (!init_event) { | |
5111 | apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | | |
5112 | MSR_IA32_APICBASE_ENABLE; | |
5113 | if (kvm_vcpu_is_reset_bsp(vcpu)) | |
5114 | apic_base_msr.data |= MSR_IA32_APICBASE_BSP; | |
5115 | apic_base_msr.host_initiated = true; | |
5116 | kvm_set_apic_base(vcpu, &apic_base_msr); | |
5117 | } | |
e00c8cf2 | 5118 | |
2fb92db1 AK |
5119 | vmx_segment_cache_clear(vmx); |
5120 | ||
5706be0d | 5121 | seg_setup(VCPU_SREG_CS); |
66450a21 | 5122 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); |
f3531054 | 5123 | vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); |
e00c8cf2 AK |
5124 | |
5125 | seg_setup(VCPU_SREG_DS); | |
5126 | seg_setup(VCPU_SREG_ES); | |
5127 | seg_setup(VCPU_SREG_FS); | |
5128 | seg_setup(VCPU_SREG_GS); | |
5129 | seg_setup(VCPU_SREG_SS); | |
5130 | ||
5131 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
5132 | vmcs_writel(GUEST_TR_BASE, 0); | |
5133 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
5134 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
5135 | ||
5136 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
5137 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
5138 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
5139 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
5140 | ||
d28bc9dd NA |
5141 | if (!init_event) { |
5142 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
5143 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
5144 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
5145 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
5146 | } | |
e00c8cf2 AK |
5147 | |
5148 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
66450a21 | 5149 | kvm_rip_write(vcpu, 0xfff0); |
e00c8cf2 | 5150 | |
e00c8cf2 AK |
5151 | vmcs_writel(GUEST_GDTR_BASE, 0); |
5152 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
5153 | ||
5154 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
5155 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
5156 | ||
443381a8 | 5157 | vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); |
e00c8cf2 | 5158 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); |
f3531054 | 5159 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); |
e00c8cf2 | 5160 | |
e00c8cf2 AK |
5161 | setup_msrs(vmx); |
5162 | ||
6aa8b732 AK |
5163 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
5164 | ||
d28bc9dd | 5165 | if (cpu_has_vmx_tpr_shadow() && !init_event) { |
f78e0e2e | 5166 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); |
35754c98 | 5167 | if (cpu_need_tpr_shadow(vcpu)) |
f78e0e2e | 5168 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, |
d28bc9dd | 5169 | __pa(vcpu->arch.apic->regs)); |
f78e0e2e SY |
5170 | vmcs_write32(TPR_THRESHOLD, 0); |
5171 | } | |
5172 | ||
a73896cb | 5173 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
6aa8b732 | 5174 | |
d62caabb | 5175 | if (kvm_vcpu_apicv_active(vcpu)) |
01e439be YZ |
5176 | memset(&vmx->pi_desc, 0, sizeof(struct pi_desc)); |
5177 | ||
2384d2b3 SY |
5178 | if (vmx->vpid != 0) |
5179 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
5180 | ||
d28bc9dd | 5181 | cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; |
d28bc9dd | 5182 | vmx->vcpu.arch.cr0 = cr0; |
f2463247 | 5183 | vmx_set_cr0(vcpu, cr0); /* enter rmode */ |
d28bc9dd | 5184 | vmx_set_cr4(vcpu, 0); |
5690891b | 5185 | vmx_set_efer(vcpu, 0); |
d28bc9dd NA |
5186 | vmx_fpu_activate(vcpu); |
5187 | update_exception_bitmap(vcpu); | |
6aa8b732 | 5188 | |
dd5f5341 | 5189 | vpid_sync_context(vmx->vpid); |
6aa8b732 AK |
5190 | } |
5191 | ||
b6f1250e NHE |
5192 | /* |
5193 | * In nested virtualization, check if L1 asked to exit on external interrupts. | |
5194 | * For most existing hypervisors, this will always return true. | |
5195 | */ | |
5196 | static bool nested_exit_on_intr(struct kvm_vcpu *vcpu) | |
5197 | { | |
5198 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
5199 | PIN_BASED_EXT_INTR_MASK; | |
5200 | } | |
5201 | ||
77b0f5d6 BD |
5202 | /* |
5203 | * In nested virtualization, check if L1 has set | |
5204 | * VM_EXIT_ACK_INTR_ON_EXIT | |
5205 | */ | |
5206 | static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu) | |
5207 | { | |
5208 | return get_vmcs12(vcpu)->vm_exit_controls & | |
5209 | VM_EXIT_ACK_INTR_ON_EXIT; | |
5210 | } | |
5211 | ||
ea8ceb83 JK |
5212 | static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu) |
5213 | { | |
5214 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
5215 | PIN_BASED_NMI_EXITING; | |
5216 | } | |
5217 | ||
c9a7953f | 5218 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
3b86cd99 JK |
5219 | { |
5220 | u32 cpu_based_vm_exec_control; | |
730dca42 | 5221 | |
3b86cd99 JK |
5222 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); |
5223 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; | |
5224 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
5225 | } | |
5226 | ||
c9a7953f | 5227 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
3b86cd99 JK |
5228 | { |
5229 | u32 cpu_based_vm_exec_control; | |
5230 | ||
c9a7953f JK |
5231 | if (!cpu_has_virtual_nmis() || |
5232 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { | |
5233 | enable_irq_window(vcpu); | |
5234 | return; | |
5235 | } | |
3b86cd99 JK |
5236 | |
5237 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
5238 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING; | |
5239 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
5240 | } | |
5241 | ||
66fd3f7f | 5242 | static void vmx_inject_irq(struct kvm_vcpu *vcpu) |
85f455f7 | 5243 | { |
9c8cba37 | 5244 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
66fd3f7f GN |
5245 | uint32_t intr; |
5246 | int irq = vcpu->arch.interrupt.nr; | |
9c8cba37 | 5247 | |
229456fc | 5248 | trace_kvm_inj_virq(irq); |
2714d1d3 | 5249 | |
fa89a817 | 5250 | ++vcpu->stat.irq_injections; |
7ffd92c5 | 5251 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
5252 | int inc_eip = 0; |
5253 | if (vcpu->arch.interrupt.soft) | |
5254 | inc_eip = vcpu->arch.event_exit_inst_len; | |
5255 | if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE) | |
a92601bb | 5256 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
85f455f7 ED |
5257 | return; |
5258 | } | |
66fd3f7f GN |
5259 | intr = irq | INTR_INFO_VALID_MASK; |
5260 | if (vcpu->arch.interrupt.soft) { | |
5261 | intr |= INTR_TYPE_SOFT_INTR; | |
5262 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
5263 | vmx->vcpu.arch.event_exit_inst_len); | |
5264 | } else | |
5265 | intr |= INTR_TYPE_EXT_INTR; | |
5266 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); | |
85f455f7 ED |
5267 | } |
5268 | ||
f08864b4 SY |
5269 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
5270 | { | |
66a5a347 JK |
5271 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
5272 | ||
0b6ac343 NHE |
5273 | if (is_guest_mode(vcpu)) |
5274 | return; | |
5275 | ||
3b86cd99 JK |
5276 | if (!cpu_has_virtual_nmis()) { |
5277 | /* | |
5278 | * Tracking the NMI-blocked state in software is built upon | |
5279 | * finding the next open IRQ window. This, in turn, depends on | |
5280 | * well-behaving guests: They have to keep IRQs disabled at | |
5281 | * least as long as the NMI handler runs. Otherwise we may | |
5282 | * cause NMI nesting, maybe breaking the guest. But as this is | |
5283 | * highly unlikely, we can live with the residual risk. | |
5284 | */ | |
5285 | vmx->soft_vnmi_blocked = 1; | |
5286 | vmx->vnmi_blocked_time = 0; | |
5287 | } | |
5288 | ||
487b391d | 5289 | ++vcpu->stat.nmi_injections; |
9d58b931 | 5290 | vmx->nmi_known_unmasked = false; |
7ffd92c5 | 5291 | if (vmx->rmode.vm86_active) { |
71f9833b | 5292 | if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE) |
a92601bb | 5293 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
66a5a347 JK |
5294 | return; |
5295 | } | |
f08864b4 SY |
5296 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
5297 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
f08864b4 SY |
5298 | } |
5299 | ||
3cfc3092 JK |
5300 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) |
5301 | { | |
5302 | if (!cpu_has_virtual_nmis()) | |
5303 | return to_vmx(vcpu)->soft_vnmi_blocked; | |
9d58b931 AK |
5304 | if (to_vmx(vcpu)->nmi_known_unmasked) |
5305 | return false; | |
c332c83a | 5306 | return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; |
3cfc3092 JK |
5307 | } |
5308 | ||
5309 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
5310 | { | |
5311 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5312 | ||
5313 | if (!cpu_has_virtual_nmis()) { | |
5314 | if (vmx->soft_vnmi_blocked != masked) { | |
5315 | vmx->soft_vnmi_blocked = masked; | |
5316 | vmx->vnmi_blocked_time = 0; | |
5317 | } | |
5318 | } else { | |
9d58b931 | 5319 | vmx->nmi_known_unmasked = !masked; |
3cfc3092 JK |
5320 | if (masked) |
5321 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
5322 | GUEST_INTR_STATE_NMI); | |
5323 | else | |
5324 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
5325 | GUEST_INTR_STATE_NMI); | |
5326 | } | |
5327 | } | |
5328 | ||
2505dc9f JK |
5329 | static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) |
5330 | { | |
b6b8a145 JK |
5331 | if (to_vmx(vcpu)->nested.nested_run_pending) |
5332 | return 0; | |
ea8ceb83 | 5333 | |
2505dc9f JK |
5334 | if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked) |
5335 | return 0; | |
5336 | ||
5337 | return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & | |
5338 | (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI | |
5339 | | GUEST_INTR_STATE_NMI)); | |
5340 | } | |
5341 | ||
78646121 GN |
5342 | static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) |
5343 | { | |
b6b8a145 JK |
5344 | return (!to_vmx(vcpu)->nested.nested_run_pending && |
5345 | vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
c4282df9 GN |
5346 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
5347 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); | |
78646121 GN |
5348 | } |
5349 | ||
cbc94022 IE |
5350 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
5351 | { | |
5352 | int ret; | |
cbc94022 | 5353 | |
1d8007bd PB |
5354 | ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, |
5355 | PAGE_SIZE * 3); | |
cbc94022 IE |
5356 | if (ret) |
5357 | return ret; | |
bfc6d222 | 5358 | kvm->arch.tss_addr = addr; |
1f755a82 | 5359 | return init_rmode_tss(kvm); |
cbc94022 IE |
5360 | } |
5361 | ||
0ca1b4f4 | 5362 | static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) |
6aa8b732 | 5363 | { |
77ab6db0 | 5364 | switch (vec) { |
77ab6db0 | 5365 | case BP_VECTOR: |
c573cd22 JK |
5366 | /* |
5367 | * Update instruction length as we may reinject the exception | |
5368 | * from user space while in guest debugging mode. | |
5369 | */ | |
5370 | to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = | |
5371 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
d0bfb940 | 5372 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
0ca1b4f4 GN |
5373 | return false; |
5374 | /* fall through */ | |
5375 | case DB_VECTOR: | |
5376 | if (vcpu->guest_debug & | |
5377 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
5378 | return false; | |
d0bfb940 JK |
5379 | /* fall through */ |
5380 | case DE_VECTOR: | |
77ab6db0 JK |
5381 | case OF_VECTOR: |
5382 | case BR_VECTOR: | |
5383 | case UD_VECTOR: | |
5384 | case DF_VECTOR: | |
5385 | case SS_VECTOR: | |
5386 | case GP_VECTOR: | |
5387 | case MF_VECTOR: | |
0ca1b4f4 GN |
5388 | return true; |
5389 | break; | |
77ab6db0 | 5390 | } |
0ca1b4f4 GN |
5391 | return false; |
5392 | } | |
5393 | ||
5394 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
5395 | int vec, u32 err_code) | |
5396 | { | |
5397 | /* | |
5398 | * Instruction with address size override prefix opcode 0x67 | |
5399 | * Cause the #SS fault with 0 error code in VM86 mode. | |
5400 | */ | |
5401 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { | |
5402 | if (emulate_instruction(vcpu, 0) == EMULATE_DONE) { | |
5403 | if (vcpu->arch.halt_request) { | |
5404 | vcpu->arch.halt_request = 0; | |
5cb56059 | 5405 | return kvm_vcpu_halt(vcpu); |
0ca1b4f4 GN |
5406 | } |
5407 | return 1; | |
5408 | } | |
5409 | return 0; | |
5410 | } | |
5411 | ||
5412 | /* | |
5413 | * Forward all other exceptions that are valid in real mode. | |
5414 | * FIXME: Breaks guest debugging in real mode, needs to be fixed with | |
5415 | * the required debugging infrastructure rework. | |
5416 | */ | |
5417 | kvm_queue_exception(vcpu, vec); | |
5418 | return 1; | |
6aa8b732 AK |
5419 | } |
5420 | ||
a0861c02 AK |
5421 | /* |
5422 | * Trigger machine check on the host. We assume all the MSRs are already set up | |
5423 | * by the CPU and that we still run on the same CPU as the MCE occurred on. | |
5424 | * We pass a fake environment to the machine check handler because we want | |
5425 | * the guest to be always treated like user space, no matter what context | |
5426 | * it used internally. | |
5427 | */ | |
5428 | static void kvm_machine_check(void) | |
5429 | { | |
5430 | #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) | |
5431 | struct pt_regs regs = { | |
5432 | .cs = 3, /* Fake ring 3 no matter what the guest ran on */ | |
5433 | .flags = X86_EFLAGS_IF, | |
5434 | }; | |
5435 | ||
5436 | do_machine_check(®s, 0); | |
5437 | #endif | |
5438 | } | |
5439 | ||
851ba692 | 5440 | static int handle_machine_check(struct kvm_vcpu *vcpu) |
a0861c02 AK |
5441 | { |
5442 | /* already handled by vcpu_run */ | |
5443 | return 1; | |
5444 | } | |
5445 | ||
851ba692 | 5446 | static int handle_exception(struct kvm_vcpu *vcpu) |
6aa8b732 | 5447 | { |
1155f76a | 5448 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
851ba692 | 5449 | struct kvm_run *kvm_run = vcpu->run; |
d0bfb940 | 5450 | u32 intr_info, ex_no, error_code; |
42dbaa5a | 5451 | unsigned long cr2, rip, dr6; |
6aa8b732 AK |
5452 | u32 vect_info; |
5453 | enum emulation_result er; | |
5454 | ||
1155f76a | 5455 | vect_info = vmx->idt_vectoring_info; |
88786475 | 5456 | intr_info = vmx->exit_intr_info; |
6aa8b732 | 5457 | |
a0861c02 | 5458 | if (is_machine_check(intr_info)) |
851ba692 | 5459 | return handle_machine_check(vcpu); |
a0861c02 | 5460 | |
e4a41889 | 5461 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR) |
1b6269db | 5462 | return 1; /* already handled by vmx_vcpu_run() */ |
2ab455cc AL |
5463 | |
5464 | if (is_no_device(intr_info)) { | |
5fd86fcf | 5465 | vmx_fpu_activate(vcpu); |
2ab455cc AL |
5466 | return 1; |
5467 | } | |
5468 | ||
7aa81cc0 | 5469 | if (is_invalid_opcode(intr_info)) { |
ae1f5767 JK |
5470 | if (is_guest_mode(vcpu)) { |
5471 | kvm_queue_exception(vcpu, UD_VECTOR); | |
5472 | return 1; | |
5473 | } | |
51d8b661 | 5474 | er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 5475 | if (er != EMULATE_DONE) |
7ee5d940 | 5476 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
5477 | return 1; |
5478 | } | |
5479 | ||
6aa8b732 | 5480 | error_code = 0; |
2e11384c | 5481 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 | 5482 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
bf4ca23e XG |
5483 | |
5484 | /* | |
5485 | * The #PF with PFEC.RSVD = 1 indicates the guest is accessing | |
5486 | * MMIO, it is better to report an internal error. | |
5487 | * See the comments in vmx_handle_exit. | |
5488 | */ | |
5489 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
5490 | !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { | |
5491 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
5492 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; | |
80f0e95d | 5493 | vcpu->run->internal.ndata = 3; |
bf4ca23e XG |
5494 | vcpu->run->internal.data[0] = vect_info; |
5495 | vcpu->run->internal.data[1] = intr_info; | |
80f0e95d | 5496 | vcpu->run->internal.data[2] = error_code; |
bf4ca23e XG |
5497 | return 0; |
5498 | } | |
5499 | ||
6aa8b732 | 5500 | if (is_page_fault(intr_info)) { |
1439442c | 5501 | /* EPT won't cause page fault directly */ |
cf3ace79 | 5502 | BUG_ON(enable_ept); |
6aa8b732 | 5503 | cr2 = vmcs_readl(EXIT_QUALIFICATION); |
229456fc MT |
5504 | trace_kvm_page_fault(cr2, error_code); |
5505 | ||
3298b75c | 5506 | if (kvm_event_needs_reinjection(vcpu)) |
577bdc49 | 5507 | kvm_mmu_unprotect_page_virt(vcpu, cr2); |
dc25e89e | 5508 | return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0); |
6aa8b732 AK |
5509 | } |
5510 | ||
d0bfb940 | 5511 | ex_no = intr_info & INTR_INFO_VECTOR_MASK; |
0ca1b4f4 GN |
5512 | |
5513 | if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) | |
5514 | return handle_rmode_exception(vcpu, ex_no, error_code); | |
5515 | ||
42dbaa5a | 5516 | switch (ex_no) { |
54a20552 EN |
5517 | case AC_VECTOR: |
5518 | kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); | |
5519 | return 1; | |
42dbaa5a JK |
5520 | case DB_VECTOR: |
5521 | dr6 = vmcs_readl(EXIT_QUALIFICATION); | |
5522 | if (!(vcpu->guest_debug & | |
5523 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { | |
8246bf52 | 5524 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 5525 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
fd2a445a HD |
5526 | if (!(dr6 & ~DR6_RESERVED)) /* icebp */ |
5527 | skip_emulated_instruction(vcpu); | |
5528 | ||
42dbaa5a JK |
5529 | kvm_queue_exception(vcpu, DB_VECTOR); |
5530 | return 1; | |
5531 | } | |
5532 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; | |
5533 | kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); | |
5534 | /* fall through */ | |
5535 | case BP_VECTOR: | |
c573cd22 JK |
5536 | /* |
5537 | * Update instruction length as we may reinject #BP from | |
5538 | * user space while in guest debugging mode. Reading it for | |
5539 | * #DB as well causes no harm, it is not used in that case. | |
5540 | */ | |
5541 | vmx->vcpu.arch.event_exit_inst_len = | |
5542 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
6aa8b732 | 5543 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
0a434bb2 | 5544 | rip = kvm_rip_read(vcpu); |
d0bfb940 JK |
5545 | kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; |
5546 | kvm_run->debug.arch.exception = ex_no; | |
42dbaa5a JK |
5547 | break; |
5548 | default: | |
d0bfb940 JK |
5549 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; |
5550 | kvm_run->ex.exception = ex_no; | |
5551 | kvm_run->ex.error_code = error_code; | |
42dbaa5a | 5552 | break; |
6aa8b732 | 5553 | } |
6aa8b732 AK |
5554 | return 0; |
5555 | } | |
5556 | ||
851ba692 | 5557 | static int handle_external_interrupt(struct kvm_vcpu *vcpu) |
6aa8b732 | 5558 | { |
1165f5fe | 5559 | ++vcpu->stat.irq_exits; |
6aa8b732 AK |
5560 | return 1; |
5561 | } | |
5562 | ||
851ba692 | 5563 | static int handle_triple_fault(struct kvm_vcpu *vcpu) |
988ad74f | 5564 | { |
851ba692 | 5565 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
988ad74f AK |
5566 | return 0; |
5567 | } | |
6aa8b732 | 5568 | |
851ba692 | 5569 | static int handle_io(struct kvm_vcpu *vcpu) |
6aa8b732 | 5570 | { |
bfdaab09 | 5571 | unsigned long exit_qualification; |
34c33d16 | 5572 | int size, in, string; |
039576c0 | 5573 | unsigned port; |
6aa8b732 | 5574 | |
bfdaab09 | 5575 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 5576 | string = (exit_qualification & 16) != 0; |
cf8f70bf | 5577 | in = (exit_qualification & 8) != 0; |
e70669ab | 5578 | |
cf8f70bf | 5579 | ++vcpu->stat.io_exits; |
e70669ab | 5580 | |
cf8f70bf | 5581 | if (string || in) |
51d8b661 | 5582 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
e70669ab | 5583 | |
cf8f70bf GN |
5584 | port = exit_qualification >> 16; |
5585 | size = (exit_qualification & 7) + 1; | |
e93f36bc | 5586 | skip_emulated_instruction(vcpu); |
cf8f70bf GN |
5587 | |
5588 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
5589 | } |
5590 | ||
102d8325 IM |
5591 | static void |
5592 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
5593 | { | |
5594 | /* | |
5595 | * Patch in the VMCALL instruction: | |
5596 | */ | |
5597 | hypercall[0] = 0x0f; | |
5598 | hypercall[1] = 0x01; | |
5599 | hypercall[2] = 0xc1; | |
102d8325 IM |
5600 | } |
5601 | ||
b9c237bb | 5602 | static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) |
92fbc7b1 JK |
5603 | { |
5604 | unsigned long always_on = VMXON_CR0_ALWAYSON; | |
b9c237bb | 5605 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
92fbc7b1 | 5606 | |
b9c237bb | 5607 | if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high & |
92fbc7b1 JK |
5608 | SECONDARY_EXEC_UNRESTRICTED_GUEST && |
5609 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST)) | |
5610 | always_on &= ~(X86_CR0_PE | X86_CR0_PG); | |
5611 | return (val & always_on) == always_on; | |
5612 | } | |
5613 | ||
0fa06071 | 5614 | /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ |
eeadf9e7 NHE |
5615 | static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) |
5616 | { | |
eeadf9e7 | 5617 | if (is_guest_mode(vcpu)) { |
1a0d74e6 JK |
5618 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
5619 | unsigned long orig_val = val; | |
5620 | ||
eeadf9e7 NHE |
5621 | /* |
5622 | * We get here when L2 changed cr0 in a way that did not change | |
5623 | * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), | |
1a0d74e6 JK |
5624 | * but did change L0 shadowed bits. So we first calculate the |
5625 | * effective cr0 value that L1 would like to write into the | |
5626 | * hardware. It consists of the L2-owned bits from the new | |
5627 | * value combined with the L1-owned bits from L1's guest_cr0. | |
eeadf9e7 | 5628 | */ |
1a0d74e6 JK |
5629 | val = (val & ~vmcs12->cr0_guest_host_mask) | |
5630 | (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); | |
5631 | ||
b9c237bb | 5632 | if (!nested_cr0_valid(vcpu, val)) |
eeadf9e7 | 5633 | return 1; |
1a0d74e6 JK |
5634 | |
5635 | if (kvm_set_cr0(vcpu, val)) | |
5636 | return 1; | |
5637 | vmcs_writel(CR0_READ_SHADOW, orig_val); | |
eeadf9e7 | 5638 | return 0; |
1a0d74e6 JK |
5639 | } else { |
5640 | if (to_vmx(vcpu)->nested.vmxon && | |
5641 | ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)) | |
5642 | return 1; | |
eeadf9e7 | 5643 | return kvm_set_cr0(vcpu, val); |
1a0d74e6 | 5644 | } |
eeadf9e7 NHE |
5645 | } |
5646 | ||
5647 | static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) | |
5648 | { | |
5649 | if (is_guest_mode(vcpu)) { | |
1a0d74e6 JK |
5650 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
5651 | unsigned long orig_val = val; | |
5652 | ||
5653 | /* analogously to handle_set_cr0 */ | |
5654 | val = (val & ~vmcs12->cr4_guest_host_mask) | | |
5655 | (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); | |
5656 | if (kvm_set_cr4(vcpu, val)) | |
eeadf9e7 | 5657 | return 1; |
1a0d74e6 | 5658 | vmcs_writel(CR4_READ_SHADOW, orig_val); |
eeadf9e7 NHE |
5659 | return 0; |
5660 | } else | |
5661 | return kvm_set_cr4(vcpu, val); | |
5662 | } | |
5663 | ||
6a6256f9 | 5664 | /* called to set cr0 as appropriate for clts instruction exit. */ |
eeadf9e7 NHE |
5665 | static void handle_clts(struct kvm_vcpu *vcpu) |
5666 | { | |
5667 | if (is_guest_mode(vcpu)) { | |
5668 | /* | |
5669 | * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS | |
5670 | * but we did (!fpu_active). We need to keep GUEST_CR0.TS on, | |
5671 | * just pretend it's off (also in arch.cr0 for fpu_activate). | |
5672 | */ | |
5673 | vmcs_writel(CR0_READ_SHADOW, | |
5674 | vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS); | |
5675 | vcpu->arch.cr0 &= ~X86_CR0_TS; | |
5676 | } else | |
5677 | vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); | |
5678 | } | |
5679 | ||
851ba692 | 5680 | static int handle_cr(struct kvm_vcpu *vcpu) |
6aa8b732 | 5681 | { |
229456fc | 5682 | unsigned long exit_qualification, val; |
6aa8b732 AK |
5683 | int cr; |
5684 | int reg; | |
49a9b07e | 5685 | int err; |
6aa8b732 | 5686 | |
bfdaab09 | 5687 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
5688 | cr = exit_qualification & 15; |
5689 | reg = (exit_qualification >> 8) & 15; | |
5690 | switch ((exit_qualification >> 4) & 3) { | |
5691 | case 0: /* mov to cr */ | |
1e32c079 | 5692 | val = kvm_register_readl(vcpu, reg); |
229456fc | 5693 | trace_kvm_cr_write(cr, val); |
6aa8b732 AK |
5694 | switch (cr) { |
5695 | case 0: | |
eeadf9e7 | 5696 | err = handle_set_cr0(vcpu, val); |
db8fcefa | 5697 | kvm_complete_insn_gp(vcpu, err); |
6aa8b732 AK |
5698 | return 1; |
5699 | case 3: | |
2390218b | 5700 | err = kvm_set_cr3(vcpu, val); |
db8fcefa | 5701 | kvm_complete_insn_gp(vcpu, err); |
6aa8b732 AK |
5702 | return 1; |
5703 | case 4: | |
eeadf9e7 | 5704 | err = handle_set_cr4(vcpu, val); |
db8fcefa | 5705 | kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 5706 | return 1; |
0a5fff19 GN |
5707 | case 8: { |
5708 | u8 cr8_prev = kvm_get_cr8(vcpu); | |
1e32c079 | 5709 | u8 cr8 = (u8)val; |
eea1cff9 | 5710 | err = kvm_set_cr8(vcpu, cr8); |
db8fcefa | 5711 | kvm_complete_insn_gp(vcpu, err); |
35754c98 | 5712 | if (lapic_in_kernel(vcpu)) |
0a5fff19 GN |
5713 | return 1; |
5714 | if (cr8_prev <= cr8) | |
5715 | return 1; | |
851ba692 | 5716 | vcpu->run->exit_reason = KVM_EXIT_SET_TPR; |
0a5fff19 GN |
5717 | return 0; |
5718 | } | |
4b8073e4 | 5719 | } |
6aa8b732 | 5720 | break; |
25c4c276 | 5721 | case 2: /* clts */ |
eeadf9e7 | 5722 | handle_clts(vcpu); |
4d4ec087 | 5723 | trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); |
25c4c276 | 5724 | skip_emulated_instruction(vcpu); |
6b52d186 | 5725 | vmx_fpu_activate(vcpu); |
25c4c276 | 5726 | return 1; |
6aa8b732 AK |
5727 | case 1: /*mov from cr*/ |
5728 | switch (cr) { | |
5729 | case 3: | |
9f8fe504 AK |
5730 | val = kvm_read_cr3(vcpu); |
5731 | kvm_register_write(vcpu, reg, val); | |
5732 | trace_kvm_cr_read(cr, val); | |
6aa8b732 AK |
5733 | skip_emulated_instruction(vcpu); |
5734 | return 1; | |
5735 | case 8: | |
229456fc MT |
5736 | val = kvm_get_cr8(vcpu); |
5737 | kvm_register_write(vcpu, reg, val); | |
5738 | trace_kvm_cr_read(cr, val); | |
6aa8b732 AK |
5739 | skip_emulated_instruction(vcpu); |
5740 | return 1; | |
5741 | } | |
5742 | break; | |
5743 | case 3: /* lmsw */ | |
a1f83a74 | 5744 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
4d4ec087 | 5745 | trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); |
a1f83a74 | 5746 | kvm_lmsw(vcpu, val); |
6aa8b732 AK |
5747 | |
5748 | skip_emulated_instruction(vcpu); | |
5749 | return 1; | |
5750 | default: | |
5751 | break; | |
5752 | } | |
851ba692 | 5753 | vcpu->run->exit_reason = 0; |
a737f256 | 5754 | vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
5755 | (int)(exit_qualification >> 4) & 3, cr); |
5756 | return 0; | |
5757 | } | |
5758 | ||
851ba692 | 5759 | static int handle_dr(struct kvm_vcpu *vcpu) |
6aa8b732 | 5760 | { |
bfdaab09 | 5761 | unsigned long exit_qualification; |
16f8a6f9 NA |
5762 | int dr, dr7, reg; |
5763 | ||
5764 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
5765 | dr = exit_qualification & DEBUG_REG_ACCESS_NUM; | |
5766 | ||
5767 | /* First, if DR does not exist, trigger UD */ | |
5768 | if (!kvm_require_dr(vcpu, dr)) | |
5769 | return 1; | |
6aa8b732 | 5770 | |
f2483415 | 5771 | /* Do not handle if the CPL > 0, will trigger GP on re-entry */ |
0a79b009 AK |
5772 | if (!kvm_require_cpl(vcpu, 0)) |
5773 | return 1; | |
16f8a6f9 NA |
5774 | dr7 = vmcs_readl(GUEST_DR7); |
5775 | if (dr7 & DR7_GD) { | |
42dbaa5a JK |
5776 | /* |
5777 | * As the vm-exit takes precedence over the debug trap, we | |
5778 | * need to emulate the latter, either for the host or the | |
5779 | * guest debugging itself. | |
5780 | */ | |
5781 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
851ba692 | 5782 | vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; |
16f8a6f9 | 5783 | vcpu->run->debug.arch.dr7 = dr7; |
82b32774 | 5784 | vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
851ba692 AK |
5785 | vcpu->run->debug.arch.exception = DB_VECTOR; |
5786 | vcpu->run->exit_reason = KVM_EXIT_DEBUG; | |
42dbaa5a JK |
5787 | return 0; |
5788 | } else { | |
7305eb5d | 5789 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 5790 | vcpu->arch.dr6 |= DR6_BD | DR6_RTM; |
42dbaa5a JK |
5791 | kvm_queue_exception(vcpu, DB_VECTOR); |
5792 | return 1; | |
5793 | } | |
5794 | } | |
5795 | ||
81908bf4 | 5796 | if (vcpu->guest_debug == 0) { |
8f22372f PB |
5797 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
5798 | CPU_BASED_MOV_DR_EXITING); | |
81908bf4 PB |
5799 | |
5800 | /* | |
5801 | * No more DR vmexits; force a reload of the debug registers | |
5802 | * and reenter on this instruction. The next vmexit will | |
5803 | * retrieve the full state of the debug registers. | |
5804 | */ | |
5805 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
5806 | return 1; | |
5807 | } | |
5808 | ||
42dbaa5a JK |
5809 | reg = DEBUG_REG_ACCESS_REG(exit_qualification); |
5810 | if (exit_qualification & TYPE_MOV_FROM_DR) { | |
020df079 | 5811 | unsigned long val; |
4c4d563b JK |
5812 | |
5813 | if (kvm_get_dr(vcpu, dr, &val)) | |
5814 | return 1; | |
5815 | kvm_register_write(vcpu, reg, val); | |
020df079 | 5816 | } else |
5777392e | 5817 | if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) |
4c4d563b JK |
5818 | return 1; |
5819 | ||
6aa8b732 AK |
5820 | skip_emulated_instruction(vcpu); |
5821 | return 1; | |
5822 | } | |
5823 | ||
73aaf249 JK |
5824 | static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) |
5825 | { | |
5826 | return vcpu->arch.dr6; | |
5827 | } | |
5828 | ||
5829 | static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) | |
5830 | { | |
5831 | } | |
5832 | ||
81908bf4 PB |
5833 | static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
5834 | { | |
81908bf4 PB |
5835 | get_debugreg(vcpu->arch.db[0], 0); |
5836 | get_debugreg(vcpu->arch.db[1], 1); | |
5837 | get_debugreg(vcpu->arch.db[2], 2); | |
5838 | get_debugreg(vcpu->arch.db[3], 3); | |
5839 | get_debugreg(vcpu->arch.dr6, 6); | |
5840 | vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); | |
5841 | ||
5842 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
8f22372f | 5843 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING); |
81908bf4 PB |
5844 | } |
5845 | ||
020df079 GN |
5846 | static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) |
5847 | { | |
5848 | vmcs_writel(GUEST_DR7, val); | |
5849 | } | |
5850 | ||
851ba692 | 5851 | static int handle_cpuid(struct kvm_vcpu *vcpu) |
6aa8b732 | 5852 | { |
06465c5a AK |
5853 | kvm_emulate_cpuid(vcpu); |
5854 | return 1; | |
6aa8b732 AK |
5855 | } |
5856 | ||
851ba692 | 5857 | static int handle_rdmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 5858 | { |
ad312c7c | 5859 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
609e36d3 | 5860 | struct msr_data msr_info; |
6aa8b732 | 5861 | |
609e36d3 PB |
5862 | msr_info.index = ecx; |
5863 | msr_info.host_initiated = false; | |
5864 | if (vmx_get_msr(vcpu, &msr_info)) { | |
59200273 | 5865 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 5866 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
5867 | return 1; |
5868 | } | |
5869 | ||
609e36d3 | 5870 | trace_kvm_msr_read(ecx, msr_info.data); |
2714d1d3 | 5871 | |
6aa8b732 | 5872 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
609e36d3 PB |
5873 | vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u; |
5874 | vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u; | |
6aa8b732 AK |
5875 | skip_emulated_instruction(vcpu); |
5876 | return 1; | |
5877 | } | |
5878 | ||
851ba692 | 5879 | static int handle_wrmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 5880 | { |
8fe8ab46 | 5881 | struct msr_data msr; |
ad312c7c ZX |
5882 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
5883 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
5884 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 | 5885 | |
8fe8ab46 WA |
5886 | msr.data = data; |
5887 | msr.index = ecx; | |
5888 | msr.host_initiated = false; | |
854e8bb1 | 5889 | if (kvm_set_msr(vcpu, &msr) != 0) { |
59200273 | 5890 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 5891 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
5892 | return 1; |
5893 | } | |
5894 | ||
59200273 | 5895 | trace_kvm_msr_write(ecx, data); |
6aa8b732 AK |
5896 | skip_emulated_instruction(vcpu); |
5897 | return 1; | |
5898 | } | |
5899 | ||
851ba692 | 5900 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) |
6e5d865c | 5901 | { |
3842d135 | 5902 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6e5d865c YS |
5903 | return 1; |
5904 | } | |
5905 | ||
851ba692 | 5906 | static int handle_interrupt_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 5907 | { |
85f455f7 ED |
5908 | u32 cpu_based_vm_exec_control; |
5909 | ||
5910 | /* clear pending irq */ | |
5911 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
5912 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
5913 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2714d1d3 | 5914 | |
3842d135 AK |
5915 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5916 | ||
a26bf12a | 5917 | ++vcpu->stat.irq_window_exits; |
6aa8b732 AK |
5918 | return 1; |
5919 | } | |
5920 | ||
851ba692 | 5921 | static int handle_halt(struct kvm_vcpu *vcpu) |
6aa8b732 | 5922 | { |
d3bef15f | 5923 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
5924 | } |
5925 | ||
851ba692 | 5926 | static int handle_vmcall(struct kvm_vcpu *vcpu) |
c21415e8 | 5927 | { |
0d9c055e | 5928 | return kvm_emulate_hypercall(vcpu); |
c21415e8 IM |
5929 | } |
5930 | ||
ec25d5e6 GN |
5931 | static int handle_invd(struct kvm_vcpu *vcpu) |
5932 | { | |
51d8b661 | 5933 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
ec25d5e6 GN |
5934 | } |
5935 | ||
851ba692 | 5936 | static int handle_invlpg(struct kvm_vcpu *vcpu) |
a7052897 | 5937 | { |
f9c617f6 | 5938 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
a7052897 MT |
5939 | |
5940 | kvm_mmu_invlpg(vcpu, exit_qualification); | |
5941 | skip_emulated_instruction(vcpu); | |
5942 | return 1; | |
5943 | } | |
5944 | ||
fee84b07 AK |
5945 | static int handle_rdpmc(struct kvm_vcpu *vcpu) |
5946 | { | |
5947 | int err; | |
5948 | ||
5949 | err = kvm_rdpmc(vcpu); | |
5950 | kvm_complete_insn_gp(vcpu, err); | |
5951 | ||
5952 | return 1; | |
5953 | } | |
5954 | ||
851ba692 | 5955 | static int handle_wbinvd(struct kvm_vcpu *vcpu) |
e5edaa01 | 5956 | { |
f5f48ee1 | 5957 | kvm_emulate_wbinvd(vcpu); |
e5edaa01 ED |
5958 | return 1; |
5959 | } | |
5960 | ||
2acf923e DC |
5961 | static int handle_xsetbv(struct kvm_vcpu *vcpu) |
5962 | { | |
5963 | u64 new_bv = kvm_read_edx_eax(vcpu); | |
5964 | u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5965 | ||
5966 | if (kvm_set_xcr(vcpu, index, new_bv) == 0) | |
5967 | skip_emulated_instruction(vcpu); | |
5968 | return 1; | |
5969 | } | |
5970 | ||
f53cd63c WL |
5971 | static int handle_xsaves(struct kvm_vcpu *vcpu) |
5972 | { | |
5973 | skip_emulated_instruction(vcpu); | |
5974 | WARN(1, "this should never happen\n"); | |
5975 | return 1; | |
5976 | } | |
5977 | ||
5978 | static int handle_xrstors(struct kvm_vcpu *vcpu) | |
5979 | { | |
5980 | skip_emulated_instruction(vcpu); | |
5981 | WARN(1, "this should never happen\n"); | |
5982 | return 1; | |
5983 | } | |
5984 | ||
851ba692 | 5985 | static int handle_apic_access(struct kvm_vcpu *vcpu) |
f78e0e2e | 5986 | { |
58fbbf26 KT |
5987 | if (likely(fasteoi)) { |
5988 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
5989 | int access_type, offset; | |
5990 | ||
5991 | access_type = exit_qualification & APIC_ACCESS_TYPE; | |
5992 | offset = exit_qualification & APIC_ACCESS_OFFSET; | |
5993 | /* | |
5994 | * Sane guest uses MOV to write EOI, with written value | |
5995 | * not cared. So make a short-circuit here by avoiding | |
5996 | * heavy instruction emulation. | |
5997 | */ | |
5998 | if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && | |
5999 | (offset == APIC_EOI)) { | |
6000 | kvm_lapic_set_eoi(vcpu); | |
6001 | skip_emulated_instruction(vcpu); | |
6002 | return 1; | |
6003 | } | |
6004 | } | |
51d8b661 | 6005 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
f78e0e2e SY |
6006 | } |
6007 | ||
c7c9c56c YZ |
6008 | static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) |
6009 | { | |
6010 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6011 | int vector = exit_qualification & 0xff; | |
6012 | ||
6013 | /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ | |
6014 | kvm_apic_set_eoi_accelerated(vcpu, vector); | |
6015 | return 1; | |
6016 | } | |
6017 | ||
83d4c286 YZ |
6018 | static int handle_apic_write(struct kvm_vcpu *vcpu) |
6019 | { | |
6020 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6021 | u32 offset = exit_qualification & 0xfff; | |
6022 | ||
6023 | /* APIC-write VM exit is trap-like and thus no need to adjust IP */ | |
6024 | kvm_apic_write_nodecode(vcpu, offset); | |
6025 | return 1; | |
6026 | } | |
6027 | ||
851ba692 | 6028 | static int handle_task_switch(struct kvm_vcpu *vcpu) |
37817f29 | 6029 | { |
60637aac | 6030 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
37817f29 | 6031 | unsigned long exit_qualification; |
e269fb21 JK |
6032 | bool has_error_code = false; |
6033 | u32 error_code = 0; | |
37817f29 | 6034 | u16 tss_selector; |
7f3d35fd | 6035 | int reason, type, idt_v, idt_index; |
64a7ec06 GN |
6036 | |
6037 | idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | |
7f3d35fd | 6038 | idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); |
64a7ec06 | 6039 | type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); |
37817f29 IE |
6040 | |
6041 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6042 | ||
6043 | reason = (u32)exit_qualification >> 30; | |
64a7ec06 GN |
6044 | if (reason == TASK_SWITCH_GATE && idt_v) { |
6045 | switch (type) { | |
6046 | case INTR_TYPE_NMI_INTR: | |
6047 | vcpu->arch.nmi_injected = false; | |
654f06fc | 6048 | vmx_set_nmi_mask(vcpu, true); |
64a7ec06 GN |
6049 | break; |
6050 | case INTR_TYPE_EXT_INTR: | |
66fd3f7f | 6051 | case INTR_TYPE_SOFT_INTR: |
64a7ec06 GN |
6052 | kvm_clear_interrupt_queue(vcpu); |
6053 | break; | |
6054 | case INTR_TYPE_HARD_EXCEPTION: | |
e269fb21 JK |
6055 | if (vmx->idt_vectoring_info & |
6056 | VECTORING_INFO_DELIVER_CODE_MASK) { | |
6057 | has_error_code = true; | |
6058 | error_code = | |
6059 | vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
6060 | } | |
6061 | /* fall through */ | |
64a7ec06 GN |
6062 | case INTR_TYPE_SOFT_EXCEPTION: |
6063 | kvm_clear_exception_queue(vcpu); | |
6064 | break; | |
6065 | default: | |
6066 | break; | |
6067 | } | |
60637aac | 6068 | } |
37817f29 IE |
6069 | tss_selector = exit_qualification; |
6070 | ||
64a7ec06 GN |
6071 | if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && |
6072 | type != INTR_TYPE_EXT_INTR && | |
6073 | type != INTR_TYPE_NMI_INTR)) | |
6074 | skip_emulated_instruction(vcpu); | |
6075 | ||
7f3d35fd KW |
6076 | if (kvm_task_switch(vcpu, tss_selector, |
6077 | type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason, | |
6078 | has_error_code, error_code) == EMULATE_FAIL) { | |
acb54517 GN |
6079 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
6080 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6081 | vcpu->run->internal.ndata = 0; | |
42dbaa5a | 6082 | return 0; |
acb54517 | 6083 | } |
42dbaa5a | 6084 | |
42dbaa5a JK |
6085 | /* |
6086 | * TODO: What about debug traps on tss switch? | |
6087 | * Are we supposed to inject them and update dr6? | |
6088 | */ | |
6089 | ||
6090 | return 1; | |
37817f29 IE |
6091 | } |
6092 | ||
851ba692 | 6093 | static int handle_ept_violation(struct kvm_vcpu *vcpu) |
1439442c | 6094 | { |
f9c617f6 | 6095 | unsigned long exit_qualification; |
1439442c | 6096 | gpa_t gpa; |
4f5982a5 | 6097 | u32 error_code; |
1439442c | 6098 | int gla_validity; |
1439442c | 6099 | |
f9c617f6 | 6100 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
1439442c | 6101 | |
1439442c SY |
6102 | gla_validity = (exit_qualification >> 7) & 0x3; |
6103 | if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) { | |
6104 | printk(KERN_ERR "EPT: Handling EPT violation failed!\n"); | |
6105 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | |
6106 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | |
f9c617f6 | 6107 | vmcs_readl(GUEST_LINEAR_ADDRESS)); |
1439442c SY |
6108 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", |
6109 | (long unsigned int)exit_qualification); | |
851ba692 AK |
6110 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
6111 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION; | |
596ae895 | 6112 | return 0; |
1439442c SY |
6113 | } |
6114 | ||
0be9c7a8 GN |
6115 | /* |
6116 | * EPT violation happened while executing iret from NMI, | |
6117 | * "blocked by NMI" bit has to be set before next VM entry. | |
6118 | * There are errata that may cause this bit to not be set: | |
6119 | * AAK134, BY25. | |
6120 | */ | |
bcd1c294 GN |
6121 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && |
6122 | cpu_has_virtual_nmis() && | |
6123 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) | |
0be9c7a8 GN |
6124 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); |
6125 | ||
1439442c | 6126 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); |
229456fc | 6127 | trace_kvm_page_fault(gpa, exit_qualification); |
4f5982a5 | 6128 | |
d95c5568 BD |
6129 | /* it is a read fault? */ |
6130 | error_code = (exit_qualification << 2) & PFERR_USER_MASK; | |
6131 | /* it is a write fault? */ | |
6132 | error_code |= exit_qualification & PFERR_WRITE_MASK; | |
25d92081 | 6133 | /* It is a fetch fault? */ |
81ed33e4 | 6134 | error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK; |
4f5982a5 | 6135 | /* ept page table is present? */ |
d95c5568 | 6136 | error_code |= (exit_qualification & 0x38) != 0; |
4f5982a5 | 6137 | |
25d92081 YZ |
6138 | vcpu->arch.exit_qualification = exit_qualification; |
6139 | ||
4f5982a5 | 6140 | return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); |
1439442c SY |
6141 | } |
6142 | ||
851ba692 | 6143 | static int handle_ept_misconfig(struct kvm_vcpu *vcpu) |
68f89400 | 6144 | { |
f735d4af | 6145 | int ret; |
68f89400 MT |
6146 | gpa_t gpa; |
6147 | ||
6148 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
e32edf4f | 6149 | if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { |
68c3b4d1 | 6150 | skip_emulated_instruction(vcpu); |
931c33b1 | 6151 | trace_kvm_fast_mmio(gpa); |
68c3b4d1 MT |
6152 | return 1; |
6153 | } | |
68f89400 | 6154 | |
450869d6 | 6155 | ret = handle_mmio_page_fault(vcpu, gpa, true); |
b37fbea6 | 6156 | if (likely(ret == RET_MMIO_PF_EMULATE)) |
ce88decf XG |
6157 | return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) == |
6158 | EMULATE_DONE; | |
f8f55942 XG |
6159 | |
6160 | if (unlikely(ret == RET_MMIO_PF_INVALID)) | |
6161 | return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0); | |
6162 | ||
b37fbea6 | 6163 | if (unlikely(ret == RET_MMIO_PF_RETRY)) |
ce88decf XG |
6164 | return 1; |
6165 | ||
6166 | /* It is the real ept misconfig */ | |
f735d4af | 6167 | WARN_ON(1); |
68f89400 | 6168 | |
851ba692 AK |
6169 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
6170 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG; | |
68f89400 MT |
6171 | |
6172 | return 0; | |
6173 | } | |
6174 | ||
851ba692 | 6175 | static int handle_nmi_window(struct kvm_vcpu *vcpu) |
f08864b4 SY |
6176 | { |
6177 | u32 cpu_based_vm_exec_control; | |
6178 | ||
6179 | /* clear pending NMI */ | |
6180 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
6181 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
6182 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
6183 | ++vcpu->stat.nmi_window_exits; | |
3842d135 | 6184 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f08864b4 SY |
6185 | |
6186 | return 1; | |
6187 | } | |
6188 | ||
80ced186 | 6189 | static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) |
ea953ef0 | 6190 | { |
8b3079a5 AK |
6191 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6192 | enum emulation_result err = EMULATE_DONE; | |
80ced186 | 6193 | int ret = 1; |
49e9d557 AK |
6194 | u32 cpu_exec_ctrl; |
6195 | bool intr_window_requested; | |
b8405c18 | 6196 | unsigned count = 130; |
49e9d557 AK |
6197 | |
6198 | cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
6199 | intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING; | |
ea953ef0 | 6200 | |
98eb2f8b | 6201 | while (vmx->emulation_required && count-- != 0) { |
bdea48e3 | 6202 | if (intr_window_requested && vmx_interrupt_allowed(vcpu)) |
49e9d557 AK |
6203 | return handle_interrupt_window(&vmx->vcpu); |
6204 | ||
de87dcdd AK |
6205 | if (test_bit(KVM_REQ_EVENT, &vcpu->requests)) |
6206 | return 1; | |
6207 | ||
991eebf9 | 6208 | err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE); |
ea953ef0 | 6209 | |
ac0a48c3 | 6210 | if (err == EMULATE_USER_EXIT) { |
94452b9e | 6211 | ++vcpu->stat.mmio_exits; |
80ced186 MG |
6212 | ret = 0; |
6213 | goto out; | |
6214 | } | |
1d5a4d9b | 6215 | |
de5f70e0 AK |
6216 | if (err != EMULATE_DONE) { |
6217 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
6218 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6219 | vcpu->run->internal.ndata = 0; | |
6d77dbfc | 6220 | return 0; |
de5f70e0 | 6221 | } |
ea953ef0 | 6222 | |
8d76c49e GN |
6223 | if (vcpu->arch.halt_request) { |
6224 | vcpu->arch.halt_request = 0; | |
5cb56059 | 6225 | ret = kvm_vcpu_halt(vcpu); |
8d76c49e GN |
6226 | goto out; |
6227 | } | |
6228 | ||
ea953ef0 | 6229 | if (signal_pending(current)) |
80ced186 | 6230 | goto out; |
ea953ef0 MG |
6231 | if (need_resched()) |
6232 | schedule(); | |
6233 | } | |
6234 | ||
80ced186 MG |
6235 | out: |
6236 | return ret; | |
ea953ef0 MG |
6237 | } |
6238 | ||
b4a2d31d RK |
6239 | static int __grow_ple_window(int val) |
6240 | { | |
6241 | if (ple_window_grow < 1) | |
6242 | return ple_window; | |
6243 | ||
6244 | val = min(val, ple_window_actual_max); | |
6245 | ||
6246 | if (ple_window_grow < ple_window) | |
6247 | val *= ple_window_grow; | |
6248 | else | |
6249 | val += ple_window_grow; | |
6250 | ||
6251 | return val; | |
6252 | } | |
6253 | ||
6254 | static int __shrink_ple_window(int val, int modifier, int minimum) | |
6255 | { | |
6256 | if (modifier < 1) | |
6257 | return ple_window; | |
6258 | ||
6259 | if (modifier < ple_window) | |
6260 | val /= modifier; | |
6261 | else | |
6262 | val -= modifier; | |
6263 | ||
6264 | return max(val, minimum); | |
6265 | } | |
6266 | ||
6267 | static void grow_ple_window(struct kvm_vcpu *vcpu) | |
6268 | { | |
6269 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6270 | int old = vmx->ple_window; | |
6271 | ||
6272 | vmx->ple_window = __grow_ple_window(old); | |
6273 | ||
6274 | if (vmx->ple_window != old) | |
6275 | vmx->ple_window_dirty = true; | |
7b46268d RK |
6276 | |
6277 | trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
6278 | } |
6279 | ||
6280 | static void shrink_ple_window(struct kvm_vcpu *vcpu) | |
6281 | { | |
6282 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6283 | int old = vmx->ple_window; | |
6284 | ||
6285 | vmx->ple_window = __shrink_ple_window(old, | |
6286 | ple_window_shrink, ple_window); | |
6287 | ||
6288 | if (vmx->ple_window != old) | |
6289 | vmx->ple_window_dirty = true; | |
7b46268d RK |
6290 | |
6291 | trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
6292 | } |
6293 | ||
6294 | /* | |
6295 | * ple_window_actual_max is computed to be one grow_ple_window() below | |
6296 | * ple_window_max. (See __grow_ple_window for the reason.) | |
6297 | * This prevents overflows, because ple_window_max is int. | |
6298 | * ple_window_max effectively rounded down to a multiple of ple_window_grow in | |
6299 | * this process. | |
6300 | * ple_window_max is also prevented from setting vmx->ple_window < ple_window. | |
6301 | */ | |
6302 | static void update_ple_window_actual_max(void) | |
6303 | { | |
6304 | ple_window_actual_max = | |
6305 | __shrink_ple_window(max(ple_window_max, ple_window), | |
6306 | ple_window_grow, INT_MIN); | |
6307 | } | |
6308 | ||
bf9f6ac8 FW |
6309 | /* |
6310 | * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. | |
6311 | */ | |
6312 | static void wakeup_handler(void) | |
6313 | { | |
6314 | struct kvm_vcpu *vcpu; | |
6315 | int cpu = smp_processor_id(); | |
6316 | ||
6317 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
6318 | list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), | |
6319 | blocked_vcpu_list) { | |
6320 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
6321 | ||
6322 | if (pi_test_on(pi_desc) == 1) | |
6323 | kvm_vcpu_kick(vcpu); | |
6324 | } | |
6325 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
6326 | } | |
6327 | ||
f2c7648d TC |
6328 | static __init int hardware_setup(void) |
6329 | { | |
34a1cd60 TC |
6330 | int r = -ENOMEM, i, msr; |
6331 | ||
6332 | rdmsrl_safe(MSR_EFER, &host_efer); | |
6333 | ||
6334 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) | |
6335 | kvm_define_shared_msr(i, vmx_msr_index[i]); | |
6336 | ||
6337 | vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL); | |
6338 | if (!vmx_io_bitmap_a) | |
6339 | return r; | |
6340 | ||
6341 | vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL); | |
6342 | if (!vmx_io_bitmap_b) | |
6343 | goto out; | |
6344 | ||
6345 | vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL); | |
6346 | if (!vmx_msr_bitmap_legacy) | |
6347 | goto out1; | |
6348 | ||
6349 | vmx_msr_bitmap_legacy_x2apic = | |
6350 | (unsigned long *)__get_free_page(GFP_KERNEL); | |
6351 | if (!vmx_msr_bitmap_legacy_x2apic) | |
6352 | goto out2; | |
6353 | ||
6354 | vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL); | |
6355 | if (!vmx_msr_bitmap_longmode) | |
6356 | goto out3; | |
6357 | ||
6358 | vmx_msr_bitmap_longmode_x2apic = | |
6359 | (unsigned long *)__get_free_page(GFP_KERNEL); | |
6360 | if (!vmx_msr_bitmap_longmode_x2apic) | |
6361 | goto out4; | |
3af18d9c WV |
6362 | |
6363 | if (nested) { | |
6364 | vmx_msr_bitmap_nested = | |
6365 | (unsigned long *)__get_free_page(GFP_KERNEL); | |
6366 | if (!vmx_msr_bitmap_nested) | |
6367 | goto out5; | |
6368 | } | |
6369 | ||
34a1cd60 TC |
6370 | vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL); |
6371 | if (!vmx_vmread_bitmap) | |
3af18d9c | 6372 | goto out6; |
34a1cd60 TC |
6373 | |
6374 | vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL); | |
6375 | if (!vmx_vmwrite_bitmap) | |
3af18d9c | 6376 | goto out7; |
34a1cd60 TC |
6377 | |
6378 | memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE); | |
6379 | memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE); | |
6380 | ||
6381 | /* | |
6382 | * Allow direct access to the PC debug port (it is often used for I/O | |
6383 | * delays, but the vmexits simply slow things down). | |
6384 | */ | |
6385 | memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE); | |
6386 | clear_bit(0x80, vmx_io_bitmap_a); | |
6387 | ||
6388 | memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE); | |
6389 | ||
6390 | memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE); | |
6391 | memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE); | |
3af18d9c WV |
6392 | if (nested) |
6393 | memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE); | |
34a1cd60 | 6394 | |
34a1cd60 TC |
6395 | if (setup_vmcs_config(&vmcs_config) < 0) { |
6396 | r = -EIO; | |
3af18d9c | 6397 | goto out8; |
baa03522 | 6398 | } |
f2c7648d TC |
6399 | |
6400 | if (boot_cpu_has(X86_FEATURE_NX)) | |
6401 | kvm_enable_efer_bits(EFER_NX); | |
6402 | ||
6403 | if (!cpu_has_vmx_vpid()) | |
6404 | enable_vpid = 0; | |
6405 | if (!cpu_has_vmx_shadow_vmcs()) | |
6406 | enable_shadow_vmcs = 0; | |
6407 | if (enable_shadow_vmcs) | |
6408 | init_vmcs_shadow_fields(); | |
6409 | ||
6410 | if (!cpu_has_vmx_ept() || | |
6411 | !cpu_has_vmx_ept_4levels()) { | |
6412 | enable_ept = 0; | |
6413 | enable_unrestricted_guest = 0; | |
6414 | enable_ept_ad_bits = 0; | |
6415 | } | |
6416 | ||
6417 | if (!cpu_has_vmx_ept_ad_bits()) | |
6418 | enable_ept_ad_bits = 0; | |
6419 | ||
6420 | if (!cpu_has_vmx_unrestricted_guest()) | |
6421 | enable_unrestricted_guest = 0; | |
6422 | ||
ad15a296 | 6423 | if (!cpu_has_vmx_flexpriority()) |
f2c7648d TC |
6424 | flexpriority_enabled = 0; |
6425 | ||
ad15a296 PB |
6426 | /* |
6427 | * set_apic_access_page_addr() is used to reload apic access | |
6428 | * page upon invalidation. No need to do anything if not | |
6429 | * using the APIC_ACCESS_ADDR VMCS field. | |
6430 | */ | |
6431 | if (!flexpriority_enabled) | |
f2c7648d | 6432 | kvm_x86_ops->set_apic_access_page_addr = NULL; |
f2c7648d TC |
6433 | |
6434 | if (!cpu_has_vmx_tpr_shadow()) | |
6435 | kvm_x86_ops->update_cr8_intercept = NULL; | |
6436 | ||
6437 | if (enable_ept && !cpu_has_vmx_ept_2m_page()) | |
6438 | kvm_disable_largepages(); | |
6439 | ||
6440 | if (!cpu_has_vmx_ple()) | |
6441 | ple_gap = 0; | |
6442 | ||
6443 | if (!cpu_has_vmx_apicv()) | |
6444 | enable_apicv = 0; | |
6445 | ||
64903d61 HZ |
6446 | if (cpu_has_vmx_tsc_scaling()) { |
6447 | kvm_has_tsc_control = true; | |
6448 | kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; | |
6449 | kvm_tsc_scaling_ratio_frac_bits = 48; | |
6450 | } | |
6451 | ||
baa03522 TC |
6452 | vmx_disable_intercept_for_msr(MSR_FS_BASE, false); |
6453 | vmx_disable_intercept_for_msr(MSR_GS_BASE, false); | |
6454 | vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true); | |
6455 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false); | |
6456 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false); | |
6457 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false); | |
6458 | vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true); | |
6459 | ||
6460 | memcpy(vmx_msr_bitmap_legacy_x2apic, | |
6461 | vmx_msr_bitmap_legacy, PAGE_SIZE); | |
6462 | memcpy(vmx_msr_bitmap_longmode_x2apic, | |
6463 | vmx_msr_bitmap_longmode, PAGE_SIZE); | |
6464 | ||
04bb92e4 WL |
6465 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
6466 | ||
3ce424e4 RK |
6467 | for (msr = 0x800; msr <= 0x8ff; msr++) |
6468 | vmx_disable_intercept_msr_read_x2apic(msr); | |
6469 | ||
3ce424e4 RK |
6470 | /* TMCCT */ |
6471 | vmx_enable_intercept_msr_read_x2apic(0x839); | |
6472 | /* TPR */ | |
6473 | vmx_disable_intercept_msr_write_x2apic(0x808); | |
6474 | /* EOI */ | |
6475 | vmx_disable_intercept_msr_write_x2apic(0x80b); | |
6476 | /* SELF-IPI */ | |
6477 | vmx_disable_intercept_msr_write_x2apic(0x83f); | |
baa03522 TC |
6478 | |
6479 | if (enable_ept) { | |
d95c5568 | 6480 | kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, |
baa03522 TC |
6481 | (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull, |
6482 | (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull, | |
d95c5568 BD |
6483 | 0ull, VMX_EPT_EXECUTABLE_MASK, |
6484 | cpu_has_vmx_ept_execute_only() ? | |
6485 | 0ull : VMX_EPT_READABLE_MASK); | |
baa03522 TC |
6486 | ept_set_mmio_spte_mask(); |
6487 | kvm_enable_tdp(); | |
6488 | } else | |
6489 | kvm_disable_tdp(); | |
6490 | ||
6491 | update_ple_window_actual_max(); | |
6492 | ||
843e4330 KH |
6493 | /* |
6494 | * Only enable PML when hardware supports PML feature, and both EPT | |
6495 | * and EPT A/D bit features are enabled -- PML depends on them to work. | |
6496 | */ | |
6497 | if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) | |
6498 | enable_pml = 0; | |
6499 | ||
6500 | if (!enable_pml) { | |
6501 | kvm_x86_ops->slot_enable_log_dirty = NULL; | |
6502 | kvm_x86_ops->slot_disable_log_dirty = NULL; | |
6503 | kvm_x86_ops->flush_log_dirty = NULL; | |
6504 | kvm_x86_ops->enable_log_dirty_pt_masked = NULL; | |
6505 | } | |
6506 | ||
64672c95 YJ |
6507 | if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) { |
6508 | u64 vmx_msr; | |
6509 | ||
6510 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
6511 | cpu_preemption_timer_multi = | |
6512 | vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; | |
6513 | } else { | |
6514 | kvm_x86_ops->set_hv_timer = NULL; | |
6515 | kvm_x86_ops->cancel_hv_timer = NULL; | |
6516 | } | |
6517 | ||
bf9f6ac8 FW |
6518 | kvm_set_posted_intr_wakeup_handler(wakeup_handler); |
6519 | ||
c45dcc71 AR |
6520 | kvm_mce_cap_supported |= MCG_LMCE_P; |
6521 | ||
f2c7648d | 6522 | return alloc_kvm_area(); |
34a1cd60 | 6523 | |
3af18d9c | 6524 | out8: |
34a1cd60 | 6525 | free_page((unsigned long)vmx_vmwrite_bitmap); |
3af18d9c | 6526 | out7: |
34a1cd60 | 6527 | free_page((unsigned long)vmx_vmread_bitmap); |
3af18d9c WV |
6528 | out6: |
6529 | if (nested) | |
6530 | free_page((unsigned long)vmx_msr_bitmap_nested); | |
34a1cd60 TC |
6531 | out5: |
6532 | free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic); | |
6533 | out4: | |
6534 | free_page((unsigned long)vmx_msr_bitmap_longmode); | |
6535 | out3: | |
6536 | free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic); | |
6537 | out2: | |
6538 | free_page((unsigned long)vmx_msr_bitmap_legacy); | |
6539 | out1: | |
6540 | free_page((unsigned long)vmx_io_bitmap_b); | |
6541 | out: | |
6542 | free_page((unsigned long)vmx_io_bitmap_a); | |
6543 | ||
6544 | return r; | |
f2c7648d TC |
6545 | } |
6546 | ||
6547 | static __exit void hardware_unsetup(void) | |
6548 | { | |
34a1cd60 TC |
6549 | free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic); |
6550 | free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic); | |
6551 | free_page((unsigned long)vmx_msr_bitmap_legacy); | |
6552 | free_page((unsigned long)vmx_msr_bitmap_longmode); | |
6553 | free_page((unsigned long)vmx_io_bitmap_b); | |
6554 | free_page((unsigned long)vmx_io_bitmap_a); | |
6555 | free_page((unsigned long)vmx_vmwrite_bitmap); | |
6556 | free_page((unsigned long)vmx_vmread_bitmap); | |
3af18d9c WV |
6557 | if (nested) |
6558 | free_page((unsigned long)vmx_msr_bitmap_nested); | |
34a1cd60 | 6559 | |
f2c7648d TC |
6560 | free_kvm_area(); |
6561 | } | |
6562 | ||
4b8d54f9 ZE |
6563 | /* |
6564 | * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE | |
6565 | * exiting, so only get here on cpu with PAUSE-Loop-Exiting. | |
6566 | */ | |
9fb41ba8 | 6567 | static int handle_pause(struct kvm_vcpu *vcpu) |
4b8d54f9 | 6568 | { |
b4a2d31d RK |
6569 | if (ple_gap) |
6570 | grow_ple_window(vcpu); | |
6571 | ||
4b8d54f9 ZE |
6572 | skip_emulated_instruction(vcpu); |
6573 | kvm_vcpu_on_spin(vcpu); | |
6574 | ||
6575 | return 1; | |
6576 | } | |
6577 | ||
87c00572 | 6578 | static int handle_nop(struct kvm_vcpu *vcpu) |
59708670 | 6579 | { |
87c00572 | 6580 | skip_emulated_instruction(vcpu); |
59708670 SY |
6581 | return 1; |
6582 | } | |
6583 | ||
87c00572 GS |
6584 | static int handle_mwait(struct kvm_vcpu *vcpu) |
6585 | { | |
6586 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
6587 | return handle_nop(vcpu); | |
6588 | } | |
6589 | ||
5f3d45e7 MD |
6590 | static int handle_monitor_trap(struct kvm_vcpu *vcpu) |
6591 | { | |
6592 | return 1; | |
6593 | } | |
6594 | ||
87c00572 GS |
6595 | static int handle_monitor(struct kvm_vcpu *vcpu) |
6596 | { | |
6597 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
6598 | return handle_nop(vcpu); | |
6599 | } | |
6600 | ||
ff2f6fe9 NHE |
6601 | /* |
6602 | * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12. | |
6603 | * We could reuse a single VMCS for all the L2 guests, but we also want the | |
6604 | * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this | |
6605 | * allows keeping them loaded on the processor, and in the future will allow | |
6606 | * optimizations where prepare_vmcs02 doesn't need to set all the fields on | |
6607 | * every entry if they never change. | |
6608 | * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE | |
6609 | * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first. | |
6610 | * | |
6611 | * The following functions allocate and free a vmcs02 in this pool. | |
6612 | */ | |
6613 | ||
6614 | /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */ | |
6615 | static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx) | |
6616 | { | |
6617 | struct vmcs02_list *item; | |
6618 | list_for_each_entry(item, &vmx->nested.vmcs02_pool, list) | |
6619 | if (item->vmptr == vmx->nested.current_vmptr) { | |
6620 | list_move(&item->list, &vmx->nested.vmcs02_pool); | |
6621 | return &item->vmcs02; | |
6622 | } | |
6623 | ||
6624 | if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) { | |
6625 | /* Recycle the least recently used VMCS. */ | |
d74c0e6b GT |
6626 | item = list_last_entry(&vmx->nested.vmcs02_pool, |
6627 | struct vmcs02_list, list); | |
ff2f6fe9 NHE |
6628 | item->vmptr = vmx->nested.current_vmptr; |
6629 | list_move(&item->list, &vmx->nested.vmcs02_pool); | |
6630 | return &item->vmcs02; | |
6631 | } | |
6632 | ||
6633 | /* Create a new VMCS */ | |
0fa24ce3 | 6634 | item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL); |
ff2f6fe9 NHE |
6635 | if (!item) |
6636 | return NULL; | |
6637 | item->vmcs02.vmcs = alloc_vmcs(); | |
6638 | if (!item->vmcs02.vmcs) { | |
6639 | kfree(item); | |
6640 | return NULL; | |
6641 | } | |
6642 | loaded_vmcs_init(&item->vmcs02); | |
6643 | item->vmptr = vmx->nested.current_vmptr; | |
6644 | list_add(&(item->list), &(vmx->nested.vmcs02_pool)); | |
6645 | vmx->nested.vmcs02_num++; | |
6646 | return &item->vmcs02; | |
6647 | } | |
6648 | ||
6649 | /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */ | |
6650 | static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr) | |
6651 | { | |
6652 | struct vmcs02_list *item; | |
6653 | list_for_each_entry(item, &vmx->nested.vmcs02_pool, list) | |
6654 | if (item->vmptr == vmptr) { | |
6655 | free_loaded_vmcs(&item->vmcs02); | |
6656 | list_del(&item->list); | |
6657 | kfree(item); | |
6658 | vmx->nested.vmcs02_num--; | |
6659 | return; | |
6660 | } | |
6661 | } | |
6662 | ||
6663 | /* | |
6664 | * Free all VMCSs saved for this vcpu, except the one pointed by | |
4fa7734c PB |
6665 | * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs |
6666 | * must be &vmx->vmcs01. | |
ff2f6fe9 NHE |
6667 | */ |
6668 | static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx) | |
6669 | { | |
6670 | struct vmcs02_list *item, *n; | |
4fa7734c PB |
6671 | |
6672 | WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01); | |
ff2f6fe9 | 6673 | list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) { |
4fa7734c PB |
6674 | /* |
6675 | * Something will leak if the above WARN triggers. Better than | |
6676 | * a use-after-free. | |
6677 | */ | |
6678 | if (vmx->loaded_vmcs == &item->vmcs02) | |
6679 | continue; | |
6680 | ||
6681 | free_loaded_vmcs(&item->vmcs02); | |
ff2f6fe9 NHE |
6682 | list_del(&item->list); |
6683 | kfree(item); | |
4fa7734c | 6684 | vmx->nested.vmcs02_num--; |
ff2f6fe9 | 6685 | } |
ff2f6fe9 NHE |
6686 | } |
6687 | ||
0658fbaa ACL |
6688 | /* |
6689 | * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(), | |
6690 | * set the success or error code of an emulated VMX instruction, as specified | |
6691 | * by Vol 2B, VMX Instruction Reference, "Conventions". | |
6692 | */ | |
6693 | static void nested_vmx_succeed(struct kvm_vcpu *vcpu) | |
6694 | { | |
6695 | vmx_set_rflags(vcpu, vmx_get_rflags(vcpu) | |
6696 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
6697 | X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF)); | |
6698 | } | |
6699 | ||
6700 | static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu) | |
6701 | { | |
6702 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
6703 | & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | | |
6704 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
6705 | | X86_EFLAGS_CF); | |
6706 | } | |
6707 | ||
145c28dd | 6708 | static void nested_vmx_failValid(struct kvm_vcpu *vcpu, |
0658fbaa ACL |
6709 | u32 vm_instruction_error) |
6710 | { | |
6711 | if (to_vmx(vcpu)->nested.current_vmptr == -1ull) { | |
6712 | /* | |
6713 | * failValid writes the error number to the current VMCS, which | |
6714 | * can't be done there isn't a current VMCS. | |
6715 | */ | |
6716 | nested_vmx_failInvalid(vcpu); | |
6717 | return; | |
6718 | } | |
6719 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
6720 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
6721 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
6722 | | X86_EFLAGS_ZF); | |
6723 | get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error; | |
6724 | /* | |
6725 | * We don't need to force a shadow sync because | |
6726 | * VM_INSTRUCTION_ERROR is not shadowed | |
6727 | */ | |
6728 | } | |
145c28dd | 6729 | |
ff651cb6 WV |
6730 | static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator) |
6731 | { | |
6732 | /* TODO: not to reset guest simply here. */ | |
6733 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
6734 | pr_warn("kvm: nested vmx abort, indicator %d\n", indicator); | |
6735 | } | |
6736 | ||
f4124500 JK |
6737 | static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer) |
6738 | { | |
6739 | struct vcpu_vmx *vmx = | |
6740 | container_of(timer, struct vcpu_vmx, nested.preemption_timer); | |
6741 | ||
6742 | vmx->nested.preemption_timer_expired = true; | |
6743 | kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu); | |
6744 | kvm_vcpu_kick(&vmx->vcpu); | |
6745 | ||
6746 | return HRTIMER_NORESTART; | |
6747 | } | |
6748 | ||
19677e32 BD |
6749 | /* |
6750 | * Decode the memory-address operand of a vmx instruction, as recorded on an | |
6751 | * exit caused by such an instruction (run by a guest hypervisor). | |
6752 | * On success, returns 0. When the operand is invalid, returns 1 and throws | |
6753 | * #UD or #GP. | |
6754 | */ | |
6755 | static int get_vmx_mem_address(struct kvm_vcpu *vcpu, | |
6756 | unsigned long exit_qualification, | |
f9eb4af6 | 6757 | u32 vmx_instruction_info, bool wr, gva_t *ret) |
19677e32 | 6758 | { |
f9eb4af6 EK |
6759 | gva_t off; |
6760 | bool exn; | |
6761 | struct kvm_segment s; | |
6762 | ||
19677e32 BD |
6763 | /* |
6764 | * According to Vol. 3B, "Information for VM Exits Due to Instruction | |
6765 | * Execution", on an exit, vmx_instruction_info holds most of the | |
6766 | * addressing components of the operand. Only the displacement part | |
6767 | * is put in exit_qualification (see 3B, "Basic VM-Exit Information"). | |
6768 | * For how an actual address is calculated from all these components, | |
6769 | * refer to Vol. 1, "Operand Addressing". | |
6770 | */ | |
6771 | int scaling = vmx_instruction_info & 3; | |
6772 | int addr_size = (vmx_instruction_info >> 7) & 7; | |
6773 | bool is_reg = vmx_instruction_info & (1u << 10); | |
6774 | int seg_reg = (vmx_instruction_info >> 15) & 7; | |
6775 | int index_reg = (vmx_instruction_info >> 18) & 0xf; | |
6776 | bool index_is_valid = !(vmx_instruction_info & (1u << 22)); | |
6777 | int base_reg = (vmx_instruction_info >> 23) & 0xf; | |
6778 | bool base_is_valid = !(vmx_instruction_info & (1u << 27)); | |
6779 | ||
6780 | if (is_reg) { | |
6781 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6782 | return 1; | |
6783 | } | |
6784 | ||
6785 | /* Addr = segment_base + offset */ | |
6786 | /* offset = base + [index * scale] + displacement */ | |
f9eb4af6 | 6787 | off = exit_qualification; /* holds the displacement */ |
19677e32 | 6788 | if (base_is_valid) |
f9eb4af6 | 6789 | off += kvm_register_read(vcpu, base_reg); |
19677e32 | 6790 | if (index_is_valid) |
f9eb4af6 EK |
6791 | off += kvm_register_read(vcpu, index_reg)<<scaling; |
6792 | vmx_get_segment(vcpu, &s, seg_reg); | |
6793 | *ret = s.base + off; | |
19677e32 BD |
6794 | |
6795 | if (addr_size == 1) /* 32 bit */ | |
6796 | *ret &= 0xffffffff; | |
6797 | ||
f9eb4af6 EK |
6798 | /* Checks for #GP/#SS exceptions. */ |
6799 | exn = false; | |
6800 | if (is_protmode(vcpu)) { | |
6801 | /* Protected mode: apply checks for segment validity in the | |
6802 | * following order: | |
6803 | * - segment type check (#GP(0) may be thrown) | |
6804 | * - usability check (#GP(0)/#SS(0)) | |
6805 | * - limit check (#GP(0)/#SS(0)) | |
6806 | */ | |
6807 | if (wr) | |
6808 | /* #GP(0) if the destination operand is located in a | |
6809 | * read-only data segment or any code segment. | |
6810 | */ | |
6811 | exn = ((s.type & 0xa) == 0 || (s.type & 8)); | |
6812 | else | |
6813 | /* #GP(0) if the source operand is located in an | |
6814 | * execute-only code segment | |
6815 | */ | |
6816 | exn = ((s.type & 0xa) == 8); | |
6817 | } | |
6818 | if (exn) { | |
6819 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
6820 | return 1; | |
6821 | } | |
6822 | if (is_long_mode(vcpu)) { | |
6823 | /* Long mode: #GP(0)/#SS(0) if the memory address is in a | |
6824 | * non-canonical form. This is an only check for long mode. | |
6825 | */ | |
6826 | exn = is_noncanonical_address(*ret); | |
6827 | } else if (is_protmode(vcpu)) { | |
6828 | /* Protected mode: #GP(0)/#SS(0) if the segment is unusable. | |
6829 | */ | |
6830 | exn = (s.unusable != 0); | |
6831 | /* Protected mode: #GP(0)/#SS(0) if the memory | |
6832 | * operand is outside the segment limit. | |
6833 | */ | |
6834 | exn = exn || (off + sizeof(u64) > s.limit); | |
6835 | } | |
6836 | if (exn) { | |
6837 | kvm_queue_exception_e(vcpu, | |
6838 | seg_reg == VCPU_SREG_SS ? | |
6839 | SS_VECTOR : GP_VECTOR, | |
6840 | 0); | |
6841 | return 1; | |
6842 | } | |
6843 | ||
19677e32 BD |
6844 | return 0; |
6845 | } | |
6846 | ||
3573e22c BD |
6847 | /* |
6848 | * This function performs the various checks including | |
6849 | * - if it's 4KB aligned | |
6850 | * - No bits beyond the physical address width are set | |
6851 | * - Returns 0 on success or else 1 | |
4291b588 | 6852 | * (Intel SDM Section 30.3) |
3573e22c | 6853 | */ |
4291b588 BD |
6854 | static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason, |
6855 | gpa_t *vmpointer) | |
3573e22c BD |
6856 | { |
6857 | gva_t gva; | |
6858 | gpa_t vmptr; | |
6859 | struct x86_exception e; | |
6860 | struct page *page; | |
6861 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6862 | int maxphyaddr = cpuid_maxphyaddr(vcpu); | |
6863 | ||
6864 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
f9eb4af6 | 6865 | vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva)) |
3573e22c BD |
6866 | return 1; |
6867 | ||
6868 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr, | |
6869 | sizeof(vmptr), &e)) { | |
6870 | kvm_inject_page_fault(vcpu, &e); | |
6871 | return 1; | |
6872 | } | |
6873 | ||
6874 | switch (exit_reason) { | |
6875 | case EXIT_REASON_VMON: | |
6876 | /* | |
6877 | * SDM 3: 24.11.5 | |
6878 | * The first 4 bytes of VMXON region contain the supported | |
6879 | * VMCS revision identifier | |
6880 | * | |
6881 | * Note - IA32_VMX_BASIC[48] will never be 1 | |
6882 | * for the nested case; | |
6883 | * which replaces physical address width with 32 | |
6884 | * | |
6885 | */ | |
bc39c4db | 6886 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) { |
3573e22c BD |
6887 | nested_vmx_failInvalid(vcpu); |
6888 | skip_emulated_instruction(vcpu); | |
6889 | return 1; | |
6890 | } | |
6891 | ||
6892 | page = nested_get_page(vcpu, vmptr); | |
6893 | if (page == NULL || | |
6894 | *(u32 *)kmap(page) != VMCS12_REVISION) { | |
6895 | nested_vmx_failInvalid(vcpu); | |
6896 | kunmap(page); | |
6897 | skip_emulated_instruction(vcpu); | |
6898 | return 1; | |
6899 | } | |
6900 | kunmap(page); | |
6901 | vmx->nested.vmxon_ptr = vmptr; | |
6902 | break; | |
4291b588 | 6903 | case EXIT_REASON_VMCLEAR: |
bc39c4db | 6904 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) { |
4291b588 BD |
6905 | nested_vmx_failValid(vcpu, |
6906 | VMXERR_VMCLEAR_INVALID_ADDRESS); | |
6907 | skip_emulated_instruction(vcpu); | |
6908 | return 1; | |
6909 | } | |
6910 | ||
6911 | if (vmptr == vmx->nested.vmxon_ptr) { | |
6912 | nested_vmx_failValid(vcpu, | |
6913 | VMXERR_VMCLEAR_VMXON_POINTER); | |
6914 | skip_emulated_instruction(vcpu); | |
6915 | return 1; | |
6916 | } | |
6917 | break; | |
6918 | case EXIT_REASON_VMPTRLD: | |
bc39c4db | 6919 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) { |
4291b588 BD |
6920 | nested_vmx_failValid(vcpu, |
6921 | VMXERR_VMPTRLD_INVALID_ADDRESS); | |
6922 | skip_emulated_instruction(vcpu); | |
6923 | return 1; | |
6924 | } | |
3573e22c | 6925 | |
4291b588 BD |
6926 | if (vmptr == vmx->nested.vmxon_ptr) { |
6927 | nested_vmx_failValid(vcpu, | |
6928 | VMXERR_VMCLEAR_VMXON_POINTER); | |
6929 | skip_emulated_instruction(vcpu); | |
6930 | return 1; | |
6931 | } | |
6932 | break; | |
3573e22c BD |
6933 | default: |
6934 | return 1; /* shouldn't happen */ | |
6935 | } | |
6936 | ||
4291b588 BD |
6937 | if (vmpointer) |
6938 | *vmpointer = vmptr; | |
3573e22c BD |
6939 | return 0; |
6940 | } | |
6941 | ||
ec378aee NHE |
6942 | /* |
6943 | * Emulate the VMXON instruction. | |
6944 | * Currently, we just remember that VMX is active, and do not save or even | |
6945 | * inspect the argument to VMXON (the so-called "VMXON pointer") because we | |
6946 | * do not currently need to store anything in that guest-allocated memory | |
6947 | * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their | |
6948 | * argument is different from the VMXON pointer (which the spec says they do). | |
6949 | */ | |
6950 | static int handle_vmon(struct kvm_vcpu *vcpu) | |
6951 | { | |
6952 | struct kvm_segment cs; | |
6953 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8de48833 | 6954 | struct vmcs *shadow_vmcs; |
b3897a49 NHE |
6955 | const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED |
6956 | | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
ec378aee NHE |
6957 | |
6958 | /* The Intel VMX Instruction Reference lists a bunch of bits that | |
6959 | * are prerequisite to running VMXON, most notably cr4.VMXE must be | |
6960 | * set to 1 (see vmx_set_cr4() for when we allow the guest to set this). | |
6961 | * Otherwise, we should fail with #UD. We test these now: | |
6962 | */ | |
6963 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) || | |
6964 | !kvm_read_cr0_bits(vcpu, X86_CR0_PE) || | |
6965 | (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { | |
6966 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6967 | return 1; | |
6968 | } | |
6969 | ||
6970 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
6971 | if (is_long_mode(vcpu) && !cs.l) { | |
6972 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6973 | return 1; | |
6974 | } | |
6975 | ||
6976 | if (vmx_get_cpl(vcpu)) { | |
6977 | kvm_inject_gp(vcpu, 0); | |
6978 | return 1; | |
6979 | } | |
3573e22c | 6980 | |
4291b588 | 6981 | if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL)) |
3573e22c BD |
6982 | return 1; |
6983 | ||
145c28dd AG |
6984 | if (vmx->nested.vmxon) { |
6985 | nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION); | |
6986 | skip_emulated_instruction(vcpu); | |
6987 | return 1; | |
6988 | } | |
b3897a49 | 6989 | |
3b84080b | 6990 | if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES) |
b3897a49 NHE |
6991 | != VMXON_NEEDED_FEATURES) { |
6992 | kvm_inject_gp(vcpu, 0); | |
6993 | return 1; | |
6994 | } | |
6995 | ||
4f2777bc DM |
6996 | vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL); |
6997 | if (!vmx->nested.cached_vmcs12) | |
6998 | return -ENOMEM; | |
6999 | ||
8de48833 AG |
7000 | if (enable_shadow_vmcs) { |
7001 | shadow_vmcs = alloc_vmcs(); | |
4f2777bc DM |
7002 | if (!shadow_vmcs) { |
7003 | kfree(vmx->nested.cached_vmcs12); | |
8de48833 | 7004 | return -ENOMEM; |
4f2777bc | 7005 | } |
8de48833 AG |
7006 | /* mark vmcs as shadow */ |
7007 | shadow_vmcs->revision_id |= (1u << 31); | |
7008 | /* init shadow vmcs */ | |
7009 | vmcs_clear(shadow_vmcs); | |
7010 | vmx->nested.current_shadow_vmcs = shadow_vmcs; | |
7011 | } | |
ec378aee | 7012 | |
ff2f6fe9 NHE |
7013 | INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool)); |
7014 | vmx->nested.vmcs02_num = 0; | |
7015 | ||
f4124500 JK |
7016 | hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC, |
7017 | HRTIMER_MODE_REL); | |
7018 | vmx->nested.preemption_timer.function = vmx_preemption_timer_fn; | |
7019 | ||
ec378aee NHE |
7020 | vmx->nested.vmxon = true; |
7021 | ||
7022 | skip_emulated_instruction(vcpu); | |
a25eb114 | 7023 | nested_vmx_succeed(vcpu); |
ec378aee NHE |
7024 | return 1; |
7025 | } | |
7026 | ||
7027 | /* | |
7028 | * Intel's VMX Instruction Reference specifies a common set of prerequisites | |
7029 | * for running VMX instructions (except VMXON, whose prerequisites are | |
7030 | * slightly different). It also specifies what exception to inject otherwise. | |
7031 | */ | |
7032 | static int nested_vmx_check_permission(struct kvm_vcpu *vcpu) | |
7033 | { | |
7034 | struct kvm_segment cs; | |
7035 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7036 | ||
7037 | if (!vmx->nested.vmxon) { | |
7038 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7039 | return 0; | |
7040 | } | |
7041 | ||
7042 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
7043 | if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) || | |
7044 | (is_long_mode(vcpu) && !cs.l)) { | |
7045 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7046 | return 0; | |
7047 | } | |
7048 | ||
7049 | if (vmx_get_cpl(vcpu)) { | |
7050 | kvm_inject_gp(vcpu, 0); | |
7051 | return 0; | |
7052 | } | |
7053 | ||
7054 | return 1; | |
7055 | } | |
7056 | ||
e7953d7f AG |
7057 | static inline void nested_release_vmcs12(struct vcpu_vmx *vmx) |
7058 | { | |
9a2a05b9 PB |
7059 | if (vmx->nested.current_vmptr == -1ull) |
7060 | return; | |
7061 | ||
7062 | /* current_vmptr and current_vmcs12 are always set/reset together */ | |
7063 | if (WARN_ON(vmx->nested.current_vmcs12 == NULL)) | |
7064 | return; | |
7065 | ||
012f83cb | 7066 | if (enable_shadow_vmcs) { |
9a2a05b9 PB |
7067 | /* copy to memory all shadowed fields in case |
7068 | they were modified */ | |
7069 | copy_shadow_to_vmcs12(vmx); | |
7070 | vmx->nested.sync_shadow_vmcs = false; | |
7ec36296 XG |
7071 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, |
7072 | SECONDARY_EXEC_SHADOW_VMCS); | |
9a2a05b9 | 7073 | vmcs_write64(VMCS_LINK_POINTER, -1ull); |
012f83cb | 7074 | } |
705699a1 | 7075 | vmx->nested.posted_intr_nv = -1; |
4f2777bc DM |
7076 | |
7077 | /* Flush VMCS12 to guest memory */ | |
7078 | memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12, | |
7079 | VMCS12_SIZE); | |
7080 | ||
e7953d7f AG |
7081 | kunmap(vmx->nested.current_vmcs12_page); |
7082 | nested_release_page(vmx->nested.current_vmcs12_page); | |
9a2a05b9 PB |
7083 | vmx->nested.current_vmptr = -1ull; |
7084 | vmx->nested.current_vmcs12 = NULL; | |
e7953d7f AG |
7085 | } |
7086 | ||
ec378aee NHE |
7087 | /* |
7088 | * Free whatever needs to be freed from vmx->nested when L1 goes down, or | |
7089 | * just stops using VMX. | |
7090 | */ | |
7091 | static void free_nested(struct vcpu_vmx *vmx) | |
7092 | { | |
7093 | if (!vmx->nested.vmxon) | |
7094 | return; | |
9a2a05b9 | 7095 | |
ec378aee | 7096 | vmx->nested.vmxon = false; |
5c614b35 | 7097 | free_vpid(vmx->nested.vpid02); |
9a2a05b9 | 7098 | nested_release_vmcs12(vmx); |
e7953d7f AG |
7099 | if (enable_shadow_vmcs) |
7100 | free_vmcs(vmx->nested.current_shadow_vmcs); | |
4f2777bc | 7101 | kfree(vmx->nested.cached_vmcs12); |
fe3ef05c NHE |
7102 | /* Unpin physical memory we referred to in current vmcs02 */ |
7103 | if (vmx->nested.apic_access_page) { | |
7104 | nested_release_page(vmx->nested.apic_access_page); | |
48d89b92 | 7105 | vmx->nested.apic_access_page = NULL; |
fe3ef05c | 7106 | } |
a7c0b07d WL |
7107 | if (vmx->nested.virtual_apic_page) { |
7108 | nested_release_page(vmx->nested.virtual_apic_page); | |
48d89b92 | 7109 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 7110 | } |
705699a1 WV |
7111 | if (vmx->nested.pi_desc_page) { |
7112 | kunmap(vmx->nested.pi_desc_page); | |
7113 | nested_release_page(vmx->nested.pi_desc_page); | |
7114 | vmx->nested.pi_desc_page = NULL; | |
7115 | vmx->nested.pi_desc = NULL; | |
7116 | } | |
ff2f6fe9 NHE |
7117 | |
7118 | nested_free_all_saved_vmcss(vmx); | |
ec378aee NHE |
7119 | } |
7120 | ||
7121 | /* Emulate the VMXOFF instruction */ | |
7122 | static int handle_vmoff(struct kvm_vcpu *vcpu) | |
7123 | { | |
7124 | if (!nested_vmx_check_permission(vcpu)) | |
7125 | return 1; | |
7126 | free_nested(to_vmx(vcpu)); | |
7127 | skip_emulated_instruction(vcpu); | |
a25eb114 | 7128 | nested_vmx_succeed(vcpu); |
ec378aee NHE |
7129 | return 1; |
7130 | } | |
7131 | ||
27d6c865 NHE |
7132 | /* Emulate the VMCLEAR instruction */ |
7133 | static int handle_vmclear(struct kvm_vcpu *vcpu) | |
7134 | { | |
7135 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
27d6c865 NHE |
7136 | gpa_t vmptr; |
7137 | struct vmcs12 *vmcs12; | |
7138 | struct page *page; | |
27d6c865 NHE |
7139 | |
7140 | if (!nested_vmx_check_permission(vcpu)) | |
7141 | return 1; | |
7142 | ||
4291b588 | 7143 | if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr)) |
27d6c865 | 7144 | return 1; |
27d6c865 | 7145 | |
9a2a05b9 | 7146 | if (vmptr == vmx->nested.current_vmptr) |
e7953d7f | 7147 | nested_release_vmcs12(vmx); |
27d6c865 NHE |
7148 | |
7149 | page = nested_get_page(vcpu, vmptr); | |
7150 | if (page == NULL) { | |
7151 | /* | |
7152 | * For accurate processor emulation, VMCLEAR beyond available | |
7153 | * physical memory should do nothing at all. However, it is | |
7154 | * possible that a nested vmx bug, not a guest hypervisor bug, | |
7155 | * resulted in this case, so let's shut down before doing any | |
7156 | * more damage: | |
7157 | */ | |
7158 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
7159 | return 1; | |
7160 | } | |
7161 | vmcs12 = kmap(page); | |
7162 | vmcs12->launch_state = 0; | |
7163 | kunmap(page); | |
7164 | nested_release_page(page); | |
7165 | ||
7166 | nested_free_vmcs02(vmx, vmptr); | |
7167 | ||
7168 | skip_emulated_instruction(vcpu); | |
7169 | nested_vmx_succeed(vcpu); | |
7170 | return 1; | |
7171 | } | |
7172 | ||
cd232ad0 NHE |
7173 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch); |
7174 | ||
7175 | /* Emulate the VMLAUNCH instruction */ | |
7176 | static int handle_vmlaunch(struct kvm_vcpu *vcpu) | |
7177 | { | |
7178 | return nested_vmx_run(vcpu, true); | |
7179 | } | |
7180 | ||
7181 | /* Emulate the VMRESUME instruction */ | |
7182 | static int handle_vmresume(struct kvm_vcpu *vcpu) | |
7183 | { | |
7184 | ||
7185 | return nested_vmx_run(vcpu, false); | |
7186 | } | |
7187 | ||
49f705c5 NHE |
7188 | enum vmcs_field_type { |
7189 | VMCS_FIELD_TYPE_U16 = 0, | |
7190 | VMCS_FIELD_TYPE_U64 = 1, | |
7191 | VMCS_FIELD_TYPE_U32 = 2, | |
7192 | VMCS_FIELD_TYPE_NATURAL_WIDTH = 3 | |
7193 | }; | |
7194 | ||
7195 | static inline int vmcs_field_type(unsigned long field) | |
7196 | { | |
7197 | if (0x1 & field) /* the *_HIGH fields are all 32 bit */ | |
7198 | return VMCS_FIELD_TYPE_U32; | |
7199 | return (field >> 13) & 0x3 ; | |
7200 | } | |
7201 | ||
7202 | static inline int vmcs_field_readonly(unsigned long field) | |
7203 | { | |
7204 | return (((field >> 10) & 0x3) == 1); | |
7205 | } | |
7206 | ||
7207 | /* | |
7208 | * Read a vmcs12 field. Since these can have varying lengths and we return | |
7209 | * one type, we chose the biggest type (u64) and zero-extend the return value | |
7210 | * to that size. Note that the caller, handle_vmread, might need to use only | |
7211 | * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of | |
7212 | * 64-bit fields are to be returned). | |
7213 | */ | |
a2ae9df7 PB |
7214 | static inline int vmcs12_read_any(struct kvm_vcpu *vcpu, |
7215 | unsigned long field, u64 *ret) | |
49f705c5 NHE |
7216 | { |
7217 | short offset = vmcs_field_to_offset(field); | |
7218 | char *p; | |
7219 | ||
7220 | if (offset < 0) | |
a2ae9df7 | 7221 | return offset; |
49f705c5 NHE |
7222 | |
7223 | p = ((char *)(get_vmcs12(vcpu))) + offset; | |
7224 | ||
7225 | switch (vmcs_field_type(field)) { | |
7226 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7227 | *ret = *((natural_width *)p); | |
a2ae9df7 | 7228 | return 0; |
49f705c5 NHE |
7229 | case VMCS_FIELD_TYPE_U16: |
7230 | *ret = *((u16 *)p); | |
a2ae9df7 | 7231 | return 0; |
49f705c5 NHE |
7232 | case VMCS_FIELD_TYPE_U32: |
7233 | *ret = *((u32 *)p); | |
a2ae9df7 | 7234 | return 0; |
49f705c5 NHE |
7235 | case VMCS_FIELD_TYPE_U64: |
7236 | *ret = *((u64 *)p); | |
a2ae9df7 | 7237 | return 0; |
49f705c5 | 7238 | default: |
a2ae9df7 PB |
7239 | WARN_ON(1); |
7240 | return -ENOENT; | |
49f705c5 NHE |
7241 | } |
7242 | } | |
7243 | ||
20b97fea | 7244 | |
a2ae9df7 PB |
7245 | static inline int vmcs12_write_any(struct kvm_vcpu *vcpu, |
7246 | unsigned long field, u64 field_value){ | |
20b97fea AG |
7247 | short offset = vmcs_field_to_offset(field); |
7248 | char *p = ((char *) get_vmcs12(vcpu)) + offset; | |
7249 | if (offset < 0) | |
a2ae9df7 | 7250 | return offset; |
20b97fea AG |
7251 | |
7252 | switch (vmcs_field_type(field)) { | |
7253 | case VMCS_FIELD_TYPE_U16: | |
7254 | *(u16 *)p = field_value; | |
a2ae9df7 | 7255 | return 0; |
20b97fea AG |
7256 | case VMCS_FIELD_TYPE_U32: |
7257 | *(u32 *)p = field_value; | |
a2ae9df7 | 7258 | return 0; |
20b97fea AG |
7259 | case VMCS_FIELD_TYPE_U64: |
7260 | *(u64 *)p = field_value; | |
a2ae9df7 | 7261 | return 0; |
20b97fea AG |
7262 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: |
7263 | *(natural_width *)p = field_value; | |
a2ae9df7 | 7264 | return 0; |
20b97fea | 7265 | default: |
a2ae9df7 PB |
7266 | WARN_ON(1); |
7267 | return -ENOENT; | |
20b97fea AG |
7268 | } |
7269 | ||
7270 | } | |
7271 | ||
16f5b903 AG |
7272 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx) |
7273 | { | |
7274 | int i; | |
7275 | unsigned long field; | |
7276 | u64 field_value; | |
7277 | struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs; | |
c2bae893 MK |
7278 | const unsigned long *fields = shadow_read_write_fields; |
7279 | const int num_fields = max_shadow_read_write_fields; | |
16f5b903 | 7280 | |
282da870 JK |
7281 | preempt_disable(); |
7282 | ||
16f5b903 AG |
7283 | vmcs_load(shadow_vmcs); |
7284 | ||
7285 | for (i = 0; i < num_fields; i++) { | |
7286 | field = fields[i]; | |
7287 | switch (vmcs_field_type(field)) { | |
7288 | case VMCS_FIELD_TYPE_U16: | |
7289 | field_value = vmcs_read16(field); | |
7290 | break; | |
7291 | case VMCS_FIELD_TYPE_U32: | |
7292 | field_value = vmcs_read32(field); | |
7293 | break; | |
7294 | case VMCS_FIELD_TYPE_U64: | |
7295 | field_value = vmcs_read64(field); | |
7296 | break; | |
7297 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7298 | field_value = vmcs_readl(field); | |
7299 | break; | |
a2ae9df7 PB |
7300 | default: |
7301 | WARN_ON(1); | |
7302 | continue; | |
16f5b903 AG |
7303 | } |
7304 | vmcs12_write_any(&vmx->vcpu, field, field_value); | |
7305 | } | |
7306 | ||
7307 | vmcs_clear(shadow_vmcs); | |
7308 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
282da870 JK |
7309 | |
7310 | preempt_enable(); | |
16f5b903 AG |
7311 | } |
7312 | ||
c3114420 AG |
7313 | static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx) |
7314 | { | |
c2bae893 MK |
7315 | const unsigned long *fields[] = { |
7316 | shadow_read_write_fields, | |
7317 | shadow_read_only_fields | |
c3114420 | 7318 | }; |
c2bae893 | 7319 | const int max_fields[] = { |
c3114420 AG |
7320 | max_shadow_read_write_fields, |
7321 | max_shadow_read_only_fields | |
7322 | }; | |
7323 | int i, q; | |
7324 | unsigned long field; | |
7325 | u64 field_value = 0; | |
7326 | struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs; | |
7327 | ||
7328 | vmcs_load(shadow_vmcs); | |
7329 | ||
c2bae893 | 7330 | for (q = 0; q < ARRAY_SIZE(fields); q++) { |
c3114420 AG |
7331 | for (i = 0; i < max_fields[q]; i++) { |
7332 | field = fields[q][i]; | |
7333 | vmcs12_read_any(&vmx->vcpu, field, &field_value); | |
7334 | ||
7335 | switch (vmcs_field_type(field)) { | |
7336 | case VMCS_FIELD_TYPE_U16: | |
7337 | vmcs_write16(field, (u16)field_value); | |
7338 | break; | |
7339 | case VMCS_FIELD_TYPE_U32: | |
7340 | vmcs_write32(field, (u32)field_value); | |
7341 | break; | |
7342 | case VMCS_FIELD_TYPE_U64: | |
7343 | vmcs_write64(field, (u64)field_value); | |
7344 | break; | |
7345 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7346 | vmcs_writel(field, (long)field_value); | |
7347 | break; | |
a2ae9df7 PB |
7348 | default: |
7349 | WARN_ON(1); | |
7350 | break; | |
c3114420 AG |
7351 | } |
7352 | } | |
7353 | } | |
7354 | ||
7355 | vmcs_clear(shadow_vmcs); | |
7356 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
7357 | } | |
7358 | ||
49f705c5 NHE |
7359 | /* |
7360 | * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was | |
7361 | * used before) all generate the same failure when it is missing. | |
7362 | */ | |
7363 | static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu) | |
7364 | { | |
7365 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7366 | if (vmx->nested.current_vmptr == -1ull) { | |
7367 | nested_vmx_failInvalid(vcpu); | |
7368 | skip_emulated_instruction(vcpu); | |
7369 | return 0; | |
7370 | } | |
7371 | return 1; | |
7372 | } | |
7373 | ||
7374 | static int handle_vmread(struct kvm_vcpu *vcpu) | |
7375 | { | |
7376 | unsigned long field; | |
7377 | u64 field_value; | |
7378 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7379 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7380 | gva_t gva = 0; | |
7381 | ||
7382 | if (!nested_vmx_check_permission(vcpu) || | |
7383 | !nested_vmx_check_vmcs12(vcpu)) | |
7384 | return 1; | |
7385 | ||
7386 | /* Decode instruction info and find the field to read */ | |
27e6fb5d | 7387 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 | 7388 | /* Read the field, zero-extended to a u64 field_value */ |
a2ae9df7 | 7389 | if (vmcs12_read_any(vcpu, field, &field_value) < 0) { |
49f705c5 NHE |
7390 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
7391 | skip_emulated_instruction(vcpu); | |
7392 | return 1; | |
7393 | } | |
7394 | /* | |
7395 | * Now copy part of this value to register or memory, as requested. | |
7396 | * Note that the number of bits actually copied is 32 or 64 depending | |
7397 | * on the guest's mode (32 or 64 bit), not on the given field's length. | |
7398 | */ | |
7399 | if (vmx_instruction_info & (1u << 10)) { | |
27e6fb5d | 7400 | kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf), |
49f705c5 NHE |
7401 | field_value); |
7402 | } else { | |
7403 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7404 | vmx_instruction_info, true, &gva)) |
49f705c5 NHE |
7405 | return 1; |
7406 | /* _system ok, as nested_vmx_check_permission verified cpl=0 */ | |
7407 | kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva, | |
7408 | &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL); | |
7409 | } | |
7410 | ||
7411 | nested_vmx_succeed(vcpu); | |
7412 | skip_emulated_instruction(vcpu); | |
7413 | return 1; | |
7414 | } | |
7415 | ||
7416 | ||
7417 | static int handle_vmwrite(struct kvm_vcpu *vcpu) | |
7418 | { | |
7419 | unsigned long field; | |
7420 | gva_t gva; | |
7421 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7422 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
49f705c5 NHE |
7423 | /* The value to write might be 32 or 64 bits, depending on L1's long |
7424 | * mode, and eventually we need to write that into a field of several | |
7425 | * possible lengths. The code below first zero-extends the value to 64 | |
6a6256f9 | 7426 | * bit (field_value), and then copies only the appropriate number of |
49f705c5 NHE |
7427 | * bits into the vmcs12 field. |
7428 | */ | |
7429 | u64 field_value = 0; | |
7430 | struct x86_exception e; | |
7431 | ||
7432 | if (!nested_vmx_check_permission(vcpu) || | |
7433 | !nested_vmx_check_vmcs12(vcpu)) | |
7434 | return 1; | |
7435 | ||
7436 | if (vmx_instruction_info & (1u << 10)) | |
27e6fb5d | 7437 | field_value = kvm_register_readl(vcpu, |
49f705c5 NHE |
7438 | (((vmx_instruction_info) >> 3) & 0xf)); |
7439 | else { | |
7440 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7441 | vmx_instruction_info, false, &gva)) |
49f705c5 NHE |
7442 | return 1; |
7443 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, | |
27e6fb5d | 7444 | &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) { |
49f705c5 NHE |
7445 | kvm_inject_page_fault(vcpu, &e); |
7446 | return 1; | |
7447 | } | |
7448 | } | |
7449 | ||
7450 | ||
27e6fb5d | 7451 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 NHE |
7452 | if (vmcs_field_readonly(field)) { |
7453 | nested_vmx_failValid(vcpu, | |
7454 | VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT); | |
7455 | skip_emulated_instruction(vcpu); | |
7456 | return 1; | |
7457 | } | |
7458 | ||
a2ae9df7 | 7459 | if (vmcs12_write_any(vcpu, field, field_value) < 0) { |
49f705c5 NHE |
7460 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
7461 | skip_emulated_instruction(vcpu); | |
7462 | return 1; | |
7463 | } | |
7464 | ||
7465 | nested_vmx_succeed(vcpu); | |
7466 | skip_emulated_instruction(vcpu); | |
7467 | return 1; | |
7468 | } | |
7469 | ||
63846663 NHE |
7470 | /* Emulate the VMPTRLD instruction */ |
7471 | static int handle_vmptrld(struct kvm_vcpu *vcpu) | |
7472 | { | |
7473 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
63846663 | 7474 | gpa_t vmptr; |
63846663 NHE |
7475 | |
7476 | if (!nested_vmx_check_permission(vcpu)) | |
7477 | return 1; | |
7478 | ||
4291b588 | 7479 | if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr)) |
63846663 | 7480 | return 1; |
63846663 NHE |
7481 | |
7482 | if (vmx->nested.current_vmptr != vmptr) { | |
7483 | struct vmcs12 *new_vmcs12; | |
7484 | struct page *page; | |
7485 | page = nested_get_page(vcpu, vmptr); | |
7486 | if (page == NULL) { | |
7487 | nested_vmx_failInvalid(vcpu); | |
7488 | skip_emulated_instruction(vcpu); | |
7489 | return 1; | |
7490 | } | |
7491 | new_vmcs12 = kmap(page); | |
7492 | if (new_vmcs12->revision_id != VMCS12_REVISION) { | |
7493 | kunmap(page); | |
7494 | nested_release_page_clean(page); | |
7495 | nested_vmx_failValid(vcpu, | |
7496 | VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID); | |
7497 | skip_emulated_instruction(vcpu); | |
7498 | return 1; | |
7499 | } | |
63846663 | 7500 | |
9a2a05b9 | 7501 | nested_release_vmcs12(vmx); |
63846663 NHE |
7502 | vmx->nested.current_vmptr = vmptr; |
7503 | vmx->nested.current_vmcs12 = new_vmcs12; | |
7504 | vmx->nested.current_vmcs12_page = page; | |
4f2777bc DM |
7505 | /* |
7506 | * Load VMCS12 from guest memory since it is not already | |
7507 | * cached. | |
7508 | */ | |
7509 | memcpy(vmx->nested.cached_vmcs12, | |
7510 | vmx->nested.current_vmcs12, VMCS12_SIZE); | |
7511 | ||
012f83cb | 7512 | if (enable_shadow_vmcs) { |
7ec36296 XG |
7513 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, |
7514 | SECONDARY_EXEC_SHADOW_VMCS); | |
8a1b9dd0 AG |
7515 | vmcs_write64(VMCS_LINK_POINTER, |
7516 | __pa(vmx->nested.current_shadow_vmcs)); | |
012f83cb AG |
7517 | vmx->nested.sync_shadow_vmcs = true; |
7518 | } | |
63846663 NHE |
7519 | } |
7520 | ||
7521 | nested_vmx_succeed(vcpu); | |
7522 | skip_emulated_instruction(vcpu); | |
7523 | return 1; | |
7524 | } | |
7525 | ||
6a4d7550 NHE |
7526 | /* Emulate the VMPTRST instruction */ |
7527 | static int handle_vmptrst(struct kvm_vcpu *vcpu) | |
7528 | { | |
7529 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7530 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7531 | gva_t vmcs_gva; | |
7532 | struct x86_exception e; | |
7533 | ||
7534 | if (!nested_vmx_check_permission(vcpu)) | |
7535 | return 1; | |
7536 | ||
7537 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7538 | vmx_instruction_info, true, &vmcs_gva)) |
6a4d7550 NHE |
7539 | return 1; |
7540 | /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */ | |
7541 | if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva, | |
7542 | (void *)&to_vmx(vcpu)->nested.current_vmptr, | |
7543 | sizeof(u64), &e)) { | |
7544 | kvm_inject_page_fault(vcpu, &e); | |
7545 | return 1; | |
7546 | } | |
7547 | nested_vmx_succeed(vcpu); | |
7548 | skip_emulated_instruction(vcpu); | |
7549 | return 1; | |
7550 | } | |
7551 | ||
bfd0a56b NHE |
7552 | /* Emulate the INVEPT instruction */ |
7553 | static int handle_invept(struct kvm_vcpu *vcpu) | |
7554 | { | |
b9c237bb | 7555 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
bfd0a56b NHE |
7556 | u32 vmx_instruction_info, types; |
7557 | unsigned long type; | |
7558 | gva_t gva; | |
7559 | struct x86_exception e; | |
7560 | struct { | |
7561 | u64 eptp, gpa; | |
7562 | } operand; | |
bfd0a56b | 7563 | |
b9c237bb WV |
7564 | if (!(vmx->nested.nested_vmx_secondary_ctls_high & |
7565 | SECONDARY_EXEC_ENABLE_EPT) || | |
7566 | !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) { | |
bfd0a56b NHE |
7567 | kvm_queue_exception(vcpu, UD_VECTOR); |
7568 | return 1; | |
7569 | } | |
7570 | ||
7571 | if (!nested_vmx_check_permission(vcpu)) | |
7572 | return 1; | |
7573 | ||
7574 | if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) { | |
7575 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7576 | return 1; | |
7577 | } | |
7578 | ||
7579 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
27e6fb5d | 7580 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); |
bfd0a56b | 7581 | |
b9c237bb | 7582 | types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6; |
bfd0a56b NHE |
7583 | |
7584 | if (!(types & (1UL << type))) { | |
7585 | nested_vmx_failValid(vcpu, | |
7586 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
2849eb4f | 7587 | skip_emulated_instruction(vcpu); |
bfd0a56b NHE |
7588 | return 1; |
7589 | } | |
7590 | ||
7591 | /* According to the Intel VMX instruction reference, the memory | |
7592 | * operand is read even if it isn't needed (e.g., for type==global) | |
7593 | */ | |
7594 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
f9eb4af6 | 7595 | vmx_instruction_info, false, &gva)) |
bfd0a56b NHE |
7596 | return 1; |
7597 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand, | |
7598 | sizeof(operand), &e)) { | |
7599 | kvm_inject_page_fault(vcpu, &e); | |
7600 | return 1; | |
7601 | } | |
7602 | ||
7603 | switch (type) { | |
bfd0a56b NHE |
7604 | case VMX_EPT_EXTENT_GLOBAL: |
7605 | kvm_mmu_sync_roots(vcpu); | |
77c3913b | 7606 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
bfd0a56b NHE |
7607 | nested_vmx_succeed(vcpu); |
7608 | break; | |
7609 | default: | |
4b855078 | 7610 | /* Trap single context invalidation invept calls */ |
bfd0a56b NHE |
7611 | BUG_ON(1); |
7612 | break; | |
7613 | } | |
7614 | ||
7615 | skip_emulated_instruction(vcpu); | |
7616 | return 1; | |
7617 | } | |
7618 | ||
a642fc30 PM |
7619 | static int handle_invvpid(struct kvm_vcpu *vcpu) |
7620 | { | |
99b83ac8 WL |
7621 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
7622 | u32 vmx_instruction_info; | |
7623 | unsigned long type, types; | |
7624 | gva_t gva; | |
7625 | struct x86_exception e; | |
7626 | int vpid; | |
7627 | ||
7628 | if (!(vmx->nested.nested_vmx_secondary_ctls_high & | |
7629 | SECONDARY_EXEC_ENABLE_VPID) || | |
7630 | !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) { | |
7631 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7632 | return 1; | |
7633 | } | |
7634 | ||
7635 | if (!nested_vmx_check_permission(vcpu)) | |
7636 | return 1; | |
7637 | ||
7638 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7639 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); | |
7640 | ||
7641 | types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7; | |
7642 | ||
7643 | if (!(types & (1UL << type))) { | |
7644 | nested_vmx_failValid(vcpu, | |
7645 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
f6870ee9 | 7646 | skip_emulated_instruction(vcpu); |
99b83ac8 WL |
7647 | return 1; |
7648 | } | |
7649 | ||
7650 | /* according to the intel vmx instruction reference, the memory | |
7651 | * operand is read even if it isn't needed (e.g., for type==global) | |
7652 | */ | |
7653 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
7654 | vmx_instruction_info, false, &gva)) | |
7655 | return 1; | |
7656 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid, | |
7657 | sizeof(u32), &e)) { | |
7658 | kvm_inject_page_fault(vcpu, &e); | |
7659 | return 1; | |
7660 | } | |
7661 | ||
7662 | switch (type) { | |
ef697a71 PB |
7663 | case VMX_VPID_EXTENT_SINGLE_CONTEXT: |
7664 | /* | |
7665 | * Old versions of KVM use the single-context version so we | |
7666 | * have to support it; just treat it the same as all-context. | |
7667 | */ | |
99b83ac8 | 7668 | case VMX_VPID_EXTENT_ALL_CONTEXT: |
5c614b35 | 7669 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02); |
99b83ac8 WL |
7670 | nested_vmx_succeed(vcpu); |
7671 | break; | |
7672 | default: | |
ef697a71 | 7673 | /* Trap individual address invalidation invvpid calls */ |
99b83ac8 WL |
7674 | BUG_ON(1); |
7675 | break; | |
7676 | } | |
7677 | ||
7678 | skip_emulated_instruction(vcpu); | |
a642fc30 PM |
7679 | return 1; |
7680 | } | |
7681 | ||
843e4330 KH |
7682 | static int handle_pml_full(struct kvm_vcpu *vcpu) |
7683 | { | |
7684 | unsigned long exit_qualification; | |
7685 | ||
7686 | trace_kvm_pml_full(vcpu->vcpu_id); | |
7687 | ||
7688 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7689 | ||
7690 | /* | |
7691 | * PML buffer FULL happened while executing iret from NMI, | |
7692 | * "blocked by NMI" bit has to be set before next VM entry. | |
7693 | */ | |
7694 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && | |
7695 | cpu_has_virtual_nmis() && | |
7696 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) | |
7697 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
7698 | GUEST_INTR_STATE_NMI); | |
7699 | ||
7700 | /* | |
7701 | * PML buffer already flushed at beginning of VMEXIT. Nothing to do | |
7702 | * here.., and there's no userspace involvement needed for PML. | |
7703 | */ | |
7704 | return 1; | |
7705 | } | |
7706 | ||
8b3e34e4 XG |
7707 | static int handle_pcommit(struct kvm_vcpu *vcpu) |
7708 | { | |
7709 | /* we never catch pcommit instruct for L1 guest. */ | |
7710 | WARN_ON(1); | |
7711 | return 1; | |
7712 | } | |
7713 | ||
64672c95 YJ |
7714 | static int handle_preemption_timer(struct kvm_vcpu *vcpu) |
7715 | { | |
7716 | kvm_lapic_expired_hv_timer(vcpu); | |
7717 | return 1; | |
7718 | } | |
7719 | ||
6aa8b732 AK |
7720 | /* |
7721 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
7722 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
7723 | * to be done to userspace and return 0. | |
7724 | */ | |
772e0318 | 7725 | static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { |
6aa8b732 AK |
7726 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, |
7727 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 7728 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
f08864b4 | 7729 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, |
6aa8b732 | 7730 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
7731 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
7732 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
7733 | [EXIT_REASON_CPUID] = handle_cpuid, | |
7734 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
7735 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
7736 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
7737 | [EXIT_REASON_HLT] = handle_halt, | |
ec25d5e6 | 7738 | [EXIT_REASON_INVD] = handle_invd, |
a7052897 | 7739 | [EXIT_REASON_INVLPG] = handle_invlpg, |
fee84b07 | 7740 | [EXIT_REASON_RDPMC] = handle_rdpmc, |
c21415e8 | 7741 | [EXIT_REASON_VMCALL] = handle_vmcall, |
27d6c865 | 7742 | [EXIT_REASON_VMCLEAR] = handle_vmclear, |
cd232ad0 | 7743 | [EXIT_REASON_VMLAUNCH] = handle_vmlaunch, |
63846663 | 7744 | [EXIT_REASON_VMPTRLD] = handle_vmptrld, |
6a4d7550 | 7745 | [EXIT_REASON_VMPTRST] = handle_vmptrst, |
49f705c5 | 7746 | [EXIT_REASON_VMREAD] = handle_vmread, |
cd232ad0 | 7747 | [EXIT_REASON_VMRESUME] = handle_vmresume, |
49f705c5 | 7748 | [EXIT_REASON_VMWRITE] = handle_vmwrite, |
ec378aee NHE |
7749 | [EXIT_REASON_VMOFF] = handle_vmoff, |
7750 | [EXIT_REASON_VMON] = handle_vmon, | |
f78e0e2e SY |
7751 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
7752 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
83d4c286 | 7753 | [EXIT_REASON_APIC_WRITE] = handle_apic_write, |
c7c9c56c | 7754 | [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, |
e5edaa01 | 7755 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
2acf923e | 7756 | [EXIT_REASON_XSETBV] = handle_xsetbv, |
37817f29 | 7757 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
a0861c02 | 7758 | [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, |
68f89400 MT |
7759 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
7760 | [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, | |
4b8d54f9 | 7761 | [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, |
87c00572 | 7762 | [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, |
5f3d45e7 | 7763 | [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, |
87c00572 | 7764 | [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, |
bfd0a56b | 7765 | [EXIT_REASON_INVEPT] = handle_invept, |
a642fc30 | 7766 | [EXIT_REASON_INVVPID] = handle_invvpid, |
f53cd63c WL |
7767 | [EXIT_REASON_XSAVES] = handle_xsaves, |
7768 | [EXIT_REASON_XRSTORS] = handle_xrstors, | |
843e4330 | 7769 | [EXIT_REASON_PML_FULL] = handle_pml_full, |
8b3e34e4 | 7770 | [EXIT_REASON_PCOMMIT] = handle_pcommit, |
64672c95 | 7771 | [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, |
6aa8b732 AK |
7772 | }; |
7773 | ||
7774 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 7775 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 | 7776 | |
908a7bdd JK |
7777 | static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu, |
7778 | struct vmcs12 *vmcs12) | |
7779 | { | |
7780 | unsigned long exit_qualification; | |
7781 | gpa_t bitmap, last_bitmap; | |
7782 | unsigned int port; | |
7783 | int size; | |
7784 | u8 b; | |
7785 | ||
908a7bdd | 7786 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) |
2f0a6397 | 7787 | return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING); |
908a7bdd JK |
7788 | |
7789 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7790 | ||
7791 | port = exit_qualification >> 16; | |
7792 | size = (exit_qualification & 7) + 1; | |
7793 | ||
7794 | last_bitmap = (gpa_t)-1; | |
7795 | b = -1; | |
7796 | ||
7797 | while (size > 0) { | |
7798 | if (port < 0x8000) | |
7799 | bitmap = vmcs12->io_bitmap_a; | |
7800 | else if (port < 0x10000) | |
7801 | bitmap = vmcs12->io_bitmap_b; | |
7802 | else | |
1d804d07 | 7803 | return true; |
908a7bdd JK |
7804 | bitmap += (port & 0x7fff) / 8; |
7805 | ||
7806 | if (last_bitmap != bitmap) | |
54bf36aa | 7807 | if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1)) |
1d804d07 | 7808 | return true; |
908a7bdd | 7809 | if (b & (1 << (port & 7))) |
1d804d07 | 7810 | return true; |
908a7bdd JK |
7811 | |
7812 | port++; | |
7813 | size--; | |
7814 | last_bitmap = bitmap; | |
7815 | } | |
7816 | ||
1d804d07 | 7817 | return false; |
908a7bdd JK |
7818 | } |
7819 | ||
644d711a NHE |
7820 | /* |
7821 | * Return 1 if we should exit from L2 to L1 to handle an MSR access access, | |
7822 | * rather than handle it ourselves in L0. I.e., check whether L1 expressed | |
7823 | * disinterest in the current event (read or write a specific MSR) by using an | |
7824 | * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps. | |
7825 | */ | |
7826 | static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu, | |
7827 | struct vmcs12 *vmcs12, u32 exit_reason) | |
7828 | { | |
7829 | u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX]; | |
7830 | gpa_t bitmap; | |
7831 | ||
cbd29cb6 | 7832 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) |
1d804d07 | 7833 | return true; |
644d711a NHE |
7834 | |
7835 | /* | |
7836 | * The MSR_BITMAP page is divided into four 1024-byte bitmaps, | |
7837 | * for the four combinations of read/write and low/high MSR numbers. | |
7838 | * First we need to figure out which of the four to use: | |
7839 | */ | |
7840 | bitmap = vmcs12->msr_bitmap; | |
7841 | if (exit_reason == EXIT_REASON_MSR_WRITE) | |
7842 | bitmap += 2048; | |
7843 | if (msr_index >= 0xc0000000) { | |
7844 | msr_index -= 0xc0000000; | |
7845 | bitmap += 1024; | |
7846 | } | |
7847 | ||
7848 | /* Then read the msr_index'th bit from this bitmap: */ | |
7849 | if (msr_index < 1024*8) { | |
7850 | unsigned char b; | |
54bf36aa | 7851 | if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1)) |
1d804d07 | 7852 | return true; |
644d711a NHE |
7853 | return 1 & (b >> (msr_index & 7)); |
7854 | } else | |
1d804d07 | 7855 | return true; /* let L1 handle the wrong parameter */ |
644d711a NHE |
7856 | } |
7857 | ||
7858 | /* | |
7859 | * Return 1 if we should exit from L2 to L1 to handle a CR access exit, | |
7860 | * rather than handle it ourselves in L0. I.e., check if L1 wanted to | |
7861 | * intercept (via guest_host_mask etc.) the current event. | |
7862 | */ | |
7863 | static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu, | |
7864 | struct vmcs12 *vmcs12) | |
7865 | { | |
7866 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7867 | int cr = exit_qualification & 15; | |
7868 | int reg = (exit_qualification >> 8) & 15; | |
1e32c079 | 7869 | unsigned long val = kvm_register_readl(vcpu, reg); |
644d711a NHE |
7870 | |
7871 | switch ((exit_qualification >> 4) & 3) { | |
7872 | case 0: /* mov to cr */ | |
7873 | switch (cr) { | |
7874 | case 0: | |
7875 | if (vmcs12->cr0_guest_host_mask & | |
7876 | (val ^ vmcs12->cr0_read_shadow)) | |
1d804d07 | 7877 | return true; |
644d711a NHE |
7878 | break; |
7879 | case 3: | |
7880 | if ((vmcs12->cr3_target_count >= 1 && | |
7881 | vmcs12->cr3_target_value0 == val) || | |
7882 | (vmcs12->cr3_target_count >= 2 && | |
7883 | vmcs12->cr3_target_value1 == val) || | |
7884 | (vmcs12->cr3_target_count >= 3 && | |
7885 | vmcs12->cr3_target_value2 == val) || | |
7886 | (vmcs12->cr3_target_count >= 4 && | |
7887 | vmcs12->cr3_target_value3 == val)) | |
1d804d07 | 7888 | return false; |
644d711a | 7889 | if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING)) |
1d804d07 | 7890 | return true; |
644d711a NHE |
7891 | break; |
7892 | case 4: | |
7893 | if (vmcs12->cr4_guest_host_mask & | |
7894 | (vmcs12->cr4_read_shadow ^ val)) | |
1d804d07 | 7895 | return true; |
644d711a NHE |
7896 | break; |
7897 | case 8: | |
7898 | if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING)) | |
1d804d07 | 7899 | return true; |
644d711a NHE |
7900 | break; |
7901 | } | |
7902 | break; | |
7903 | case 2: /* clts */ | |
7904 | if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) && | |
7905 | (vmcs12->cr0_read_shadow & X86_CR0_TS)) | |
1d804d07 | 7906 | return true; |
644d711a NHE |
7907 | break; |
7908 | case 1: /* mov from cr */ | |
7909 | switch (cr) { | |
7910 | case 3: | |
7911 | if (vmcs12->cpu_based_vm_exec_control & | |
7912 | CPU_BASED_CR3_STORE_EXITING) | |
1d804d07 | 7913 | return true; |
644d711a NHE |
7914 | break; |
7915 | case 8: | |
7916 | if (vmcs12->cpu_based_vm_exec_control & | |
7917 | CPU_BASED_CR8_STORE_EXITING) | |
1d804d07 | 7918 | return true; |
644d711a NHE |
7919 | break; |
7920 | } | |
7921 | break; | |
7922 | case 3: /* lmsw */ | |
7923 | /* | |
7924 | * lmsw can change bits 1..3 of cr0, and only set bit 0 of | |
7925 | * cr0. Other attempted changes are ignored, with no exit. | |
7926 | */ | |
7927 | if (vmcs12->cr0_guest_host_mask & 0xe & | |
7928 | (val ^ vmcs12->cr0_read_shadow)) | |
1d804d07 | 7929 | return true; |
644d711a NHE |
7930 | if ((vmcs12->cr0_guest_host_mask & 0x1) && |
7931 | !(vmcs12->cr0_read_shadow & 0x1) && | |
7932 | (val & 0x1)) | |
1d804d07 | 7933 | return true; |
644d711a NHE |
7934 | break; |
7935 | } | |
1d804d07 | 7936 | return false; |
644d711a NHE |
7937 | } |
7938 | ||
7939 | /* | |
7940 | * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we | |
7941 | * should handle it ourselves in L0 (and then continue L2). Only call this | |
7942 | * when in is_guest_mode (L2). | |
7943 | */ | |
7944 | static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu) | |
7945 | { | |
644d711a NHE |
7946 | u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
7947 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7948 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
957c897e | 7949 | u32 exit_reason = vmx->exit_reason; |
644d711a | 7950 | |
542060ea JK |
7951 | trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason, |
7952 | vmcs_readl(EXIT_QUALIFICATION), | |
7953 | vmx->idt_vectoring_info, | |
7954 | intr_info, | |
7955 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
7956 | KVM_ISA_VMX); | |
7957 | ||
644d711a | 7958 | if (vmx->nested.nested_run_pending) |
1d804d07 | 7959 | return false; |
644d711a NHE |
7960 | |
7961 | if (unlikely(vmx->fail)) { | |
bd80158a JK |
7962 | pr_info_ratelimited("%s failed vm entry %x\n", __func__, |
7963 | vmcs_read32(VM_INSTRUCTION_ERROR)); | |
1d804d07 | 7964 | return true; |
644d711a NHE |
7965 | } |
7966 | ||
7967 | switch (exit_reason) { | |
7968 | case EXIT_REASON_EXCEPTION_NMI: | |
7969 | if (!is_exception(intr_info)) | |
1d804d07 | 7970 | return false; |
644d711a NHE |
7971 | else if (is_page_fault(intr_info)) |
7972 | return enable_ept; | |
e504c909 | 7973 | else if (is_no_device(intr_info) && |
ccf9844e | 7974 | !(vmcs12->guest_cr0 & X86_CR0_TS)) |
1d804d07 | 7975 | return false; |
6f05485d JK |
7976 | else if (is_debug(intr_info) && |
7977 | vcpu->guest_debug & | |
7978 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
7979 | return false; | |
7980 | else if (is_breakpoint(intr_info) && | |
7981 | vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) | |
7982 | return false; | |
644d711a NHE |
7983 | return vmcs12->exception_bitmap & |
7984 | (1u << (intr_info & INTR_INFO_VECTOR_MASK)); | |
7985 | case EXIT_REASON_EXTERNAL_INTERRUPT: | |
1d804d07 | 7986 | return false; |
644d711a | 7987 | case EXIT_REASON_TRIPLE_FAULT: |
1d804d07 | 7988 | return true; |
644d711a | 7989 | case EXIT_REASON_PENDING_INTERRUPT: |
3b656cf7 | 7990 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING); |
644d711a | 7991 | case EXIT_REASON_NMI_WINDOW: |
3b656cf7 | 7992 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING); |
644d711a | 7993 | case EXIT_REASON_TASK_SWITCH: |
1d804d07 | 7994 | return true; |
644d711a | 7995 | case EXIT_REASON_CPUID: |
bc613494 | 7996 | if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa) |
1d804d07 JP |
7997 | return false; |
7998 | return true; | |
644d711a NHE |
7999 | case EXIT_REASON_HLT: |
8000 | return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING); | |
8001 | case EXIT_REASON_INVD: | |
1d804d07 | 8002 | return true; |
644d711a NHE |
8003 | case EXIT_REASON_INVLPG: |
8004 | return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); | |
8005 | case EXIT_REASON_RDPMC: | |
8006 | return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING); | |
b3a2a907 | 8007 | case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP: |
644d711a NHE |
8008 | return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING); |
8009 | case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR: | |
8010 | case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD: | |
8011 | case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD: | |
8012 | case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE: | |
8013 | case EXIT_REASON_VMOFF: case EXIT_REASON_VMON: | |
a642fc30 | 8014 | case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID: |
644d711a NHE |
8015 | /* |
8016 | * VMX instructions trap unconditionally. This allows L1 to | |
8017 | * emulate them for its L2 guest, i.e., allows 3-level nesting! | |
8018 | */ | |
1d804d07 | 8019 | return true; |
644d711a NHE |
8020 | case EXIT_REASON_CR_ACCESS: |
8021 | return nested_vmx_exit_handled_cr(vcpu, vmcs12); | |
8022 | case EXIT_REASON_DR_ACCESS: | |
8023 | return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING); | |
8024 | case EXIT_REASON_IO_INSTRUCTION: | |
908a7bdd | 8025 | return nested_vmx_exit_handled_io(vcpu, vmcs12); |
644d711a NHE |
8026 | case EXIT_REASON_MSR_READ: |
8027 | case EXIT_REASON_MSR_WRITE: | |
8028 | return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason); | |
8029 | case EXIT_REASON_INVALID_STATE: | |
1d804d07 | 8030 | return true; |
644d711a NHE |
8031 | case EXIT_REASON_MWAIT_INSTRUCTION: |
8032 | return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING); | |
5f3d45e7 MD |
8033 | case EXIT_REASON_MONITOR_TRAP_FLAG: |
8034 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG); | |
644d711a NHE |
8035 | case EXIT_REASON_MONITOR_INSTRUCTION: |
8036 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING); | |
8037 | case EXIT_REASON_PAUSE_INSTRUCTION: | |
8038 | return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) || | |
8039 | nested_cpu_has2(vmcs12, | |
8040 | SECONDARY_EXEC_PAUSE_LOOP_EXITING); | |
8041 | case EXIT_REASON_MCE_DURING_VMENTRY: | |
1d804d07 | 8042 | return false; |
644d711a | 8043 | case EXIT_REASON_TPR_BELOW_THRESHOLD: |
a7c0b07d | 8044 | return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW); |
644d711a NHE |
8045 | case EXIT_REASON_APIC_ACCESS: |
8046 | return nested_cpu_has2(vmcs12, | |
8047 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
82f0dd4b | 8048 | case EXIT_REASON_APIC_WRITE: |
608406e2 WV |
8049 | case EXIT_REASON_EOI_INDUCED: |
8050 | /* apic_write and eoi_induced should exit unconditionally. */ | |
1d804d07 | 8051 | return true; |
644d711a | 8052 | case EXIT_REASON_EPT_VIOLATION: |
2b1be677 NHE |
8053 | /* |
8054 | * L0 always deals with the EPT violation. If nested EPT is | |
8055 | * used, and the nested mmu code discovers that the address is | |
8056 | * missing in the guest EPT table (EPT12), the EPT violation | |
8057 | * will be injected with nested_ept_inject_page_fault() | |
8058 | */ | |
1d804d07 | 8059 | return false; |
644d711a | 8060 | case EXIT_REASON_EPT_MISCONFIG: |
2b1be677 NHE |
8061 | /* |
8062 | * L2 never uses directly L1's EPT, but rather L0's own EPT | |
8063 | * table (shadow on EPT) or a merged EPT table that L0 built | |
8064 | * (EPT on EPT). So any problems with the structure of the | |
8065 | * table is L0's fault. | |
8066 | */ | |
1d804d07 | 8067 | return false; |
644d711a NHE |
8068 | case EXIT_REASON_WBINVD: |
8069 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING); | |
8070 | case EXIT_REASON_XSETBV: | |
1d804d07 | 8071 | return true; |
81dc01f7 WL |
8072 | case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS: |
8073 | /* | |
8074 | * This should never happen, since it is not possible to | |
8075 | * set XSS to a non-zero value---neither in L1 nor in L2. | |
8076 | * If if it were, XSS would have to be checked against | |
8077 | * the XSS exit bitmap in vmcs12. | |
8078 | */ | |
8079 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES); | |
8b3e34e4 XG |
8080 | case EXIT_REASON_PCOMMIT: |
8081 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT); | |
55123e3c WL |
8082 | case EXIT_REASON_PREEMPTION_TIMER: |
8083 | return false; | |
644d711a | 8084 | default: |
1d804d07 | 8085 | return true; |
644d711a NHE |
8086 | } |
8087 | } | |
8088 | ||
586f9607 AK |
8089 | static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
8090 | { | |
8091 | *info1 = vmcs_readl(EXIT_QUALIFICATION); | |
8092 | *info2 = vmcs_read32(VM_EXIT_INTR_INFO); | |
8093 | } | |
8094 | ||
a3eaa864 | 8095 | static int vmx_create_pml_buffer(struct vcpu_vmx *vmx) |
843e4330 KH |
8096 | { |
8097 | struct page *pml_pg; | |
843e4330 KH |
8098 | |
8099 | pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
8100 | if (!pml_pg) | |
8101 | return -ENOMEM; | |
8102 | ||
8103 | vmx->pml_pg = pml_pg; | |
8104 | ||
8105 | vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); | |
8106 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
8107 | ||
843e4330 KH |
8108 | return 0; |
8109 | } | |
8110 | ||
a3eaa864 | 8111 | static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) |
843e4330 | 8112 | { |
a3eaa864 KH |
8113 | if (vmx->pml_pg) { |
8114 | __free_page(vmx->pml_pg); | |
8115 | vmx->pml_pg = NULL; | |
8116 | } | |
843e4330 KH |
8117 | } |
8118 | ||
54bf36aa | 8119 | static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) |
843e4330 | 8120 | { |
54bf36aa | 8121 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
843e4330 KH |
8122 | u64 *pml_buf; |
8123 | u16 pml_idx; | |
8124 | ||
8125 | pml_idx = vmcs_read16(GUEST_PML_INDEX); | |
8126 | ||
8127 | /* Do nothing if PML buffer is empty */ | |
8128 | if (pml_idx == (PML_ENTITY_NUM - 1)) | |
8129 | return; | |
8130 | ||
8131 | /* PML index always points to next available PML buffer entity */ | |
8132 | if (pml_idx >= PML_ENTITY_NUM) | |
8133 | pml_idx = 0; | |
8134 | else | |
8135 | pml_idx++; | |
8136 | ||
8137 | pml_buf = page_address(vmx->pml_pg); | |
8138 | for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { | |
8139 | u64 gpa; | |
8140 | ||
8141 | gpa = pml_buf[pml_idx]; | |
8142 | WARN_ON(gpa & (PAGE_SIZE - 1)); | |
54bf36aa | 8143 | kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); |
843e4330 KH |
8144 | } |
8145 | ||
8146 | /* reset PML index */ | |
8147 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
8148 | } | |
8149 | ||
8150 | /* | |
8151 | * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. | |
8152 | * Called before reporting dirty_bitmap to userspace. | |
8153 | */ | |
8154 | static void kvm_flush_pml_buffers(struct kvm *kvm) | |
8155 | { | |
8156 | int i; | |
8157 | struct kvm_vcpu *vcpu; | |
8158 | /* | |
8159 | * We only need to kick vcpu out of guest mode here, as PML buffer | |
8160 | * is flushed at beginning of all VMEXITs, and it's obvious that only | |
8161 | * vcpus running in guest are possible to have unflushed GPAs in PML | |
8162 | * buffer. | |
8163 | */ | |
8164 | kvm_for_each_vcpu(i, vcpu, kvm) | |
8165 | kvm_vcpu_kick(vcpu); | |
8166 | } | |
8167 | ||
4eb64dce PB |
8168 | static void vmx_dump_sel(char *name, uint32_t sel) |
8169 | { | |
8170 | pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", | |
8171 | name, vmcs_read32(sel), | |
8172 | vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), | |
8173 | vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), | |
8174 | vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); | |
8175 | } | |
8176 | ||
8177 | static void vmx_dump_dtsel(char *name, uint32_t limit) | |
8178 | { | |
8179 | pr_err("%s limit=0x%08x, base=0x%016lx\n", | |
8180 | name, vmcs_read32(limit), | |
8181 | vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); | |
8182 | } | |
8183 | ||
8184 | static void dump_vmcs(void) | |
8185 | { | |
8186 | u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); | |
8187 | u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); | |
8188 | u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
8189 | u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); | |
8190 | u32 secondary_exec_control = 0; | |
8191 | unsigned long cr4 = vmcs_readl(GUEST_CR4); | |
f3531054 | 8192 | u64 efer = vmcs_read64(GUEST_IA32_EFER); |
4eb64dce PB |
8193 | int i, n; |
8194 | ||
8195 | if (cpu_has_secondary_exec_ctrls()) | |
8196 | secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
8197 | ||
8198 | pr_err("*** Guest State ***\n"); | |
8199 | pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
8200 | vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), | |
8201 | vmcs_readl(CR0_GUEST_HOST_MASK)); | |
8202 | pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
8203 | cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); | |
8204 | pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); | |
8205 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && | |
8206 | (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) | |
8207 | { | |
845c5b40 PB |
8208 | pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", |
8209 | vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); | |
8210 | pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", | |
8211 | vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); | |
4eb64dce PB |
8212 | } |
8213 | pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", | |
8214 | vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); | |
8215 | pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", | |
8216 | vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); | |
8217 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
8218 | vmcs_readl(GUEST_SYSENTER_ESP), | |
8219 | vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); | |
8220 | vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); | |
8221 | vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); | |
8222 | vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); | |
8223 | vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); | |
8224 | vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); | |
8225 | vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); | |
8226 | vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); | |
8227 | vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); | |
8228 | vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); | |
8229 | vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); | |
8230 | if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || | |
8231 | (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) | |
845c5b40 PB |
8232 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", |
8233 | efer, vmcs_read64(GUEST_IA32_PAT)); | |
8234 | pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", | |
8235 | vmcs_read64(GUEST_IA32_DEBUGCTL), | |
4eb64dce PB |
8236 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); |
8237 | if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
845c5b40 PB |
8238 | pr_err("PerfGlobCtl = 0x%016llx\n", |
8239 | vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); | |
4eb64dce | 8240 | if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) |
845c5b40 | 8241 | pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); |
4eb64dce PB |
8242 | pr_err("Interruptibility = %08x ActivityState = %08x\n", |
8243 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), | |
8244 | vmcs_read32(GUEST_ACTIVITY_STATE)); | |
8245 | if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) | |
8246 | pr_err("InterruptStatus = %04x\n", | |
8247 | vmcs_read16(GUEST_INTR_STATUS)); | |
8248 | ||
8249 | pr_err("*** Host State ***\n"); | |
8250 | pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", | |
8251 | vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); | |
8252 | pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", | |
8253 | vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), | |
8254 | vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), | |
8255 | vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), | |
8256 | vmcs_read16(HOST_TR_SELECTOR)); | |
8257 | pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", | |
8258 | vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), | |
8259 | vmcs_readl(HOST_TR_BASE)); | |
8260 | pr_err("GDTBase=%016lx IDTBase=%016lx\n", | |
8261 | vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); | |
8262 | pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", | |
8263 | vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), | |
8264 | vmcs_readl(HOST_CR4)); | |
8265 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
8266 | vmcs_readl(HOST_IA32_SYSENTER_ESP), | |
8267 | vmcs_read32(HOST_IA32_SYSENTER_CS), | |
8268 | vmcs_readl(HOST_IA32_SYSENTER_EIP)); | |
8269 | if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) | |
845c5b40 PB |
8270 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", |
8271 | vmcs_read64(HOST_IA32_EFER), | |
8272 | vmcs_read64(HOST_IA32_PAT)); | |
4eb64dce | 8273 | if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) |
845c5b40 PB |
8274 | pr_err("PerfGlobCtl = 0x%016llx\n", |
8275 | vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); | |
4eb64dce PB |
8276 | |
8277 | pr_err("*** Control State ***\n"); | |
8278 | pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", | |
8279 | pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); | |
8280 | pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); | |
8281 | pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", | |
8282 | vmcs_read32(EXCEPTION_BITMAP), | |
8283 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), | |
8284 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); | |
8285 | pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", | |
8286 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), | |
8287 | vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), | |
8288 | vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); | |
8289 | pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", | |
8290 | vmcs_read32(VM_EXIT_INTR_INFO), | |
8291 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
8292 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); | |
8293 | pr_err(" reason=%08x qualification=%016lx\n", | |
8294 | vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); | |
8295 | pr_err("IDTVectoring: info=%08x errcode=%08x\n", | |
8296 | vmcs_read32(IDT_VECTORING_INFO_FIELD), | |
8297 | vmcs_read32(IDT_VECTORING_ERROR_CODE)); | |
845c5b40 | 8298 | pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); |
8cfe9866 | 8299 | if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) |
845c5b40 PB |
8300 | pr_err("TSC Multiplier = 0x%016llx\n", |
8301 | vmcs_read64(TSC_MULTIPLIER)); | |
4eb64dce PB |
8302 | if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) |
8303 | pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); | |
8304 | if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) | |
8305 | pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); | |
8306 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) | |
845c5b40 | 8307 | pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); |
4eb64dce PB |
8308 | n = vmcs_read32(CR3_TARGET_COUNT); |
8309 | for (i = 0; i + 1 < n; i += 4) | |
8310 | pr_err("CR3 target%u=%016lx target%u=%016lx\n", | |
8311 | i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), | |
8312 | i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); | |
8313 | if (i < n) | |
8314 | pr_err("CR3 target%u=%016lx\n", | |
8315 | i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); | |
8316 | if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) | |
8317 | pr_err("PLE Gap=%08x Window=%08x\n", | |
8318 | vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); | |
8319 | if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) | |
8320 | pr_err("Virtual processor ID = 0x%04x\n", | |
8321 | vmcs_read16(VIRTUAL_PROCESSOR_ID)); | |
8322 | } | |
8323 | ||
6aa8b732 AK |
8324 | /* |
8325 | * The guest has exited. See if we can fix it or if we need userspace | |
8326 | * assistance. | |
8327 | */ | |
851ba692 | 8328 | static int vmx_handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 8329 | { |
29bd8a78 | 8330 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
a0861c02 | 8331 | u32 exit_reason = vmx->exit_reason; |
1155f76a | 8332 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 8333 | |
8b89fe1f PB |
8334 | trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); |
8335 | ||
843e4330 KH |
8336 | /* |
8337 | * Flush logged GPAs PML buffer, this will make dirty_bitmap more | |
8338 | * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before | |
8339 | * querying dirty_bitmap, we only need to kick all vcpus out of guest | |
8340 | * mode as if vcpus is in root mode, the PML buffer must has been | |
8341 | * flushed already. | |
8342 | */ | |
8343 | if (enable_pml) | |
54bf36aa | 8344 | vmx_flush_pml_buffer(vcpu); |
843e4330 | 8345 | |
80ced186 | 8346 | /* If guest state is invalid, start emulating */ |
14168786 | 8347 | if (vmx->emulation_required) |
80ced186 | 8348 | return handle_invalid_guest_state(vcpu); |
1d5a4d9b | 8349 | |
644d711a | 8350 | if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) { |
533558bc JK |
8351 | nested_vmx_vmexit(vcpu, exit_reason, |
8352 | vmcs_read32(VM_EXIT_INTR_INFO), | |
8353 | vmcs_readl(EXIT_QUALIFICATION)); | |
644d711a NHE |
8354 | return 1; |
8355 | } | |
8356 | ||
5120702e | 8357 | if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { |
4eb64dce | 8358 | dump_vmcs(); |
5120702e MG |
8359 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
8360 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
8361 | = exit_reason; | |
8362 | return 0; | |
8363 | } | |
8364 | ||
29bd8a78 | 8365 | if (unlikely(vmx->fail)) { |
851ba692 AK |
8366 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
8367 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
29bd8a78 AK |
8368 | = vmcs_read32(VM_INSTRUCTION_ERROR); |
8369 | return 0; | |
8370 | } | |
6aa8b732 | 8371 | |
b9bf6882 XG |
8372 | /* |
8373 | * Note: | |
8374 | * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by | |
8375 | * delivery event since it indicates guest is accessing MMIO. | |
8376 | * The vm-exit can be triggered again after return to guest that | |
8377 | * will cause infinite loop. | |
8378 | */ | |
d77c26fc | 8379 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c | 8380 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
60637aac | 8381 | exit_reason != EXIT_REASON_EPT_VIOLATION && |
b9bf6882 XG |
8382 | exit_reason != EXIT_REASON_TASK_SWITCH)) { |
8383 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
8384 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; | |
8385 | vcpu->run->internal.ndata = 2; | |
8386 | vcpu->run->internal.data[0] = vectoring_info; | |
8387 | vcpu->run->internal.data[1] = exit_reason; | |
8388 | return 0; | |
8389 | } | |
3b86cd99 | 8390 | |
644d711a NHE |
8391 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked && |
8392 | !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis( | |
f5c4368f | 8393 | get_vmcs12(vcpu))))) { |
c4282df9 | 8394 | if (vmx_interrupt_allowed(vcpu)) { |
3b86cd99 | 8395 | vmx->soft_vnmi_blocked = 0; |
3b86cd99 | 8396 | } else if (vmx->vnmi_blocked_time > 1000000000LL && |
4531220b | 8397 | vcpu->arch.nmi_pending) { |
3b86cd99 JK |
8398 | /* |
8399 | * This CPU don't support us in finding the end of an | |
8400 | * NMI-blocked window if the guest runs with IRQs | |
8401 | * disabled. So we pull the trigger after 1 s of | |
8402 | * futile waiting, but inform the user about this. | |
8403 | */ | |
8404 | printk(KERN_WARNING "%s: Breaking out of NMI-blocked " | |
8405 | "state on VCPU %d after 1 s timeout\n", | |
8406 | __func__, vcpu->vcpu_id); | |
8407 | vmx->soft_vnmi_blocked = 0; | |
3b86cd99 | 8408 | } |
3b86cd99 JK |
8409 | } |
8410 | ||
6aa8b732 AK |
8411 | if (exit_reason < kvm_vmx_max_exit_handlers |
8412 | && kvm_vmx_exit_handlers[exit_reason]) | |
851ba692 | 8413 | return kvm_vmx_exit_handlers[exit_reason](vcpu); |
6aa8b732 | 8414 | else { |
2bc19dc3 MT |
8415 | WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason); |
8416 | kvm_queue_exception(vcpu, UD_VECTOR); | |
8417 | return 1; | |
6aa8b732 | 8418 | } |
6aa8b732 AK |
8419 | } |
8420 | ||
95ba8273 | 8421 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
6e5d865c | 8422 | { |
a7c0b07d WL |
8423 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
8424 | ||
8425 | if (is_guest_mode(vcpu) && | |
8426 | nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
8427 | return; | |
8428 | ||
95ba8273 | 8429 | if (irr == -1 || tpr < irr) { |
6e5d865c YS |
8430 | vmcs_write32(TPR_THRESHOLD, 0); |
8431 | return; | |
8432 | } | |
8433 | ||
95ba8273 | 8434 | vmcs_write32(TPR_THRESHOLD, irr); |
6e5d865c YS |
8435 | } |
8436 | ||
8d14695f YZ |
8437 | static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) |
8438 | { | |
8439 | u32 sec_exec_control; | |
8440 | ||
8441 | /* | |
8442 | * There is not point to enable virtualize x2apic without enable | |
8443 | * apicv | |
8444 | */ | |
c7c9c56c | 8445 | if (!cpu_has_vmx_virtualize_x2apic_mode() || |
d62caabb | 8446 | !kvm_vcpu_apicv_active(vcpu)) |
8d14695f YZ |
8447 | return; |
8448 | ||
35754c98 | 8449 | if (!cpu_need_tpr_shadow(vcpu)) |
8d14695f YZ |
8450 | return; |
8451 | ||
8452 | sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
8453 | ||
8454 | if (set) { | |
8455 | sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
8456 | sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
8457 | } else { | |
8458 | sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
8459 | sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
8460 | } | |
8461 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control); | |
8462 | ||
8463 | vmx_set_msr_bitmap(vcpu); | |
8464 | } | |
8465 | ||
38b99173 TC |
8466 | static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) |
8467 | { | |
8468 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8469 | ||
8470 | /* | |
8471 | * Currently we do not handle the nested case where L2 has an | |
8472 | * APIC access page of its own; that page is still pinned. | |
8473 | * Hence, we skip the case where the VCPU is in guest mode _and_ | |
8474 | * L1 prepared an APIC access page for L2. | |
8475 | * | |
8476 | * For the case where L1 and L2 share the same APIC access page | |
8477 | * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear | |
8478 | * in the vmcs12), this function will only update either the vmcs01 | |
8479 | * or the vmcs02. If the former, the vmcs02 will be updated by | |
8480 | * prepare_vmcs02. If the latter, the vmcs01 will be updated in | |
8481 | * the next L2->L1 exit. | |
8482 | */ | |
8483 | if (!is_guest_mode(vcpu) || | |
4f2777bc | 8484 | !nested_cpu_has2(get_vmcs12(&vmx->vcpu), |
38b99173 TC |
8485 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) |
8486 | vmcs_write64(APIC_ACCESS_ADDR, hpa); | |
8487 | } | |
8488 | ||
67c9dddc | 8489 | static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) |
c7c9c56c YZ |
8490 | { |
8491 | u16 status; | |
8492 | u8 old; | |
8493 | ||
67c9dddc PB |
8494 | if (max_isr == -1) |
8495 | max_isr = 0; | |
c7c9c56c YZ |
8496 | |
8497 | status = vmcs_read16(GUEST_INTR_STATUS); | |
8498 | old = status >> 8; | |
67c9dddc | 8499 | if (max_isr != old) { |
c7c9c56c | 8500 | status &= 0xff; |
67c9dddc | 8501 | status |= max_isr << 8; |
c7c9c56c YZ |
8502 | vmcs_write16(GUEST_INTR_STATUS, status); |
8503 | } | |
8504 | } | |
8505 | ||
8506 | static void vmx_set_rvi(int vector) | |
8507 | { | |
8508 | u16 status; | |
8509 | u8 old; | |
8510 | ||
4114c27d WW |
8511 | if (vector == -1) |
8512 | vector = 0; | |
8513 | ||
c7c9c56c YZ |
8514 | status = vmcs_read16(GUEST_INTR_STATUS); |
8515 | old = (u8)status & 0xff; | |
8516 | if ((u8)vector != old) { | |
8517 | status &= ~0xff; | |
8518 | status |= (u8)vector; | |
8519 | vmcs_write16(GUEST_INTR_STATUS, status); | |
8520 | } | |
8521 | } | |
8522 | ||
8523 | static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) | |
8524 | { | |
4114c27d WW |
8525 | if (!is_guest_mode(vcpu)) { |
8526 | vmx_set_rvi(max_irr); | |
8527 | return; | |
8528 | } | |
8529 | ||
c7c9c56c YZ |
8530 | if (max_irr == -1) |
8531 | return; | |
8532 | ||
963fee16 | 8533 | /* |
4114c27d WW |
8534 | * In guest mode. If a vmexit is needed, vmx_check_nested_events |
8535 | * handles it. | |
963fee16 | 8536 | */ |
4114c27d | 8537 | if (nested_exit_on_intr(vcpu)) |
963fee16 WL |
8538 | return; |
8539 | ||
963fee16 | 8540 | /* |
4114c27d | 8541 | * Else, fall back to pre-APICv interrupt injection since L2 |
963fee16 WL |
8542 | * is run without virtual interrupt delivery. |
8543 | */ | |
8544 | if (!kvm_event_needs_reinjection(vcpu) && | |
8545 | vmx_interrupt_allowed(vcpu)) { | |
8546 | kvm_queue_interrupt(vcpu, max_irr, false); | |
8547 | vmx_inject_irq(vcpu); | |
8548 | } | |
c7c9c56c YZ |
8549 | } |
8550 | ||
6308630b | 8551 | static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
c7c9c56c | 8552 | { |
d62caabb | 8553 | if (!kvm_vcpu_apicv_active(vcpu)) |
3d81bc7e YZ |
8554 | return; |
8555 | ||
c7c9c56c YZ |
8556 | vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); |
8557 | vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); | |
8558 | vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); | |
8559 | vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); | |
8560 | } | |
8561 | ||
51aa01d1 | 8562 | static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx) |
cf393f75 | 8563 | { |
00eba012 AK |
8564 | u32 exit_intr_info; |
8565 | ||
8566 | if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY | |
8567 | || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)) | |
8568 | return; | |
8569 | ||
c5ca8e57 | 8570 | vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
00eba012 | 8571 | exit_intr_info = vmx->exit_intr_info; |
a0861c02 AK |
8572 | |
8573 | /* Handle machine checks before interrupts are enabled */ | |
00eba012 | 8574 | if (is_machine_check(exit_intr_info)) |
a0861c02 AK |
8575 | kvm_machine_check(); |
8576 | ||
20f65983 | 8577 | /* We need to handle NMIs before interrupts are enabled */ |
00eba012 | 8578 | if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR && |
ff9d07a0 ZY |
8579 | (exit_intr_info & INTR_INFO_VALID_MASK)) { |
8580 | kvm_before_handle_nmi(&vmx->vcpu); | |
20f65983 | 8581 | asm("int $2"); |
ff9d07a0 ZY |
8582 | kvm_after_handle_nmi(&vmx->vcpu); |
8583 | } | |
51aa01d1 | 8584 | } |
20f65983 | 8585 | |
a547c6db YZ |
8586 | static void vmx_handle_external_intr(struct kvm_vcpu *vcpu) |
8587 | { | |
8588 | u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
3f62de5f | 8589 | register void *__sp asm(_ASM_SP); |
a547c6db YZ |
8590 | |
8591 | /* | |
8592 | * If external interrupt exists, IF bit is set in rflags/eflags on the | |
8593 | * interrupt stack frame, and interrupt will be enabled on a return | |
8594 | * from interrupt handler. | |
8595 | */ | |
8596 | if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK)) | |
8597 | == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) { | |
8598 | unsigned int vector; | |
8599 | unsigned long entry; | |
8600 | gate_desc *desc; | |
8601 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8602 | #ifdef CONFIG_X86_64 | |
8603 | unsigned long tmp; | |
8604 | #endif | |
8605 | ||
8606 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
8607 | desc = (gate_desc *)vmx->host_idt_base + vector; | |
8608 | entry = gate_offset(*desc); | |
8609 | asm volatile( | |
8610 | #ifdef CONFIG_X86_64 | |
8611 | "mov %%" _ASM_SP ", %[sp]\n\t" | |
8612 | "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" | |
8613 | "push $%c[ss]\n\t" | |
8614 | "push %[sp]\n\t" | |
8615 | #endif | |
8616 | "pushf\n\t" | |
a547c6db YZ |
8617 | __ASM_SIZE(push) " $%c[cs]\n\t" |
8618 | "call *%[entry]\n\t" | |
8619 | : | |
8620 | #ifdef CONFIG_X86_64 | |
3f62de5f | 8621 | [sp]"=&r"(tmp), |
a547c6db | 8622 | #endif |
3f62de5f | 8623 | "+r"(__sp) |
a547c6db YZ |
8624 | : |
8625 | [entry]"r"(entry), | |
8626 | [ss]"i"(__KERNEL_DS), | |
8627 | [cs]"i"(__KERNEL_CS) | |
8628 | ); | |
f2485b3e | 8629 | } |
a547c6db YZ |
8630 | } |
8631 | ||
6d396b55 PB |
8632 | static bool vmx_has_high_real_mode_segbase(void) |
8633 | { | |
8634 | return enable_unrestricted_guest || emulate_invalid_guest_state; | |
8635 | } | |
8636 | ||
da8999d3 LJ |
8637 | static bool vmx_mpx_supported(void) |
8638 | { | |
8639 | return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) && | |
8640 | (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS); | |
8641 | } | |
8642 | ||
55412b2e WL |
8643 | static bool vmx_xsaves_supported(void) |
8644 | { | |
8645 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
8646 | SECONDARY_EXEC_XSAVES; | |
8647 | } | |
8648 | ||
51aa01d1 AK |
8649 | static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) |
8650 | { | |
c5ca8e57 | 8651 | u32 exit_intr_info; |
51aa01d1 AK |
8652 | bool unblock_nmi; |
8653 | u8 vector; | |
8654 | bool idtv_info_valid; | |
8655 | ||
8656 | idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
20f65983 | 8657 | |
cf393f75 | 8658 | if (cpu_has_virtual_nmis()) { |
9d58b931 AK |
8659 | if (vmx->nmi_known_unmasked) |
8660 | return; | |
c5ca8e57 AK |
8661 | /* |
8662 | * Can't use vmx->exit_intr_info since we're not sure what | |
8663 | * the exit reason is. | |
8664 | */ | |
8665 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
cf393f75 AK |
8666 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; |
8667 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
8668 | /* | |
7b4a25cb | 8669 | * SDM 3: 27.7.1.2 (September 2008) |
cf393f75 AK |
8670 | * Re-set bit "block by NMI" before VM entry if vmexit caused by |
8671 | * a guest IRET fault. | |
7b4a25cb GN |
8672 | * SDM 3: 23.2.2 (September 2008) |
8673 | * Bit 12 is undefined in any of the following cases: | |
8674 | * If the VM exit sets the valid bit in the IDT-vectoring | |
8675 | * information field. | |
8676 | * If the VM exit is due to a double fault. | |
cf393f75 | 8677 | */ |
7b4a25cb GN |
8678 | if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && |
8679 | vector != DF_VECTOR && !idtv_info_valid) | |
cf393f75 AK |
8680 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, |
8681 | GUEST_INTR_STATE_NMI); | |
9d58b931 AK |
8682 | else |
8683 | vmx->nmi_known_unmasked = | |
8684 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) | |
8685 | & GUEST_INTR_STATE_NMI); | |
3b86cd99 JK |
8686 | } else if (unlikely(vmx->soft_vnmi_blocked)) |
8687 | vmx->vnmi_blocked_time += | |
8688 | ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time)); | |
51aa01d1 AK |
8689 | } |
8690 | ||
3ab66e8a | 8691 | static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, |
83422e17 AK |
8692 | u32 idt_vectoring_info, |
8693 | int instr_len_field, | |
8694 | int error_code_field) | |
51aa01d1 | 8695 | { |
51aa01d1 AK |
8696 | u8 vector; |
8697 | int type; | |
8698 | bool idtv_info_valid; | |
8699 | ||
8700 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
668f612f | 8701 | |
3ab66e8a JK |
8702 | vcpu->arch.nmi_injected = false; |
8703 | kvm_clear_exception_queue(vcpu); | |
8704 | kvm_clear_interrupt_queue(vcpu); | |
37b96e98 GN |
8705 | |
8706 | if (!idtv_info_valid) | |
8707 | return; | |
8708 | ||
3ab66e8a | 8709 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3842d135 | 8710 | |
668f612f AK |
8711 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; |
8712 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | |
37b96e98 | 8713 | |
64a7ec06 | 8714 | switch (type) { |
37b96e98 | 8715 | case INTR_TYPE_NMI_INTR: |
3ab66e8a | 8716 | vcpu->arch.nmi_injected = true; |
668f612f | 8717 | /* |
7b4a25cb | 8718 | * SDM 3: 27.7.1.2 (September 2008) |
37b96e98 GN |
8719 | * Clear bit "block by NMI" before VM entry if a NMI |
8720 | * delivery faulted. | |
668f612f | 8721 | */ |
3ab66e8a | 8722 | vmx_set_nmi_mask(vcpu, false); |
37b96e98 | 8723 | break; |
37b96e98 | 8724 | case INTR_TYPE_SOFT_EXCEPTION: |
3ab66e8a | 8725 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f GN |
8726 | /* fall through */ |
8727 | case INTR_TYPE_HARD_EXCEPTION: | |
35920a35 | 8728 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { |
83422e17 | 8729 | u32 err = vmcs_read32(error_code_field); |
851eb667 | 8730 | kvm_requeue_exception_e(vcpu, vector, err); |
35920a35 | 8731 | } else |
851eb667 | 8732 | kvm_requeue_exception(vcpu, vector); |
37b96e98 | 8733 | break; |
66fd3f7f | 8734 | case INTR_TYPE_SOFT_INTR: |
3ab66e8a | 8735 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f | 8736 | /* fall through */ |
37b96e98 | 8737 | case INTR_TYPE_EXT_INTR: |
3ab66e8a | 8738 | kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); |
37b96e98 GN |
8739 | break; |
8740 | default: | |
8741 | break; | |
f7d9238f | 8742 | } |
cf393f75 AK |
8743 | } |
8744 | ||
83422e17 AK |
8745 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
8746 | { | |
3ab66e8a | 8747 | __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, |
83422e17 AK |
8748 | VM_EXIT_INSTRUCTION_LEN, |
8749 | IDT_VECTORING_ERROR_CODE); | |
8750 | } | |
8751 | ||
b463a6f7 AK |
8752 | static void vmx_cancel_injection(struct kvm_vcpu *vcpu) |
8753 | { | |
3ab66e8a | 8754 | __vmx_complete_interrupts(vcpu, |
b463a6f7 AK |
8755 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), |
8756 | VM_ENTRY_INSTRUCTION_LEN, | |
8757 | VM_ENTRY_EXCEPTION_ERROR_CODE); | |
8758 | ||
8759 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); | |
8760 | } | |
8761 | ||
d7cd9796 GN |
8762 | static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) |
8763 | { | |
8764 | int i, nr_msrs; | |
8765 | struct perf_guest_switch_msr *msrs; | |
8766 | ||
8767 | msrs = perf_guest_get_msrs(&nr_msrs); | |
8768 | ||
8769 | if (!msrs) | |
8770 | return; | |
8771 | ||
8772 | for (i = 0; i < nr_msrs; i++) | |
8773 | if (msrs[i].host == msrs[i].guest) | |
8774 | clear_atomic_switch_msr(vmx, msrs[i].msr); | |
8775 | else | |
8776 | add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, | |
8777 | msrs[i].host); | |
8778 | } | |
8779 | ||
64672c95 YJ |
8780 | void vmx_arm_hv_timer(struct kvm_vcpu *vcpu) |
8781 | { | |
8782 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8783 | u64 tscl; | |
8784 | u32 delta_tsc; | |
8785 | ||
8786 | if (vmx->hv_deadline_tsc == -1) | |
8787 | return; | |
8788 | ||
8789 | tscl = rdtsc(); | |
8790 | if (vmx->hv_deadline_tsc > tscl) | |
8791 | /* sure to be 32 bit only because checked on set_hv_timer */ | |
8792 | delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> | |
8793 | cpu_preemption_timer_multi); | |
8794 | else | |
8795 | delta_tsc = 0; | |
8796 | ||
8797 | vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); | |
8798 | } | |
8799 | ||
a3b5ba49 | 8800 | static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 8801 | { |
a2fa3e9f | 8802 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
d974baa3 | 8803 | unsigned long debugctlmsr, cr4; |
104f226b AK |
8804 | |
8805 | /* Record the guest's net vcpu time for enforced NMI injections. */ | |
8806 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) | |
8807 | vmx->entry_time = ktime_get(); | |
8808 | ||
8809 | /* Don't enter VMX if guest state is invalid, let the exit handler | |
8810 | start emulation until we arrive back to a valid state */ | |
14168786 | 8811 | if (vmx->emulation_required) |
104f226b AK |
8812 | return; |
8813 | ||
a7653ecd RK |
8814 | if (vmx->ple_window_dirty) { |
8815 | vmx->ple_window_dirty = false; | |
8816 | vmcs_write32(PLE_WINDOW, vmx->ple_window); | |
8817 | } | |
8818 | ||
012f83cb AG |
8819 | if (vmx->nested.sync_shadow_vmcs) { |
8820 | copy_vmcs12_to_shadow(vmx); | |
8821 | vmx->nested.sync_shadow_vmcs = false; | |
8822 | } | |
8823 | ||
104f226b AK |
8824 | if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) |
8825 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); | |
8826 | if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
8827 | vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); | |
8828 | ||
1e02ce4c | 8829 | cr4 = cr4_read_shadow(); |
d974baa3 AL |
8830 | if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) { |
8831 | vmcs_writel(HOST_CR4, cr4); | |
8832 | vmx->host_state.vmcs_host_cr4 = cr4; | |
8833 | } | |
8834 | ||
104f226b AK |
8835 | /* When single-stepping over STI and MOV SS, we must clear the |
8836 | * corresponding interruptibility bits in the guest state. Otherwise | |
8837 | * vmentry fails as it then expects bit 14 (BS) in pending debug | |
8838 | * exceptions being set, but that's not correct for the guest debugging | |
8839 | * case. */ | |
8840 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
8841 | vmx_set_interrupt_shadow(vcpu, 0); | |
8842 | ||
1be0e61c XG |
8843 | if (vmx->guest_pkru_valid) |
8844 | __write_pkru(vmx->guest_pkru); | |
8845 | ||
d7cd9796 | 8846 | atomic_switch_perf_msrs(vmx); |
2a7921b7 | 8847 | debugctlmsr = get_debugctlmsr(); |
d7cd9796 | 8848 | |
64672c95 YJ |
8849 | vmx_arm_hv_timer(vcpu); |
8850 | ||
d462b819 | 8851 | vmx->__launched = vmx->loaded_vmcs->launched; |
104f226b | 8852 | asm( |
6aa8b732 | 8853 | /* Store host registers */ |
b188c81f AK |
8854 | "push %%" _ASM_DX "; push %%" _ASM_BP ";" |
8855 | "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */ | |
8856 | "push %%" _ASM_CX " \n\t" | |
8857 | "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t" | |
313dbd49 | 8858 | "je 1f \n\t" |
b188c81f | 8859 | "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t" |
4ecac3fd | 8860 | __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t" |
313dbd49 | 8861 | "1: \n\t" |
d3edefc0 | 8862 | /* Reload cr2 if changed */ |
b188c81f AK |
8863 | "mov %c[cr2](%0), %%" _ASM_AX " \n\t" |
8864 | "mov %%cr2, %%" _ASM_DX " \n\t" | |
8865 | "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t" | |
d3edefc0 | 8866 | "je 2f \n\t" |
b188c81f | 8867 | "mov %%" _ASM_AX", %%cr2 \n\t" |
d3edefc0 | 8868 | "2: \n\t" |
6aa8b732 | 8869 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 8870 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 8871 | /* Load guest registers. Don't clobber flags. */ |
b188c81f AK |
8872 | "mov %c[rax](%0), %%" _ASM_AX " \n\t" |
8873 | "mov %c[rbx](%0), %%" _ASM_BX " \n\t" | |
8874 | "mov %c[rdx](%0), %%" _ASM_DX " \n\t" | |
8875 | "mov %c[rsi](%0), %%" _ASM_SI " \n\t" | |
8876 | "mov %c[rdi](%0), %%" _ASM_DI " \n\t" | |
8877 | "mov %c[rbp](%0), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 8878 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
8879 | "mov %c[r8](%0), %%r8 \n\t" |
8880 | "mov %c[r9](%0), %%r9 \n\t" | |
8881 | "mov %c[r10](%0), %%r10 \n\t" | |
8882 | "mov %c[r11](%0), %%r11 \n\t" | |
8883 | "mov %c[r12](%0), %%r12 \n\t" | |
8884 | "mov %c[r13](%0), %%r13 \n\t" | |
8885 | "mov %c[r14](%0), %%r14 \n\t" | |
8886 | "mov %c[r15](%0), %%r15 \n\t" | |
6aa8b732 | 8887 | #endif |
b188c81f | 8888 | "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */ |
c801949d | 8889 | |
6aa8b732 | 8890 | /* Enter guest mode */ |
83287ea4 | 8891 | "jne 1f \n\t" |
4ecac3fd | 8892 | __ex(ASM_VMX_VMLAUNCH) "\n\t" |
83287ea4 AK |
8893 | "jmp 2f \n\t" |
8894 | "1: " __ex(ASM_VMX_VMRESUME) "\n\t" | |
8895 | "2: " | |
6aa8b732 | 8896 | /* Save guest registers, load host registers, keep flags */ |
b188c81f | 8897 | "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t" |
40712fae | 8898 | "pop %0 \n\t" |
b188c81f AK |
8899 | "mov %%" _ASM_AX ", %c[rax](%0) \n\t" |
8900 | "mov %%" _ASM_BX ", %c[rbx](%0) \n\t" | |
8901 | __ASM_SIZE(pop) " %c[rcx](%0) \n\t" | |
8902 | "mov %%" _ASM_DX ", %c[rdx](%0) \n\t" | |
8903 | "mov %%" _ASM_SI ", %c[rsi](%0) \n\t" | |
8904 | "mov %%" _ASM_DI ", %c[rdi](%0) \n\t" | |
8905 | "mov %%" _ASM_BP ", %c[rbp](%0) \n\t" | |
05b3e0c2 | 8906 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
8907 | "mov %%r8, %c[r8](%0) \n\t" |
8908 | "mov %%r9, %c[r9](%0) \n\t" | |
8909 | "mov %%r10, %c[r10](%0) \n\t" | |
8910 | "mov %%r11, %c[r11](%0) \n\t" | |
8911 | "mov %%r12, %c[r12](%0) \n\t" | |
8912 | "mov %%r13, %c[r13](%0) \n\t" | |
8913 | "mov %%r14, %c[r14](%0) \n\t" | |
8914 | "mov %%r15, %c[r15](%0) \n\t" | |
6aa8b732 | 8915 | #endif |
b188c81f AK |
8916 | "mov %%cr2, %%" _ASM_AX " \n\t" |
8917 | "mov %%" _ASM_AX ", %c[cr2](%0) \n\t" | |
c801949d | 8918 | |
b188c81f | 8919 | "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t" |
e08aa78a | 8920 | "setbe %c[fail](%0) \n\t" |
83287ea4 AK |
8921 | ".pushsection .rodata \n\t" |
8922 | ".global vmx_return \n\t" | |
8923 | "vmx_return: " _ASM_PTR " 2b \n\t" | |
8924 | ".popsection" | |
e08aa78a | 8925 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), |
d462b819 | 8926 | [launched]"i"(offsetof(struct vcpu_vmx, __launched)), |
e08aa78a | 8927 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), |
313dbd49 | 8928 | [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)), |
ad312c7c ZX |
8929 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
8930 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
8931 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
8932 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
8933 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
8934 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
8935 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 8936 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
8937 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
8938 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
8939 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
8940 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
8941 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
8942 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
8943 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
8944 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 8945 | #endif |
40712fae AK |
8946 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)), |
8947 | [wordsize]"i"(sizeof(ulong)) | |
c2036300 LV |
8948 | : "cc", "memory" |
8949 | #ifdef CONFIG_X86_64 | |
b188c81f | 8950 | , "rax", "rbx", "rdi", "rsi" |
c2036300 | 8951 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
b188c81f AK |
8952 | #else |
8953 | , "eax", "ebx", "edi", "esi" | |
c2036300 LV |
8954 | #endif |
8955 | ); | |
6aa8b732 | 8956 | |
2a7921b7 GN |
8957 | /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ |
8958 | if (debugctlmsr) | |
8959 | update_debugctlmsr(debugctlmsr); | |
8960 | ||
aa67f609 AK |
8961 | #ifndef CONFIG_X86_64 |
8962 | /* | |
8963 | * The sysexit path does not restore ds/es, so we must set them to | |
8964 | * a reasonable value ourselves. | |
8965 | * | |
8966 | * We can't defer this to vmx_load_host_state() since that function | |
8967 | * may be executed in interrupt context, which saves and restore segments | |
8968 | * around it, nullifying its effect. | |
8969 | */ | |
8970 | loadsegment(ds, __USER_DS); | |
8971 | loadsegment(es, __USER_DS); | |
8972 | #endif | |
8973 | ||
6de4f3ad | 8974 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) |
6de12732 | 8975 | | (1 << VCPU_EXREG_RFLAGS) |
aff48baa | 8976 | | (1 << VCPU_EXREG_PDPTR) |
2fb92db1 | 8977 | | (1 << VCPU_EXREG_SEGMENTS) |
aff48baa | 8978 | | (1 << VCPU_EXREG_CR3)); |
5fdbf976 MT |
8979 | vcpu->arch.regs_dirty = 0; |
8980 | ||
1155f76a AK |
8981 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); |
8982 | ||
d462b819 | 8983 | vmx->loaded_vmcs->launched = 1; |
1b6269db | 8984 | |
51aa01d1 | 8985 | vmx->exit_reason = vmcs_read32(VM_EXIT_REASON); |
51aa01d1 | 8986 | |
1be0e61c XG |
8987 | /* |
8988 | * eager fpu is enabled if PKEY is supported and CR4 is switched | |
8989 | * back on host, so it is safe to read guest PKRU from current | |
8990 | * XSAVE. | |
8991 | */ | |
8992 | if (boot_cpu_has(X86_FEATURE_OSPKE)) { | |
8993 | vmx->guest_pkru = __read_pkru(); | |
8994 | if (vmx->guest_pkru != vmx->host_pkru) { | |
8995 | vmx->guest_pkru_valid = true; | |
8996 | __write_pkru(vmx->host_pkru); | |
8997 | } else | |
8998 | vmx->guest_pkru_valid = false; | |
8999 | } | |
9000 | ||
e0b890d3 GN |
9001 | /* |
9002 | * the KVM_REQ_EVENT optimization bit is only on for one entry, and if | |
9003 | * we did not inject a still-pending event to L1 now because of | |
9004 | * nested_run_pending, we need to re-enable this bit. | |
9005 | */ | |
9006 | if (vmx->nested.nested_run_pending) | |
9007 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
9008 | ||
9009 | vmx->nested.nested_run_pending = 0; | |
9010 | ||
51aa01d1 AK |
9011 | vmx_complete_atomic_exit(vmx); |
9012 | vmx_recover_nmi_blocking(vmx); | |
cf393f75 | 9013 | vmx_complete_interrupts(vmx); |
6aa8b732 AK |
9014 | } |
9015 | ||
4fa7734c PB |
9016 | static void vmx_load_vmcs01(struct kvm_vcpu *vcpu) |
9017 | { | |
9018 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9019 | int cpu; | |
9020 | ||
9021 | if (vmx->loaded_vmcs == &vmx->vmcs01) | |
9022 | return; | |
9023 | ||
9024 | cpu = get_cpu(); | |
9025 | vmx->loaded_vmcs = &vmx->vmcs01; | |
9026 | vmx_vcpu_put(vcpu); | |
9027 | vmx_vcpu_load(vcpu, cpu); | |
9028 | vcpu->cpu = cpu; | |
9029 | put_cpu(); | |
9030 | } | |
9031 | ||
6aa8b732 AK |
9032 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) |
9033 | { | |
fb3f0f51 RR |
9034 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
9035 | ||
843e4330 | 9036 | if (enable_pml) |
a3eaa864 | 9037 | vmx_destroy_pml_buffer(vmx); |
991e7a0e | 9038 | free_vpid(vmx->vpid); |
4fa7734c PB |
9039 | leave_guest_mode(vcpu); |
9040 | vmx_load_vmcs01(vcpu); | |
26a865f4 | 9041 | free_nested(vmx); |
4fa7734c | 9042 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 RR |
9043 | kfree(vmx->guest_msrs); |
9044 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 9045 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
9046 | } |
9047 | ||
fb3f0f51 | 9048 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 9049 | { |
fb3f0f51 | 9050 | int err; |
c16f862d | 9051 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
15ad7146 | 9052 | int cpu; |
6aa8b732 | 9053 | |
a2fa3e9f | 9054 | if (!vmx) |
fb3f0f51 RR |
9055 | return ERR_PTR(-ENOMEM); |
9056 | ||
991e7a0e | 9057 | vmx->vpid = allocate_vpid(); |
2384d2b3 | 9058 | |
fb3f0f51 RR |
9059 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
9060 | if (err) | |
9061 | goto free_vcpu; | |
965b58a5 | 9062 | |
a2fa3e9f | 9063 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
03916db9 PB |
9064 | BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0]) |
9065 | > PAGE_SIZE); | |
0123be42 | 9066 | |
be6d05cf | 9067 | err = -ENOMEM; |
fb3f0f51 | 9068 | if (!vmx->guest_msrs) { |
fb3f0f51 RR |
9069 | goto uninit_vcpu; |
9070 | } | |
965b58a5 | 9071 | |
d462b819 NHE |
9072 | vmx->loaded_vmcs = &vmx->vmcs01; |
9073 | vmx->loaded_vmcs->vmcs = alloc_vmcs(); | |
9074 | if (!vmx->loaded_vmcs->vmcs) | |
fb3f0f51 | 9075 | goto free_msrs; |
d462b819 NHE |
9076 | if (!vmm_exclusive) |
9077 | kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id()))); | |
9078 | loaded_vmcs_init(vmx->loaded_vmcs); | |
9079 | if (!vmm_exclusive) | |
9080 | kvm_cpu_vmxoff(); | |
a2fa3e9f | 9081 | |
15ad7146 AK |
9082 | cpu = get_cpu(); |
9083 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
e48672fa | 9084 | vmx->vcpu.cpu = cpu; |
8b9cf98c | 9085 | err = vmx_vcpu_setup(vmx); |
fb3f0f51 | 9086 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 9087 | put_cpu(); |
fb3f0f51 RR |
9088 | if (err) |
9089 | goto free_vmcs; | |
35754c98 | 9090 | if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { |
be6d05cf JK |
9091 | err = alloc_apic_access_page(kvm); |
9092 | if (err) | |
5e4a0b3c | 9093 | goto free_vmcs; |
a63cb560 | 9094 | } |
fb3f0f51 | 9095 | |
b927a3ce SY |
9096 | if (enable_ept) { |
9097 | if (!kvm->arch.ept_identity_map_addr) | |
9098 | kvm->arch.ept_identity_map_addr = | |
9099 | VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
f51770ed TC |
9100 | err = init_rmode_identity_map(kvm); |
9101 | if (err) | |
93ea5388 | 9102 | goto free_vmcs; |
b927a3ce | 9103 | } |
b7ebfb05 | 9104 | |
5c614b35 | 9105 | if (nested) { |
b9c237bb | 9106 | nested_vmx_setup_ctls_msrs(vmx); |
5c614b35 WL |
9107 | vmx->nested.vpid02 = allocate_vpid(); |
9108 | } | |
b9c237bb | 9109 | |
705699a1 | 9110 | vmx->nested.posted_intr_nv = -1; |
a9d30f33 NHE |
9111 | vmx->nested.current_vmptr = -1ull; |
9112 | vmx->nested.current_vmcs12 = NULL; | |
9113 | ||
843e4330 KH |
9114 | /* |
9115 | * If PML is turned on, failure on enabling PML just results in failure | |
9116 | * of creating the vcpu, therefore we can simplify PML logic (by | |
9117 | * avoiding dealing with cases, such as enabling PML partially on vcpus | |
9118 | * for the guest, etc. | |
9119 | */ | |
9120 | if (enable_pml) { | |
a3eaa864 | 9121 | err = vmx_create_pml_buffer(vmx); |
843e4330 KH |
9122 | if (err) |
9123 | goto free_vmcs; | |
9124 | } | |
9125 | ||
37e4c997 HZ |
9126 | vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED; |
9127 | ||
fb3f0f51 RR |
9128 | return &vmx->vcpu; |
9129 | ||
9130 | free_vmcs: | |
5c614b35 | 9131 | free_vpid(vmx->nested.vpid02); |
5f3fbc34 | 9132 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 | 9133 | free_msrs: |
fb3f0f51 RR |
9134 | kfree(vmx->guest_msrs); |
9135 | uninit_vcpu: | |
9136 | kvm_vcpu_uninit(&vmx->vcpu); | |
9137 | free_vcpu: | |
991e7a0e | 9138 | free_vpid(vmx->vpid); |
a4770347 | 9139 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 9140 | return ERR_PTR(err); |
6aa8b732 AK |
9141 | } |
9142 | ||
002c7f7c YS |
9143 | static void __init vmx_check_processor_compat(void *rtn) |
9144 | { | |
9145 | struct vmcs_config vmcs_conf; | |
9146 | ||
9147 | *(int *)rtn = 0; | |
9148 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
9149 | *(int *)rtn = -EIO; | |
9150 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
9151 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
9152 | smp_processor_id()); | |
9153 | *(int *)rtn = -EIO; | |
9154 | } | |
9155 | } | |
9156 | ||
67253af5 SY |
9157 | static int get_ept_level(void) |
9158 | { | |
9159 | return VMX_EPT_DEFAULT_GAW + 1; | |
9160 | } | |
9161 | ||
4b12f0de | 9162 | static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 | 9163 | { |
b18d5431 XG |
9164 | u8 cache; |
9165 | u64 ipat = 0; | |
4b12f0de | 9166 | |
522c68c4 | 9167 | /* For VT-d and EPT combination |
606decd6 | 9168 | * 1. MMIO: always map as UC |
522c68c4 SY |
9169 | * 2. EPT with VT-d: |
9170 | * a. VT-d without snooping control feature: can't guarantee the | |
606decd6 | 9171 | * result, try to trust guest. |
522c68c4 SY |
9172 | * b. VT-d with snooping control feature: snooping control feature of |
9173 | * VT-d engine can guarantee the cache correctness. Just set it | |
9174 | * to WB to keep consistent with host. So the same as item 3. | |
a19a6d11 | 9175 | * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep |
522c68c4 SY |
9176 | * consistent with host MTRR |
9177 | */ | |
606decd6 PB |
9178 | if (is_mmio) { |
9179 | cache = MTRR_TYPE_UNCACHABLE; | |
9180 | goto exit; | |
9181 | } | |
9182 | ||
9183 | if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { | |
b18d5431 XG |
9184 | ipat = VMX_EPT_IPAT_BIT; |
9185 | cache = MTRR_TYPE_WRBACK; | |
9186 | goto exit; | |
9187 | } | |
9188 | ||
9189 | if (kvm_read_cr0(vcpu) & X86_CR0_CD) { | |
9190 | ipat = VMX_EPT_IPAT_BIT; | |
0da029ed | 9191 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) |
fb279950 XG |
9192 | cache = MTRR_TYPE_WRBACK; |
9193 | else | |
9194 | cache = MTRR_TYPE_UNCACHABLE; | |
b18d5431 XG |
9195 | goto exit; |
9196 | } | |
9197 | ||
ff53604b | 9198 | cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); |
b18d5431 XG |
9199 | |
9200 | exit: | |
9201 | return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; | |
64d4d521 SY |
9202 | } |
9203 | ||
17cc3935 | 9204 | static int vmx_get_lpage_level(void) |
344f414f | 9205 | { |
878403b7 SY |
9206 | if (enable_ept && !cpu_has_vmx_ept_1g_page()) |
9207 | return PT_DIRECTORY_LEVEL; | |
9208 | else | |
9209 | /* For shadow and EPT supported 1GB page */ | |
9210 | return PT_PDPE_LEVEL; | |
344f414f JR |
9211 | } |
9212 | ||
feda805f XG |
9213 | static void vmcs_set_secondary_exec_control(u32 new_ctl) |
9214 | { | |
9215 | /* | |
9216 | * These bits in the secondary execution controls field | |
9217 | * are dynamic, the others are mostly based on the hypervisor | |
9218 | * architecture and the guest's CPUID. Do not touch the | |
9219 | * dynamic bits. | |
9220 | */ | |
9221 | u32 mask = | |
9222 | SECONDARY_EXEC_SHADOW_VMCS | | |
9223 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | | |
9224 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
9225 | ||
9226 | u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
9227 | ||
9228 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, | |
9229 | (new_ctl & ~mask) | (cur_ctl & mask)); | |
9230 | } | |
9231 | ||
0e851880 SY |
9232 | static void vmx_cpuid_update(struct kvm_vcpu *vcpu) |
9233 | { | |
4e47c7a6 SY |
9234 | struct kvm_cpuid_entry2 *best; |
9235 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
feda805f | 9236 | u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx); |
4e47c7a6 | 9237 | |
4e47c7a6 | 9238 | if (vmx_rdtscp_supported()) { |
1cea0ce6 XG |
9239 | bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu); |
9240 | if (!rdtscp_enabled) | |
feda805f | 9241 | secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP; |
f36201e5 | 9242 | |
8b97265a | 9243 | if (nested) { |
1cea0ce6 | 9244 | if (rdtscp_enabled) |
8b97265a PB |
9245 | vmx->nested.nested_vmx_secondary_ctls_high |= |
9246 | SECONDARY_EXEC_RDTSCP; | |
9247 | else | |
9248 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
9249 | ~SECONDARY_EXEC_RDTSCP; | |
9250 | } | |
4e47c7a6 | 9251 | } |
ad756a16 | 9252 | |
ad756a16 MJ |
9253 | /* Exposing INVPCID only when PCID is exposed */ |
9254 | best = kvm_find_cpuid_entry(vcpu, 0x7, 0); | |
9255 | if (vmx_invpcid_supported() && | |
29541bb8 XG |
9256 | (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) || |
9257 | !guest_cpuid_has_pcid(vcpu))) { | |
feda805f | 9258 | secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID; |
29541bb8 | 9259 | |
ad756a16 | 9260 | if (best) |
4f977045 | 9261 | best->ebx &= ~bit(X86_FEATURE_INVPCID); |
ad756a16 | 9262 | } |
8b3e34e4 | 9263 | |
45bdbcfd HH |
9264 | if (cpu_has_secondary_exec_ctrls()) |
9265 | vmcs_set_secondary_exec_control(secondary_exec_ctl); | |
feda805f | 9266 | |
8b3e34e4 XG |
9267 | if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) { |
9268 | if (guest_cpuid_has_pcommit(vcpu)) | |
9269 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
9270 | SECONDARY_EXEC_PCOMMIT; | |
9271 | else | |
9272 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
9273 | ~SECONDARY_EXEC_PCOMMIT; | |
9274 | } | |
37e4c997 HZ |
9275 | |
9276 | if (nested_vmx_allowed(vcpu)) | |
9277 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= | |
9278 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
9279 | else | |
9280 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= | |
9281 | ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
0e851880 SY |
9282 | } |
9283 | ||
d4330ef2 JR |
9284 | static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
9285 | { | |
7b8050f5 NHE |
9286 | if (func == 1 && nested) |
9287 | entry->ecx |= bit(X86_FEATURE_VMX); | |
d4330ef2 JR |
9288 | } |
9289 | ||
25d92081 YZ |
9290 | static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu, |
9291 | struct x86_exception *fault) | |
9292 | { | |
533558bc JK |
9293 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
9294 | u32 exit_reason; | |
25d92081 YZ |
9295 | |
9296 | if (fault->error_code & PFERR_RSVD_MASK) | |
533558bc | 9297 | exit_reason = EXIT_REASON_EPT_MISCONFIG; |
25d92081 | 9298 | else |
533558bc JK |
9299 | exit_reason = EXIT_REASON_EPT_VIOLATION; |
9300 | nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification); | |
25d92081 YZ |
9301 | vmcs12->guest_physical_address = fault->address; |
9302 | } | |
9303 | ||
155a97a3 NHE |
9304 | /* Callbacks for nested_ept_init_mmu_context: */ |
9305 | ||
9306 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu) | |
9307 | { | |
9308 | /* return the page table to be shadowed - in our case, EPT12 */ | |
9309 | return get_vmcs12(vcpu)->ept_pointer; | |
9310 | } | |
9311 | ||
8a3c1a33 | 9312 | static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu) |
155a97a3 | 9313 | { |
ad896af0 PB |
9314 | WARN_ON(mmu_is_nested(vcpu)); |
9315 | kvm_init_shadow_ept_mmu(vcpu, | |
b9c237bb WV |
9316 | to_vmx(vcpu)->nested.nested_vmx_ept_caps & |
9317 | VMX_EPT_EXECUTE_ONLY_BIT); | |
155a97a3 NHE |
9318 | vcpu->arch.mmu.set_cr3 = vmx_set_cr3; |
9319 | vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3; | |
9320 | vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault; | |
9321 | ||
9322 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
155a97a3 NHE |
9323 | } |
9324 | ||
9325 | static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
9326 | { | |
9327 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
9328 | } | |
9329 | ||
19d5f10b EK |
9330 | static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, |
9331 | u16 error_code) | |
9332 | { | |
9333 | bool inequality, bit; | |
9334 | ||
9335 | bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0; | |
9336 | inequality = | |
9337 | (error_code & vmcs12->page_fault_error_code_mask) != | |
9338 | vmcs12->page_fault_error_code_match; | |
9339 | return inequality ^ bit; | |
9340 | } | |
9341 | ||
feaf0c7d GN |
9342 | static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu, |
9343 | struct x86_exception *fault) | |
9344 | { | |
9345 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
9346 | ||
9347 | WARN_ON(!is_guest_mode(vcpu)); | |
9348 | ||
19d5f10b | 9349 | if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code)) |
533558bc JK |
9350 | nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason, |
9351 | vmcs_read32(VM_EXIT_INTR_INFO), | |
9352 | vmcs_readl(EXIT_QUALIFICATION)); | |
feaf0c7d GN |
9353 | else |
9354 | kvm_inject_page_fault(vcpu, fault); | |
9355 | } | |
9356 | ||
a2bcba50 WL |
9357 | static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu, |
9358 | struct vmcs12 *vmcs12) | |
9359 | { | |
9360 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9090422f | 9361 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
a2bcba50 WL |
9362 | |
9363 | if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
9090422f EK |
9364 | if (!PAGE_ALIGNED(vmcs12->apic_access_addr) || |
9365 | vmcs12->apic_access_addr >> maxphyaddr) | |
a2bcba50 WL |
9366 | return false; |
9367 | ||
9368 | /* | |
9369 | * Translate L1 physical address to host physical | |
9370 | * address for vmcs02. Keep the page pinned, so this | |
9371 | * physical address remains valid. We keep a reference | |
9372 | * to it so we can release it later. | |
9373 | */ | |
9374 | if (vmx->nested.apic_access_page) /* shouldn't happen */ | |
9375 | nested_release_page(vmx->nested.apic_access_page); | |
9376 | vmx->nested.apic_access_page = | |
9377 | nested_get_page(vcpu, vmcs12->apic_access_addr); | |
9378 | } | |
a7c0b07d WL |
9379 | |
9380 | if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { | |
9090422f EK |
9381 | if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) || |
9382 | vmcs12->virtual_apic_page_addr >> maxphyaddr) | |
a7c0b07d WL |
9383 | return false; |
9384 | ||
9385 | if (vmx->nested.virtual_apic_page) /* shouldn't happen */ | |
9386 | nested_release_page(vmx->nested.virtual_apic_page); | |
9387 | vmx->nested.virtual_apic_page = | |
9388 | nested_get_page(vcpu, vmcs12->virtual_apic_page_addr); | |
9389 | ||
9390 | /* | |
9391 | * Failing the vm entry is _not_ what the processor does | |
9392 | * but it's basically the only possibility we have. | |
9393 | * We could still enter the guest if CR8 load exits are | |
9394 | * enabled, CR8 store exits are enabled, and virtualize APIC | |
9395 | * access is disabled; in this case the processor would never | |
9396 | * use the TPR shadow and we could simply clear the bit from | |
9397 | * the execution control. But such a configuration is useless, | |
9398 | * so let's keep the code simple. | |
9399 | */ | |
9400 | if (!vmx->nested.virtual_apic_page) | |
9401 | return false; | |
9402 | } | |
9403 | ||
705699a1 | 9404 | if (nested_cpu_has_posted_intr(vmcs12)) { |
9090422f EK |
9405 | if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) || |
9406 | vmcs12->posted_intr_desc_addr >> maxphyaddr) | |
705699a1 WV |
9407 | return false; |
9408 | ||
9409 | if (vmx->nested.pi_desc_page) { /* shouldn't happen */ | |
9410 | kunmap(vmx->nested.pi_desc_page); | |
9411 | nested_release_page(vmx->nested.pi_desc_page); | |
9412 | } | |
9413 | vmx->nested.pi_desc_page = | |
9414 | nested_get_page(vcpu, vmcs12->posted_intr_desc_addr); | |
9415 | if (!vmx->nested.pi_desc_page) | |
9416 | return false; | |
9417 | ||
9418 | vmx->nested.pi_desc = | |
9419 | (struct pi_desc *)kmap(vmx->nested.pi_desc_page); | |
9420 | if (!vmx->nested.pi_desc) { | |
9421 | nested_release_page_clean(vmx->nested.pi_desc_page); | |
9422 | return false; | |
9423 | } | |
9424 | vmx->nested.pi_desc = | |
9425 | (struct pi_desc *)((void *)vmx->nested.pi_desc + | |
9426 | (unsigned long)(vmcs12->posted_intr_desc_addr & | |
9427 | (PAGE_SIZE - 1))); | |
9428 | } | |
9429 | ||
a2bcba50 WL |
9430 | return true; |
9431 | } | |
9432 | ||
f4124500 JK |
9433 | static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu) |
9434 | { | |
9435 | u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value; | |
9436 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9437 | ||
9438 | if (vcpu->arch.virtual_tsc_khz == 0) | |
9439 | return; | |
9440 | ||
9441 | /* Make sure short timeouts reliably trigger an immediate vmexit. | |
9442 | * hrtimer_start does not guarantee this. */ | |
9443 | if (preemption_timeout <= 1) { | |
9444 | vmx_preemption_timer_fn(&vmx->nested.preemption_timer); | |
9445 | return; | |
9446 | } | |
9447 | ||
9448 | preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
9449 | preemption_timeout *= 1000000; | |
9450 | do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz); | |
9451 | hrtimer_start(&vmx->nested.preemption_timer, | |
9452 | ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL); | |
9453 | } | |
9454 | ||
3af18d9c WV |
9455 | static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, |
9456 | struct vmcs12 *vmcs12) | |
9457 | { | |
9458 | int maxphyaddr; | |
9459 | u64 addr; | |
9460 | ||
9461 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) | |
9462 | return 0; | |
9463 | ||
9464 | if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) { | |
9465 | WARN_ON(1); | |
9466 | return -EINVAL; | |
9467 | } | |
9468 | maxphyaddr = cpuid_maxphyaddr(vcpu); | |
9469 | ||
9470 | if (!PAGE_ALIGNED(vmcs12->msr_bitmap) || | |
9471 | ((addr + PAGE_SIZE) >> maxphyaddr)) | |
9472 | return -EINVAL; | |
9473 | ||
9474 | return 0; | |
9475 | } | |
9476 | ||
9477 | /* | |
9478 | * Merge L0's and L1's MSR bitmap, return false to indicate that | |
9479 | * we do not use the hardware. | |
9480 | */ | |
9481 | static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu, | |
9482 | struct vmcs12 *vmcs12) | |
9483 | { | |
82f0dd4b | 9484 | int msr; |
f2b93280 WV |
9485 | struct page *page; |
9486 | unsigned long *msr_bitmap; | |
9487 | ||
9488 | if (!nested_cpu_has_virt_x2apic_mode(vmcs12)) | |
9489 | return false; | |
9490 | ||
9491 | page = nested_get_page(vcpu, vmcs12->msr_bitmap); | |
9492 | if (!page) { | |
9493 | WARN_ON(1); | |
9494 | return false; | |
9495 | } | |
9496 | msr_bitmap = (unsigned long *)kmap(page); | |
9497 | if (!msr_bitmap) { | |
9498 | nested_release_page_clean(page); | |
9499 | WARN_ON(1); | |
9500 | return false; | |
9501 | } | |
9502 | ||
9503 | if (nested_cpu_has_virt_x2apic_mode(vmcs12)) { | |
82f0dd4b WV |
9504 | if (nested_cpu_has_apic_reg_virt(vmcs12)) |
9505 | for (msr = 0x800; msr <= 0x8ff; msr++) | |
9506 | nested_vmx_disable_intercept_for_msr( | |
9507 | msr_bitmap, | |
9508 | vmx_msr_bitmap_nested, | |
9509 | msr, MSR_TYPE_R); | |
f2b93280 WV |
9510 | /* TPR is allowed */ |
9511 | nested_vmx_disable_intercept_for_msr(msr_bitmap, | |
9512 | vmx_msr_bitmap_nested, | |
9513 | APIC_BASE_MSR + (APIC_TASKPRI >> 4), | |
9514 | MSR_TYPE_R | MSR_TYPE_W); | |
608406e2 WV |
9515 | if (nested_cpu_has_vid(vmcs12)) { |
9516 | /* EOI and self-IPI are allowed */ | |
9517 | nested_vmx_disable_intercept_for_msr( | |
9518 | msr_bitmap, | |
9519 | vmx_msr_bitmap_nested, | |
9520 | APIC_BASE_MSR + (APIC_EOI >> 4), | |
9521 | MSR_TYPE_W); | |
9522 | nested_vmx_disable_intercept_for_msr( | |
9523 | msr_bitmap, | |
9524 | vmx_msr_bitmap_nested, | |
9525 | APIC_BASE_MSR + (APIC_SELF_IPI >> 4), | |
9526 | MSR_TYPE_W); | |
9527 | } | |
82f0dd4b WV |
9528 | } else { |
9529 | /* | |
9530 | * Enable reading intercept of all the x2apic | |
9531 | * MSRs. We should not rely on vmcs12 to do any | |
9532 | * optimizations here, it may have been modified | |
9533 | * by L1. | |
9534 | */ | |
9535 | for (msr = 0x800; msr <= 0x8ff; msr++) | |
9536 | __vmx_enable_intercept_for_msr( | |
9537 | vmx_msr_bitmap_nested, | |
9538 | msr, | |
9539 | MSR_TYPE_R); | |
9540 | ||
f2b93280 WV |
9541 | __vmx_enable_intercept_for_msr( |
9542 | vmx_msr_bitmap_nested, | |
9543 | APIC_BASE_MSR + (APIC_TASKPRI >> 4), | |
82f0dd4b | 9544 | MSR_TYPE_W); |
608406e2 WV |
9545 | __vmx_enable_intercept_for_msr( |
9546 | vmx_msr_bitmap_nested, | |
9547 | APIC_BASE_MSR + (APIC_EOI >> 4), | |
9548 | MSR_TYPE_W); | |
9549 | __vmx_enable_intercept_for_msr( | |
9550 | vmx_msr_bitmap_nested, | |
9551 | APIC_BASE_MSR + (APIC_SELF_IPI >> 4), | |
9552 | MSR_TYPE_W); | |
82f0dd4b | 9553 | } |
f2b93280 WV |
9554 | kunmap(page); |
9555 | nested_release_page_clean(page); | |
9556 | ||
9557 | return true; | |
9558 | } | |
9559 | ||
9560 | static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu, | |
9561 | struct vmcs12 *vmcs12) | |
9562 | { | |
82f0dd4b | 9563 | if (!nested_cpu_has_virt_x2apic_mode(vmcs12) && |
608406e2 | 9564 | !nested_cpu_has_apic_reg_virt(vmcs12) && |
705699a1 WV |
9565 | !nested_cpu_has_vid(vmcs12) && |
9566 | !nested_cpu_has_posted_intr(vmcs12)) | |
f2b93280 WV |
9567 | return 0; |
9568 | ||
9569 | /* | |
9570 | * If virtualize x2apic mode is enabled, | |
9571 | * virtualize apic access must be disabled. | |
9572 | */ | |
82f0dd4b WV |
9573 | if (nested_cpu_has_virt_x2apic_mode(vmcs12) && |
9574 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
f2b93280 WV |
9575 | return -EINVAL; |
9576 | ||
608406e2 WV |
9577 | /* |
9578 | * If virtual interrupt delivery is enabled, | |
9579 | * we must exit on external interrupts. | |
9580 | */ | |
9581 | if (nested_cpu_has_vid(vmcs12) && | |
9582 | !nested_exit_on_intr(vcpu)) | |
9583 | return -EINVAL; | |
9584 | ||
705699a1 WV |
9585 | /* |
9586 | * bits 15:8 should be zero in posted_intr_nv, | |
9587 | * the descriptor address has been already checked | |
9588 | * in nested_get_vmcs12_pages. | |
9589 | */ | |
9590 | if (nested_cpu_has_posted_intr(vmcs12) && | |
9591 | (!nested_cpu_has_vid(vmcs12) || | |
9592 | !nested_exit_intr_ack_set(vcpu) || | |
9593 | vmcs12->posted_intr_nv & 0xff00)) | |
9594 | return -EINVAL; | |
9595 | ||
f2b93280 WV |
9596 | /* tpr shadow is needed by all apicv features. */ |
9597 | if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
9598 | return -EINVAL; | |
9599 | ||
9600 | return 0; | |
3af18d9c WV |
9601 | } |
9602 | ||
e9ac033e EK |
9603 | static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu, |
9604 | unsigned long count_field, | |
92d71bc6 | 9605 | unsigned long addr_field) |
ff651cb6 | 9606 | { |
92d71bc6 | 9607 | int maxphyaddr; |
e9ac033e EK |
9608 | u64 count, addr; |
9609 | ||
9610 | if (vmcs12_read_any(vcpu, count_field, &count) || | |
9611 | vmcs12_read_any(vcpu, addr_field, &addr)) { | |
9612 | WARN_ON(1); | |
9613 | return -EINVAL; | |
9614 | } | |
9615 | if (count == 0) | |
9616 | return 0; | |
92d71bc6 | 9617 | maxphyaddr = cpuid_maxphyaddr(vcpu); |
e9ac033e EK |
9618 | if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr || |
9619 | (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) { | |
9620 | pr_warn_ratelimited( | |
9621 | "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)", | |
9622 | addr_field, maxphyaddr, count, addr); | |
9623 | return -EINVAL; | |
9624 | } | |
9625 | return 0; | |
9626 | } | |
9627 | ||
9628 | static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu, | |
9629 | struct vmcs12 *vmcs12) | |
9630 | { | |
e9ac033e EK |
9631 | if (vmcs12->vm_exit_msr_load_count == 0 && |
9632 | vmcs12->vm_exit_msr_store_count == 0 && | |
9633 | vmcs12->vm_entry_msr_load_count == 0) | |
9634 | return 0; /* Fast path */ | |
e9ac033e | 9635 | if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT, |
92d71bc6 | 9636 | VM_EXIT_MSR_LOAD_ADDR) || |
e9ac033e | 9637 | nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT, |
92d71bc6 | 9638 | VM_EXIT_MSR_STORE_ADDR) || |
e9ac033e | 9639 | nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT, |
92d71bc6 | 9640 | VM_ENTRY_MSR_LOAD_ADDR)) |
e9ac033e EK |
9641 | return -EINVAL; |
9642 | return 0; | |
9643 | } | |
9644 | ||
9645 | static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu, | |
9646 | struct vmx_msr_entry *e) | |
9647 | { | |
9648 | /* x2APIC MSR accesses are not allowed */ | |
8a9781f7 | 9649 | if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8) |
e9ac033e EK |
9650 | return -EINVAL; |
9651 | if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */ | |
9652 | e->index == MSR_IA32_UCODE_REV) | |
9653 | return -EINVAL; | |
9654 | if (e->reserved != 0) | |
ff651cb6 WV |
9655 | return -EINVAL; |
9656 | return 0; | |
9657 | } | |
9658 | ||
e9ac033e EK |
9659 | static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu, |
9660 | struct vmx_msr_entry *e) | |
ff651cb6 WV |
9661 | { |
9662 | if (e->index == MSR_FS_BASE || | |
9663 | e->index == MSR_GS_BASE || | |
e9ac033e EK |
9664 | e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */ |
9665 | nested_vmx_msr_check_common(vcpu, e)) | |
9666 | return -EINVAL; | |
9667 | return 0; | |
9668 | } | |
9669 | ||
9670 | static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu, | |
9671 | struct vmx_msr_entry *e) | |
9672 | { | |
9673 | if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */ | |
9674 | nested_vmx_msr_check_common(vcpu, e)) | |
ff651cb6 WV |
9675 | return -EINVAL; |
9676 | return 0; | |
9677 | } | |
9678 | ||
9679 | /* | |
9680 | * Load guest's/host's msr at nested entry/exit. | |
9681 | * return 0 for success, entry index for failure. | |
9682 | */ | |
9683 | static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) | |
9684 | { | |
9685 | u32 i; | |
9686 | struct vmx_msr_entry e; | |
9687 | struct msr_data msr; | |
9688 | ||
9689 | msr.host_initiated = false; | |
9690 | for (i = 0; i < count; i++) { | |
54bf36aa PB |
9691 | if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e), |
9692 | &e, sizeof(e))) { | |
e9ac033e EK |
9693 | pr_warn_ratelimited( |
9694 | "%s cannot read MSR entry (%u, 0x%08llx)\n", | |
9695 | __func__, i, gpa + i * sizeof(e)); | |
ff651cb6 | 9696 | goto fail; |
e9ac033e EK |
9697 | } |
9698 | if (nested_vmx_load_msr_check(vcpu, &e)) { | |
9699 | pr_warn_ratelimited( | |
9700 | "%s check failed (%u, 0x%x, 0x%x)\n", | |
9701 | __func__, i, e.index, e.reserved); | |
9702 | goto fail; | |
9703 | } | |
ff651cb6 WV |
9704 | msr.index = e.index; |
9705 | msr.data = e.value; | |
e9ac033e EK |
9706 | if (kvm_set_msr(vcpu, &msr)) { |
9707 | pr_warn_ratelimited( | |
9708 | "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", | |
9709 | __func__, i, e.index, e.value); | |
ff651cb6 | 9710 | goto fail; |
e9ac033e | 9711 | } |
ff651cb6 WV |
9712 | } |
9713 | return 0; | |
9714 | fail: | |
9715 | return i + 1; | |
9716 | } | |
9717 | ||
9718 | static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) | |
9719 | { | |
9720 | u32 i; | |
9721 | struct vmx_msr_entry e; | |
9722 | ||
9723 | for (i = 0; i < count; i++) { | |
609e36d3 | 9724 | struct msr_data msr_info; |
54bf36aa PB |
9725 | if (kvm_vcpu_read_guest(vcpu, |
9726 | gpa + i * sizeof(e), | |
9727 | &e, 2 * sizeof(u32))) { | |
e9ac033e EK |
9728 | pr_warn_ratelimited( |
9729 | "%s cannot read MSR entry (%u, 0x%08llx)\n", | |
9730 | __func__, i, gpa + i * sizeof(e)); | |
ff651cb6 | 9731 | return -EINVAL; |
e9ac033e EK |
9732 | } |
9733 | if (nested_vmx_store_msr_check(vcpu, &e)) { | |
9734 | pr_warn_ratelimited( | |
9735 | "%s check failed (%u, 0x%x, 0x%x)\n", | |
9736 | __func__, i, e.index, e.reserved); | |
ff651cb6 | 9737 | return -EINVAL; |
e9ac033e | 9738 | } |
609e36d3 PB |
9739 | msr_info.host_initiated = false; |
9740 | msr_info.index = e.index; | |
9741 | if (kvm_get_msr(vcpu, &msr_info)) { | |
e9ac033e EK |
9742 | pr_warn_ratelimited( |
9743 | "%s cannot read MSR (%u, 0x%x)\n", | |
9744 | __func__, i, e.index); | |
9745 | return -EINVAL; | |
9746 | } | |
54bf36aa PB |
9747 | if (kvm_vcpu_write_guest(vcpu, |
9748 | gpa + i * sizeof(e) + | |
9749 | offsetof(struct vmx_msr_entry, value), | |
9750 | &msr_info.data, sizeof(msr_info.data))) { | |
e9ac033e EK |
9751 | pr_warn_ratelimited( |
9752 | "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", | |
609e36d3 | 9753 | __func__, i, e.index, msr_info.data); |
e9ac033e EK |
9754 | return -EINVAL; |
9755 | } | |
ff651cb6 WV |
9756 | } |
9757 | return 0; | |
9758 | } | |
9759 | ||
fe3ef05c NHE |
9760 | /* |
9761 | * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested | |
9762 | * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it | |
b4619660 | 9763 | * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2 |
fe3ef05c NHE |
9764 | * guest in a way that will both be appropriate to L1's requests, and our |
9765 | * needs. In addition to modifying the active vmcs (which is vmcs02), this | |
9766 | * function also has additional necessary side-effects, like setting various | |
9767 | * vcpu->arch fields. | |
9768 | */ | |
9769 | static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
9770 | { | |
9771 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9772 | u32 exec_control; | |
9773 | ||
9774 | vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector); | |
9775 | vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector); | |
9776 | vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector); | |
9777 | vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector); | |
9778 | vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector); | |
9779 | vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector); | |
9780 | vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector); | |
9781 | vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector); | |
9782 | vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit); | |
9783 | vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit); | |
9784 | vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit); | |
9785 | vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit); | |
9786 | vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit); | |
9787 | vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit); | |
9788 | vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit); | |
9789 | vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit); | |
9790 | vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit); | |
9791 | vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit); | |
9792 | vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes); | |
9793 | vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes); | |
9794 | vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes); | |
9795 | vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes); | |
9796 | vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes); | |
9797 | vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes); | |
9798 | vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes); | |
9799 | vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes); | |
9800 | vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base); | |
9801 | vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base); | |
9802 | vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base); | |
9803 | vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base); | |
9804 | vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base); | |
9805 | vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base); | |
9806 | vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base); | |
9807 | vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base); | |
9808 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base); | |
9809 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base); | |
9810 | ||
2996fca0 JK |
9811 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) { |
9812 | kvm_set_dr(vcpu, 7, vmcs12->guest_dr7); | |
9813 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl); | |
9814 | } else { | |
9815 | kvm_set_dr(vcpu, 7, vcpu->arch.dr7); | |
9816 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl); | |
9817 | } | |
fe3ef05c NHE |
9818 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
9819 | vmcs12->vm_entry_intr_info_field); | |
9820 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, | |
9821 | vmcs12->vm_entry_exception_error_code); | |
9822 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
9823 | vmcs12->vm_entry_instruction_len); | |
9824 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
9825 | vmcs12->guest_interruptibility_info); | |
fe3ef05c | 9826 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs); |
63fbf59f | 9827 | vmx_set_rflags(vcpu, vmcs12->guest_rflags); |
fe3ef05c NHE |
9828 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, |
9829 | vmcs12->guest_pending_dbg_exceptions); | |
9830 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp); | |
9831 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip); | |
9832 | ||
81dc01f7 WL |
9833 | if (nested_cpu_has_xsaves(vmcs12)) |
9834 | vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap); | |
fe3ef05c NHE |
9835 | vmcs_write64(VMCS_LINK_POINTER, -1ull); |
9836 | ||
f4124500 | 9837 | exec_control = vmcs12->pin_based_vm_exec_control; |
9314006d PB |
9838 | |
9839 | /* Preemption timer setting is only taken from vmcs01. */ | |
705699a1 | 9840 | exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; |
9314006d PB |
9841 | exec_control |= vmcs_config.pin_based_exec_ctrl; |
9842 | if (vmx->hv_deadline_tsc == -1) | |
9843 | exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
705699a1 | 9844 | |
9314006d | 9845 | /* Posted interrupts setting is only taken from vmcs12. */ |
705699a1 WV |
9846 | if (nested_cpu_has_posted_intr(vmcs12)) { |
9847 | /* | |
9848 | * Note that we use L0's vector here and in | |
9849 | * vmx_deliver_nested_posted_interrupt. | |
9850 | */ | |
9851 | vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv; | |
9852 | vmx->nested.pi_pending = false; | |
0bcf261c | 9853 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); |
705699a1 WV |
9854 | vmcs_write64(POSTED_INTR_DESC_ADDR, |
9855 | page_to_phys(vmx->nested.pi_desc_page) + | |
9856 | (unsigned long)(vmcs12->posted_intr_desc_addr & | |
9857 | (PAGE_SIZE - 1))); | |
9858 | } else | |
9859 | exec_control &= ~PIN_BASED_POSTED_INTR; | |
9860 | ||
f4124500 | 9861 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control); |
fe3ef05c | 9862 | |
f4124500 JK |
9863 | vmx->nested.preemption_timer_expired = false; |
9864 | if (nested_cpu_has_preemption_timer(vmcs12)) | |
9865 | vmx_start_preemption_timer(vcpu); | |
0238ea91 | 9866 | |
fe3ef05c NHE |
9867 | /* |
9868 | * Whether page-faults are trapped is determined by a combination of | |
9869 | * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF. | |
9870 | * If enable_ept, L0 doesn't care about page faults and we should | |
9871 | * set all of these to L1's desires. However, if !enable_ept, L0 does | |
9872 | * care about (at least some) page faults, and because it is not easy | |
9873 | * (if at all possible?) to merge L0 and L1's desires, we simply ask | |
9874 | * to exit on each and every L2 page fault. This is done by setting | |
9875 | * MASK=MATCH=0 and (see below) EB.PF=1. | |
9876 | * Note that below we don't need special code to set EB.PF beyond the | |
9877 | * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept, | |
9878 | * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when | |
9879 | * !enable_ept, EB.PF is 1, so the "or" will always be 1. | |
9880 | * | |
9881 | * A problem with this approach (when !enable_ept) is that L1 may be | |
9882 | * injected with more page faults than it asked for. This could have | |
9883 | * caused problems, but in practice existing hypervisors don't care. | |
9884 | * To fix this, we will need to emulate the PFEC checking (on the L1 | |
9885 | * page tables), using walk_addr(), when injecting PFs to L1. | |
9886 | */ | |
9887 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, | |
9888 | enable_ept ? vmcs12->page_fault_error_code_mask : 0); | |
9889 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, | |
9890 | enable_ept ? vmcs12->page_fault_error_code_match : 0); | |
9891 | ||
9892 | if (cpu_has_secondary_exec_ctrls()) { | |
f4124500 | 9893 | exec_control = vmx_secondary_exec_control(vmx); |
e2821620 | 9894 | |
fe3ef05c | 9895 | /* Take the following fields only from vmcs12 */ |
696dfd95 | 9896 | exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
b3a2a907 | 9897 | SECONDARY_EXEC_RDTSCP | |
696dfd95 | 9898 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
8b3e34e4 XG |
9899 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
9900 | SECONDARY_EXEC_PCOMMIT); | |
fe3ef05c NHE |
9901 | if (nested_cpu_has(vmcs12, |
9902 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) | |
9903 | exec_control |= vmcs12->secondary_vm_exec_control; | |
9904 | ||
9905 | if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) { | |
fe3ef05c NHE |
9906 | /* |
9907 | * If translation failed, no matter: This feature asks | |
9908 | * to exit when accessing the given address, and if it | |
9909 | * can never be accessed, this feature won't do | |
9910 | * anything anyway. | |
9911 | */ | |
9912 | if (!vmx->nested.apic_access_page) | |
9913 | exec_control &= | |
9914 | ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
9915 | else | |
9916 | vmcs_write64(APIC_ACCESS_ADDR, | |
9917 | page_to_phys(vmx->nested.apic_access_page)); | |
f2b93280 | 9918 | } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) && |
35754c98 | 9919 | cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { |
ca3f257a JK |
9920 | exec_control |= |
9921 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
38b99173 | 9922 | kvm_vcpu_reload_apic_access_page(vcpu); |
fe3ef05c NHE |
9923 | } |
9924 | ||
608406e2 WV |
9925 | if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { |
9926 | vmcs_write64(EOI_EXIT_BITMAP0, | |
9927 | vmcs12->eoi_exit_bitmap0); | |
9928 | vmcs_write64(EOI_EXIT_BITMAP1, | |
9929 | vmcs12->eoi_exit_bitmap1); | |
9930 | vmcs_write64(EOI_EXIT_BITMAP2, | |
9931 | vmcs12->eoi_exit_bitmap2); | |
9932 | vmcs_write64(EOI_EXIT_BITMAP3, | |
9933 | vmcs12->eoi_exit_bitmap3); | |
9934 | vmcs_write16(GUEST_INTR_STATUS, | |
9935 | vmcs12->guest_intr_status); | |
9936 | } | |
9937 | ||
fe3ef05c NHE |
9938 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
9939 | } | |
9940 | ||
9941 | ||
9942 | /* | |
9943 | * Set host-state according to L0's settings (vmcs12 is irrelevant here) | |
9944 | * Some constant fields are set here by vmx_set_constant_host_state(). | |
9945 | * Other fields are different per CPU, and will be set later when | |
9946 | * vmx_vcpu_load() is called, and when vmx_save_host_state() is called. | |
9947 | */ | |
a547c6db | 9948 | vmx_set_constant_host_state(vmx); |
fe3ef05c NHE |
9949 | |
9950 | /* | |
9951 | * HOST_RSP is normally set correctly in vmx_vcpu_run() just before | |
9952 | * entry, but only if the current (host) sp changed from the value | |
9953 | * we wrote last (vmx->host_rsp). This cache is no longer relevant | |
9954 | * if we switch vmcs, and rather than hold a separate cache per vmcs, | |
9955 | * here we just force the write to happen on entry. | |
9956 | */ | |
9957 | vmx->host_rsp = 0; | |
9958 | ||
9959 | exec_control = vmx_exec_control(vmx); /* L0's desires */ | |
9960 | exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
9961 | exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
9962 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
9963 | exec_control |= vmcs12->cpu_based_vm_exec_control; | |
a7c0b07d WL |
9964 | |
9965 | if (exec_control & CPU_BASED_TPR_SHADOW) { | |
9966 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, | |
9967 | page_to_phys(vmx->nested.virtual_apic_page)); | |
9968 | vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold); | |
9969 | } | |
9970 | ||
3af18d9c | 9971 | if (cpu_has_vmx_msr_bitmap() && |
670125bd WV |
9972 | exec_control & CPU_BASED_USE_MSR_BITMAPS) { |
9973 | nested_vmx_merge_msr_bitmap(vcpu, vmcs12); | |
9974 | /* MSR_BITMAP will be set by following vmx_set_efer. */ | |
3af18d9c WV |
9975 | } else |
9976 | exec_control &= ~CPU_BASED_USE_MSR_BITMAPS; | |
9977 | ||
fe3ef05c | 9978 | /* |
3af18d9c | 9979 | * Merging of IO bitmap not currently supported. |
fe3ef05c NHE |
9980 | * Rather, exit every time. |
9981 | */ | |
fe3ef05c NHE |
9982 | exec_control &= ~CPU_BASED_USE_IO_BITMAPS; |
9983 | exec_control |= CPU_BASED_UNCOND_IO_EXITING; | |
9984 | ||
9985 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); | |
9986 | ||
9987 | /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the | |
9988 | * bitwise-or of what L1 wants to trap for L2, and what we want to | |
9989 | * trap. Note that CR0.TS also needs updating - we do this later. | |
9990 | */ | |
9991 | update_exception_bitmap(vcpu); | |
9992 | vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask; | |
9993 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
9994 | ||
8049d651 NHE |
9995 | /* L2->L1 exit controls are emulated - the hardware exit is to L0 so |
9996 | * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER | |
9997 | * bits are further modified by vmx_set_efer() below. | |
9998 | */ | |
f4124500 | 9999 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
8049d651 NHE |
10000 | |
10001 | /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are | |
10002 | * emulated by vmx_set_efer(), below. | |
10003 | */ | |
2961e876 | 10004 | vm_entry_controls_init(vmx, |
8049d651 NHE |
10005 | (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER & |
10006 | ~VM_ENTRY_IA32E_MODE) | | |
fe3ef05c NHE |
10007 | (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE)); |
10008 | ||
44811c02 | 10009 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) { |
fe3ef05c | 10010 | vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat); |
44811c02 JK |
10011 | vcpu->arch.pat = vmcs12->guest_ia32_pat; |
10012 | } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) | |
fe3ef05c NHE |
10013 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); |
10014 | ||
10015 | ||
10016 | set_cr4_guest_host_mask(vmx); | |
10017 | ||
36be0b9d PB |
10018 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) |
10019 | vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs); | |
10020 | ||
27fc51b2 NHE |
10021 | if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING) |
10022 | vmcs_write64(TSC_OFFSET, | |
10023 | vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset); | |
10024 | else | |
10025 | vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset); | |
fe3ef05c NHE |
10026 | |
10027 | if (enable_vpid) { | |
10028 | /* | |
5c614b35 WL |
10029 | * There is no direct mapping between vpid02 and vpid12, the |
10030 | * vpid02 is per-vCPU for L0 and reused while the value of | |
10031 | * vpid12 is changed w/ one invvpid during nested vmentry. | |
10032 | * The vpid12 is allocated by L1 for L2, so it will not | |
10033 | * influence global bitmap(for vpid01 and vpid02 allocation) | |
10034 | * even if spawn a lot of nested vCPUs. | |
fe3ef05c | 10035 | */ |
5c614b35 WL |
10036 | if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) { |
10037 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02); | |
10038 | if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) { | |
10039 | vmx->nested.last_vpid = vmcs12->virtual_processor_id; | |
10040 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02); | |
10041 | } | |
10042 | } else { | |
10043 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
10044 | vmx_flush_tlb(vcpu); | |
10045 | } | |
10046 | ||
fe3ef05c NHE |
10047 | } |
10048 | ||
155a97a3 NHE |
10049 | if (nested_cpu_has_ept(vmcs12)) { |
10050 | kvm_mmu_unload(vcpu); | |
10051 | nested_ept_init_mmu_context(vcpu); | |
10052 | } | |
10053 | ||
fe3ef05c NHE |
10054 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) |
10055 | vcpu->arch.efer = vmcs12->guest_ia32_efer; | |
d1fa0352 | 10056 | else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) |
fe3ef05c NHE |
10057 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); |
10058 | else | |
10059 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
10060 | /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */ | |
10061 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
10062 | ||
10063 | /* | |
10064 | * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified | |
10065 | * TS bit (for lazy fpu) and bits which we consider mandatory enabled. | |
10066 | * The CR0_READ_SHADOW is what L2 should have expected to read given | |
10067 | * the specifications by L1; It's not enough to take | |
10068 | * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we | |
10069 | * have more bits than L1 expected. | |
10070 | */ | |
10071 | vmx_set_cr0(vcpu, vmcs12->guest_cr0); | |
10072 | vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); | |
10073 | ||
10074 | vmx_set_cr4(vcpu, vmcs12->guest_cr4); | |
10075 | vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12)); | |
10076 | ||
10077 | /* shadow page tables on either EPT or shadow page tables */ | |
10078 | kvm_set_cr3(vcpu, vmcs12->guest_cr3); | |
10079 | kvm_mmu_reset_context(vcpu); | |
10080 | ||
feaf0c7d GN |
10081 | if (!enable_ept) |
10082 | vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested; | |
10083 | ||
3633cfc3 NHE |
10084 | /* |
10085 | * L1 may access the L2's PDPTR, so save them to construct vmcs12 | |
10086 | */ | |
10087 | if (enable_ept) { | |
10088 | vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0); | |
10089 | vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1); | |
10090 | vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2); | |
10091 | vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3); | |
10092 | } | |
10093 | ||
fe3ef05c NHE |
10094 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp); |
10095 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip); | |
10096 | } | |
10097 | ||
cd232ad0 NHE |
10098 | /* |
10099 | * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1 | |
10100 | * for running an L2 nested guest. | |
10101 | */ | |
10102 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch) | |
10103 | { | |
10104 | struct vmcs12 *vmcs12; | |
10105 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10106 | int cpu; | |
10107 | struct loaded_vmcs *vmcs02; | |
384bb783 | 10108 | bool ia32e; |
ff651cb6 | 10109 | u32 msr_entry_idx; |
cd232ad0 NHE |
10110 | |
10111 | if (!nested_vmx_check_permission(vcpu) || | |
10112 | !nested_vmx_check_vmcs12(vcpu)) | |
10113 | return 1; | |
10114 | ||
10115 | skip_emulated_instruction(vcpu); | |
10116 | vmcs12 = get_vmcs12(vcpu); | |
10117 | ||
012f83cb AG |
10118 | if (enable_shadow_vmcs) |
10119 | copy_shadow_to_vmcs12(vmx); | |
10120 | ||
7c177938 NHE |
10121 | /* |
10122 | * The nested entry process starts with enforcing various prerequisites | |
10123 | * on vmcs12 as required by the Intel SDM, and act appropriately when | |
10124 | * they fail: As the SDM explains, some conditions should cause the | |
10125 | * instruction to fail, while others will cause the instruction to seem | |
10126 | * to succeed, but return an EXIT_REASON_INVALID_STATE. | |
10127 | * To speed up the normal (success) code path, we should avoid checking | |
10128 | * for misconfigurations which will anyway be caught by the processor | |
10129 | * when using the merged vmcs02. | |
10130 | */ | |
10131 | if (vmcs12->launch_state == launch) { | |
10132 | nested_vmx_failValid(vcpu, | |
10133 | launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS | |
10134 | : VMXERR_VMRESUME_NONLAUNCHED_VMCS); | |
10135 | return 1; | |
10136 | } | |
10137 | ||
6dfacadd JK |
10138 | if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE && |
10139 | vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) { | |
26539bd0 PB |
10140 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); |
10141 | return 1; | |
10142 | } | |
10143 | ||
3af18d9c | 10144 | if (!nested_get_vmcs12_pages(vcpu, vmcs12)) { |
7c177938 NHE |
10145 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); |
10146 | return 1; | |
10147 | } | |
10148 | ||
3af18d9c | 10149 | if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) { |
7c177938 NHE |
10150 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); |
10151 | return 1; | |
10152 | } | |
10153 | ||
f2b93280 WV |
10154 | if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) { |
10155 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
10156 | return 1; | |
10157 | } | |
10158 | ||
e9ac033e EK |
10159 | if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) { |
10160 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
10161 | return 1; | |
10162 | } | |
10163 | ||
7c177938 | 10164 | if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control, |
b9c237bb WV |
10165 | vmx->nested.nested_vmx_true_procbased_ctls_low, |
10166 | vmx->nested.nested_vmx_procbased_ctls_high) || | |
7c177938 | 10167 | !vmx_control_verify(vmcs12->secondary_vm_exec_control, |
b9c237bb WV |
10168 | vmx->nested.nested_vmx_secondary_ctls_low, |
10169 | vmx->nested.nested_vmx_secondary_ctls_high) || | |
7c177938 | 10170 | !vmx_control_verify(vmcs12->pin_based_vm_exec_control, |
b9c237bb WV |
10171 | vmx->nested.nested_vmx_pinbased_ctls_low, |
10172 | vmx->nested.nested_vmx_pinbased_ctls_high) || | |
7c177938 | 10173 | !vmx_control_verify(vmcs12->vm_exit_controls, |
b9c237bb WV |
10174 | vmx->nested.nested_vmx_true_exit_ctls_low, |
10175 | vmx->nested.nested_vmx_exit_ctls_high) || | |
7c177938 | 10176 | !vmx_control_verify(vmcs12->vm_entry_controls, |
b9c237bb WV |
10177 | vmx->nested.nested_vmx_true_entry_ctls_low, |
10178 | vmx->nested.nested_vmx_entry_ctls_high)) | |
7c177938 NHE |
10179 | { |
10180 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
10181 | return 1; | |
10182 | } | |
10183 | ||
10184 | if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) || | |
10185 | ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) { | |
10186 | nested_vmx_failValid(vcpu, | |
10187 | VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); | |
10188 | return 1; | |
10189 | } | |
10190 | ||
b9c237bb | 10191 | if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) || |
7c177938 NHE |
10192 | ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) { |
10193 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10194 | EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT); | |
10195 | return 1; | |
10196 | } | |
10197 | if (vmcs12->vmcs_link_pointer != -1ull) { | |
10198 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10199 | EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR); | |
10200 | return 1; | |
10201 | } | |
10202 | ||
384bb783 | 10203 | /* |
cb0c8cda | 10204 | * If the load IA32_EFER VM-entry control is 1, the following checks |
384bb783 JK |
10205 | * are performed on the field for the IA32_EFER MSR: |
10206 | * - Bits reserved in the IA32_EFER MSR must be 0. | |
10207 | * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of | |
10208 | * the IA-32e mode guest VM-exit control. It must also be identical | |
10209 | * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to | |
10210 | * CR0.PG) is 1. | |
10211 | */ | |
10212 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) { | |
10213 | ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0; | |
10214 | if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) || | |
10215 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) || | |
10216 | ((vmcs12->guest_cr0 & X86_CR0_PG) && | |
10217 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) { | |
10218 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10219 | EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT); | |
10220 | return 1; | |
10221 | } | |
10222 | } | |
10223 | ||
10224 | /* | |
10225 | * If the load IA32_EFER VM-exit control is 1, bits reserved in the | |
10226 | * IA32_EFER MSR must be 0 in the field for that register. In addition, | |
10227 | * the values of the LMA and LME bits in the field must each be that of | |
10228 | * the host address-space size VM-exit control. | |
10229 | */ | |
10230 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) { | |
10231 | ia32e = (vmcs12->vm_exit_controls & | |
10232 | VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0; | |
10233 | if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) || | |
10234 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) || | |
10235 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) { | |
10236 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10237 | EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT); | |
10238 | return 1; | |
10239 | } | |
10240 | } | |
10241 | ||
7c177938 NHE |
10242 | /* |
10243 | * We're finally done with prerequisite checking, and can start with | |
10244 | * the nested entry. | |
10245 | */ | |
10246 | ||
cd232ad0 NHE |
10247 | vmcs02 = nested_get_current_vmcs02(vmx); |
10248 | if (!vmcs02) | |
10249 | return -ENOMEM; | |
10250 | ||
10251 | enter_guest_mode(vcpu); | |
10252 | ||
10253 | vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET); | |
10254 | ||
2996fca0 JK |
10255 | if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) |
10256 | vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
10257 | ||
cd232ad0 NHE |
10258 | cpu = get_cpu(); |
10259 | vmx->loaded_vmcs = vmcs02; | |
10260 | vmx_vcpu_put(vcpu); | |
10261 | vmx_vcpu_load(vcpu, cpu); | |
10262 | vcpu->cpu = cpu; | |
10263 | put_cpu(); | |
10264 | ||
36c3cc42 JK |
10265 | vmx_segment_cache_clear(vmx); |
10266 | ||
cd232ad0 NHE |
10267 | prepare_vmcs02(vcpu, vmcs12); |
10268 | ||
ff651cb6 WV |
10269 | msr_entry_idx = nested_vmx_load_msr(vcpu, |
10270 | vmcs12->vm_entry_msr_load_addr, | |
10271 | vmcs12->vm_entry_msr_load_count); | |
10272 | if (msr_entry_idx) { | |
10273 | leave_guest_mode(vcpu); | |
10274 | vmx_load_vmcs01(vcpu); | |
10275 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10276 | EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx); | |
10277 | return 1; | |
10278 | } | |
10279 | ||
10280 | vmcs12->launch_state = 1; | |
10281 | ||
6dfacadd | 10282 | if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) |
5cb56059 | 10283 | return kvm_vcpu_halt(vcpu); |
6dfacadd | 10284 | |
7af40ad3 JK |
10285 | vmx->nested.nested_run_pending = 1; |
10286 | ||
cd232ad0 NHE |
10287 | /* |
10288 | * Note no nested_vmx_succeed or nested_vmx_fail here. At this point | |
10289 | * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet | |
10290 | * returned as far as L1 is concerned. It will only return (and set | |
10291 | * the success flag) when L2 exits (see nested_vmx_vmexit()). | |
10292 | */ | |
10293 | return 1; | |
10294 | } | |
10295 | ||
4704d0be NHE |
10296 | /* |
10297 | * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date | |
10298 | * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK). | |
10299 | * This function returns the new value we should put in vmcs12.guest_cr0. | |
10300 | * It's not enough to just return the vmcs02 GUEST_CR0. Rather, | |
10301 | * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now | |
10302 | * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0 | |
10303 | * didn't trap the bit, because if L1 did, so would L0). | |
10304 | * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have | |
10305 | * been modified by L2, and L1 knows it. So just leave the old value of | |
10306 | * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0 | |
10307 | * isn't relevant, because if L0 traps this bit it can set it to anything. | |
10308 | * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have | |
10309 | * changed these bits, and therefore they need to be updated, but L0 | |
10310 | * didn't necessarily allow them to be changed in GUEST_CR0 - and rather | |
10311 | * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there. | |
10312 | */ | |
10313 | static inline unsigned long | |
10314 | vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
10315 | { | |
10316 | return | |
10317 | /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) | | |
10318 | /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) | | |
10319 | /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask | | |
10320 | vcpu->arch.cr0_guest_owned_bits)); | |
10321 | } | |
10322 | ||
10323 | static inline unsigned long | |
10324 | vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
10325 | { | |
10326 | return | |
10327 | /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) | | |
10328 | /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) | | |
10329 | /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask | | |
10330 | vcpu->arch.cr4_guest_owned_bits)); | |
10331 | } | |
10332 | ||
5f3d5799 JK |
10333 | static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu, |
10334 | struct vmcs12 *vmcs12) | |
10335 | { | |
10336 | u32 idt_vectoring; | |
10337 | unsigned int nr; | |
10338 | ||
851eb667 | 10339 | if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) { |
5f3d5799 JK |
10340 | nr = vcpu->arch.exception.nr; |
10341 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
10342 | ||
10343 | if (kvm_exception_is_soft(nr)) { | |
10344 | vmcs12->vm_exit_instruction_len = | |
10345 | vcpu->arch.event_exit_inst_len; | |
10346 | idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION; | |
10347 | } else | |
10348 | idt_vectoring |= INTR_TYPE_HARD_EXCEPTION; | |
10349 | ||
10350 | if (vcpu->arch.exception.has_error_code) { | |
10351 | idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK; | |
10352 | vmcs12->idt_vectoring_error_code = | |
10353 | vcpu->arch.exception.error_code; | |
10354 | } | |
10355 | ||
10356 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
cd2633c5 | 10357 | } else if (vcpu->arch.nmi_injected) { |
5f3d5799 JK |
10358 | vmcs12->idt_vectoring_info_field = |
10359 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR; | |
10360 | } else if (vcpu->arch.interrupt.pending) { | |
10361 | nr = vcpu->arch.interrupt.nr; | |
10362 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
10363 | ||
10364 | if (vcpu->arch.interrupt.soft) { | |
10365 | idt_vectoring |= INTR_TYPE_SOFT_INTR; | |
10366 | vmcs12->vm_entry_instruction_len = | |
10367 | vcpu->arch.event_exit_inst_len; | |
10368 | } else | |
10369 | idt_vectoring |= INTR_TYPE_EXT_INTR; | |
10370 | ||
10371 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
10372 | } | |
10373 | } | |
10374 | ||
b6b8a145 JK |
10375 | static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr) |
10376 | { | |
10377 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10378 | ||
f4124500 JK |
10379 | if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) && |
10380 | vmx->nested.preemption_timer_expired) { | |
10381 | if (vmx->nested.nested_run_pending) | |
10382 | return -EBUSY; | |
10383 | nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0); | |
10384 | return 0; | |
10385 | } | |
10386 | ||
b6b8a145 | 10387 | if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) { |
220c5672 JK |
10388 | if (vmx->nested.nested_run_pending || |
10389 | vcpu->arch.interrupt.pending) | |
b6b8a145 JK |
10390 | return -EBUSY; |
10391 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, | |
10392 | NMI_VECTOR | INTR_TYPE_NMI_INTR | | |
10393 | INTR_INFO_VALID_MASK, 0); | |
10394 | /* | |
10395 | * The NMI-triggered VM exit counts as injection: | |
10396 | * clear this one and block further NMIs. | |
10397 | */ | |
10398 | vcpu->arch.nmi_pending = 0; | |
10399 | vmx_set_nmi_mask(vcpu, true); | |
10400 | return 0; | |
10401 | } | |
10402 | ||
10403 | if ((kvm_cpu_has_interrupt(vcpu) || external_intr) && | |
10404 | nested_exit_on_intr(vcpu)) { | |
10405 | if (vmx->nested.nested_run_pending) | |
10406 | return -EBUSY; | |
10407 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0); | |
705699a1 | 10408 | return 0; |
b6b8a145 JK |
10409 | } |
10410 | ||
705699a1 | 10411 | return vmx_complete_nested_posted_interrupt(vcpu); |
b6b8a145 JK |
10412 | } |
10413 | ||
f4124500 JK |
10414 | static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu) |
10415 | { | |
10416 | ktime_t remaining = | |
10417 | hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer); | |
10418 | u64 value; | |
10419 | ||
10420 | if (ktime_to_ns(remaining) <= 0) | |
10421 | return 0; | |
10422 | ||
10423 | value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz; | |
10424 | do_div(value, 1000000); | |
10425 | return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
10426 | } | |
10427 | ||
4704d0be NHE |
10428 | /* |
10429 | * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits | |
10430 | * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12), | |
10431 | * and this function updates it to reflect the changes to the guest state while | |
10432 | * L2 was running (and perhaps made some exits which were handled directly by L0 | |
10433 | * without going back to L1), and to reflect the exit reason. | |
10434 | * Note that we do not have to copy here all VMCS fields, just those that | |
10435 | * could have changed by the L2 guest or the exit - i.e., the guest-state and | |
10436 | * exit-information fields only. Other fields are modified by L1 with VMWRITE, | |
10437 | * which already writes to vmcs12 directly. | |
10438 | */ | |
533558bc JK |
10439 | static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, |
10440 | u32 exit_reason, u32 exit_intr_info, | |
10441 | unsigned long exit_qualification) | |
4704d0be NHE |
10442 | { |
10443 | /* update guest state fields: */ | |
10444 | vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12); | |
10445 | vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12); | |
10446 | ||
4704d0be NHE |
10447 | vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); |
10448 | vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP); | |
10449 | vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS); | |
10450 | ||
10451 | vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR); | |
10452 | vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR); | |
10453 | vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR); | |
10454 | vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR); | |
10455 | vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR); | |
10456 | vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR); | |
10457 | vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR); | |
10458 | vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR); | |
10459 | vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT); | |
10460 | vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT); | |
10461 | vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT); | |
10462 | vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT); | |
10463 | vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT); | |
10464 | vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT); | |
10465 | vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT); | |
10466 | vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT); | |
10467 | vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
10468 | vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
10469 | vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES); | |
10470 | vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES); | |
10471 | vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES); | |
10472 | vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES); | |
10473 | vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES); | |
10474 | vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES); | |
10475 | vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES); | |
10476 | vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES); | |
10477 | vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE); | |
10478 | vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE); | |
10479 | vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE); | |
10480 | vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE); | |
10481 | vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE); | |
10482 | vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE); | |
10483 | vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE); | |
10484 | vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE); | |
10485 | vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE); | |
10486 | vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE); | |
10487 | ||
4704d0be NHE |
10488 | vmcs12->guest_interruptibility_info = |
10489 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
10490 | vmcs12->guest_pending_dbg_exceptions = | |
10491 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS); | |
3edf1e69 JK |
10492 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) |
10493 | vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT; | |
10494 | else | |
10495 | vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE; | |
4704d0be | 10496 | |
f4124500 JK |
10497 | if (nested_cpu_has_preemption_timer(vmcs12)) { |
10498 | if (vmcs12->vm_exit_controls & | |
10499 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER) | |
10500 | vmcs12->vmx_preemption_timer_value = | |
10501 | vmx_get_preemption_timer_value(vcpu); | |
10502 | hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer); | |
10503 | } | |
7854cbca | 10504 | |
3633cfc3 NHE |
10505 | /* |
10506 | * In some cases (usually, nested EPT), L2 is allowed to change its | |
10507 | * own CR3 without exiting. If it has changed it, we must keep it. | |
10508 | * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined | |
10509 | * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12. | |
10510 | * | |
10511 | * Additionally, restore L2's PDPTR to vmcs12. | |
10512 | */ | |
10513 | if (enable_ept) { | |
f3531054 | 10514 | vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3); |
3633cfc3 NHE |
10515 | vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0); |
10516 | vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1); | |
10517 | vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2); | |
10518 | vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3); | |
10519 | } | |
10520 | ||
608406e2 WV |
10521 | if (nested_cpu_has_vid(vmcs12)) |
10522 | vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS); | |
10523 | ||
c18911a2 JK |
10524 | vmcs12->vm_entry_controls = |
10525 | (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) | | |
2961e876 | 10526 | (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE); |
c18911a2 | 10527 | |
2996fca0 JK |
10528 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) { |
10529 | kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7); | |
10530 | vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
10531 | } | |
10532 | ||
4704d0be NHE |
10533 | /* TODO: These cannot have changed unless we have MSR bitmaps and |
10534 | * the relevant bit asks not to trap the change */ | |
b8c07d55 | 10535 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) |
4704d0be | 10536 | vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT); |
10ba54a5 JK |
10537 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER) |
10538 | vmcs12->guest_ia32_efer = vcpu->arch.efer; | |
4704d0be NHE |
10539 | vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS); |
10540 | vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP); | |
10541 | vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP); | |
a87036ad | 10542 | if (kvm_mpx_supported()) |
36be0b9d | 10543 | vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS); |
81dc01f7 WL |
10544 | if (nested_cpu_has_xsaves(vmcs12)) |
10545 | vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP); | |
4704d0be NHE |
10546 | |
10547 | /* update exit information fields: */ | |
10548 | ||
533558bc JK |
10549 | vmcs12->vm_exit_reason = exit_reason; |
10550 | vmcs12->exit_qualification = exit_qualification; | |
4704d0be | 10551 | |
533558bc | 10552 | vmcs12->vm_exit_intr_info = exit_intr_info; |
c0d1c770 JK |
10553 | if ((vmcs12->vm_exit_intr_info & |
10554 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) == | |
10555 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) | |
10556 | vmcs12->vm_exit_intr_error_code = | |
10557 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE); | |
5f3d5799 | 10558 | vmcs12->idt_vectoring_info_field = 0; |
4704d0be NHE |
10559 | vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
10560 | vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
10561 | ||
5f3d5799 JK |
10562 | if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) { |
10563 | /* vm_entry_intr_info_field is cleared on exit. Emulate this | |
10564 | * instead of reading the real value. */ | |
4704d0be | 10565 | vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK; |
5f3d5799 JK |
10566 | |
10567 | /* | |
10568 | * Transfer the event that L0 or L1 may wanted to inject into | |
10569 | * L2 to IDT_VECTORING_INFO_FIELD. | |
10570 | */ | |
10571 | vmcs12_save_pending_event(vcpu, vmcs12); | |
10572 | } | |
10573 | ||
10574 | /* | |
10575 | * Drop what we picked up for L2 via vmx_complete_interrupts. It is | |
10576 | * preserved above and would only end up incorrectly in L1. | |
10577 | */ | |
10578 | vcpu->arch.nmi_injected = false; | |
10579 | kvm_clear_exception_queue(vcpu); | |
10580 | kvm_clear_interrupt_queue(vcpu); | |
4704d0be NHE |
10581 | } |
10582 | ||
10583 | /* | |
10584 | * A part of what we need to when the nested L2 guest exits and we want to | |
10585 | * run its L1 parent, is to reset L1's guest state to the host state specified | |
10586 | * in vmcs12. | |
10587 | * This function is to be called not only on normal nested exit, but also on | |
10588 | * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry | |
10589 | * Failures During or After Loading Guest State"). | |
10590 | * This function should be called when the active VMCS is L1's (vmcs01). | |
10591 | */ | |
733568f9 JK |
10592 | static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, |
10593 | struct vmcs12 *vmcs12) | |
4704d0be | 10594 | { |
21feb4eb ACL |
10595 | struct kvm_segment seg; |
10596 | ||
4704d0be NHE |
10597 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) |
10598 | vcpu->arch.efer = vmcs12->host_ia32_efer; | |
d1fa0352 | 10599 | else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) |
4704d0be NHE |
10600 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); |
10601 | else | |
10602 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
10603 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
10604 | ||
10605 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp); | |
10606 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip); | |
1adfa76a | 10607 | vmx_set_rflags(vcpu, X86_EFLAGS_FIXED); |
4704d0be NHE |
10608 | /* |
10609 | * Note that calling vmx_set_cr0 is important, even if cr0 hasn't | |
10610 | * actually changed, because it depends on the current state of | |
10611 | * fpu_active (which may have changed). | |
10612 | * Note that vmx_set_cr0 refers to efer set above. | |
10613 | */ | |
9e3e4dbf | 10614 | vmx_set_cr0(vcpu, vmcs12->host_cr0); |
4704d0be NHE |
10615 | /* |
10616 | * If we did fpu_activate()/fpu_deactivate() during L2's run, we need | |
10617 | * to apply the same changes to L1's vmcs. We just set cr0 correctly, | |
10618 | * but we also need to update cr0_guest_host_mask and exception_bitmap. | |
10619 | */ | |
10620 | update_exception_bitmap(vcpu); | |
10621 | vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0); | |
10622 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
10623 | ||
10624 | /* | |
10625 | * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01 | |
10626 | * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask(); | |
10627 | */ | |
10628 | vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK); | |
10629 | kvm_set_cr4(vcpu, vmcs12->host_cr4); | |
10630 | ||
29bf08f1 | 10631 | nested_ept_uninit_mmu_context(vcpu); |
155a97a3 | 10632 | |
4704d0be NHE |
10633 | kvm_set_cr3(vcpu, vmcs12->host_cr3); |
10634 | kvm_mmu_reset_context(vcpu); | |
10635 | ||
feaf0c7d GN |
10636 | if (!enable_ept) |
10637 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; | |
10638 | ||
4704d0be NHE |
10639 | if (enable_vpid) { |
10640 | /* | |
10641 | * Trivially support vpid by letting L2s share their parent | |
10642 | * L1's vpid. TODO: move to a more elaborate solution, giving | |
10643 | * each L2 its own vpid and exposing the vpid feature to L1. | |
10644 | */ | |
10645 | vmx_flush_tlb(vcpu); | |
10646 | } | |
10647 | ||
10648 | ||
10649 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs); | |
10650 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp); | |
10651 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip); | |
10652 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base); | |
10653 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base); | |
4704d0be | 10654 | |
36be0b9d PB |
10655 | /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */ |
10656 | if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS) | |
10657 | vmcs_write64(GUEST_BNDCFGS, 0); | |
10658 | ||
44811c02 | 10659 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) { |
4704d0be | 10660 | vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat); |
44811c02 JK |
10661 | vcpu->arch.pat = vmcs12->host_ia32_pat; |
10662 | } | |
4704d0be NHE |
10663 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) |
10664 | vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL, | |
10665 | vmcs12->host_ia32_perf_global_ctrl); | |
503cd0c5 | 10666 | |
21feb4eb ACL |
10667 | /* Set L1 segment info according to Intel SDM |
10668 | 27.5.2 Loading Host Segment and Descriptor-Table Registers */ | |
10669 | seg = (struct kvm_segment) { | |
10670 | .base = 0, | |
10671 | .limit = 0xFFFFFFFF, | |
10672 | .selector = vmcs12->host_cs_selector, | |
10673 | .type = 11, | |
10674 | .present = 1, | |
10675 | .s = 1, | |
10676 | .g = 1 | |
10677 | }; | |
10678 | if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) | |
10679 | seg.l = 1; | |
10680 | else | |
10681 | seg.db = 1; | |
10682 | vmx_set_segment(vcpu, &seg, VCPU_SREG_CS); | |
10683 | seg = (struct kvm_segment) { | |
10684 | .base = 0, | |
10685 | .limit = 0xFFFFFFFF, | |
10686 | .type = 3, | |
10687 | .present = 1, | |
10688 | .s = 1, | |
10689 | .db = 1, | |
10690 | .g = 1 | |
10691 | }; | |
10692 | seg.selector = vmcs12->host_ds_selector; | |
10693 | vmx_set_segment(vcpu, &seg, VCPU_SREG_DS); | |
10694 | seg.selector = vmcs12->host_es_selector; | |
10695 | vmx_set_segment(vcpu, &seg, VCPU_SREG_ES); | |
10696 | seg.selector = vmcs12->host_ss_selector; | |
10697 | vmx_set_segment(vcpu, &seg, VCPU_SREG_SS); | |
10698 | seg.selector = vmcs12->host_fs_selector; | |
10699 | seg.base = vmcs12->host_fs_base; | |
10700 | vmx_set_segment(vcpu, &seg, VCPU_SREG_FS); | |
10701 | seg.selector = vmcs12->host_gs_selector; | |
10702 | seg.base = vmcs12->host_gs_base; | |
10703 | vmx_set_segment(vcpu, &seg, VCPU_SREG_GS); | |
10704 | seg = (struct kvm_segment) { | |
205befd9 | 10705 | .base = vmcs12->host_tr_base, |
21feb4eb ACL |
10706 | .limit = 0x67, |
10707 | .selector = vmcs12->host_tr_selector, | |
10708 | .type = 11, | |
10709 | .present = 1 | |
10710 | }; | |
10711 | vmx_set_segment(vcpu, &seg, VCPU_SREG_TR); | |
10712 | ||
503cd0c5 JK |
10713 | kvm_set_dr(vcpu, 7, 0x400); |
10714 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
ff651cb6 | 10715 | |
3af18d9c WV |
10716 | if (cpu_has_vmx_msr_bitmap()) |
10717 | vmx_set_msr_bitmap(vcpu); | |
10718 | ||
ff651cb6 WV |
10719 | if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr, |
10720 | vmcs12->vm_exit_msr_load_count)) | |
10721 | nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL); | |
4704d0be NHE |
10722 | } |
10723 | ||
10724 | /* | |
10725 | * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1 | |
10726 | * and modify vmcs12 to make it see what it would expect to see there if | |
10727 | * L2 was its real guest. Must only be called when in L2 (is_guest_mode()) | |
10728 | */ | |
533558bc JK |
10729 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
10730 | u32 exit_intr_info, | |
10731 | unsigned long exit_qualification) | |
4704d0be NHE |
10732 | { |
10733 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4704d0be NHE |
10734 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
10735 | ||
5f3d5799 JK |
10736 | /* trying to cancel vmlaunch/vmresume is a bug */ |
10737 | WARN_ON_ONCE(vmx->nested.nested_run_pending); | |
10738 | ||
4704d0be | 10739 | leave_guest_mode(vcpu); |
533558bc JK |
10740 | prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info, |
10741 | exit_qualification); | |
4704d0be | 10742 | |
ff651cb6 WV |
10743 | if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr, |
10744 | vmcs12->vm_exit_msr_store_count)) | |
10745 | nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL); | |
10746 | ||
f3380ca5 WL |
10747 | vmx_load_vmcs01(vcpu); |
10748 | ||
77b0f5d6 BD |
10749 | if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) |
10750 | && nested_exit_intr_ack_set(vcpu)) { | |
10751 | int irq = kvm_cpu_get_interrupt(vcpu); | |
10752 | WARN_ON(irq < 0); | |
10753 | vmcs12->vm_exit_intr_info = irq | | |
10754 | INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR; | |
10755 | } | |
10756 | ||
542060ea JK |
10757 | trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason, |
10758 | vmcs12->exit_qualification, | |
10759 | vmcs12->idt_vectoring_info_field, | |
10760 | vmcs12->vm_exit_intr_info, | |
10761 | vmcs12->vm_exit_intr_error_code, | |
10762 | KVM_ISA_VMX); | |
4704d0be | 10763 | |
8391ce44 PB |
10764 | vm_entry_controls_reset_shadow(vmx); |
10765 | vm_exit_controls_reset_shadow(vmx); | |
36c3cc42 JK |
10766 | vmx_segment_cache_clear(vmx); |
10767 | ||
4704d0be NHE |
10768 | /* if no vmcs02 cache requested, remove the one we used */ |
10769 | if (VMCS02_POOL_SIZE == 0) | |
10770 | nested_free_vmcs02(vmx, vmx->nested.current_vmptr); | |
10771 | ||
10772 | load_vmcs12_host_state(vcpu, vmcs12); | |
10773 | ||
9314006d | 10774 | /* Update any VMCS fields that might have changed while L2 ran */ |
4704d0be | 10775 | vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset); |
9314006d PB |
10776 | if (vmx->hv_deadline_tsc == -1) |
10777 | vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL, | |
10778 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
10779 | else | |
10780 | vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL, | |
10781 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
4704d0be NHE |
10782 | |
10783 | /* This is needed for same reason as it was needed in prepare_vmcs02 */ | |
10784 | vmx->host_rsp = 0; | |
10785 | ||
10786 | /* Unpin physical memory we referred to in vmcs02 */ | |
10787 | if (vmx->nested.apic_access_page) { | |
10788 | nested_release_page(vmx->nested.apic_access_page); | |
48d89b92 | 10789 | vmx->nested.apic_access_page = NULL; |
4704d0be | 10790 | } |
a7c0b07d WL |
10791 | if (vmx->nested.virtual_apic_page) { |
10792 | nested_release_page(vmx->nested.virtual_apic_page); | |
48d89b92 | 10793 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 10794 | } |
705699a1 WV |
10795 | if (vmx->nested.pi_desc_page) { |
10796 | kunmap(vmx->nested.pi_desc_page); | |
10797 | nested_release_page(vmx->nested.pi_desc_page); | |
10798 | vmx->nested.pi_desc_page = NULL; | |
10799 | vmx->nested.pi_desc = NULL; | |
10800 | } | |
4704d0be | 10801 | |
38b99173 TC |
10802 | /* |
10803 | * We are now running in L2, mmu_notifier will force to reload the | |
10804 | * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1. | |
10805 | */ | |
10806 | kvm_vcpu_reload_apic_access_page(vcpu); | |
10807 | ||
4704d0be NHE |
10808 | /* |
10809 | * Exiting from L2 to L1, we're now back to L1 which thinks it just | |
10810 | * finished a VMLAUNCH or VMRESUME instruction, so we need to set the | |
10811 | * success or failure flag accordingly. | |
10812 | */ | |
10813 | if (unlikely(vmx->fail)) { | |
10814 | vmx->fail = 0; | |
10815 | nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
10816 | } else | |
10817 | nested_vmx_succeed(vcpu); | |
012f83cb AG |
10818 | if (enable_shadow_vmcs) |
10819 | vmx->nested.sync_shadow_vmcs = true; | |
b6b8a145 JK |
10820 | |
10821 | /* in case we halted in L2 */ | |
10822 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
4704d0be NHE |
10823 | } |
10824 | ||
42124925 JK |
10825 | /* |
10826 | * Forcibly leave nested mode in order to be able to reset the VCPU later on. | |
10827 | */ | |
10828 | static void vmx_leave_nested(struct kvm_vcpu *vcpu) | |
10829 | { | |
10830 | if (is_guest_mode(vcpu)) | |
533558bc | 10831 | nested_vmx_vmexit(vcpu, -1, 0, 0); |
42124925 JK |
10832 | free_nested(to_vmx(vcpu)); |
10833 | } | |
10834 | ||
7c177938 NHE |
10835 | /* |
10836 | * L1's failure to enter L2 is a subset of a normal exit, as explained in | |
10837 | * 23.7 "VM-entry failures during or after loading guest state" (this also | |
10838 | * lists the acceptable exit-reason and exit-qualification parameters). | |
10839 | * It should only be called before L2 actually succeeded to run, and when | |
10840 | * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss). | |
10841 | */ | |
10842 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, | |
10843 | struct vmcs12 *vmcs12, | |
10844 | u32 reason, unsigned long qualification) | |
10845 | { | |
10846 | load_vmcs12_host_state(vcpu, vmcs12); | |
10847 | vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY; | |
10848 | vmcs12->exit_qualification = qualification; | |
10849 | nested_vmx_succeed(vcpu); | |
012f83cb AG |
10850 | if (enable_shadow_vmcs) |
10851 | to_vmx(vcpu)->nested.sync_shadow_vmcs = true; | |
7c177938 NHE |
10852 | } |
10853 | ||
8a76d7f2 JR |
10854 | static int vmx_check_intercept(struct kvm_vcpu *vcpu, |
10855 | struct x86_instruction_info *info, | |
10856 | enum x86_intercept_stage stage) | |
10857 | { | |
10858 | return X86EMUL_CONTINUE; | |
10859 | } | |
10860 | ||
64672c95 YJ |
10861 | #ifdef CONFIG_X86_64 |
10862 | /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ | |
10863 | static inline int u64_shl_div_u64(u64 a, unsigned int shift, | |
10864 | u64 divisor, u64 *result) | |
10865 | { | |
10866 | u64 low = a << shift, high = a >> (64 - shift); | |
10867 | ||
10868 | /* To avoid the overflow on divq */ | |
10869 | if (high >= divisor) | |
10870 | return 1; | |
10871 | ||
10872 | /* Low hold the result, high hold rem which is discarded */ | |
10873 | asm("divq %2\n\t" : "=a" (low), "=d" (high) : | |
10874 | "rm" (divisor), "0" (low), "1" (high)); | |
10875 | *result = low; | |
10876 | ||
10877 | return 0; | |
10878 | } | |
10879 | ||
10880 | static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc) | |
10881 | { | |
10882 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9175d2e9 PB |
10883 | u64 tscl = rdtsc(); |
10884 | u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); | |
10885 | u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; | |
64672c95 YJ |
10886 | |
10887 | /* Convert to host delta tsc if tsc scaling is enabled */ | |
10888 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && | |
10889 | u64_shl_div_u64(delta_tsc, | |
10890 | kvm_tsc_scaling_ratio_frac_bits, | |
10891 | vcpu->arch.tsc_scaling_ratio, | |
10892 | &delta_tsc)) | |
10893 | return -ERANGE; | |
10894 | ||
10895 | /* | |
10896 | * If the delta tsc can't fit in the 32 bit after the multi shift, | |
10897 | * we can't use the preemption timer. | |
10898 | * It's possible that it fits on later vmentries, but checking | |
10899 | * on every vmentry is costly so we just use an hrtimer. | |
10900 | */ | |
10901 | if (delta_tsc >> (cpu_preemption_timer_multi + 32)) | |
10902 | return -ERANGE; | |
10903 | ||
10904 | vmx->hv_deadline_tsc = tscl + delta_tsc; | |
10905 | vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL, | |
10906 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
10907 | return 0; | |
10908 | } | |
10909 | ||
10910 | static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) | |
10911 | { | |
10912 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10913 | vmx->hv_deadline_tsc = -1; | |
10914 | vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL, | |
10915 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
10916 | } | |
10917 | #endif | |
10918 | ||
48d89b92 | 10919 | static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) |
ae97a3b8 | 10920 | { |
b4a2d31d RK |
10921 | if (ple_gap) |
10922 | shrink_ple_window(vcpu); | |
ae97a3b8 RK |
10923 | } |
10924 | ||
843e4330 KH |
10925 | static void vmx_slot_enable_log_dirty(struct kvm *kvm, |
10926 | struct kvm_memory_slot *slot) | |
10927 | { | |
10928 | kvm_mmu_slot_leaf_clear_dirty(kvm, slot); | |
10929 | kvm_mmu_slot_largepage_remove_write_access(kvm, slot); | |
10930 | } | |
10931 | ||
10932 | static void vmx_slot_disable_log_dirty(struct kvm *kvm, | |
10933 | struct kvm_memory_slot *slot) | |
10934 | { | |
10935 | kvm_mmu_slot_set_dirty(kvm, slot); | |
10936 | } | |
10937 | ||
10938 | static void vmx_flush_log_dirty(struct kvm *kvm) | |
10939 | { | |
10940 | kvm_flush_pml_buffers(kvm); | |
10941 | } | |
10942 | ||
10943 | static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, | |
10944 | struct kvm_memory_slot *memslot, | |
10945 | gfn_t offset, unsigned long mask) | |
10946 | { | |
10947 | kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); | |
10948 | } | |
10949 | ||
bf9f6ac8 FW |
10950 | /* |
10951 | * This routine does the following things for vCPU which is going | |
10952 | * to be blocked if VT-d PI is enabled. | |
10953 | * - Store the vCPU to the wakeup list, so when interrupts happen | |
10954 | * we can find the right vCPU to wake up. | |
10955 | * - Change the Posted-interrupt descriptor as below: | |
10956 | * 'NDST' <-- vcpu->pre_pcpu | |
10957 | * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR | |
10958 | * - If 'ON' is set during this process, which means at least one | |
10959 | * interrupt is posted for this vCPU, we cannot block it, in | |
10960 | * this case, return 1, otherwise, return 0. | |
10961 | * | |
10962 | */ | |
bc22512b | 10963 | static int pi_pre_block(struct kvm_vcpu *vcpu) |
bf9f6ac8 FW |
10964 | { |
10965 | unsigned long flags; | |
10966 | unsigned int dest; | |
10967 | struct pi_desc old, new; | |
10968 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
10969 | ||
10970 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
10971 | !irq_remapping_cap(IRQ_POSTING_CAP)) | |
10972 | return 0; | |
10973 | ||
10974 | vcpu->pre_pcpu = vcpu->cpu; | |
10975 | spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock, | |
10976 | vcpu->pre_pcpu), flags); | |
10977 | list_add_tail(&vcpu->blocked_vcpu_list, | |
10978 | &per_cpu(blocked_vcpu_on_cpu, | |
10979 | vcpu->pre_pcpu)); | |
10980 | spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock, | |
10981 | vcpu->pre_pcpu), flags); | |
10982 | ||
10983 | do { | |
10984 | old.control = new.control = pi_desc->control; | |
10985 | ||
10986 | /* | |
10987 | * We should not block the vCPU if | |
10988 | * an interrupt is posted for it. | |
10989 | */ | |
10990 | if (pi_test_on(pi_desc) == 1) { | |
10991 | spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock, | |
10992 | vcpu->pre_pcpu), flags); | |
10993 | list_del(&vcpu->blocked_vcpu_list); | |
10994 | spin_unlock_irqrestore( | |
10995 | &per_cpu(blocked_vcpu_on_cpu_lock, | |
10996 | vcpu->pre_pcpu), flags); | |
10997 | vcpu->pre_pcpu = -1; | |
10998 | ||
10999 | return 1; | |
11000 | } | |
11001 | ||
11002 | WARN((pi_desc->sn == 1), | |
11003 | "Warning: SN field of posted-interrupts " | |
11004 | "is set before blocking\n"); | |
11005 | ||
11006 | /* | |
11007 | * Since vCPU can be preempted during this process, | |
11008 | * vcpu->cpu could be different with pre_pcpu, we | |
11009 | * need to set pre_pcpu as the destination of wakeup | |
11010 | * notification event, then we can find the right vCPU | |
11011 | * to wakeup in wakeup handler if interrupts happen | |
11012 | * when the vCPU is in blocked state. | |
11013 | */ | |
11014 | dest = cpu_physical_id(vcpu->pre_pcpu); | |
11015 | ||
11016 | if (x2apic_enabled()) | |
11017 | new.ndst = dest; | |
11018 | else | |
11019 | new.ndst = (dest << 8) & 0xFF00; | |
11020 | ||
11021 | /* set 'NV' to 'wakeup vector' */ | |
11022 | new.nv = POSTED_INTR_WAKEUP_VECTOR; | |
11023 | } while (cmpxchg(&pi_desc->control, old.control, | |
11024 | new.control) != old.control); | |
11025 | ||
11026 | return 0; | |
11027 | } | |
11028 | ||
bc22512b YJ |
11029 | static int vmx_pre_block(struct kvm_vcpu *vcpu) |
11030 | { | |
11031 | if (pi_pre_block(vcpu)) | |
11032 | return 1; | |
11033 | ||
64672c95 YJ |
11034 | if (kvm_lapic_hv_timer_in_use(vcpu)) |
11035 | kvm_lapic_switch_to_sw_timer(vcpu); | |
11036 | ||
bc22512b YJ |
11037 | return 0; |
11038 | } | |
11039 | ||
11040 | static void pi_post_block(struct kvm_vcpu *vcpu) | |
bf9f6ac8 FW |
11041 | { |
11042 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
11043 | struct pi_desc old, new; | |
11044 | unsigned int dest; | |
11045 | unsigned long flags; | |
11046 | ||
11047 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
11048 | !irq_remapping_cap(IRQ_POSTING_CAP)) | |
11049 | return; | |
11050 | ||
11051 | do { | |
11052 | old.control = new.control = pi_desc->control; | |
11053 | ||
11054 | dest = cpu_physical_id(vcpu->cpu); | |
11055 | ||
11056 | if (x2apic_enabled()) | |
11057 | new.ndst = dest; | |
11058 | else | |
11059 | new.ndst = (dest << 8) & 0xFF00; | |
11060 | ||
11061 | /* Allow posting non-urgent interrupts */ | |
11062 | new.sn = 0; | |
11063 | ||
11064 | /* set 'NV' to 'notification vector' */ | |
11065 | new.nv = POSTED_INTR_VECTOR; | |
11066 | } while (cmpxchg(&pi_desc->control, old.control, | |
11067 | new.control) != old.control); | |
11068 | ||
11069 | if(vcpu->pre_pcpu != -1) { | |
11070 | spin_lock_irqsave( | |
11071 | &per_cpu(blocked_vcpu_on_cpu_lock, | |
11072 | vcpu->pre_pcpu), flags); | |
11073 | list_del(&vcpu->blocked_vcpu_list); | |
11074 | spin_unlock_irqrestore( | |
11075 | &per_cpu(blocked_vcpu_on_cpu_lock, | |
11076 | vcpu->pre_pcpu), flags); | |
11077 | vcpu->pre_pcpu = -1; | |
11078 | } | |
11079 | } | |
11080 | ||
bc22512b YJ |
11081 | static void vmx_post_block(struct kvm_vcpu *vcpu) |
11082 | { | |
64672c95 YJ |
11083 | if (kvm_x86_ops->set_hv_timer) |
11084 | kvm_lapic_switch_to_hv_timer(vcpu); | |
11085 | ||
bc22512b YJ |
11086 | pi_post_block(vcpu); |
11087 | } | |
11088 | ||
efc64404 FW |
11089 | /* |
11090 | * vmx_update_pi_irte - set IRTE for Posted-Interrupts | |
11091 | * | |
11092 | * @kvm: kvm | |
11093 | * @host_irq: host irq of the interrupt | |
11094 | * @guest_irq: gsi of the interrupt | |
11095 | * @set: set or unset PI | |
11096 | * returns 0 on success, < 0 on failure | |
11097 | */ | |
11098 | static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, | |
11099 | uint32_t guest_irq, bool set) | |
11100 | { | |
11101 | struct kvm_kernel_irq_routing_entry *e; | |
11102 | struct kvm_irq_routing_table *irq_rt; | |
11103 | struct kvm_lapic_irq irq; | |
11104 | struct kvm_vcpu *vcpu; | |
11105 | struct vcpu_data vcpu_info; | |
11106 | int idx, ret = -EINVAL; | |
11107 | ||
11108 | if (!kvm_arch_has_assigned_device(kvm) || | |
11109 | !irq_remapping_cap(IRQ_POSTING_CAP)) | |
11110 | return 0; | |
11111 | ||
11112 | idx = srcu_read_lock(&kvm->irq_srcu); | |
11113 | irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); | |
11114 | BUG_ON(guest_irq >= irq_rt->nr_rt_entries); | |
11115 | ||
11116 | hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { | |
11117 | if (e->type != KVM_IRQ_ROUTING_MSI) | |
11118 | continue; | |
11119 | /* | |
11120 | * VT-d PI cannot support posting multicast/broadcast | |
11121 | * interrupts to a vCPU, we still use interrupt remapping | |
11122 | * for these kind of interrupts. | |
11123 | * | |
11124 | * For lowest-priority interrupts, we only support | |
11125 | * those with single CPU as the destination, e.g. user | |
11126 | * configures the interrupts via /proc/irq or uses | |
11127 | * irqbalance to make the interrupts single-CPU. | |
11128 | * | |
11129 | * We will support full lowest-priority interrupt later. | |
11130 | */ | |
11131 | ||
37131313 | 11132 | kvm_set_msi_irq(kvm, e, &irq); |
23a1c257 FW |
11133 | if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) { |
11134 | /* | |
11135 | * Make sure the IRTE is in remapped mode if | |
11136 | * we don't handle it in posted mode. | |
11137 | */ | |
11138 | ret = irq_set_vcpu_affinity(host_irq, NULL); | |
11139 | if (ret < 0) { | |
11140 | printk(KERN_INFO | |
11141 | "failed to back to remapped mode, irq: %u\n", | |
11142 | host_irq); | |
11143 | goto out; | |
11144 | } | |
11145 | ||
efc64404 | 11146 | continue; |
23a1c257 | 11147 | } |
efc64404 FW |
11148 | |
11149 | vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); | |
11150 | vcpu_info.vector = irq.vector; | |
11151 | ||
b6ce9780 | 11152 | trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi, |
efc64404 FW |
11153 | vcpu_info.vector, vcpu_info.pi_desc_addr, set); |
11154 | ||
11155 | if (set) | |
11156 | ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); | |
11157 | else { | |
11158 | /* suppress notification event before unposting */ | |
11159 | pi_set_sn(vcpu_to_pi_desc(vcpu)); | |
11160 | ret = irq_set_vcpu_affinity(host_irq, NULL); | |
11161 | pi_clear_sn(vcpu_to_pi_desc(vcpu)); | |
11162 | } | |
11163 | ||
11164 | if (ret < 0) { | |
11165 | printk(KERN_INFO "%s: failed to update PI IRTE\n", | |
11166 | __func__); | |
11167 | goto out; | |
11168 | } | |
11169 | } | |
11170 | ||
11171 | ret = 0; | |
11172 | out: | |
11173 | srcu_read_unlock(&kvm->irq_srcu, idx); | |
11174 | return ret; | |
11175 | } | |
11176 | ||
c45dcc71 AR |
11177 | static void vmx_setup_mce(struct kvm_vcpu *vcpu) |
11178 | { | |
11179 | if (vcpu->arch.mcg_cap & MCG_LMCE_P) | |
11180 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= | |
11181 | FEATURE_CONTROL_LMCE; | |
11182 | else | |
11183 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= | |
11184 | ~FEATURE_CONTROL_LMCE; | |
11185 | } | |
11186 | ||
cbdd1bea | 11187 | static struct kvm_x86_ops vmx_x86_ops = { |
6aa8b732 AK |
11188 | .cpu_has_kvm_support = cpu_has_kvm_support, |
11189 | .disabled_by_bios = vmx_disabled_by_bios, | |
11190 | .hardware_setup = hardware_setup, | |
11191 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 11192 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
11193 | .hardware_enable = hardware_enable, |
11194 | .hardware_disable = hardware_disable, | |
04547156 | 11195 | .cpu_has_accelerated_tpr = report_flexpriority, |
6d396b55 | 11196 | .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase, |
6aa8b732 AK |
11197 | |
11198 | .vcpu_create = vmx_create_vcpu, | |
11199 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 11200 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 11201 | |
04d2cc77 | 11202 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
11203 | .vcpu_load = vmx_vcpu_load, |
11204 | .vcpu_put = vmx_vcpu_put, | |
11205 | ||
a96036b8 | 11206 | .update_bp_intercept = update_exception_bitmap, |
6aa8b732 AK |
11207 | .get_msr = vmx_get_msr, |
11208 | .set_msr = vmx_set_msr, | |
11209 | .get_segment_base = vmx_get_segment_base, | |
11210 | .get_segment = vmx_get_segment, | |
11211 | .set_segment = vmx_set_segment, | |
2e4d2653 | 11212 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 11213 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
e8467fda | 11214 | .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, |
aff48baa | 11215 | .decache_cr3 = vmx_decache_cr3, |
25c4c276 | 11216 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 11217 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
11218 | .set_cr3 = vmx_set_cr3, |
11219 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 11220 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
11221 | .get_idt = vmx_get_idt, |
11222 | .set_idt = vmx_set_idt, | |
11223 | .get_gdt = vmx_get_gdt, | |
11224 | .set_gdt = vmx_set_gdt, | |
73aaf249 JK |
11225 | .get_dr6 = vmx_get_dr6, |
11226 | .set_dr6 = vmx_set_dr6, | |
020df079 | 11227 | .set_dr7 = vmx_set_dr7, |
81908bf4 | 11228 | .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, |
5fdbf976 | 11229 | .cache_reg = vmx_cache_reg, |
6aa8b732 AK |
11230 | .get_rflags = vmx_get_rflags, |
11231 | .set_rflags = vmx_set_rflags, | |
be94f6b7 HH |
11232 | |
11233 | .get_pkru = vmx_get_pkru, | |
11234 | ||
0fdd74f7 | 11235 | .fpu_activate = vmx_fpu_activate, |
02daab21 | 11236 | .fpu_deactivate = vmx_fpu_deactivate, |
6aa8b732 AK |
11237 | |
11238 | .tlb_flush = vmx_flush_tlb, | |
6aa8b732 | 11239 | |
6aa8b732 | 11240 | .run = vmx_vcpu_run, |
6062d012 | 11241 | .handle_exit = vmx_handle_exit, |
6aa8b732 | 11242 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
11243 | .set_interrupt_shadow = vmx_set_interrupt_shadow, |
11244 | .get_interrupt_shadow = vmx_get_interrupt_shadow, | |
102d8325 | 11245 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 | 11246 | .set_irq = vmx_inject_irq, |
95ba8273 | 11247 | .set_nmi = vmx_inject_nmi, |
298101da | 11248 | .queue_exception = vmx_queue_exception, |
b463a6f7 | 11249 | .cancel_injection = vmx_cancel_injection, |
78646121 | 11250 | .interrupt_allowed = vmx_interrupt_allowed, |
95ba8273 | 11251 | .nmi_allowed = vmx_nmi_allowed, |
3cfc3092 JK |
11252 | .get_nmi_mask = vmx_get_nmi_mask, |
11253 | .set_nmi_mask = vmx_set_nmi_mask, | |
95ba8273 GN |
11254 | .enable_nmi_window = enable_nmi_window, |
11255 | .enable_irq_window = enable_irq_window, | |
11256 | .update_cr8_intercept = update_cr8_intercept, | |
8d14695f | 11257 | .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode, |
38b99173 | 11258 | .set_apic_access_page_addr = vmx_set_apic_access_page_addr, |
d62caabb AS |
11259 | .get_enable_apicv = vmx_get_enable_apicv, |
11260 | .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, | |
c7c9c56c YZ |
11261 | .load_eoi_exitmap = vmx_load_eoi_exitmap, |
11262 | .hwapic_irr_update = vmx_hwapic_irr_update, | |
11263 | .hwapic_isr_update = vmx_hwapic_isr_update, | |
a20ed54d YZ |
11264 | .sync_pir_to_irr = vmx_sync_pir_to_irr, |
11265 | .deliver_posted_interrupt = vmx_deliver_posted_interrupt, | |
95ba8273 | 11266 | |
cbc94022 | 11267 | .set_tss_addr = vmx_set_tss_addr, |
67253af5 | 11268 | .get_tdp_level = get_ept_level, |
4b12f0de | 11269 | .get_mt_mask = vmx_get_mt_mask, |
229456fc | 11270 | |
586f9607 | 11271 | .get_exit_info = vmx_get_exit_info, |
586f9607 | 11272 | |
17cc3935 | 11273 | .get_lpage_level = vmx_get_lpage_level, |
0e851880 SY |
11274 | |
11275 | .cpuid_update = vmx_cpuid_update, | |
4e47c7a6 SY |
11276 | |
11277 | .rdtscp_supported = vmx_rdtscp_supported, | |
ad756a16 | 11278 | .invpcid_supported = vmx_invpcid_supported, |
d4330ef2 JR |
11279 | |
11280 | .set_supported_cpuid = vmx_set_supported_cpuid, | |
f5f48ee1 SY |
11281 | |
11282 | .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, | |
99e3e30a | 11283 | |
ba904635 | 11284 | .read_tsc_offset = vmx_read_tsc_offset, |
99e3e30a | 11285 | .write_tsc_offset = vmx_write_tsc_offset, |
58ea6767 | 11286 | .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest, |
d5c1785d | 11287 | .read_l1_tsc = vmx_read_l1_tsc, |
1c97f0a0 JR |
11288 | |
11289 | .set_tdp_cr3 = vmx_set_cr3, | |
8a76d7f2 JR |
11290 | |
11291 | .check_intercept = vmx_check_intercept, | |
a547c6db | 11292 | .handle_external_intr = vmx_handle_external_intr, |
da8999d3 | 11293 | .mpx_supported = vmx_mpx_supported, |
55412b2e | 11294 | .xsaves_supported = vmx_xsaves_supported, |
b6b8a145 JK |
11295 | |
11296 | .check_nested_events = vmx_check_nested_events, | |
ae97a3b8 RK |
11297 | |
11298 | .sched_in = vmx_sched_in, | |
843e4330 KH |
11299 | |
11300 | .slot_enable_log_dirty = vmx_slot_enable_log_dirty, | |
11301 | .slot_disable_log_dirty = vmx_slot_disable_log_dirty, | |
11302 | .flush_log_dirty = vmx_flush_log_dirty, | |
11303 | .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, | |
25462f7f | 11304 | |
bf9f6ac8 FW |
11305 | .pre_block = vmx_pre_block, |
11306 | .post_block = vmx_post_block, | |
11307 | ||
25462f7f | 11308 | .pmu_ops = &intel_pmu_ops, |
efc64404 FW |
11309 | |
11310 | .update_pi_irte = vmx_update_pi_irte, | |
64672c95 YJ |
11311 | |
11312 | #ifdef CONFIG_X86_64 | |
11313 | .set_hv_timer = vmx_set_hv_timer, | |
11314 | .cancel_hv_timer = vmx_cancel_hv_timer, | |
11315 | #endif | |
c45dcc71 AR |
11316 | |
11317 | .setup_mce = vmx_setup_mce, | |
6aa8b732 AK |
11318 | }; |
11319 | ||
11320 | static int __init vmx_init(void) | |
11321 | { | |
34a1cd60 TC |
11322 | int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), |
11323 | __alignof__(struct vcpu_vmx), THIS_MODULE); | |
fdef3ad1 | 11324 | if (r) |
34a1cd60 | 11325 | return r; |
25c5f225 | 11326 | |
2965faa5 | 11327 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
11328 | rcu_assign_pointer(crash_vmclear_loaded_vmcss, |
11329 | crash_vmclear_local_loaded_vmcss); | |
11330 | #endif | |
11331 | ||
fdef3ad1 | 11332 | return 0; |
6aa8b732 AK |
11333 | } |
11334 | ||
11335 | static void __exit vmx_exit(void) | |
11336 | { | |
2965faa5 | 11337 | #ifdef CONFIG_KEXEC_CORE |
3b63a43f | 11338 | RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); |
8f536b76 ZY |
11339 | synchronize_rcu(); |
11340 | #endif | |
11341 | ||
cb498ea2 | 11342 | kvm_exit(); |
6aa8b732 AK |
11343 | } |
11344 | ||
11345 | module_init(vmx_init) | |
11346 | module_exit(vmx_exit) |