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KVM: no longer EXPERIMENTAL
[linux-block.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
6aa8b732 19#include "vmx.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
e495606d 29
6aa8b732 30#include <asm/io.h>
3b3be0d1 31#include <asm/desc.h>
6aa8b732 32
6aa8b732
AK		 33MODULE_AUTHOR("Qumranet");
34MODULE_LICENSE("GPL");
35
c7addb90
AK		 36static int bypass_guest_pf = 1;
37module_param(bypass_guest_pf, bool, 0);
38
2384d2b3
SY		 39static int enable_vpid = 1;
40module_param(enable_vpid, bool, 0);
41
a2fa3e9f
GH		 42struct vmcs {
43 u32 revision_id;
44 u32 abort;
45 char data[0];
46};
47
48struct vcpu_vmx {
fb3f0f51 49 struct kvm_vcpu vcpu;
a2fa3e9f 50 int launched;
29bd8a78 51 u8 fail;
1155f76a 52 u32 idt_vectoring_info;
a2fa3e9f
GH		 53 struct kvm_msr_entry *guest_msrs;
54 struct kvm_msr_entry *host_msrs;
55 int nmsrs;
56 int save_nmsrs;
57 int msr_offset_efer;
58#ifdef CONFIG_X86_64
59 int msr_offset_kernel_gs_base;
60#endif
61 struct vmcs *vmcs;
62 struct {
63 int loaded;
64 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 65 int gs_ldt_reload_needed;
66 int fs_reload_needed;
51c6cf66 67 int guest_efer_loaded;
d77c26fc 68 } host_state;
9c8cba37
AK		 69 struct {
70 struct {
71 bool pending;
72 u8 vector;
73 unsigned rip;
74 } irq;
75 } rmode;
2384d2b3 76 int vpid;
a2fa3e9f
GH		 77};
78
79static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
80{
fb3f0f51 81 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 82}
83
75880a01
AK		 84static int init_rmode_tss(struct kvm *kvm);
85
6aa8b732
AK		 86static DEFINE_PER_CPU(struct vmcs *, vmxarea);
87static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
88
fdef3ad1
HQ		 89static struct page *vmx_io_bitmap_a;
90static struct page *vmx_io_bitmap_b;
91
2384d2b3
SY		 92static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
93static DEFINE_SPINLOCK(vmx_vpid_lock);
94
1c3d14fe 95static struct vmcs_config {
6aa8b732
AK		 96 int size;
97 int order;
98 u32 revision_id;
1c3d14fe
YS		 99 u32 pin_based_exec_ctrl;
100 u32 cpu_based_exec_ctrl;
f78e0e2e 101 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 102 u32 vmexit_ctrl;
103 u32 vmentry_ctrl;
104} vmcs_config;
6aa8b732
AK		 105
106#define VMX_SEGMENT_FIELD(seg) \
107 [VCPU_SREG_##seg] = { \
108 .selector = GUEST_##seg##_SELECTOR, \
109 .base = GUEST_##seg##_BASE, \
110 .limit = GUEST_##seg##_LIMIT, \
111 .ar_bytes = GUEST_##seg##_AR_BYTES, \
112 }
113
114static struct kvm_vmx_segment_field {
115 unsigned selector;
116 unsigned base;
117 unsigned limit;
118 unsigned ar_bytes;
119} kvm_vmx_segment_fields[] = {
120 VMX_SEGMENT_FIELD(CS),
121 VMX_SEGMENT_FIELD(DS),
122 VMX_SEGMENT_FIELD(ES),
123 VMX_SEGMENT_FIELD(FS),
124 VMX_SEGMENT_FIELD(GS),
125 VMX_SEGMENT_FIELD(SS),
126 VMX_SEGMENT_FIELD(TR),
127 VMX_SEGMENT_FIELD(LDTR),
128};
129
4d56c8a7
AK		 130/*
131 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
132 * away by decrementing the array size.
133 */
6aa8b732 134static const u32 vmx_msr_index[] = {
05b3e0c2 135#ifdef CONFIG_X86_64
6aa8b732
AK		 136 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
137#endif
138 MSR_EFER, MSR_K6_STAR,
139};
9d8f549d 140#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 141
a2fa3e9f
GH		 142static void load_msrs(struct kvm_msr_entry *e, int n)
143{
144 int i;
145
146 for (i = 0; i < n; ++i)
147 wrmsrl(e[i].index, e[i].data);
148}
149
150static void save_msrs(struct kvm_msr_entry *e, int n)
151{
152 int i;
153
154 for (i = 0; i < n; ++i)
155 rdmsrl(e[i].index, e[i].data);
156}
157
6aa8b732
AK		 158static inline int is_page_fault(u32 intr_info)
159{
160 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
161 INTR_INFO_VALID_MASK)) ==
162 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
163}
164
2ab455cc
AL		 165static inline int is_no_device(u32 intr_info)
166{
167 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
168 INTR_INFO_VALID_MASK)) ==
169 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
170}
171
7aa81cc0
AL		 172static inline int is_invalid_opcode(u32 intr_info)
173{
174 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
175 INTR_INFO_VALID_MASK)) ==
176 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
177}
178
6aa8b732
AK		 179static inline int is_external_interrupt(u32 intr_info)
180{
181 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
182 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
183}
184
6e5d865c
YS		 185static inline int cpu_has_vmx_tpr_shadow(void)
186{
187 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
188}
189
190static inline int vm_need_tpr_shadow(struct kvm *kvm)
191{
192 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
193}
194
f78e0e2e
SY		 195static inline int cpu_has_secondary_exec_ctrls(void)
196{
197 return (vmcs_config.cpu_based_exec_ctrl &
198 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
199}
200
774ead3a 201static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e
SY		 202{
203 return (vmcs_config.cpu_based_2nd_exec_ctrl &
204 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
205}
206
207static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
208{
209 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
210 (irqchip_in_kernel(kvm)));
211}
212
2384d2b3
SY		 213static inline int cpu_has_vmx_vpid(void)
214{
215 return (vmcs_config.cpu_based_2nd_exec_ctrl &
216 SECONDARY_EXEC_ENABLE_VPID);
217}
218
8b9cf98c 219static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 220{
221 int i;
222
a2fa3e9f
GH		 223 for (i = 0; i < vmx->nmsrs; ++i)
224 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 225 return i;
226 return -1;
227}
228
2384d2b3
SY		 229static inline void __invvpid(int ext, u16 vpid, gva_t gva)
230{
231 struct {
232 u64 vpid : 16;
233 u64 rsvd : 48;
234 u64 gva;
235 } operand = { vpid, 0, gva };
236
237 asm volatile (ASM_VMX_INVVPID
238 /* CF==1 or ZF==1 --> rc = -1 */
239 "; ja 1f ; ud2 ; 1:"
240 : : "a"(&operand), "c"(ext) : "cc", "memory");
241}
242
8b9cf98c 243static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 244{
245 int i;
246
8b9cf98c 247 i = __find_msr_index(vmx, msr);
a75beee6 248 if (i >= 0)
a2fa3e9f 249 return &vmx->guest_msrs[i];
8b6d44c7 250 return NULL;
7725f0ba
AK		 251}
252
6aa8b732
AK		 253static void vmcs_clear(struct vmcs *vmcs)
254{
255 u64 phys_addr = __pa(vmcs);
256 u8 error;
257
258 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
259 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
260 : "cc", "memory");
261 if (error)
262 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
263 vmcs, phys_addr);
264}
265
266static void __vcpu_clear(void *arg)
267{
8b9cf98c 268 struct vcpu_vmx *vmx = arg;
d3b2c338 269 int cpu = raw_smp_processor_id();
6aa8b732 270
8b9cf98c 271 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 272 vmcs_clear(vmx->vmcs);
273 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 274 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 275 rdtscll(vmx->vcpu.arch.host_tsc);
6aa8b732
AK		 276}
277
8b9cf98c 278static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 279{
eae5ecb5
AK		 280 if (vmx->vcpu.cpu == -1)
281 return;
f566e09f 282 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1);
8b9cf98c 283 vmx->launched = 0;
8d0be2b3
AK		 284}
285
2384d2b3
SY		 286static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
287{
288 if (vmx->vpid == 0)
289 return;
290
291 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
292}
293
6aa8b732
AK		 294static unsigned long vmcs_readl(unsigned long field)
295{
296 unsigned long value;
297
298 asm volatile (ASM_VMX_VMREAD_RDX_RAX
299 : "=a"(value) : "d"(field) : "cc");
300 return value;
301}
302
303static u16 vmcs_read16(unsigned long field)
304{
305 return vmcs_readl(field);
306}
307
308static u32 vmcs_read32(unsigned long field)
309{
310 return vmcs_readl(field);
311}
312
313static u64 vmcs_read64(unsigned long field)
314{
05b3e0c2 315#ifdef CONFIG_X86_64
6aa8b732
AK		 316 return vmcs_readl(field);
317#else
318 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
319#endif
320}
321
e52de1b8
AK		 322static noinline void vmwrite_error(unsigned long field, unsigned long value)
323{
324 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
325 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
326 dump_stack();
327}
328
6aa8b732
AK		 329static void vmcs_writel(unsigned long field, unsigned long value)
330{
331 u8 error;
332
333 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
d77c26fc 334 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 335 if (unlikely(error))
336 vmwrite_error(field, value);
6aa8b732
AK		 337}
338
339static void vmcs_write16(unsigned long field, u16 value)
340{
341 vmcs_writel(field, value);
342}
343
344static void vmcs_write32(unsigned long field, u32 value)
345{
346 vmcs_writel(field, value);
347}
348
349static void vmcs_write64(unsigned long field, u64 value)
350{
05b3e0c2 351#ifdef CONFIG_X86_64
6aa8b732
AK		 352 vmcs_writel(field, value);
353#else
354 vmcs_writel(field, value);
355 asm volatile ("");
356 vmcs_writel(field+1, value >> 32);
357#endif
358}
359
2ab455cc
AL		 360static void vmcs_clear_bits(unsigned long field, u32 mask)
361{
362 vmcs_writel(field, vmcs_readl(field) & ~mask);
363}
364
365static void vmcs_set_bits(unsigned long field, u32 mask)
366{
367 vmcs_writel(field, vmcs_readl(field) | mask);
368}
369
abd3f2d6
AK		 370static void update_exception_bitmap(struct kvm_vcpu *vcpu)
371{
372 u32 eb;
373
7aa81cc0 374 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
abd3f2d6
AK		 375 if (!vcpu->fpu_active)
376 eb |= 1u << NM_VECTOR;
377 if (vcpu->guest_debug.enabled)
378 eb |= 1u << 1;
ad312c7c 379 if (vcpu->arch.rmode.active)
abd3f2d6
AK		 380 eb = ~0;
381 vmcs_write32(EXCEPTION_BITMAP, eb);
382}
383
33ed6329
AK		 384static void reload_tss(void)
385{
33ed6329
AK		 386 /*
387 * VT restores TR but not its size. Useless.
388 */
389 struct descriptor_table gdt;
a5f61300 390 struct desc_struct *descs;
33ed6329
AK		 391
392 get_gdt(&gdt);
393 descs = (void *)gdt.base;
394 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
395 load_TR_desc();
33ed6329
AK		 396}
397
8b9cf98c 398static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560 399{
a2fa3e9f 400 int efer_offset = vmx->msr_offset_efer;
51c6cf66
AK		 401 u64 host_efer = vmx->host_msrs[efer_offset].data;
402 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
403 u64 ignore_bits;
404
405 if (efer_offset < 0)
406 return;
407 /*
408 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
409 * outside long mode
410 */
411 ignore_bits = EFER_NX | EFER_SCE;
412#ifdef CONFIG_X86_64
413 ignore_bits |= EFER_LMA | EFER_LME;
414 /* SCE is meaningful only in long mode on Intel */
415 if (guest_efer & EFER_LMA)
416 ignore_bits &= ~(u64)EFER_SCE;
417#endif
418 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
419 return;
2cc51560 420
51c6cf66
AK		 421 vmx->host_state.guest_efer_loaded = 1;
422 guest_efer &= ~ignore_bits;
423 guest_efer |= host_efer & ignore_bits;
424 wrmsrl(MSR_EFER, guest_efer);
8b9cf98c 425 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 426}
427
51c6cf66
AK		 428static void reload_host_efer(struct vcpu_vmx *vmx)
429{
430 if (vmx->host_state.guest_efer_loaded) {
431 vmx->host_state.guest_efer_loaded = 0;
432 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
433 }
434}
435
04d2cc77 436static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 437{
04d2cc77
AK		 438 struct vcpu_vmx *vmx = to_vmx(vcpu);
439
a2fa3e9f 440 if (vmx->host_state.loaded)
33ed6329
AK		 441 return;
442
a2fa3e9f 443 vmx->host_state.loaded = 1;
33ed6329
AK		 444 /*
445 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
446 * allow segment selectors with cpl > 0 or ti == 1.
447 */
a2fa3e9f 448 vmx->host_state.ldt_sel = read_ldt();
152d3f2f 449 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
a2fa3e9f 450 vmx->host_state.fs_sel = read_fs();
152d3f2f 451 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 452 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 453 vmx->host_state.fs_reload_needed = 0;
454 } else {
33ed6329 455 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 456 vmx->host_state.fs_reload_needed = 1;
33ed6329 457 }
a2fa3e9f
GH		 458 vmx->host_state.gs_sel = read_gs();
459 if (!(vmx->host_state.gs_sel & 7))
460 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 461 else {
462 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 463 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 464 }
465
466#ifdef CONFIG_X86_64
467 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
468 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
469#else
a2fa3e9f
GH		 470 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
471 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 472#endif
707c0874
AK		 473
474#ifdef CONFIG_X86_64
d77c26fc 475 if (is_long_mode(&vmx->vcpu))
a2fa3e9f
GH		 476 save_msrs(vmx->host_msrs +
477 vmx->msr_offset_kernel_gs_base, 1);
d77c26fc 478
707c0874 479#endif
a2fa3e9f 480 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
51c6cf66 481 load_transition_efer(vmx);
33ed6329
AK		 482}
483
8b9cf98c 484static void vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 485{
15ad7146 486 unsigned long flags;
33ed6329 487
a2fa3e9f 488 if (!vmx->host_state.loaded)
33ed6329
AK		 489 return;
490
e1beb1d3 491 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 492 vmx->host_state.loaded = 0;
152d3f2f 493 if (vmx->host_state.fs_reload_needed)
a2fa3e9f 494 load_fs(vmx->host_state.fs_sel);
152d3f2f
LV		 495 if (vmx->host_state.gs_ldt_reload_needed) {
496 load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 497 /*
498 * If we have to reload gs, we must take care to
499 * preserve our gs base.
500 */
15ad7146 501 local_irq_save(flags);
a2fa3e9f 502 load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 503#ifdef CONFIG_X86_64
504 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
505#endif
15ad7146 506 local_irq_restore(flags);
33ed6329 507 }
152d3f2f 508 reload_tss();
a2fa3e9f
GH		 509 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
510 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
51c6cf66 511 reload_host_efer(vmx);
33ed6329
AK		 512}
513
6aa8b732
AK		 514/*
515 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
516 * vcpu mutex is already taken.
517 */
15ad7146 518static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 519{
a2fa3e9f
GH		 520 struct vcpu_vmx *vmx = to_vmx(vcpu);
521 u64 phys_addr = __pa(vmx->vmcs);
019960ae 522 u64 tsc_this, delta, new_offset;
6aa8b732 523
a3d7f85f 524 if (vcpu->cpu != cpu) {
8b9cf98c 525 vcpu_clear(vmx);
a3d7f85f 526 kvm_migrate_apic_timer(vcpu);
2384d2b3 527 vpid_sync_vcpu_all(vmx);
a3d7f85f 528 }
6aa8b732 529
a2fa3e9f 530 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 531 u8 error;
532
a2fa3e9f 533 per_cpu(current_vmcs, cpu) = vmx->vmcs;
6aa8b732
AK		 534 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
535 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
536 : "cc");
537 if (error)
538 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 539 vmx->vmcs, phys_addr);
6aa8b732
AK		 540 }
541
542 if (vcpu->cpu != cpu) {
543 struct descriptor_table dt;
544 unsigned long sysenter_esp;
545
546 vcpu->cpu = cpu;
547 /*
548 * Linux uses per-cpu TSS and GDT, so set these when switching
549 * processors.
550 */
551 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
552 get_gdt(&dt);
553 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
554
555 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
556 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 557
558 /*
559 * Make sure the time stamp counter is monotonous.
560 */
561 rdtscll(tsc_this);
019960ae
AK		 562 if (tsc_this < vcpu->arch.host_tsc) {
563 delta = vcpu->arch.host_tsc - tsc_this;
564 new_offset = vmcs_read64(TSC_OFFSET) + delta;
565 vmcs_write64(TSC_OFFSET, new_offset);
566 }
6aa8b732 567 }
6aa8b732
AK		 568}
569
570static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
571{
8b9cf98c 572 vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 573}
574
5fd86fcf
AK		 575static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
576{
577 if (vcpu->fpu_active)
578 return;
579 vcpu->fpu_active = 1;
707d92fa 580 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 581 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 582 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 583 update_exception_bitmap(vcpu);
584}
585
586static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
587{
588 if (!vcpu->fpu_active)
589 return;
590 vcpu->fpu_active = 0;
707d92fa 591 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 592 update_exception_bitmap(vcpu);
593}
594
774c47f1
AK		 595static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
596{
8b9cf98c 597 vcpu_clear(to_vmx(vcpu));
774c47f1
AK		 598}
599
6aa8b732
AK		 600static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
601{
602 return vmcs_readl(GUEST_RFLAGS);
603}
604
605static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
606{
ad312c7c 607 if (vcpu->arch.rmode.active)
053de044 608 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 609 vmcs_writel(GUEST_RFLAGS, rflags);
610}
611
612static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
613{
614 unsigned long rip;
615 u32 interruptibility;
616
617 rip = vmcs_readl(GUEST_RIP);
618 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
619 vmcs_writel(GUEST_RIP, rip);
620
621 /*
622 * We emulated an instruction, so temporary interrupt blocking
623 * should be removed, if set.
624 */
625 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
626 if (interruptibility & 3)
627 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
628 interruptibility & ~3);
ad312c7c 629 vcpu->arch.interrupt_window_open = 1;
6aa8b732
AK		 630}
631
298101da
AK		 632static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
633 bool has_error_code, u32 error_code)
634{
635 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
636 nr | INTR_TYPE_EXCEPTION
2e11384c 637 | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
298101da
AK		 638 | INTR_INFO_VALID_MASK);
639 if (has_error_code)
640 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
641}
642
643static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
644{
645 struct vcpu_vmx *vmx = to_vmx(vcpu);
646
647 return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
648}
649
a75beee6
ED		 650/*
651 * Swap MSR entry in host/guest MSR entry array.
652 */
54e11fa1 653#ifdef CONFIG_X86_64
8b9cf98c 654static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 655{
a2fa3e9f
GH		 656 struct kvm_msr_entry tmp;
657
658 tmp = vmx->guest_msrs[to];
659 vmx->guest_msrs[to] = vmx->guest_msrs[from];
660 vmx->guest_msrs[from] = tmp;
661 tmp = vmx->host_msrs[to];
662 vmx->host_msrs[to] = vmx->host_msrs[from];
663 vmx->host_msrs[from] = tmp;
a75beee6 664}
54e11fa1 665#endif
a75beee6 666
e38aea3e
AK		 667/*
668 * Set up the vmcs to automatically save and restore system
669 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
670 * mode, as fiddling with msrs is very expensive.
671 */
8b9cf98c 672static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 673{
2cc51560 674 int save_nmsrs;
e38aea3e 675
33f9c505 676 vmx_load_host_state(vmx);
a75beee6
ED		 677 save_nmsrs = 0;
678#ifdef CONFIG_X86_64
8b9cf98c 679 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 680 int index;
681
8b9cf98c 682 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 683 if (index >= 0)
8b9cf98c
RR		 684 move_msr_up(vmx, index, save_nmsrs++);
685 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 686 if (index >= 0)
8b9cf98c
RR		 687 move_msr_up(vmx, index, save_nmsrs++);
688 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 689 if (index >= 0)
8b9cf98c
RR		 690 move_msr_up(vmx, index, save_nmsrs++);
691 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 692 if (index >= 0)
8b9cf98c 693 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 694 /*
695 * MSR_K6_STAR is only needed on long mode guests, and only
696 * if efer.sce is enabled.
697 */
8b9cf98c 698 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 699 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 700 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 701 }
702#endif
a2fa3e9f 703 vmx->save_nmsrs = save_nmsrs;
e38aea3e 704
4d56c8a7 705#ifdef CONFIG_X86_64
a2fa3e9f 706 vmx->msr_offset_kernel_gs_base =
8b9cf98c 707 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 708#endif
8b9cf98c 709 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
e38aea3e
AK		 710}
711
6aa8b732
AK		 712/*
713 * reads and returns guest's timestamp counter "register"
714 * guest_tsc = host_tsc + tsc_offset -- 21.3
715 */
716static u64 guest_read_tsc(void)
717{
718 u64 host_tsc, tsc_offset;
719
720 rdtscll(host_tsc);
721 tsc_offset = vmcs_read64(TSC_OFFSET);
722 return host_tsc + tsc_offset;
723}
724
725/*
726 * writes 'guest_tsc' into guest's timestamp counter "register"
727 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
728 */
729static void guest_write_tsc(u64 guest_tsc)
730{
731 u64 host_tsc;
732
733 rdtscll(host_tsc);
734 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
735}
736
6aa8b732
AK		 737/*
738 * Reads an msr value (of 'msr_index') into 'pdata'.
739 * Returns 0 on success, non-0 otherwise.
740 * Assumes vcpu_load() was already called.
741 */
742static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
743{
744 u64 data;
a2fa3e9f 745 struct kvm_msr_entry *msr;
6aa8b732
AK		 746
747 if (!pdata) {
748 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
749 return -EINVAL;
750 }
751
752 switch (msr_index) {
05b3e0c2 753#ifdef CONFIG_X86_64
6aa8b732
AK		 754 case MSR_FS_BASE:
755 data = vmcs_readl(GUEST_FS_BASE);
756 break;
757 case MSR_GS_BASE:
758 data = vmcs_readl(GUEST_GS_BASE);
759 break;
760 case MSR_EFER:
3bab1f5d 761 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 762#endif
763 case MSR_IA32_TIME_STAMP_COUNTER:
764 data = guest_read_tsc();
765 break;
766 case MSR_IA32_SYSENTER_CS:
767 data = vmcs_read32(GUEST_SYSENTER_CS);
768 break;
769 case MSR_IA32_SYSENTER_EIP:
f5b42c33 770 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 771 break;
772 case MSR_IA32_SYSENTER_ESP:
f5b42c33 773 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 774 break;
6aa8b732 775 default:
8b9cf98c 776 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 777 if (msr) {
778 data = msr->data;
779 break;
6aa8b732 780 }
3bab1f5d 781 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 782 }
783
784 *pdata = data;
785 return 0;
786}
787
788/*
789 * Writes msr value into into the appropriate "register".
790 * Returns 0 on success, non-0 otherwise.
791 * Assumes vcpu_load() was already called.
792 */
793static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
794{
a2fa3e9f
GH		 795 struct vcpu_vmx *vmx = to_vmx(vcpu);
796 struct kvm_msr_entry *msr;
2cc51560
ED		 797 int ret = 0;
798
6aa8b732 799 switch (msr_index) {
05b3e0c2 800#ifdef CONFIG_X86_64
3bab1f5d 801 case MSR_EFER:
2cc51560 802 ret = kvm_set_msr_common(vcpu, msr_index, data);
51c6cf66
AK		 803 if (vmx->host_state.loaded) {
804 reload_host_efer(vmx);
8b9cf98c 805 load_transition_efer(vmx);
51c6cf66 806 }
2cc51560 807 break;
6aa8b732
AK		 808 case MSR_FS_BASE:
809 vmcs_writel(GUEST_FS_BASE, data);
810 break;
811 case MSR_GS_BASE:
812 vmcs_writel(GUEST_GS_BASE, data);
813 break;
814#endif
815 case MSR_IA32_SYSENTER_CS:
816 vmcs_write32(GUEST_SYSENTER_CS, data);
817 break;
818 case MSR_IA32_SYSENTER_EIP:
f5b42c33 819 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 820 break;
821 case MSR_IA32_SYSENTER_ESP:
f5b42c33 822 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 823 break;
d27d4aca 824 case MSR_IA32_TIME_STAMP_COUNTER:
6aa8b732
AK		 825 guest_write_tsc(data);
826 break;
6aa8b732 827 default:
8b9cf98c 828 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 829 if (msr) {
830 msr->data = data;
a2fa3e9f
GH		 831 if (vmx->host_state.loaded)
832 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
3bab1f5d 833 break;
6aa8b732 834 }
2cc51560 835 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 836 }
837
2cc51560 838 return ret;
6aa8b732
AK		 839}
840
841/*
842 * Sync the rsp and rip registers into the vcpu structure. This allows
ad312c7c 843 * registers to be accessed by indexing vcpu->arch.regs.
6aa8b732
AK		 844 */
845static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
846{
ad312c7c
ZX		 847 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
848 vcpu->arch.rip = vmcs_readl(GUEST_RIP);
6aa8b732
AK		 849}
850
851/*
852 * Syncs rsp and rip back into the vmcs. Should be called after possible
853 * modification.
854 */
855static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
856{
ad312c7c
ZX		 857 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
858 vmcs_writel(GUEST_RIP, vcpu->arch.rip);
6aa8b732
AK		 859}
860
861static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
862{
863 unsigned long dr7 = 0x400;
6aa8b732
AK		 864 int old_singlestep;
865
6aa8b732
AK		 866 old_singlestep = vcpu->guest_debug.singlestep;
867
868 vcpu->guest_debug.enabled = dbg->enabled;
869 if (vcpu->guest_debug.enabled) {
870 int i;
871
872 dr7 |= 0x200; /* exact */
873 for (i = 0; i < 4; ++i) {
874 if (!dbg->breakpoints[i].enabled)
875 continue;
876 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
877 dr7 |= 2 << (i*2); /* global enable */
878 dr7 |= 0 << (i*4+16); /* execution breakpoint */
879 }
880
6aa8b732 881 vcpu->guest_debug.singlestep = dbg->singlestep;
abd3f2d6 882 } else
6aa8b732 883 vcpu->guest_debug.singlestep = 0;
6aa8b732
AK		 884
885 if (old_singlestep && !vcpu->guest_debug.singlestep) {
886 unsigned long flags;
887
888 flags = vmcs_readl(GUEST_RFLAGS);
889 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
890 vmcs_writel(GUEST_RFLAGS, flags);
891 }
892
abd3f2d6 893 update_exception_bitmap(vcpu);
6aa8b732
AK		 894 vmcs_writel(GUEST_DR7, dr7);
895
896 return 0;
897}
898
2a8067f1
ED		 899static int vmx_get_irq(struct kvm_vcpu *vcpu)
900{
1155f76a 901 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a8067f1
ED		 902 u32 idtv_info_field;
903
1155f76a 904 idtv_info_field = vmx->idt_vectoring_info;
2a8067f1
ED		 905 if (idtv_info_field & INTR_INFO_VALID_MASK) {
906 if (is_external_interrupt(idtv_info_field))
907 return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
908 else
d77c26fc 909 printk(KERN_DEBUG "pending exception: not handled yet\n");
2a8067f1
ED		 910 }
911 return -1;
912}
913
6aa8b732
AK		 914static __init int cpu_has_kvm_support(void)
915{
916 unsigned long ecx = cpuid_ecx(1);
917 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
918}
919
920static __init int vmx_disabled_by_bios(void)
921{
922 u64 msr;
923
924 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
62b3ffb8
YS		 925 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
926 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
927 == MSR_IA32_FEATURE_CONTROL_LOCKED;
928 /* locked but not enabled */
6aa8b732
AK		 929}
930
774c47f1 931static void hardware_enable(void *garbage)
6aa8b732
AK		 932{
933 int cpu = raw_smp_processor_id();
934 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
935 u64 old;
936
937 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
62b3ffb8
YS		 938 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
939 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
940 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
941 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 942 /* enable and lock */
62b3ffb8
YS		 943 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
944 MSR_IA32_FEATURE_CONTROL_LOCKED |
945 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 946 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
6aa8b732
AK		 947 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
948 : "memory", "cc");
949}
950
951static void hardware_disable(void *garbage)
952{
953 asm volatile (ASM_VMX_VMXOFF : : : "cc");
954}
955
1c3d14fe 956static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 957 u32 msr, u32 *result)
1c3d14fe
YS		 958{
959 u32 vmx_msr_low, vmx_msr_high;
960 u32 ctl = ctl_min | ctl_opt;
961
962 rdmsr(msr, vmx_msr_low, vmx_msr_high);
963
964 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
965 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
966
967 /* Ensure minimum (required) set of control bits are supported. */
968 if (ctl_min & ~ctl)
002c7f7c 969 return -EIO;
1c3d14fe
YS		 970
971 *result = ctl;
972 return 0;
973}
974
002c7f7c 975static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 976{
977 u32 vmx_msr_low, vmx_msr_high;
1c3d14fe
YS		 978 u32 min, opt;
979 u32 _pin_based_exec_control = 0;
980 u32 _cpu_based_exec_control = 0;
f78e0e2e 981 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 982 u32 _vmexit_control = 0;
983 u32 _vmentry_control = 0;
984
985 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
986 opt = 0;
987 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
988 &_pin_based_exec_control) < 0)
002c7f7c 989 return -EIO;
1c3d14fe
YS		 990
991 min = CPU_BASED_HLT_EXITING |
992#ifdef CONFIG_X86_64
993 CPU_BASED_CR8_LOAD_EXITING |
994 CPU_BASED_CR8_STORE_EXITING |
995#endif
996 CPU_BASED_USE_IO_BITMAPS |
997 CPU_BASED_MOV_DR_EXITING |
998 CPU_BASED_USE_TSC_OFFSETING;
f78e0e2e
SY		 999 opt = CPU_BASED_TPR_SHADOW |
1000 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1001 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1002 &_cpu_based_exec_control) < 0)
002c7f7c 1003 return -EIO;
6e5d865c
YS		 1004#ifdef CONFIG_X86_64
1005 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1006 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1007 ~CPU_BASED_CR8_STORE_EXITING;
1008#endif
f78e0e2e
SY		 1009 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1010 min = 0;
e5edaa01 1011 opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3
SY		 1012 SECONDARY_EXEC_WBINVD_EXITING |
1013 SECONDARY_EXEC_ENABLE_VPID;
f78e0e2e
SY		 1014 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS2,
1015 &_cpu_based_2nd_exec_control) < 0)
1016 return -EIO;
1017 }
1018#ifndef CONFIG_X86_64
1019 if (!(_cpu_based_2nd_exec_control &
1020 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1021 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1022#endif
1c3d14fe
YS		 1023
1024 min = 0;
1025#ifdef CONFIG_X86_64
1026 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1027#endif
1028 opt = 0;
1029 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1030 &_vmexit_control) < 0)
002c7f7c 1031 return -EIO;
1c3d14fe
YS		 1032
1033 min = opt = 0;
1034 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1035 &_vmentry_control) < 0)
002c7f7c 1036 return -EIO;
6aa8b732 1037
c68876fd 1038 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1039
1040 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1041 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1042 return -EIO;
1c3d14fe
YS		 1043
1044#ifdef CONFIG_X86_64
1045 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1046 if (vmx_msr_high & (1u<<16))
002c7f7c 1047 return -EIO;
1c3d14fe
YS		 1048#endif
1049
1050 /* Require Write-Back (WB) memory type for VMCS accesses. */
1051 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1052 return -EIO;
1c3d14fe 1053
002c7f7c
YS		 1054 vmcs_conf->size = vmx_msr_high & 0x1fff;
1055 vmcs_conf->order = get_order(vmcs_config.size);
1056 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1057
002c7f7c
YS		 1058 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1059 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1060 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1061 vmcs_conf->vmexit_ctrl = _vmexit_control;
1062 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1063
1064 return 0;
c68876fd 1065}
6aa8b732
AK		 1066
1067static struct vmcs *alloc_vmcs_cpu(int cpu)
1068{
1069 int node = cpu_to_node(cpu);
1070 struct page *pages;
1071 struct vmcs *vmcs;
1072
1c3d14fe 1073 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1074 if (!pages)
1075 return NULL;
1076 vmcs = page_address(pages);
1c3d14fe
YS		 1077 memset(vmcs, 0, vmcs_config.size);
1078 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1079 return vmcs;
1080}
1081
1082static struct vmcs *alloc_vmcs(void)
1083{
d3b2c338 1084 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1085}
1086
1087static void free_vmcs(struct vmcs *vmcs)
1088{
1c3d14fe 1089 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1090}
1091
39959588 1092static void free_kvm_area(void)
6aa8b732
AK		 1093{
1094 int cpu;
1095
1096 for_each_online_cpu(cpu)
1097 free_vmcs(per_cpu(vmxarea, cpu));
1098}
1099
6aa8b732
AK		 1100static __init int alloc_kvm_area(void)
1101{
1102 int cpu;
1103
1104 for_each_online_cpu(cpu) {
1105 struct vmcs *vmcs;
1106
1107 vmcs = alloc_vmcs_cpu(cpu);
1108 if (!vmcs) {
1109 free_kvm_area();
1110 return -ENOMEM;
1111 }
1112
1113 per_cpu(vmxarea, cpu) = vmcs;
1114 }
1115 return 0;
1116}
1117
1118static __init int hardware_setup(void)
1119{
002c7f7c
YS		 1120 if (setup_vmcs_config(&vmcs_config) < 0)
1121 return -EIO;
50a37eb4
JR		 1122
1123 if (boot_cpu_has(X86_FEATURE_NX))
1124 kvm_enable_efer_bits(EFER_NX);
1125
6aa8b732
AK		 1126 return alloc_kvm_area();
1127}
1128
1129static __exit void hardware_unsetup(void)
1130{
1131 free_kvm_area();
1132}
1133
6aa8b732
AK		 1134static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1135{
1136 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1137
6af11b9e 1138 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1139 vmcs_write16(sf->selector, save->selector);
1140 vmcs_writel(sf->base, save->base);
1141 vmcs_write32(sf->limit, save->limit);
1142 vmcs_write32(sf->ar_bytes, save->ar);
1143 } else {
1144 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1145 << AR_DPL_SHIFT;
1146 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1147 }
1148}
1149
1150static void enter_pmode(struct kvm_vcpu *vcpu)
1151{
1152 unsigned long flags;
1153
ad312c7c 1154 vcpu->arch.rmode.active = 0;
6aa8b732 1155
ad312c7c
ZX		 1156 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1157 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1158 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
6aa8b732
AK		 1159
1160 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1161 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
ad312c7c 1162 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1163 vmcs_writel(GUEST_RFLAGS, flags);
1164
66aee91a
RR		 1165 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1166 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1167
1168 update_exception_bitmap(vcpu);
1169
ad312c7c
ZX		 1170 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1171 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1172 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1173 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
6aa8b732
AK		 1174
1175 vmcs_write16(GUEST_SS_SELECTOR, 0);
1176 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1177
1178 vmcs_write16(GUEST_CS_SELECTOR,
1179 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1180 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1181}
1182
d77c26fc 1183static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1184{
bfc6d222 1185 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1186 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1187 kvm->memslots[0].npages - 3;
1188 return base_gfn << PAGE_SHIFT;
1189 }
bfc6d222 1190 return kvm->arch.tss_addr;
6aa8b732
AK		 1191}
1192
1193static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1194{
1195 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1196
1197 save->selector = vmcs_read16(sf->selector);
1198 save->base = vmcs_readl(sf->base);
1199 save->limit = vmcs_read32(sf->limit);
1200 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1201 vmcs_write16(sf->selector, save->base >> 4);
1202 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1203 vmcs_write32(sf->limit, 0xffff);
1204 vmcs_write32(sf->ar_bytes, 0xf3);
1205}
1206
1207static void enter_rmode(struct kvm_vcpu *vcpu)
1208{
1209 unsigned long flags;
1210
ad312c7c 1211 vcpu->arch.rmode.active = 1;
6aa8b732 1212
ad312c7c 1213 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1214 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1215
ad312c7c 1216 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1217 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1218
ad312c7c 1219 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1220 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1221
1222 flags = vmcs_readl(GUEST_RFLAGS);
ad312c7c
ZX		 1223 vcpu->arch.rmode.save_iopl
1224 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1225
053de044 1226 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1227
1228 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1229 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1230 update_exception_bitmap(vcpu);
1231
1232 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1233 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1234 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1235
1236 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1237 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1238 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1239 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1240 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1241
ad312c7c
ZX		 1242 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1243 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1244 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1245 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
75880a01 1246
8668a3c4 1247 kvm_mmu_reset_context(vcpu);
75880a01 1248 init_rmode_tss(vcpu->kvm);
6aa8b732
AK		 1249}
1250
05b3e0c2 1251#ifdef CONFIG_X86_64
6aa8b732
AK		 1252
1253static void enter_lmode(struct kvm_vcpu *vcpu)
1254{
1255 u32 guest_tr_ar;
1256
1257 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1258 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1259 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1260 __func__);
6aa8b732
AK		 1261 vmcs_write32(GUEST_TR_AR_BYTES,
1262 (guest_tr_ar & ~AR_TYPE_MASK)
1263 | AR_TYPE_BUSY_64_TSS);
1264 }
1265
ad312c7c 1266 vcpu->arch.shadow_efer |= EFER_LMA;
6aa8b732 1267
8b9cf98c 1268 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1269 vmcs_write32(VM_ENTRY_CONTROLS,
1270 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1271 | VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1272}
1273
1274static void exit_lmode(struct kvm_vcpu *vcpu)
1275{
ad312c7c 1276 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1277
1278 vmcs_write32(VM_ENTRY_CONTROLS,
1279 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1280 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1281}
1282
1283#endif
1284
2384d2b3
SY		 1285static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1286{
1287 vpid_sync_vcpu_all(to_vmx(vcpu));
1288}
1289
25c4c276 1290static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1291{
ad312c7c
ZX		 1292 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1293 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
399badf3
AK		 1294}
1295
6aa8b732
AK		 1296static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1297{
5fd86fcf
AK		 1298 vmx_fpu_deactivate(vcpu);
1299
ad312c7c 1300 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1301 enter_pmode(vcpu);
1302
ad312c7c 1303 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1304 enter_rmode(vcpu);
1305
05b3e0c2 1306#ifdef CONFIG_X86_64
ad312c7c 1307 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1308 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1309 enter_lmode(vcpu);
707d92fa 1310 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1311 exit_lmode(vcpu);
1312 }
1313#endif
1314
1315 vmcs_writel(CR0_READ_SHADOW, cr0);
1316 vmcs_writel(GUEST_CR0,
1317 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
ad312c7c 1318 vcpu->arch.cr0 = cr0;
5fd86fcf 1319
707d92fa 1320 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1321 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1322}
1323
6aa8b732
AK		 1324static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1325{
2384d2b3 1326 vmx_flush_tlb(vcpu);
6aa8b732 1327 vmcs_writel(GUEST_CR3, cr3);
ad312c7c 1328 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1329 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1330}
1331
1332static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1333{
1334 vmcs_writel(CR4_READ_SHADOW, cr4);
ad312c7c 1335 vmcs_writel(GUEST_CR4, cr4 | (vcpu->arch.rmode.active ?
6aa8b732 1336 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
ad312c7c 1337 vcpu->arch.cr4 = cr4;
6aa8b732
AK		 1338}
1339
6aa8b732
AK		 1340static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1341{
8b9cf98c
RR		 1342 struct vcpu_vmx *vmx = to_vmx(vcpu);
1343 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
6aa8b732 1344
ad312c7c 1345 vcpu->arch.shadow_efer = efer;
9f62e19a
JR		 1346 if (!msr)
1347 return;
6aa8b732
AK		 1348 if (efer & EFER_LMA) {
1349 vmcs_write32(VM_ENTRY_CONTROLS,
1350 vmcs_read32(VM_ENTRY_CONTROLS) |
1e4e6e00 1351 VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1352 msr->data = efer;
1353
1354 } else {
1355 vmcs_write32(VM_ENTRY_CONTROLS,
1356 vmcs_read32(VM_ENTRY_CONTROLS) &
1e4e6e00 1357 ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1358
1359 msr->data = efer & ~EFER_LME;
1360 }
8b9cf98c 1361 setup_msrs(vmx);
6aa8b732
AK		 1362}
1363
6aa8b732
AK		 1364static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1365{
1366 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1367
1368 return vmcs_readl(sf->base);
1369}
1370
1371static void vmx_get_segment(struct kvm_vcpu *vcpu,
1372 struct kvm_segment *var, int seg)
1373{
1374 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1375 u32 ar;
1376
1377 var->base = vmcs_readl(sf->base);
1378 var->limit = vmcs_read32(sf->limit);
1379 var->selector = vmcs_read16(sf->selector);
1380 ar = vmcs_read32(sf->ar_bytes);
1381 if (ar & AR_UNUSABLE_MASK)
1382 ar = 0;
1383 var->type = ar & 15;
1384 var->s = (ar >> 4) & 1;
1385 var->dpl = (ar >> 5) & 3;
1386 var->present = (ar >> 7) & 1;
1387 var->avl = (ar >> 12) & 1;
1388 var->l = (ar >> 13) & 1;
1389 var->db = (ar >> 14) & 1;
1390 var->g = (ar >> 15) & 1;
1391 var->unusable = (ar >> 16) & 1;
1392}
1393
653e3108 1394static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1395{
6aa8b732
AK		 1396 u32 ar;
1397
653e3108 1398 if (var->unusable)
6aa8b732
AK		 1399 ar = 1 << 16;
1400 else {
1401 ar = var->type & 15;
1402 ar |= (var->s & 1) << 4;
1403 ar |= (var->dpl & 3) << 5;
1404 ar |= (var->present & 1) << 7;
1405 ar |= (var->avl & 1) << 12;
1406 ar |= (var->l & 1) << 13;
1407 ar |= (var->db & 1) << 14;
1408 ar |= (var->g & 1) << 15;
1409 }
f7fbf1fd
UL		 1410 if (ar == 0) /* a 0 value means unusable */
1411 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1412
1413 return ar;
1414}
1415
1416static void vmx_set_segment(struct kvm_vcpu *vcpu,
1417 struct kvm_segment *var, int seg)
1418{
1419 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1420 u32 ar;
1421
ad312c7c
ZX		 1422 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1423 vcpu->arch.rmode.tr.selector = var->selector;
1424 vcpu->arch.rmode.tr.base = var->base;
1425 vcpu->arch.rmode.tr.limit = var->limit;
1426 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1427 return;
1428 }
1429 vmcs_writel(sf->base, var->base);
1430 vmcs_write32(sf->limit, var->limit);
1431 vmcs_write16(sf->selector, var->selector);
ad312c7c 1432 if (vcpu->arch.rmode.active && var->s) {
653e3108
AK		 1433 /*
1434 * Hack real-mode segments into vm86 compatibility.
1435 */
1436 if (var->base == 0xffff0000 && var->selector == 0xf000)
1437 vmcs_writel(sf->base, 0xf0000);
1438 ar = 0xf3;
1439 } else
1440 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1441 vmcs_write32(sf->ar_bytes, ar);
1442}
1443
6aa8b732
AK		 1444static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1445{
1446 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1447
1448 *db = (ar >> 14) & 1;
1449 *l = (ar >> 13) & 1;
1450}
1451
1452static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1453{
1454 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1455 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1456}
1457
1458static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1459{
1460 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1461 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1462}
1463
1464static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1465{
1466 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1467 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1468}
1469
1470static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1471{
1472 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1473 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1474}
1475
d77c26fc 1476static int init_rmode_tss(struct kvm *kvm)
6aa8b732 1477{
6aa8b732 1478 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 1479 u16 data = 0;
10589a46 1480 int ret = 0;
195aefde 1481 int r;
6aa8b732 1482
707a18a5 1483 down_read(&kvm->slots_lock);
195aefde
IE		 1484 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1485 if (r < 0)
10589a46 1486 goto out;
195aefde
IE		 1487 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1488 r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1489 if (r < 0)
10589a46 1490 goto out;
195aefde
IE		 1491 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1492 if (r < 0)
10589a46 1493 goto out;
195aefde
IE		 1494 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1495 if (r < 0)
10589a46 1496 goto out;
195aefde 1497 data = ~0;
10589a46
MT		 1498 r = kvm_write_guest_page(kvm, fn, &data,
1499 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1500 sizeof(u8));
195aefde 1501 if (r < 0)
10589a46
MT		 1502 goto out;
1503
1504 ret = 1;
1505out:
707a18a5 1506 up_read(&kvm->slots_lock);
10589a46 1507 return ret;
6aa8b732
AK		 1508}
1509
6aa8b732
AK		 1510static void seg_setup(int seg)
1511{
1512 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1513
1514 vmcs_write16(sf->selector, 0);
1515 vmcs_writel(sf->base, 0);
1516 vmcs_write32(sf->limit, 0xffff);
1517 vmcs_write32(sf->ar_bytes, 0x93);
1518}
1519
f78e0e2e
SY		 1520static int alloc_apic_access_page(struct kvm *kvm)
1521{
1522 struct kvm_userspace_memory_region kvm_userspace_mem;
1523 int r = 0;
1524
72dc67a6 1525 down_write(&kvm->slots_lock);
bfc6d222 1526 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 1527 goto out;
1528 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1529 kvm_userspace_mem.flags = 0;
1530 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1531 kvm_userspace_mem.memory_size = PAGE_SIZE;
1532 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1533 if (r)
1534 goto out;
72dc67a6
IE		 1535
1536 down_read(&current->mm->mmap_sem);
bfc6d222 1537 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
72dc67a6 1538 up_read(&current->mm->mmap_sem);
f78e0e2e 1539out:
72dc67a6 1540 up_write(&kvm->slots_lock);
f78e0e2e
SY		 1541 return r;
1542}
1543
2384d2b3
SY		 1544static void allocate_vpid(struct vcpu_vmx *vmx)
1545{
1546 int vpid;
1547
1548 vmx->vpid = 0;
1549 if (!enable_vpid || !cpu_has_vmx_vpid())
1550 return;
1551 spin_lock(&vmx_vpid_lock);
1552 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
1553 if (vpid < VMX_NR_VPIDS) {
1554 vmx->vpid = vpid;
1555 __set_bit(vpid, vmx_vpid_bitmap);
1556 }
1557 spin_unlock(&vmx_vpid_lock);
1558}
1559
6aa8b732
AK		 1560/*
1561 * Sets up the vmcs for emulated real mode.
1562 */
8b9cf98c 1563static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732
AK		 1564{
1565 u32 host_sysenter_cs;
1566 u32 junk;
1567 unsigned long a;
1568 struct descriptor_table dt;
1569 int i;
cd2276a7 1570 unsigned long kvm_vmx_return;
6e5d865c 1571 u32 exec_control;
6aa8b732 1572
6aa8b732 1573 /* I/O */
fdef3ad1
HQ		 1574 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1575 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732 1576
6aa8b732
AK		 1577 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1578
6aa8b732 1579 /* Control */
1c3d14fe
YS		 1580 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1581 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 1582
1583 exec_control = vmcs_config.cpu_based_exec_ctrl;
1584 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1585 exec_control &= ~CPU_BASED_TPR_SHADOW;
1586#ifdef CONFIG_X86_64
1587 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1588 CPU_BASED_CR8_LOAD_EXITING;
1589#endif
1590 }
1591 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 1592
83ff3b9d
SY		 1593 if (cpu_has_secondary_exec_ctrls()) {
1594 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1595 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1596 exec_control &=
1597 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 1598 if (vmx->vpid == 0)
1599 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
83ff3b9d
SY		 1600 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1601 }
f78e0e2e 1602
c7addb90
AK		 1603 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1604 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 1605 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1606
1607 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1608 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1609 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1610
1611 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1612 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1613 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1614 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1615 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1616 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 1617#ifdef CONFIG_X86_64
6aa8b732
AK		 1618 rdmsrl(MSR_FS_BASE, a);
1619 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1620 rdmsrl(MSR_GS_BASE, a);
1621 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1622#else
1623 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1624 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1625#endif
1626
1627 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1628
1629 get_idt(&dt);
1630 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1631
d77c26fc 1632 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 1633 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 1634 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1635 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1636 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 1637
1638 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1639 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1640 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1641 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1642 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1643 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1644
6aa8b732
AK		 1645 for (i = 0; i < NR_VMX_MSR; ++i) {
1646 u32 index = vmx_msr_index[i];
1647 u32 data_low, data_high;
1648 u64 data;
a2fa3e9f 1649 int j = vmx->nmsrs;
6aa8b732
AK		 1650
1651 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1652 continue;
432bd6cb
AK		 1653 if (wrmsr_safe(index, data_low, data_high) < 0)
1654 continue;
6aa8b732 1655 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 1656 vmx->host_msrs[j].index = index;
1657 vmx->host_msrs[j].reserved = 0;
1658 vmx->host_msrs[j].data = data;
1659 vmx->guest_msrs[j] = vmx->host_msrs[j];
1660 ++vmx->nmsrs;
6aa8b732 1661 }
6aa8b732 1662
1c3d14fe 1663 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 1664
1665 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 1666 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1667
e00c8cf2
AK		 1668 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1669 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1670
f78e0e2e 1671
e00c8cf2
AK		 1672 return 0;
1673}
1674
1675static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1676{
1677 struct vcpu_vmx *vmx = to_vmx(vcpu);
1678 u64 msr;
1679 int ret;
1680
1681 if (!init_rmode_tss(vmx->vcpu.kvm)) {
1682 ret = -ENOMEM;
1683 goto out;
1684 }
1685
ad312c7c 1686 vmx->vcpu.arch.rmode.active = 0;
e00c8cf2 1687
ad312c7c 1688 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 1689 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2
AK		 1690 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1691 if (vmx->vcpu.vcpu_id == 0)
1692 msr |= MSR_IA32_APICBASE_BSP;
1693 kvm_set_apic_base(&vmx->vcpu, msr);
1694
1695 fx_init(&vmx->vcpu);
1696
1697 /*
1698 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1699 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1700 */
1701 if (vmx->vcpu.vcpu_id == 0) {
1702 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1703 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1704 } else {
ad312c7c
ZX		 1705 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
1706 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2
AK		 1707 }
1708 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1709 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1710
1711 seg_setup(VCPU_SREG_DS);
1712 seg_setup(VCPU_SREG_ES);
1713 seg_setup(VCPU_SREG_FS);
1714 seg_setup(VCPU_SREG_GS);
1715 seg_setup(VCPU_SREG_SS);
1716
1717 vmcs_write16(GUEST_TR_SELECTOR, 0);
1718 vmcs_writel(GUEST_TR_BASE, 0);
1719 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1720 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1721
1722 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1723 vmcs_writel(GUEST_LDTR_BASE, 0);
1724 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1725 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1726
1727 vmcs_write32(GUEST_SYSENTER_CS, 0);
1728 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1729 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1730
1731 vmcs_writel(GUEST_RFLAGS, 0x02);
1732 if (vmx->vcpu.vcpu_id == 0)
1733 vmcs_writel(GUEST_RIP, 0xfff0);
1734 else
1735 vmcs_writel(GUEST_RIP, 0);
1736 vmcs_writel(GUEST_RSP, 0);
1737
1738 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
1739 vmcs_writel(GUEST_DR7, 0x400);
1740
1741 vmcs_writel(GUEST_GDTR_BASE, 0);
1742 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1743
1744 vmcs_writel(GUEST_IDTR_BASE, 0);
1745 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1746
1747 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1748 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1749 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1750
1751 guest_write_tsc(0);
1752
1753 /* Special registers */
1754 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1755
1756 setup_msrs(vmx);
1757
6aa8b732
AK		 1758 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1759
f78e0e2e
SY		 1760 if (cpu_has_vmx_tpr_shadow()) {
1761 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1762 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1763 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 1764 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 1765 vmcs_write32(TPR_THRESHOLD, 0);
1766 }
1767
1768 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1769 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 1770 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 1771
2384d2b3
SY		 1772 if (vmx->vpid != 0)
1773 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
1774
ad312c7c
ZX		 1775 vmx->vcpu.arch.cr0 = 0x60000010;
1776 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 1777 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 1778 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 1779 vmx_fpu_activate(&vmx->vcpu);
1780 update_exception_bitmap(&vmx->vcpu);
6aa8b732 1781
2384d2b3
SY		 1782 vpid_sync_vcpu_all(vmx);
1783
6aa8b732
AK		 1784 return 0;
1785
6aa8b732
AK		 1786out:
1787 return ret;
1788}
1789
85f455f7
ED		 1790static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1791{
9c8cba37
AK		 1792 struct vcpu_vmx *vmx = to_vmx(vcpu);
1793
ad312c7c 1794 if (vcpu->arch.rmode.active) {
9c8cba37
AK		 1795 vmx->rmode.irq.pending = true;
1796 vmx->rmode.irq.vector = irq;
1797 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
9c5623e3
AK		 1798 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1799 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
1800 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
9c8cba37 1801 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
85f455f7
ED		 1802 return;
1803 }
1804 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1805 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1806}
1807
6aa8b732
AK		 1808static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1809{
ad312c7c
ZX		 1810 int word_index = __ffs(vcpu->arch.irq_summary);
1811 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
6aa8b732
AK		 1812 int irq = word_index * BITS_PER_LONG + bit_index;
1813
ad312c7c
ZX		 1814 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1815 if (!vcpu->arch.irq_pending[word_index])
1816 clear_bit(word_index, &vcpu->arch.irq_summary);
85f455f7 1817 vmx_inject_irq(vcpu, irq);
6aa8b732
AK		 1818}
1819
c1150d8c
DL		 1820
1821static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1822 struct kvm_run *kvm_run)
6aa8b732 1823{
c1150d8c
DL		 1824 u32 cpu_based_vm_exec_control;
1825
ad312c7c 1826 vcpu->arch.interrupt_window_open =
c1150d8c
DL		 1827 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1828 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1829
ad312c7c
ZX		 1830 if (vcpu->arch.interrupt_window_open &&
1831 vcpu->arch.irq_summary &&
c1150d8c 1832 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
6aa8b732 1833 /*
c1150d8c 1834 * If interrupts enabled, and not blocked by sti or mov ss. Good.
6aa8b732
AK		 1835 */
1836 kvm_do_inject_irq(vcpu);
c1150d8c
DL		 1837
1838 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
ad312c7c
ZX		 1839 if (!vcpu->arch.interrupt_window_open &&
1840 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
6aa8b732
AK		 1841 /*
1842 * Interrupts blocked. Wait for unblock.
1843 */
c1150d8c
DL		 1844 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1845 else
1846 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1847 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6aa8b732
AK		 1848}
1849
cbc94022
IE		 1850static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
1851{
1852 int ret;
1853 struct kvm_userspace_memory_region tss_mem = {
1854 .slot = 8,
1855 .guest_phys_addr = addr,
1856 .memory_size = PAGE_SIZE * 3,
1857 .flags = 0,
1858 };
1859
1860 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
1861 if (ret)
1862 return ret;
bfc6d222 1863 kvm->arch.tss_addr = addr;
cbc94022
IE		 1864 return 0;
1865}
1866
6aa8b732
AK		 1867static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1868{
1869 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1870
1871 set_debugreg(dbg->bp[0], 0);
1872 set_debugreg(dbg->bp[1], 1);
1873 set_debugreg(dbg->bp[2], 2);
1874 set_debugreg(dbg->bp[3], 3);
1875
1876 if (dbg->singlestep) {
1877 unsigned long flags;
1878
1879 flags = vmcs_readl(GUEST_RFLAGS);
1880 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1881 vmcs_writel(GUEST_RFLAGS, flags);
1882 }
1883}
1884
1885static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1886 int vec, u32 err_code)
1887{
ad312c7c 1888 if (!vcpu->arch.rmode.active)
6aa8b732
AK		 1889 return 0;
1890
b3f37707
NK		 1891 /*
1892 * Instruction with address size override prefix opcode 0x67
1893 * Cause the #SS fault with 0 error code in VM86 mode.
1894 */
1895 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3427318f 1896 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
6aa8b732
AK		 1897 return 1;
1898 return 0;
1899}
1900
1901static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1902{
1155f76a 1903 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 1904 u32 intr_info, error_code;
1905 unsigned long cr2, rip;
1906 u32 vect_info;
1907 enum emulation_result er;
1908
1155f76a 1909 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 1910 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1911
1912 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
d77c26fc 1913 !is_page_fault(intr_info))
6aa8b732 1914 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
b8688d51 1915 "intr info 0x%x\n", __func__, vect_info, intr_info);
6aa8b732 1916
85f455f7 1917 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
6aa8b732 1918 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
ad312c7c
ZX		 1919 set_bit(irq, vcpu->arch.irq_pending);
1920 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
6aa8b732
AK		 1921 }
1922
1b6269db
AK		 1923 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1924 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 1925
1926 if (is_no_device(intr_info)) {
5fd86fcf 1927 vmx_fpu_activate(vcpu);
2ab455cc
AL		 1928 return 1;
1929 }
1930
7aa81cc0 1931 if (is_invalid_opcode(intr_info)) {
571008da 1932 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1933 if (er != EMULATE_DONE)
7ee5d940 1934 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 1935 return 1;
1936 }
1937
6aa8b732
AK		 1938 error_code = 0;
1939 rip = vmcs_readl(GUEST_RIP);
2e11384c 1940 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 1941 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1942 if (is_page_fault(intr_info)) {
1943 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3067714c 1944 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 1945 }
1946
ad312c7c 1947 if (vcpu->arch.rmode.active &&
6aa8b732 1948 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 1949 error_code)) {
ad312c7c
ZX		 1950 if (vcpu->arch.halt_request) {
1951 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 1952 return kvm_emulate_halt(vcpu);
1953 }
6aa8b732 1954 return 1;
72d6e5a0 1955 }
6aa8b732 1956
d77c26fc
MD		 1957 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
1958 (INTR_TYPE_EXCEPTION | 1)) {
6aa8b732
AK		 1959 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1960 return 0;
1961 }
1962 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1963 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1964 kvm_run->ex.error_code = error_code;
1965 return 0;
1966}
1967
1968static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1969 struct kvm_run *kvm_run)
1970{
1165f5fe 1971 ++vcpu->stat.irq_exits;
6aa8b732
AK		 1972 return 1;
1973}
1974
988ad74f
AK		 1975static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1976{
1977 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1978 return 0;
1979}
6aa8b732 1980
6aa8b732
AK		 1981static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1982{
bfdaab09 1983 unsigned long exit_qualification;
039576c0
AK		 1984 int size, down, in, string, rep;
1985 unsigned port;
6aa8b732 1986
1165f5fe 1987 ++vcpu->stat.io_exits;
bfdaab09 1988 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 1989 string = (exit_qualification & 16) != 0;
e70669ab
LV		 1990
1991 if (string) {
3427318f
LV		 1992 if (emulate_instruction(vcpu,
1993 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1994 return 0;
1995 return 1;
1996 }
1997
1998 size = (exit_qualification & 7) + 1;
1999 in = (exit_qualification & 8) != 0;
039576c0 2000 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
039576c0
AK		 2001 rep = (exit_qualification & 32) != 0;
2002 port = exit_qualification >> 16;
e70669ab 2003
3090dd73 2004 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 2005}
2006
102d8325
IM		 2007static void
2008vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2009{
2010 /*
2011 * Patch in the VMCALL instruction:
2012 */
2013 hypercall[0] = 0x0f;
2014 hypercall[1] = 0x01;
2015 hypercall[2] = 0xc1;
102d8325
IM		 2016}
2017
6aa8b732
AK		 2018static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2019{
bfdaab09 2020 unsigned long exit_qualification;
6aa8b732
AK		 2021 int cr;
2022 int reg;
2023
bfdaab09 2024 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2025 cr = exit_qualification & 15;
2026 reg = (exit_qualification >> 8) & 15;
2027 switch ((exit_qualification >> 4) & 3) {
2028 case 0: /* mov to cr */
2029 switch (cr) {
2030 case 0:
2031 vcpu_load_rsp_rip(vcpu);
2d3ad1f4 2032 kvm_set_cr0(vcpu, vcpu->arch.regs[reg]);
6aa8b732
AK		 2033 skip_emulated_instruction(vcpu);
2034 return 1;
2035 case 3:
2036 vcpu_load_rsp_rip(vcpu);
2d3ad1f4 2037 kvm_set_cr3(vcpu, vcpu->arch.regs[reg]);
6aa8b732
AK		 2038 skip_emulated_instruction(vcpu);
2039 return 1;
2040 case 4:
2041 vcpu_load_rsp_rip(vcpu);
2d3ad1f4 2042 kvm_set_cr4(vcpu, vcpu->arch.regs[reg]);
6aa8b732
AK		 2043 skip_emulated_instruction(vcpu);
2044 return 1;
2045 case 8:
2046 vcpu_load_rsp_rip(vcpu);
2d3ad1f4 2047 kvm_set_cr8(vcpu, vcpu->arch.regs[reg]);
6aa8b732 2048 skip_emulated_instruction(vcpu);
e5314067
AK		 2049 if (irqchip_in_kernel(vcpu->kvm))
2050 return 1;
253abdee
YS		 2051 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2052 return 0;
6aa8b732
AK		 2053 };
2054 break;
25c4c276
AL		 2055 case 2: /* clts */
2056 vcpu_load_rsp_rip(vcpu);
5fd86fcf 2057 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2058 vcpu->arch.cr0 &= ~X86_CR0_TS;
2059 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2060 vmx_fpu_activate(vcpu);
25c4c276
AL		 2061 skip_emulated_instruction(vcpu);
2062 return 1;
6aa8b732
AK		 2063 case 1: /*mov from cr*/
2064 switch (cr) {
2065 case 3:
2066 vcpu_load_rsp_rip(vcpu);
ad312c7c 2067 vcpu->arch.regs[reg] = vcpu->arch.cr3;
6aa8b732
AK		 2068 vcpu_put_rsp_rip(vcpu);
2069 skip_emulated_instruction(vcpu);
2070 return 1;
2071 case 8:
6aa8b732 2072 vcpu_load_rsp_rip(vcpu);
2d3ad1f4 2073 vcpu->arch.regs[reg] = kvm_get_cr8(vcpu);
6aa8b732
AK		 2074 vcpu_put_rsp_rip(vcpu);
2075 skip_emulated_instruction(vcpu);
2076 return 1;
2077 }
2078 break;
2079 case 3: /* lmsw */
2d3ad1f4 2080 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2081
2082 skip_emulated_instruction(vcpu);
2083 return 1;
2084 default:
2085 break;
2086 }
2087 kvm_run->exit_reason = 0;
f0242478 2088 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2089 (int)(exit_qualification >> 4) & 3, cr);
2090 return 0;
2091}
2092
2093static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2094{
bfdaab09 2095 unsigned long exit_qualification;
6aa8b732
AK		 2096 unsigned long val;
2097 int dr, reg;
2098
2099 /*
2100 * FIXME: this code assumes the host is debugging the guest.
2101 * need to deal with guest debugging itself too.
2102 */
bfdaab09 2103 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2104 dr = exit_qualification & 7;
2105 reg = (exit_qualification >> 8) & 15;
2106 vcpu_load_rsp_rip(vcpu);
2107 if (exit_qualification & 16) {
2108 /* mov from dr */
2109 switch (dr) {
2110 case 6:
2111 val = 0xffff0ff0;
2112 break;
2113 case 7:
2114 val = 0x400;
2115 break;
2116 default:
2117 val = 0;
2118 }
ad312c7c 2119 vcpu->arch.regs[reg] = val;
6aa8b732
AK		 2120 } else {
2121 /* mov to dr */
2122 }
2123 vcpu_put_rsp_rip(vcpu);
2124 skip_emulated_instruction(vcpu);
2125 return 1;
2126}
2127
2128static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2129{
06465c5a
AK		 2130 kvm_emulate_cpuid(vcpu);
2131 return 1;
6aa8b732
AK		 2132}
2133
2134static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2135{
ad312c7c 2136 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2137 u64 data;
2138
2139 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 2140 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2141 return 1;
2142 }
2143
2144 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 2145 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2146 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 2147 skip_emulated_instruction(vcpu);
2148 return 1;
2149}
2150
2151static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2152{
ad312c7c
ZX		 2153 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2154 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2155 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 2156
2157 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 2158 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2159 return 1;
2160 }
2161
2162 skip_emulated_instruction(vcpu);
2163 return 1;
2164}
2165
6e5d865c
YS		 2166static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2167 struct kvm_run *kvm_run)
2168{
2169 return 1;
2170}
2171
6aa8b732
AK		 2172static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2173 struct kvm_run *kvm_run)
2174{
85f455f7
ED		 2175 u32 cpu_based_vm_exec_control;
2176
2177 /* clear pending irq */
2178 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2179 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2180 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
c1150d8c
DL		 2181 /*
2182 * If the user space waits to inject interrupts, exit as soon as
2183 * possible
2184 */
2185 if (kvm_run->request_interrupt_window &&
ad312c7c 2186 !vcpu->arch.irq_summary) {
c1150d8c 2187 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1165f5fe 2188 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 2189 return 0;
2190 }
6aa8b732
AK		 2191 return 1;
2192}
2193
2194static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2195{
2196 skip_emulated_instruction(vcpu);
d3bef15f 2197 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 2198}
2199
c21415e8
IM		 2200static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2201{
510043da 2202 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 2203 kvm_emulate_hypercall(vcpu);
2204 return 1;
c21415e8
IM		 2205}
2206
e5edaa01
ED		 2207static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2208{
2209 skip_emulated_instruction(vcpu);
2210 /* TODO: Add support for VT-d/pass-through device */
2211 return 1;
2212}
2213
f78e0e2e
SY		 2214static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2215{
2216 u64 exit_qualification;
2217 enum emulation_result er;
2218 unsigned long offset;
2219
2220 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2221 offset = exit_qualification & 0xffful;
2222
2223 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2224
2225 if (er != EMULATE_DONE) {
2226 printk(KERN_ERR
2227 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2228 offset);
2229 return -ENOTSUPP;
2230 }
2231 return 1;
2232}
2233
6aa8b732
AK		 2234/*
2235 * The exit handlers return 1 if the exit was handled fully and guest execution
2236 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2237 * to be done to userspace and return 0.
2238 */
2239static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2240 struct kvm_run *kvm_run) = {
2241 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2242 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 2243 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
6aa8b732 2244 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 2245 [EXIT_REASON_CR_ACCESS] = handle_cr,
2246 [EXIT_REASON_DR_ACCESS] = handle_dr,
2247 [EXIT_REASON_CPUID] = handle_cpuid,
2248 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2249 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2250 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2251 [EXIT_REASON_HLT] = handle_halt,
c21415e8 2252 [EXIT_REASON_VMCALL] = handle_vmcall,
f78e0e2e
SY		 2253 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
2254 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 2255 [EXIT_REASON_WBINVD] = handle_wbinvd,
6aa8b732
AK		 2256};
2257
2258static const int kvm_vmx_max_exit_handlers =
50a3485c 2259 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 2260
2261/*
2262 * The guest has exited. See if we can fix it or if we need userspace
2263 * assistance.
2264 */
2265static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2266{
6aa8b732 2267 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
29bd8a78 2268 struct vcpu_vmx *vmx = to_vmx(vcpu);
1155f76a 2269 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78
AK		 2270
2271 if (unlikely(vmx->fail)) {
2272 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2273 kvm_run->fail_entry.hardware_entry_failure_reason
2274 = vmcs_read32(VM_INSTRUCTION_ERROR);
2275 return 0;
2276 }
6aa8b732 2277
d77c26fc
MD		 2278 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2279 exit_reason != EXIT_REASON_EXCEPTION_NMI)
6aa8b732 2280 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
b8688d51 2281 "exit reason is 0x%x\n", __func__, exit_reason);
6aa8b732
AK		 2282 if (exit_reason < kvm_vmx_max_exit_handlers
2283 && kvm_vmx_exit_handlers[exit_reason])
2284 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2285 else {
2286 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2287 kvm_run->hw.hardware_exit_reason = exit_reason;
2288 }
2289 return 0;
2290}
2291
6e5d865c
YS		 2292static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2293{
2294 int max_irr, tpr;
2295
2296 if (!vm_need_tpr_shadow(vcpu->kvm))
2297 return;
2298
2299 if (!kvm_lapic_enabled(vcpu) ||
2300 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2301 vmcs_write32(TPR_THRESHOLD, 0);
2302 return;
2303 }
2304
2305 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2306 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2307}
2308
85f455f7
ED		 2309static void enable_irq_window(struct kvm_vcpu *vcpu)
2310{
2311 u32 cpu_based_vm_exec_control;
2312
2313 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2314 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2315 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2316}
2317
2318static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2319{
1155f76a 2320 struct vcpu_vmx *vmx = to_vmx(vcpu);
85f455f7
ED		 2321 u32 idtv_info_field, intr_info_field;
2322 int has_ext_irq, interrupt_window_open;
1b9778da 2323 int vector;
85f455f7 2324
6e5d865c
YS		 2325 update_tpr_threshold(vcpu);
2326
85f455f7
ED		 2327 has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2328 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
1155f76a 2329 idtv_info_field = vmx->idt_vectoring_info;
85f455f7
ED		 2330 if (intr_info_field & INTR_INFO_VALID_MASK) {
2331 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2332 /* TODO: fault when IDT_Vectoring */
9584bf2c
RH		 2333 if (printk_ratelimit())
2334 printk(KERN_ERR "Fault when IDT_Vectoring\n");
85f455f7
ED		 2335 }
2336 if (has_ext_irq)
2337 enable_irq_window(vcpu);
2338 return;
2339 }
2340 if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
9c8cba37
AK		 2341 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2342 == INTR_TYPE_EXT_INTR
ad312c7c 2343 && vcpu->arch.rmode.active) {
9c8cba37
AK		 2344 u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2345
2346 vmx_inject_irq(vcpu, vect);
2347 if (unlikely(has_ext_irq))
2348 enable_irq_window(vcpu);
2349 return;
2350 }
2351
85f455f7
ED		 2352 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2353 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2354 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2355
2e11384c 2356 if (unlikely(idtv_info_field & INTR_INFO_DELIVER_CODE_MASK))
85f455f7
ED		 2357 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2358 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2359 if (unlikely(has_ext_irq))
2360 enable_irq_window(vcpu);
2361 return;
2362 }
2363 if (!has_ext_irq)
2364 return;
2365 interrupt_window_open =
2366 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2367 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1b9778da
ED		 2368 if (interrupt_window_open) {
2369 vector = kvm_cpu_get_interrupt(vcpu);
2370 vmx_inject_irq(vcpu, vector);
2371 kvm_timer_intr_post(vcpu, vector);
2372 } else
85f455f7
ED		 2373 enable_irq_window(vcpu);
2374}
2375
9c8cba37
AK		 2376/*
2377 * Failure to inject an interrupt should give us the information
2378 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
2379 * when fetching the interrupt redirection bitmap in the real-mode
2380 * tss, this doesn't happen. So we do it ourselves.
2381 */
2382static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2383{
2384 vmx->rmode.irq.pending = 0;
2385 if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2386 return;
2387 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2388 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2389 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2390 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2391 return;
2392 }
2393 vmx->idt_vectoring_info =
2394 VECTORING_INFO_VALID_MASK
2395 | INTR_TYPE_EXT_INTR
2396 | vmx->rmode.irq.vector;
2397}
2398
04d2cc77 2399static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2400{
a2fa3e9f 2401 struct vcpu_vmx *vmx = to_vmx(vcpu);
1b6269db 2402 u32 intr_info;
e6adf283
AK		 2403
2404 /*
2405 * Loading guest fpu may have cleared host cr0.ts
2406 */
2407 vmcs_writel(HOST_CR0, read_cr0());
2408
d77c26fc 2409 asm(
6aa8b732 2410 /* Store host registers */
05b3e0c2 2411#ifdef CONFIG_X86_64
c2036300 2412 "push %%rdx; push %%rbp;"
6aa8b732 2413 "push %%rcx \n\t"
6aa8b732 2414#else
ff593e5a
LV		 2415 "push %%edx; push %%ebp;"
2416 "push %%ecx \n\t"
6aa8b732 2417#endif
c2036300 2418 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
6aa8b732 2419 /* Check if vmlaunch of vmresume is needed */
e08aa78a 2420 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 2421 /* Load guest registers. Don't clobber flags. */
05b3e0c2 2422#ifdef CONFIG_X86_64
e08aa78a 2423 "mov %c[cr2](%0), %%rax \n\t"
6aa8b732 2424 "mov %%rax, %%cr2 \n\t"
e08aa78a
AK		 2425 "mov %c[rax](%0), %%rax \n\t"
2426 "mov %c[rbx](%0), %%rbx \n\t"
2427 "mov %c[rdx](%0), %%rdx \n\t"
2428 "mov %c[rsi](%0), %%rsi \n\t"
2429 "mov %c[rdi](%0), %%rdi \n\t"
2430 "mov %c[rbp](%0), %%rbp \n\t"
2431 "mov %c[r8](%0), %%r8 \n\t"
2432 "mov %c[r9](%0), %%r9 \n\t"
2433 "mov %c[r10](%0), %%r10 \n\t"
2434 "mov %c[r11](%0), %%r11 \n\t"
2435 "mov %c[r12](%0), %%r12 \n\t"
2436 "mov %c[r13](%0), %%r13 \n\t"
2437 "mov %c[r14](%0), %%r14 \n\t"
2438 "mov %c[r15](%0), %%r15 \n\t"
2439 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
6aa8b732 2440#else
e08aa78a 2441 "mov %c[cr2](%0), %%eax \n\t"
6aa8b732 2442 "mov %%eax, %%cr2 \n\t"
e08aa78a
AK		 2443 "mov %c[rax](%0), %%eax \n\t"
2444 "mov %c[rbx](%0), %%ebx \n\t"
2445 "mov %c[rdx](%0), %%edx \n\t"
2446 "mov %c[rsi](%0), %%esi \n\t"
2447 "mov %c[rdi](%0), %%edi \n\t"
2448 "mov %c[rbp](%0), %%ebp \n\t"
2449 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
6aa8b732
AK		 2450#endif
2451 /* Enter guest mode */
cd2276a7 2452 "jne .Llaunched \n\t"
6aa8b732 2453 ASM_VMX_VMLAUNCH "\n\t"
cd2276a7
AK		 2454 "jmp .Lkvm_vmx_return \n\t"
2455 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2456 ".Lkvm_vmx_return: "
6aa8b732 2457 /* Save guest registers, load host registers, keep flags */
05b3e0c2 2458#ifdef CONFIG_X86_64
e08aa78a
AK		 2459 "xchg %0, (%%rsp) \n\t"
2460 "mov %%rax, %c[rax](%0) \n\t"
2461 "mov %%rbx, %c[rbx](%0) \n\t"
2462 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2463 "mov %%rdx, %c[rdx](%0) \n\t"
2464 "mov %%rsi, %c[rsi](%0) \n\t"
2465 "mov %%rdi, %c[rdi](%0) \n\t"
2466 "mov %%rbp, %c[rbp](%0) \n\t"
2467 "mov %%r8, %c[r8](%0) \n\t"
2468 "mov %%r9, %c[r9](%0) \n\t"
2469 "mov %%r10, %c[r10](%0) \n\t"
2470 "mov %%r11, %c[r11](%0) \n\t"
2471 "mov %%r12, %c[r12](%0) \n\t"
2472 "mov %%r13, %c[r13](%0) \n\t"
2473 "mov %%r14, %c[r14](%0) \n\t"
2474 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 2475 "mov %%cr2, %%rax \n\t"
e08aa78a 2476 "mov %%rax, %c[cr2](%0) \n\t"
6aa8b732 2477
e08aa78a 2478 "pop %%rbp; pop %%rbp; pop %%rdx \n\t"
6aa8b732 2479#else
e08aa78a
AK		 2480 "xchg %0, (%%esp) \n\t"
2481 "mov %%eax, %c[rax](%0) \n\t"
2482 "mov %%ebx, %c[rbx](%0) \n\t"
2483 "pushl (%%esp); popl %c[rcx](%0) \n\t"
2484 "mov %%edx, %c[rdx](%0) \n\t"
2485 "mov %%esi, %c[rsi](%0) \n\t"
2486 "mov %%edi, %c[rdi](%0) \n\t"
2487 "mov %%ebp, %c[rbp](%0) \n\t"
6aa8b732 2488 "mov %%cr2, %%eax \n\t"
e08aa78a 2489 "mov %%eax, %c[cr2](%0) \n\t"
6aa8b732 2490
e08aa78a 2491 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
6aa8b732 2492#endif
e08aa78a
AK		 2493 "setbe %c[fail](%0) \n\t"
2494 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
2495 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
2496 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
ad312c7c
ZX		 2497 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
2498 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
2499 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
2500 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
2501 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
2502 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
2503 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 2504#ifdef CONFIG_X86_64
ad312c7c
ZX		 2505 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
2506 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
2507 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
2508 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
2509 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
2510 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
2511 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
2512 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 2513#endif
ad312c7c 2514 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300
LV		 2515 : "cc", "memory"
2516#ifdef CONFIG_X86_64
2517 , "rbx", "rdi", "rsi"
2518 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
ff593e5a
LV		 2519#else
2520 , "ebx", "edi", "rsi"
c2036300
LV		 2521#endif
2522 );
6aa8b732 2523
1155f76a 2524 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 2525 if (vmx->rmode.irq.pending)
2526 fixup_rmode_irq(vmx);
1155f76a 2527
ad312c7c 2528 vcpu->arch.interrupt_window_open =
d77c26fc 2529 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
6aa8b732 2530
d77c26fc 2531 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 2532 vmx->launched = 1;
1b6269db
AK		 2533
2534 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2535
2536 /* We need to handle NMIs before interrupts are enabled */
2537 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2538 asm("int $2");
6aa8b732
AK		 2539}
2540
6aa8b732
AK		 2541static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2542{
a2fa3e9f
GH		 2543 struct vcpu_vmx *vmx = to_vmx(vcpu);
2544
2545 if (vmx->vmcs) {
8b9cf98c 2546 on_each_cpu(__vcpu_clear, vmx, 0, 1);
a2fa3e9f
GH		 2547 free_vmcs(vmx->vmcs);
2548 vmx->vmcs = NULL;
6aa8b732
AK		 2549 }
2550}
2551
2552static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2553{
fb3f0f51
RR		 2554 struct vcpu_vmx *vmx = to_vmx(vcpu);
2555
2384d2b3
SY		 2556 spin_lock(&vmx_vpid_lock);
2557 if (vmx->vpid != 0)
2558 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2559 spin_unlock(&vmx_vpid_lock);
6aa8b732 2560 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 2561 kfree(vmx->host_msrs);
2562 kfree(vmx->guest_msrs);
2563 kvm_vcpu_uninit(vcpu);
a4770347 2564 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 2565}
2566
fb3f0f51 2567static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 2568{
fb3f0f51 2569 int err;
c16f862d 2570 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 2571 int cpu;
6aa8b732 2572
a2fa3e9f 2573 if (!vmx)
fb3f0f51
RR		 2574 return ERR_PTR(-ENOMEM);
2575
2384d2b3
SY		 2576 allocate_vpid(vmx);
2577
fb3f0f51
RR		 2578 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2579 if (err)
2580 goto free_vcpu;
965b58a5 2581
a2fa3e9f 2582 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 2583 if (!vmx->guest_msrs) {
2584 err = -ENOMEM;
2585 goto uninit_vcpu;
2586 }
965b58a5 2587
a2fa3e9f
GH		 2588 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2589 if (!vmx->host_msrs)
fb3f0f51 2590 goto free_guest_msrs;
965b58a5 2591
a2fa3e9f
GH		 2592 vmx->vmcs = alloc_vmcs();
2593 if (!vmx->vmcs)
fb3f0f51 2594 goto free_msrs;
a2fa3e9f
GH		 2595
2596 vmcs_clear(vmx->vmcs);
2597
15ad7146
AK		 2598 cpu = get_cpu();
2599 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 2600 err = vmx_vcpu_setup(vmx);
fb3f0f51 2601 vmx_vcpu_put(&vmx->vcpu);
15ad7146 2602 put_cpu();
fb3f0f51
RR		 2603 if (err)
2604 goto free_vmcs;
5e4a0b3c
MT		 2605 if (vm_need_virtualize_apic_accesses(kvm))
2606 if (alloc_apic_access_page(kvm) != 0)
2607 goto free_vmcs;
fb3f0f51
RR		 2608
2609 return &vmx->vcpu;
2610
2611free_vmcs:
2612 free_vmcs(vmx->vmcs);
2613free_msrs:
2614 kfree(vmx->host_msrs);
2615free_guest_msrs:
2616 kfree(vmx->guest_msrs);
2617uninit_vcpu:
2618 kvm_vcpu_uninit(&vmx->vcpu);
2619free_vcpu:
a4770347 2620 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 2621 return ERR_PTR(err);
6aa8b732
AK		 2622}
2623
002c7f7c
YS		 2624static void __init vmx_check_processor_compat(void *rtn)
2625{
2626 struct vmcs_config vmcs_conf;
2627
2628 *(int *)rtn = 0;
2629 if (setup_vmcs_config(&vmcs_conf) < 0)
2630 *(int *)rtn = -EIO;
2631 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2632 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2633 smp_processor_id());
2634 *(int *)rtn = -EIO;
2635 }
2636}
2637
cbdd1bea 2638static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 2639 .cpu_has_kvm_support = cpu_has_kvm_support,
2640 .disabled_by_bios = vmx_disabled_by_bios,
2641 .hardware_setup = hardware_setup,
2642 .hardware_unsetup = hardware_unsetup,
002c7f7c 2643 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 2644 .hardware_enable = hardware_enable,
2645 .hardware_disable = hardware_disable,
774ead3a 2646 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
6aa8b732
AK		 2647
2648 .vcpu_create = vmx_create_vcpu,
2649 .vcpu_free = vmx_free_vcpu,
04d2cc77 2650 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 2651
04d2cc77 2652 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 2653 .vcpu_load = vmx_vcpu_load,
2654 .vcpu_put = vmx_vcpu_put,
774c47f1 2655 .vcpu_decache = vmx_vcpu_decache,
6aa8b732
AK		 2656
2657 .set_guest_debug = set_guest_debug,
04d2cc77 2658 .guest_debug_pre = kvm_guest_debug_pre,
6aa8b732
AK		 2659 .get_msr = vmx_get_msr,
2660 .set_msr = vmx_set_msr,
2661 .get_segment_base = vmx_get_segment_base,
2662 .get_segment = vmx_get_segment,
2663 .set_segment = vmx_set_segment,
6aa8b732 2664 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 2665 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 2666 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 2667 .set_cr3 = vmx_set_cr3,
2668 .set_cr4 = vmx_set_cr4,
6aa8b732 2669 .set_efer = vmx_set_efer,
6aa8b732
AK		 2670 .get_idt = vmx_get_idt,
2671 .set_idt = vmx_set_idt,
2672 .get_gdt = vmx_get_gdt,
2673 .set_gdt = vmx_set_gdt,
2674 .cache_regs = vcpu_load_rsp_rip,
2675 .decache_regs = vcpu_put_rsp_rip,
2676 .get_rflags = vmx_get_rflags,
2677 .set_rflags = vmx_set_rflags,
2678
2679 .tlb_flush = vmx_flush_tlb,
6aa8b732 2680
6aa8b732 2681 .run = vmx_vcpu_run,
04d2cc77 2682 .handle_exit = kvm_handle_exit,
6aa8b732 2683 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 2684 .patch_hypercall = vmx_patch_hypercall,
2a8067f1
ED		 2685 .get_irq = vmx_get_irq,
2686 .set_irq = vmx_inject_irq,
298101da
AK		 2687 .queue_exception = vmx_queue_exception,
2688 .exception_injected = vmx_exception_injected,
04d2cc77
AK		 2689 .inject_pending_irq = vmx_intr_assist,
2690 .inject_pending_vectors = do_interrupt_requests,
cbc94022
IE		 2691
2692 .set_tss_addr = vmx_set_tss_addr,
6aa8b732
AK		 2693};
2694
2695static int __init vmx_init(void)
2696{
fdef3ad1
HQ		 2697 void *iova;
2698 int r;
2699
2700 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2701 if (!vmx_io_bitmap_a)
2702 return -ENOMEM;
2703
2704 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2705 if (!vmx_io_bitmap_b) {
2706 r = -ENOMEM;
2707 goto out;
2708 }
2709
2710 /*
2711 * Allow direct access to the PC debug port (it is often used for I/O
2712 * delays, but the vmexits simply slow things down).
2713 */
2714 iova = kmap(vmx_io_bitmap_a);
2715 memset(iova, 0xff, PAGE_SIZE);
2716 clear_bit(0x80, iova);
cd0536d7 2717 kunmap(vmx_io_bitmap_a);
fdef3ad1
HQ		 2718
2719 iova = kmap(vmx_io_bitmap_b);
2720 memset(iova, 0xff, PAGE_SIZE);
cd0536d7 2721 kunmap(vmx_io_bitmap_b);
fdef3ad1 2722
2384d2b3
SY		 2723 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
2724
cb498ea2 2725 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1
HQ		 2726 if (r)
2727 goto out1;
2728
c7addb90
AK		 2729 if (bypass_guest_pf)
2730 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
2731
fdef3ad1
HQ		 2732 return 0;
2733
2734out1:
2735 __free_page(vmx_io_bitmap_b);
2736out:
2737 __free_page(vmx_io_bitmap_a);
2738 return r;
6aa8b732
AK		 2739}
2740
2741static void __exit vmx_exit(void)
2742{
fdef3ad1
HQ		 2743 __free_page(vmx_io_bitmap_b);
2744 __free_page(vmx_io_bitmap_a);
2745
cb498ea2 2746 kvm_exit();
6aa8b732
AK		 2747}
2748
2749module_init(vmx_init)
2750module_exit(vmx_exit)
Linux 6.x block layer and io_uring tree(s)