projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: VMX: drop rdtscp_enabled field
[linux-2.6-block.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
af658dca 31#include <linux/trace_events.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
952f07ec 43#include <asm/fpu/internal.h>
d7cd9796 44#include <asm/perf_event.h>
81908bf4 45#include <asm/debugreg.h>
8f536b76 46#include <asm/kexec.h>
dab2087d 47#include <asm/apic.h>
6aa8b732 48
229456fc 49#include "trace.h"
25462f7f 50#include "pmu.h"
229456fc 51
4ecac3fd 52#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 53#define __ex_clear(x, reg) \
54 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 55
6aa8b732
AK		 56MODULE_AUTHOR("Qumranet");
57MODULE_LICENSE("GPL");
58
e9bda3b3
JT		 59static const struct x86_cpu_id vmx_cpu_id[] = {
60 X86_FEATURE_MATCH(X86_FEATURE_VMX),
61 {}
62};
63MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
64
476bc001 65static bool __read_mostly enable_vpid = 1;
736caefe 66module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 67
476bc001 68static bool __read_mostly flexpriority_enabled = 1;
736caefe 69module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 70
476bc001 71static bool __read_mostly enable_ept = 1;
736caefe 72module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 73
476bc001 74static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 75module_param_named(unrestricted_guest,
76 enable_unrestricted_guest, bool, S_IRUGO);
77
83c3a331
XH		 78static bool __read_mostly enable_ept_ad_bits = 1;
79module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
80
a27685c3 81static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 82module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 83
476bc001 84static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 85module_param(vmm_exclusive, bool, S_IRUGO);
86
476bc001 87static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 88module_param(fasteoi, bool, S_IRUGO);
89
5a71785d 90static bool __read_mostly enable_apicv = 1;
01e439be 91module_param(enable_apicv, bool, S_IRUGO);
83d4c286 92
abc4fc58
AG		 93static bool __read_mostly enable_shadow_vmcs = 1;
94module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 95/*
96 * If nested=1, nested virtualization is supported, i.e., guests may use
97 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
98 * use VMX instructions.
99 */
476bc001 100static bool __read_mostly nested = 0;
801d3424
NHE		 101module_param(nested, bool, S_IRUGO);
102
20300099
WL		 103static u64 __read_mostly host_xss;
104
843e4330
KH		 105static bool __read_mostly enable_pml = 1;
106module_param_named(pml, enable_pml, bool, S_IRUGO);
107
5037878e
GN		 108#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
109#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 110#define KVM_VM_CR0_ALWAYS_ON \
111 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 112#define KVM_CR4_GUEST_OWNED_BITS \
113 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 114 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 115
cdc0e244
AK		 116#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
117#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
118
78ac8b47
AK		 119#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
120
f4124500
JK		 121#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
122
4b8d54f9
ZE		 123/*
124 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
125 * ple_gap: upper bound on the amount of time between two successive
126 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 127 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 128 * ple_window: upper bound on the amount of time a guest is allowed to execute
129 * in a PAUSE loop. Tests indicate that most spinlocks are held for
130 * less than 2^12 cycles
131 * Time is measured based on a counter that runs at the same rate as the TSC,
132 * refer SDM volume 3b section 21.6.13 & 22.1.3.
133 */
b4a2d31d
RK		 134#define KVM_VMX_DEFAULT_PLE_GAP 128
135#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
136#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
137#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
138#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
139 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
140
4b8d54f9
ZE		 141static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
142module_param(ple_gap, int, S_IRUGO);
143
144static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
145module_param(ple_window, int, S_IRUGO);
146
b4a2d31d
RK		 147/* Default doubles per-vcpu window every exit. */
148static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
149module_param(ple_window_grow, int, S_IRUGO);
150
151/* Default resets per-vcpu window every exit to ple_window. */
152static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
153module_param(ple_window_shrink, int, S_IRUGO);
154
155/* Default is to compute the maximum so we can never overflow. */
156static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
157static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
158module_param(ple_window_max, int, S_IRUGO);
159
83287ea4
AK		 160extern const ulong vmx_return;
161
8bf00a52 162#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 163#define VMCS02_POOL_SIZE 1
61d2ef2c 164
a2fa3e9f
GH		 165struct vmcs {
166 u32 revision_id;
167 u32 abort;
168 char data[0];
169};
170
d462b819
NHE		 171/*
172 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
173 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
174 * loaded on this CPU (so we can clear them if the CPU goes down).
175 */
176struct loaded_vmcs {
177 struct vmcs *vmcs;
178 int cpu;
179 int launched;
180 struct list_head loaded_vmcss_on_cpu_link;
181};
182
26bb0981
AK		 183struct shared_msr_entry {
184 unsigned index;
185 u64 data;
d5696725 186 u64 mask;
26bb0981
AK		 187};
188
a9d30f33
NHE		 189/*
190 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
191 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
192 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
193 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
194 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
195 * More than one of these structures may exist, if L1 runs multiple L2 guests.
196 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
197 * underlying hardware which will be used to run L2.
198 * This structure is packed to ensure that its layout is identical across
199 * machines (necessary for live migration).
200 * If there are changes in this struct, VMCS12_REVISION must be changed.
201 */
22bd0358 202typedef u64 natural_width;
a9d30f33
NHE		 203struct __packed vmcs12 {
204 /* According to the Intel spec, a VMCS region must start with the
205 * following two fields. Then follow implementation-specific data.
206 */
207 u32 revision_id;
208 u32 abort;
22bd0358 209
27d6c865
NHE		 210 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
211 u32 padding[7]; /* room for future expansion */
212
22bd0358
NHE		 213 u64 io_bitmap_a;
214 u64 io_bitmap_b;
215 u64 msr_bitmap;
216 u64 vm_exit_msr_store_addr;
217 u64 vm_exit_msr_load_addr;
218 u64 vm_entry_msr_load_addr;
219 u64 tsc_offset;
220 u64 virtual_apic_page_addr;
221 u64 apic_access_addr;
705699a1 222 u64 posted_intr_desc_addr;
22bd0358 223 u64 ept_pointer;
608406e2
WV		 224 u64 eoi_exit_bitmap0;
225 u64 eoi_exit_bitmap1;
226 u64 eoi_exit_bitmap2;
227 u64 eoi_exit_bitmap3;
81dc01f7 228 u64 xss_exit_bitmap;
22bd0358
NHE		 229 u64 guest_physical_address;
230 u64 vmcs_link_pointer;
231 u64 guest_ia32_debugctl;
232 u64 guest_ia32_pat;
233 u64 guest_ia32_efer;
234 u64 guest_ia32_perf_global_ctrl;
235 u64 guest_pdptr0;
236 u64 guest_pdptr1;
237 u64 guest_pdptr2;
238 u64 guest_pdptr3;
36be0b9d 239 u64 guest_bndcfgs;
22bd0358
NHE		 240 u64 host_ia32_pat;
241 u64 host_ia32_efer;
242 u64 host_ia32_perf_global_ctrl;
243 u64 padding64[8]; /* room for future expansion */
244 /*
245 * To allow migration of L1 (complete with its L2 guests) between
246 * machines of different natural widths (32 or 64 bit), we cannot have
247 * unsigned long fields with no explict size. We use u64 (aliased
248 * natural_width) instead. Luckily, x86 is little-endian.
249 */
250 natural_width cr0_guest_host_mask;
251 natural_width cr4_guest_host_mask;
252 natural_width cr0_read_shadow;
253 natural_width cr4_read_shadow;
254 natural_width cr3_target_value0;
255 natural_width cr3_target_value1;
256 natural_width cr3_target_value2;
257 natural_width cr3_target_value3;
258 natural_width exit_qualification;
259 natural_width guest_linear_address;
260 natural_width guest_cr0;
261 natural_width guest_cr3;
262 natural_width guest_cr4;
263 natural_width guest_es_base;
264 natural_width guest_cs_base;
265 natural_width guest_ss_base;
266 natural_width guest_ds_base;
267 natural_width guest_fs_base;
268 natural_width guest_gs_base;
269 natural_width guest_ldtr_base;
270 natural_width guest_tr_base;
271 natural_width guest_gdtr_base;
272 natural_width guest_idtr_base;
273 natural_width guest_dr7;
274 natural_width guest_rsp;
275 natural_width guest_rip;
276 natural_width guest_rflags;
277 natural_width guest_pending_dbg_exceptions;
278 natural_width guest_sysenter_esp;
279 natural_width guest_sysenter_eip;
280 natural_width host_cr0;
281 natural_width host_cr3;
282 natural_width host_cr4;
283 natural_width host_fs_base;
284 natural_width host_gs_base;
285 natural_width host_tr_base;
286 natural_width host_gdtr_base;
287 natural_width host_idtr_base;
288 natural_width host_ia32_sysenter_esp;
289 natural_width host_ia32_sysenter_eip;
290 natural_width host_rsp;
291 natural_width host_rip;
292 natural_width paddingl[8]; /* room for future expansion */
293 u32 pin_based_vm_exec_control;
294 u32 cpu_based_vm_exec_control;
295 u32 exception_bitmap;
296 u32 page_fault_error_code_mask;
297 u32 page_fault_error_code_match;
298 u32 cr3_target_count;
299 u32 vm_exit_controls;
300 u32 vm_exit_msr_store_count;
301 u32 vm_exit_msr_load_count;
302 u32 vm_entry_controls;
303 u32 vm_entry_msr_load_count;
304 u32 vm_entry_intr_info_field;
305 u32 vm_entry_exception_error_code;
306 u32 vm_entry_instruction_len;
307 u32 tpr_threshold;
308 u32 secondary_vm_exec_control;
309 u32 vm_instruction_error;
310 u32 vm_exit_reason;
311 u32 vm_exit_intr_info;
312 u32 vm_exit_intr_error_code;
313 u32 idt_vectoring_info_field;
314 u32 idt_vectoring_error_code;
315 u32 vm_exit_instruction_len;
316 u32 vmx_instruction_info;
317 u32 guest_es_limit;
318 u32 guest_cs_limit;
319 u32 guest_ss_limit;
320 u32 guest_ds_limit;
321 u32 guest_fs_limit;
322 u32 guest_gs_limit;
323 u32 guest_ldtr_limit;
324 u32 guest_tr_limit;
325 u32 guest_gdtr_limit;
326 u32 guest_idtr_limit;
327 u32 guest_es_ar_bytes;
328 u32 guest_cs_ar_bytes;
329 u32 guest_ss_ar_bytes;
330 u32 guest_ds_ar_bytes;
331 u32 guest_fs_ar_bytes;
332 u32 guest_gs_ar_bytes;
333 u32 guest_ldtr_ar_bytes;
334 u32 guest_tr_ar_bytes;
335 u32 guest_interruptibility_info;
336 u32 guest_activity_state;
337 u32 guest_sysenter_cs;
338 u32 host_ia32_sysenter_cs;
0238ea91
JK		 339 u32 vmx_preemption_timer_value;
340 u32 padding32[7]; /* room for future expansion */
22bd0358 341 u16 virtual_processor_id;
705699a1 342 u16 posted_intr_nv;
22bd0358
NHE		 343 u16 guest_es_selector;
344 u16 guest_cs_selector;
345 u16 guest_ss_selector;
346 u16 guest_ds_selector;
347 u16 guest_fs_selector;
348 u16 guest_gs_selector;
349 u16 guest_ldtr_selector;
350 u16 guest_tr_selector;
608406e2 351 u16 guest_intr_status;
22bd0358
NHE		 352 u16 host_es_selector;
353 u16 host_cs_selector;
354 u16 host_ss_selector;
355 u16 host_ds_selector;
356 u16 host_fs_selector;
357 u16 host_gs_selector;
358 u16 host_tr_selector;
a9d30f33
NHE		 359};
360
361/*
362 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
363 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
364 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
365 */
366#define VMCS12_REVISION 0x11e57ed0
367
368/*
369 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
370 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
371 * current implementation, 4K are reserved to avoid future complications.
372 */
373#define VMCS12_SIZE 0x1000
374
ff2f6fe9
NHE		 375/* Used to remember the last vmcs02 used for some recently used vmcs12s */
376struct vmcs02_list {
377 struct list_head list;
378 gpa_t vmptr;
379 struct loaded_vmcs vmcs02;
380};
381
ec378aee
NHE		 382/*
383 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
384 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
385 */
386struct nested_vmx {
387 /* Has the level1 guest done vmxon? */
388 bool vmxon;
3573e22c 389 gpa_t vmxon_ptr;
a9d30f33
NHE		 390
391 /* The guest-physical address of the current VMCS L1 keeps for L2 */
392 gpa_t current_vmptr;
393 /* The host-usable pointer to the above */
394 struct page *current_vmcs12_page;
395 struct vmcs12 *current_vmcs12;
8de48833 396 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 397 /*
398 * Indicates if the shadow vmcs must be updated with the
399 * data hold by vmcs12
400 */
401 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 402
403 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
404 struct list_head vmcs02_pool;
405 int vmcs02_num;
fe3ef05c 406 u64 vmcs01_tsc_offset;
644d711a
NHE		 407 /* L2 must run next, and mustn't decide to exit to L1. */
408 bool nested_run_pending;
fe3ef05c
NHE		 409 /*
410 * Guest pages referred to in vmcs02 with host-physical pointers, so
411 * we must keep them pinned while L2 runs.
412 */
413 struct page *apic_access_page;
a7c0b07d 414 struct page *virtual_apic_page;
705699a1
WV		 415 struct page *pi_desc_page;
416 struct pi_desc *pi_desc;
417 bool pi_pending;
418 u16 posted_intr_nv;
b3897a49 419 u64 msr_ia32_feature_control;
f4124500
JK		 420
421 struct hrtimer preemption_timer;
422 bool preemption_timer_expired;
2996fca0
JK		 423
424 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
425 u64 vmcs01_debugctl;
b9c237bb
WV		 426
427 u32 nested_vmx_procbased_ctls_low;
428 u32 nested_vmx_procbased_ctls_high;
429 u32 nested_vmx_true_procbased_ctls_low;
430 u32 nested_vmx_secondary_ctls_low;
431 u32 nested_vmx_secondary_ctls_high;
432 u32 nested_vmx_pinbased_ctls_low;
433 u32 nested_vmx_pinbased_ctls_high;
434 u32 nested_vmx_exit_ctls_low;
435 u32 nested_vmx_exit_ctls_high;
436 u32 nested_vmx_true_exit_ctls_low;
437 u32 nested_vmx_entry_ctls_low;
438 u32 nested_vmx_entry_ctls_high;
439 u32 nested_vmx_true_entry_ctls_low;
440 u32 nested_vmx_misc_low;
441 u32 nested_vmx_misc_high;
442 u32 nested_vmx_ept_caps;
ec378aee
NHE		 443};
444
01e439be
YZ		 445#define POSTED_INTR_ON 0
446/* Posted-Interrupt Descriptor */
447struct pi_desc {
448 u32 pir[8]; /* Posted interrupt requested */
449 u32 control; /* bit 0 of control is outstanding notification bit */
450 u32 rsvd[7];
451} __aligned(64);
452
a20ed54d
YZ		 453static bool pi_test_and_set_on(struct pi_desc *pi_desc)
454{
455 return test_and_set_bit(POSTED_INTR_ON,
456 (unsigned long *)&pi_desc->control);
457}
458
459static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
460{
461 return test_and_clear_bit(POSTED_INTR_ON,
462 (unsigned long *)&pi_desc->control);
463}
464
465static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
466{
467 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
468}
469
a2fa3e9f 470struct vcpu_vmx {
fb3f0f51 471 struct kvm_vcpu vcpu;
313dbd49 472 unsigned long host_rsp;
29bd8a78 473 u8 fail;
9d58b931 474 bool nmi_known_unmasked;
51aa01d1 475 u32 exit_intr_info;
1155f76a 476 u32 idt_vectoring_info;
6de12732 477 ulong rflags;
26bb0981 478 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 479 int nmsrs;
480 int save_nmsrs;
a547c6db 481 unsigned long host_idt_base;
a2fa3e9f 482#ifdef CONFIG_X86_64
44ea2b17
AK		 483 u64 msr_host_kernel_gs_base;
484 u64 msr_guest_kernel_gs_base;
a2fa3e9f 485#endif
2961e876
GN		 486 u32 vm_entry_controls_shadow;
487 u32 vm_exit_controls_shadow;
d462b819
NHE		 488 /*
489 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
490 * non-nested (L1) guest, it always points to vmcs01. For a nested
491 * guest (L2), it points to a different VMCS.
492 */
493 struct loaded_vmcs vmcs01;
494 struct loaded_vmcs *loaded_vmcs;
495 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 496 struct msr_autoload {
497 unsigned nr;
498 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
499 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
500 } msr_autoload;
a2fa3e9f
GH		 501 struct {
502 int loaded;
503 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 504#ifdef CONFIG_X86_64
505 u16 ds_sel, es_sel;
506#endif
152d3f2f
LV		 507 int gs_ldt_reload_needed;
508 int fs_reload_needed;
da8999d3 509 u64 msr_host_bndcfgs;
d974baa3 510 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 511 } host_state;
9c8cba37 512 struct {
7ffd92c5 513 int vm86_active;
78ac8b47 514 ulong save_rflags;
f5f7b2fe
AK		 515 struct kvm_segment segs[8];
516 } rmode;
517 struct {
518 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 519 struct kvm_save_segment {
520 u16 selector;
521 unsigned long base;
522 u32 limit;
523 u32 ar;
f5f7b2fe 524 } seg[8];
2fb92db1 525 } segment_cache;
2384d2b3 526 int vpid;
04fa4d32 527 bool emulation_required;
3b86cd99
JK		 528
529 /* Support for vnmi-less CPUs */
530 int soft_vnmi_blocked;
531 ktime_t entry_time;
532 s64 vnmi_blocked_time;
a0861c02 533 u32 exit_reason;
4e47c7a6 534
01e439be
YZ		 535 /* Posted interrupt descriptor */
536 struct pi_desc pi_desc;
537
ec378aee
NHE		 538 /* Support for a guest hypervisor (nested VMX) */
539 struct nested_vmx nested;
a7653ecd
RK		 540
541 /* Dynamic PLE window. */
542 int ple_window;
543 bool ple_window_dirty;
843e4330
KH		 544
545 /* Support for PML */
546#define PML_ENTITY_NUM 512
547 struct page *pml_pg;
a2fa3e9f
GH		 548};
549
2fb92db1
AK		 550enum segment_cache_field {
551 SEG_FIELD_SEL = 0,
552 SEG_FIELD_BASE = 1,
553 SEG_FIELD_LIMIT = 2,
554 SEG_FIELD_AR = 3,
555
556 SEG_FIELD_NR = 4
557};
558
a2fa3e9f
GH		 559static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
560{
fb3f0f51 561 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 562}
563
22bd0358
NHE		 564#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
565#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
566#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
567 [number##_HIGH] = VMCS12_OFFSET(name)+4
568
4607c2d7 569
fe2b201b 570static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 571 /*
572 * We do NOT shadow fields that are modified when L0
573 * traps and emulates any vmx instruction (e.g. VMPTRLD,
574 * VMXON...) executed by L1.
575 * For example, VM_INSTRUCTION_ERROR is read
576 * by L1 if a vmx instruction fails (part of the error path).
577 * Note the code assumes this logic. If for some reason
578 * we start shadowing these fields then we need to
579 * force a shadow sync when L0 emulates vmx instructions
580 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
581 * by nested_vmx_failValid)
582 */
583 VM_EXIT_REASON,
584 VM_EXIT_INTR_INFO,
585 VM_EXIT_INSTRUCTION_LEN,
586 IDT_VECTORING_INFO_FIELD,
587 IDT_VECTORING_ERROR_CODE,
588 VM_EXIT_INTR_ERROR_CODE,
589 EXIT_QUALIFICATION,
590 GUEST_LINEAR_ADDRESS,
591 GUEST_PHYSICAL_ADDRESS
592};
fe2b201b 593static int max_shadow_read_only_fields =
4607c2d7
AG		 594 ARRAY_SIZE(shadow_read_only_fields);
595
fe2b201b 596static unsigned long shadow_read_write_fields[] = {
a7c0b07d 597 TPR_THRESHOLD,
4607c2d7
AG		 598 GUEST_RIP,
599 GUEST_RSP,
600 GUEST_CR0,
601 GUEST_CR3,
602 GUEST_CR4,
603 GUEST_INTERRUPTIBILITY_INFO,
604 GUEST_RFLAGS,
605 GUEST_CS_SELECTOR,
606 GUEST_CS_AR_BYTES,
607 GUEST_CS_LIMIT,
608 GUEST_CS_BASE,
609 GUEST_ES_BASE,
36be0b9d 610 GUEST_BNDCFGS,
4607c2d7
AG		 611 CR0_GUEST_HOST_MASK,
612 CR0_READ_SHADOW,
613 CR4_READ_SHADOW,
614 TSC_OFFSET,
615 EXCEPTION_BITMAP,
616 CPU_BASED_VM_EXEC_CONTROL,
617 VM_ENTRY_EXCEPTION_ERROR_CODE,
618 VM_ENTRY_INTR_INFO_FIELD,
619 VM_ENTRY_INSTRUCTION_LEN,
620 VM_ENTRY_EXCEPTION_ERROR_CODE,
621 HOST_FS_BASE,
622 HOST_GS_BASE,
623 HOST_FS_SELECTOR,
624 HOST_GS_SELECTOR
625};
fe2b201b 626static int max_shadow_read_write_fields =
4607c2d7
AG		 627 ARRAY_SIZE(shadow_read_write_fields);
628
772e0318 629static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358 630 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
705699a1 631 FIELD(POSTED_INTR_NV, posted_intr_nv),
22bd0358
NHE		 632 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
633 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
634 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
635 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
636 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
637 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
638 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
639 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
608406e2 640 FIELD(GUEST_INTR_STATUS, guest_intr_status),
22bd0358
NHE		 641 FIELD(HOST_ES_SELECTOR, host_es_selector),
642 FIELD(HOST_CS_SELECTOR, host_cs_selector),
643 FIELD(HOST_SS_SELECTOR, host_ss_selector),
644 FIELD(HOST_DS_SELECTOR, host_ds_selector),
645 FIELD(HOST_FS_SELECTOR, host_fs_selector),
646 FIELD(HOST_GS_SELECTOR, host_gs_selector),
647 FIELD(HOST_TR_SELECTOR, host_tr_selector),
648 FIELD64(IO_BITMAP_A, io_bitmap_a),
649 FIELD64(IO_BITMAP_B, io_bitmap_b),
650 FIELD64(MSR_BITMAP, msr_bitmap),
651 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
652 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
653 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
654 FIELD64(TSC_OFFSET, tsc_offset),
655 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
656 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
705699a1 657 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
22bd0358 658 FIELD64(EPT_POINTER, ept_pointer),
608406e2
WV		 659 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
660 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
661 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
662 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
81dc01f7 663 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE		 664 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
665 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
666 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
667 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
668 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
669 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
670 FIELD64(GUEST_PDPTR0, guest_pdptr0),
671 FIELD64(GUEST_PDPTR1, guest_pdptr1),
672 FIELD64(GUEST_PDPTR2, guest_pdptr2),
673 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 674 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 675 FIELD64(HOST_IA32_PAT, host_ia32_pat),
676 FIELD64(HOST_IA32_EFER, host_ia32_efer),
677 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
678 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
679 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
680 FIELD(EXCEPTION_BITMAP, exception_bitmap),
681 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
682 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
683 FIELD(CR3_TARGET_COUNT, cr3_target_count),
684 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
685 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
686 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
687 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
688 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
689 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
690 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
691 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
692 FIELD(TPR_THRESHOLD, tpr_threshold),
693 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
694 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
695 FIELD(VM_EXIT_REASON, vm_exit_reason),
696 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
697 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
698 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
699 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
700 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
701 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
702 FIELD(GUEST_ES_LIMIT, guest_es_limit),
703 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
704 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
705 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
706 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
707 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
708 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
709 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
710 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
711 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
712 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
713 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
714 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
715 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
716 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
717 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
718 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
719 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
720 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
721 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
722 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
723 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 724 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 725 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
726 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
727 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
728 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
729 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
730 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
731 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
732 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
733 FIELD(EXIT_QUALIFICATION, exit_qualification),
734 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
735 FIELD(GUEST_CR0, guest_cr0),
736 FIELD(GUEST_CR3, guest_cr3),
737 FIELD(GUEST_CR4, guest_cr4),
738 FIELD(GUEST_ES_BASE, guest_es_base),
739 FIELD(GUEST_CS_BASE, guest_cs_base),
740 FIELD(GUEST_SS_BASE, guest_ss_base),
741 FIELD(GUEST_DS_BASE, guest_ds_base),
742 FIELD(GUEST_FS_BASE, guest_fs_base),
743 FIELD(GUEST_GS_BASE, guest_gs_base),
744 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
745 FIELD(GUEST_TR_BASE, guest_tr_base),
746 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
747 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
748 FIELD(GUEST_DR7, guest_dr7),
749 FIELD(GUEST_RSP, guest_rsp),
750 FIELD(GUEST_RIP, guest_rip),
751 FIELD(GUEST_RFLAGS, guest_rflags),
752 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
753 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
754 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
755 FIELD(HOST_CR0, host_cr0),
756 FIELD(HOST_CR3, host_cr3),
757 FIELD(HOST_CR4, host_cr4),
758 FIELD(HOST_FS_BASE, host_fs_base),
759 FIELD(HOST_GS_BASE, host_gs_base),
760 FIELD(HOST_TR_BASE, host_tr_base),
761 FIELD(HOST_GDTR_BASE, host_gdtr_base),
762 FIELD(HOST_IDTR_BASE, host_idtr_base),
763 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
764 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
765 FIELD(HOST_RSP, host_rsp),
766 FIELD(HOST_RIP, host_rip),
767};
22bd0358
NHE		 768
769static inline short vmcs_field_to_offset(unsigned long field)
770{
a2ae9df7
PB		 771 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
772
773 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
774 vmcs_field_to_offset_table[field] == 0)
775 return -ENOENT;
776
22bd0358
NHE		 777 return vmcs_field_to_offset_table[field];
778}
779
a9d30f33
NHE		 780static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
781{
782 return to_vmx(vcpu)->nested.current_vmcs12;
783}
784
785static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
786{
54bf36aa 787 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
32cad84f 788 if (is_error_page(page))
a9d30f33 789 return NULL;
32cad84f 790
a9d30f33
NHE		 791 return page;
792}
793
794static void nested_release_page(struct page *page)
795{
796 kvm_release_page_dirty(page);
797}
798
799static void nested_release_page_clean(struct page *page)
800{
801 kvm_release_page_clean(page);
802}
803
bfd0a56b 804static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 805static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 806static void kvm_cpu_vmxon(u64 addr);
807static void kvm_cpu_vmxoff(void);
93c4adc7 808static bool vmx_mpx_supported(void);
f53cd63c 809static bool vmx_xsaves_supported(void);
d50ab6c1 810static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
776e58ea 811static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 812static void vmx_set_segment(struct kvm_vcpu *vcpu,
813 struct kvm_segment *var, int seg);
814static void vmx_get_segment(struct kvm_vcpu *vcpu,
815 struct kvm_segment *var, int seg);
d99e4152
GN		 816static bool guest_state_valid(struct kvm_vcpu *vcpu);
817static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 818static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 819static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 820static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 821static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 822
6aa8b732
AK		 823static DEFINE_PER_CPU(struct vmcs *, vmxarea);
824static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 825/*
826 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
827 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
828 */
829static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 830static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 831
3e7c73e9
AK		 832static unsigned long *vmx_io_bitmap_a;
833static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 834static unsigned long *vmx_msr_bitmap_legacy;
835static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 836static unsigned long *vmx_msr_bitmap_legacy_x2apic;
837static unsigned long *vmx_msr_bitmap_longmode_x2apic;
3af18d9c 838static unsigned long *vmx_msr_bitmap_nested;
4607c2d7
AG		 839static unsigned long *vmx_vmread_bitmap;
840static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 841
110312c8 842static bool cpu_has_load_ia32_efer;
8bf00a52 843static bool cpu_has_load_perf_global_ctrl;
110312c8 844
2384d2b3
SY		 845static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
846static DEFINE_SPINLOCK(vmx_vpid_lock);
847
1c3d14fe 848static struct vmcs_config {
6aa8b732
AK		 849 int size;
850 int order;
851 u32 revision_id;
1c3d14fe
YS		 852 u32 pin_based_exec_ctrl;
853 u32 cpu_based_exec_ctrl;
f78e0e2e 854 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 855 u32 vmexit_ctrl;
856 u32 vmentry_ctrl;
857} vmcs_config;
6aa8b732 858
efff9e53 859static struct vmx_capability {
d56f546d
SY		 860 u32 ept;
861 u32 vpid;
862} vmx_capability;
863
6aa8b732
AK		 864#define VMX_SEGMENT_FIELD(seg) \
865 [VCPU_SREG_##seg] = { \
866 .selector = GUEST_##seg##_SELECTOR, \
867 .base = GUEST_##seg##_BASE, \
868 .limit = GUEST_##seg##_LIMIT, \
869 .ar_bytes = GUEST_##seg##_AR_BYTES, \
870 }
871
772e0318 872static const struct kvm_vmx_segment_field {
6aa8b732
AK		 873 unsigned selector;
874 unsigned base;
875 unsigned limit;
876 unsigned ar_bytes;
877} kvm_vmx_segment_fields[] = {
878 VMX_SEGMENT_FIELD(CS),
879 VMX_SEGMENT_FIELD(DS),
880 VMX_SEGMENT_FIELD(ES),
881 VMX_SEGMENT_FIELD(FS),
882 VMX_SEGMENT_FIELD(GS),
883 VMX_SEGMENT_FIELD(SS),
884 VMX_SEGMENT_FIELD(TR),
885 VMX_SEGMENT_FIELD(LDTR),
886};
887
26bb0981
AK		 888static u64 host_efer;
889
6de4f3ad
AK		 890static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
891
4d56c8a7 892/*
8c06585d 893 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 894 * away by decrementing the array size.
895 */
6aa8b732 896static const u32 vmx_msr_index[] = {
05b3e0c2 897#ifdef CONFIG_X86_64
44ea2b17 898 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 899#endif
8c06585d 900 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 901};
6aa8b732 902
31299944 903static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 904{
905 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
906 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 907 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 908}
909
31299944 910static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 911{
912 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
913 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 914 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 915}
916
31299944 917static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 918{
919 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
920 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 921 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 922}
923
31299944 924static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 925{
926 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
927 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
928}
929
31299944 930static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 931{
932 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
933 INTR_INFO_VALID_MASK)) ==
934 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
935}
936
31299944 937static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 938{
04547156 939 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 940}
941
31299944 942static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 943{
04547156 944 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 945}
946
35754c98 947static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
6e5d865c 948{
35754c98 949 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
6e5d865c
YS		 950}
951
31299944 952static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 953{
04547156
SY		 954 return vmcs_config.cpu_based_exec_ctrl &
955 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 956}
957
774ead3a 958static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 959{
04547156
SY		 960 return vmcs_config.cpu_based_2nd_exec_ctrl &
961 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
962}
963
8d14695f
YZ		 964static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
965{
966 return vmcs_config.cpu_based_2nd_exec_ctrl &
967 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
968}
969
83d4c286
YZ		 970static inline bool cpu_has_vmx_apic_register_virt(void)
971{
972 return vmcs_config.cpu_based_2nd_exec_ctrl &
973 SECONDARY_EXEC_APIC_REGISTER_VIRT;
974}
975
c7c9c56c
YZ		 976static inline bool cpu_has_vmx_virtual_intr_delivery(void)
977{
978 return vmcs_config.cpu_based_2nd_exec_ctrl &
979 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
980}
981
01e439be
YZ		 982static inline bool cpu_has_vmx_posted_intr(void)
983{
d6a858d1
PB		 984 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
985 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
01e439be
YZ		 986}
987
988static inline bool cpu_has_vmx_apicv(void)
989{
990 return cpu_has_vmx_apic_register_virt() &&
991 cpu_has_vmx_virtual_intr_delivery() &&
992 cpu_has_vmx_posted_intr();
993}
994
04547156
SY		 995static inline bool cpu_has_vmx_flexpriority(void)
996{
997 return cpu_has_vmx_tpr_shadow() &&
998 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 999}
1000
e799794e
MT		 1001static inline bool cpu_has_vmx_ept_execute_only(void)
1002{
31299944 1003 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 1004}
1005
e799794e
MT		 1006static inline bool cpu_has_vmx_ept_2m_page(void)
1007{
31299944 1008 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 1009}
1010
878403b7
SY		 1011static inline bool cpu_has_vmx_ept_1g_page(void)
1012{
31299944 1013 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 1014}
1015
4bc9b982
SY		 1016static inline bool cpu_has_vmx_ept_4levels(void)
1017{
1018 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1019}
1020
83c3a331
XH		 1021static inline bool cpu_has_vmx_ept_ad_bits(void)
1022{
1023 return vmx_capability.ept & VMX_EPT_AD_BIT;
1024}
1025
31299944 1026static inline bool cpu_has_vmx_invept_context(void)
d56f546d 1027{
31299944 1028 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 1029}
1030
31299944 1031static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1032{
31299944 1033 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 1034}
1035
518c8aee
GJ		 1036static inline bool cpu_has_vmx_invvpid_single(void)
1037{
1038 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1039}
1040
b9d762fa
GJ		 1041static inline bool cpu_has_vmx_invvpid_global(void)
1042{
1043 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1044}
1045
31299944 1046static inline bool cpu_has_vmx_ept(void)
d56f546d 1047{
04547156
SY		 1048 return vmcs_config.cpu_based_2nd_exec_ctrl &
1049 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1050}
1051
31299944 1052static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1053{
1054 return vmcs_config.cpu_based_2nd_exec_ctrl &
1055 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1056}
1057
31299944 1058static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1059{
1060 return vmcs_config.cpu_based_2nd_exec_ctrl &
1061 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1062}
1063
35754c98 1064static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 1065{
35754c98 1066 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY		 1067}
1068
31299944 1069static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1070{
04547156
SY		 1071 return vmcs_config.cpu_based_2nd_exec_ctrl &
1072 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1073}
1074
31299944 1075static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1076{
1077 return vmcs_config.cpu_based_2nd_exec_ctrl &
1078 SECONDARY_EXEC_RDTSCP;
1079}
1080
ad756a16
MJ		 1081static inline bool cpu_has_vmx_invpcid(void)
1082{
1083 return vmcs_config.cpu_based_2nd_exec_ctrl &
1084 SECONDARY_EXEC_ENABLE_INVPCID;
1085}
1086
31299944 1087static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1088{
1089 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1090}
1091
f5f48ee1
SY		 1092static inline bool cpu_has_vmx_wbinvd_exit(void)
1093{
1094 return vmcs_config.cpu_based_2nd_exec_ctrl &
1095 SECONDARY_EXEC_WBINVD_EXITING;
1096}
1097
abc4fc58
AG		 1098static inline bool cpu_has_vmx_shadow_vmcs(void)
1099{
1100 u64 vmx_msr;
1101 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1102 /* check if the cpu supports writing r/o exit information fields */
1103 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1104 return false;
1105
1106 return vmcs_config.cpu_based_2nd_exec_ctrl &
1107 SECONDARY_EXEC_SHADOW_VMCS;
1108}
1109
843e4330
KH		 1110static inline bool cpu_has_vmx_pml(void)
1111{
1112 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1113}
1114
04547156
SY		 1115static inline bool report_flexpriority(void)
1116{
1117 return flexpriority_enabled;
1118}
1119
fe3ef05c
NHE		 1120static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1121{
1122 return vmcs12->cpu_based_vm_exec_control & bit;
1123}
1124
1125static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1126{
1127 return (vmcs12->cpu_based_vm_exec_control &
1128 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1129 (vmcs12->secondary_vm_exec_control & bit);
1130}
1131
f5c4368f 1132static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1133{
1134 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1135}
1136
f4124500
JK		 1137static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1138{
1139 return vmcs12->pin_based_vm_exec_control &
1140 PIN_BASED_VMX_PREEMPTION_TIMER;
1141}
1142
155a97a3
NHE		 1143static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1144{
1145 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1146}
1147
81dc01f7
WL		 1148static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1149{
1150 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1151 vmx_xsaves_supported();
1152}
1153
f2b93280
WV		 1154static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1155{
1156 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1157}
1158
82f0dd4b
WV		 1159static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1160{
1161 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1162}
1163
608406e2
WV		 1164static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1165{
1166 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1167}
1168
705699a1
WV		 1169static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1170{
1171 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1172}
1173
644d711a
NHE		 1174static inline bool is_exception(u32 intr_info)
1175{
1176 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1177 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1178}
1179
533558bc
JK		 1180static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1181 u32 exit_intr_info,
1182 unsigned long exit_qualification);
7c177938
NHE		 1183static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1184 struct vmcs12 *vmcs12,
1185 u32 reason, unsigned long qualification);
1186
8b9cf98c 1187static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1188{
1189 int i;
1190
a2fa3e9f 1191 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1192 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1193 return i;
1194 return -1;
1195}
1196
2384d2b3
SY		 1197static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1198{
1199 struct {
1200 u64 vpid : 16;
1201 u64 rsvd : 48;
1202 u64 gva;
1203 } operand = { vpid, 0, gva };
1204
4ecac3fd 1205 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1206 /* CF==1 or ZF==1 --> rc = -1 */
1207 "; ja 1f ; ud2 ; 1:"
1208 : : "a"(&operand), "c"(ext) : "cc", "memory");
1209}
1210
1439442c
SY		 1211static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1212{
1213 struct {
1214 u64 eptp, gpa;
1215 } operand = {eptp, gpa};
1216
4ecac3fd 1217 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1218 /* CF==1 or ZF==1 --> rc = -1 */
1219 "; ja 1f ; ud2 ; 1:\n"
1220 : : "a" (&operand), "c" (ext) : "cc", "memory");
1221}
1222
26bb0981 1223static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1224{
1225 int i;
1226
8b9cf98c 1227 i = __find_msr_index(vmx, msr);
a75beee6 1228 if (i >= 0)
a2fa3e9f 1229 return &vmx->guest_msrs[i];
8b6d44c7 1230 return NULL;
7725f0ba
AK		 1231}
1232
6aa8b732
AK		 1233static void vmcs_clear(struct vmcs *vmcs)
1234{
1235 u64 phys_addr = __pa(vmcs);
1236 u8 error;
1237
4ecac3fd 1238 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1239 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1240 : "cc", "memory");
1241 if (error)
1242 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1243 vmcs, phys_addr);
1244}
1245
d462b819
NHE		 1246static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1247{
1248 vmcs_clear(loaded_vmcs->vmcs);
1249 loaded_vmcs->cpu = -1;
1250 loaded_vmcs->launched = 0;
1251}
1252
7725b894
DX		 1253static void vmcs_load(struct vmcs *vmcs)
1254{
1255 u64 phys_addr = __pa(vmcs);
1256 u8 error;
1257
1258 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1259 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1260 : "cc", "memory");
1261 if (error)
2844d849 1262 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1263 vmcs, phys_addr);
1264}
1265
2965faa5 1266#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 1267/*
1268 * This bitmap is used to indicate whether the vmclear
1269 * operation is enabled on all cpus. All disabled by
1270 * default.
1271 */
1272static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1273
1274static inline void crash_enable_local_vmclear(int cpu)
1275{
1276 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1277}
1278
1279static inline void crash_disable_local_vmclear(int cpu)
1280{
1281 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1282}
1283
1284static inline int crash_local_vmclear_enabled(int cpu)
1285{
1286 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1287}
1288
1289static void crash_vmclear_local_loaded_vmcss(void)
1290{
1291 int cpu = raw_smp_processor_id();
1292 struct loaded_vmcs *v;
1293
1294 if (!crash_local_vmclear_enabled(cpu))
1295 return;
1296
1297 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1298 loaded_vmcss_on_cpu_link)
1299 vmcs_clear(v->vmcs);
1300}
1301#else
1302static inline void crash_enable_local_vmclear(int cpu) { }
1303static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 1304#endif /* CONFIG_KEXEC_CORE */
8f536b76 1305
d462b819 1306static void __loaded_vmcs_clear(void *arg)
6aa8b732 1307{
d462b819 1308 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1309 int cpu = raw_smp_processor_id();
6aa8b732 1310
d462b819
NHE		 1311 if (loaded_vmcs->cpu != cpu)
1312 return; /* vcpu migration can race with cpu offline */
1313 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1314 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1315 crash_disable_local_vmclear(cpu);
d462b819 1316 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1317
1318 /*
1319 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1320 * is before setting loaded_vmcs->vcpu to -1 which is done in
1321 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1322 * then adds the vmcs into percpu list before it is deleted.
1323 */
1324 smp_wmb();
1325
d462b819 1326 loaded_vmcs_init(loaded_vmcs);
8f536b76 1327 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1328}
1329
d462b819 1330static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1331{
e6c7d321
XG		 1332 int cpu = loaded_vmcs->cpu;
1333
1334 if (cpu != -1)
1335 smp_call_function_single(cpu,
1336 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1337}
1338
1760dd49 1339static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1340{
1341 if (vmx->vpid == 0)
1342 return;
1343
518c8aee
GJ		 1344 if (cpu_has_vmx_invvpid_single())
1345 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1346}
1347
b9d762fa
GJ		 1348static inline void vpid_sync_vcpu_global(void)
1349{
1350 if (cpu_has_vmx_invvpid_global())
1351 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1352}
1353
1354static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1355{
1356 if (cpu_has_vmx_invvpid_single())
1760dd49 1357 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1358 else
1359 vpid_sync_vcpu_global();
1360}
1361
1439442c
SY		 1362static inline void ept_sync_global(void)
1363{
1364 if (cpu_has_vmx_invept_global())
1365 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1366}
1367
1368static inline void ept_sync_context(u64 eptp)
1369{
089d034e 1370 if (enable_ept) {
1439442c
SY		 1371 if (cpu_has_vmx_invept_context())
1372 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1373 else
1374 ept_sync_global();
1375 }
1376}
1377
96304217 1378static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1379{
5e520e62 1380 unsigned long value;
6aa8b732 1381
5e520e62
AK		 1382 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1383 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1384 return value;
1385}
1386
96304217 1387static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1388{
1389 return vmcs_readl(field);
1390}
1391
96304217 1392static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1393{
1394 return vmcs_readl(field);
1395}
1396
96304217 1397static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1398{
05b3e0c2 1399#ifdef CONFIG_X86_64
6aa8b732
AK		 1400 return vmcs_readl(field);
1401#else
1402 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1403#endif
1404}
1405
e52de1b8
AK		 1406static noinline void vmwrite_error(unsigned long field, unsigned long value)
1407{
1408 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1409 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1410 dump_stack();
1411}
1412
6aa8b732
AK		 1413static void vmcs_writel(unsigned long field, unsigned long value)
1414{
1415 u8 error;
1416
4ecac3fd 1417 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1418 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1419 if (unlikely(error))
1420 vmwrite_error(field, value);
6aa8b732
AK		 1421}
1422
1423static void vmcs_write16(unsigned long field, u16 value)
1424{
1425 vmcs_writel(field, value);
1426}
1427
1428static void vmcs_write32(unsigned long field, u32 value)
1429{
1430 vmcs_writel(field, value);
1431}
1432
1433static void vmcs_write64(unsigned long field, u64 value)
1434{
6aa8b732 1435 vmcs_writel(field, value);
7682f2d0 1436#ifndef CONFIG_X86_64
6aa8b732
AK		 1437 asm volatile ("");
1438 vmcs_writel(field+1, value >> 32);
1439#endif
1440}
1441
2ab455cc
AL		 1442static void vmcs_clear_bits(unsigned long field, u32 mask)
1443{
1444 vmcs_writel(field, vmcs_readl(field) & ~mask);
1445}
1446
1447static void vmcs_set_bits(unsigned long field, u32 mask)
1448{
1449 vmcs_writel(field, vmcs_readl(field) | mask);
1450}
1451
2961e876
GN		 1452static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1453{
1454 vmcs_write32(VM_ENTRY_CONTROLS, val);
1455 vmx->vm_entry_controls_shadow = val;
1456}
1457
1458static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1459{
1460 if (vmx->vm_entry_controls_shadow != val)
1461 vm_entry_controls_init(vmx, val);
1462}
1463
1464static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1465{
1466 return vmx->vm_entry_controls_shadow;
1467}
1468
1469
1470static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1471{
1472 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1473}
1474
1475static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1476{
1477 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1478}
1479
1480static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1481{
1482 vmcs_write32(VM_EXIT_CONTROLS, val);
1483 vmx->vm_exit_controls_shadow = val;
1484}
1485
1486static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1487{
1488 if (vmx->vm_exit_controls_shadow != val)
1489 vm_exit_controls_init(vmx, val);
1490}
1491
1492static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1493{
1494 return vmx->vm_exit_controls_shadow;
1495}
1496
1497
1498static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1499{
1500 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1501}
1502
1503static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1504{
1505 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1506}
1507
2fb92db1
AK		 1508static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1509{
1510 vmx->segment_cache.bitmask = 0;
1511}
1512
1513static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1514 unsigned field)
1515{
1516 bool ret;
1517 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1518
1519 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1520 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1521 vmx->segment_cache.bitmask = 0;
1522 }
1523 ret = vmx->segment_cache.bitmask & mask;
1524 vmx->segment_cache.bitmask |= mask;
1525 return ret;
1526}
1527
1528static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1529{
1530 u16 *p = &vmx->segment_cache.seg[seg].selector;
1531
1532 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1533 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1534 return *p;
1535}
1536
1537static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1538{
1539 ulong *p = &vmx->segment_cache.seg[seg].base;
1540
1541 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1542 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1543 return *p;
1544}
1545
1546static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1547{
1548 u32 *p = &vmx->segment_cache.seg[seg].limit;
1549
1550 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1551 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1552 return *p;
1553}
1554
1555static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1556{
1557 u32 *p = &vmx->segment_cache.seg[seg].ar;
1558
1559 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1560 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1561 return *p;
1562}
1563
abd3f2d6
AK		 1564static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1565{
1566 u32 eb;
1567
fd7373cc
JK		 1568 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1569 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1570 if ((vcpu->guest_debug &
1571 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1572 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1573 eb |= 1u << BP_VECTOR;
7ffd92c5 1574 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1575 eb = ~0;
089d034e 1576 if (enable_ept)
1439442c 1577 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1578 if (vcpu->fpu_active)
1579 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1580
1581 /* When we are running a nested L2 guest and L1 specified for it a
1582 * certain exception bitmap, we must trap the same exceptions and pass
1583 * them to L1. When running L2, we will only handle the exceptions
1584 * specified above if L1 did not want them.
1585 */
1586 if (is_guest_mode(vcpu))
1587 eb |= get_vmcs12(vcpu)->exception_bitmap;
1588
abd3f2d6
AK		 1589 vmcs_write32(EXCEPTION_BITMAP, eb);
1590}
1591
2961e876
GN		 1592static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1593 unsigned long entry, unsigned long exit)
8bf00a52 1594{
2961e876
GN		 1595 vm_entry_controls_clearbit(vmx, entry);
1596 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1597}
1598
61d2ef2c
AK		 1599static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1600{
1601 unsigned i;
1602 struct msr_autoload *m = &vmx->msr_autoload;
1603
8bf00a52
GN		 1604 switch (msr) {
1605 case MSR_EFER:
1606 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1607 clear_atomic_switch_msr_special(vmx,
1608 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1609 VM_EXIT_LOAD_IA32_EFER);
1610 return;
1611 }
1612 break;
1613 case MSR_CORE_PERF_GLOBAL_CTRL:
1614 if (cpu_has_load_perf_global_ctrl) {
2961e876 1615 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1616 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1617 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1618 return;
1619 }
1620 break;
110312c8
AK		 1621 }
1622
61d2ef2c
AK		 1623 for (i = 0; i < m->nr; ++i)
1624 if (m->guest[i].index == msr)
1625 break;
1626
1627 if (i == m->nr)
1628 return;
1629 --m->nr;
1630 m->guest[i] = m->guest[m->nr];
1631 m->host[i] = m->host[m->nr];
1632 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1633 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1634}
1635
2961e876
GN		 1636static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1637 unsigned long entry, unsigned long exit,
1638 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1639 u64 guest_val, u64 host_val)
8bf00a52
GN		 1640{
1641 vmcs_write64(guest_val_vmcs, guest_val);
1642 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1643 vm_entry_controls_setbit(vmx, entry);
1644 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1645}
1646
61d2ef2c
AK		 1647static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1648 u64 guest_val, u64 host_val)
1649{
1650 unsigned i;
1651 struct msr_autoload *m = &vmx->msr_autoload;
1652
8bf00a52
GN		 1653 switch (msr) {
1654 case MSR_EFER:
1655 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1656 add_atomic_switch_msr_special(vmx,
1657 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1658 VM_EXIT_LOAD_IA32_EFER,
1659 GUEST_IA32_EFER,
1660 HOST_IA32_EFER,
1661 guest_val, host_val);
1662 return;
1663 }
1664 break;
1665 case MSR_CORE_PERF_GLOBAL_CTRL:
1666 if (cpu_has_load_perf_global_ctrl) {
2961e876 1667 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1668 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1669 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1670 GUEST_IA32_PERF_GLOBAL_CTRL,
1671 HOST_IA32_PERF_GLOBAL_CTRL,
1672 guest_val, host_val);
1673 return;
1674 }
1675 break;
110312c8
AK		 1676 }
1677
61d2ef2c
AK		 1678 for (i = 0; i < m->nr; ++i)
1679 if (m->guest[i].index == msr)
1680 break;
1681
e7fc6f93 1682 if (i == NR_AUTOLOAD_MSRS) {
60266204 1683 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1684 "Can't add msr %x\n", msr);
1685 return;
1686 } else if (i == m->nr) {
61d2ef2c
AK		 1687 ++m->nr;
1688 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1689 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1690 }
1691
1692 m->guest[i].index = msr;
1693 m->guest[i].value = guest_val;
1694 m->host[i].index = msr;
1695 m->host[i].value = host_val;
1696}
1697
33ed6329
AK		 1698static void reload_tss(void)
1699{
33ed6329
AK		 1700 /*
1701 * VT restores TR but not its size. Useless.
1702 */
89cbc767 1703 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1704 struct desc_struct *descs;
33ed6329 1705
d359192f 1706 descs = (void *)gdt->address;
33ed6329
AK		 1707 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1708 load_TR_desc();
33ed6329
AK		 1709}
1710
92c0d900 1711static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1712{
3a34a881 1713 u64 guest_efer;
51c6cf66
AK		 1714 u64 ignore_bits;
1715
f6801dff 1716 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1717
51c6cf66 1718 /*
0fa06071 1719 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1720 * outside long mode
1721 */
1722 ignore_bits = EFER_NX | EFER_SCE;
1723#ifdef CONFIG_X86_64
1724 ignore_bits |= EFER_LMA | EFER_LME;
1725 /* SCE is meaningful only in long mode on Intel */
1726 if (guest_efer & EFER_LMA)
1727 ignore_bits &= ~(u64)EFER_SCE;
1728#endif
51c6cf66
AK		 1729 guest_efer &= ~ignore_bits;
1730 guest_efer |= host_efer & ignore_bits;
26bb0981 1731 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1732 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1733
1734 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL		 1735
1736 /*
1737 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1738 * On CPUs that support "load IA32_EFER", always switch EFER
1739 * atomically, since it's faster than switching it manually.
1740 */
1741 if (cpu_has_load_ia32_efer ||
1742 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1743 guest_efer = vmx->vcpu.arch.efer;
1744 if (!(guest_efer & EFER_LMA))
1745 guest_efer &= ~EFER_LME;
54b98bff
AL		 1746 if (guest_efer != host_efer)
1747 add_atomic_switch_msr(vmx, MSR_EFER,
1748 guest_efer, host_efer);
84ad33ef
AK		 1749 return false;
1750 }
1751
26bb0981 1752 return true;
51c6cf66
AK		 1753}
1754
2d49ec72
GN		 1755static unsigned long segment_base(u16 selector)
1756{
89cbc767 1757 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1758 struct desc_struct *d;
1759 unsigned long table_base;
1760 unsigned long v;
1761
1762 if (!(selector & ~3))
1763 return 0;
1764
d359192f 1765 table_base = gdt->address;
2d49ec72
GN		 1766
1767 if (selector & 4) { /* from ldt */
1768 u16 ldt_selector = kvm_read_ldt();
1769
1770 if (!(ldt_selector & ~3))
1771 return 0;
1772
1773 table_base = segment_base(ldt_selector);
1774 }
1775 d = (struct desc_struct *)(table_base + (selector & ~7));
1776 v = get_desc_base(d);
1777#ifdef CONFIG_X86_64
1778 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1779 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1780#endif
1781 return v;
1782}
1783
1784static inline unsigned long kvm_read_tr_base(void)
1785{
1786 u16 tr;
1787 asm("str %0" : "=g"(tr));
1788 return segment_base(tr);
1789}
1790
04d2cc77 1791static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1792{
04d2cc77 1793 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1794 int i;
04d2cc77 1795
a2fa3e9f 1796 if (vmx->host_state.loaded)
33ed6329
AK		 1797 return;
1798
a2fa3e9f 1799 vmx->host_state.loaded = 1;
33ed6329
AK		 1800 /*
1801 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1802 * allow segment selectors with cpl > 0 or ti == 1.
1803 */
d6e88aec 1804 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1805 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1806 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1807 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1808 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1809 vmx->host_state.fs_reload_needed = 0;
1810 } else {
33ed6329 1811 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1812 vmx->host_state.fs_reload_needed = 1;
33ed6329 1813 }
9581d442 1814 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1815 if (!(vmx->host_state.gs_sel & 7))
1816 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1817 else {
1818 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1819 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1820 }
1821
b2da15ac
AK		 1822#ifdef CONFIG_X86_64
1823 savesegment(ds, vmx->host_state.ds_sel);
1824 savesegment(es, vmx->host_state.es_sel);
1825#endif
1826
33ed6329
AK		 1827#ifdef CONFIG_X86_64
1828 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1829 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1830#else
a2fa3e9f
GH		 1831 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1832 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1833#endif
707c0874
AK		 1834
1835#ifdef CONFIG_X86_64
c8770e7b
AK		 1836 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1837 if (is_long_mode(&vmx->vcpu))
44ea2b17 1838 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1839#endif
da8999d3
LJ		 1840 if (boot_cpu_has(X86_FEATURE_MPX))
1841 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1842 for (i = 0; i < vmx->save_nmsrs; ++i)
1843 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1844 vmx->guest_msrs[i].data,
1845 vmx->guest_msrs[i].mask);
33ed6329
AK		 1846}
1847
a9b21b62 1848static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1849{
a2fa3e9f 1850 if (!vmx->host_state.loaded)
33ed6329
AK		 1851 return;
1852
e1beb1d3 1853 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1854 vmx->host_state.loaded = 0;
c8770e7b
AK		 1855#ifdef CONFIG_X86_64
1856 if (is_long_mode(&vmx->vcpu))
1857 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1858#endif
152d3f2f 1859 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1860 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1861#ifdef CONFIG_X86_64
9581d442 1862 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1863#else
1864 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1865#endif
33ed6329 1866 }
0a77fe4c
AK		 1867 if (vmx->host_state.fs_reload_needed)
1868 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1869#ifdef CONFIG_X86_64
1870 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1871 loadsegment(ds, vmx->host_state.ds_sel);
1872 loadsegment(es, vmx->host_state.es_sel);
1873 }
b2da15ac 1874#endif
152d3f2f 1875 reload_tss();
44ea2b17 1876#ifdef CONFIG_X86_64
c8770e7b 1877 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1878#endif
da8999d3
LJ		 1879 if (vmx->host_state.msr_host_bndcfgs)
1880 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1881 /*
1882 * If the FPU is not active (through the host task or
1883 * the guest vcpu), then restore the cr0.TS bit.
1884 */
3c6dffa9 1885 if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
b1a74bf8 1886 stts();
89cbc767 1887 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1888}
1889
a9b21b62
AK		 1890static void vmx_load_host_state(struct vcpu_vmx *vmx)
1891{
1892 preempt_disable();
1893 __vmx_load_host_state(vmx);
1894 preempt_enable();
1895}
1896
6aa8b732
AK		 1897/*
1898 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1899 * vcpu mutex is already taken.
1900 */
15ad7146 1901static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1902{
a2fa3e9f 1903 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1904 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1905
4610c9cc
DX		 1906 if (!vmm_exclusive)
1907 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1908 else if (vmx->loaded_vmcs->cpu != cpu)
1909 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1910
d462b819
NHE		 1911 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1912 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1913 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1914 }
1915
d462b819 1916 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 1917 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 1918 unsigned long sysenter_esp;
1919
a8eeb04a 1920 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1921 local_irq_disable();
8f536b76 1922 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1923
1924 /*
1925 * Read loaded_vmcs->cpu should be before fetching
1926 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1927 * See the comments in __loaded_vmcs_clear().
1928 */
1929 smp_rmb();
1930
d462b819
NHE		 1931 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1932 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1933 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1934 local_irq_enable();
1935
6aa8b732
AK		 1936 /*
1937 * Linux uses per-cpu TSS and GDT, so set these when switching
1938 * processors.
1939 */
d6e88aec 1940 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1941 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1942
1943 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1944 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1945 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1946 }
6aa8b732
AK		 1947}
1948
1949static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1950{
a9b21b62 1951 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1952 if (!vmm_exclusive) {
d462b819
NHE		 1953 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1954 vcpu->cpu = -1;
4610c9cc
DX		 1955 kvm_cpu_vmxoff();
1956 }
6aa8b732
AK		 1957}
1958
5fd86fcf
AK		 1959static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1960{
81231c69
AK		 1961 ulong cr0;
1962
5fd86fcf
AK		 1963 if (vcpu->fpu_active)
1964 return;
1965 vcpu->fpu_active = 1;
81231c69
AK		 1966 cr0 = vmcs_readl(GUEST_CR0);
1967 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1968 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1969 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1970 update_exception_bitmap(vcpu);
edcafe3c 1971 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1972 if (is_guest_mode(vcpu))
1973 vcpu->arch.cr0_guest_owned_bits &=
1974 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1975 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1976}
1977
edcafe3c
AK		 1978static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1979
fe3ef05c
NHE		 1980/*
1981 * Return the cr0 value that a nested guest would read. This is a combination
1982 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1983 * its hypervisor (cr0_read_shadow).
1984 */
1985static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1986{
1987 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1988 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1989}
1990static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1991{
1992 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1993 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1994}
1995
5fd86fcf
AK		 1996static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1997{
36cf24e0
NHE		 1998 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1999 * set this *before* calling this function.
2000 */
edcafe3c 2001 vmx_decache_cr0_guest_bits(vcpu);
81231c69 2002 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 2003 update_exception_bitmap(vcpu);
edcafe3c
AK		 2004 vcpu->arch.cr0_guest_owned_bits = 0;
2005 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 2006 if (is_guest_mode(vcpu)) {
2007 /*
2008 * L1's specified read shadow might not contain the TS bit,
2009 * so now that we turned on shadowing of this bit, we need to
2010 * set this bit of the shadow. Like in nested_vmx_run we need
2011 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2012 * up-to-date here because we just decached cr0.TS (and we'll
2013 * only update vmcs12->guest_cr0 on nested exit).
2014 */
2015 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2016 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2017 (vcpu->arch.cr0 & X86_CR0_TS);
2018 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2019 } else
2020 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 2021}
2022
6aa8b732
AK		 2023static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2024{
78ac8b47 2025 unsigned long rflags, save_rflags;
345dcaa8 2026
6de12732
AK		 2027 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2028 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2029 rflags = vmcs_readl(GUEST_RFLAGS);
2030 if (to_vmx(vcpu)->rmode.vm86_active) {
2031 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2032 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2033 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2034 }
2035 to_vmx(vcpu)->rflags = rflags;
78ac8b47 2036 }
6de12732 2037 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 2038}
2039
2040static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2041{
6de12732
AK		 2042 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2043 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 2044 if (to_vmx(vcpu)->rmode.vm86_active) {
2045 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 2046 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 2047 }
6aa8b732
AK		 2048 vmcs_writel(GUEST_RFLAGS, rflags);
2049}
2050
37ccdcbe 2051static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 2052{
2053 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2054 int ret = 0;
2055
2056 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2057 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2058 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2059 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2060
37ccdcbe 2061 return ret;
2809f5d2
GC		 2062}
2063
2064static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2065{
2066 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2067 u32 interruptibility = interruptibility_old;
2068
2069 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2070
48005f64 2071 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2072 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2073 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 2074 interruptibility |= GUEST_INTR_STATE_STI;
2075
2076 if ((interruptibility != interruptibility_old))
2077 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2078}
2079
6aa8b732
AK		 2080static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2081{
2082 unsigned long rip;
6aa8b732 2083
5fdbf976 2084 rip = kvm_rip_read(vcpu);
6aa8b732 2085 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2086 kvm_rip_write(vcpu, rip);
6aa8b732 2087
2809f5d2
GC		 2088 /* skipping an emulated instruction also counts */
2089 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2090}
2091
0b6ac343
NHE		 2092/*
2093 * KVM wants to inject page-faults which it got to the guest. This function
2094 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2095 */
e011c663 2096static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2097{
2098 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2099
e011c663 2100 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2101 return 0;
2102
533558bc
JK		 2103 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2104 vmcs_read32(VM_EXIT_INTR_INFO),
2105 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2106 return 1;
2107}
2108
298101da 2109static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2110 bool has_error_code, u32 error_code,
2111 bool reinject)
298101da 2112{
77ab6db0 2113 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2114 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2115
e011c663
GN		 2116 if (!reinject && is_guest_mode(vcpu) &&
2117 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2118 return;
2119
8ab2d2e2 2120 if (has_error_code) {
77ab6db0 2121 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2122 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2123 }
77ab6db0 2124
7ffd92c5 2125 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2126 int inc_eip = 0;
2127 if (kvm_exception_is_soft(nr))
2128 inc_eip = vcpu->arch.event_exit_inst_len;
2129 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2130 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2131 return;
2132 }
2133
66fd3f7f
GN		 2134 if (kvm_exception_is_soft(nr)) {
2135 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2136 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2137 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2138 } else
2139 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2140
2141 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2142}
2143
4e47c7a6
SY		 2144static bool vmx_rdtscp_supported(void)
2145{
2146 return cpu_has_vmx_rdtscp();
2147}
2148
ad756a16
MJ		 2149static bool vmx_invpcid_supported(void)
2150{
2151 return cpu_has_vmx_invpcid() && enable_ept;
2152}
2153
a75beee6
ED		 2154/*
2155 * Swap MSR entry in host/guest MSR entry array.
2156 */
8b9cf98c 2157static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2158{
26bb0981 2159 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2160
2161 tmp = vmx->guest_msrs[to];
2162 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2163 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2164}
2165
8d14695f
YZ		 2166static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2167{
2168 unsigned long *msr_bitmap;
2169
670125bd
WV		 2170 if (is_guest_mode(vcpu))
2171 msr_bitmap = vmx_msr_bitmap_nested;
8a9781f7 2172 else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
8d14695f
YZ		 2173 if (is_long_mode(vcpu))
2174 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2175 else
2176 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2177 } else {
2178 if (is_long_mode(vcpu))
2179 msr_bitmap = vmx_msr_bitmap_longmode;
2180 else
2181 msr_bitmap = vmx_msr_bitmap_legacy;
2182 }
2183
2184 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2185}
2186
e38aea3e
AK		 2187/*
2188 * Set up the vmcs to automatically save and restore system
2189 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2190 * mode, as fiddling with msrs is very expensive.
2191 */
8b9cf98c 2192static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2193{
26bb0981 2194 int save_nmsrs, index;
e38aea3e 2195
a75beee6
ED		 2196 save_nmsrs = 0;
2197#ifdef CONFIG_X86_64
8b9cf98c 2198 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2199 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2200 if (index >= 0)
8b9cf98c
RR		 2201 move_msr_up(vmx, index, save_nmsrs++);
2202 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2203 if (index >= 0)
8b9cf98c
RR		 2204 move_msr_up(vmx, index, save_nmsrs++);
2205 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2206 if (index >= 0)
8b9cf98c 2207 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6 2208 index = __find_msr_index(vmx, MSR_TSC_AUX);
1cea0ce6 2209 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
4e47c7a6 2210 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2211 /*
8c06585d 2212 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2213 * if efer.sce is enabled.
2214 */
8c06585d 2215 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2216 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2217 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2218 }
2219#endif
92c0d900
AK		 2220 index = __find_msr_index(vmx, MSR_EFER);
2221 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2222 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2223
26bb0981 2224 vmx->save_nmsrs = save_nmsrs;
5897297b 2225
8d14695f
YZ		 2226 if (cpu_has_vmx_msr_bitmap())
2227 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2228}
2229
6aa8b732
AK		 2230/*
2231 * reads and returns guest's timestamp counter "register"
2232 * guest_tsc = host_tsc + tsc_offset -- 21.3
2233 */
2234static u64 guest_read_tsc(void)
2235{
2236 u64 host_tsc, tsc_offset;
2237
4ea1636b 2238 host_tsc = rdtsc();
6aa8b732
AK		 2239 tsc_offset = vmcs_read64(TSC_OFFSET);
2240 return host_tsc + tsc_offset;
2241}
2242
d5c1785d
NHE		 2243/*
2244 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2245 * counter, even if a nested guest (L2) is currently running.
2246 */
48d89b92 2247static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2248{
886b470c 2249 u64 tsc_offset;
d5c1785d 2250
d5c1785d
NHE		 2251 tsc_offset = is_guest_mode(vcpu) ?
2252 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2253 vmcs_read64(TSC_OFFSET);
2254 return host_tsc + tsc_offset;
2255}
2256
4051b188 2257/*
cc578287
ZA		 2258 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2259 * software catchup for faster rates on slower CPUs.
4051b188 2260 */
cc578287 2261static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2262{
cc578287
ZA		 2263 if (!scale)
2264 return;
2265
2266 if (user_tsc_khz > tsc_khz) {
2267 vcpu->arch.tsc_catchup = 1;
2268 vcpu->arch.tsc_always_catchup = 1;
2269 } else
2270 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2271}
2272
ba904635
WA		 2273static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2274{
2275 return vmcs_read64(TSC_OFFSET);
2276}
2277
6aa8b732 2278/*
99e3e30a 2279 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2280 */
99e3e30a 2281static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2282{
27fc51b2 2283 if (is_guest_mode(vcpu)) {
7991825b 2284 /*
27fc51b2
NHE		 2285 * We're here if L1 chose not to trap WRMSR to TSC. According
2286 * to the spec, this should set L1's TSC; The offset that L1
2287 * set for L2 remains unchanged, and still needs to be added
2288 * to the newly set TSC to get L2's TSC.
7991825b 2289 */
27fc51b2
NHE		 2290 struct vmcs12 *vmcs12;
2291 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2292 /* recalculate vmcs02.TSC_OFFSET: */
2293 vmcs12 = get_vmcs12(vcpu);
2294 vmcs_write64(TSC_OFFSET, offset +
2295 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2296 vmcs12->tsc_offset : 0));
2297 } else {
489223ed
YY		 2298 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2299 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2300 vmcs_write64(TSC_OFFSET, offset);
2301 }
6aa8b732
AK		 2302}
2303
f1e2b260 2304static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2305{
2306 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2307
e48672fa 2308 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2309 if (is_guest_mode(vcpu)) {
2310 /* Even when running L2, the adjustment needs to apply to L1 */
2311 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2312 } else
2313 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2314 offset + adjustment);
e48672fa
ZA		 2315}
2316
857e4099
JR		 2317static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2318{
4ea1636b 2319 return target_tsc - rdtsc();
857e4099
JR		 2320}
2321
801d3424
NHE		 2322static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2323{
2324 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2325 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2326}
2327
2328/*
2329 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2330 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2331 * all guests if the "nested" module option is off, and can also be disabled
2332 * for a single guest by disabling its VMX cpuid bit.
2333 */
2334static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2335{
2336 return nested && guest_cpuid_has_vmx(vcpu);
2337}
2338
b87a51ae
NHE		 2339/*
2340 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2341 * returned for the various VMX controls MSRs when nested VMX is enabled.
2342 * The same values should also be used to verify that vmcs12 control fields are
2343 * valid during nested entry from L1 to L2.
2344 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2345 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2346 * bit in the high half is on if the corresponding bit in the control field
2347 * may be on. See also vmx_control_verify().
b87a51ae 2348 */
b9c237bb 2349static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
b87a51ae
NHE		 2350{
2351 /*
2352 * Note that as a general rule, the high half of the MSRs (bits in
2353 * the control fields which may be 1) should be initialized by the
2354 * intersection of the underlying hardware's MSR (i.e., features which
2355 * can be supported) and the list of features we want to expose -
2356 * because they are known to be properly supported in our code.
2357 * Also, usually, the low half of the MSRs (bits which must be 1) can
2358 * be set to 0, meaning that L1 may turn off any of these bits. The
2359 * reason is that if one of these bits is necessary, it will appear
2360 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2361 * fields of vmcs01 and vmcs02, will turn these bits off - and
2362 * nested_vmx_exit_handled() will not pass related exits to L1.
2363 * These rules have exceptions below.
2364 */
2365
2366 /* pin-based controls */
eabeaacc 2367 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
b9c237bb
WV		 2368 vmx->nested.nested_vmx_pinbased_ctls_low,
2369 vmx->nested.nested_vmx_pinbased_ctls_high);
2370 vmx->nested.nested_vmx_pinbased_ctls_low |=
2371 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2372 vmx->nested.nested_vmx_pinbased_ctls_high &=
2373 PIN_BASED_EXT_INTR_MASK |
2374 PIN_BASED_NMI_EXITING |
2375 PIN_BASED_VIRTUAL_NMIS;
2376 vmx->nested.nested_vmx_pinbased_ctls_high |=
2377 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2378 PIN_BASED_VMX_PREEMPTION_TIMER;
35754c98 2379 if (vmx_cpu_uses_apicv(&vmx->vcpu))
705699a1
WV		 2380 vmx->nested.nested_vmx_pinbased_ctls_high |=
2381 PIN_BASED_POSTED_INTR;
b87a51ae 2382
3dbcd8da 2383 /* exit controls */
c0dfee58 2384 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
b9c237bb
WV		 2385 vmx->nested.nested_vmx_exit_ctls_low,
2386 vmx->nested.nested_vmx_exit_ctls_high);
2387 vmx->nested.nested_vmx_exit_ctls_low =
2388 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2389
b9c237bb 2390 vmx->nested.nested_vmx_exit_ctls_high &=
b87a51ae 2391#ifdef CONFIG_X86_64
c0dfee58 2392 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2393#endif
f4124500 2394 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
b9c237bb
WV		 2395 vmx->nested.nested_vmx_exit_ctls_high |=
2396 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
f4124500 2397 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2398 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2399
36be0b9d 2400 if (vmx_mpx_supported())
b9c237bb 2401 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2402
2996fca0 2403 /* We support free control of debug control saving. */
b9c237bb
WV		 2404 vmx->nested.nested_vmx_true_exit_ctls_low =
2405 vmx->nested.nested_vmx_exit_ctls_low &
2996fca0
JK		 2406 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2407
b87a51ae
NHE		 2408 /* entry controls */
2409 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
b9c237bb
WV		 2410 vmx->nested.nested_vmx_entry_ctls_low,
2411 vmx->nested.nested_vmx_entry_ctls_high);
2412 vmx->nested.nested_vmx_entry_ctls_low =
2413 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2414 vmx->nested.nested_vmx_entry_ctls_high &=
57435349
JK		 2415#ifdef CONFIG_X86_64
2416 VM_ENTRY_IA32E_MODE |
2417#endif
2418 VM_ENTRY_LOAD_IA32_PAT;
b9c237bb
WV		 2419 vmx->nested.nested_vmx_entry_ctls_high |=
2420 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
36be0b9d 2421 if (vmx_mpx_supported())
b9c237bb 2422 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2423
2996fca0 2424 /* We support free control of debug control loading. */
b9c237bb
WV		 2425 vmx->nested.nested_vmx_true_entry_ctls_low =
2426 vmx->nested.nested_vmx_entry_ctls_low &
2996fca0
JK		 2427 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2428
b87a51ae
NHE		 2429 /* cpu-based controls */
2430 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
b9c237bb
WV		 2431 vmx->nested.nested_vmx_procbased_ctls_low,
2432 vmx->nested.nested_vmx_procbased_ctls_high);
2433 vmx->nested.nested_vmx_procbased_ctls_low =
2434 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2435 vmx->nested.nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2436 CPU_BASED_VIRTUAL_INTR_PENDING |
2437 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2438 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2439 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2440 CPU_BASED_CR3_STORE_EXITING |
2441#ifdef CONFIG_X86_64
2442 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2443#endif
2444 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
5f3d45e7
MD		 2445 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2446 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2447 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2448 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
b87a51ae
NHE		 2449 /*
2450 * We can allow some features even when not supported by the
2451 * hardware. For example, L1 can specify an MSR bitmap - and we
2452 * can use it to avoid exits to L1 - even when L0 runs L2
2453 * without MSR bitmaps.
2454 */
b9c237bb
WV		 2455 vmx->nested.nested_vmx_procbased_ctls_high |=
2456 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
560b7ee1 2457 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2458
3dcdf3ec 2459 /* We support free control of CR3 access interception. */
b9c237bb
WV		 2460 vmx->nested.nested_vmx_true_procbased_ctls_low =
2461 vmx->nested.nested_vmx_procbased_ctls_low &
3dcdf3ec
JK		 2462 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2463
b87a51ae
NHE		 2464 /* secondary cpu-based controls */
2465 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
b9c237bb
WV		 2466 vmx->nested.nested_vmx_secondary_ctls_low,
2467 vmx->nested.nested_vmx_secondary_ctls_high);
2468 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2469 vmx->nested.nested_vmx_secondary_ctls_high &=
d6851fbe 2470 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 2471 SECONDARY_EXEC_RDTSCP |
f2b93280 2472 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
82f0dd4b 2473 SECONDARY_EXEC_APIC_REGISTER_VIRT |
608406e2 2474 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
81dc01f7 2475 SECONDARY_EXEC_WBINVD_EXITING |
8b3e34e4
XG		 2476 SECONDARY_EXEC_XSAVES |
2477 SECONDARY_EXEC_PCOMMIT;
c18911a2 2478
afa61f75
NHE		 2479 if (enable_ept) {
2480 /* nested EPT: emulate EPT also to L1 */
b9c237bb 2481 vmx->nested.nested_vmx_secondary_ctls_high |=
0790ec17 2482 SECONDARY_EXEC_ENABLE_EPT;
b9c237bb 2483 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2484 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2485 VMX_EPT_INVEPT_BIT;
b9c237bb 2486 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
afa61f75 2487 /*
4b855078
BD		 2488 * For nested guests, we don't do anything specific
2489 * for single context invalidation. Hence, only advertise
2490 * support for global context invalidation.
afa61f75 2491 */
b9c237bb 2492 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75 2493 } else
b9c237bb 2494 vmx->nested.nested_vmx_ept_caps = 0;
afa61f75 2495
0790ec17
RK		 2496 if (enable_unrestricted_guest)
2497 vmx->nested.nested_vmx_secondary_ctls_high |=
2498 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2499
c18911a2 2500 /* miscellaneous data */
b9c237bb
WV		 2501 rdmsr(MSR_IA32_VMX_MISC,
2502 vmx->nested.nested_vmx_misc_low,
2503 vmx->nested.nested_vmx_misc_high);
2504 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2505 vmx->nested.nested_vmx_misc_low |=
2506 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
f4124500 2507 VMX_MISC_ACTIVITY_HLT;
b9c237bb 2508 vmx->nested.nested_vmx_misc_high = 0;
b87a51ae
NHE		 2509}
2510
2511static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2512{
2513 /*
2514 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2515 */
2516 return ((control & high) | low) == control;
2517}
2518
2519static inline u64 vmx_control_msr(u32 low, u32 high)
2520{
2521 return low | ((u64)high << 32);
2522}
2523
cae50139 2524/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2525static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2526{
b9c237bb
WV		 2527 struct vcpu_vmx *vmx = to_vmx(vcpu);
2528
b87a51ae 2529 switch (msr_index) {
b87a51ae
NHE		 2530 case MSR_IA32_VMX_BASIC:
2531 /*
2532 * This MSR reports some information about VMX support. We
2533 * should return information about the VMX we emulate for the
2534 * guest, and the VMCS structure we give it - not about the
2535 * VMX support of the underlying hardware.
2536 */
3dbcd8da 2537 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2538 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2539 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2540 break;
2541 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2542 case MSR_IA32_VMX_PINBASED_CTLS:
b9c237bb
WV		 2543 *pdata = vmx_control_msr(
2544 vmx->nested.nested_vmx_pinbased_ctls_low,
2545 vmx->nested.nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2546 break;
2547 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
b9c237bb
WV		 2548 *pdata = vmx_control_msr(
2549 vmx->nested.nested_vmx_true_procbased_ctls_low,
2550 vmx->nested.nested_vmx_procbased_ctls_high);
3dcdf3ec 2551 break;
b87a51ae 2552 case MSR_IA32_VMX_PROCBASED_CTLS:
b9c237bb
WV		 2553 *pdata = vmx_control_msr(
2554 vmx->nested.nested_vmx_procbased_ctls_low,
2555 vmx->nested.nested_vmx_procbased_ctls_high);
b87a51ae
NHE		 2556 break;
2557 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
b9c237bb
WV		 2558 *pdata = vmx_control_msr(
2559 vmx->nested.nested_vmx_true_exit_ctls_low,
2560 vmx->nested.nested_vmx_exit_ctls_high);
2996fca0 2561 break;
b87a51ae 2562 case MSR_IA32_VMX_EXIT_CTLS:
b9c237bb
WV		 2563 *pdata = vmx_control_msr(
2564 vmx->nested.nested_vmx_exit_ctls_low,
2565 vmx->nested.nested_vmx_exit_ctls_high);
b87a51ae
NHE		 2566 break;
2567 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
b9c237bb
WV		 2568 *pdata = vmx_control_msr(
2569 vmx->nested.nested_vmx_true_entry_ctls_low,
2570 vmx->nested.nested_vmx_entry_ctls_high);
2996fca0 2571 break;
b87a51ae 2572 case MSR_IA32_VMX_ENTRY_CTLS:
b9c237bb
WV		 2573 *pdata = vmx_control_msr(
2574 vmx->nested.nested_vmx_entry_ctls_low,
2575 vmx->nested.nested_vmx_entry_ctls_high);
b87a51ae
NHE		 2576 break;
2577 case MSR_IA32_VMX_MISC:
b9c237bb
WV		 2578 *pdata = vmx_control_msr(
2579 vmx->nested.nested_vmx_misc_low,
2580 vmx->nested.nested_vmx_misc_high);
b87a51ae
NHE		 2581 break;
2582 /*
2583 * These MSRs specify bits which the guest must keep fixed (on or off)
2584 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2585 * We picked the standard core2 setting.
2586 */
2587#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2588#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2589 case MSR_IA32_VMX_CR0_FIXED0:
2590 *pdata = VMXON_CR0_ALWAYSON;
2591 break;
2592 case MSR_IA32_VMX_CR0_FIXED1:
2593 *pdata = -1ULL;
2594 break;
2595 case MSR_IA32_VMX_CR4_FIXED0:
2596 *pdata = VMXON_CR4_ALWAYSON;
2597 break;
2598 case MSR_IA32_VMX_CR4_FIXED1:
2599 *pdata = -1ULL;
2600 break;
2601 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2602 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2603 break;
2604 case MSR_IA32_VMX_PROCBASED_CTLS2:
b9c237bb
WV		 2605 *pdata = vmx_control_msr(
2606 vmx->nested.nested_vmx_secondary_ctls_low,
2607 vmx->nested.nested_vmx_secondary_ctls_high);
b87a51ae
NHE		 2608 break;
2609 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75 2610 /* Currently, no nested vpid support */
b9c237bb 2611 *pdata = vmx->nested.nested_vmx_ept_caps;
b87a51ae
NHE		 2612 break;
2613 default:
b87a51ae 2614 return 1;
b3897a49
NHE		 2615 }
2616
b87a51ae
NHE		 2617 return 0;
2618}
2619
6aa8b732
AK		 2620/*
2621 * Reads an msr value (of 'msr_index') into 'pdata'.
2622 * Returns 0 on success, non-0 otherwise.
2623 * Assumes vcpu_load() was already called.
2624 */
609e36d3 2625static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2626{
26bb0981 2627 struct shared_msr_entry *msr;
6aa8b732 2628
609e36d3 2629 switch (msr_info->index) {
05b3e0c2 2630#ifdef CONFIG_X86_64
6aa8b732 2631 case MSR_FS_BASE:
609e36d3 2632 msr_info->data = vmcs_readl(GUEST_FS_BASE);
6aa8b732
AK		 2633 break;
2634 case MSR_GS_BASE:
609e36d3 2635 msr_info->data = vmcs_readl(GUEST_GS_BASE);
6aa8b732 2636 break;
44ea2b17
AK		 2637 case MSR_KERNEL_GS_BASE:
2638 vmx_load_host_state(to_vmx(vcpu));
609e36d3 2639 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
44ea2b17 2640 break;
26bb0981 2641#endif
6aa8b732 2642 case MSR_EFER:
609e36d3 2643 return kvm_get_msr_common(vcpu, msr_info);
af24a4e4 2644 case MSR_IA32_TSC:
609e36d3 2645 msr_info->data = guest_read_tsc();
6aa8b732
AK		 2646 break;
2647 case MSR_IA32_SYSENTER_CS:
609e36d3 2648 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK		 2649 break;
2650 case MSR_IA32_SYSENTER_EIP:
609e36d3 2651 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2652 break;
2653 case MSR_IA32_SYSENTER_ESP:
609e36d3 2654 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2655 break;
0dd376e7 2656 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2657 if (!vmx_mpx_supported())
2658 return 1;
609e36d3 2659 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 2660 break;
cae50139
JK		 2661 case MSR_IA32_FEATURE_CONTROL:
2662 if (!nested_vmx_allowed(vcpu))
2663 return 1;
609e36d3 2664 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
cae50139
JK		 2665 break;
2666 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2667 if (!nested_vmx_allowed(vcpu))
2668 return 1;
609e36d3 2669 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
20300099
WL		 2670 case MSR_IA32_XSS:
2671 if (!vmx_xsaves_supported())
2672 return 1;
609e36d3 2673 msr_info->data = vcpu->arch.ia32_xss;
20300099 2674 break;
4e47c7a6 2675 case MSR_TSC_AUX:
1cea0ce6 2676 if (!guest_cpuid_has_rdtscp(vcpu))
4e47c7a6
SY		 2677 return 1;
2678 /* Otherwise falls through */
6aa8b732 2679 default:
609e36d3 2680 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3bab1f5d 2681 if (msr) {
609e36d3 2682 msr_info->data = msr->data;
3bab1f5d 2683 break;
6aa8b732 2684 }
609e36d3 2685 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 2686 }
2687
6aa8b732
AK		 2688 return 0;
2689}
2690
cae50139
JK		 2691static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2692
6aa8b732
AK		 2693/*
2694 * Writes msr value into into the appropriate "register".
2695 * Returns 0 on success, non-0 otherwise.
2696 * Assumes vcpu_load() was already called.
2697 */
8fe8ab46 2698static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2699{
a2fa3e9f 2700 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2701 struct shared_msr_entry *msr;
2cc51560 2702 int ret = 0;
8fe8ab46
WA		 2703 u32 msr_index = msr_info->index;
2704 u64 data = msr_info->data;
2cc51560 2705
6aa8b732 2706 switch (msr_index) {
3bab1f5d 2707 case MSR_EFER:
8fe8ab46 2708 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2709 break;
16175a79 2710#ifdef CONFIG_X86_64
6aa8b732 2711 case MSR_FS_BASE:
2fb92db1 2712 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2713 vmcs_writel(GUEST_FS_BASE, data);
2714 break;
2715 case MSR_GS_BASE:
2fb92db1 2716 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2717 vmcs_writel(GUEST_GS_BASE, data);
2718 break;
44ea2b17
AK		 2719 case MSR_KERNEL_GS_BASE:
2720 vmx_load_host_state(vmx);
2721 vmx->msr_guest_kernel_gs_base = data;
2722 break;
6aa8b732
AK		 2723#endif
2724 case MSR_IA32_SYSENTER_CS:
2725 vmcs_write32(GUEST_SYSENTER_CS, data);
2726 break;
2727 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2728 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2729 break;
2730 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2731 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2732 break;
0dd376e7 2733 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2734 if (!vmx_mpx_supported())
2735 return 1;
0dd376e7
LJ		 2736 vmcs_write64(GUEST_BNDCFGS, data);
2737 break;
af24a4e4 2738 case MSR_IA32_TSC:
8fe8ab46 2739 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2740 break;
468d472f
SY		 2741 case MSR_IA32_CR_PAT:
2742 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2743 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2744 return 1;
468d472f
SY		 2745 vmcs_write64(GUEST_IA32_PAT, data);
2746 vcpu->arch.pat = data;
2747 break;
2748 }
8fe8ab46 2749 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2750 break;
ba904635
WA		 2751 case MSR_IA32_TSC_ADJUST:
2752 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2753 break;
cae50139
JK		 2754 case MSR_IA32_FEATURE_CONTROL:
2755 if (!nested_vmx_allowed(vcpu) ||
2756 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2757 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2758 return 1;
2759 vmx->nested.msr_ia32_feature_control = data;
2760 if (msr_info->host_initiated && data == 0)
2761 vmx_leave_nested(vcpu);
2762 break;
2763 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2764 return 1; /* they are read-only */
20300099
WL		 2765 case MSR_IA32_XSS:
2766 if (!vmx_xsaves_supported())
2767 return 1;
2768 /*
2769 * The only supported bit as of Skylake is bit 8, but
2770 * it is not supported on KVM.
2771 */
2772 if (data != 0)
2773 return 1;
2774 vcpu->arch.ia32_xss = data;
2775 if (vcpu->arch.ia32_xss != host_xss)
2776 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2777 vcpu->arch.ia32_xss, host_xss);
2778 else
2779 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2780 break;
4e47c7a6 2781 case MSR_TSC_AUX:
1cea0ce6 2782 if (!guest_cpuid_has_rdtscp(vcpu))
4e47c7a6
SY		 2783 return 1;
2784 /* Check reserved bit, higher 32 bits should be zero */
2785 if ((data >> 32) != 0)
2786 return 1;
2787 /* Otherwise falls through */
6aa8b732 2788 default:
8b9cf98c 2789 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2790 if (msr) {
8b3c3104 2791 u64 old_msr_data = msr->data;
3bab1f5d 2792 msr->data = data;
2225fd56
AK		 2793 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2794 preempt_disable();
8b3c3104
AH		 2795 ret = kvm_set_shared_msr(msr->index, msr->data,
2796 msr->mask);
2225fd56 2797 preempt_enable();
8b3c3104
AH		 2798 if (ret)
2799 msr->data = old_msr_data;
2225fd56 2800 }
3bab1f5d 2801 break;
6aa8b732 2802 }
8fe8ab46 2803 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2804 }
2805
2cc51560 2806 return ret;
6aa8b732
AK		 2807}
2808
5fdbf976 2809static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2810{
5fdbf976
MT		 2811 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2812 switch (reg) {
2813 case VCPU_REGS_RSP:
2814 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2815 break;
2816 case VCPU_REGS_RIP:
2817 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2818 break;
6de4f3ad
AK		 2819 case VCPU_EXREG_PDPTR:
2820 if (enable_ept)
2821 ept_save_pdptrs(vcpu);
2822 break;
5fdbf976
MT		 2823 default:
2824 break;
2825 }
6aa8b732
AK		 2826}
2827
6aa8b732
AK		 2828static __init int cpu_has_kvm_support(void)
2829{
6210e37b 2830 return cpu_has_vmx();
6aa8b732
AK		 2831}
2832
2833static __init int vmx_disabled_by_bios(void)
2834{
2835 u64 msr;
2836
2837 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2838 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2839 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2840 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2841 && tboot_enabled())
2842 return 1;
23f3e991 2843 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2844 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2845 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2846 && !tboot_enabled()) {
2847 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2848 "activate TXT before enabling KVM\n");
cafd6659 2849 return 1;
f9335afe 2850 }
23f3e991
JC		 2851 /* launched w/o TXT and VMX disabled */
2852 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2853 && !tboot_enabled())
2854 return 1;
cafd6659
SW		 2855 }
2856
2857 return 0;
6aa8b732
AK		 2858}
2859
7725b894
DX		 2860static void kvm_cpu_vmxon(u64 addr)
2861{
2862 asm volatile (ASM_VMX_VMXON_RAX
2863 : : "a"(&addr), "m"(addr)
2864 : "memory", "cc");
2865}
2866
13a34e06 2867static int hardware_enable(void)
6aa8b732
AK		 2868{
2869 int cpu = raw_smp_processor_id();
2870 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2871 u64 old, test_bits;
6aa8b732 2872
1e02ce4c 2873 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 2874 return -EBUSY;
2875
d462b819 2876 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2877
2878 /*
2879 * Now we can enable the vmclear operation in kdump
2880 * since the loaded_vmcss_on_cpu list on this cpu
2881 * has been initialized.
2882 *
2883 * Though the cpu is not in VMX operation now, there
2884 * is no problem to enable the vmclear operation
2885 * for the loaded_vmcss_on_cpu list is empty!
2886 */
2887 crash_enable_local_vmclear(cpu);
2888
6aa8b732 2889 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2890
2891 test_bits = FEATURE_CONTROL_LOCKED;
2892 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2893 if (tboot_enabled())
2894 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2895
2896 if ((old & test_bits) != test_bits) {
6aa8b732 2897 /* enable and lock */
cafd6659
SW		 2898 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2899 }
375074cc 2900 cr4_set_bits(X86_CR4_VMXE);
10474ae8 2901
4610c9cc
DX		 2902 if (vmm_exclusive) {
2903 kvm_cpu_vmxon(phys_addr);
2904 ept_sync_global();
2905 }
10474ae8 2906
89cbc767 2907 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 2908
10474ae8 2909 return 0;
6aa8b732
AK		 2910}
2911
d462b819 2912static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2913{
2914 int cpu = raw_smp_processor_id();
d462b819 2915 struct loaded_vmcs *v, *n;
543e4243 2916
d462b819
NHE		 2917 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2918 loaded_vmcss_on_cpu_link)
2919 __loaded_vmcs_clear(v);
543e4243
AK		 2920}
2921
710ff4a8
EH		 2922
2923/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2924 * tricks.
2925 */
2926static void kvm_cpu_vmxoff(void)
6aa8b732 2927{
4ecac3fd 2928 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2929}
2930
13a34e06 2931static void hardware_disable(void)
710ff4a8 2932{
4610c9cc 2933 if (vmm_exclusive) {
d462b819 2934 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2935 kvm_cpu_vmxoff();
2936 }
375074cc 2937 cr4_clear_bits(X86_CR4_VMXE);
710ff4a8
EH		 2938}
2939
1c3d14fe 2940static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2941 u32 msr, u32 *result)
1c3d14fe
YS		 2942{
2943 u32 vmx_msr_low, vmx_msr_high;
2944 u32 ctl = ctl_min | ctl_opt;
2945
2946 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2947
2948 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2949 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2950
2951 /* Ensure minimum (required) set of control bits are supported. */
2952 if (ctl_min & ~ctl)
002c7f7c 2953 return -EIO;
1c3d14fe
YS		 2954
2955 *result = ctl;
2956 return 0;
2957}
2958
110312c8
AK		 2959static __init bool allow_1_setting(u32 msr, u32 ctl)
2960{
2961 u32 vmx_msr_low, vmx_msr_high;
2962
2963 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2964 return vmx_msr_high & ctl;
2965}
2966
002c7f7c 2967static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2968{
2969 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2970 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2971 u32 _pin_based_exec_control = 0;
2972 u32 _cpu_based_exec_control = 0;
f78e0e2e 2973 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2974 u32 _vmexit_control = 0;
2975 u32 _vmentry_control = 0;
2976
10166744 2977 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2978#ifdef CONFIG_X86_64
2979 CPU_BASED_CR8_LOAD_EXITING |
2980 CPU_BASED_CR8_STORE_EXITING |
2981#endif
d56f546d
SY		 2982 CPU_BASED_CR3_LOAD_EXITING |
2983 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2984 CPU_BASED_USE_IO_BITMAPS |
2985 CPU_BASED_MOV_DR_EXITING |
a7052897 2986 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2987 CPU_BASED_MWAIT_EXITING |
2988 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2989 CPU_BASED_INVLPG_EXITING |
2990 CPU_BASED_RDPMC_EXITING;
443381a8 2991
f78e0e2e 2992 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2993 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2994 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2995 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2996 &_cpu_based_exec_control) < 0)
002c7f7c 2997 return -EIO;
6e5d865c
YS		 2998#ifdef CONFIG_X86_64
2999 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3000 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3001 ~CPU_BASED_CR8_STORE_EXITING;
3002#endif
f78e0e2e 3003 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 3004 min2 = 0;
3005 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 3006 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 3007 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 3008 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 3009 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 3010 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 3011 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 3012 SECONDARY_EXEC_RDTSCP |
83d4c286 3013 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 3014 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 3015 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 3016 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 3017 SECONDARY_EXEC_XSAVES |
8b3e34e4
XG		 3018 SECONDARY_EXEC_ENABLE_PML |
3019 SECONDARY_EXEC_PCOMMIT;
d56f546d
SY		 3020 if (adjust_vmx_controls(min2, opt2,
3021 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 3022 &_cpu_based_2nd_exec_control) < 0)
3023 return -EIO;
3024 }
3025#ifndef CONFIG_X86_64
3026 if (!(_cpu_based_2nd_exec_control &
3027 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3028 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3029#endif
83d4c286
YZ		 3030
3031 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3032 _cpu_based_2nd_exec_control &= ~(
8d14695f 3033 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 3034 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3035 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 3036
d56f546d 3037 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 3038 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3039 enabled */
5fff7d27
GN		 3040 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3041 CPU_BASED_CR3_STORE_EXITING |
3042 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 3043 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3044 vmx_capability.ept, vmx_capability.vpid);
3045 }
1c3d14fe 3046
81908bf4 3047 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 3048#ifdef CONFIG_X86_64
3049 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3050#endif
a547c6db 3051 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 3052 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 3053 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3054 &_vmexit_control) < 0)
002c7f7c 3055 return -EIO;
1c3d14fe 3056
01e439be
YZ		 3057 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3058 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3059 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3060 &_pin_based_exec_control) < 0)
3061 return -EIO;
3062
3063 if (!(_cpu_based_2nd_exec_control &
3064 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3065 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3066 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3067
c845f9c6 3068 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 3069 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 3070 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3071 &_vmentry_control) < 0)
002c7f7c 3072 return -EIO;
6aa8b732 3073
c68876fd 3074 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 3075
3076 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3077 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3078 return -EIO;
1c3d14fe
YS		 3079
3080#ifdef CONFIG_X86_64
3081 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3082 if (vmx_msr_high & (1u<<16))
002c7f7c 3083 return -EIO;
1c3d14fe
YS		 3084#endif
3085
3086 /* Require Write-Back (WB) memory type for VMCS accesses. */
3087 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3088 return -EIO;
1c3d14fe 3089
002c7f7c
YS		 3090 vmcs_conf->size = vmx_msr_high & 0x1fff;
3091 vmcs_conf->order = get_order(vmcs_config.size);
3092 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3093
002c7f7c
YS		 3094 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3095 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3096 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 3097 vmcs_conf->vmexit_ctrl = _vmexit_control;
3098 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3099
110312c8
AK		 3100 cpu_has_load_ia32_efer =
3101 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3102 VM_ENTRY_LOAD_IA32_EFER)
3103 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3104 VM_EXIT_LOAD_IA32_EFER);
3105
8bf00a52
GN		 3106 cpu_has_load_perf_global_ctrl =
3107 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3108 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3109 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3110 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3111
3112 /*
3113 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3114 * but due to arrata below it can't be used. Workaround is to use
3115 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3116 *
3117 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3118 *
3119 * AAK155 (model 26)
3120 * AAP115 (model 30)
3121 * AAT100 (model 37)
3122 * BC86,AAY89,BD102 (model 44)
3123 * BA97 (model 46)
3124 *
3125 */
3126 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3127 switch (boot_cpu_data.x86_model) {
3128 case 26:
3129 case 30:
3130 case 37:
3131 case 44:
3132 case 46:
3133 cpu_has_load_perf_global_ctrl = false;
3134 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3135 "does not work properly. Using workaround\n");
3136 break;
3137 default:
3138 break;
3139 }
3140 }
3141
20300099
WL		 3142 if (cpu_has_xsaves)
3143 rdmsrl(MSR_IA32_XSS, host_xss);
3144
1c3d14fe 3145 return 0;
c68876fd 3146}
6aa8b732
AK		 3147
3148static struct vmcs *alloc_vmcs_cpu(int cpu)
3149{
3150 int node = cpu_to_node(cpu);
3151 struct page *pages;
3152 struct vmcs *vmcs;
3153
96db800f 3154 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3155 if (!pages)
3156 return NULL;
3157 vmcs = page_address(pages);
1c3d14fe
YS		 3158 memset(vmcs, 0, vmcs_config.size);
3159 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3160 return vmcs;
3161}
3162
3163static struct vmcs *alloc_vmcs(void)
3164{
d3b2c338 3165 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3166}
3167
3168static void free_vmcs(struct vmcs *vmcs)
3169{
1c3d14fe 3170 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3171}
3172
d462b819
NHE		 3173/*
3174 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3175 */
3176static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3177{
3178 if (!loaded_vmcs->vmcs)
3179 return;
3180 loaded_vmcs_clear(loaded_vmcs);
3181 free_vmcs(loaded_vmcs->vmcs);
3182 loaded_vmcs->vmcs = NULL;
3183}
3184
39959588 3185static void free_kvm_area(void)
6aa8b732
AK		 3186{
3187 int cpu;
3188
3230bb47 3189 for_each_possible_cpu(cpu) {
6aa8b732 3190 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3191 per_cpu(vmxarea, cpu) = NULL;
3192 }
6aa8b732
AK		 3193}
3194
fe2b201b
BD		 3195static void init_vmcs_shadow_fields(void)
3196{
3197 int i, j;
3198
3199 /* No checks for read only fields yet */
3200
3201 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3202 switch (shadow_read_write_fields[i]) {
3203 case GUEST_BNDCFGS:
3204 if (!vmx_mpx_supported())
3205 continue;
3206 break;
3207 default:
3208 break;
3209 }
3210
3211 if (j < i)
3212 shadow_read_write_fields[j] =
3213 shadow_read_write_fields[i];
3214 j++;
3215 }
3216 max_shadow_read_write_fields = j;
3217
3218 /* shadowed fields guest access without vmexit */
3219 for (i = 0; i < max_shadow_read_write_fields; i++) {
3220 clear_bit(shadow_read_write_fields[i],
3221 vmx_vmwrite_bitmap);
3222 clear_bit(shadow_read_write_fields[i],
3223 vmx_vmread_bitmap);
3224 }
3225 for (i = 0; i < max_shadow_read_only_fields; i++)
3226 clear_bit(shadow_read_only_fields[i],
3227 vmx_vmread_bitmap);
3228}
3229
6aa8b732
AK		 3230static __init int alloc_kvm_area(void)
3231{
3232 int cpu;
3233
3230bb47 3234 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3235 struct vmcs *vmcs;
3236
3237 vmcs = alloc_vmcs_cpu(cpu);
3238 if (!vmcs) {
3239 free_kvm_area();
3240 return -ENOMEM;
3241 }
3242
3243 per_cpu(vmxarea, cpu) = vmcs;
3244 }
3245 return 0;
3246}
3247
14168786
GN		 3248static bool emulation_required(struct kvm_vcpu *vcpu)
3249{
3250 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3251}
3252
91b0aa2c 3253static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3254 struct kvm_segment *save)
6aa8b732 3255{
d99e4152
GN		 3256 if (!emulate_invalid_guest_state) {
3257 /*
3258 * CS and SS RPL should be equal during guest entry according
3259 * to VMX spec, but in reality it is not always so. Since vcpu
3260 * is in the middle of the transition from real mode to
3261 * protected mode it is safe to assume that RPL 0 is a good
3262 * default value.
3263 */
3264 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA		 3265 save->selector &= ~SEGMENT_RPL_MASK;
3266 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 3267 save->s = 1;
6aa8b732 3268 }
d99e4152 3269 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3270}
3271
3272static void enter_pmode(struct kvm_vcpu *vcpu)
3273{
3274 unsigned long flags;
a89a8fb9 3275 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3276
d99e4152
GN		 3277 /*
3278 * Update real mode segment cache. It may be not up-to-date if sement
3279 * register was written while vcpu was in a guest mode.
3280 */
3281 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3282 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3283 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3284 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3285 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3286 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3287
7ffd92c5 3288 vmx->rmode.vm86_active = 0;
6aa8b732 3289
2fb92db1
AK		 3290 vmx_segment_cache_clear(vmx);
3291
f5f7b2fe 3292 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3293
3294 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3295 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3296 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3297 vmcs_writel(GUEST_RFLAGS, flags);
3298
66aee91a
RR		 3299 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3300 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3301
3302 update_exception_bitmap(vcpu);
3303
91b0aa2c
GN		 3304 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3305 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3306 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3307 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3308 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3309 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3310}
3311
f5f7b2fe 3312static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3313{
772e0318 3314 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3315 struct kvm_segment var = *save;
3316
3317 var.dpl = 0x3;
3318 if (seg == VCPU_SREG_CS)
3319 var.type = 0x3;
3320
3321 if (!emulate_invalid_guest_state) {
3322 var.selector = var.base >> 4;
3323 var.base = var.base & 0xffff0;
3324 var.limit = 0xffff;
3325 var.g = 0;
3326 var.db = 0;
3327 var.present = 1;
3328 var.s = 1;
3329 var.l = 0;
3330 var.unusable = 0;
3331 var.type = 0x3;
3332 var.avl = 0;
3333 if (save->base & 0xf)
3334 printk_once(KERN_WARNING "kvm: segment base is not "
3335 "paragraph aligned when entering "
3336 "protected mode (seg=%d)", seg);
3337 }
6aa8b732 3338
d99e4152
GN		 3339 vmcs_write16(sf->selector, var.selector);
3340 vmcs_write32(sf->base, var.base);
3341 vmcs_write32(sf->limit, var.limit);
3342 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3343}
3344
3345static void enter_rmode(struct kvm_vcpu *vcpu)
3346{
3347 unsigned long flags;
a89a8fb9 3348 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3349
f5f7b2fe
AK		 3350 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3351 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3352 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3353 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3354 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3355 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3356 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3357
7ffd92c5 3358 vmx->rmode.vm86_active = 1;
6aa8b732 3359
776e58ea
GN		 3360 /*
3361 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3362 * vcpu. Warn the user that an update is overdue.
776e58ea 3363 */
4918c6ca 3364 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3365 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3366 "called before entering vcpu\n");
776e58ea 3367
2fb92db1
AK		 3368 vmx_segment_cache_clear(vmx);
3369
4918c6ca 3370 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3371 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3372 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3373
3374 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3375 vmx->rmode.save_rflags = flags;
6aa8b732 3376
053de044 3377 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3378
3379 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3380 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3381 update_exception_bitmap(vcpu);
3382
d99e4152
GN		 3383 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3384 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3385 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3386 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3387 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3388 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3389
8668a3c4 3390 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3391}
3392
401d10de
AS		 3393static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3394{
3395 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3396 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3397
3398 if (!msr)
3399 return;
401d10de 3400
44ea2b17
AK		 3401 /*
3402 * Force kernel_gs_base reloading before EFER changes, as control
3403 * of this msr depends on is_long_mode().
3404 */
3405 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3406 vcpu->arch.efer = efer;
401d10de 3407 if (efer & EFER_LMA) {
2961e876 3408 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3409 msr->data = efer;
3410 } else {
2961e876 3411 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3412
3413 msr->data = efer & ~EFER_LME;
3414 }
3415 setup_msrs(vmx);
3416}
3417
05b3e0c2 3418#ifdef CONFIG_X86_64
6aa8b732
AK		 3419
3420static void enter_lmode(struct kvm_vcpu *vcpu)
3421{
3422 u32 guest_tr_ar;
3423
2fb92db1
AK		 3424 vmx_segment_cache_clear(to_vmx(vcpu));
3425
6aa8b732 3426 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 3427 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3428 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3429 __func__);
6aa8b732 3430 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL		 3431 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3432 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 3433 }
da38f438 3434 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3435}
3436
3437static void exit_lmode(struct kvm_vcpu *vcpu)
3438{
2961e876 3439 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3440 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3441}
3442
3443#endif
3444
2384d2b3
SY		 3445static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3446{
b9d762fa 3447 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3448 if (enable_ept) {
3449 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3450 return;
4e1096d2 3451 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3452 }
2384d2b3
SY		 3453}
3454
e8467fda
AK		 3455static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3456{
3457 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3458
3459 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3460 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3461}
3462
aff48baa
AK		 3463static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3464{
3465 if (enable_ept && is_paging(vcpu))
3466 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3467 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3468}
3469
25c4c276 3470static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3471{
fc78f519
AK		 3472 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3473
3474 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3475 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3476}
3477
1439442c
SY		 3478static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3479{
d0d538b9
GN		 3480 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3481
6de4f3ad
AK		 3482 if (!test_bit(VCPU_EXREG_PDPTR,
3483 (unsigned long *)&vcpu->arch.regs_dirty))
3484 return;
3485
1439442c 3486 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3487 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3488 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3489 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3490 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3491 }
3492}
3493
8f5d549f
AK		 3494static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3495{
d0d538b9
GN		 3496 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3497
8f5d549f 3498 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3499 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3500 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3501 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3502 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3503 }
6de4f3ad
AK		 3504
3505 __set_bit(VCPU_EXREG_PDPTR,
3506 (unsigned long *)&vcpu->arch.regs_avail);
3507 __set_bit(VCPU_EXREG_PDPTR,
3508 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3509}
3510
5e1746d6 3511static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3512
3513static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3514 unsigned long cr0,
3515 struct kvm_vcpu *vcpu)
3516{
5233dd51
MT		 3517 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3518 vmx_decache_cr3(vcpu);
1439442c
SY		 3519 if (!(cr0 & X86_CR0_PG)) {
3520 /* From paging/starting to nonpaging */
3521 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3522 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3523 (CPU_BASED_CR3_LOAD_EXITING |
3524 CPU_BASED_CR3_STORE_EXITING));
3525 vcpu->arch.cr0 = cr0;
fc78f519 3526 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3527 } else if (!is_paging(vcpu)) {
3528 /* From nonpaging to paging */
3529 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3530 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3531 ~(CPU_BASED_CR3_LOAD_EXITING |
3532 CPU_BASED_CR3_STORE_EXITING));
3533 vcpu->arch.cr0 = cr0;
fc78f519 3534 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3535 }
95eb84a7
SY		 3536
3537 if (!(cr0 & X86_CR0_WP))
3538 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3539}
3540
6aa8b732
AK		 3541static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3542{
7ffd92c5 3543 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3544 unsigned long hw_cr0;
3545
5037878e 3546 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3547 if (enable_unrestricted_guest)
5037878e 3548 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3549 else {
5037878e 3550 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3551
218e763f
GN		 3552 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3553 enter_pmode(vcpu);
6aa8b732 3554
218e763f
GN		 3555 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3556 enter_rmode(vcpu);
3557 }
6aa8b732 3558
05b3e0c2 3559#ifdef CONFIG_X86_64
f6801dff 3560 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3561 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3562 enter_lmode(vcpu);
707d92fa 3563 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3564 exit_lmode(vcpu);
3565 }
3566#endif
3567
089d034e 3568 if (enable_ept)
1439442c
SY		 3569 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3570
02daab21 3571 if (!vcpu->fpu_active)
81231c69 3572 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3573
6aa8b732 3574 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3575 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3576 vcpu->arch.cr0 = cr0;
14168786
GN		 3577
3578 /* depends on vcpu->arch.cr0 to be set to a new value */
3579 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3580}
3581
1439442c
SY		 3582static u64 construct_eptp(unsigned long root_hpa)
3583{
3584 u64 eptp;
3585
3586 /* TODO write the value reading from MSR */
3587 eptp = VMX_EPT_DEFAULT_MT |
3588 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3589 if (enable_ept_ad_bits)
3590 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3591 eptp |= (root_hpa & PAGE_MASK);
3592
3593 return eptp;
3594}
3595
6aa8b732
AK		 3596static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3597{
1439442c
SY		 3598 unsigned long guest_cr3;
3599 u64 eptp;
3600
3601 guest_cr3 = cr3;
089d034e 3602 if (enable_ept) {
1439442c
SY		 3603 eptp = construct_eptp(cr3);
3604 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3605 if (is_paging(vcpu) || is_guest_mode(vcpu))
3606 guest_cr3 = kvm_read_cr3(vcpu);
3607 else
3608 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3609 ept_load_pdptrs(vcpu);
1439442c
SY		 3610 }
3611
2384d2b3 3612 vmx_flush_tlb(vcpu);
1439442c 3613 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3614}
3615
5e1746d6 3616static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3617{
085e68ee
BS		 3618 /*
3619 * Pass through host's Machine Check Enable value to hw_cr4, which
3620 * is in force while we are in guest mode. Do not let guests control
3621 * this bit, even if host CR4.MCE == 0.
3622 */
3623 unsigned long hw_cr4 =
3624 (cr4_read_shadow() & X86_CR4_MCE) |
3625 (cr4 & ~X86_CR4_MCE) |
3626 (to_vmx(vcpu)->rmode.vm86_active ?
3627 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1439442c 3628
5e1746d6
NHE		 3629 if (cr4 & X86_CR4_VMXE) {
3630 /*
3631 * To use VMXON (and later other VMX instructions), a guest
3632 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3633 * So basically the check on whether to allow nested VMX
3634 * is here.
3635 */
3636 if (!nested_vmx_allowed(vcpu))
3637 return 1;
1a0d74e6
JK		 3638 }
3639 if (to_vmx(vcpu)->nested.vmxon &&
3640 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3641 return 1;
3642
ad312c7c 3643 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3644 if (enable_ept) {
3645 if (!is_paging(vcpu)) {
3646 hw_cr4 &= ~X86_CR4_PAE;
3647 hw_cr4 |= X86_CR4_PSE;
c08800a5 3648 /*
e1e746b3
FW		 3649 * SMEP/SMAP is disabled if CPU is in non-paging mode
3650 * in hardware. However KVM always uses paging mode to
c08800a5 3651 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3652 * To emulate this behavior, SMEP/SMAP needs to be
3653 * manually disabled when guest switches to non-paging
3654 * mode.
c08800a5 3655 */
e1e746b3 3656 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3657 } else if (!(cr4 & X86_CR4_PAE)) {
3658 hw_cr4 &= ~X86_CR4_PAE;
3659 }
3660 }
1439442c
SY		 3661
3662 vmcs_writel(CR4_READ_SHADOW, cr4);
3663 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3664 return 0;
6aa8b732
AK		 3665}
3666
6aa8b732
AK		 3667static void vmx_get_segment(struct kvm_vcpu *vcpu,
3668 struct kvm_segment *var, int seg)
3669{
a9179499 3670 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3671 u32 ar;
3672
c6ad1153 3673 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3674 *var = vmx->rmode.segs[seg];
a9179499 3675 if (seg == VCPU_SREG_TR
2fb92db1 3676 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3677 return;
1390a28b
AK		 3678 var->base = vmx_read_guest_seg_base(vmx, seg);
3679 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3680 return;
a9179499 3681 }
2fb92db1
AK		 3682 var->base = vmx_read_guest_seg_base(vmx, seg);
3683 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3684 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3685 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3686 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3687 var->type = ar & 15;
3688 var->s = (ar >> 4) & 1;
3689 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3690 /*
3691 * Some userspaces do not preserve unusable property. Since usable
3692 * segment has to be present according to VMX spec we can use present
3693 * property to amend userspace bug by making unusable segment always
3694 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3695 * segment as unusable.
3696 */
3697 var->present = !var->unusable;
6aa8b732
AK		 3698 var->avl = (ar >> 12) & 1;
3699 var->l = (ar >> 13) & 1;
3700 var->db = (ar >> 14) & 1;
3701 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3702}
3703
a9179499
AK		 3704static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3705{
a9179499
AK		 3706 struct kvm_segment s;
3707
3708 if (to_vmx(vcpu)->rmode.vm86_active) {
3709 vmx_get_segment(vcpu, &s, seg);
3710 return s.base;
3711 }
2fb92db1 3712 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3713}
3714
b09408d0 3715static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3716{
b09408d0
MT		 3717 struct vcpu_vmx *vmx = to_vmx(vcpu);
3718
ae9fedc7 3719 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3720 return 0;
ae9fedc7
PB		 3721 else {
3722 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 3723 return VMX_AR_DPL(ar);
69c73028 3724 }
69c73028
AK		 3725}
3726
653e3108 3727static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3728{
6aa8b732
AK		 3729 u32 ar;
3730
f0495f9b 3731 if (var->unusable || !var->present)
6aa8b732
AK		 3732 ar = 1 << 16;
3733 else {
3734 ar = var->type & 15;
3735 ar |= (var->s & 1) << 4;
3736 ar |= (var->dpl & 3) << 5;
3737 ar |= (var->present & 1) << 7;
3738 ar |= (var->avl & 1) << 12;
3739 ar |= (var->l & 1) << 13;
3740 ar |= (var->db & 1) << 14;
3741 ar |= (var->g & 1) << 15;
3742 }
653e3108
AK		 3743
3744 return ar;
3745}
3746
3747static void vmx_set_segment(struct kvm_vcpu *vcpu,
3748 struct kvm_segment *var, int seg)
3749{
7ffd92c5 3750 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3751 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3752
2fb92db1
AK		 3753 vmx_segment_cache_clear(vmx);
3754
1ecd50a9
GN		 3755 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3756 vmx->rmode.segs[seg] = *var;
3757 if (seg == VCPU_SREG_TR)
3758 vmcs_write16(sf->selector, var->selector);
3759 else if (var->s)
3760 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3761 goto out;
653e3108 3762 }
1ecd50a9 3763
653e3108
AK		 3764 vmcs_writel(sf->base, var->base);
3765 vmcs_write32(sf->limit, var->limit);
3766 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3767
3768 /*
3769 * Fix the "Accessed" bit in AR field of segment registers for older
3770 * qemu binaries.
3771 * IA32 arch specifies that at the time of processor reset the
3772 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3773 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3774 * state vmexit when "unrestricted guest" mode is turned on.
3775 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3776 * tree. Newer qemu binaries with that qemu fix would not need this
3777 * kvm hack.
3778 */
3779 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3780 var->type |= 0x1; /* Accessed */
3a624e29 3781
f924d66d 3782 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3783
3784out:
98eb2f8b 3785 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3786}
3787
6aa8b732
AK		 3788static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3789{
2fb92db1 3790 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3791
3792 *db = (ar >> 14) & 1;
3793 *l = (ar >> 13) & 1;
3794}
3795
89a27f4d 3796static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3797{
89a27f4d
GN		 3798 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3799 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3800}
3801
89a27f4d 3802static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3803{
89a27f4d
GN		 3804 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3805 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3806}
3807
89a27f4d 3808static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3809{
89a27f4d
GN		 3810 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3811 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3812}
3813
89a27f4d 3814static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3815{
89a27f4d
GN		 3816 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3817 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3818}
3819
648dfaa7
MG		 3820static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3821{
3822 struct kvm_segment var;
3823 u32 ar;
3824
3825 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3826 var.dpl = 0x3;
0647f4aa
GN		 3827 if (seg == VCPU_SREG_CS)
3828 var.type = 0x3;
648dfaa7
MG		 3829 ar = vmx_segment_access_rights(&var);
3830
3831 if (var.base != (var.selector << 4))
3832 return false;
89efbed0 3833 if (var.limit != 0xffff)
648dfaa7 3834 return false;
07f42f5f 3835 if (ar != 0xf3)
648dfaa7
MG		 3836 return false;
3837
3838 return true;
3839}
3840
3841static bool code_segment_valid(struct kvm_vcpu *vcpu)
3842{
3843 struct kvm_segment cs;
3844 unsigned int cs_rpl;
3845
3846 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 3847 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 3848
1872a3f4
AK		 3849 if (cs.unusable)
3850 return false;
4d283ec9 3851 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG		 3852 return false;
3853 if (!cs.s)
3854 return false;
4d283ec9 3855 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3856 if (cs.dpl > cs_rpl)
3857 return false;
1872a3f4 3858 } else {
648dfaa7
MG		 3859 if (cs.dpl != cs_rpl)
3860 return false;
3861 }
3862 if (!cs.present)
3863 return false;
3864
3865 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3866 return true;
3867}
3868
3869static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3870{
3871 struct kvm_segment ss;
3872 unsigned int ss_rpl;
3873
3874 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 3875 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 3876
1872a3f4
AK		 3877 if (ss.unusable)
3878 return true;
3879 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3880 return false;
3881 if (!ss.s)
3882 return false;
3883 if (ss.dpl != ss_rpl) /* DPL != RPL */
3884 return false;
3885 if (!ss.present)
3886 return false;
3887
3888 return true;
3889}
3890
3891static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3892{
3893 struct kvm_segment var;
3894 unsigned int rpl;
3895
3896 vmx_get_segment(vcpu, &var, seg);
b32a9918 3897 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 3898
1872a3f4
AK		 3899 if (var.unusable)
3900 return true;
648dfaa7
MG		 3901 if (!var.s)
3902 return false;
3903 if (!var.present)
3904 return false;
4d283ec9 3905 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG		 3906 if (var.dpl < rpl) /* DPL < RPL */
3907 return false;
3908 }
3909
3910 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3911 * rights flags
3912 */
3913 return true;
3914}
3915
3916static bool tr_valid(struct kvm_vcpu *vcpu)
3917{
3918 struct kvm_segment tr;
3919
3920 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3921
1872a3f4
AK		 3922 if (tr.unusable)
3923 return false;
b32a9918 3924 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 3925 return false;
1872a3f4 3926 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3927 return false;
3928 if (!tr.present)
3929 return false;
3930
3931 return true;
3932}
3933
3934static bool ldtr_valid(struct kvm_vcpu *vcpu)
3935{
3936 struct kvm_segment ldtr;
3937
3938 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3939
1872a3f4
AK		 3940 if (ldtr.unusable)
3941 return true;
b32a9918 3942 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG		 3943 return false;
3944 if (ldtr.type != 2)
3945 return false;
3946 if (!ldtr.present)
3947 return false;
3948
3949 return true;
3950}
3951
3952static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3953{
3954 struct kvm_segment cs, ss;
3955
3956 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3957 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3958
b32a9918
NA		 3959 return ((cs.selector & SEGMENT_RPL_MASK) ==
3960 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG		 3961}
3962
3963/*
3964 * Check if guest state is valid. Returns true if valid, false if
3965 * not.
3966 * We assume that registers are always usable
3967 */
3968static bool guest_state_valid(struct kvm_vcpu *vcpu)
3969{
c5e97c80
GN		 3970 if (enable_unrestricted_guest)
3971 return true;
3972
648dfaa7 3973 /* real mode guest state checks */
f13882d8 3974 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3975 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3976 return false;
3977 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3978 return false;
3979 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3980 return false;
3981 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3982 return false;
3983 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3984 return false;
3985 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3986 return false;
3987 } else {
3988 /* protected mode guest state checks */
3989 if (!cs_ss_rpl_check(vcpu))
3990 return false;
3991 if (!code_segment_valid(vcpu))
3992 return false;
3993 if (!stack_segment_valid(vcpu))
3994 return false;
3995 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3996 return false;
3997 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3998 return false;
3999 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4000 return false;
4001 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4002 return false;
4003 if (!tr_valid(vcpu))
4004 return false;
4005 if (!ldtr_valid(vcpu))
4006 return false;
4007 }
4008 /* TODO:
4009 * - Add checks on RIP
4010 * - Add checks on RFLAGS
4011 */
4012
4013 return true;
4014}
4015
d77c26fc 4016static int init_rmode_tss(struct kvm *kvm)
6aa8b732 4017{
40dcaa9f 4018 gfn_t fn;
195aefde 4019 u16 data = 0;
1f755a82 4020 int idx, r;
6aa8b732 4021
40dcaa9f 4022 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 4023 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 4024 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4025 if (r < 0)
10589a46 4026 goto out;
195aefde 4027 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 4028 r = kvm_write_guest_page(kvm, fn++, &data,
4029 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 4030 if (r < 0)
10589a46 4031 goto out;
195aefde
IE		 4032 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4033 if (r < 0)
10589a46 4034 goto out;
195aefde
IE		 4035 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4036 if (r < 0)
10589a46 4037 goto out;
195aefde 4038 data = ~0;
10589a46
MT		 4039 r = kvm_write_guest_page(kvm, fn, &data,
4040 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4041 sizeof(u8));
10589a46 4042out:
40dcaa9f 4043 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 4044 return r;
6aa8b732
AK		 4045}
4046
b7ebfb05
SY		 4047static int init_rmode_identity_map(struct kvm *kvm)
4048{
f51770ed 4049 int i, idx, r = 0;
b7ebfb05
SY		 4050 pfn_t identity_map_pfn;
4051 u32 tmp;
4052
089d034e 4053 if (!enable_ept)
f51770ed 4054 return 0;
a255d479
TC		 4055
4056 /* Protect kvm->arch.ept_identity_pagetable_done. */
4057 mutex_lock(&kvm->slots_lock);
4058
f51770ed 4059 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 4060 goto out2;
a255d479 4061
b927a3ce 4062 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 4063
4064 r = alloc_identity_pagetable(kvm);
f51770ed 4065 if (r < 0)
a255d479
TC		 4066 goto out2;
4067
40dcaa9f 4068 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 4069 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4070 if (r < 0)
4071 goto out;
4072 /* Set up identity-mapping pagetable for EPT in real mode */
4073 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4074 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4075 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4076 r = kvm_write_guest_page(kvm, identity_map_pfn,
4077 &tmp, i * sizeof(tmp), sizeof(tmp));
4078 if (r < 0)
4079 goto out;
4080 }
4081 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4082
b7ebfb05 4083out:
40dcaa9f 4084 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 4085
4086out2:
4087 mutex_unlock(&kvm->slots_lock);
f51770ed 4088 return r;
b7ebfb05
SY		 4089}
4090
6aa8b732
AK		 4091static void seg_setup(int seg)
4092{
772e0318 4093 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4094 unsigned int ar;
6aa8b732
AK		 4095
4096 vmcs_write16(sf->selector, 0);
4097 vmcs_writel(sf->base, 0);
4098 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4099 ar = 0x93;
4100 if (seg == VCPU_SREG_CS)
4101 ar |= 0x08; /* code segment */
3a624e29
NK		 4102
4103 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4104}
4105
f78e0e2e
SY		 4106static int alloc_apic_access_page(struct kvm *kvm)
4107{
4484141a 4108 struct page *page;
f78e0e2e
SY		 4109 struct kvm_userspace_memory_region kvm_userspace_mem;
4110 int r = 0;
4111
79fac95e 4112 mutex_lock(&kvm->slots_lock);
c24ae0dc 4113 if (kvm->arch.apic_access_page_done)
f78e0e2e
SY		 4114 goto out;
4115 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4116 kvm_userspace_mem.flags = 0;
73a6d941 4117 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 4118 kvm_userspace_mem.memory_size = PAGE_SIZE;
9da0e4d5 4119 r = __x86_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4120 if (r)
4121 goto out;
72dc67a6 4122
73a6d941 4123 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4124 if (is_error_page(page)) {
4125 r = -EFAULT;
4126 goto out;
4127 }
4128
c24ae0dc
TC		 4129 /*
4130 * Do not pin the page in memory, so that memory hot-unplug
4131 * is able to migrate it.
4132 */
4133 put_page(page);
4134 kvm->arch.apic_access_page_done = true;
f78e0e2e 4135out:
79fac95e 4136 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4137 return r;
4138}
4139
b7ebfb05
SY		 4140static int alloc_identity_pagetable(struct kvm *kvm)
4141{
a255d479
TC		 4142 /* Called with kvm->slots_lock held. */
4143
b7ebfb05
SY		 4144 struct kvm_userspace_memory_region kvm_userspace_mem;
4145 int r = 0;
4146
a255d479
TC		 4147 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4148
b7ebfb05
SY		 4149 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4150 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4151 kvm_userspace_mem.guest_phys_addr =
4152 kvm->arch.ept_identity_map_addr;
b7ebfb05 4153 kvm_userspace_mem.memory_size = PAGE_SIZE;
9da0e4d5 4154 r = __x86_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4155
b7ebfb05
SY		 4156 return r;
4157}
4158
2384d2b3
SY		 4159static void allocate_vpid(struct vcpu_vmx *vmx)
4160{
4161 int vpid;
4162
4163 vmx->vpid = 0;
919818ab 4164 if (!enable_vpid)
2384d2b3
SY		 4165 return;
4166 spin_lock(&vmx_vpid_lock);
4167 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4168 if (vpid < VMX_NR_VPIDS) {
4169 vmx->vpid = vpid;
4170 __set_bit(vpid, vmx_vpid_bitmap);
4171 }
4172 spin_unlock(&vmx_vpid_lock);
4173}
4174
cdbecfc3
LJ		 4175static void free_vpid(struct vcpu_vmx *vmx)
4176{
4177 if (!enable_vpid)
4178 return;
4179 spin_lock(&vmx_vpid_lock);
4180 if (vmx->vpid != 0)
4181 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4182 spin_unlock(&vmx_vpid_lock);
4183}
4184
8d14695f
YZ		 4185#define MSR_TYPE_R 1
4186#define MSR_TYPE_W 2
4187static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4188 u32 msr, int type)
25c5f225 4189{
3e7c73e9 4190 int f = sizeof(unsigned long);
25c5f225
SY		 4191
4192 if (!cpu_has_vmx_msr_bitmap())
4193 return;
4194
4195 /*
4196 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4197 * have the write-low and read-high bitmap offsets the wrong way round.
4198 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4199 */
25c5f225 4200 if (msr <= 0x1fff) {
8d14695f
YZ		 4201 if (type & MSR_TYPE_R)
4202 /* read-low */
4203 __clear_bit(msr, msr_bitmap + 0x000 / f);
4204
4205 if (type & MSR_TYPE_W)
4206 /* write-low */
4207 __clear_bit(msr, msr_bitmap + 0x800 / f);
4208
25c5f225
SY		 4209 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4210 msr &= 0x1fff;
8d14695f
YZ		 4211 if (type & MSR_TYPE_R)
4212 /* read-high */
4213 __clear_bit(msr, msr_bitmap + 0x400 / f);
4214
4215 if (type & MSR_TYPE_W)
4216 /* write-high */
4217 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4218
4219 }
4220}
4221
4222static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4223 u32 msr, int type)
4224{
4225 int f = sizeof(unsigned long);
4226
4227 if (!cpu_has_vmx_msr_bitmap())
4228 return;
4229
4230 /*
4231 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4232 * have the write-low and read-high bitmap offsets the wrong way round.
4233 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4234 */
4235 if (msr <= 0x1fff) {
4236 if (type & MSR_TYPE_R)
4237 /* read-low */
4238 __set_bit(msr, msr_bitmap + 0x000 / f);
4239
4240 if (type & MSR_TYPE_W)
4241 /* write-low */
4242 __set_bit(msr, msr_bitmap + 0x800 / f);
4243
4244 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4245 msr &= 0x1fff;
4246 if (type & MSR_TYPE_R)
4247 /* read-high */
4248 __set_bit(msr, msr_bitmap + 0x400 / f);
4249
4250 if (type & MSR_TYPE_W)
4251 /* write-high */
4252 __set_bit(msr, msr_bitmap + 0xc00 / f);
4253
25c5f225 4254 }
25c5f225
SY		 4255}
4256
f2b93280
WV		 4257/*
4258 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4259 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4260 */
4261static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4262 unsigned long *msr_bitmap_nested,
4263 u32 msr, int type)
4264{
4265 int f = sizeof(unsigned long);
4266
4267 if (!cpu_has_vmx_msr_bitmap()) {
4268 WARN_ON(1);
4269 return;
4270 }
4271
4272 /*
4273 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4274 * have the write-low and read-high bitmap offsets the wrong way round.
4275 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4276 */
4277 if (msr <= 0x1fff) {
4278 if (type & MSR_TYPE_R &&
4279 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4280 /* read-low */
4281 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4282
4283 if (type & MSR_TYPE_W &&
4284 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4285 /* write-low */
4286 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4287
4288 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4289 msr &= 0x1fff;
4290 if (type & MSR_TYPE_R &&
4291 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4292 /* read-high */
4293 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4294
4295 if (type & MSR_TYPE_W &&
4296 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4297 /* write-high */
4298 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4299
4300 }
4301}
4302
5897297b
AK		 4303static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4304{
4305 if (!longmode_only)
8d14695f
YZ		 4306 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4307 msr, MSR_TYPE_R | MSR_TYPE_W);
4308 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4309 msr, MSR_TYPE_R | MSR_TYPE_W);
4310}
4311
4312static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4313{
4314 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4315 msr, MSR_TYPE_R);
4316 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4317 msr, MSR_TYPE_R);
4318}
4319
4320static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4321{
4322 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4323 msr, MSR_TYPE_R);
4324 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4325 msr, MSR_TYPE_R);
4326}
4327
4328static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4329{
4330 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4331 msr, MSR_TYPE_W);
4332 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4333 msr, MSR_TYPE_W);
5897297b
AK		 4334}
4335
d50ab6c1
PB		 4336static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
4337{
35754c98 4338 return enable_apicv && lapic_in_kernel(vcpu);
d50ab6c1
PB		 4339}
4340
705699a1
WV		 4341static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4342{
4343 struct vcpu_vmx *vmx = to_vmx(vcpu);
4344 int max_irr;
4345 void *vapic_page;
4346 u16 status;
4347
4348 if (vmx->nested.pi_desc &&
4349 vmx->nested.pi_pending) {
4350 vmx->nested.pi_pending = false;
4351 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4352 return 0;
4353
4354 max_irr = find_last_bit(
4355 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4356
4357 if (max_irr == 256)
4358 return 0;
4359
4360 vapic_page = kmap(vmx->nested.virtual_apic_page);
4361 if (!vapic_page) {
4362 WARN_ON(1);
4363 return -ENOMEM;
4364 }
4365 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4366 kunmap(vmx->nested.virtual_apic_page);
4367
4368 status = vmcs_read16(GUEST_INTR_STATUS);
4369 if ((u8)max_irr > ((u8)status & 0xff)) {
4370 status &= ~0xff;
4371 status |= (u8)max_irr;
4372 vmcs_write16(GUEST_INTR_STATUS, status);
4373 }
4374 }
4375 return 0;
4376}
4377
21bc8dc5
RK		 4378static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4379{
4380#ifdef CONFIG_SMP
4381 if (vcpu->mode == IN_GUEST_MODE) {
4382 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4383 POSTED_INTR_VECTOR);
4384 return true;
4385 }
4386#endif
4387 return false;
4388}
4389
705699a1
WV		 4390static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4391 int vector)
4392{
4393 struct vcpu_vmx *vmx = to_vmx(vcpu);
4394
4395 if (is_guest_mode(vcpu) &&
4396 vector == vmx->nested.posted_intr_nv) {
4397 /* the PIR and ON have been set by L1. */
21bc8dc5 4398 kvm_vcpu_trigger_posted_interrupt(vcpu);
705699a1
WV		 4399 /*
4400 * If a posted intr is not recognized by hardware,
4401 * we will accomplish it in the next vmentry.
4402 */
4403 vmx->nested.pi_pending = true;
4404 kvm_make_request(KVM_REQ_EVENT, vcpu);
4405 return 0;
4406 }
4407 return -1;
4408}
a20ed54d
YZ		 4409/*
4410 * Send interrupt to vcpu via posted interrupt way.
4411 * 1. If target vcpu is running(non-root mode), send posted interrupt
4412 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4413 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4414 * interrupt from PIR in next vmentry.
4415 */
4416static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4417{
4418 struct vcpu_vmx *vmx = to_vmx(vcpu);
4419 int r;
4420
705699a1
WV		 4421 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4422 if (!r)
4423 return;
4424
a20ed54d
YZ		 4425 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4426 return;
4427
4428 r = pi_test_and_set_on(&vmx->pi_desc);
4429 kvm_make_request(KVM_REQ_EVENT, vcpu);
21bc8dc5 4430 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
a20ed54d
YZ		 4431 kvm_vcpu_kick(vcpu);
4432}
4433
4434static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4435{
4436 struct vcpu_vmx *vmx = to_vmx(vcpu);
4437
4438 if (!pi_test_and_clear_on(&vmx->pi_desc))
4439 return;
4440
4441 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4442}
4443
4444static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4445{
4446 return;
4447}
4448
a3a8ff8e
NHE		 4449/*
4450 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4451 * will not change in the lifetime of the guest.
4452 * Note that host-state that does change is set elsewhere. E.g., host-state
4453 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4454 */
a547c6db 4455static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4456{
4457 u32 low32, high32;
4458 unsigned long tmpl;
4459 struct desc_ptr dt;
d974baa3 4460 unsigned long cr4;
a3a8ff8e 4461
b1a74bf8 4462 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4463 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4464
d974baa3 4465 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 4466 cr4 = cr4_read_shadow();
d974baa3
AL		 4467 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4468 vmx->host_state.vmcs_host_cr4 = cr4;
4469
a3a8ff8e 4470 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4471#ifdef CONFIG_X86_64
4472 /*
4473 * Load null selectors, so we can avoid reloading them in
4474 * __vmx_load_host_state(), in case userspace uses the null selectors
4475 * too (the expected case).
4476 */
4477 vmcs_write16(HOST_DS_SELECTOR, 0);
4478 vmcs_write16(HOST_ES_SELECTOR, 0);
4479#else
a3a8ff8e
NHE		 4480 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4481 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4482#endif
a3a8ff8e
NHE		 4483 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4484 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4485
4486 native_store_idt(&dt);
4487 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4488 vmx->host_idt_base = dt.address;
a3a8ff8e 4489
83287ea4 4490 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4491
4492 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4493 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4494 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4495 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4496
4497 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4498 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4499 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4500 }
4501}
4502
bf8179a0
NHE		 4503static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4504{
4505 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4506 if (enable_ept)
4507 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4508 if (is_guest_mode(&vmx->vcpu))
4509 vmx->vcpu.arch.cr4_guest_owned_bits &=
4510 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4511 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4512}
4513
01e439be
YZ		 4514static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4515{
4516 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4517
35754c98 4518 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
01e439be
YZ		 4519 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4520 return pin_based_exec_ctrl;
4521}
4522
bf8179a0
NHE		 4523static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4524{
4525 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4526
4527 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4528 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4529
35754c98 4530 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
bf8179a0
NHE		 4531 exec_control &= ~CPU_BASED_TPR_SHADOW;
4532#ifdef CONFIG_X86_64
4533 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4534 CPU_BASED_CR8_LOAD_EXITING;
4535#endif
4536 }
4537 if (!enable_ept)
4538 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4539 CPU_BASED_CR3_LOAD_EXITING |
4540 CPU_BASED_INVLPG_EXITING;
4541 return exec_control;
4542}
4543
4544static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4545{
4546 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
35754c98 4547 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
bf8179a0
NHE		 4548 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4549 if (vmx->vpid == 0)
4550 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4551 if (!enable_ept) {
4552 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4553 enable_unrestricted_guest = 0;
ad756a16
MJ		 4554 /* Enable INVPCID for non-ept guests may cause performance regression. */
4555 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4556 }
4557 if (!enable_unrestricted_guest)
4558 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4559 if (!ple_gap)
4560 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
35754c98 4561 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
c7c9c56c
YZ		 4562 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4563 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4564 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4565 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4566 (handle_vmptrld).
4567 We can NOT enable shadow_vmcs here because we don't have yet
4568 a current VMCS12
4569 */
4570 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
843e4330
KH		 4571 /* PML is enabled/disabled in creating/destorying vcpu */
4572 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4573
8b3e34e4
XG		 4574 /* Currently, we allow L1 guest to directly run pcommit instruction. */
4575 exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4576
bf8179a0
NHE		 4577 return exec_control;
4578}
4579
ce88decf
XG		 4580static void ept_set_mmio_spte_mask(void)
4581{
4582 /*
4583 * EPT Misconfigurations can be generated if the value of bits 2:0
4584 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4585 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4586 * spte.
4587 */
885032b9 4588 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4589}
4590
f53cd63c 4591#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK		 4592/*
4593 * Sets up the vmcs for emulated real mode.
4594 */
8b9cf98c 4595static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4596{
2e4ce7f5 4597#ifdef CONFIG_X86_64
6aa8b732 4598 unsigned long a;
2e4ce7f5 4599#endif
6aa8b732 4600 int i;
6aa8b732 4601
6aa8b732 4602 /* I/O */
3e7c73e9
AK		 4603 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4604 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4605
4607c2d7
AG		 4606 if (enable_shadow_vmcs) {
4607 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4608 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4609 }
25c5f225 4610 if (cpu_has_vmx_msr_bitmap())
5897297b 4611 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4612
6aa8b732
AK		 4613 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4614
6aa8b732 4615 /* Control */
01e439be 4616 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4617
bf8179a0 4618 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4619
8b3e34e4 4620 if (cpu_has_secondary_exec_ctrls())
bf8179a0
NHE		 4621 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4622 vmx_secondary_exec_control(vmx));
f78e0e2e 4623
35754c98 4624 if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
c7c9c56c
YZ		 4625 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4626 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4627 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4628 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4629
4630 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4631
4632 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4633 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4634 }
4635
4b8d54f9
ZE		 4636 if (ple_gap) {
4637 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4638 vmx->ple_window = ple_window;
4639 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4640 }
4641
c3707958
XG		 4642 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4643 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4644 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4645
9581d442
AK		 4646 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4647 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4648 vmx_set_constant_host_state(vmx);
05b3e0c2 4649#ifdef CONFIG_X86_64
6aa8b732
AK		 4650 rdmsrl(MSR_FS_BASE, a);
4651 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4652 rdmsrl(MSR_GS_BASE, a);
4653 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4654#else
4655 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4656 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4657#endif
4658
2cc51560
ED		 4659 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4660 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4661 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4662 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4663 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4664
74545705
RK		 4665 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4666 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 4667
03916db9 4668 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4669 u32 index = vmx_msr_index[i];
4670 u32 data_low, data_high;
a2fa3e9f 4671 int j = vmx->nmsrs;
6aa8b732
AK		 4672
4673 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4674 continue;
432bd6cb
AK		 4675 if (wrmsr_safe(index, data_low, data_high) < 0)
4676 continue;
26bb0981
AK		 4677 vmx->guest_msrs[j].index = i;
4678 vmx->guest_msrs[j].data = 0;
d5696725 4679 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4680 ++vmx->nmsrs;
6aa8b732 4681 }
6aa8b732 4682
2961e876
GN		 4683
4684 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4685
4686 /* 22.2.1, 20.8.1 */
2961e876 4687 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4688
e00c8cf2 4689 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4690 set_cr4_guest_host_mask(vmx);
e00c8cf2 4691
f53cd63c
WL		 4692 if (vmx_xsaves_supported())
4693 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4694
e00c8cf2
AK		 4695 return 0;
4696}
4697
d28bc9dd 4698static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK		 4699{
4700 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4701 struct msr_data apic_base_msr;
d28bc9dd 4702 u64 cr0;
e00c8cf2 4703
7ffd92c5 4704 vmx->rmode.vm86_active = 0;
e00c8cf2 4705
3b86cd99
JK		 4706 vmx->soft_vnmi_blocked = 0;
4707
ad312c7c 4708 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
d28bc9dd
NA		 4709 kvm_set_cr8(vcpu, 0);
4710
4711 if (!init_event) {
4712 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4713 MSR_IA32_APICBASE_ENABLE;
4714 if (kvm_vcpu_is_reset_bsp(vcpu))
4715 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4716 apic_base_msr.host_initiated = true;
4717 kvm_set_apic_base(vcpu, &apic_base_msr);
4718 }
e00c8cf2 4719
2fb92db1
AK		 4720 vmx_segment_cache_clear(vmx);
4721
5706be0d 4722 seg_setup(VCPU_SREG_CS);
66450a21 4723 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4724 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4725
4726 seg_setup(VCPU_SREG_DS);
4727 seg_setup(VCPU_SREG_ES);
4728 seg_setup(VCPU_SREG_FS);
4729 seg_setup(VCPU_SREG_GS);
4730 seg_setup(VCPU_SREG_SS);
4731
4732 vmcs_write16(GUEST_TR_SELECTOR, 0);
4733 vmcs_writel(GUEST_TR_BASE, 0);
4734 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4735 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4736
4737 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4738 vmcs_writel(GUEST_LDTR_BASE, 0);
4739 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4740 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4741
d28bc9dd
NA		 4742 if (!init_event) {
4743 vmcs_write32(GUEST_SYSENTER_CS, 0);
4744 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4745 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4746 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4747 }
e00c8cf2
AK		 4748
4749 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4750 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4751
e00c8cf2
AK		 4752 vmcs_writel(GUEST_GDTR_BASE, 0);
4753 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4754
4755 vmcs_writel(GUEST_IDTR_BASE, 0);
4756 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4757
443381a8 4758 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4759 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4760 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4761
e00c8cf2
AK		 4762 setup_msrs(vmx);
4763
6aa8b732
AK		 4764 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4765
d28bc9dd 4766 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 4767 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 4768 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 4769 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 4770 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY		 4771 vmcs_write32(TPR_THRESHOLD, 0);
4772 }
4773
a73896cb 4774 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4775
35754c98 4776 if (vmx_cpu_uses_apicv(vcpu))
01e439be
YZ		 4777 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4778
2384d2b3
SY		 4779 if (vmx->vpid != 0)
4780 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4781
d28bc9dd
NA		 4782 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4783 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4784 vmx->vcpu.arch.cr0 = cr0;
4785 vmx_set_cr4(vcpu, 0);
4786 if (!init_event)
4787 vmx_set_efer(vcpu, 0);
4788 vmx_fpu_activate(vcpu);
4789 update_exception_bitmap(vcpu);
6aa8b732 4790
b9d762fa 4791 vpid_sync_context(vmx);
6aa8b732
AK		 4792}
4793
b6f1250e
NHE		 4794/*
4795 * In nested virtualization, check if L1 asked to exit on external interrupts.
4796 * For most existing hypervisors, this will always return true.
4797 */
4798static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4799{
4800 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4801 PIN_BASED_EXT_INTR_MASK;
4802}
4803
77b0f5d6
BD		 4804/*
4805 * In nested virtualization, check if L1 has set
4806 * VM_EXIT_ACK_INTR_ON_EXIT
4807 */
4808static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4809{
4810 return get_vmcs12(vcpu)->vm_exit_controls &
4811 VM_EXIT_ACK_INTR_ON_EXIT;
4812}
4813
ea8ceb83
JK		 4814static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4815{
4816 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4817 PIN_BASED_NMI_EXITING;
4818}
4819
c9a7953f 4820static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4821{
4822 u32 cpu_based_vm_exec_control;
730dca42 4823
3b86cd99
JK		 4824 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4825 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4826 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4827}
4828
c9a7953f 4829static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4830{
4831 u32 cpu_based_vm_exec_control;
4832
c9a7953f
JK		 4833 if (!cpu_has_virtual_nmis() ||
4834 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4835 enable_irq_window(vcpu);
4836 return;
4837 }
3b86cd99
JK		 4838
4839 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4840 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4841 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4842}
4843
66fd3f7f 4844static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4845{
9c8cba37 4846 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4847 uint32_t intr;
4848 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4849
229456fc 4850 trace_kvm_inj_virq(irq);
2714d1d3 4851
fa89a817 4852 ++vcpu->stat.irq_injections;
7ffd92c5 4853 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4854 int inc_eip = 0;
4855 if (vcpu->arch.interrupt.soft)
4856 inc_eip = vcpu->arch.event_exit_inst_len;
4857 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4858 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4859 return;
4860 }
66fd3f7f
GN		 4861 intr = irq | INTR_INFO_VALID_MASK;
4862 if (vcpu->arch.interrupt.soft) {
4863 intr |= INTR_TYPE_SOFT_INTR;
4864 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4865 vmx->vcpu.arch.event_exit_inst_len);
4866 } else
4867 intr |= INTR_TYPE_EXT_INTR;
4868 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4869}
4870
f08864b4
SY		 4871static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4872{
66a5a347
JK		 4873 struct vcpu_vmx *vmx = to_vmx(vcpu);
4874
0b6ac343
NHE		 4875 if (is_guest_mode(vcpu))
4876 return;
4877
3b86cd99
JK		 4878 if (!cpu_has_virtual_nmis()) {
4879 /*
4880 * Tracking the NMI-blocked state in software is built upon
4881 * finding the next open IRQ window. This, in turn, depends on
4882 * well-behaving guests: They have to keep IRQs disabled at
4883 * least as long as the NMI handler runs. Otherwise we may
4884 * cause NMI nesting, maybe breaking the guest. But as this is
4885 * highly unlikely, we can live with the residual risk.
4886 */
4887 vmx->soft_vnmi_blocked = 1;
4888 vmx->vnmi_blocked_time = 0;
4889 }
4890
487b391d 4891 ++vcpu->stat.nmi_injections;
9d58b931 4892 vmx->nmi_known_unmasked = false;
7ffd92c5 4893 if (vmx->rmode.vm86_active) {
71f9833b 4894 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4895 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4896 return;
4897 }
f08864b4
SY		 4898 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4899 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4900}
4901
3cfc3092
JK		 4902static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4903{
4904 if (!cpu_has_virtual_nmis())
4905 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4906 if (to_vmx(vcpu)->nmi_known_unmasked)
4907 return false;
c332c83a 4908 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4909}
4910
4911static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4912{
4913 struct vcpu_vmx *vmx = to_vmx(vcpu);
4914
4915 if (!cpu_has_virtual_nmis()) {
4916 if (vmx->soft_vnmi_blocked != masked) {
4917 vmx->soft_vnmi_blocked = masked;
4918 vmx->vnmi_blocked_time = 0;
4919 }
4920 } else {
9d58b931 4921 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4922 if (masked)
4923 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4924 GUEST_INTR_STATE_NMI);
4925 else
4926 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4927 GUEST_INTR_STATE_NMI);
4928 }
4929}
4930
2505dc9f
JK		 4931static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4932{
b6b8a145
JK		 4933 if (to_vmx(vcpu)->nested.nested_run_pending)
4934 return 0;
ea8ceb83 4935
2505dc9f
JK		 4936 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4937 return 0;
4938
4939 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4940 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4941 | GUEST_INTR_STATE_NMI));
4942}
4943
78646121
GN		 4944static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4945{
b6b8a145
JK		 4946 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4947 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4948 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4949 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4950}
4951
cbc94022
IE		 4952static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4953{
4954 int ret;
4955 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4956 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4957 .guest_phys_addr = addr,
4958 .memory_size = PAGE_SIZE * 3,
4959 .flags = 0,
4960 };
4961
9da0e4d5 4962 ret = x86_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4963 if (ret)
4964 return ret;
bfc6d222 4965 kvm->arch.tss_addr = addr;
1f755a82 4966 return init_rmode_tss(kvm);
cbc94022
IE		 4967}
4968
0ca1b4f4 4969static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4970{
77ab6db0 4971 switch (vec) {
77ab6db0 4972 case BP_VECTOR:
c573cd22
JK		 4973 /*
4974 * Update instruction length as we may reinject the exception
4975 * from user space while in guest debugging mode.
4976 */
4977 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4978 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4979 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4980 return false;
4981 /* fall through */
4982 case DB_VECTOR:
4983 if (vcpu->guest_debug &
4984 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4985 return false;
d0bfb940
JK		 4986 /* fall through */
4987 case DE_VECTOR:
77ab6db0
JK		 4988 case OF_VECTOR:
4989 case BR_VECTOR:
4990 case UD_VECTOR:
4991 case DF_VECTOR:
4992 case SS_VECTOR:
4993 case GP_VECTOR:
4994 case MF_VECTOR:
0ca1b4f4
GN		 4995 return true;
4996 break;
77ab6db0 4997 }
0ca1b4f4
GN		 4998 return false;
4999}
5000
5001static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5002 int vec, u32 err_code)
5003{
5004 /*
5005 * Instruction with address size override prefix opcode 0x67
5006 * Cause the #SS fault with 0 error code in VM86 mode.
5007 */
5008 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5009 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5010 if (vcpu->arch.halt_request) {
5011 vcpu->arch.halt_request = 0;
5cb56059 5012 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN		 5013 }
5014 return 1;
5015 }
5016 return 0;
5017 }
5018
5019 /*
5020 * Forward all other exceptions that are valid in real mode.
5021 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5022 * the required debugging infrastructure rework.
5023 */
5024 kvm_queue_exception(vcpu, vec);
5025 return 1;
6aa8b732
AK		 5026}
5027
a0861c02
AK		 5028/*
5029 * Trigger machine check on the host. We assume all the MSRs are already set up
5030 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5031 * We pass a fake environment to the machine check handler because we want
5032 * the guest to be always treated like user space, no matter what context
5033 * it used internally.
5034 */
5035static void kvm_machine_check(void)
5036{
5037#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5038 struct pt_regs regs = {
5039 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5040 .flags = X86_EFLAGS_IF,
5041 };
5042
5043 do_machine_check(&regs, 0);
5044#endif
5045}
5046
851ba692 5047static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 5048{
5049 /* already handled by vcpu_run */
5050 return 1;
5051}
5052
851ba692 5053static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 5054{
1155f76a 5055 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 5056 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 5057 u32 intr_info, ex_no, error_code;
42dbaa5a 5058 unsigned long cr2, rip, dr6;
6aa8b732
AK		 5059 u32 vect_info;
5060 enum emulation_result er;
5061
1155f76a 5062 vect_info = vmx->idt_vectoring_info;
88786475 5063 intr_info = vmx->exit_intr_info;
6aa8b732 5064
a0861c02 5065 if (is_machine_check(intr_info))
851ba692 5066 return handle_machine_check(vcpu);
a0861c02 5067
e4a41889 5068 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 5069 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 5070
5071 if (is_no_device(intr_info)) {
5fd86fcf 5072 vmx_fpu_activate(vcpu);
2ab455cc
AL		 5073 return 1;
5074 }
5075
7aa81cc0 5076 if (is_invalid_opcode(intr_info)) {
ae1f5767
JK		 5077 if (is_guest_mode(vcpu)) {
5078 kvm_queue_exception(vcpu, UD_VECTOR);
5079 return 1;
5080 }
51d8b661 5081 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 5082 if (er != EMULATE_DONE)
7ee5d940 5083 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 5084 return 1;
5085 }
5086
6aa8b732 5087 error_code = 0;
2e11384c 5088 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 5089 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 5090
5091 /*
5092 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5093 * MMIO, it is better to report an internal error.
5094 * See the comments in vmx_handle_exit.
5095 */
5096 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5097 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5098 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5099 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 5100 vcpu->run->internal.ndata = 3;
bf4ca23e
XG		 5101 vcpu->run->internal.data[0] = vect_info;
5102 vcpu->run->internal.data[1] = intr_info;
80f0e95d 5103 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG		 5104 return 0;
5105 }
5106
6aa8b732 5107 if (is_page_fault(intr_info)) {
1439442c 5108 /* EPT won't cause page fault directly */
cf3ace79 5109 BUG_ON(enable_ept);
6aa8b732 5110 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 5111 trace_kvm_page_fault(cr2, error_code);
5112
3298b75c 5113 if (kvm_event_needs_reinjection(vcpu))
577bdc49 5114 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 5115 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 5116 }
5117
d0bfb940 5118 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 5119
5120 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5121 return handle_rmode_exception(vcpu, ex_no, error_code);
5122
42dbaa5a
JK		 5123 switch (ex_no) {
5124 case DB_VECTOR:
5125 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5126 if (!(vcpu->guest_debug &
5127 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 5128 vcpu->arch.dr6 &= ~15;
6f43ed01 5129 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 5130 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5131 skip_emulated_instruction(vcpu);
5132
42dbaa5a
JK		 5133 kvm_queue_exception(vcpu, DB_VECTOR);
5134 return 1;
5135 }
5136 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5137 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5138 /* fall through */
5139 case BP_VECTOR:
c573cd22
JK		 5140 /*
5141 * Update instruction length as we may reinject #BP from
5142 * user space while in guest debugging mode. Reading it for
5143 * #DB as well causes no harm, it is not used in that case.
5144 */
5145 vmx->vcpu.arch.event_exit_inst_len =
5146 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 5147 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 5148 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 5149 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5150 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 5151 break;
5152 default:
d0bfb940
JK		 5153 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5154 kvm_run->ex.exception = ex_no;
5155 kvm_run->ex.error_code = error_code;
42dbaa5a 5156 break;
6aa8b732 5157 }
6aa8b732
AK		 5158 return 0;
5159}
5160
851ba692 5161static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5162{
1165f5fe 5163 ++vcpu->stat.irq_exits;
6aa8b732
AK		 5164 return 1;
5165}
5166
851ba692 5167static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5168{
851ba692 5169 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 5170 return 0;
5171}
6aa8b732 5172
851ba692 5173static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5174{
bfdaab09 5175 unsigned long exit_qualification;
34c33d16 5176 int size, in, string;
039576c0 5177 unsigned port;
6aa8b732 5178
bfdaab09 5179 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5180 string = (exit_qualification & 16) != 0;
cf8f70bf 5181 in = (exit_qualification & 8) != 0;
e70669ab 5182
cf8f70bf 5183 ++vcpu->stat.io_exits;
e70669ab 5184
cf8f70bf 5185 if (string || in)
51d8b661 5186 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5187
cf8f70bf
GN		 5188 port = exit_qualification >> 16;
5189 size = (exit_qualification & 7) + 1;
e93f36bc 5190 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 5191
5192 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 5193}
5194
102d8325
IM		 5195static void
5196vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5197{
5198 /*
5199 * Patch in the VMCALL instruction:
5200 */
5201 hypercall[0] = 0x0f;
5202 hypercall[1] = 0x01;
5203 hypercall[2] = 0xc1;
102d8325
IM		 5204}
5205
b9c237bb 5206static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
92fbc7b1
JK		 5207{
5208 unsigned long always_on = VMXON_CR0_ALWAYSON;
b9c237bb 5209 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
92fbc7b1 5210
b9c237bb 5211 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
92fbc7b1
JK		 5212 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5213 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5214 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5215 return (val & always_on) == always_on;
5216}
5217
0fa06071 5218/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5219static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5220{
eeadf9e7 5221 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5222 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5223 unsigned long orig_val = val;
5224
eeadf9e7
NHE		 5225 /*
5226 * We get here when L2 changed cr0 in a way that did not change
5227 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5228 * but did change L0 shadowed bits. So we first calculate the
5229 * effective cr0 value that L1 would like to write into the
5230 * hardware. It consists of the L2-owned bits from the new
5231 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5232 */
1a0d74e6
JK		 5233 val = (val & ~vmcs12->cr0_guest_host_mask) |
5234 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5235
b9c237bb 5236 if (!nested_cr0_valid(vcpu, val))
eeadf9e7 5237 return 1;
1a0d74e6
JK		 5238
5239 if (kvm_set_cr0(vcpu, val))
5240 return 1;
5241 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5242 return 0;
1a0d74e6
JK		 5243 } else {
5244 if (to_vmx(vcpu)->nested.vmxon &&
5245 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5246 return 1;
eeadf9e7 5247 return kvm_set_cr0(vcpu, val);
1a0d74e6 5248 }
eeadf9e7
NHE		 5249}
5250
5251static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5252{
5253 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5254 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5255 unsigned long orig_val = val;
5256
5257 /* analogously to handle_set_cr0 */
5258 val = (val & ~vmcs12->cr4_guest_host_mask) |
5259 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5260 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5261 return 1;
1a0d74e6 5262 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5263 return 0;
5264 } else
5265 return kvm_set_cr4(vcpu, val);
5266}
5267
5268/* called to set cr0 as approriate for clts instruction exit. */
5269static void handle_clts(struct kvm_vcpu *vcpu)
5270{
5271 if (is_guest_mode(vcpu)) {
5272 /*
5273 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5274 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5275 * just pretend it's off (also in arch.cr0 for fpu_activate).
5276 */
5277 vmcs_writel(CR0_READ_SHADOW,
5278 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5279 vcpu->arch.cr0 &= ~X86_CR0_TS;
5280 } else
5281 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5282}
5283
851ba692 5284static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5285{
229456fc 5286 unsigned long exit_qualification, val;
6aa8b732
AK		 5287 int cr;
5288 int reg;
49a9b07e 5289 int err;
6aa8b732 5290
bfdaab09 5291 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5292 cr = exit_qualification & 15;
5293 reg = (exit_qualification >> 8) & 15;
5294 switch ((exit_qualification >> 4) & 3) {
5295 case 0: /* mov to cr */
1e32c079 5296 val = kvm_register_readl(vcpu, reg);
229456fc 5297 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5298 switch (cr) {
5299 case 0:
eeadf9e7 5300 err = handle_set_cr0(vcpu, val);
db8fcefa 5301 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5302 return 1;
5303 case 3:
2390218b 5304 err = kvm_set_cr3(vcpu, val);
db8fcefa 5305 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5306 return 1;
5307 case 4:
eeadf9e7 5308 err = handle_set_cr4(vcpu, val);
db8fcefa 5309 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5310 return 1;
0a5fff19
GN		 5311 case 8: {
5312 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5313 u8 cr8 = (u8)val;
eea1cff9 5314 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5315 kvm_complete_insn_gp(vcpu, err);
35754c98 5316 if (lapic_in_kernel(vcpu))
0a5fff19
GN		 5317 return 1;
5318 if (cr8_prev <= cr8)
5319 return 1;
851ba692 5320 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5321 return 0;
5322 }
4b8073e4 5323 }
6aa8b732 5324 break;
25c4c276 5325 case 2: /* clts */
eeadf9e7 5326 handle_clts(vcpu);
4d4ec087 5327 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5328 skip_emulated_instruction(vcpu);
6b52d186 5329 vmx_fpu_activate(vcpu);
25c4c276 5330 return 1;
6aa8b732
AK		 5331 case 1: /*mov from cr*/
5332 switch (cr) {
5333 case 3:
9f8fe504
AK		 5334 val = kvm_read_cr3(vcpu);
5335 kvm_register_write(vcpu, reg, val);
5336 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5337 skip_emulated_instruction(vcpu);
5338 return 1;
5339 case 8:
229456fc
MT		 5340 val = kvm_get_cr8(vcpu);
5341 kvm_register_write(vcpu, reg, val);
5342 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5343 skip_emulated_instruction(vcpu);
5344 return 1;
5345 }
5346 break;
5347 case 3: /* lmsw */
a1f83a74 5348 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5349 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5350 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5351
5352 skip_emulated_instruction(vcpu);
5353 return 1;
5354 default:
5355 break;
5356 }
851ba692 5357 vcpu->run->exit_reason = 0;
a737f256 5358 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5359 (int)(exit_qualification >> 4) & 3, cr);
5360 return 0;
5361}
5362
851ba692 5363static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5364{
bfdaab09 5365 unsigned long exit_qualification;
16f8a6f9
NA		 5366 int dr, dr7, reg;
5367
5368 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5369 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5370
5371 /* First, if DR does not exist, trigger UD */
5372 if (!kvm_require_dr(vcpu, dr))
5373 return 1;
6aa8b732 5374
f2483415 5375 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5376 if (!kvm_require_cpl(vcpu, 0))
5377 return 1;
16f8a6f9
NA		 5378 dr7 = vmcs_readl(GUEST_DR7);
5379 if (dr7 & DR7_GD) {
42dbaa5a
JK		 5380 /*
5381 * As the vm-exit takes precedence over the debug trap, we
5382 * need to emulate the latter, either for the host or the
5383 * guest debugging itself.
5384 */
5385 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5386 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5387 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5388 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 5389 vcpu->run->debug.arch.exception = DB_VECTOR;
5390 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5391 return 0;
5392 } else {
7305eb5d 5393 vcpu->arch.dr6 &= ~15;
6f43ed01 5394 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5395 kvm_queue_exception(vcpu, DB_VECTOR);
5396 return 1;
5397 }
5398 }
5399
81908bf4
PB		 5400 if (vcpu->guest_debug == 0) {
5401 u32 cpu_based_vm_exec_control;
5402
5403 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5404 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5405 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5406
5407 /*
5408 * No more DR vmexits; force a reload of the debug registers
5409 * and reenter on this instruction. The next vmexit will
5410 * retrieve the full state of the debug registers.
5411 */
5412 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5413 return 1;
5414 }
5415
42dbaa5a
JK		 5416 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5417 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5418 unsigned long val;
4c4d563b
JK		 5419
5420 if (kvm_get_dr(vcpu, dr, &val))
5421 return 1;
5422 kvm_register_write(vcpu, reg, val);
020df079 5423 } else
5777392e 5424 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5425 return 1;
5426
6aa8b732
AK		 5427 skip_emulated_instruction(vcpu);
5428 return 1;
5429}
5430
73aaf249
JK		 5431static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5432{
5433 return vcpu->arch.dr6;
5434}
5435
5436static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5437{
5438}
5439
81908bf4
PB		 5440static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5441{
5442 u32 cpu_based_vm_exec_control;
5443
5444 get_debugreg(vcpu->arch.db[0], 0);
5445 get_debugreg(vcpu->arch.db[1], 1);
5446 get_debugreg(vcpu->arch.db[2], 2);
5447 get_debugreg(vcpu->arch.db[3], 3);
5448 get_debugreg(vcpu->arch.dr6, 6);
5449 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5450
5451 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5452
5453 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5454 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5455 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5456}
5457
020df079
GN		 5458static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5459{
5460 vmcs_writel(GUEST_DR7, val);
5461}
5462
851ba692 5463static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5464{
06465c5a
AK		 5465 kvm_emulate_cpuid(vcpu);
5466 return 1;
6aa8b732
AK		 5467}
5468
851ba692 5469static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5470{
ad312c7c 5471 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
609e36d3 5472 struct msr_data msr_info;
6aa8b732 5473
609e36d3
PB		 5474 msr_info.index = ecx;
5475 msr_info.host_initiated = false;
5476 if (vmx_get_msr(vcpu, &msr_info)) {
59200273 5477 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5478 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5479 return 1;
5480 }
5481
609e36d3 5482 trace_kvm_msr_read(ecx, msr_info.data);
2714d1d3 5483
6aa8b732 5484 /* FIXME: handling of bits 32:63 of rax, rdx */
609e36d3
PB		 5485 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5486 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6aa8b732
AK		 5487 skip_emulated_instruction(vcpu);
5488 return 1;
5489}
5490
851ba692 5491static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5492{
8fe8ab46 5493 struct msr_data msr;
ad312c7c
ZX		 5494 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5495 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5496 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5497
8fe8ab46
WA		 5498 msr.data = data;
5499 msr.index = ecx;
5500 msr.host_initiated = false;
854e8bb1 5501 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5502 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5503 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5504 return 1;
5505 }
5506
59200273 5507 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5508 skip_emulated_instruction(vcpu);
5509 return 1;
5510}
5511
851ba692 5512static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5513{
3842d135 5514 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5515 return 1;
5516}
5517
851ba692 5518static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5519{
85f455f7
ED		 5520 u32 cpu_based_vm_exec_control;
5521
5522 /* clear pending irq */
5523 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5524 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5525 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5526
3842d135
AK		 5527 kvm_make_request(KVM_REQ_EVENT, vcpu);
5528
a26bf12a 5529 ++vcpu->stat.irq_window_exits;
6aa8b732
AK		 5530 return 1;
5531}
5532
851ba692 5533static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 5534{
d3bef15f 5535 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5536}
5537
851ba692 5538static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5539{
7aa81cc0
AL		 5540 kvm_emulate_hypercall(vcpu);
5541 return 1;
c21415e8
IM		 5542}
5543
ec25d5e6
GN		 5544static int handle_invd(struct kvm_vcpu *vcpu)
5545{
51d8b661 5546 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5547}
5548
851ba692 5549static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5550{
f9c617f6 5551 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5552
5553 kvm_mmu_invlpg(vcpu, exit_qualification);
5554 skip_emulated_instruction(vcpu);
5555 return 1;
5556}
5557
fee84b07
AK		 5558static int handle_rdpmc(struct kvm_vcpu *vcpu)
5559{
5560 int err;
5561
5562 err = kvm_rdpmc(vcpu);
5563 kvm_complete_insn_gp(vcpu, err);
5564
5565 return 1;
5566}
5567
851ba692 5568static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 5569{
f5f48ee1 5570 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5571 return 1;
5572}
5573
2acf923e
DC		 5574static int handle_xsetbv(struct kvm_vcpu *vcpu)
5575{
5576 u64 new_bv = kvm_read_edx_eax(vcpu);
5577 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5578
5579 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5580 skip_emulated_instruction(vcpu);
5581 return 1;
5582}
5583
f53cd63c
WL		 5584static int handle_xsaves(struct kvm_vcpu *vcpu)
5585{
5586 skip_emulated_instruction(vcpu);
5587 WARN(1, "this should never happen\n");
5588 return 1;
5589}
5590
5591static int handle_xrstors(struct kvm_vcpu *vcpu)
5592{
5593 skip_emulated_instruction(vcpu);
5594 WARN(1, "this should never happen\n");
5595 return 1;
5596}
5597
851ba692 5598static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5599{
58fbbf26
KT		 5600 if (likely(fasteoi)) {
5601 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5602 int access_type, offset;
5603
5604 access_type = exit_qualification & APIC_ACCESS_TYPE;
5605 offset = exit_qualification & APIC_ACCESS_OFFSET;
5606 /*
5607 * Sane guest uses MOV to write EOI, with written value
5608 * not cared. So make a short-circuit here by avoiding
5609 * heavy instruction emulation.
5610 */
5611 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5612 (offset == APIC_EOI)) {
5613 kvm_lapic_set_eoi(vcpu);
5614 skip_emulated_instruction(vcpu);
5615 return 1;
5616 }
5617 }
51d8b661 5618 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5619}
5620
c7c9c56c
YZ		 5621static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5622{
5623 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5624 int vector = exit_qualification & 0xff;
5625
5626 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5627 kvm_apic_set_eoi_accelerated(vcpu, vector);
5628 return 1;
5629}
5630
83d4c286
YZ		 5631static int handle_apic_write(struct kvm_vcpu *vcpu)
5632{
5633 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5634 u32 offset = exit_qualification & 0xfff;
5635
5636 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5637 kvm_apic_write_nodecode(vcpu, offset);
5638 return 1;
5639}
5640
851ba692 5641static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5642{
60637aac 5643 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5644 unsigned long exit_qualification;
e269fb21
JK		 5645 bool has_error_code = false;
5646 u32 error_code = 0;
37817f29 5647 u16 tss_selector;
7f3d35fd 5648 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5649
5650 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5651 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5652 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5653
5654 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5655
5656 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5657 if (reason == TASK_SWITCH_GATE && idt_v) {
5658 switch (type) {
5659 case INTR_TYPE_NMI_INTR:
5660 vcpu->arch.nmi_injected = false;
654f06fc 5661 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5662 break;
5663 case INTR_TYPE_EXT_INTR:
66fd3f7f 5664 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5665 kvm_clear_interrupt_queue(vcpu);
5666 break;
5667 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5668 if (vmx->idt_vectoring_info &
5669 VECTORING_INFO_DELIVER_CODE_MASK) {
5670 has_error_code = true;
5671 error_code =
5672 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5673 }
5674 /* fall through */
64a7ec06
GN		 5675 case INTR_TYPE_SOFT_EXCEPTION:
5676 kvm_clear_exception_queue(vcpu);
5677 break;
5678 default:
5679 break;
5680 }
60637aac 5681 }
37817f29
IE		 5682 tss_selector = exit_qualification;
5683
64a7ec06
GN		 5684 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5685 type != INTR_TYPE_EXT_INTR &&
5686 type != INTR_TYPE_NMI_INTR))
5687 skip_emulated_instruction(vcpu);
5688
7f3d35fd
KW		 5689 if (kvm_task_switch(vcpu, tss_selector,
5690 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5691 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5692 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5693 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5694 vcpu->run->internal.ndata = 0;
42dbaa5a 5695 return 0;
acb54517 5696 }
42dbaa5a 5697
42dbaa5a
JK		 5698 /*
5699 * TODO: What about debug traps on tss switch?
5700 * Are we supposed to inject them and update dr6?
5701 */
5702
5703 return 1;
37817f29
IE		 5704}
5705
851ba692 5706static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5707{
f9c617f6 5708 unsigned long exit_qualification;
1439442c 5709 gpa_t gpa;
4f5982a5 5710 u32 error_code;
1439442c 5711 int gla_validity;
1439442c 5712
f9c617f6 5713 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5714
1439442c
SY		 5715 gla_validity = (exit_qualification >> 7) & 0x3;
5716 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5717 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5718 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5719 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5720 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5721 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5722 (long unsigned int)exit_qualification);
851ba692
AK		 5723 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5724 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5725 return 0;
1439442c
SY		 5726 }
5727
0be9c7a8
GN		 5728 /*
5729 * EPT violation happened while executing iret from NMI,
5730 * "blocked by NMI" bit has to be set before next VM entry.
5731 * There are errata that may cause this bit to not be set:
5732 * AAK134, BY25.
5733 */
bcd1c294
GN		 5734 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5735 cpu_has_virtual_nmis() &&
5736 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5737 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5738
1439442c 5739 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5740 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5741
5742 /* It is a write fault? */
81ed33e4 5743 error_code = exit_qualification & PFERR_WRITE_MASK;
25d92081 5744 /* It is a fetch fault? */
81ed33e4 5745 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
4f5982a5 5746 /* ept page table is present? */
81ed33e4 5747 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
4f5982a5 5748
25d92081
YZ		 5749 vcpu->arch.exit_qualification = exit_qualification;
5750
4f5982a5 5751 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5752}
5753
851ba692 5754static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 5755{
f735d4af 5756 int ret;
68f89400
MT		 5757 gpa_t gpa;
5758
5759 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
e32edf4f 5760 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
68c3b4d1 5761 skip_emulated_instruction(vcpu);
931c33b1 5762 trace_kvm_fast_mmio(gpa);
68c3b4d1
MT		 5763 return 1;
5764 }
68f89400 5765
ce88decf 5766 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5767 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5768 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5769 EMULATE_DONE;
f8f55942
XG		 5770
5771 if (unlikely(ret == RET_MMIO_PF_INVALID))
5772 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5773
b37fbea6 5774 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5775 return 1;
5776
5777 /* It is the real ept misconfig */
f735d4af 5778 WARN_ON(1);
68f89400 5779
851ba692
AK		 5780 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5781 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5782
5783 return 0;
5784}
5785
851ba692 5786static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5787{
5788 u32 cpu_based_vm_exec_control;
5789
5790 /* clear pending NMI */
5791 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5792 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5793 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5794 ++vcpu->stat.nmi_window_exits;
3842d135 5795 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5796
5797 return 1;
5798}
5799
80ced186 5800static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5801{
8b3079a5
AK		 5802 struct vcpu_vmx *vmx = to_vmx(vcpu);
5803 enum emulation_result err = EMULATE_DONE;
80ced186 5804 int ret = 1;
49e9d557
AK		 5805 u32 cpu_exec_ctrl;
5806 bool intr_window_requested;
b8405c18 5807 unsigned count = 130;
49e9d557
AK		 5808
5809 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5810 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5811
98eb2f8b 5812 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5813 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5814 return handle_interrupt_window(&vmx->vcpu);
5815
de87dcdd
AK		 5816 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5817 return 1;
5818
991eebf9 5819 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5820
ac0a48c3 5821 if (err == EMULATE_USER_EXIT) {
94452b9e 5822 ++vcpu->stat.mmio_exits;
80ced186
MG		 5823 ret = 0;
5824 goto out;
5825 }
1d5a4d9b 5826
de5f70e0
AK		 5827 if (err != EMULATE_DONE) {
5828 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5829 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5830 vcpu->run->internal.ndata = 0;
6d77dbfc 5831 return 0;
de5f70e0 5832 }
ea953ef0 5833
8d76c49e
GN		 5834 if (vcpu->arch.halt_request) {
5835 vcpu->arch.halt_request = 0;
5cb56059 5836 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN		 5837 goto out;
5838 }
5839
ea953ef0 5840 if (signal_pending(current))
80ced186 5841 goto out;
ea953ef0
MG		 5842 if (need_resched())
5843 schedule();
5844 }
5845
80ced186
MG		 5846out:
5847 return ret;
ea953ef0
MG		 5848}
5849
b4a2d31d
RK		 5850static int __grow_ple_window(int val)
5851{
5852 if (ple_window_grow < 1)
5853 return ple_window;
5854
5855 val = min(val, ple_window_actual_max);
5856
5857 if (ple_window_grow < ple_window)
5858 val *= ple_window_grow;
5859 else
5860 val += ple_window_grow;
5861
5862 return val;
5863}
5864
5865static int __shrink_ple_window(int val, int modifier, int minimum)
5866{
5867 if (modifier < 1)
5868 return ple_window;
5869
5870 if (modifier < ple_window)
5871 val /= modifier;
5872 else
5873 val -= modifier;
5874
5875 return max(val, minimum);
5876}
5877
5878static void grow_ple_window(struct kvm_vcpu *vcpu)
5879{
5880 struct vcpu_vmx *vmx = to_vmx(vcpu);
5881 int old = vmx->ple_window;
5882
5883 vmx->ple_window = __grow_ple_window(old);
5884
5885 if (vmx->ple_window != old)
5886 vmx->ple_window_dirty = true;
7b46268d
RK		 5887
5888 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5889}
5890
5891static void shrink_ple_window(struct kvm_vcpu *vcpu)
5892{
5893 struct vcpu_vmx *vmx = to_vmx(vcpu);
5894 int old = vmx->ple_window;
5895
5896 vmx->ple_window = __shrink_ple_window(old,
5897 ple_window_shrink, ple_window);
5898
5899 if (vmx->ple_window != old)
5900 vmx->ple_window_dirty = true;
7b46268d
RK		 5901
5902 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5903}
5904
5905/*
5906 * ple_window_actual_max is computed to be one grow_ple_window() below
5907 * ple_window_max. (See __grow_ple_window for the reason.)
5908 * This prevents overflows, because ple_window_max is int.
5909 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5910 * this process.
5911 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5912 */
5913static void update_ple_window_actual_max(void)
5914{
5915 ple_window_actual_max =
5916 __shrink_ple_window(max(ple_window_max, ple_window),
5917 ple_window_grow, INT_MIN);
5918}
5919
f2c7648d
TC		 5920static __init int hardware_setup(void)
5921{
34a1cd60
TC		 5922 int r = -ENOMEM, i, msr;
5923
5924 rdmsrl_safe(MSR_EFER, &host_efer);
5925
5926 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
5927 kvm_define_shared_msr(i, vmx_msr_index[i]);
5928
5929 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
5930 if (!vmx_io_bitmap_a)
5931 return r;
5932
5933 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
5934 if (!vmx_io_bitmap_b)
5935 goto out;
5936
5937 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
5938 if (!vmx_msr_bitmap_legacy)
5939 goto out1;
5940
5941 vmx_msr_bitmap_legacy_x2apic =
5942 (unsigned long *)__get_free_page(GFP_KERNEL);
5943 if (!vmx_msr_bitmap_legacy_x2apic)
5944 goto out2;
5945
5946 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
5947 if (!vmx_msr_bitmap_longmode)
5948 goto out3;
5949
5950 vmx_msr_bitmap_longmode_x2apic =
5951 (unsigned long *)__get_free_page(GFP_KERNEL);
5952 if (!vmx_msr_bitmap_longmode_x2apic)
5953 goto out4;
3af18d9c
WV		 5954
5955 if (nested) {
5956 vmx_msr_bitmap_nested =
5957 (unsigned long *)__get_free_page(GFP_KERNEL);
5958 if (!vmx_msr_bitmap_nested)
5959 goto out5;
5960 }
5961
34a1cd60
TC		 5962 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5963 if (!vmx_vmread_bitmap)
3af18d9c 5964 goto out6;
34a1cd60
TC		 5965
5966 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5967 if (!vmx_vmwrite_bitmap)
3af18d9c 5968 goto out7;
34a1cd60
TC		 5969
5970 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
5971 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5972
5973 /*
5974 * Allow direct access to the PC debug port (it is often used for I/O
5975 * delays, but the vmexits simply slow things down).
5976 */
5977 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
5978 clear_bit(0x80, vmx_io_bitmap_a);
5979
5980 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
5981
5982 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
5983 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3af18d9c
WV		 5984 if (nested)
5985 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
34a1cd60 5986
34a1cd60
TC		 5987 if (setup_vmcs_config(&vmcs_config) < 0) {
5988 r = -EIO;
3af18d9c 5989 goto out8;
baa03522 5990 }
f2c7648d
TC		 5991
5992 if (boot_cpu_has(X86_FEATURE_NX))
5993 kvm_enable_efer_bits(EFER_NX);
5994
5995 if (!cpu_has_vmx_vpid())
5996 enable_vpid = 0;
5997 if (!cpu_has_vmx_shadow_vmcs())
5998 enable_shadow_vmcs = 0;
5999 if (enable_shadow_vmcs)
6000 init_vmcs_shadow_fields();
6001
6002 if (!cpu_has_vmx_ept() ||
6003 !cpu_has_vmx_ept_4levels()) {
6004 enable_ept = 0;
6005 enable_unrestricted_guest = 0;
6006 enable_ept_ad_bits = 0;
6007 }
6008
6009 if (!cpu_has_vmx_ept_ad_bits())
6010 enable_ept_ad_bits = 0;
6011
6012 if (!cpu_has_vmx_unrestricted_guest())
6013 enable_unrestricted_guest = 0;
6014
ad15a296 6015 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC		 6016 flexpriority_enabled = 0;
6017
ad15a296
PB		 6018 /*
6019 * set_apic_access_page_addr() is used to reload apic access
6020 * page upon invalidation. No need to do anything if not
6021 * using the APIC_ACCESS_ADDR VMCS field.
6022 */
6023 if (!flexpriority_enabled)
f2c7648d 6024 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC		 6025
6026 if (!cpu_has_vmx_tpr_shadow())
6027 kvm_x86_ops->update_cr8_intercept = NULL;
6028
6029 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6030 kvm_disable_largepages();
6031
6032 if (!cpu_has_vmx_ple())
6033 ple_gap = 0;
6034
6035 if (!cpu_has_vmx_apicv())
6036 enable_apicv = 0;
6037
6038 if (enable_apicv)
6039 kvm_x86_ops->update_cr8_intercept = NULL;
6040 else {
6041 kvm_x86_ops->hwapic_irr_update = NULL;
b4eef9b3 6042 kvm_x86_ops->hwapic_isr_update = NULL;
f2c7648d
TC		 6043 kvm_x86_ops->deliver_posted_interrupt = NULL;
6044 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6045 }
6046
baa03522
TC		 6047 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6048 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6049 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6050 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6051 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6052 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6053 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6054
6055 memcpy(vmx_msr_bitmap_legacy_x2apic,
6056 vmx_msr_bitmap_legacy, PAGE_SIZE);
6057 memcpy(vmx_msr_bitmap_longmode_x2apic,
6058 vmx_msr_bitmap_longmode, PAGE_SIZE);
6059
04bb92e4
WL		 6060 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6061
baa03522
TC		 6062 if (enable_apicv) {
6063 for (msr = 0x800; msr <= 0x8ff; msr++)
6064 vmx_disable_intercept_msr_read_x2apic(msr);
6065
6066 /* According SDM, in x2apic mode, the whole id reg is used.
6067 * But in KVM, it only use the highest eight bits. Need to
6068 * intercept it */
6069 vmx_enable_intercept_msr_read_x2apic(0x802);
6070 /* TMCCT */
6071 vmx_enable_intercept_msr_read_x2apic(0x839);
6072 /* TPR */
6073 vmx_disable_intercept_msr_write_x2apic(0x808);
6074 /* EOI */
6075 vmx_disable_intercept_msr_write_x2apic(0x80b);
6076 /* SELF-IPI */
6077 vmx_disable_intercept_msr_write_x2apic(0x83f);
6078 }
6079
6080 if (enable_ept) {
6081 kvm_mmu_set_mask_ptes(0ull,
6082 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6083 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6084 0ull, VMX_EPT_EXECUTABLE_MASK);
6085 ept_set_mmio_spte_mask();
6086 kvm_enable_tdp();
6087 } else
6088 kvm_disable_tdp();
6089
6090 update_ple_window_actual_max();
6091
843e4330
KH		 6092 /*
6093 * Only enable PML when hardware supports PML feature, and both EPT
6094 * and EPT A/D bit features are enabled -- PML depends on them to work.
6095 */
6096 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6097 enable_pml = 0;
6098
6099 if (!enable_pml) {
6100 kvm_x86_ops->slot_enable_log_dirty = NULL;
6101 kvm_x86_ops->slot_disable_log_dirty = NULL;
6102 kvm_x86_ops->flush_log_dirty = NULL;
6103 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6104 }
6105
f2c7648d 6106 return alloc_kvm_area();
34a1cd60 6107
3af18d9c 6108out8:
34a1cd60 6109 free_page((unsigned long)vmx_vmwrite_bitmap);
3af18d9c 6110out7:
34a1cd60 6111 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6112out6:
6113 if (nested)
6114 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60
TC		 6115out5:
6116 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6117out4:
6118 free_page((unsigned long)vmx_msr_bitmap_longmode);
6119out3:
6120 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6121out2:
6122 free_page((unsigned long)vmx_msr_bitmap_legacy);
6123out1:
6124 free_page((unsigned long)vmx_io_bitmap_b);
6125out:
6126 free_page((unsigned long)vmx_io_bitmap_a);
6127
6128 return r;
f2c7648d
TC		 6129}
6130
6131static __exit void hardware_unsetup(void)
6132{
34a1cd60
TC		 6133 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6134 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6135 free_page((unsigned long)vmx_msr_bitmap_legacy);
6136 free_page((unsigned long)vmx_msr_bitmap_longmode);
6137 free_page((unsigned long)vmx_io_bitmap_b);
6138 free_page((unsigned long)vmx_io_bitmap_a);
6139 free_page((unsigned long)vmx_vmwrite_bitmap);
6140 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6141 if (nested)
6142 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60 6143
f2c7648d
TC		 6144 free_kvm_area();
6145}
6146
4b8d54f9
ZE		 6147/*
6148 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6149 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6150 */
9fb41ba8 6151static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6152{
b4a2d31d
RK		 6153 if (ple_gap)
6154 grow_ple_window(vcpu);
6155
4b8d54f9
ZE		 6156 skip_emulated_instruction(vcpu);
6157 kvm_vcpu_on_spin(vcpu);
6158
6159 return 1;
6160}
6161
87c00572 6162static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6163{
87c00572 6164 skip_emulated_instruction(vcpu);
59708670
SY		 6165 return 1;
6166}
6167
87c00572
GS		 6168static int handle_mwait(struct kvm_vcpu *vcpu)
6169{
6170 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6171 return handle_nop(vcpu);
6172}
6173
5f3d45e7
MD		 6174static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6175{
6176 return 1;
6177}
6178
87c00572
GS		 6179static int handle_monitor(struct kvm_vcpu *vcpu)
6180{
6181 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6182 return handle_nop(vcpu);
6183}
6184
ff2f6fe9
NHE		 6185/*
6186 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6187 * We could reuse a single VMCS for all the L2 guests, but we also want the
6188 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6189 * allows keeping them loaded on the processor, and in the future will allow
6190 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6191 * every entry if they never change.
6192 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6193 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6194 *
6195 * The following functions allocate and free a vmcs02 in this pool.
6196 */
6197
6198/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6199static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6200{
6201 struct vmcs02_list *item;
6202 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6203 if (item->vmptr == vmx->nested.current_vmptr) {
6204 list_move(&item->list, &vmx->nested.vmcs02_pool);
6205 return &item->vmcs02;
6206 }
6207
6208 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6209 /* Recycle the least recently used VMCS. */
6210 item = list_entry(vmx->nested.vmcs02_pool.prev,
6211 struct vmcs02_list, list);
6212 item->vmptr = vmx->nested.current_vmptr;
6213 list_move(&item->list, &vmx->nested.vmcs02_pool);
6214 return &item->vmcs02;
6215 }
6216
6217 /* Create a new VMCS */
0fa24ce3 6218 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 6219 if (!item)
6220 return NULL;
6221 item->vmcs02.vmcs = alloc_vmcs();
6222 if (!item->vmcs02.vmcs) {
6223 kfree(item);
6224 return NULL;
6225 }
6226 loaded_vmcs_init(&item->vmcs02);
6227 item->vmptr = vmx->nested.current_vmptr;
6228 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6229 vmx->nested.vmcs02_num++;
6230 return &item->vmcs02;
6231}
6232
6233/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6234static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6235{
6236 struct vmcs02_list *item;
6237 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6238 if (item->vmptr == vmptr) {
6239 free_loaded_vmcs(&item->vmcs02);
6240 list_del(&item->list);
6241 kfree(item);
6242 vmx->nested.vmcs02_num--;
6243 return;
6244 }
6245}
6246
6247/*
6248 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6249 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6250 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6251 */
6252static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6253{
6254 struct vmcs02_list *item, *n;
4fa7734c
PB		 6255
6256 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6257 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6258 /*
6259 * Something will leak if the above WARN triggers. Better than
6260 * a use-after-free.
6261 */
6262 if (vmx->loaded_vmcs == &item->vmcs02)
6263 continue;
6264
6265 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6266 list_del(&item->list);
6267 kfree(item);
4fa7734c 6268 vmx->nested.vmcs02_num--;
ff2f6fe9 6269 }
ff2f6fe9
NHE		 6270}
6271
0658fbaa
ACL		 6272/*
6273 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6274 * set the success or error code of an emulated VMX instruction, as specified
6275 * by Vol 2B, VMX Instruction Reference, "Conventions".
6276 */
6277static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6278{
6279 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6280 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6281 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6282}
6283
6284static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6285{
6286 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6287 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6288 X86_EFLAGS_SF | X86_EFLAGS_OF))
6289 | X86_EFLAGS_CF);
6290}
6291
145c28dd 6292static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6293 u32 vm_instruction_error)
6294{
6295 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6296 /*
6297 * failValid writes the error number to the current VMCS, which
6298 * can't be done there isn't a current VMCS.
6299 */
6300 nested_vmx_failInvalid(vcpu);
6301 return;
6302 }
6303 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6304 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6305 X86_EFLAGS_SF | X86_EFLAGS_OF))
6306 | X86_EFLAGS_ZF);
6307 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6308 /*
6309 * We don't need to force a shadow sync because
6310 * VM_INSTRUCTION_ERROR is not shadowed
6311 */
6312}
145c28dd 6313
ff651cb6
WV		 6314static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6315{
6316 /* TODO: not to reset guest simply here. */
6317 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6318 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6319}
6320
f4124500
JK		 6321static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6322{
6323 struct vcpu_vmx *vmx =
6324 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6325
6326 vmx->nested.preemption_timer_expired = true;
6327 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6328 kvm_vcpu_kick(&vmx->vcpu);
6329
6330 return HRTIMER_NORESTART;
6331}
6332
19677e32
BD		 6333/*
6334 * Decode the memory-address operand of a vmx instruction, as recorded on an
6335 * exit caused by such an instruction (run by a guest hypervisor).
6336 * On success, returns 0. When the operand is invalid, returns 1 and throws
6337 * #UD or #GP.
6338 */
6339static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6340 unsigned long exit_qualification,
f9eb4af6 6341 u32 vmx_instruction_info, bool wr, gva_t *ret)
19677e32 6342{
f9eb4af6
EK		 6343 gva_t off;
6344 bool exn;
6345 struct kvm_segment s;
6346
19677e32
BD		 6347 /*
6348 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6349 * Execution", on an exit, vmx_instruction_info holds most of the
6350 * addressing components of the operand. Only the displacement part
6351 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6352 * For how an actual address is calculated from all these components,
6353 * refer to Vol. 1, "Operand Addressing".
6354 */
6355 int scaling = vmx_instruction_info & 3;
6356 int addr_size = (vmx_instruction_info >> 7) & 7;
6357 bool is_reg = vmx_instruction_info & (1u << 10);
6358 int seg_reg = (vmx_instruction_info >> 15) & 7;
6359 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6360 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6361 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6362 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6363
6364 if (is_reg) {
6365 kvm_queue_exception(vcpu, UD_VECTOR);
6366 return 1;
6367 }
6368
6369 /* Addr = segment_base + offset */
6370 /* offset = base + [index * scale] + displacement */
f9eb4af6 6371 off = exit_qualification; /* holds the displacement */
19677e32 6372 if (base_is_valid)
f9eb4af6 6373 off += kvm_register_read(vcpu, base_reg);
19677e32 6374 if (index_is_valid)
f9eb4af6
EK		 6375 off += kvm_register_read(vcpu, index_reg)<<scaling;
6376 vmx_get_segment(vcpu, &s, seg_reg);
6377 *ret = s.base + off;
19677e32
BD		 6378
6379 if (addr_size == 1) /* 32 bit */
6380 *ret &= 0xffffffff;
6381
f9eb4af6
EK		 6382 /* Checks for #GP/#SS exceptions. */
6383 exn = false;
6384 if (is_protmode(vcpu)) {
6385 /* Protected mode: apply checks for segment validity in the
6386 * following order:
6387 * - segment type check (#GP(0) may be thrown)
6388 * - usability check (#GP(0)/#SS(0))
6389 * - limit check (#GP(0)/#SS(0))
6390 */
6391 if (wr)
6392 /* #GP(0) if the destination operand is located in a
6393 * read-only data segment or any code segment.
6394 */
6395 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6396 else
6397 /* #GP(0) if the source operand is located in an
6398 * execute-only code segment
6399 */
6400 exn = ((s.type & 0xa) == 8);
6401 }
6402 if (exn) {
6403 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6404 return 1;
6405 }
6406 if (is_long_mode(vcpu)) {
6407 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6408 * non-canonical form. This is an only check for long mode.
6409 */
6410 exn = is_noncanonical_address(*ret);
6411 } else if (is_protmode(vcpu)) {
6412 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6413 */
6414 exn = (s.unusable != 0);
6415 /* Protected mode: #GP(0)/#SS(0) if the memory
6416 * operand is outside the segment limit.
6417 */
6418 exn = exn || (off + sizeof(u64) > s.limit);
6419 }
6420 if (exn) {
6421 kvm_queue_exception_e(vcpu,
6422 seg_reg == VCPU_SREG_SS ?
6423 SS_VECTOR : GP_VECTOR,
6424 0);
6425 return 1;
6426 }
6427
19677e32
BD		 6428 return 0;
6429}
6430
3573e22c
BD		 6431/*
6432 * This function performs the various checks including
6433 * - if it's 4KB aligned
6434 * - No bits beyond the physical address width are set
6435 * - Returns 0 on success or else 1
4291b588 6436 * (Intel SDM Section 30.3)
3573e22c 6437 */
4291b588
BD		 6438static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6439 gpa_t *vmpointer)
3573e22c
BD		 6440{
6441 gva_t gva;
6442 gpa_t vmptr;
6443 struct x86_exception e;
6444 struct page *page;
6445 struct vcpu_vmx *vmx = to_vmx(vcpu);
6446 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6447
6448 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 6449 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
3573e22c
BD		 6450 return 1;
6451
6452 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6453 sizeof(vmptr), &e)) {
6454 kvm_inject_page_fault(vcpu, &e);
6455 return 1;
6456 }
6457
6458 switch (exit_reason) {
6459 case EXIT_REASON_VMON:
6460 /*
6461 * SDM 3: 24.11.5
6462 * The first 4 bytes of VMXON region contain the supported
6463 * VMCS revision identifier
6464 *
6465 * Note - IA32_VMX_BASIC[48] will never be 1
6466 * for the nested case;
6467 * which replaces physical address width with 32
6468 *
6469 */
bc39c4db 6470 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6471 nested_vmx_failInvalid(vcpu);
6472 skip_emulated_instruction(vcpu);
6473 return 1;
6474 }
6475
6476 page = nested_get_page(vcpu, vmptr);
6477 if (page == NULL ||
6478 *(u32 *)kmap(page) != VMCS12_REVISION) {
6479 nested_vmx_failInvalid(vcpu);
6480 kunmap(page);
6481 skip_emulated_instruction(vcpu);
6482 return 1;
6483 }
6484 kunmap(page);
6485 vmx->nested.vmxon_ptr = vmptr;
6486 break;
4291b588 6487 case EXIT_REASON_VMCLEAR:
bc39c4db 6488 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6489 nested_vmx_failValid(vcpu,
6490 VMXERR_VMCLEAR_INVALID_ADDRESS);
6491 skip_emulated_instruction(vcpu);
6492 return 1;
6493 }
6494
6495 if (vmptr == vmx->nested.vmxon_ptr) {
6496 nested_vmx_failValid(vcpu,
6497 VMXERR_VMCLEAR_VMXON_POINTER);
6498 skip_emulated_instruction(vcpu);
6499 return 1;
6500 }
6501 break;
6502 case EXIT_REASON_VMPTRLD:
bc39c4db 6503 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6504 nested_vmx_failValid(vcpu,
6505 VMXERR_VMPTRLD_INVALID_ADDRESS);
6506 skip_emulated_instruction(vcpu);
6507 return 1;
6508 }
3573e22c 6509
4291b588
BD		 6510 if (vmptr == vmx->nested.vmxon_ptr) {
6511 nested_vmx_failValid(vcpu,
6512 VMXERR_VMCLEAR_VMXON_POINTER);
6513 skip_emulated_instruction(vcpu);
6514 return 1;
6515 }
6516 break;
3573e22c
BD		 6517 default:
6518 return 1; /* shouldn't happen */
6519 }
6520
4291b588
BD		 6521 if (vmpointer)
6522 *vmpointer = vmptr;
3573e22c
BD		 6523 return 0;
6524}
6525
ec378aee
NHE		 6526/*
6527 * Emulate the VMXON instruction.
6528 * Currently, we just remember that VMX is active, and do not save or even
6529 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6530 * do not currently need to store anything in that guest-allocated memory
6531 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6532 * argument is different from the VMXON pointer (which the spec says they do).
6533 */
6534static int handle_vmon(struct kvm_vcpu *vcpu)
6535{
6536 struct kvm_segment cs;
6537 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6538 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6539 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6540 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6541
6542 /* The Intel VMX Instruction Reference lists a bunch of bits that
6543 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6544 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6545 * Otherwise, we should fail with #UD. We test these now:
6546 */
6547 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6548 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6549 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6550 kvm_queue_exception(vcpu, UD_VECTOR);
6551 return 1;
6552 }
6553
6554 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6555 if (is_long_mode(vcpu) && !cs.l) {
6556 kvm_queue_exception(vcpu, UD_VECTOR);
6557 return 1;
6558 }
6559
6560 if (vmx_get_cpl(vcpu)) {
6561 kvm_inject_gp(vcpu, 0);
6562 return 1;
6563 }
3573e22c 6564
4291b588 6565 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6566 return 1;
6567
145c28dd
AG		 6568 if (vmx->nested.vmxon) {
6569 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6570 skip_emulated_instruction(vcpu);
6571 return 1;
6572 }
b3897a49
NHE		 6573
6574 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6575 != VMXON_NEEDED_FEATURES) {
6576 kvm_inject_gp(vcpu, 0);
6577 return 1;
6578 }
6579
8de48833
AG		 6580 if (enable_shadow_vmcs) {
6581 shadow_vmcs = alloc_vmcs();
6582 if (!shadow_vmcs)
6583 return -ENOMEM;
6584 /* mark vmcs as shadow */
6585 shadow_vmcs->revision_id |= (1u << 31);
6586 /* init shadow vmcs */
6587 vmcs_clear(shadow_vmcs);
6588 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6589 }
ec378aee 6590
ff2f6fe9
NHE		 6591 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6592 vmx->nested.vmcs02_num = 0;
6593
f4124500
JK		 6594 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6595 HRTIMER_MODE_REL);
6596 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6597
ec378aee
NHE		 6598 vmx->nested.vmxon = true;
6599
6600 skip_emulated_instruction(vcpu);
a25eb114 6601 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6602 return 1;
6603}
6604
6605/*
6606 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6607 * for running VMX instructions (except VMXON, whose prerequisites are
6608 * slightly different). It also specifies what exception to inject otherwise.
6609 */
6610static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6611{
6612 struct kvm_segment cs;
6613 struct vcpu_vmx *vmx = to_vmx(vcpu);
6614
6615 if (!vmx->nested.vmxon) {
6616 kvm_queue_exception(vcpu, UD_VECTOR);
6617 return 0;
6618 }
6619
6620 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6621 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6622 (is_long_mode(vcpu) && !cs.l)) {
6623 kvm_queue_exception(vcpu, UD_VECTOR);
6624 return 0;
6625 }
6626
6627 if (vmx_get_cpl(vcpu)) {
6628 kvm_inject_gp(vcpu, 0);
6629 return 0;
6630 }
6631
6632 return 1;
6633}
6634
e7953d7f
AG		 6635static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6636{
9a2a05b9
PB		 6637 if (vmx->nested.current_vmptr == -1ull)
6638 return;
6639
6640 /* current_vmptr and current_vmcs12 are always set/reset together */
6641 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6642 return;
6643
012f83cb 6644 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6645 /* copy to memory all shadowed fields in case
6646 they were modified */
6647 copy_shadow_to_vmcs12(vmx);
6648 vmx->nested.sync_shadow_vmcs = false;
7ec36296
XG		 6649 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6650 SECONDARY_EXEC_SHADOW_VMCS);
9a2a05b9 6651 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6652 }
705699a1 6653 vmx->nested.posted_intr_nv = -1;
e7953d7f
AG		 6654 kunmap(vmx->nested.current_vmcs12_page);
6655 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6656 vmx->nested.current_vmptr = -1ull;
6657 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6658}
6659
ec378aee
NHE		 6660/*
6661 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6662 * just stops using VMX.
6663 */
6664static void free_nested(struct vcpu_vmx *vmx)
6665{
6666 if (!vmx->nested.vmxon)
6667 return;
9a2a05b9 6668
ec378aee 6669 vmx->nested.vmxon = false;
9a2a05b9 6670 nested_release_vmcs12(vmx);
e7953d7f
AG		 6671 if (enable_shadow_vmcs)
6672 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6673 /* Unpin physical memory we referred to in current vmcs02 */
6674 if (vmx->nested.apic_access_page) {
6675 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6676 vmx->nested.apic_access_page = NULL;
fe3ef05c 6677 }
a7c0b07d
WL		 6678 if (vmx->nested.virtual_apic_page) {
6679 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6680 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6681 }
705699a1
WV		 6682 if (vmx->nested.pi_desc_page) {
6683 kunmap(vmx->nested.pi_desc_page);
6684 nested_release_page(vmx->nested.pi_desc_page);
6685 vmx->nested.pi_desc_page = NULL;
6686 vmx->nested.pi_desc = NULL;
6687 }
ff2f6fe9
NHE		 6688
6689 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6690}
6691
6692/* Emulate the VMXOFF instruction */
6693static int handle_vmoff(struct kvm_vcpu *vcpu)
6694{
6695 if (!nested_vmx_check_permission(vcpu))
6696 return 1;
6697 free_nested(to_vmx(vcpu));
6698 skip_emulated_instruction(vcpu);
a25eb114 6699 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6700 return 1;
6701}
6702
27d6c865
NHE		 6703/* Emulate the VMCLEAR instruction */
6704static int handle_vmclear(struct kvm_vcpu *vcpu)
6705{
6706 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6707 gpa_t vmptr;
6708 struct vmcs12 *vmcs12;
6709 struct page *page;
27d6c865
NHE		 6710
6711 if (!nested_vmx_check_permission(vcpu))
6712 return 1;
6713
4291b588 6714 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6715 return 1;
27d6c865 6716
9a2a05b9 6717 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6718 nested_release_vmcs12(vmx);
27d6c865
NHE		 6719
6720 page = nested_get_page(vcpu, vmptr);
6721 if (page == NULL) {
6722 /*
6723 * For accurate processor emulation, VMCLEAR beyond available
6724 * physical memory should do nothing at all. However, it is
6725 * possible that a nested vmx bug, not a guest hypervisor bug,
6726 * resulted in this case, so let's shut down before doing any
6727 * more damage:
6728 */
6729 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6730 return 1;
6731 }
6732 vmcs12 = kmap(page);
6733 vmcs12->launch_state = 0;
6734 kunmap(page);
6735 nested_release_page(page);
6736
6737 nested_free_vmcs02(vmx, vmptr);
6738
6739 skip_emulated_instruction(vcpu);
6740 nested_vmx_succeed(vcpu);
6741 return 1;
6742}
6743
cd232ad0
NHE		 6744static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6745
6746/* Emulate the VMLAUNCH instruction */
6747static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6748{
6749 return nested_vmx_run(vcpu, true);
6750}
6751
6752/* Emulate the VMRESUME instruction */
6753static int handle_vmresume(struct kvm_vcpu *vcpu)
6754{
6755
6756 return nested_vmx_run(vcpu, false);
6757}
6758
49f705c5
NHE		 6759enum vmcs_field_type {
6760 VMCS_FIELD_TYPE_U16 = 0,
6761 VMCS_FIELD_TYPE_U64 = 1,
6762 VMCS_FIELD_TYPE_U32 = 2,
6763 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6764};
6765
6766static inline int vmcs_field_type(unsigned long field)
6767{
6768 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6769 return VMCS_FIELD_TYPE_U32;
6770 return (field >> 13) & 0x3 ;
6771}
6772
6773static inline int vmcs_field_readonly(unsigned long field)
6774{
6775 return (((field >> 10) & 0x3) == 1);
6776}
6777
6778/*
6779 * Read a vmcs12 field. Since these can have varying lengths and we return
6780 * one type, we chose the biggest type (u64) and zero-extend the return value
6781 * to that size. Note that the caller, handle_vmread, might need to use only
6782 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6783 * 64-bit fields are to be returned).
6784 */
a2ae9df7
PB		 6785static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6786 unsigned long field, u64 *ret)
49f705c5
NHE		 6787{
6788 short offset = vmcs_field_to_offset(field);
6789 char *p;
6790
6791 if (offset < 0)
a2ae9df7 6792 return offset;
49f705c5
NHE		 6793
6794 p = ((char *)(get_vmcs12(vcpu))) + offset;
6795
6796 switch (vmcs_field_type(field)) {
6797 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6798 *ret = *((natural_width *)p);
a2ae9df7 6799 return 0;
49f705c5
NHE		 6800 case VMCS_FIELD_TYPE_U16:
6801 *ret = *((u16 *)p);
a2ae9df7 6802 return 0;
49f705c5
NHE		 6803 case VMCS_FIELD_TYPE_U32:
6804 *ret = *((u32 *)p);
a2ae9df7 6805 return 0;
49f705c5
NHE		 6806 case VMCS_FIELD_TYPE_U64:
6807 *ret = *((u64 *)p);
a2ae9df7 6808 return 0;
49f705c5 6809 default:
a2ae9df7
PB		 6810 WARN_ON(1);
6811 return -ENOENT;
49f705c5
NHE		 6812 }
6813}
6814
20b97fea 6815
a2ae9df7
PB		 6816static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6817 unsigned long field, u64 field_value){
20b97fea
AG		 6818 short offset = vmcs_field_to_offset(field);
6819 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6820 if (offset < 0)
a2ae9df7 6821 return offset;
20b97fea
AG		 6822
6823 switch (vmcs_field_type(field)) {
6824 case VMCS_FIELD_TYPE_U16:
6825 *(u16 *)p = field_value;
a2ae9df7 6826 return 0;
20b97fea
AG		 6827 case VMCS_FIELD_TYPE_U32:
6828 *(u32 *)p = field_value;
a2ae9df7 6829 return 0;
20b97fea
AG		 6830 case VMCS_FIELD_TYPE_U64:
6831 *(u64 *)p = field_value;
a2ae9df7 6832 return 0;
20b97fea
AG		 6833 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6834 *(natural_width *)p = field_value;
a2ae9df7 6835 return 0;
20b97fea 6836 default:
a2ae9df7
PB		 6837 WARN_ON(1);
6838 return -ENOENT;
20b97fea
AG		 6839 }
6840
6841}
6842
16f5b903
AG		 6843static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6844{
6845 int i;
6846 unsigned long field;
6847 u64 field_value;
6848 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6849 const unsigned long *fields = shadow_read_write_fields;
6850 const int num_fields = max_shadow_read_write_fields;
16f5b903 6851
282da870
JK		 6852 preempt_disable();
6853
16f5b903
AG		 6854 vmcs_load(shadow_vmcs);
6855
6856 for (i = 0; i < num_fields; i++) {
6857 field = fields[i];
6858 switch (vmcs_field_type(field)) {
6859 case VMCS_FIELD_TYPE_U16:
6860 field_value = vmcs_read16(field);
6861 break;
6862 case VMCS_FIELD_TYPE_U32:
6863 field_value = vmcs_read32(field);
6864 break;
6865 case VMCS_FIELD_TYPE_U64:
6866 field_value = vmcs_read64(field);
6867 break;
6868 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6869 field_value = vmcs_readl(field);
6870 break;
a2ae9df7
PB		 6871 default:
6872 WARN_ON(1);
6873 continue;
16f5b903
AG		 6874 }
6875 vmcs12_write_any(&vmx->vcpu, field, field_value);
6876 }
6877
6878 vmcs_clear(shadow_vmcs);
6879 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 6880
6881 preempt_enable();
16f5b903
AG		 6882}
6883
c3114420
AG		 6884static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6885{
c2bae893
MK		 6886 const unsigned long *fields[] = {
6887 shadow_read_write_fields,
6888 shadow_read_only_fields
c3114420 6889 };
c2bae893 6890 const int max_fields[] = {
c3114420
AG		 6891 max_shadow_read_write_fields,
6892 max_shadow_read_only_fields
6893 };
6894 int i, q;
6895 unsigned long field;
6896 u64 field_value = 0;
6897 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6898
6899 vmcs_load(shadow_vmcs);
6900
c2bae893 6901 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6902 for (i = 0; i < max_fields[q]; i++) {
6903 field = fields[q][i];
6904 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6905
6906 switch (vmcs_field_type(field)) {
6907 case VMCS_FIELD_TYPE_U16:
6908 vmcs_write16(field, (u16)field_value);
6909 break;
6910 case VMCS_FIELD_TYPE_U32:
6911 vmcs_write32(field, (u32)field_value);
6912 break;
6913 case VMCS_FIELD_TYPE_U64:
6914 vmcs_write64(field, (u64)field_value);
6915 break;
6916 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6917 vmcs_writel(field, (long)field_value);
6918 break;
a2ae9df7
PB		 6919 default:
6920 WARN_ON(1);
6921 break;
c3114420
AG		 6922 }
6923 }
6924 }
6925
6926 vmcs_clear(shadow_vmcs);
6927 vmcs_load(vmx->loaded_vmcs->vmcs);
6928}
6929
49f705c5
NHE		 6930/*
6931 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6932 * used before) all generate the same failure when it is missing.
6933 */
6934static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6935{
6936 struct vcpu_vmx *vmx = to_vmx(vcpu);
6937 if (vmx->nested.current_vmptr == -1ull) {
6938 nested_vmx_failInvalid(vcpu);
6939 skip_emulated_instruction(vcpu);
6940 return 0;
6941 }
6942 return 1;
6943}
6944
6945static int handle_vmread(struct kvm_vcpu *vcpu)
6946{
6947 unsigned long field;
6948 u64 field_value;
6949 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6950 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6951 gva_t gva = 0;
6952
6953 if (!nested_vmx_check_permission(vcpu) ||
6954 !nested_vmx_check_vmcs12(vcpu))
6955 return 1;
6956
6957 /* Decode instruction info and find the field to read */
27e6fb5d 6958 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 6959 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 6960 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5
NHE		 6961 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6962 skip_emulated_instruction(vcpu);
6963 return 1;
6964 }
6965 /*
6966 * Now copy part of this value to register or memory, as requested.
6967 * Note that the number of bits actually copied is 32 or 64 depending
6968 * on the guest's mode (32 or 64 bit), not on the given field's length.
6969 */
6970 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6971 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6972 field_value);
6973 } else {
6974 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 6975 vmx_instruction_info, true, &gva))
49f705c5
NHE		 6976 return 1;
6977 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6978 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6979 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6980 }
6981
6982 nested_vmx_succeed(vcpu);
6983 skip_emulated_instruction(vcpu);
6984 return 1;
6985}
6986
6987
6988static int handle_vmwrite(struct kvm_vcpu *vcpu)
6989{
6990 unsigned long field;
6991 gva_t gva;
6992 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6993 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6994 /* The value to write might be 32 or 64 bits, depending on L1's long
6995 * mode, and eventually we need to write that into a field of several
6996 * possible lengths. The code below first zero-extends the value to 64
6997 * bit (field_value), and then copies only the approriate number of
6998 * bits into the vmcs12 field.
6999 */
7000 u64 field_value = 0;
7001 struct x86_exception e;
7002
7003 if (!nested_vmx_check_permission(vcpu) ||
7004 !nested_vmx_check_vmcs12(vcpu))
7005 return 1;
7006
7007 if (vmx_instruction_info & (1u << 10))
27e6fb5d 7008 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 7009 (((vmx_instruction_info) >> 3) & 0xf));
7010 else {
7011 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7012 vmx_instruction_info, false, &gva))
49f705c5
NHE		 7013 return 1;
7014 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 7015 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 7016 kvm_inject_page_fault(vcpu, &e);
7017 return 1;
7018 }
7019 }
7020
7021
27e6fb5d 7022 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 7023 if (vmcs_field_readonly(field)) {
7024 nested_vmx_failValid(vcpu,
7025 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7026 skip_emulated_instruction(vcpu);
7027 return 1;
7028 }
7029
a2ae9df7 7030 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5
NHE		 7031 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7032 skip_emulated_instruction(vcpu);
7033 return 1;
7034 }
7035
7036 nested_vmx_succeed(vcpu);
7037 skip_emulated_instruction(vcpu);
7038 return 1;
7039}
7040
63846663
NHE		 7041/* Emulate the VMPTRLD instruction */
7042static int handle_vmptrld(struct kvm_vcpu *vcpu)
7043{
7044 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 7045 gpa_t vmptr;
63846663
NHE		 7046
7047 if (!nested_vmx_check_permission(vcpu))
7048 return 1;
7049
4291b588 7050 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 7051 return 1;
63846663
NHE		 7052
7053 if (vmx->nested.current_vmptr != vmptr) {
7054 struct vmcs12 *new_vmcs12;
7055 struct page *page;
7056 page = nested_get_page(vcpu, vmptr);
7057 if (page == NULL) {
7058 nested_vmx_failInvalid(vcpu);
7059 skip_emulated_instruction(vcpu);
7060 return 1;
7061 }
7062 new_vmcs12 = kmap(page);
7063 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7064 kunmap(page);
7065 nested_release_page_clean(page);
7066 nested_vmx_failValid(vcpu,
7067 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7068 skip_emulated_instruction(vcpu);
7069 return 1;
7070 }
63846663 7071
9a2a05b9 7072 nested_release_vmcs12(vmx);
63846663
NHE		 7073 vmx->nested.current_vmptr = vmptr;
7074 vmx->nested.current_vmcs12 = new_vmcs12;
7075 vmx->nested.current_vmcs12_page = page;
012f83cb 7076 if (enable_shadow_vmcs) {
7ec36296
XG		 7077 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7078 SECONDARY_EXEC_SHADOW_VMCS);
8a1b9dd0
AG		 7079 vmcs_write64(VMCS_LINK_POINTER,
7080 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 7081 vmx->nested.sync_shadow_vmcs = true;
7082 }
63846663
NHE		 7083 }
7084
7085 nested_vmx_succeed(vcpu);
7086 skip_emulated_instruction(vcpu);
7087 return 1;
7088}
7089
6a4d7550
NHE		 7090/* Emulate the VMPTRST instruction */
7091static int handle_vmptrst(struct kvm_vcpu *vcpu)
7092{
7093 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7094 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7095 gva_t vmcs_gva;
7096 struct x86_exception e;
7097
7098 if (!nested_vmx_check_permission(vcpu))
7099 return 1;
7100
7101 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7102 vmx_instruction_info, true, &vmcs_gva))
6a4d7550
NHE		 7103 return 1;
7104 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7105 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7106 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7107 sizeof(u64), &e)) {
7108 kvm_inject_page_fault(vcpu, &e);
7109 return 1;
7110 }
7111 nested_vmx_succeed(vcpu);
7112 skip_emulated_instruction(vcpu);
7113 return 1;
7114}
7115
bfd0a56b
NHE		 7116/* Emulate the INVEPT instruction */
7117static int handle_invept(struct kvm_vcpu *vcpu)
7118{
b9c237bb 7119 struct vcpu_vmx *vmx = to_vmx(vcpu);
bfd0a56b
NHE		 7120 u32 vmx_instruction_info, types;
7121 unsigned long type;
7122 gva_t gva;
7123 struct x86_exception e;
7124 struct {
7125 u64 eptp, gpa;
7126 } operand;
bfd0a56b 7127
b9c237bb
WV		 7128 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7129 SECONDARY_EXEC_ENABLE_EPT) ||
7130 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
bfd0a56b
NHE		 7131 kvm_queue_exception(vcpu, UD_VECTOR);
7132 return 1;
7133 }
7134
7135 if (!nested_vmx_check_permission(vcpu))
7136 return 1;
7137
7138 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7139 kvm_queue_exception(vcpu, UD_VECTOR);
7140 return 1;
7141 }
7142
7143 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7144 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b 7145
b9c237bb 7146 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
bfd0a56b
NHE		 7147
7148 if (!(types & (1UL << type))) {
7149 nested_vmx_failValid(vcpu,
7150 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7151 return 1;
7152 }
7153
7154 /* According to the Intel VMX instruction reference, the memory
7155 * operand is read even if it isn't needed (e.g., for type==global)
7156 */
7157 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 7158 vmx_instruction_info, false, &gva))
bfd0a56b
NHE		 7159 return 1;
7160 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7161 sizeof(operand), &e)) {
7162 kvm_inject_page_fault(vcpu, &e);
7163 return 1;
7164 }
7165
7166 switch (type) {
bfd0a56b
NHE		 7167 case VMX_EPT_EXTENT_GLOBAL:
7168 kvm_mmu_sync_roots(vcpu);
77c3913b 7169 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 7170 nested_vmx_succeed(vcpu);
7171 break;
7172 default:
4b855078 7173 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 7174 BUG_ON(1);
7175 break;
7176 }
7177
7178 skip_emulated_instruction(vcpu);
7179 return 1;
7180}
7181
a642fc30
PM		 7182static int handle_invvpid(struct kvm_vcpu *vcpu)
7183{
7184 kvm_queue_exception(vcpu, UD_VECTOR);
7185 return 1;
7186}
7187
843e4330
KH		 7188static int handle_pml_full(struct kvm_vcpu *vcpu)
7189{
7190 unsigned long exit_qualification;
7191
7192 trace_kvm_pml_full(vcpu->vcpu_id);
7193
7194 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7195
7196 /*
7197 * PML buffer FULL happened while executing iret from NMI,
7198 * "blocked by NMI" bit has to be set before next VM entry.
7199 */
7200 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7201 cpu_has_virtual_nmis() &&
7202 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7203 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7204 GUEST_INTR_STATE_NMI);
7205
7206 /*
7207 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7208 * here.., and there's no userspace involvement needed for PML.
7209 */
7210 return 1;
7211}
7212
8b3e34e4
XG		 7213static int handle_pcommit(struct kvm_vcpu *vcpu)
7214{
7215 /* we never catch pcommit instruct for L1 guest. */
7216 WARN_ON(1);
7217 return 1;
7218}
7219
6aa8b732
AK		 7220/*
7221 * The exit handlers return 1 if the exit was handled fully and guest execution
7222 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7223 * to be done to userspace and return 0.
7224 */
772e0318 7225static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 7226 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7227 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7228 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7229 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7230 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 7231 [EXIT_REASON_CR_ACCESS] = handle_cr,
7232 [EXIT_REASON_DR_ACCESS] = handle_dr,
7233 [EXIT_REASON_CPUID] = handle_cpuid,
7234 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7235 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7236 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7237 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7238 [EXIT_REASON_INVD] = handle_invd,
a7052897 7239 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7240 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7241 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7242 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7243 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7244 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7245 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7246 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7247 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7248 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 7249 [EXIT_REASON_VMOFF] = handle_vmoff,
7250 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 7251 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7252 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7253 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7254 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7255 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7256 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7257 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7258 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 7259 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7260 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7261 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572 7262 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5f3d45e7 7263 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
87c00572 7264 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7265 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7266 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL		 7267 [EXIT_REASON_XSAVES] = handle_xsaves,
7268 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7269 [EXIT_REASON_PML_FULL] = handle_pml_full,
8b3e34e4 7270 [EXIT_REASON_PCOMMIT] = handle_pcommit,
6aa8b732
AK		 7271};
7272
7273static const int kvm_vmx_max_exit_handlers =
50a3485c 7274 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7275
908a7bdd
JK		 7276static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7277 struct vmcs12 *vmcs12)
7278{
7279 unsigned long exit_qualification;
7280 gpa_t bitmap, last_bitmap;
7281 unsigned int port;
7282 int size;
7283 u8 b;
7284
908a7bdd 7285 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7286 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 7287
7288 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7289
7290 port = exit_qualification >> 16;
7291 size = (exit_qualification & 7) + 1;
7292
7293 last_bitmap = (gpa_t)-1;
7294 b = -1;
7295
7296 while (size > 0) {
7297 if (port < 0x8000)
7298 bitmap = vmcs12->io_bitmap_a;
7299 else if (port < 0x10000)
7300 bitmap = vmcs12->io_bitmap_b;
7301 else
1d804d07 7302 return true;
908a7bdd
JK		 7303 bitmap += (port & 0x7fff) / 8;
7304
7305 if (last_bitmap != bitmap)
54bf36aa 7306 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
1d804d07 7307 return true;
908a7bdd 7308 if (b & (1 << (port & 7)))
1d804d07 7309 return true;
908a7bdd
JK		 7310
7311 port++;
7312 size--;
7313 last_bitmap = bitmap;
7314 }
7315
1d804d07 7316 return false;
908a7bdd
JK		 7317}
7318
644d711a
NHE		 7319/*
7320 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7321 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7322 * disinterest in the current event (read or write a specific MSR) by using an
7323 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7324 */
7325static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7326 struct vmcs12 *vmcs12, u32 exit_reason)
7327{
7328 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7329 gpa_t bitmap;
7330
cbd29cb6 7331 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
1d804d07 7332 return true;
644d711a
NHE		 7333
7334 /*
7335 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7336 * for the four combinations of read/write and low/high MSR numbers.
7337 * First we need to figure out which of the four to use:
7338 */
7339 bitmap = vmcs12->msr_bitmap;
7340 if (exit_reason == EXIT_REASON_MSR_WRITE)
7341 bitmap += 2048;
7342 if (msr_index >= 0xc0000000) {
7343 msr_index -= 0xc0000000;
7344 bitmap += 1024;
7345 }
7346
7347 /* Then read the msr_index'th bit from this bitmap: */
7348 if (msr_index < 1024*8) {
7349 unsigned char b;
54bf36aa 7350 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
1d804d07 7351 return true;
644d711a
NHE		 7352 return 1 & (b >> (msr_index & 7));
7353 } else
1d804d07 7354 return true; /* let L1 handle the wrong parameter */
644d711a
NHE		 7355}
7356
7357/*
7358 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7359 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7360 * intercept (via guest_host_mask etc.) the current event.
7361 */
7362static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7363 struct vmcs12 *vmcs12)
7364{
7365 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7366 int cr = exit_qualification & 15;
7367 int reg = (exit_qualification >> 8) & 15;
1e32c079 7368 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 7369
7370 switch ((exit_qualification >> 4) & 3) {
7371 case 0: /* mov to cr */
7372 switch (cr) {
7373 case 0:
7374 if (vmcs12->cr0_guest_host_mask &
7375 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7376 return true;
644d711a
NHE		 7377 break;
7378 case 3:
7379 if ((vmcs12->cr3_target_count >= 1 &&
7380 vmcs12->cr3_target_value0 == val) ||
7381 (vmcs12->cr3_target_count >= 2 &&
7382 vmcs12->cr3_target_value1 == val) ||
7383 (vmcs12->cr3_target_count >= 3 &&
7384 vmcs12->cr3_target_value2 == val) ||
7385 (vmcs12->cr3_target_count >= 4 &&
7386 vmcs12->cr3_target_value3 == val))
1d804d07 7387 return false;
644d711a 7388 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
1d804d07 7389 return true;
644d711a
NHE		 7390 break;
7391 case 4:
7392 if (vmcs12->cr4_guest_host_mask &
7393 (vmcs12->cr4_read_shadow ^ val))
1d804d07 7394 return true;
644d711a
NHE		 7395 break;
7396 case 8:
7397 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
1d804d07 7398 return true;
644d711a
NHE		 7399 break;
7400 }
7401 break;
7402 case 2: /* clts */
7403 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7404 (vmcs12->cr0_read_shadow & X86_CR0_TS))
1d804d07 7405 return true;
644d711a
NHE		 7406 break;
7407 case 1: /* mov from cr */
7408 switch (cr) {
7409 case 3:
7410 if (vmcs12->cpu_based_vm_exec_control &
7411 CPU_BASED_CR3_STORE_EXITING)
1d804d07 7412 return true;
644d711a
NHE		 7413 break;
7414 case 8:
7415 if (vmcs12->cpu_based_vm_exec_control &
7416 CPU_BASED_CR8_STORE_EXITING)
1d804d07 7417 return true;
644d711a
NHE		 7418 break;
7419 }
7420 break;
7421 case 3: /* lmsw */
7422 /*
7423 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7424 * cr0. Other attempted changes are ignored, with no exit.
7425 */
7426 if (vmcs12->cr0_guest_host_mask & 0xe &
7427 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7428 return true;
644d711a
NHE		 7429 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7430 !(vmcs12->cr0_read_shadow & 0x1) &&
7431 (val & 0x1))
1d804d07 7432 return true;
644d711a
NHE		 7433 break;
7434 }
1d804d07 7435 return false;
644d711a
NHE		 7436}
7437
7438/*
7439 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7440 * should handle it ourselves in L0 (and then continue L2). Only call this
7441 * when in is_guest_mode (L2).
7442 */
7443static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7444{
644d711a
NHE		 7445 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7446 struct vcpu_vmx *vmx = to_vmx(vcpu);
7447 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7448 u32 exit_reason = vmx->exit_reason;
644d711a 7449
542060ea
JK		 7450 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7451 vmcs_readl(EXIT_QUALIFICATION),
7452 vmx->idt_vectoring_info,
7453 intr_info,
7454 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7455 KVM_ISA_VMX);
7456
644d711a 7457 if (vmx->nested.nested_run_pending)
1d804d07 7458 return false;
644d711a
NHE		 7459
7460 if (unlikely(vmx->fail)) {
bd80158a
JK		 7461 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7462 vmcs_read32(VM_INSTRUCTION_ERROR));
1d804d07 7463 return true;
644d711a
NHE		 7464 }
7465
7466 switch (exit_reason) {
7467 case EXIT_REASON_EXCEPTION_NMI:
7468 if (!is_exception(intr_info))
1d804d07 7469 return false;
644d711a
NHE		 7470 else if (is_page_fault(intr_info))
7471 return enable_ept;
e504c909 7472 else if (is_no_device(intr_info) &&
ccf9844e 7473 !(vmcs12->guest_cr0 & X86_CR0_TS))
1d804d07 7474 return false;
644d711a
NHE		 7475 return vmcs12->exception_bitmap &
7476 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7477 case EXIT_REASON_EXTERNAL_INTERRUPT:
1d804d07 7478 return false;
644d711a 7479 case EXIT_REASON_TRIPLE_FAULT:
1d804d07 7480 return true;
644d711a 7481 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7482 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7483 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7484 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a 7485 case EXIT_REASON_TASK_SWITCH:
1d804d07 7486 return true;
644d711a 7487 case EXIT_REASON_CPUID:
bc613494 7488 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
1d804d07
JP		 7489 return false;
7490 return true;
644d711a
NHE		 7491 case EXIT_REASON_HLT:
7492 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7493 case EXIT_REASON_INVD:
1d804d07 7494 return true;
644d711a
NHE		 7495 case EXIT_REASON_INVLPG:
7496 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7497 case EXIT_REASON_RDPMC:
7498 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
b3a2a907 7499 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
644d711a
NHE		 7500 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7501 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7502 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7503 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7504 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7505 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 7506 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 7507 /*
7508 * VMX instructions trap unconditionally. This allows L1 to
7509 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7510 */
1d804d07 7511 return true;
644d711a
NHE		 7512 case EXIT_REASON_CR_ACCESS:
7513 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7514 case EXIT_REASON_DR_ACCESS:
7515 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7516 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7517 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7518 case EXIT_REASON_MSR_READ:
7519 case EXIT_REASON_MSR_WRITE:
7520 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7521 case EXIT_REASON_INVALID_STATE:
1d804d07 7522 return true;
644d711a
NHE		 7523 case EXIT_REASON_MWAIT_INSTRUCTION:
7524 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5f3d45e7
MD		 7525 case EXIT_REASON_MONITOR_TRAP_FLAG:
7526 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
644d711a
NHE		 7527 case EXIT_REASON_MONITOR_INSTRUCTION:
7528 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7529 case EXIT_REASON_PAUSE_INSTRUCTION:
7530 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7531 nested_cpu_has2(vmcs12,
7532 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7533 case EXIT_REASON_MCE_DURING_VMENTRY:
1d804d07 7534 return false;
644d711a 7535 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7536 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7537 case EXIT_REASON_APIC_ACCESS:
7538 return nested_cpu_has2(vmcs12,
7539 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
82f0dd4b 7540 case EXIT_REASON_APIC_WRITE:
608406e2
WV		 7541 case EXIT_REASON_EOI_INDUCED:
7542 /* apic_write and eoi_induced should exit unconditionally. */
1d804d07 7543 return true;
644d711a 7544 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7545 /*
7546 * L0 always deals with the EPT violation. If nested EPT is
7547 * used, and the nested mmu code discovers that the address is
7548 * missing in the guest EPT table (EPT12), the EPT violation
7549 * will be injected with nested_ept_inject_page_fault()
7550 */
1d804d07 7551 return false;
644d711a 7552 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7553 /*
7554 * L2 never uses directly L1's EPT, but rather L0's own EPT
7555 * table (shadow on EPT) or a merged EPT table that L0 built
7556 * (EPT on EPT). So any problems with the structure of the
7557 * table is L0's fault.
7558 */
1d804d07 7559 return false;
644d711a
NHE		 7560 case EXIT_REASON_WBINVD:
7561 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7562 case EXIT_REASON_XSETBV:
1d804d07 7563 return true;
81dc01f7
WL		 7564 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7565 /*
7566 * This should never happen, since it is not possible to
7567 * set XSS to a non-zero value---neither in L1 nor in L2.
7568 * If if it were, XSS would have to be checked against
7569 * the XSS exit bitmap in vmcs12.
7570 */
7571 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8b3e34e4
XG		 7572 case EXIT_REASON_PCOMMIT:
7573 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
644d711a 7574 default:
1d804d07 7575 return true;
644d711a
NHE		 7576 }
7577}
7578
586f9607
AK		 7579static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7580{
7581 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7582 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7583}
7584
843e4330
KH		 7585static int vmx_enable_pml(struct vcpu_vmx *vmx)
7586{
7587 struct page *pml_pg;
843e4330
KH		 7588
7589 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7590 if (!pml_pg)
7591 return -ENOMEM;
7592
7593 vmx->pml_pg = pml_pg;
7594
7595 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7596 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7597
7ec36296 7598 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_ENABLE_PML);
843e4330
KH		 7599
7600 return 0;
7601}
7602
7603static void vmx_disable_pml(struct vcpu_vmx *vmx)
7604{
843e4330
KH		 7605 ASSERT(vmx->pml_pg);
7606 __free_page(vmx->pml_pg);
7607 vmx->pml_pg = NULL;
7608
7ec36296 7609 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_ENABLE_PML);
843e4330
KH		 7610}
7611
54bf36aa 7612static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
843e4330 7613{
54bf36aa 7614 struct vcpu_vmx *vmx = to_vmx(vcpu);
843e4330
KH		 7615 u64 *pml_buf;
7616 u16 pml_idx;
7617
7618 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7619
7620 /* Do nothing if PML buffer is empty */
7621 if (pml_idx == (PML_ENTITY_NUM - 1))
7622 return;
7623
7624 /* PML index always points to next available PML buffer entity */
7625 if (pml_idx >= PML_ENTITY_NUM)
7626 pml_idx = 0;
7627 else
7628 pml_idx++;
7629
7630 pml_buf = page_address(vmx->pml_pg);
7631 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7632 u64 gpa;
7633
7634 gpa = pml_buf[pml_idx];
7635 WARN_ON(gpa & (PAGE_SIZE - 1));
54bf36aa 7636 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
843e4330
KH		 7637 }
7638
7639 /* reset PML index */
7640 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7641}
7642
7643/*
7644 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7645 * Called before reporting dirty_bitmap to userspace.
7646 */
7647static void kvm_flush_pml_buffers(struct kvm *kvm)
7648{
7649 int i;
7650 struct kvm_vcpu *vcpu;
7651 /*
7652 * We only need to kick vcpu out of guest mode here, as PML buffer
7653 * is flushed at beginning of all VMEXITs, and it's obvious that only
7654 * vcpus running in guest are possible to have unflushed GPAs in PML
7655 * buffer.
7656 */
7657 kvm_for_each_vcpu(i, vcpu, kvm)
7658 kvm_vcpu_kick(vcpu);
7659}
7660
4eb64dce
PB		 7661static void vmx_dump_sel(char *name, uint32_t sel)
7662{
7663 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7664 name, vmcs_read32(sel),
7665 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7666 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7667 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7668}
7669
7670static void vmx_dump_dtsel(char *name, uint32_t limit)
7671{
7672 pr_err("%s limit=0x%08x, base=0x%016lx\n",
7673 name, vmcs_read32(limit),
7674 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7675}
7676
7677static void dump_vmcs(void)
7678{
7679 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7680 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7681 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7682 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7683 u32 secondary_exec_control = 0;
7684 unsigned long cr4 = vmcs_readl(GUEST_CR4);
7685 u64 efer = vmcs_readl(GUEST_IA32_EFER);
7686 int i, n;
7687
7688 if (cpu_has_secondary_exec_ctrls())
7689 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7690
7691 pr_err("*** Guest State ***\n");
7692 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7693 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7694 vmcs_readl(CR0_GUEST_HOST_MASK));
7695 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7696 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7697 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7698 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7699 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7700 {
7701 pr_err("PDPTR0 = 0x%016lx PDPTR1 = 0x%016lx\n",
7702 vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7703 pr_err("PDPTR2 = 0x%016lx PDPTR3 = 0x%016lx\n",
7704 vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7705 }
7706 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
7707 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7708 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
7709 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7710 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7711 vmcs_readl(GUEST_SYSENTER_ESP),
7712 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7713 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
7714 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
7715 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
7716 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
7717 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
7718 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
7719 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7720 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7721 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7722 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
7723 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7724 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7725 pr_err("EFER = 0x%016llx PAT = 0x%016lx\n",
7726 efer, vmcs_readl(GUEST_IA32_PAT));
7727 pr_err("DebugCtl = 0x%016lx DebugExceptions = 0x%016lx\n",
7728 vmcs_readl(GUEST_IA32_DEBUGCTL),
7729 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7730 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7731 pr_err("PerfGlobCtl = 0x%016lx\n",
7732 vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7733 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7734 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7735 pr_err("Interruptibility = %08x ActivityState = %08x\n",
7736 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7737 vmcs_read32(GUEST_ACTIVITY_STATE));
7738 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7739 pr_err("InterruptStatus = %04x\n",
7740 vmcs_read16(GUEST_INTR_STATUS));
7741
7742 pr_err("*** Host State ***\n");
7743 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
7744 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7745 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7746 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
7747 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
7748 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
7749 vmcs_read16(HOST_TR_SELECTOR));
7750 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7751 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
7752 vmcs_readl(HOST_TR_BASE));
7753 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7754 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
7755 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7756 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
7757 vmcs_readl(HOST_CR4));
7758 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7759 vmcs_readl(HOST_IA32_SYSENTER_ESP),
7760 vmcs_read32(HOST_IA32_SYSENTER_CS),
7761 vmcs_readl(HOST_IA32_SYSENTER_EIP));
7762 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
7763 pr_err("EFER = 0x%016lx PAT = 0x%016lx\n",
7764 vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
7765 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7766 pr_err("PerfGlobCtl = 0x%016lx\n",
7767 vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
7768
7769 pr_err("*** Control State ***\n");
7770 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
7771 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
7772 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
7773 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
7774 vmcs_read32(EXCEPTION_BITMAP),
7775 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
7776 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
7777 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
7778 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7779 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
7780 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
7781 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
7782 vmcs_read32(VM_EXIT_INTR_INFO),
7783 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7784 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
7785 pr_err(" reason=%08x qualification=%016lx\n",
7786 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
7787 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
7788 vmcs_read32(IDT_VECTORING_INFO_FIELD),
7789 vmcs_read32(IDT_VECTORING_ERROR_CODE));
7790 pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
7791 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
7792 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
7793 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
7794 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
7795 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
7796 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
7797 n = vmcs_read32(CR3_TARGET_COUNT);
7798 for (i = 0; i + 1 < n; i += 4)
7799 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
7800 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
7801 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
7802 if (i < n)
7803 pr_err("CR3 target%u=%016lx\n",
7804 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
7805 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
7806 pr_err("PLE Gap=%08x Window=%08x\n",
7807 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
7808 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
7809 pr_err("Virtual processor ID = 0x%04x\n",
7810 vmcs_read16(VIRTUAL_PROCESSOR_ID));
7811}
7812
6aa8b732
AK		 7813/*
7814 * The guest has exited. See if we can fix it or if we need userspace
7815 * assistance.
7816 */
851ba692 7817static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7818{
29bd8a78 7819 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7820 u32 exit_reason = vmx->exit_reason;
1155f76a 7821 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7822
843e4330
KH		 7823 /*
7824 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7825 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7826 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7827 * mode as if vcpus is in root mode, the PML buffer must has been
7828 * flushed already.
7829 */
7830 if (enable_pml)
54bf36aa 7831 vmx_flush_pml_buffer(vcpu);
843e4330 7832
80ced186 7833 /* If guest state is invalid, start emulating */
14168786 7834 if (vmx->emulation_required)
80ced186 7835 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7836
644d711a 7837 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7838 nested_vmx_vmexit(vcpu, exit_reason,
7839 vmcs_read32(VM_EXIT_INTR_INFO),
7840 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7841 return 1;
7842 }
7843
5120702e 7844 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
4eb64dce 7845 dump_vmcs();
5120702e
MG		 7846 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7847 vcpu->run->fail_entry.hardware_entry_failure_reason
7848 = exit_reason;
7849 return 0;
7850 }
7851
29bd8a78 7852 if (unlikely(vmx->fail)) {
851ba692
AK		 7853 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7854 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7855 = vmcs_read32(VM_INSTRUCTION_ERROR);
7856 return 0;
7857 }
6aa8b732 7858
b9bf6882
XG		 7859 /*
7860 * Note:
7861 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7862 * delivery event since it indicates guest is accessing MMIO.
7863 * The vm-exit can be triggered again after return to guest that
7864 * will cause infinite loop.
7865 */
d77c26fc 7866 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7867 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7868 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7869 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7870 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7871 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7872 vcpu->run->internal.ndata = 2;
7873 vcpu->run->internal.data[0] = vectoring_info;
7874 vcpu->run->internal.data[1] = exit_reason;
7875 return 0;
7876 }
3b86cd99 7877
644d711a
NHE		 7878 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7879 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7880 get_vmcs12(vcpu))))) {
c4282df9 7881 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7882 vmx->soft_vnmi_blocked = 0;
3b86cd99 7883 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7884 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7885 /*
7886 * This CPU don't support us in finding the end of an
7887 * NMI-blocked window if the guest runs with IRQs
7888 * disabled. So we pull the trigger after 1 s of
7889 * futile waiting, but inform the user about this.
7890 */
7891 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7892 "state on VCPU %d after 1 s timeout\n",
7893 __func__, vcpu->vcpu_id);
7894 vmx->soft_vnmi_blocked = 0;
3b86cd99 7895 }
3b86cd99
JK		 7896 }
7897
6aa8b732
AK		 7898 if (exit_reason < kvm_vmx_max_exit_handlers
7899 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7900 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7901 else {
2bc19dc3
MT		 7902 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7903 kvm_queue_exception(vcpu, UD_VECTOR);
7904 return 1;
6aa8b732 7905 }
6aa8b732
AK		 7906}
7907
95ba8273 7908static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7909{
a7c0b07d
WL		 7910 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7911
7912 if (is_guest_mode(vcpu) &&
7913 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7914 return;
7915
95ba8273 7916 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7917 vmcs_write32(TPR_THRESHOLD, 0);
7918 return;
7919 }
7920
95ba8273 7921 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7922}
7923
8d14695f
YZ		 7924static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7925{
7926 u32 sec_exec_control;
7927
7928 /*
7929 * There is not point to enable virtualize x2apic without enable
7930 * apicv
7931 */
c7c9c56c 7932 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
35754c98 7933 !vmx_cpu_uses_apicv(vcpu))
8d14695f
YZ		 7934 return;
7935
35754c98 7936 if (!cpu_need_tpr_shadow(vcpu))
8d14695f
YZ		 7937 return;
7938
7939 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7940
7941 if (set) {
7942 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7943 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7944 } else {
7945 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7946 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7947 }
7948 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7949
7950 vmx_set_msr_bitmap(vcpu);
7951}
7952
38b99173
TC		 7953static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7954{
7955 struct vcpu_vmx *vmx = to_vmx(vcpu);
7956
7957 /*
7958 * Currently we do not handle the nested case where L2 has an
7959 * APIC access page of its own; that page is still pinned.
7960 * Hence, we skip the case where the VCPU is in guest mode _and_
7961 * L1 prepared an APIC access page for L2.
7962 *
7963 * For the case where L1 and L2 share the same APIC access page
7964 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7965 * in the vmcs12), this function will only update either the vmcs01
7966 * or the vmcs02. If the former, the vmcs02 will be updated by
7967 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7968 * the next L2->L1 exit.
7969 */
7970 if (!is_guest_mode(vcpu) ||
7971 !nested_cpu_has2(vmx->nested.current_vmcs12,
7972 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7973 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7974}
7975
c7c9c56c
YZ		 7976static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7977{
7978 u16 status;
7979 u8 old;
7980
c7c9c56c
YZ		 7981 if (isr == -1)
7982 isr = 0;
7983
7984 status = vmcs_read16(GUEST_INTR_STATUS);
7985 old = status >> 8;
7986 if (isr != old) {
7987 status &= 0xff;
7988 status |= isr << 8;
7989 vmcs_write16(GUEST_INTR_STATUS, status);
7990 }
7991}
7992
7993static void vmx_set_rvi(int vector)
7994{
7995 u16 status;
7996 u8 old;
7997
4114c27d
WW		 7998 if (vector == -1)
7999 vector = 0;
8000
c7c9c56c
YZ		 8001 status = vmcs_read16(GUEST_INTR_STATUS);
8002 old = (u8)status & 0xff;
8003 if ((u8)vector != old) {
8004 status &= ~0xff;
8005 status |= (u8)vector;
8006 vmcs_write16(GUEST_INTR_STATUS, status);
8007 }
8008}
8009
8010static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8011{
4114c27d
WW		 8012 if (!is_guest_mode(vcpu)) {
8013 vmx_set_rvi(max_irr);
8014 return;
8015 }
8016
c7c9c56c
YZ		 8017 if (max_irr == -1)
8018 return;
8019
963fee16 8020 /*
4114c27d
WW		 8021 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8022 * handles it.
963fee16 8023 */
4114c27d 8024 if (nested_exit_on_intr(vcpu))
963fee16
WL		 8025 return;
8026
963fee16 8027 /*
4114c27d 8028 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL		 8029 * is run without virtual interrupt delivery.
8030 */
8031 if (!kvm_event_needs_reinjection(vcpu) &&
8032 vmx_interrupt_allowed(vcpu)) {
8033 kvm_queue_interrupt(vcpu, max_irr, false);
8034 vmx_inject_irq(vcpu);
8035 }
c7c9c56c
YZ		 8036}
8037
3bb345f3 8038static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
c7c9c56c 8039{
3bb345f3 8040 u64 *eoi_exit_bitmap = vcpu->arch.eoi_exit_bitmap;
35754c98 8041 if (!vmx_cpu_uses_apicv(vcpu))
3d81bc7e
YZ		 8042 return;
8043
c7c9c56c
YZ		 8044 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8045 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8046 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8047 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8048}
8049
51aa01d1 8050static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 8051{
00eba012
AK		 8052 u32 exit_intr_info;
8053
8054 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8055 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8056 return;
8057
c5ca8e57 8058 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 8059 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 8060
8061 /* Handle machine checks before interrupts are enabled */
00eba012 8062 if (is_machine_check(exit_intr_info))
a0861c02
AK		 8063 kvm_machine_check();
8064
20f65983 8065 /* We need to handle NMIs before interrupts are enabled */
00eba012 8066 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 8067 (exit_intr_info & INTR_INFO_VALID_MASK)) {
8068 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 8069 asm("int $2");
ff9d07a0
ZY		 8070 kvm_after_handle_nmi(&vmx->vcpu);
8071 }
51aa01d1 8072}
20f65983 8073
a547c6db
YZ		 8074static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8075{
8076 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8077
8078 /*
8079 * If external interrupt exists, IF bit is set in rflags/eflags on the
8080 * interrupt stack frame, and interrupt will be enabled on a return
8081 * from interrupt handler.
8082 */
8083 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8084 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8085 unsigned int vector;
8086 unsigned long entry;
8087 gate_desc *desc;
8088 struct vcpu_vmx *vmx = to_vmx(vcpu);
8089#ifdef CONFIG_X86_64
8090 unsigned long tmp;
8091#endif
8092
8093 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8094 desc = (gate_desc *)vmx->host_idt_base + vector;
8095 entry = gate_offset(*desc);
8096 asm volatile(
8097#ifdef CONFIG_X86_64
8098 "mov %%" _ASM_SP ", %[sp]\n\t"
8099 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8100 "push $%c[ss]\n\t"
8101 "push %[sp]\n\t"
8102#endif
8103 "pushf\n\t"
8104 "orl $0x200, (%%" _ASM_SP ")\n\t"
8105 __ASM_SIZE(push) " $%c[cs]\n\t"
8106 "call *%[entry]\n\t"
8107 :
8108#ifdef CONFIG_X86_64
8109 [sp]"=&r"(tmp)
8110#endif
8111 :
8112 [entry]"r"(entry),
8113 [ss]"i"(__KERNEL_DS),
8114 [cs]"i"(__KERNEL_CS)
8115 );
8116 } else
8117 local_irq_enable();
8118}
8119
6d396b55
PB		 8120static bool vmx_has_high_real_mode_segbase(void)
8121{
8122 return enable_unrestricted_guest || emulate_invalid_guest_state;
8123}
8124
da8999d3
LJ		 8125static bool vmx_mpx_supported(void)
8126{
8127 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8128 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8129}
8130
55412b2e
WL		 8131static bool vmx_xsaves_supported(void)
8132{
8133 return vmcs_config.cpu_based_2nd_exec_ctrl &
8134 SECONDARY_EXEC_XSAVES;
8135}
8136
51aa01d1
AK		 8137static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8138{
c5ca8e57 8139 u32 exit_intr_info;
51aa01d1
AK		 8140 bool unblock_nmi;
8141 u8 vector;
8142 bool idtv_info_valid;
8143
8144 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 8145
cf393f75 8146 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 8147 if (vmx->nmi_known_unmasked)
8148 return;
c5ca8e57
AK		 8149 /*
8150 * Can't use vmx->exit_intr_info since we're not sure what
8151 * the exit reason is.
8152 */
8153 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 8154 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8155 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8156 /*
7b4a25cb 8157 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 8158 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8159 * a guest IRET fault.
7b4a25cb
GN		 8160 * SDM 3: 23.2.2 (September 2008)
8161 * Bit 12 is undefined in any of the following cases:
8162 * If the VM exit sets the valid bit in the IDT-vectoring
8163 * information field.
8164 * If the VM exit is due to a double fault.
cf393f75 8165 */
7b4a25cb
GN		 8166 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8167 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 8168 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8169 GUEST_INTR_STATE_NMI);
9d58b931
AK		 8170 else
8171 vmx->nmi_known_unmasked =
8172 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8173 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 8174 } else if (unlikely(vmx->soft_vnmi_blocked))
8175 vmx->vnmi_blocked_time +=
8176 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 8177}
8178
3ab66e8a 8179static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 8180 u32 idt_vectoring_info,
8181 int instr_len_field,
8182 int error_code_field)
51aa01d1 8183{
51aa01d1
AK		 8184 u8 vector;
8185 int type;
8186 bool idtv_info_valid;
8187
8188 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 8189
3ab66e8a
JK		 8190 vcpu->arch.nmi_injected = false;
8191 kvm_clear_exception_queue(vcpu);
8192 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 8193
8194 if (!idtv_info_valid)
8195 return;
8196
3ab66e8a 8197 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 8198
668f612f
AK		 8199 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8200 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 8201
64a7ec06 8202 switch (type) {
37b96e98 8203 case INTR_TYPE_NMI_INTR:
3ab66e8a 8204 vcpu->arch.nmi_injected = true;
668f612f 8205 /*
7b4a25cb 8206 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 8207 * Clear bit "block by NMI" before VM entry if a NMI
8208 * delivery faulted.
668f612f 8209 */
3ab66e8a 8210 vmx_set_nmi_mask(vcpu, false);
37b96e98 8211 break;
37b96e98 8212 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 8213 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 8214 /* fall through */
8215 case INTR_TYPE_HARD_EXCEPTION:
35920a35 8216 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 8217 u32 err = vmcs_read32(error_code_field);
851eb667 8218 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 8219 } else
851eb667 8220 kvm_requeue_exception(vcpu, vector);
37b96e98 8221 break;
66fd3f7f 8222 case INTR_TYPE_SOFT_INTR:
3ab66e8a 8223 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 8224 /* fall through */
37b96e98 8225 case INTR_TYPE_EXT_INTR:
3ab66e8a 8226 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 8227 break;
8228 default:
8229 break;
f7d9238f 8230 }
cf393f75
AK		 8231}
8232
83422e17
AK		 8233static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8234{
3ab66e8a 8235 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 8236 VM_EXIT_INSTRUCTION_LEN,
8237 IDT_VECTORING_ERROR_CODE);
8238}
8239
b463a6f7
AK		 8240static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8241{
3ab66e8a 8242 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 8243 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8244 VM_ENTRY_INSTRUCTION_LEN,
8245 VM_ENTRY_EXCEPTION_ERROR_CODE);
8246
8247 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8248}
8249
d7cd9796
GN		 8250static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8251{
8252 int i, nr_msrs;
8253 struct perf_guest_switch_msr *msrs;
8254
8255 msrs = perf_guest_get_msrs(&nr_msrs);
8256
8257 if (!msrs)
8258 return;
8259
8260 for (i = 0; i < nr_msrs; i++)
8261 if (msrs[i].host == msrs[i].guest)
8262 clear_atomic_switch_msr(vmx, msrs[i].msr);
8263 else
8264 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8265 msrs[i].host);
8266}
8267
a3b5ba49 8268static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 8269{
a2fa3e9f 8270 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 8271 unsigned long debugctlmsr, cr4;
104f226b
AK		 8272
8273 /* Record the guest's net vcpu time for enforced NMI injections. */
8274 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8275 vmx->entry_time = ktime_get();
8276
8277 /* Don't enter VMX if guest state is invalid, let the exit handler
8278 start emulation until we arrive back to a valid state */
14168786 8279 if (vmx->emulation_required)
104f226b
AK		 8280 return;
8281
a7653ecd
RK		 8282 if (vmx->ple_window_dirty) {
8283 vmx->ple_window_dirty = false;
8284 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8285 }
8286
012f83cb
AG		 8287 if (vmx->nested.sync_shadow_vmcs) {
8288 copy_vmcs12_to_shadow(vmx);
8289 vmx->nested.sync_shadow_vmcs = false;
8290 }
8291
104f226b
AK		 8292 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8293 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8294 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8295 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8296
1e02ce4c 8297 cr4 = cr4_read_shadow();
d974baa3
AL		 8298 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8299 vmcs_writel(HOST_CR4, cr4);
8300 vmx->host_state.vmcs_host_cr4 = cr4;
8301 }
8302
104f226b
AK		 8303 /* When single-stepping over STI and MOV SS, we must clear the
8304 * corresponding interruptibility bits in the guest state. Otherwise
8305 * vmentry fails as it then expects bit 14 (BS) in pending debug
8306 * exceptions being set, but that's not correct for the guest debugging
8307 * case. */
8308 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8309 vmx_set_interrupt_shadow(vcpu, 0);
8310
d7cd9796 8311 atomic_switch_perf_msrs(vmx);
2a7921b7 8312 debugctlmsr = get_debugctlmsr();
d7cd9796 8313
d462b819 8314 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 8315 asm(
6aa8b732 8316 /* Store host registers */
b188c81f
AK		 8317 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8318 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8319 "push %%" _ASM_CX " \n\t"
8320 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 8321 "je 1f \n\t"
b188c81f 8322 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 8323 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 8324 "1: \n\t"
d3edefc0 8325 /* Reload cr2 if changed */
b188c81f
AK		 8326 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8327 "mov %%cr2, %%" _ASM_DX " \n\t"
8328 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 8329 "je 2f \n\t"
b188c81f 8330 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 8331 "2: \n\t"
6aa8b732 8332 /* Check if vmlaunch of vmresume is needed */
e08aa78a 8333 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 8334 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 8335 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8336 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8337 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8338 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8339 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8340 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 8341#ifdef CONFIG_X86_64
e08aa78a
AK		 8342 "mov %c[r8](%0), %%r8 \n\t"
8343 "mov %c[r9](%0), %%r9 \n\t"
8344 "mov %c[r10](%0), %%r10 \n\t"
8345 "mov %c[r11](%0), %%r11 \n\t"
8346 "mov %c[r12](%0), %%r12 \n\t"
8347 "mov %c[r13](%0), %%r13 \n\t"
8348 "mov %c[r14](%0), %%r14 \n\t"
8349 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 8350#endif
b188c81f 8351 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 8352
6aa8b732 8353 /* Enter guest mode */
83287ea4 8354 "jne 1f \n\t"
4ecac3fd 8355 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 8356 "jmp 2f \n\t"
8357 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8358 "2: "
6aa8b732 8359 /* Save guest registers, load host registers, keep flags */
b188c81f 8360 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 8361 "pop %0 \n\t"
b188c81f
AK		 8362 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8363 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8364 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8365 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8366 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8367 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8368 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 8369#ifdef CONFIG_X86_64
e08aa78a
AK		 8370 "mov %%r8, %c[r8](%0) \n\t"
8371 "mov %%r9, %c[r9](%0) \n\t"
8372 "mov %%r10, %c[r10](%0) \n\t"
8373 "mov %%r11, %c[r11](%0) \n\t"
8374 "mov %%r12, %c[r12](%0) \n\t"
8375 "mov %%r13, %c[r13](%0) \n\t"
8376 "mov %%r14, %c[r14](%0) \n\t"
8377 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 8378#endif
b188c81f
AK		 8379 "mov %%cr2, %%" _ASM_AX " \n\t"
8380 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 8381
b188c81f 8382 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 8383 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 8384 ".pushsection .rodata \n\t"
8385 ".global vmx_return \n\t"
8386 "vmx_return: " _ASM_PTR " 2b \n\t"
8387 ".popsection"
e08aa78a 8388 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 8389 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 8390 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 8391 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 8392 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8393 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8394 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8395 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8396 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8397 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8398 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 8399#ifdef CONFIG_X86_64
ad312c7c
ZX		 8400 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8401 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8402 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8403 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8404 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8405 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8406 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8407 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 8408#endif
40712fae
AK		 8409 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8410 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 8411 : "cc", "memory"
8412#ifdef CONFIG_X86_64
b188c81f 8413 , "rax", "rbx", "rdi", "rsi"
c2036300 8414 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 8415#else
8416 , "eax", "ebx", "edi", "esi"
c2036300
LV		 8417#endif
8418 );
6aa8b732 8419
2a7921b7
GN		 8420 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8421 if (debugctlmsr)
8422 update_debugctlmsr(debugctlmsr);
8423
aa67f609
AK		 8424#ifndef CONFIG_X86_64
8425 /*
8426 * The sysexit path does not restore ds/es, so we must set them to
8427 * a reasonable value ourselves.
8428 *
8429 * We can't defer this to vmx_load_host_state() since that function
8430 * may be executed in interrupt context, which saves and restore segments
8431 * around it, nullifying its effect.
8432 */
8433 loadsegment(ds, __USER_DS);
8434 loadsegment(es, __USER_DS);
8435#endif
8436
6de4f3ad 8437 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 8438 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 8439 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 8440 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 8441 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 8442 vcpu->arch.regs_dirty = 0;
8443
1155f76a
AK		 8444 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8445
d462b819 8446 vmx->loaded_vmcs->launched = 1;
1b6269db 8447
51aa01d1 8448 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 8449 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 8450
e0b890d3
GN		 8451 /*
8452 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8453 * we did not inject a still-pending event to L1 now because of
8454 * nested_run_pending, we need to re-enable this bit.
8455 */
8456 if (vmx->nested.nested_run_pending)
8457 kvm_make_request(KVM_REQ_EVENT, vcpu);
8458
8459 vmx->nested.nested_run_pending = 0;
8460
51aa01d1
AK		 8461 vmx_complete_atomic_exit(vmx);
8462 vmx_recover_nmi_blocking(vmx);
cf393f75 8463 vmx_complete_interrupts(vmx);
6aa8b732
AK		 8464}
8465
4fa7734c
PB		 8466static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8467{
8468 struct vcpu_vmx *vmx = to_vmx(vcpu);
8469 int cpu;
8470
8471 if (vmx->loaded_vmcs == &vmx->vmcs01)
8472 return;
8473
8474 cpu = get_cpu();
8475 vmx->loaded_vmcs = &vmx->vmcs01;
8476 vmx_vcpu_put(vcpu);
8477 vmx_vcpu_load(vcpu, cpu);
8478 vcpu->cpu = cpu;
8479 put_cpu();
8480}
8481
6aa8b732
AK		 8482static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8483{
fb3f0f51
RR		 8484 struct vcpu_vmx *vmx = to_vmx(vcpu);
8485
843e4330
KH		 8486 if (enable_pml)
8487 vmx_disable_pml(vmx);
cdbecfc3 8488 free_vpid(vmx);
4fa7734c
PB		 8489 leave_guest_mode(vcpu);
8490 vmx_load_vmcs01(vcpu);
26a865f4 8491 free_nested(vmx);
4fa7734c 8492 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 8493 kfree(vmx->guest_msrs);
8494 kvm_vcpu_uninit(vcpu);
a4770347 8495 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 8496}
8497
fb3f0f51 8498static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 8499{
fb3f0f51 8500 int err;
c16f862d 8501 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 8502 int cpu;
6aa8b732 8503
a2fa3e9f 8504 if (!vmx)
fb3f0f51
RR		 8505 return ERR_PTR(-ENOMEM);
8506
2384d2b3
SY		 8507 allocate_vpid(vmx);
8508
fb3f0f51
RR		 8509 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8510 if (err)
8511 goto free_vcpu;
965b58a5 8512
a2fa3e9f 8513 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 8514 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8515 > PAGE_SIZE);
0123be42 8516
be6d05cf 8517 err = -ENOMEM;
fb3f0f51 8518 if (!vmx->guest_msrs) {
fb3f0f51
RR		 8519 goto uninit_vcpu;
8520 }
965b58a5 8521
d462b819
NHE		 8522 vmx->loaded_vmcs = &vmx->vmcs01;
8523 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8524 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 8525 goto free_msrs;
d462b819
NHE		 8526 if (!vmm_exclusive)
8527 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8528 loaded_vmcs_init(vmx->loaded_vmcs);
8529 if (!vmm_exclusive)
8530 kvm_cpu_vmxoff();
a2fa3e9f 8531
15ad7146
AK		 8532 cpu = get_cpu();
8533 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 8534 vmx->vcpu.cpu = cpu;
8b9cf98c 8535 err = vmx_vcpu_setup(vmx);
fb3f0f51 8536 vmx_vcpu_put(&vmx->vcpu);
15ad7146 8537 put_cpu();
fb3f0f51
RR		 8538 if (err)
8539 goto free_vmcs;
35754c98 8540 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
be6d05cf
JK		 8541 err = alloc_apic_access_page(kvm);
8542 if (err)
5e4a0b3c 8543 goto free_vmcs;
a63cb560 8544 }
fb3f0f51 8545
b927a3ce
SY		 8546 if (enable_ept) {
8547 if (!kvm->arch.ept_identity_map_addr)
8548 kvm->arch.ept_identity_map_addr =
8549 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 8550 err = init_rmode_identity_map(kvm);
8551 if (err)
93ea5388 8552 goto free_vmcs;
b927a3ce 8553 }
b7ebfb05 8554
b9c237bb
WV		 8555 if (nested)
8556 nested_vmx_setup_ctls_msrs(vmx);
8557
705699a1 8558 vmx->nested.posted_intr_nv = -1;
a9d30f33
NHE		 8559 vmx->nested.current_vmptr = -1ull;
8560 vmx->nested.current_vmcs12 = NULL;
8561
843e4330
KH		 8562 /*
8563 * If PML is turned on, failure on enabling PML just results in failure
8564 * of creating the vcpu, therefore we can simplify PML logic (by
8565 * avoiding dealing with cases, such as enabling PML partially on vcpus
8566 * for the guest, etc.
8567 */
8568 if (enable_pml) {
8569 err = vmx_enable_pml(vmx);
8570 if (err)
8571 goto free_vmcs;
8572 }
8573
fb3f0f51
RR		 8574 return &vmx->vcpu;
8575
8576free_vmcs:
5f3fbc34 8577 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 8578free_msrs:
fb3f0f51
RR		 8579 kfree(vmx->guest_msrs);
8580uninit_vcpu:
8581 kvm_vcpu_uninit(&vmx->vcpu);
8582free_vcpu:
cdbecfc3 8583 free_vpid(vmx);
a4770347 8584 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 8585 return ERR_PTR(err);
6aa8b732
AK		 8586}
8587
002c7f7c
YS		 8588static void __init vmx_check_processor_compat(void *rtn)
8589{
8590 struct vmcs_config vmcs_conf;
8591
8592 *(int *)rtn = 0;
8593 if (setup_vmcs_config(&vmcs_conf) < 0)
8594 *(int *)rtn = -EIO;
8595 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8596 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8597 smp_processor_id());
8598 *(int *)rtn = -EIO;
8599 }
8600}
8601
67253af5
SY		 8602static int get_ept_level(void)
8603{
8604 return VMX_EPT_DEFAULT_GAW + 1;
8605}
8606
4b12f0de 8607static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 8608{
b18d5431
XG		 8609 u8 cache;
8610 u64 ipat = 0;
4b12f0de 8611
522c68c4 8612 /* For VT-d and EPT combination
606decd6 8613 * 1. MMIO: always map as UC
522c68c4
SY		 8614 * 2. EPT with VT-d:
8615 * a. VT-d without snooping control feature: can't guarantee the
606decd6 8616 * result, try to trust guest.
522c68c4
SY		 8617 * b. VT-d with snooping control feature: snooping control feature of
8618 * VT-d engine can guarantee the cache correctness. Just set it
8619 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 8620 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 8621 * consistent with host MTRR
8622 */
606decd6
PB		 8623 if (is_mmio) {
8624 cache = MTRR_TYPE_UNCACHABLE;
8625 goto exit;
8626 }
8627
8628 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
b18d5431
XG		 8629 ipat = VMX_EPT_IPAT_BIT;
8630 cache = MTRR_TYPE_WRBACK;
8631 goto exit;
8632 }
8633
8634 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8635 ipat = VMX_EPT_IPAT_BIT;
0da029ed 8636 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
fb279950
XG		 8637 cache = MTRR_TYPE_WRBACK;
8638 else
8639 cache = MTRR_TYPE_UNCACHABLE;
b18d5431
XG		 8640 goto exit;
8641 }
8642
ff53604b 8643 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
b18d5431
XG		 8644
8645exit:
8646 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
64d4d521
SY		 8647}
8648
17cc3935 8649static int vmx_get_lpage_level(void)
344f414f 8650{
878403b7
SY		 8651 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8652 return PT_DIRECTORY_LEVEL;
8653 else
8654 /* For shadow and EPT supported 1GB page */
8655 return PT_PDPE_LEVEL;
344f414f
JR		 8656}
8657
feda805f
XG		 8658static void vmcs_set_secondary_exec_control(u32 new_ctl)
8659{
8660 /*
8661 * These bits in the secondary execution controls field
8662 * are dynamic, the others are mostly based on the hypervisor
8663 * architecture and the guest's CPUID. Do not touch the
8664 * dynamic bits.
8665 */
8666 u32 mask =
8667 SECONDARY_EXEC_SHADOW_VMCS |
8668 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8669 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8670
8671 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8672
8673 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8674 (new_ctl & ~mask) | (cur_ctl & mask));
8675}
8676
0e851880
SY		 8677static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8678{
4e47c7a6
SY		 8679 struct kvm_cpuid_entry2 *best;
8680 struct vcpu_vmx *vmx = to_vmx(vcpu);
feda805f 8681 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
4e47c7a6 8682
4e47c7a6 8683 if (vmx_rdtscp_supported()) {
1cea0ce6
XG		 8684 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8685 if (!rdtscp_enabled)
feda805f 8686 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
f36201e5 8687
8b97265a 8688 if (nested) {
1cea0ce6 8689 if (rdtscp_enabled)
8b97265a
PB		 8690 vmx->nested.nested_vmx_secondary_ctls_high |=
8691 SECONDARY_EXEC_RDTSCP;
8692 else
8693 vmx->nested.nested_vmx_secondary_ctls_high &=
8694 ~SECONDARY_EXEC_RDTSCP;
8695 }
4e47c7a6 8696 }
ad756a16 8697
ad756a16
MJ		 8698 /* Exposing INVPCID only when PCID is exposed */
8699 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8700 if (vmx_invpcid_supported() &&
29541bb8
XG		 8701 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8702 !guest_cpuid_has_pcid(vcpu))) {
feda805f 8703 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
29541bb8 8704
ad756a16 8705 if (best)
4f977045 8706 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 8707 }
8b3e34e4 8708
feda805f
XG		 8709 vmcs_set_secondary_exec_control(secondary_exec_ctl);
8710
8b3e34e4
XG		 8711 if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
8712 if (guest_cpuid_has_pcommit(vcpu))
8713 vmx->nested.nested_vmx_secondary_ctls_high |=
8714 SECONDARY_EXEC_PCOMMIT;
8715 else
8716 vmx->nested.nested_vmx_secondary_ctls_high &=
8717 ~SECONDARY_EXEC_PCOMMIT;
8718 }
0e851880
SY		 8719}
8720
d4330ef2
JR		 8721static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8722{
7b8050f5
NHE		 8723 if (func == 1 && nested)
8724 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 8725}
8726
25d92081
YZ		 8727static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8728 struct x86_exception *fault)
8729{
533558bc
JK		 8730 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8731 u32 exit_reason;
25d92081
YZ		 8732
8733 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 8734 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 8735 else
533558bc
JK		 8736 exit_reason = EXIT_REASON_EPT_VIOLATION;
8737 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 8738 vmcs12->guest_physical_address = fault->address;
8739}
8740
155a97a3
NHE		 8741/* Callbacks for nested_ept_init_mmu_context: */
8742
8743static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8744{
8745 /* return the page table to be shadowed - in our case, EPT12 */
8746 return get_vmcs12(vcpu)->ept_pointer;
8747}
8748
8a3c1a33 8749static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 8750{
ad896af0
PB		 8751 WARN_ON(mmu_is_nested(vcpu));
8752 kvm_init_shadow_ept_mmu(vcpu,
b9c237bb
WV		 8753 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8754 VMX_EPT_EXECUTE_ONLY_BIT);
155a97a3
NHE		 8755 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8756 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8757 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8758
8759 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 8760}
8761
8762static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8763{
8764 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8765}
8766
19d5f10b
EK		 8767static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8768 u16 error_code)
8769{
8770 bool inequality, bit;
8771
8772 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8773 inequality =
8774 (error_code & vmcs12->page_fault_error_code_mask) !=
8775 vmcs12->page_fault_error_code_match;
8776 return inequality ^ bit;
8777}
8778
feaf0c7d
GN		 8779static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8780 struct x86_exception *fault)
8781{
8782 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8783
8784 WARN_ON(!is_guest_mode(vcpu));
8785
19d5f10b 8786 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK		 8787 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8788 vmcs_read32(VM_EXIT_INTR_INFO),
8789 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 8790 else
8791 kvm_inject_page_fault(vcpu, fault);
8792}
8793
a2bcba50
WL		 8794static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8795 struct vmcs12 *vmcs12)
8796{
8797 struct vcpu_vmx *vmx = to_vmx(vcpu);
9090422f 8798 int maxphyaddr = cpuid_maxphyaddr(vcpu);
a2bcba50
WL		 8799
8800 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9090422f
EK		 8801 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
8802 vmcs12->apic_access_addr >> maxphyaddr)
a2bcba50
WL		 8803 return false;
8804
8805 /*
8806 * Translate L1 physical address to host physical
8807 * address for vmcs02. Keep the page pinned, so this
8808 * physical address remains valid. We keep a reference
8809 * to it so we can release it later.
8810 */
8811 if (vmx->nested.apic_access_page) /* shouldn't happen */
8812 nested_release_page(vmx->nested.apic_access_page);
8813 vmx->nested.apic_access_page =
8814 nested_get_page(vcpu, vmcs12->apic_access_addr);
8815 }
a7c0b07d
WL		 8816
8817 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9090422f
EK		 8818 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
8819 vmcs12->virtual_apic_page_addr >> maxphyaddr)
a7c0b07d
WL		 8820 return false;
8821
8822 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8823 nested_release_page(vmx->nested.virtual_apic_page);
8824 vmx->nested.virtual_apic_page =
8825 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8826
8827 /*
8828 * Failing the vm entry is _not_ what the processor does
8829 * but it's basically the only possibility we have.
8830 * We could still enter the guest if CR8 load exits are
8831 * enabled, CR8 store exits are enabled, and virtualize APIC
8832 * access is disabled; in this case the processor would never
8833 * use the TPR shadow and we could simply clear the bit from
8834 * the execution control. But such a configuration is useless,
8835 * so let's keep the code simple.
8836 */
8837 if (!vmx->nested.virtual_apic_page)
8838 return false;
8839 }
8840
705699a1 8841 if (nested_cpu_has_posted_intr(vmcs12)) {
9090422f
EK		 8842 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
8843 vmcs12->posted_intr_desc_addr >> maxphyaddr)
705699a1
WV		 8844 return false;
8845
8846 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
8847 kunmap(vmx->nested.pi_desc_page);
8848 nested_release_page(vmx->nested.pi_desc_page);
8849 }
8850 vmx->nested.pi_desc_page =
8851 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
8852 if (!vmx->nested.pi_desc_page)
8853 return false;
8854
8855 vmx->nested.pi_desc =
8856 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
8857 if (!vmx->nested.pi_desc) {
8858 nested_release_page_clean(vmx->nested.pi_desc_page);
8859 return false;
8860 }
8861 vmx->nested.pi_desc =
8862 (struct pi_desc *)((void *)vmx->nested.pi_desc +
8863 (unsigned long)(vmcs12->posted_intr_desc_addr &
8864 (PAGE_SIZE - 1)));
8865 }
8866
a2bcba50
WL		 8867 return true;
8868}
8869
f4124500
JK		 8870static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8871{
8872 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8873 struct vcpu_vmx *vmx = to_vmx(vcpu);
8874
8875 if (vcpu->arch.virtual_tsc_khz == 0)
8876 return;
8877
8878 /* Make sure short timeouts reliably trigger an immediate vmexit.
8879 * hrtimer_start does not guarantee this. */
8880 if (preemption_timeout <= 1) {
8881 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8882 return;
8883 }
8884
8885 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8886 preemption_timeout *= 1000000;
8887 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8888 hrtimer_start(&vmx->nested.preemption_timer,
8889 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8890}
8891
3af18d9c
WV		 8892static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
8893 struct vmcs12 *vmcs12)
8894{
8895 int maxphyaddr;
8896 u64 addr;
8897
8898 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8899 return 0;
8900
8901 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
8902 WARN_ON(1);
8903 return -EINVAL;
8904 }
8905 maxphyaddr = cpuid_maxphyaddr(vcpu);
8906
8907 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
8908 ((addr + PAGE_SIZE) >> maxphyaddr))
8909 return -EINVAL;
8910
8911 return 0;
8912}
8913
8914/*
8915 * Merge L0's and L1's MSR bitmap, return false to indicate that
8916 * we do not use the hardware.
8917 */
8918static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
8919 struct vmcs12 *vmcs12)
8920{
82f0dd4b 8921 int msr;
f2b93280
WV		 8922 struct page *page;
8923 unsigned long *msr_bitmap;
8924
8925 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8926 return false;
8927
8928 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
8929 if (!page) {
8930 WARN_ON(1);
8931 return false;
8932 }
8933 msr_bitmap = (unsigned long *)kmap(page);
8934 if (!msr_bitmap) {
8935 nested_release_page_clean(page);
8936 WARN_ON(1);
8937 return false;
8938 }
8939
8940 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
82f0dd4b
WV		 8941 if (nested_cpu_has_apic_reg_virt(vmcs12))
8942 for (msr = 0x800; msr <= 0x8ff; msr++)
8943 nested_vmx_disable_intercept_for_msr(
8944 msr_bitmap,
8945 vmx_msr_bitmap_nested,
8946 msr, MSR_TYPE_R);
f2b93280
WV		 8947 /* TPR is allowed */
8948 nested_vmx_disable_intercept_for_msr(msr_bitmap,
8949 vmx_msr_bitmap_nested,
8950 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8951 MSR_TYPE_R | MSR_TYPE_W);
608406e2
WV		 8952 if (nested_cpu_has_vid(vmcs12)) {
8953 /* EOI and self-IPI are allowed */
8954 nested_vmx_disable_intercept_for_msr(
8955 msr_bitmap,
8956 vmx_msr_bitmap_nested,
8957 APIC_BASE_MSR + (APIC_EOI >> 4),
8958 MSR_TYPE_W);
8959 nested_vmx_disable_intercept_for_msr(
8960 msr_bitmap,
8961 vmx_msr_bitmap_nested,
8962 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8963 MSR_TYPE_W);
8964 }
82f0dd4b
WV		 8965 } else {
8966 /*
8967 * Enable reading intercept of all the x2apic
8968 * MSRs. We should not rely on vmcs12 to do any
8969 * optimizations here, it may have been modified
8970 * by L1.
8971 */
8972 for (msr = 0x800; msr <= 0x8ff; msr++)
8973 __vmx_enable_intercept_for_msr(
8974 vmx_msr_bitmap_nested,
8975 msr,
8976 MSR_TYPE_R);
8977
f2b93280
WV		 8978 __vmx_enable_intercept_for_msr(
8979 vmx_msr_bitmap_nested,
8980 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
82f0dd4b 8981 MSR_TYPE_W);
608406e2
WV		 8982 __vmx_enable_intercept_for_msr(
8983 vmx_msr_bitmap_nested,
8984 APIC_BASE_MSR + (APIC_EOI >> 4),
8985 MSR_TYPE_W);
8986 __vmx_enable_intercept_for_msr(
8987 vmx_msr_bitmap_nested,
8988 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8989 MSR_TYPE_W);
82f0dd4b 8990 }
f2b93280
WV		 8991 kunmap(page);
8992 nested_release_page_clean(page);
8993
8994 return true;
8995}
8996
8997static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
8998 struct vmcs12 *vmcs12)
8999{
82f0dd4b 9000 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
608406e2 9001 !nested_cpu_has_apic_reg_virt(vmcs12) &&
705699a1
WV		 9002 !nested_cpu_has_vid(vmcs12) &&
9003 !nested_cpu_has_posted_intr(vmcs12))
f2b93280
WV		 9004 return 0;
9005
9006 /*
9007 * If virtualize x2apic mode is enabled,
9008 * virtualize apic access must be disabled.
9009 */
82f0dd4b
WV		 9010 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9011 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
f2b93280
WV		 9012 return -EINVAL;
9013
608406e2
WV		 9014 /*
9015 * If virtual interrupt delivery is enabled,
9016 * we must exit on external interrupts.
9017 */
9018 if (nested_cpu_has_vid(vmcs12) &&
9019 !nested_exit_on_intr(vcpu))
9020 return -EINVAL;
9021
705699a1
WV		 9022 /*
9023 * bits 15:8 should be zero in posted_intr_nv,
9024 * the descriptor address has been already checked
9025 * in nested_get_vmcs12_pages.
9026 */
9027 if (nested_cpu_has_posted_intr(vmcs12) &&
9028 (!nested_cpu_has_vid(vmcs12) ||
9029 !nested_exit_intr_ack_set(vcpu) ||
9030 vmcs12->posted_intr_nv & 0xff00))
9031 return -EINVAL;
9032
f2b93280
WV		 9033 /* tpr shadow is needed by all apicv features. */
9034 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9035 return -EINVAL;
9036
9037 return 0;
3af18d9c
WV		 9038}
9039
e9ac033e
EK		 9040static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9041 unsigned long count_field,
92d71bc6 9042 unsigned long addr_field)
ff651cb6 9043{
92d71bc6 9044 int maxphyaddr;
e9ac033e
EK		 9045 u64 count, addr;
9046
9047 if (vmcs12_read_any(vcpu, count_field, &count) ||
9048 vmcs12_read_any(vcpu, addr_field, &addr)) {
9049 WARN_ON(1);
9050 return -EINVAL;
9051 }
9052 if (count == 0)
9053 return 0;
92d71bc6 9054 maxphyaddr = cpuid_maxphyaddr(vcpu);
e9ac033e
EK		 9055 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9056 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9057 pr_warn_ratelimited(
9058 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9059 addr_field, maxphyaddr, count, addr);
9060 return -EINVAL;
9061 }
9062 return 0;
9063}
9064
9065static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9066 struct vmcs12 *vmcs12)
9067{
e9ac033e
EK		 9068 if (vmcs12->vm_exit_msr_load_count == 0 &&
9069 vmcs12->vm_exit_msr_store_count == 0 &&
9070 vmcs12->vm_entry_msr_load_count == 0)
9071 return 0; /* Fast path */
e9ac033e 9072 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
92d71bc6 9073 VM_EXIT_MSR_LOAD_ADDR) ||
e9ac033e 9074 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
92d71bc6 9075 VM_EXIT_MSR_STORE_ADDR) ||
e9ac033e 9076 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
92d71bc6 9077 VM_ENTRY_MSR_LOAD_ADDR))
e9ac033e
EK		 9078 return -EINVAL;
9079 return 0;
9080}
9081
9082static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9083 struct vmx_msr_entry *e)
9084{
9085 /* x2APIC MSR accesses are not allowed */
8a9781f7 9086 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
e9ac033e
EK		 9087 return -EINVAL;
9088 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9089 e->index == MSR_IA32_UCODE_REV)
9090 return -EINVAL;
9091 if (e->reserved != 0)
ff651cb6
WV		 9092 return -EINVAL;
9093 return 0;
9094}
9095
e9ac033e
EK		 9096static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9097 struct vmx_msr_entry *e)
ff651cb6
WV		 9098{
9099 if (e->index == MSR_FS_BASE ||
9100 e->index == MSR_GS_BASE ||
e9ac033e
EK		 9101 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9102 nested_vmx_msr_check_common(vcpu, e))
9103 return -EINVAL;
9104 return 0;
9105}
9106
9107static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9108 struct vmx_msr_entry *e)
9109{
9110 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9111 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV		 9112 return -EINVAL;
9113 return 0;
9114}
9115
9116/*
9117 * Load guest's/host's msr at nested entry/exit.
9118 * return 0 for success, entry index for failure.
9119 */
9120static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9121{
9122 u32 i;
9123 struct vmx_msr_entry e;
9124 struct msr_data msr;
9125
9126 msr.host_initiated = false;
9127 for (i = 0; i < count; i++) {
54bf36aa
PB		 9128 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9129 &e, sizeof(e))) {
e9ac033e
EK		 9130 pr_warn_ratelimited(
9131 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9132 __func__, i, gpa + i * sizeof(e));
ff651cb6 9133 goto fail;
e9ac033e
EK		 9134 }
9135 if (nested_vmx_load_msr_check(vcpu, &e)) {
9136 pr_warn_ratelimited(
9137 "%s check failed (%u, 0x%x, 0x%x)\n",
9138 __func__, i, e.index, e.reserved);
9139 goto fail;
9140 }
ff651cb6
WV		 9141 msr.index = e.index;
9142 msr.data = e.value;
e9ac033e
EK		 9143 if (kvm_set_msr(vcpu, &msr)) {
9144 pr_warn_ratelimited(
9145 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9146 __func__, i, e.index, e.value);
ff651cb6 9147 goto fail;
e9ac033e 9148 }
ff651cb6
WV		 9149 }
9150 return 0;
9151fail:
9152 return i + 1;
9153}
9154
9155static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9156{
9157 u32 i;
9158 struct vmx_msr_entry e;
9159
9160 for (i = 0; i < count; i++) {
609e36d3 9161 struct msr_data msr_info;
54bf36aa
PB		 9162 if (kvm_vcpu_read_guest(vcpu,
9163 gpa + i * sizeof(e),
9164 &e, 2 * sizeof(u32))) {
e9ac033e
EK		 9165 pr_warn_ratelimited(
9166 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9167 __func__, i, gpa + i * sizeof(e));
ff651cb6 9168 return -EINVAL;
e9ac033e
EK		 9169 }
9170 if (nested_vmx_store_msr_check(vcpu, &e)) {
9171 pr_warn_ratelimited(
9172 "%s check failed (%u, 0x%x, 0x%x)\n",
9173 __func__, i, e.index, e.reserved);
ff651cb6 9174 return -EINVAL;
e9ac033e 9175 }
609e36d3
PB		 9176 msr_info.host_initiated = false;
9177 msr_info.index = e.index;
9178 if (kvm_get_msr(vcpu, &msr_info)) {
e9ac033e
EK		 9179 pr_warn_ratelimited(
9180 "%s cannot read MSR (%u, 0x%x)\n",
9181 __func__, i, e.index);
9182 return -EINVAL;
9183 }
54bf36aa
PB		 9184 if (kvm_vcpu_write_guest(vcpu,
9185 gpa + i * sizeof(e) +
9186 offsetof(struct vmx_msr_entry, value),
9187 &msr_info.data, sizeof(msr_info.data))) {
e9ac033e
EK		 9188 pr_warn_ratelimited(
9189 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
609e36d3 9190 __func__, i, e.index, msr_info.data);
e9ac033e
EK		 9191 return -EINVAL;
9192 }
ff651cb6
WV		 9193 }
9194 return 0;
9195}
9196
fe3ef05c
NHE		 9197/*
9198 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9199 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 9200 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 9201 * guest in a way that will both be appropriate to L1's requests, and our
9202 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9203 * function also has additional necessary side-effects, like setting various
9204 * vcpu->arch fields.
9205 */
9206static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9207{
9208 struct vcpu_vmx *vmx = to_vmx(vcpu);
9209 u32 exec_control;
9210
9211 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9212 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9213 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9214 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9215 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9216 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9217 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9218 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9219 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9220 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9221 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9222 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9223 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9224 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9225 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9226 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9227 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9228 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9229 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9230 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9231 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9232 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9233 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9234 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9235 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9236 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9237 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9238 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9239 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9240 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9241 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9242 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9243 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9244 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9245 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9246 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9247
2996fca0
JK		 9248 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9249 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9250 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9251 } else {
9252 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9253 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9254 }
fe3ef05c
NHE		 9255 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9256 vmcs12->vm_entry_intr_info_field);
9257 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9258 vmcs12->vm_entry_exception_error_code);
9259 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9260 vmcs12->vm_entry_instruction_len);
9261 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9262 vmcs12->guest_interruptibility_info);
fe3ef05c 9263 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 9264 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 9265 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9266 vmcs12->guest_pending_dbg_exceptions);
9267 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9268 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9269
81dc01f7
WL		 9270 if (nested_cpu_has_xsaves(vmcs12))
9271 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE		 9272 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9273
f4124500
JK		 9274 exec_control = vmcs12->pin_based_vm_exec_control;
9275 exec_control |= vmcs_config.pin_based_exec_ctrl;
705699a1
WV		 9276 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9277
9278 if (nested_cpu_has_posted_intr(vmcs12)) {
9279 /*
9280 * Note that we use L0's vector here and in
9281 * vmx_deliver_nested_posted_interrupt.
9282 */
9283 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9284 vmx->nested.pi_pending = false;
9285 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9286 vmcs_write64(POSTED_INTR_DESC_ADDR,
9287 page_to_phys(vmx->nested.pi_desc_page) +
9288 (unsigned long)(vmcs12->posted_intr_desc_addr &
9289 (PAGE_SIZE - 1)));
9290 } else
9291 exec_control &= ~PIN_BASED_POSTED_INTR;
9292
f4124500 9293 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 9294
f4124500
JK		 9295 vmx->nested.preemption_timer_expired = false;
9296 if (nested_cpu_has_preemption_timer(vmcs12))
9297 vmx_start_preemption_timer(vcpu);
0238ea91 9298
fe3ef05c
NHE		 9299 /*
9300 * Whether page-faults are trapped is determined by a combination of
9301 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9302 * If enable_ept, L0 doesn't care about page faults and we should
9303 * set all of these to L1's desires. However, if !enable_ept, L0 does
9304 * care about (at least some) page faults, and because it is not easy
9305 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9306 * to exit on each and every L2 page fault. This is done by setting
9307 * MASK=MATCH=0 and (see below) EB.PF=1.
9308 * Note that below we don't need special code to set EB.PF beyond the
9309 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9310 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9311 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9312 *
9313 * A problem with this approach (when !enable_ept) is that L1 may be
9314 * injected with more page faults than it asked for. This could have
9315 * caused problems, but in practice existing hypervisors don't care.
9316 * To fix this, we will need to emulate the PFEC checking (on the L1
9317 * page tables), using walk_addr(), when injecting PFs to L1.
9318 */
9319 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9320 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9321 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9322 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9323
9324 if (cpu_has_secondary_exec_ctrls()) {
f4124500 9325 exec_control = vmx_secondary_exec_control(vmx);
e2821620 9326
fe3ef05c 9327 /* Take the following fields only from vmcs12 */
696dfd95 9328 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 9329 SECONDARY_EXEC_RDTSCP |
696dfd95 9330 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8b3e34e4
XG		 9331 SECONDARY_EXEC_APIC_REGISTER_VIRT |
9332 SECONDARY_EXEC_PCOMMIT);
fe3ef05c
NHE		 9333 if (nested_cpu_has(vmcs12,
9334 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9335 exec_control |= vmcs12->secondary_vm_exec_control;
9336
9337 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 9338 /*
9339 * If translation failed, no matter: This feature asks
9340 * to exit when accessing the given address, and if it
9341 * can never be accessed, this feature won't do
9342 * anything anyway.
9343 */
9344 if (!vmx->nested.apic_access_page)
9345 exec_control &=
9346 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9347 else
9348 vmcs_write64(APIC_ACCESS_ADDR,
9349 page_to_phys(vmx->nested.apic_access_page));
f2b93280 9350 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
35754c98 9351 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
ca3f257a
JK		 9352 exec_control |=
9353 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 9354 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 9355 }
9356
608406e2
WV		 9357 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9358 vmcs_write64(EOI_EXIT_BITMAP0,
9359 vmcs12->eoi_exit_bitmap0);
9360 vmcs_write64(EOI_EXIT_BITMAP1,
9361 vmcs12->eoi_exit_bitmap1);
9362 vmcs_write64(EOI_EXIT_BITMAP2,
9363 vmcs12->eoi_exit_bitmap2);
9364 vmcs_write64(EOI_EXIT_BITMAP3,
9365 vmcs12->eoi_exit_bitmap3);
9366 vmcs_write16(GUEST_INTR_STATUS,
9367 vmcs12->guest_intr_status);
9368 }
9369
fe3ef05c
NHE		 9370 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9371 }
9372
9373
9374 /*
9375 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9376 * Some constant fields are set here by vmx_set_constant_host_state().
9377 * Other fields are different per CPU, and will be set later when
9378 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9379 */
a547c6db 9380 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 9381
9382 /*
9383 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9384 * entry, but only if the current (host) sp changed from the value
9385 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9386 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9387 * here we just force the write to happen on entry.
9388 */
9389 vmx->host_rsp = 0;
9390
9391 exec_control = vmx_exec_control(vmx); /* L0's desires */
9392 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9393 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9394 exec_control &= ~CPU_BASED_TPR_SHADOW;
9395 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 9396
9397 if (exec_control & CPU_BASED_TPR_SHADOW) {
9398 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9399 page_to_phys(vmx->nested.virtual_apic_page));
9400 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9401 }
9402
3af18d9c 9403 if (cpu_has_vmx_msr_bitmap() &&
670125bd
WV		 9404 exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9405 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9406 /* MSR_BITMAP will be set by following vmx_set_efer. */
3af18d9c
WV		 9407 } else
9408 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9409
fe3ef05c 9410 /*
3af18d9c 9411 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE		 9412 * Rather, exit every time.
9413 */
fe3ef05c
NHE		 9414 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9415 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9416
9417 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9418
9419 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9420 * bitwise-or of what L1 wants to trap for L2, and what we want to
9421 * trap. Note that CR0.TS also needs updating - we do this later.
9422 */
9423 update_exception_bitmap(vcpu);
9424 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9425 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9426
8049d651
NHE		 9427 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9428 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9429 * bits are further modified by vmx_set_efer() below.
9430 */
f4124500 9431 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 9432
9433 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9434 * emulated by vmx_set_efer(), below.
9435 */
2961e876 9436 vm_entry_controls_init(vmx,
8049d651
NHE		 9437 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9438 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 9439 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9440
44811c02 9441 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 9442 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 9443 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9444 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 9445 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9446
9447
9448 set_cr4_guest_host_mask(vmx);
9449
36be0b9d
PB		 9450 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9451 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9452
27fc51b2
NHE		 9453 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9454 vmcs_write64(TSC_OFFSET,
9455 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9456 else
9457 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 9458
9459 if (enable_vpid) {
9460 /*
9461 * Trivially support vpid by letting L2s share their parent
9462 * L1's vpid. TODO: move to a more elaborate solution, giving
9463 * each L2 its own vpid and exposing the vpid feature to L1.
9464 */
9465 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9466 vmx_flush_tlb(vcpu);
9467 }
9468
155a97a3
NHE		 9469 if (nested_cpu_has_ept(vmcs12)) {
9470 kvm_mmu_unload(vcpu);
9471 nested_ept_init_mmu_context(vcpu);
9472 }
9473
fe3ef05c
NHE		 9474 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9475 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 9476 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 9477 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9478 else
9479 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9480 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9481 vmx_set_efer(vcpu, vcpu->arch.efer);
9482
9483 /*
9484 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9485 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9486 * The CR0_READ_SHADOW is what L2 should have expected to read given
9487 * the specifications by L1; It's not enough to take
9488 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9489 * have more bits than L1 expected.
9490 */
9491 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9492 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9493
9494 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9495 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9496
9497 /* shadow page tables on either EPT or shadow page tables */
9498 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9499 kvm_mmu_reset_context(vcpu);
9500
feaf0c7d
GN		 9501 if (!enable_ept)
9502 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9503
3633cfc3
NHE		 9504 /*
9505 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9506 */
9507 if (enable_ept) {
9508 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9509 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9510 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9511 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9512 }
9513
fe3ef05c
NHE		 9514 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9515 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9516}
9517
cd232ad0
NHE		 9518/*
9519 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9520 * for running an L2 nested guest.
9521 */
9522static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9523{
9524 struct vmcs12 *vmcs12;
9525 struct vcpu_vmx *vmx = to_vmx(vcpu);
9526 int cpu;
9527 struct loaded_vmcs *vmcs02;
384bb783 9528 bool ia32e;
ff651cb6 9529 u32 msr_entry_idx;
cd232ad0
NHE		 9530
9531 if (!nested_vmx_check_permission(vcpu) ||
9532 !nested_vmx_check_vmcs12(vcpu))
9533 return 1;
9534
9535 skip_emulated_instruction(vcpu);
9536 vmcs12 = get_vmcs12(vcpu);
9537
012f83cb
AG		 9538 if (enable_shadow_vmcs)
9539 copy_shadow_to_vmcs12(vmx);
9540
7c177938
NHE		 9541 /*
9542 * The nested entry process starts with enforcing various prerequisites
9543 * on vmcs12 as required by the Intel SDM, and act appropriately when
9544 * they fail: As the SDM explains, some conditions should cause the
9545 * instruction to fail, while others will cause the instruction to seem
9546 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9547 * To speed up the normal (success) code path, we should avoid checking
9548 * for misconfigurations which will anyway be caught by the processor
9549 * when using the merged vmcs02.
9550 */
9551 if (vmcs12->launch_state == launch) {
9552 nested_vmx_failValid(vcpu,
9553 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9554 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9555 return 1;
9556 }
9557
6dfacadd
JK		 9558 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9559 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 9560 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9561 return 1;
9562 }
9563
3af18d9c 9564 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 9565 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9566 return 1;
9567 }
9568
3af18d9c 9569 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
7c177938
NHE		 9570 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9571 return 1;
9572 }
9573
f2b93280
WV		 9574 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9575 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9576 return 1;
9577 }
9578
e9ac033e
EK		 9579 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9580 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9581 return 1;
9582 }
9583
7c177938 9584 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
b9c237bb
WV		 9585 vmx->nested.nested_vmx_true_procbased_ctls_low,
9586 vmx->nested.nested_vmx_procbased_ctls_high) ||
7c177938 9587 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
b9c237bb
WV		 9588 vmx->nested.nested_vmx_secondary_ctls_low,
9589 vmx->nested.nested_vmx_secondary_ctls_high) ||
7c177938 9590 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
b9c237bb
WV		 9591 vmx->nested.nested_vmx_pinbased_ctls_low,
9592 vmx->nested.nested_vmx_pinbased_ctls_high) ||
7c177938 9593 !vmx_control_verify(vmcs12->vm_exit_controls,
b9c237bb
WV		 9594 vmx->nested.nested_vmx_true_exit_ctls_low,
9595 vmx->nested.nested_vmx_exit_ctls_high) ||
7c177938 9596 !vmx_control_verify(vmcs12->vm_entry_controls,
b9c237bb
WV		 9597 vmx->nested.nested_vmx_true_entry_ctls_low,
9598 vmx->nested.nested_vmx_entry_ctls_high))
7c177938
NHE		 9599 {
9600 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9601 return 1;
9602 }
9603
9604 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9605 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9606 nested_vmx_failValid(vcpu,
9607 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9608 return 1;
9609 }
9610
b9c237bb 9611 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
7c177938
NHE		 9612 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9613 nested_vmx_entry_failure(vcpu, vmcs12,
9614 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9615 return 1;
9616 }
9617 if (vmcs12->vmcs_link_pointer != -1ull) {
9618 nested_vmx_entry_failure(vcpu, vmcs12,
9619 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9620 return 1;
9621 }
9622
384bb783 9623 /*
cb0c8cda 9624 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 9625 * are performed on the field for the IA32_EFER MSR:
9626 * - Bits reserved in the IA32_EFER MSR must be 0.
9627 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9628 * the IA-32e mode guest VM-exit control. It must also be identical
9629 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9630 * CR0.PG) is 1.
9631 */
9632 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9633 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9634 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9635 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9636 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9637 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9638 nested_vmx_entry_failure(vcpu, vmcs12,
9639 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9640 return 1;
9641 }
9642 }
9643
9644 /*
9645 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9646 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9647 * the values of the LMA and LME bits in the field must each be that of
9648 * the host address-space size VM-exit control.
9649 */
9650 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9651 ia32e = (vmcs12->vm_exit_controls &
9652 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9653 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9654 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9655 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9656 nested_vmx_entry_failure(vcpu, vmcs12,
9657 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9658 return 1;
9659 }
9660 }
9661
7c177938
NHE		 9662 /*
9663 * We're finally done with prerequisite checking, and can start with
9664 * the nested entry.
9665 */
9666
cd232ad0
NHE		 9667 vmcs02 = nested_get_current_vmcs02(vmx);
9668 if (!vmcs02)
9669 return -ENOMEM;
9670
9671 enter_guest_mode(vcpu);
9672
9673 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9674
2996fca0
JK		 9675 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9676 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9677
cd232ad0
NHE		 9678 cpu = get_cpu();
9679 vmx->loaded_vmcs = vmcs02;
9680 vmx_vcpu_put(vcpu);
9681 vmx_vcpu_load(vcpu, cpu);
9682 vcpu->cpu = cpu;
9683 put_cpu();
9684
36c3cc42
JK		 9685 vmx_segment_cache_clear(vmx);
9686
cd232ad0
NHE		 9687 prepare_vmcs02(vcpu, vmcs12);
9688
ff651cb6
WV		 9689 msr_entry_idx = nested_vmx_load_msr(vcpu,
9690 vmcs12->vm_entry_msr_load_addr,
9691 vmcs12->vm_entry_msr_load_count);
9692 if (msr_entry_idx) {
9693 leave_guest_mode(vcpu);
9694 vmx_load_vmcs01(vcpu);
9695 nested_vmx_entry_failure(vcpu, vmcs12,
9696 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9697 return 1;
9698 }
9699
9700 vmcs12->launch_state = 1;
9701
6dfacadd 9702 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
5cb56059 9703 return kvm_vcpu_halt(vcpu);
6dfacadd 9704
7af40ad3
JK		 9705 vmx->nested.nested_run_pending = 1;
9706
cd232ad0
NHE		 9707 /*
9708 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9709 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9710 * returned as far as L1 is concerned. It will only return (and set
9711 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9712 */
9713 return 1;
9714}
9715
4704d0be
NHE		 9716/*
9717 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9718 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9719 * This function returns the new value we should put in vmcs12.guest_cr0.
9720 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9721 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9722 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9723 * didn't trap the bit, because if L1 did, so would L0).
9724 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9725 * been modified by L2, and L1 knows it. So just leave the old value of
9726 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9727 * isn't relevant, because if L0 traps this bit it can set it to anything.
9728 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9729 * changed these bits, and therefore they need to be updated, but L0
9730 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9731 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9732 */
9733static inline unsigned long
9734vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9735{
9736 return
9737 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9738 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9739 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9740 vcpu->arch.cr0_guest_owned_bits));
9741}
9742
9743static inline unsigned long
9744vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9745{
9746 return
9747 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9748 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9749 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9750 vcpu->arch.cr4_guest_owned_bits));
9751}
9752
5f3d5799
JK		 9753static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9754 struct vmcs12 *vmcs12)
9755{
9756 u32 idt_vectoring;
9757 unsigned int nr;
9758
851eb667 9759 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 9760 nr = vcpu->arch.exception.nr;
9761 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9762
9763 if (kvm_exception_is_soft(nr)) {
9764 vmcs12->vm_exit_instruction_len =
9765 vcpu->arch.event_exit_inst_len;
9766 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9767 } else
9768 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9769
9770 if (vcpu->arch.exception.has_error_code) {
9771 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9772 vmcs12->idt_vectoring_error_code =
9773 vcpu->arch.exception.error_code;
9774 }
9775
9776 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 9777 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 9778 vmcs12->idt_vectoring_info_field =
9779 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9780 } else if (vcpu->arch.interrupt.pending) {
9781 nr = vcpu->arch.interrupt.nr;
9782 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9783
9784 if (vcpu->arch.interrupt.soft) {
9785 idt_vectoring |= INTR_TYPE_SOFT_INTR;
9786 vmcs12->vm_entry_instruction_len =
9787 vcpu->arch.event_exit_inst_len;
9788 } else
9789 idt_vectoring |= INTR_TYPE_EXT_INTR;
9790
9791 vmcs12->idt_vectoring_info_field = idt_vectoring;
9792 }
9793}
9794
b6b8a145
JK		 9795static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9796{
9797 struct vcpu_vmx *vmx = to_vmx(vcpu);
9798
f4124500
JK		 9799 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9800 vmx->nested.preemption_timer_expired) {
9801 if (vmx->nested.nested_run_pending)
9802 return -EBUSY;
9803 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9804 return 0;
9805 }
9806
b6b8a145 9807 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 9808 if (vmx->nested.nested_run_pending ||
9809 vcpu->arch.interrupt.pending)
b6b8a145
JK		 9810 return -EBUSY;
9811 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9812 NMI_VECTOR | INTR_TYPE_NMI_INTR |
9813 INTR_INFO_VALID_MASK, 0);
9814 /*
9815 * The NMI-triggered VM exit counts as injection:
9816 * clear this one and block further NMIs.
9817 */
9818 vcpu->arch.nmi_pending = 0;
9819 vmx_set_nmi_mask(vcpu, true);
9820 return 0;
9821 }
9822
9823 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9824 nested_exit_on_intr(vcpu)) {
9825 if (vmx->nested.nested_run_pending)
9826 return -EBUSY;
9827 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
705699a1 9828 return 0;
b6b8a145
JK		 9829 }
9830
705699a1 9831 return vmx_complete_nested_posted_interrupt(vcpu);
b6b8a145
JK		 9832}
9833
f4124500
JK		 9834static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9835{
9836 ktime_t remaining =
9837 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9838 u64 value;
9839
9840 if (ktime_to_ns(remaining) <= 0)
9841 return 0;
9842
9843 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9844 do_div(value, 1000000);
9845 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9846}
9847
4704d0be
NHE		 9848/*
9849 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9850 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9851 * and this function updates it to reflect the changes to the guest state while
9852 * L2 was running (and perhaps made some exits which were handled directly by L0
9853 * without going back to L1), and to reflect the exit reason.
9854 * Note that we do not have to copy here all VMCS fields, just those that
9855 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9856 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9857 * which already writes to vmcs12 directly.
9858 */
533558bc
JK		 9859static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9860 u32 exit_reason, u32 exit_intr_info,
9861 unsigned long exit_qualification)
4704d0be
NHE		 9862{
9863 /* update guest state fields: */
9864 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9865 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9866
4704d0be
NHE		 9867 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9868 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9869 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9870
9871 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9872 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9873 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9874 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9875 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9876 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9877 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9878 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9879 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9880 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9881 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9882 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9883 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9884 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9885 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9886 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9887 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9888 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9889 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9890 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9891 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9892 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9893 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9894 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9895 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9896 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9897 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9898 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9899 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9900 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9901 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9902 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9903 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9904 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9905 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9906 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9907
4704d0be
NHE		 9908 vmcs12->guest_interruptibility_info =
9909 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9910 vmcs12->guest_pending_dbg_exceptions =
9911 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 9912 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9913 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9914 else
9915 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 9916
f4124500
JK		 9917 if (nested_cpu_has_preemption_timer(vmcs12)) {
9918 if (vmcs12->vm_exit_controls &
9919 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9920 vmcs12->vmx_preemption_timer_value =
9921 vmx_get_preemption_timer_value(vcpu);
9922 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9923 }
7854cbca 9924
3633cfc3
NHE		 9925 /*
9926 * In some cases (usually, nested EPT), L2 is allowed to change its
9927 * own CR3 without exiting. If it has changed it, we must keep it.
9928 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9929 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9930 *
9931 * Additionally, restore L2's PDPTR to vmcs12.
9932 */
9933 if (enable_ept) {
9934 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9935 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9936 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9937 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9938 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9939 }
9940
608406e2
WV		 9941 if (nested_cpu_has_vid(vmcs12))
9942 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
9943
c18911a2
JK		 9944 vmcs12->vm_entry_controls =
9945 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 9946 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 9947
2996fca0
JK		 9948 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9949 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9950 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9951 }
9952
4704d0be
NHE		 9953 /* TODO: These cannot have changed unless we have MSR bitmaps and
9954 * the relevant bit asks not to trap the change */
b8c07d55 9955 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 9956 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 9957 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9958 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 9959 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9960 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9961 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 9962 if (vmx_mpx_supported())
9963 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
81dc01f7
WL		 9964 if (nested_cpu_has_xsaves(vmcs12))
9965 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
4704d0be
NHE		 9966
9967 /* update exit information fields: */
9968
533558bc
JK		 9969 vmcs12->vm_exit_reason = exit_reason;
9970 vmcs12->exit_qualification = exit_qualification;
4704d0be 9971
533558bc 9972 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 9973 if ((vmcs12->vm_exit_intr_info &
9974 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9975 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9976 vmcs12->vm_exit_intr_error_code =
9977 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 9978 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 9979 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9980 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9981
5f3d5799
JK		 9982 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9983 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9984 * instead of reading the real value. */
4704d0be 9985 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 9986
9987 /*
9988 * Transfer the event that L0 or L1 may wanted to inject into
9989 * L2 to IDT_VECTORING_INFO_FIELD.
9990 */
9991 vmcs12_save_pending_event(vcpu, vmcs12);
9992 }
9993
9994 /*
9995 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9996 * preserved above and would only end up incorrectly in L1.
9997 */
9998 vcpu->arch.nmi_injected = false;
9999 kvm_clear_exception_queue(vcpu);
10000 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 10001}
10002
10003/*
10004 * A part of what we need to when the nested L2 guest exits and we want to
10005 * run its L1 parent, is to reset L1's guest state to the host state specified
10006 * in vmcs12.
10007 * This function is to be called not only on normal nested exit, but also on
10008 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10009 * Failures During or After Loading Guest State").
10010 * This function should be called when the active VMCS is L1's (vmcs01).
10011 */
733568f9
JK		 10012static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10013 struct vmcs12 *vmcs12)
4704d0be 10014{
21feb4eb
ACL		 10015 struct kvm_segment seg;
10016
4704d0be
NHE		 10017 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10018 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 10019 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 10020 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10021 else
10022 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10023 vmx_set_efer(vcpu, vcpu->arch.efer);
10024
10025 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10026 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 10027 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 10028 /*
10029 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10030 * actually changed, because it depends on the current state of
10031 * fpu_active (which may have changed).
10032 * Note that vmx_set_cr0 refers to efer set above.
10033 */
9e3e4dbf 10034 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 10035 /*
10036 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10037 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10038 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10039 */
10040 update_exception_bitmap(vcpu);
10041 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10042 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10043
10044 /*
10045 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10046 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10047 */
10048 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10049 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10050
29bf08f1 10051 nested_ept_uninit_mmu_context(vcpu);
155a97a3 10052
4704d0be
NHE		 10053 kvm_set_cr3(vcpu, vmcs12->host_cr3);
10054 kvm_mmu_reset_context(vcpu);
10055
feaf0c7d
GN		 10056 if (!enable_ept)
10057 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10058
4704d0be
NHE		 10059 if (enable_vpid) {
10060 /*
10061 * Trivially support vpid by letting L2s share their parent
10062 * L1's vpid. TODO: move to a more elaborate solution, giving
10063 * each L2 its own vpid and exposing the vpid feature to L1.
10064 */
10065 vmx_flush_tlb(vcpu);
10066 }
10067
10068
10069 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10070 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10071 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10072 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10073 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 10074
36be0b9d
PB		 10075 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10076 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10077 vmcs_write64(GUEST_BNDCFGS, 0);
10078
44811c02 10079 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 10080 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 10081 vcpu->arch.pat = vmcs12->host_ia32_pat;
10082 }
4704d0be
NHE		 10083 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10084 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10085 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 10086
21feb4eb
ACL		 10087 /* Set L1 segment info according to Intel SDM
10088 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10089 seg = (struct kvm_segment) {
10090 .base = 0,
10091 .limit = 0xFFFFFFFF,
10092 .selector = vmcs12->host_cs_selector,
10093 .type = 11,
10094 .present = 1,
10095 .s = 1,
10096 .g = 1
10097 };
10098 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10099 seg.l = 1;
10100 else
10101 seg.db = 1;
10102 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10103 seg = (struct kvm_segment) {
10104 .base = 0,
10105 .limit = 0xFFFFFFFF,
10106 .type = 3,
10107 .present = 1,
10108 .s = 1,
10109 .db = 1,
10110 .g = 1
10111 };
10112 seg.selector = vmcs12->host_ds_selector;
10113 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10114 seg.selector = vmcs12->host_es_selector;
10115 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10116 seg.selector = vmcs12->host_ss_selector;
10117 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10118 seg.selector = vmcs12->host_fs_selector;
10119 seg.base = vmcs12->host_fs_base;
10120 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10121 seg.selector = vmcs12->host_gs_selector;
10122 seg.base = vmcs12->host_gs_base;
10123 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10124 seg = (struct kvm_segment) {
205befd9 10125 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 10126 .limit = 0x67,
10127 .selector = vmcs12->host_tr_selector,
10128 .type = 11,
10129 .present = 1
10130 };
10131 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10132
503cd0c5
JK		 10133 kvm_set_dr(vcpu, 7, 0x400);
10134 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 10135
3af18d9c
WV		 10136 if (cpu_has_vmx_msr_bitmap())
10137 vmx_set_msr_bitmap(vcpu);
10138
ff651cb6
WV		 10139 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10140 vmcs12->vm_exit_msr_load_count))
10141 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE		 10142}
10143
10144/*
10145 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10146 * and modify vmcs12 to make it see what it would expect to see there if
10147 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10148 */
533558bc
JK		 10149static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10150 u32 exit_intr_info,
10151 unsigned long exit_qualification)
4704d0be
NHE		 10152{
10153 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 10154 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10155
5f3d5799
JK		 10156 /* trying to cancel vmlaunch/vmresume is a bug */
10157 WARN_ON_ONCE(vmx->nested.nested_run_pending);
10158
4704d0be 10159 leave_guest_mode(vcpu);
533558bc
JK		 10160 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10161 exit_qualification);
4704d0be 10162
ff651cb6
WV		 10163 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10164 vmcs12->vm_exit_msr_store_count))
10165 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10166
f3380ca5
WL		 10167 vmx_load_vmcs01(vcpu);
10168
77b0f5d6
BD		 10169 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10170 && nested_exit_intr_ack_set(vcpu)) {
10171 int irq = kvm_cpu_get_interrupt(vcpu);
10172 WARN_ON(irq < 0);
10173 vmcs12->vm_exit_intr_info = irq |
10174 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10175 }
10176
542060ea
JK		 10177 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10178 vmcs12->exit_qualification,
10179 vmcs12->idt_vectoring_info_field,
10180 vmcs12->vm_exit_intr_info,
10181 vmcs12->vm_exit_intr_error_code,
10182 KVM_ISA_VMX);
4704d0be 10183
2961e876
GN		 10184 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10185 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 10186 vmx_segment_cache_clear(vmx);
10187
4704d0be
NHE		 10188 /* if no vmcs02 cache requested, remove the one we used */
10189 if (VMCS02_POOL_SIZE == 0)
10190 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10191
10192 load_vmcs12_host_state(vcpu, vmcs12);
10193
27fc51b2 10194 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 10195 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10196
10197 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10198 vmx->host_rsp = 0;
10199
10200 /* Unpin physical memory we referred to in vmcs02 */
10201 if (vmx->nested.apic_access_page) {
10202 nested_release_page(vmx->nested.apic_access_page);
48d89b92 10203 vmx->nested.apic_access_page = NULL;
4704d0be 10204 }
a7c0b07d
WL		 10205 if (vmx->nested.virtual_apic_page) {
10206 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 10207 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 10208 }
705699a1
WV		 10209 if (vmx->nested.pi_desc_page) {
10210 kunmap(vmx->nested.pi_desc_page);
10211 nested_release_page(vmx->nested.pi_desc_page);
10212 vmx->nested.pi_desc_page = NULL;
10213 vmx->nested.pi_desc = NULL;
10214 }
4704d0be 10215
38b99173
TC		 10216 /*
10217 * We are now running in L2, mmu_notifier will force to reload the
10218 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10219 */
10220 kvm_vcpu_reload_apic_access_page(vcpu);
10221
4704d0be
NHE		 10222 /*
10223 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10224 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10225 * success or failure flag accordingly.
10226 */
10227 if (unlikely(vmx->fail)) {
10228 vmx->fail = 0;
10229 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10230 } else
10231 nested_vmx_succeed(vcpu);
012f83cb
AG		 10232 if (enable_shadow_vmcs)
10233 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 10234
10235 /* in case we halted in L2 */
10236 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 10237}
10238
42124925
JK		 10239/*
10240 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10241 */
10242static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10243{
10244 if (is_guest_mode(vcpu))
533558bc 10245 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 10246 free_nested(to_vmx(vcpu));
10247}
10248
7c177938
NHE		 10249/*
10250 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10251 * 23.7 "VM-entry failures during or after loading guest state" (this also
10252 * lists the acceptable exit-reason and exit-qualification parameters).
10253 * It should only be called before L2 actually succeeded to run, and when
10254 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10255 */
10256static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10257 struct vmcs12 *vmcs12,
10258 u32 reason, unsigned long qualification)
10259{
10260 load_vmcs12_host_state(vcpu, vmcs12);
10261 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10262 vmcs12->exit_qualification = qualification;
10263 nested_vmx_succeed(vcpu);
012f83cb
AG		 10264 if (enable_shadow_vmcs)
10265 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 10266}
10267
8a76d7f2
JR		 10268static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10269 struct x86_instruction_info *info,
10270 enum x86_intercept_stage stage)
10271{
10272 return X86EMUL_CONTINUE;
10273}
10274
48d89b92 10275static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 10276{
b4a2d31d
RK		 10277 if (ple_gap)
10278 shrink_ple_window(vcpu);
ae97a3b8
RK		 10279}
10280
843e4330
KH		 10281static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10282 struct kvm_memory_slot *slot)
10283{
10284 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10285 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10286}
10287
10288static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10289 struct kvm_memory_slot *slot)
10290{
10291 kvm_mmu_slot_set_dirty(kvm, slot);
10292}
10293
10294static void vmx_flush_log_dirty(struct kvm *kvm)
10295{
10296 kvm_flush_pml_buffers(kvm);
10297}
10298
10299static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10300 struct kvm_memory_slot *memslot,
10301 gfn_t offset, unsigned long mask)
10302{
10303 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10304}
10305
cbdd1bea 10306static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 10307 .cpu_has_kvm_support = cpu_has_kvm_support,
10308 .disabled_by_bios = vmx_disabled_by_bios,
10309 .hardware_setup = hardware_setup,
10310 .hardware_unsetup = hardware_unsetup,
002c7f7c 10311 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 10312 .hardware_enable = hardware_enable,
10313 .hardware_disable = hardware_disable,
04547156 10314 .cpu_has_accelerated_tpr = report_flexpriority,
6d396b55 10315 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
6aa8b732
AK		 10316
10317 .vcpu_create = vmx_create_vcpu,
10318 .vcpu_free = vmx_free_vcpu,
04d2cc77 10319 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 10320
04d2cc77 10321 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 10322 .vcpu_load = vmx_vcpu_load,
10323 .vcpu_put = vmx_vcpu_put,
10324
c8639010 10325 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 10326 .get_msr = vmx_get_msr,
10327 .set_msr = vmx_set_msr,
10328 .get_segment_base = vmx_get_segment_base,
10329 .get_segment = vmx_get_segment,
10330 .set_segment = vmx_set_segment,
2e4d2653 10331 .get_cpl = vmx_get_cpl,
6aa8b732 10332 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 10333 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 10334 .decache_cr3 = vmx_decache_cr3,
25c4c276 10335 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 10336 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 10337 .set_cr3 = vmx_set_cr3,
10338 .set_cr4 = vmx_set_cr4,
6aa8b732 10339 .set_efer = vmx_set_efer,
6aa8b732
AK		 10340 .get_idt = vmx_get_idt,
10341 .set_idt = vmx_set_idt,
10342 .get_gdt = vmx_get_gdt,
10343 .set_gdt = vmx_set_gdt,
73aaf249
JK		 10344 .get_dr6 = vmx_get_dr6,
10345 .set_dr6 = vmx_set_dr6,
020df079 10346 .set_dr7 = vmx_set_dr7,
81908bf4 10347 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 10348 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 10349 .get_rflags = vmx_get_rflags,
10350 .set_rflags = vmx_set_rflags,
0fdd74f7 10351 .fpu_activate = vmx_fpu_activate,
02daab21 10352 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 10353
10354 .tlb_flush = vmx_flush_tlb,
6aa8b732 10355
6aa8b732 10356 .run = vmx_vcpu_run,
6062d012 10357 .handle_exit = vmx_handle_exit,
6aa8b732 10358 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 10359 .set_interrupt_shadow = vmx_set_interrupt_shadow,
10360 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 10361 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 10362 .set_irq = vmx_inject_irq,
95ba8273 10363 .set_nmi = vmx_inject_nmi,
298101da 10364 .queue_exception = vmx_queue_exception,
b463a6f7 10365 .cancel_injection = vmx_cancel_injection,
78646121 10366 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 10367 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 10368 .get_nmi_mask = vmx_get_nmi_mask,
10369 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 10370 .enable_nmi_window = enable_nmi_window,
10371 .enable_irq_window = enable_irq_window,
10372 .update_cr8_intercept = update_cr8_intercept,
8d14695f 10373 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 10374 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d50ab6c1 10375 .cpu_uses_apicv = vmx_cpu_uses_apicv,
c7c9c56c
YZ		 10376 .load_eoi_exitmap = vmx_load_eoi_exitmap,
10377 .hwapic_irr_update = vmx_hwapic_irr_update,
10378 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 10379 .sync_pir_to_irr = vmx_sync_pir_to_irr,
10380 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 10381
cbc94022 10382 .set_tss_addr = vmx_set_tss_addr,
67253af5 10383 .get_tdp_level = get_ept_level,
4b12f0de 10384 .get_mt_mask = vmx_get_mt_mask,
229456fc 10385
586f9607 10386 .get_exit_info = vmx_get_exit_info,
586f9607 10387
17cc3935 10388 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 10389
10390 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 10391
10392 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 10393 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 10394
10395 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 10396
10397 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 10398
4051b188 10399 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 10400 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 10401 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 10402 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 10403 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 10404 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 10405
10406 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 10407
10408 .check_intercept = vmx_check_intercept,
a547c6db 10409 .handle_external_intr = vmx_handle_external_intr,
da8999d3 10410 .mpx_supported = vmx_mpx_supported,
55412b2e 10411 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK		 10412
10413 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 10414
10415 .sched_in = vmx_sched_in,
843e4330
KH		 10416
10417 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10418 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10419 .flush_log_dirty = vmx_flush_log_dirty,
10420 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
25462f7f
WH		 10421
10422 .pmu_ops = &intel_pmu_ops,
6aa8b732
AK		 10423};
10424
10425static int __init vmx_init(void)
10426{
34a1cd60
TC		 10427 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10428 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 10429 if (r)
34a1cd60 10430 return r;
25c5f225 10431
2965faa5 10432#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 10433 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10434 crash_vmclear_local_loaded_vmcss);
10435#endif
10436
fdef3ad1 10437 return 0;
6aa8b732
AK		 10438}
10439
10440static void __exit vmx_exit(void)
10441{
2965faa5 10442#ifdef CONFIG_KEXEC_CORE
3b63a43f 10443 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 10444 synchronize_rcu();
10445#endif
10446
cb498ea2 10447 kvm_exit();
6aa8b732
AK		 10448}
10449
10450module_init(vmx_init)
10451module_exit(vmx_exit)
Linux 6.x block layer and io_uring tree(s)