Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
8 | * | |
9 | * Authors: | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * Yaniv Kamay <yaniv@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
17 | ||
85f455f7 | 18 | #include "irq.h" |
6aa8b732 | 19 | #include "vmx.h" |
1d737c8a | 20 | #include "mmu.h" |
e495606d | 21 | |
edf88417 | 22 | #include <linux/kvm_host.h> |
6aa8b732 | 23 | #include <linux/module.h> |
9d8f549d | 24 | #include <linux/kernel.h> |
6aa8b732 AK |
25 | #include <linux/mm.h> |
26 | #include <linux/highmem.h> | |
e8edc6e0 | 27 | #include <linux/sched.h> |
c7addb90 | 28 | #include <linux/moduleparam.h> |
e495606d | 29 | |
6aa8b732 | 30 | #include <asm/io.h> |
3b3be0d1 | 31 | #include <asm/desc.h> |
6aa8b732 | 32 | |
6aa8b732 AK |
33 | MODULE_AUTHOR("Qumranet"); |
34 | MODULE_LICENSE("GPL"); | |
35 | ||
c7addb90 AK |
36 | static int bypass_guest_pf = 1; |
37 | module_param(bypass_guest_pf, bool, 0); | |
38 | ||
2384d2b3 SY |
39 | static int enable_vpid = 1; |
40 | module_param(enable_vpid, bool, 0); | |
41 | ||
4c9fc8ef AK |
42 | static int flexpriority_enabled = 1; |
43 | module_param(flexpriority_enabled, bool, 0); | |
44 | ||
1439442c | 45 | static int enable_ept = 1; |
d56f546d SY |
46 | module_param(enable_ept, bool, 0); |
47 | ||
a2fa3e9f GH |
48 | struct vmcs { |
49 | u32 revision_id; | |
50 | u32 abort; | |
51 | char data[0]; | |
52 | }; | |
53 | ||
54 | struct vcpu_vmx { | |
fb3f0f51 | 55 | struct kvm_vcpu vcpu; |
a2fa3e9f | 56 | int launched; |
29bd8a78 | 57 | u8 fail; |
1155f76a | 58 | u32 idt_vectoring_info; |
a2fa3e9f GH |
59 | struct kvm_msr_entry *guest_msrs; |
60 | struct kvm_msr_entry *host_msrs; | |
61 | int nmsrs; | |
62 | int save_nmsrs; | |
63 | int msr_offset_efer; | |
64 | #ifdef CONFIG_X86_64 | |
65 | int msr_offset_kernel_gs_base; | |
66 | #endif | |
67 | struct vmcs *vmcs; | |
68 | struct { | |
69 | int loaded; | |
70 | u16 fs_sel, gs_sel, ldt_sel; | |
152d3f2f LV |
71 | int gs_ldt_reload_needed; |
72 | int fs_reload_needed; | |
51c6cf66 | 73 | int guest_efer_loaded; |
d77c26fc | 74 | } host_state; |
9c8cba37 AK |
75 | struct { |
76 | struct { | |
77 | bool pending; | |
78 | u8 vector; | |
79 | unsigned rip; | |
80 | } irq; | |
81 | } rmode; | |
2384d2b3 | 82 | int vpid; |
a2fa3e9f GH |
83 | }; |
84 | ||
85 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) | |
86 | { | |
fb3f0f51 | 87 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
88 | } |
89 | ||
b7ebfb05 | 90 | static int init_rmode(struct kvm *kvm); |
75880a01 | 91 | |
6aa8b732 AK |
92 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
93 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
94 | ||
fdef3ad1 HQ |
95 | static struct page *vmx_io_bitmap_a; |
96 | static struct page *vmx_io_bitmap_b; | |
25c5f225 | 97 | static struct page *vmx_msr_bitmap; |
fdef3ad1 | 98 | |
2384d2b3 SY |
99 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
100 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
101 | ||
1c3d14fe | 102 | static struct vmcs_config { |
6aa8b732 AK |
103 | int size; |
104 | int order; | |
105 | u32 revision_id; | |
1c3d14fe YS |
106 | u32 pin_based_exec_ctrl; |
107 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 108 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
109 | u32 vmexit_ctrl; |
110 | u32 vmentry_ctrl; | |
111 | } vmcs_config; | |
6aa8b732 | 112 | |
d56f546d SY |
113 | struct vmx_capability { |
114 | u32 ept; | |
115 | u32 vpid; | |
116 | } vmx_capability; | |
117 | ||
6aa8b732 AK |
118 | #define VMX_SEGMENT_FIELD(seg) \ |
119 | [VCPU_SREG_##seg] = { \ | |
120 | .selector = GUEST_##seg##_SELECTOR, \ | |
121 | .base = GUEST_##seg##_BASE, \ | |
122 | .limit = GUEST_##seg##_LIMIT, \ | |
123 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
124 | } | |
125 | ||
126 | static struct kvm_vmx_segment_field { | |
127 | unsigned selector; | |
128 | unsigned base; | |
129 | unsigned limit; | |
130 | unsigned ar_bytes; | |
131 | } kvm_vmx_segment_fields[] = { | |
132 | VMX_SEGMENT_FIELD(CS), | |
133 | VMX_SEGMENT_FIELD(DS), | |
134 | VMX_SEGMENT_FIELD(ES), | |
135 | VMX_SEGMENT_FIELD(FS), | |
136 | VMX_SEGMENT_FIELD(GS), | |
137 | VMX_SEGMENT_FIELD(SS), | |
138 | VMX_SEGMENT_FIELD(TR), | |
139 | VMX_SEGMENT_FIELD(LDTR), | |
140 | }; | |
141 | ||
4d56c8a7 AK |
142 | /* |
143 | * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it | |
144 | * away by decrementing the array size. | |
145 | */ | |
6aa8b732 | 146 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 147 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
148 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE, |
149 | #endif | |
150 | MSR_EFER, MSR_K6_STAR, | |
151 | }; | |
9d8f549d | 152 | #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index) |
6aa8b732 | 153 | |
a2fa3e9f GH |
154 | static void load_msrs(struct kvm_msr_entry *e, int n) |
155 | { | |
156 | int i; | |
157 | ||
158 | for (i = 0; i < n; ++i) | |
159 | wrmsrl(e[i].index, e[i].data); | |
160 | } | |
161 | ||
162 | static void save_msrs(struct kvm_msr_entry *e, int n) | |
163 | { | |
164 | int i; | |
165 | ||
166 | for (i = 0; i < n; ++i) | |
167 | rdmsrl(e[i].index, e[i].data); | |
168 | } | |
169 | ||
6aa8b732 AK |
170 | static inline int is_page_fault(u32 intr_info) |
171 | { | |
172 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
173 | INTR_INFO_VALID_MASK)) == | |
174 | (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK); | |
175 | } | |
176 | ||
2ab455cc AL |
177 | static inline int is_no_device(u32 intr_info) |
178 | { | |
179 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
180 | INTR_INFO_VALID_MASK)) == | |
181 | (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK); | |
182 | } | |
183 | ||
7aa81cc0 AL |
184 | static inline int is_invalid_opcode(u32 intr_info) |
185 | { | |
186 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
187 | INTR_INFO_VALID_MASK)) == | |
188 | (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK); | |
189 | } | |
190 | ||
6aa8b732 AK |
191 | static inline int is_external_interrupt(u32 intr_info) |
192 | { | |
193 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
194 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
195 | } | |
196 | ||
25c5f225 SY |
197 | static inline int cpu_has_vmx_msr_bitmap(void) |
198 | { | |
199 | return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS); | |
200 | } | |
201 | ||
6e5d865c YS |
202 | static inline int cpu_has_vmx_tpr_shadow(void) |
203 | { | |
204 | return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW); | |
205 | } | |
206 | ||
207 | static inline int vm_need_tpr_shadow(struct kvm *kvm) | |
208 | { | |
209 | return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm))); | |
210 | } | |
211 | ||
f78e0e2e SY |
212 | static inline int cpu_has_secondary_exec_ctrls(void) |
213 | { | |
214 | return (vmcs_config.cpu_based_exec_ctrl & | |
215 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS); | |
216 | } | |
217 | ||
774ead3a | 218 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 219 | { |
4c9fc8ef AK |
220 | return flexpriority_enabled |
221 | && (vmcs_config.cpu_based_2nd_exec_ctrl & | |
222 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
f78e0e2e SY |
223 | } |
224 | ||
d56f546d SY |
225 | static inline int cpu_has_vmx_invept_individual_addr(void) |
226 | { | |
227 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT)); | |
228 | } | |
229 | ||
230 | static inline int cpu_has_vmx_invept_context(void) | |
231 | { | |
232 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT)); | |
233 | } | |
234 | ||
235 | static inline int cpu_has_vmx_invept_global(void) | |
236 | { | |
237 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT)); | |
238 | } | |
239 | ||
240 | static inline int cpu_has_vmx_ept(void) | |
241 | { | |
242 | return (vmcs_config.cpu_based_2nd_exec_ctrl & | |
243 | SECONDARY_EXEC_ENABLE_EPT); | |
244 | } | |
245 | ||
246 | static inline int vm_need_ept(void) | |
247 | { | |
248 | return (cpu_has_vmx_ept() && enable_ept); | |
249 | } | |
250 | ||
f78e0e2e SY |
251 | static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm) |
252 | { | |
253 | return ((cpu_has_vmx_virtualize_apic_accesses()) && | |
254 | (irqchip_in_kernel(kvm))); | |
255 | } | |
256 | ||
2384d2b3 SY |
257 | static inline int cpu_has_vmx_vpid(void) |
258 | { | |
259 | return (vmcs_config.cpu_based_2nd_exec_ctrl & | |
260 | SECONDARY_EXEC_ENABLE_VPID); | |
261 | } | |
262 | ||
8b9cf98c | 263 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
264 | { |
265 | int i; | |
266 | ||
a2fa3e9f GH |
267 | for (i = 0; i < vmx->nmsrs; ++i) |
268 | if (vmx->guest_msrs[i].index == msr) | |
a75beee6 ED |
269 | return i; |
270 | return -1; | |
271 | } | |
272 | ||
2384d2b3 SY |
273 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
274 | { | |
275 | struct { | |
276 | u64 vpid : 16; | |
277 | u64 rsvd : 48; | |
278 | u64 gva; | |
279 | } operand = { vpid, 0, gva }; | |
280 | ||
281 | asm volatile (ASM_VMX_INVVPID | |
282 | /* CF==1 or ZF==1 --> rc = -1 */ | |
283 | "; ja 1f ; ud2 ; 1:" | |
284 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
285 | } | |
286 | ||
1439442c SY |
287 | static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
288 | { | |
289 | struct { | |
290 | u64 eptp, gpa; | |
291 | } operand = {eptp, gpa}; | |
292 | ||
293 | asm volatile (ASM_VMX_INVEPT | |
294 | /* CF==1 or ZF==1 --> rc = -1 */ | |
295 | "; ja 1f ; ud2 ; 1:\n" | |
296 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
297 | } | |
298 | ||
8b9cf98c | 299 | static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
300 | { |
301 | int i; | |
302 | ||
8b9cf98c | 303 | i = __find_msr_index(vmx, msr); |
a75beee6 | 304 | if (i >= 0) |
a2fa3e9f | 305 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 306 | return NULL; |
7725f0ba AK |
307 | } |
308 | ||
6aa8b732 AK |
309 | static void vmcs_clear(struct vmcs *vmcs) |
310 | { | |
311 | u64 phys_addr = __pa(vmcs); | |
312 | u8 error; | |
313 | ||
314 | asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0" | |
315 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) | |
316 | : "cc", "memory"); | |
317 | if (error) | |
318 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
319 | vmcs, phys_addr); | |
320 | } | |
321 | ||
322 | static void __vcpu_clear(void *arg) | |
323 | { | |
8b9cf98c | 324 | struct vcpu_vmx *vmx = arg; |
d3b2c338 | 325 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 326 | |
8b9cf98c | 327 | if (vmx->vcpu.cpu == cpu) |
a2fa3e9f GH |
328 | vmcs_clear(vmx->vmcs); |
329 | if (per_cpu(current_vmcs, cpu) == vmx->vmcs) | |
6aa8b732 | 330 | per_cpu(current_vmcs, cpu) = NULL; |
ad312c7c | 331 | rdtscll(vmx->vcpu.arch.host_tsc); |
6aa8b732 AK |
332 | } |
333 | ||
8b9cf98c | 334 | static void vcpu_clear(struct vcpu_vmx *vmx) |
8d0be2b3 | 335 | { |
eae5ecb5 AK |
336 | if (vmx->vcpu.cpu == -1) |
337 | return; | |
8691e5a8 | 338 | smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1); |
8b9cf98c | 339 | vmx->launched = 0; |
8d0be2b3 AK |
340 | } |
341 | ||
2384d2b3 SY |
342 | static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx) |
343 | { | |
344 | if (vmx->vpid == 0) | |
345 | return; | |
346 | ||
347 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0); | |
348 | } | |
349 | ||
1439442c SY |
350 | static inline void ept_sync_global(void) |
351 | { | |
352 | if (cpu_has_vmx_invept_global()) | |
353 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); | |
354 | } | |
355 | ||
356 | static inline void ept_sync_context(u64 eptp) | |
357 | { | |
358 | if (vm_need_ept()) { | |
359 | if (cpu_has_vmx_invept_context()) | |
360 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
361 | else | |
362 | ept_sync_global(); | |
363 | } | |
364 | } | |
365 | ||
366 | static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa) | |
367 | { | |
368 | if (vm_need_ept()) { | |
369 | if (cpu_has_vmx_invept_individual_addr()) | |
370 | __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR, | |
371 | eptp, gpa); | |
372 | else | |
373 | ept_sync_context(eptp); | |
374 | } | |
375 | } | |
376 | ||
6aa8b732 AK |
377 | static unsigned long vmcs_readl(unsigned long field) |
378 | { | |
379 | unsigned long value; | |
380 | ||
381 | asm volatile (ASM_VMX_VMREAD_RDX_RAX | |
382 | : "=a"(value) : "d"(field) : "cc"); | |
383 | return value; | |
384 | } | |
385 | ||
386 | static u16 vmcs_read16(unsigned long field) | |
387 | { | |
388 | return vmcs_readl(field); | |
389 | } | |
390 | ||
391 | static u32 vmcs_read32(unsigned long field) | |
392 | { | |
393 | return vmcs_readl(field); | |
394 | } | |
395 | ||
396 | static u64 vmcs_read64(unsigned long field) | |
397 | { | |
05b3e0c2 | 398 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
399 | return vmcs_readl(field); |
400 | #else | |
401 | return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32); | |
402 | #endif | |
403 | } | |
404 | ||
e52de1b8 AK |
405 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
406 | { | |
407 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
408 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
409 | dump_stack(); | |
410 | } | |
411 | ||
6aa8b732 AK |
412 | static void vmcs_writel(unsigned long field, unsigned long value) |
413 | { | |
414 | u8 error; | |
415 | ||
416 | asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0" | |
d77c26fc | 417 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
418 | if (unlikely(error)) |
419 | vmwrite_error(field, value); | |
6aa8b732 AK |
420 | } |
421 | ||
422 | static void vmcs_write16(unsigned long field, u16 value) | |
423 | { | |
424 | vmcs_writel(field, value); | |
425 | } | |
426 | ||
427 | static void vmcs_write32(unsigned long field, u32 value) | |
428 | { | |
429 | vmcs_writel(field, value); | |
430 | } | |
431 | ||
432 | static void vmcs_write64(unsigned long field, u64 value) | |
433 | { | |
05b3e0c2 | 434 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
435 | vmcs_writel(field, value); |
436 | #else | |
437 | vmcs_writel(field, value); | |
438 | asm volatile (""); | |
439 | vmcs_writel(field+1, value >> 32); | |
440 | #endif | |
441 | } | |
442 | ||
2ab455cc AL |
443 | static void vmcs_clear_bits(unsigned long field, u32 mask) |
444 | { | |
445 | vmcs_writel(field, vmcs_readl(field) & ~mask); | |
446 | } | |
447 | ||
448 | static void vmcs_set_bits(unsigned long field, u32 mask) | |
449 | { | |
450 | vmcs_writel(field, vmcs_readl(field) | mask); | |
451 | } | |
452 | ||
abd3f2d6 AK |
453 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
454 | { | |
455 | u32 eb; | |
456 | ||
7aa81cc0 | 457 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR); |
abd3f2d6 AK |
458 | if (!vcpu->fpu_active) |
459 | eb |= 1u << NM_VECTOR; | |
460 | if (vcpu->guest_debug.enabled) | |
461 | eb |= 1u << 1; | |
ad312c7c | 462 | if (vcpu->arch.rmode.active) |
abd3f2d6 | 463 | eb = ~0; |
1439442c SY |
464 | if (vm_need_ept()) |
465 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ | |
abd3f2d6 AK |
466 | vmcs_write32(EXCEPTION_BITMAP, eb); |
467 | } | |
468 | ||
33ed6329 AK |
469 | static void reload_tss(void) |
470 | { | |
33ed6329 AK |
471 | /* |
472 | * VT restores TR but not its size. Useless. | |
473 | */ | |
474 | struct descriptor_table gdt; | |
a5f61300 | 475 | struct desc_struct *descs; |
33ed6329 AK |
476 | |
477 | get_gdt(&gdt); | |
478 | descs = (void *)gdt.base; | |
479 | descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ | |
480 | load_TR_desc(); | |
33ed6329 AK |
481 | } |
482 | ||
8b9cf98c | 483 | static void load_transition_efer(struct vcpu_vmx *vmx) |
2cc51560 | 484 | { |
a2fa3e9f | 485 | int efer_offset = vmx->msr_offset_efer; |
51c6cf66 AK |
486 | u64 host_efer = vmx->host_msrs[efer_offset].data; |
487 | u64 guest_efer = vmx->guest_msrs[efer_offset].data; | |
488 | u64 ignore_bits; | |
489 | ||
490 | if (efer_offset < 0) | |
491 | return; | |
492 | /* | |
493 | * NX is emulated; LMA and LME handled by hardware; SCE meaninless | |
494 | * outside long mode | |
495 | */ | |
496 | ignore_bits = EFER_NX | EFER_SCE; | |
497 | #ifdef CONFIG_X86_64 | |
498 | ignore_bits |= EFER_LMA | EFER_LME; | |
499 | /* SCE is meaningful only in long mode on Intel */ | |
500 | if (guest_efer & EFER_LMA) | |
501 | ignore_bits &= ~(u64)EFER_SCE; | |
502 | #endif | |
503 | if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits)) | |
504 | return; | |
2cc51560 | 505 | |
51c6cf66 AK |
506 | vmx->host_state.guest_efer_loaded = 1; |
507 | guest_efer &= ~ignore_bits; | |
508 | guest_efer |= host_efer & ignore_bits; | |
509 | wrmsrl(MSR_EFER, guest_efer); | |
8b9cf98c | 510 | vmx->vcpu.stat.efer_reload++; |
2cc51560 ED |
511 | } |
512 | ||
51c6cf66 AK |
513 | static void reload_host_efer(struct vcpu_vmx *vmx) |
514 | { | |
515 | if (vmx->host_state.guest_efer_loaded) { | |
516 | vmx->host_state.guest_efer_loaded = 0; | |
517 | load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1); | |
518 | } | |
519 | } | |
520 | ||
04d2cc77 | 521 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 522 | { |
04d2cc77 AK |
523 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
524 | ||
a2fa3e9f | 525 | if (vmx->host_state.loaded) |
33ed6329 AK |
526 | return; |
527 | ||
a2fa3e9f | 528 | vmx->host_state.loaded = 1; |
33ed6329 AK |
529 | /* |
530 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
531 | * allow segment selectors with cpl > 0 or ti == 1. | |
532 | */ | |
a2fa3e9f | 533 | vmx->host_state.ldt_sel = read_ldt(); |
152d3f2f | 534 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
a2fa3e9f | 535 | vmx->host_state.fs_sel = read_fs(); |
152d3f2f | 536 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 537 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
538 | vmx->host_state.fs_reload_needed = 0; |
539 | } else { | |
33ed6329 | 540 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 541 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 542 | } |
a2fa3e9f GH |
543 | vmx->host_state.gs_sel = read_gs(); |
544 | if (!(vmx->host_state.gs_sel & 7)) | |
545 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
546 | else { |
547 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 548 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
549 | } |
550 | ||
551 | #ifdef CONFIG_X86_64 | |
552 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
553 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
554 | #else | |
a2fa3e9f GH |
555 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
556 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 557 | #endif |
707c0874 AK |
558 | |
559 | #ifdef CONFIG_X86_64 | |
d77c26fc | 560 | if (is_long_mode(&vmx->vcpu)) |
a2fa3e9f GH |
561 | save_msrs(vmx->host_msrs + |
562 | vmx->msr_offset_kernel_gs_base, 1); | |
d77c26fc | 563 | |
707c0874 | 564 | #endif |
a2fa3e9f | 565 | load_msrs(vmx->guest_msrs, vmx->save_nmsrs); |
51c6cf66 | 566 | load_transition_efer(vmx); |
33ed6329 AK |
567 | } |
568 | ||
a9b21b62 | 569 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 570 | { |
15ad7146 | 571 | unsigned long flags; |
33ed6329 | 572 | |
a2fa3e9f | 573 | if (!vmx->host_state.loaded) |
33ed6329 AK |
574 | return; |
575 | ||
e1beb1d3 | 576 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 577 | vmx->host_state.loaded = 0; |
152d3f2f | 578 | if (vmx->host_state.fs_reload_needed) |
a2fa3e9f | 579 | load_fs(vmx->host_state.fs_sel); |
152d3f2f LV |
580 | if (vmx->host_state.gs_ldt_reload_needed) { |
581 | load_ldt(vmx->host_state.ldt_sel); | |
33ed6329 AK |
582 | /* |
583 | * If we have to reload gs, we must take care to | |
584 | * preserve our gs base. | |
585 | */ | |
15ad7146 | 586 | local_irq_save(flags); |
a2fa3e9f | 587 | load_gs(vmx->host_state.gs_sel); |
33ed6329 AK |
588 | #ifdef CONFIG_X86_64 |
589 | wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE)); | |
590 | #endif | |
15ad7146 | 591 | local_irq_restore(flags); |
33ed6329 | 592 | } |
152d3f2f | 593 | reload_tss(); |
a2fa3e9f GH |
594 | save_msrs(vmx->guest_msrs, vmx->save_nmsrs); |
595 | load_msrs(vmx->host_msrs, vmx->save_nmsrs); | |
51c6cf66 | 596 | reload_host_efer(vmx); |
33ed6329 AK |
597 | } |
598 | ||
a9b21b62 AK |
599 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
600 | { | |
601 | preempt_disable(); | |
602 | __vmx_load_host_state(vmx); | |
603 | preempt_enable(); | |
604 | } | |
605 | ||
6aa8b732 AK |
606 | /* |
607 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
608 | * vcpu mutex is already taken. | |
609 | */ | |
15ad7146 | 610 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 611 | { |
a2fa3e9f GH |
612 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
613 | u64 phys_addr = __pa(vmx->vmcs); | |
019960ae | 614 | u64 tsc_this, delta, new_offset; |
6aa8b732 | 615 | |
a3d7f85f | 616 | if (vcpu->cpu != cpu) { |
8b9cf98c | 617 | vcpu_clear(vmx); |
2f599714 | 618 | kvm_migrate_timers(vcpu); |
2384d2b3 | 619 | vpid_sync_vcpu_all(vmx); |
a3d7f85f | 620 | } |
6aa8b732 | 621 | |
a2fa3e9f | 622 | if (per_cpu(current_vmcs, cpu) != vmx->vmcs) { |
6aa8b732 AK |
623 | u8 error; |
624 | ||
a2fa3e9f | 625 | per_cpu(current_vmcs, cpu) = vmx->vmcs; |
6aa8b732 AK |
626 | asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0" |
627 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) | |
628 | : "cc"); | |
629 | if (error) | |
630 | printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n", | |
a2fa3e9f | 631 | vmx->vmcs, phys_addr); |
6aa8b732 AK |
632 | } |
633 | ||
634 | if (vcpu->cpu != cpu) { | |
635 | struct descriptor_table dt; | |
636 | unsigned long sysenter_esp; | |
637 | ||
638 | vcpu->cpu = cpu; | |
639 | /* | |
640 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
641 | * processors. | |
642 | */ | |
643 | vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */ | |
644 | get_gdt(&dt); | |
645 | vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */ | |
646 | ||
647 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
648 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
7700270e AK |
649 | |
650 | /* | |
651 | * Make sure the time stamp counter is monotonous. | |
652 | */ | |
653 | rdtscll(tsc_this); | |
019960ae AK |
654 | if (tsc_this < vcpu->arch.host_tsc) { |
655 | delta = vcpu->arch.host_tsc - tsc_this; | |
656 | new_offset = vmcs_read64(TSC_OFFSET) + delta; | |
657 | vmcs_write64(TSC_OFFSET, new_offset); | |
658 | } | |
6aa8b732 | 659 | } |
6aa8b732 AK |
660 | } |
661 | ||
662 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
663 | { | |
a9b21b62 | 664 | __vmx_load_host_state(to_vmx(vcpu)); |
6aa8b732 AK |
665 | } |
666 | ||
5fd86fcf AK |
667 | static void vmx_fpu_activate(struct kvm_vcpu *vcpu) |
668 | { | |
669 | if (vcpu->fpu_active) | |
670 | return; | |
671 | vcpu->fpu_active = 1; | |
707d92fa | 672 | vmcs_clear_bits(GUEST_CR0, X86_CR0_TS); |
ad312c7c | 673 | if (vcpu->arch.cr0 & X86_CR0_TS) |
707d92fa | 674 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS); |
5fd86fcf AK |
675 | update_exception_bitmap(vcpu); |
676 | } | |
677 | ||
678 | static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu) | |
679 | { | |
680 | if (!vcpu->fpu_active) | |
681 | return; | |
682 | vcpu->fpu_active = 0; | |
707d92fa | 683 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS); |
5fd86fcf AK |
684 | update_exception_bitmap(vcpu); |
685 | } | |
686 | ||
774c47f1 AK |
687 | static void vmx_vcpu_decache(struct kvm_vcpu *vcpu) |
688 | { | |
8b9cf98c | 689 | vcpu_clear(to_vmx(vcpu)); |
774c47f1 AK |
690 | } |
691 | ||
6aa8b732 AK |
692 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
693 | { | |
694 | return vmcs_readl(GUEST_RFLAGS); | |
695 | } | |
696 | ||
697 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
698 | { | |
ad312c7c | 699 | if (vcpu->arch.rmode.active) |
053de044 | 700 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
701 | vmcs_writel(GUEST_RFLAGS, rflags); |
702 | } | |
703 | ||
704 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
705 | { | |
706 | unsigned long rip; | |
707 | u32 interruptibility; | |
708 | ||
709 | rip = vmcs_readl(GUEST_RIP); | |
710 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
711 | vmcs_writel(GUEST_RIP, rip); | |
712 | ||
713 | /* | |
714 | * We emulated an instruction, so temporary interrupt blocking | |
715 | * should be removed, if set. | |
716 | */ | |
717 | interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
718 | if (interruptibility & 3) | |
719 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
720 | interruptibility & ~3); | |
ad312c7c | 721 | vcpu->arch.interrupt_window_open = 1; |
6aa8b732 AK |
722 | } |
723 | ||
298101da AK |
724 | static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
725 | bool has_error_code, u32 error_code) | |
726 | { | |
727 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
728 | nr | INTR_TYPE_EXCEPTION | |
2e11384c | 729 | | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0) |
298101da AK |
730 | | INTR_INFO_VALID_MASK); |
731 | if (has_error_code) | |
732 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); | |
733 | } | |
734 | ||
735 | static bool vmx_exception_injected(struct kvm_vcpu *vcpu) | |
736 | { | |
737 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
738 | ||
739 | return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | |
740 | } | |
741 | ||
a75beee6 ED |
742 | /* |
743 | * Swap MSR entry in host/guest MSR entry array. | |
744 | */ | |
54e11fa1 | 745 | #ifdef CONFIG_X86_64 |
8b9cf98c | 746 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 747 | { |
a2fa3e9f GH |
748 | struct kvm_msr_entry tmp; |
749 | ||
750 | tmp = vmx->guest_msrs[to]; | |
751 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
752 | vmx->guest_msrs[from] = tmp; | |
753 | tmp = vmx->host_msrs[to]; | |
754 | vmx->host_msrs[to] = vmx->host_msrs[from]; | |
755 | vmx->host_msrs[from] = tmp; | |
a75beee6 | 756 | } |
54e11fa1 | 757 | #endif |
a75beee6 | 758 | |
e38aea3e AK |
759 | /* |
760 | * Set up the vmcs to automatically save and restore system | |
761 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
762 | * mode, as fiddling with msrs is very expensive. | |
763 | */ | |
8b9cf98c | 764 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 765 | { |
2cc51560 | 766 | int save_nmsrs; |
e38aea3e | 767 | |
33f9c505 | 768 | vmx_load_host_state(vmx); |
a75beee6 ED |
769 | save_nmsrs = 0; |
770 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 771 | if (is_long_mode(&vmx->vcpu)) { |
2cc51560 ED |
772 | int index; |
773 | ||
8b9cf98c | 774 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 775 | if (index >= 0) |
8b9cf98c RR |
776 | move_msr_up(vmx, index, save_nmsrs++); |
777 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 778 | if (index >= 0) |
8b9cf98c RR |
779 | move_msr_up(vmx, index, save_nmsrs++); |
780 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 781 | if (index >= 0) |
8b9cf98c RR |
782 | move_msr_up(vmx, index, save_nmsrs++); |
783 | index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE); | |
a75beee6 | 784 | if (index >= 0) |
8b9cf98c | 785 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
786 | /* |
787 | * MSR_K6_STAR is only needed on long mode guests, and only | |
788 | * if efer.sce is enabled. | |
789 | */ | |
8b9cf98c | 790 | index = __find_msr_index(vmx, MSR_K6_STAR); |
ad312c7c | 791 | if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE)) |
8b9cf98c | 792 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
793 | } |
794 | #endif | |
a2fa3e9f | 795 | vmx->save_nmsrs = save_nmsrs; |
e38aea3e | 796 | |
4d56c8a7 | 797 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 798 | vmx->msr_offset_kernel_gs_base = |
8b9cf98c | 799 | __find_msr_index(vmx, MSR_KERNEL_GS_BASE); |
4d56c8a7 | 800 | #endif |
8b9cf98c | 801 | vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER); |
e38aea3e AK |
802 | } |
803 | ||
6aa8b732 AK |
804 | /* |
805 | * reads and returns guest's timestamp counter "register" | |
806 | * guest_tsc = host_tsc + tsc_offset -- 21.3 | |
807 | */ | |
808 | static u64 guest_read_tsc(void) | |
809 | { | |
810 | u64 host_tsc, tsc_offset; | |
811 | ||
812 | rdtscll(host_tsc); | |
813 | tsc_offset = vmcs_read64(TSC_OFFSET); | |
814 | return host_tsc + tsc_offset; | |
815 | } | |
816 | ||
817 | /* | |
818 | * writes 'guest_tsc' into guest's timestamp counter "register" | |
819 | * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc | |
820 | */ | |
821 | static void guest_write_tsc(u64 guest_tsc) | |
822 | { | |
823 | u64 host_tsc; | |
824 | ||
825 | rdtscll(host_tsc); | |
826 | vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc); | |
827 | } | |
828 | ||
6aa8b732 AK |
829 | /* |
830 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
831 | * Returns 0 on success, non-0 otherwise. | |
832 | * Assumes vcpu_load() was already called. | |
833 | */ | |
834 | static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
835 | { | |
836 | u64 data; | |
a2fa3e9f | 837 | struct kvm_msr_entry *msr; |
6aa8b732 AK |
838 | |
839 | if (!pdata) { | |
840 | printk(KERN_ERR "BUG: get_msr called with NULL pdata\n"); | |
841 | return -EINVAL; | |
842 | } | |
843 | ||
844 | switch (msr_index) { | |
05b3e0c2 | 845 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
846 | case MSR_FS_BASE: |
847 | data = vmcs_readl(GUEST_FS_BASE); | |
848 | break; | |
849 | case MSR_GS_BASE: | |
850 | data = vmcs_readl(GUEST_GS_BASE); | |
851 | break; | |
852 | case MSR_EFER: | |
3bab1f5d | 853 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
854 | #endif |
855 | case MSR_IA32_TIME_STAMP_COUNTER: | |
856 | data = guest_read_tsc(); | |
857 | break; | |
858 | case MSR_IA32_SYSENTER_CS: | |
859 | data = vmcs_read32(GUEST_SYSENTER_CS); | |
860 | break; | |
861 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 862 | data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
863 | break; |
864 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 865 | data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 866 | break; |
6aa8b732 | 867 | default: |
8b9cf98c | 868 | msr = find_msr_entry(to_vmx(vcpu), msr_index); |
3bab1f5d AK |
869 | if (msr) { |
870 | data = msr->data; | |
871 | break; | |
6aa8b732 | 872 | } |
3bab1f5d | 873 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
874 | } |
875 | ||
876 | *pdata = data; | |
877 | return 0; | |
878 | } | |
879 | ||
880 | /* | |
881 | * Writes msr value into into the appropriate "register". | |
882 | * Returns 0 on success, non-0 otherwise. | |
883 | * Assumes vcpu_load() was already called. | |
884 | */ | |
885 | static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
886 | { | |
a2fa3e9f GH |
887 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
888 | struct kvm_msr_entry *msr; | |
2cc51560 ED |
889 | int ret = 0; |
890 | ||
6aa8b732 | 891 | switch (msr_index) { |
05b3e0c2 | 892 | #ifdef CONFIG_X86_64 |
3bab1f5d | 893 | case MSR_EFER: |
a9b21b62 | 894 | vmx_load_host_state(vmx); |
2cc51560 | 895 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
2cc51560 | 896 | break; |
6aa8b732 AK |
897 | case MSR_FS_BASE: |
898 | vmcs_writel(GUEST_FS_BASE, data); | |
899 | break; | |
900 | case MSR_GS_BASE: | |
901 | vmcs_writel(GUEST_GS_BASE, data); | |
902 | break; | |
903 | #endif | |
904 | case MSR_IA32_SYSENTER_CS: | |
905 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
906 | break; | |
907 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 908 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
909 | break; |
910 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 911 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 912 | break; |
d27d4aca | 913 | case MSR_IA32_TIME_STAMP_COUNTER: |
6aa8b732 AK |
914 | guest_write_tsc(data); |
915 | break; | |
6aa8b732 | 916 | default: |
a9b21b62 | 917 | vmx_load_host_state(vmx); |
8b9cf98c | 918 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d AK |
919 | if (msr) { |
920 | msr->data = data; | |
921 | break; | |
6aa8b732 | 922 | } |
2cc51560 | 923 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
6aa8b732 AK |
924 | } |
925 | ||
2cc51560 | 926 | return ret; |
6aa8b732 AK |
927 | } |
928 | ||
929 | /* | |
930 | * Sync the rsp and rip registers into the vcpu structure. This allows | |
ad312c7c | 931 | * registers to be accessed by indexing vcpu->arch.regs. |
6aa8b732 AK |
932 | */ |
933 | static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu) | |
934 | { | |
ad312c7c ZX |
935 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); |
936 | vcpu->arch.rip = vmcs_readl(GUEST_RIP); | |
6aa8b732 AK |
937 | } |
938 | ||
939 | /* | |
940 | * Syncs rsp and rip back into the vmcs. Should be called after possible | |
941 | * modification. | |
942 | */ | |
943 | static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu) | |
944 | { | |
ad312c7c ZX |
945 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); |
946 | vmcs_writel(GUEST_RIP, vcpu->arch.rip); | |
6aa8b732 AK |
947 | } |
948 | ||
949 | static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
950 | { | |
951 | unsigned long dr7 = 0x400; | |
6aa8b732 AK |
952 | int old_singlestep; |
953 | ||
6aa8b732 AK |
954 | old_singlestep = vcpu->guest_debug.singlestep; |
955 | ||
956 | vcpu->guest_debug.enabled = dbg->enabled; | |
957 | if (vcpu->guest_debug.enabled) { | |
958 | int i; | |
959 | ||
960 | dr7 |= 0x200; /* exact */ | |
961 | for (i = 0; i < 4; ++i) { | |
962 | if (!dbg->breakpoints[i].enabled) | |
963 | continue; | |
964 | vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address; | |
965 | dr7 |= 2 << (i*2); /* global enable */ | |
966 | dr7 |= 0 << (i*4+16); /* execution breakpoint */ | |
967 | } | |
968 | ||
6aa8b732 | 969 | vcpu->guest_debug.singlestep = dbg->singlestep; |
abd3f2d6 | 970 | } else |
6aa8b732 | 971 | vcpu->guest_debug.singlestep = 0; |
6aa8b732 AK |
972 | |
973 | if (old_singlestep && !vcpu->guest_debug.singlestep) { | |
974 | unsigned long flags; | |
975 | ||
976 | flags = vmcs_readl(GUEST_RFLAGS); | |
977 | flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
978 | vmcs_writel(GUEST_RFLAGS, flags); | |
979 | } | |
980 | ||
abd3f2d6 | 981 | update_exception_bitmap(vcpu); |
6aa8b732 AK |
982 | vmcs_writel(GUEST_DR7, dr7); |
983 | ||
984 | return 0; | |
985 | } | |
986 | ||
2a8067f1 ED |
987 | static int vmx_get_irq(struct kvm_vcpu *vcpu) |
988 | { | |
1155f76a | 989 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2a8067f1 ED |
990 | u32 idtv_info_field; |
991 | ||
1155f76a | 992 | idtv_info_field = vmx->idt_vectoring_info; |
2a8067f1 ED |
993 | if (idtv_info_field & INTR_INFO_VALID_MASK) { |
994 | if (is_external_interrupt(idtv_info_field)) | |
995 | return idtv_info_field & VECTORING_INFO_VECTOR_MASK; | |
996 | else | |
d77c26fc | 997 | printk(KERN_DEBUG "pending exception: not handled yet\n"); |
2a8067f1 ED |
998 | } |
999 | return -1; | |
1000 | } | |
1001 | ||
6aa8b732 AK |
1002 | static __init int cpu_has_kvm_support(void) |
1003 | { | |
1004 | unsigned long ecx = cpuid_ecx(1); | |
1005 | return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */ | |
1006 | } | |
1007 | ||
1008 | static __init int vmx_disabled_by_bios(void) | |
1009 | { | |
1010 | u64 msr; | |
1011 | ||
1012 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
62b3ffb8 YS |
1013 | return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED | |
1014 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED)) | |
1015 | == MSR_IA32_FEATURE_CONTROL_LOCKED; | |
1016 | /* locked but not enabled */ | |
6aa8b732 AK |
1017 | } |
1018 | ||
774c47f1 | 1019 | static void hardware_enable(void *garbage) |
6aa8b732 AK |
1020 | { |
1021 | int cpu = raw_smp_processor_id(); | |
1022 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
1023 | u64 old; | |
1024 | ||
1025 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); | |
62b3ffb8 YS |
1026 | if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED | |
1027 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED)) | |
1028 | != (MSR_IA32_FEATURE_CONTROL_LOCKED | | |
1029 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED)) | |
6aa8b732 | 1030 | /* enable and lock */ |
62b3ffb8 YS |
1031 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | |
1032 | MSR_IA32_FEATURE_CONTROL_LOCKED | | |
1033 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED); | |
66aee91a | 1034 | write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */ |
6aa8b732 AK |
1035 | asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr) |
1036 | : "memory", "cc"); | |
1037 | } | |
1038 | ||
1039 | static void hardware_disable(void *garbage) | |
1040 | { | |
1041 | asm volatile (ASM_VMX_VMXOFF : : : "cc"); | |
e693d71b | 1042 | write_cr4(read_cr4() & ~X86_CR4_VMXE); |
6aa8b732 AK |
1043 | } |
1044 | ||
1c3d14fe | 1045 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 1046 | u32 msr, u32 *result) |
1c3d14fe YS |
1047 | { |
1048 | u32 vmx_msr_low, vmx_msr_high; | |
1049 | u32 ctl = ctl_min | ctl_opt; | |
1050 | ||
1051 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
1052 | ||
1053 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
1054 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
1055 | ||
1056 | /* Ensure minimum (required) set of control bits are supported. */ | |
1057 | if (ctl_min & ~ctl) | |
002c7f7c | 1058 | return -EIO; |
1c3d14fe YS |
1059 | |
1060 | *result = ctl; | |
1061 | return 0; | |
1062 | } | |
1063 | ||
002c7f7c | 1064 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
1065 | { |
1066 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 1067 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
1068 | u32 _pin_based_exec_control = 0; |
1069 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 1070 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
1071 | u32 _vmexit_control = 0; |
1072 | u32 _vmentry_control = 0; | |
1073 | ||
1074 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; | |
1075 | opt = 0; | |
1076 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, | |
1077 | &_pin_based_exec_control) < 0) | |
002c7f7c | 1078 | return -EIO; |
1c3d14fe YS |
1079 | |
1080 | min = CPU_BASED_HLT_EXITING | | |
1081 | #ifdef CONFIG_X86_64 | |
1082 | CPU_BASED_CR8_LOAD_EXITING | | |
1083 | CPU_BASED_CR8_STORE_EXITING | | |
1084 | #endif | |
d56f546d SY |
1085 | CPU_BASED_CR3_LOAD_EXITING | |
1086 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
1087 | CPU_BASED_USE_IO_BITMAPS | |
1088 | CPU_BASED_MOV_DR_EXITING | | |
1089 | CPU_BASED_USE_TSC_OFFSETING; | |
f78e0e2e | 1090 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 1091 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 1092 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
1093 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
1094 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 1095 | return -EIO; |
6e5d865c YS |
1096 | #ifdef CONFIG_X86_64 |
1097 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
1098 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
1099 | ~CPU_BASED_CR8_STORE_EXITING; | |
1100 | #endif | |
f78e0e2e | 1101 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
1102 | min2 = 0; |
1103 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
2384d2b3 | 1104 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d SY |
1105 | SECONDARY_EXEC_ENABLE_VPID | |
1106 | SECONDARY_EXEC_ENABLE_EPT; | |
1107 | if (adjust_vmx_controls(min2, opt2, | |
1108 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
1109 | &_cpu_based_2nd_exec_control) < 0) |
1110 | return -EIO; | |
1111 | } | |
1112 | #ifndef CONFIG_X86_64 | |
1113 | if (!(_cpu_based_2nd_exec_control & | |
1114 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
1115 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
1116 | #endif | |
d56f546d SY |
1117 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
1118 | /* CR3 accesses don't need to cause VM Exits when EPT enabled */ | |
1119 | min &= ~(CPU_BASED_CR3_LOAD_EXITING | | |
1120 | CPU_BASED_CR3_STORE_EXITING); | |
1121 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, | |
1122 | &_cpu_based_exec_control) < 0) | |
1123 | return -EIO; | |
1124 | rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, | |
1125 | vmx_capability.ept, vmx_capability.vpid); | |
1126 | } | |
1c3d14fe YS |
1127 | |
1128 | min = 0; | |
1129 | #ifdef CONFIG_X86_64 | |
1130 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
1131 | #endif | |
1132 | opt = 0; | |
1133 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, | |
1134 | &_vmexit_control) < 0) | |
002c7f7c | 1135 | return -EIO; |
1c3d14fe YS |
1136 | |
1137 | min = opt = 0; | |
1138 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, | |
1139 | &_vmentry_control) < 0) | |
002c7f7c | 1140 | return -EIO; |
6aa8b732 | 1141 | |
c68876fd | 1142 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
1143 | |
1144 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
1145 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 1146 | return -EIO; |
1c3d14fe YS |
1147 | |
1148 | #ifdef CONFIG_X86_64 | |
1149 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
1150 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 1151 | return -EIO; |
1c3d14fe YS |
1152 | #endif |
1153 | ||
1154 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
1155 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 1156 | return -EIO; |
1c3d14fe | 1157 | |
002c7f7c YS |
1158 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
1159 | vmcs_conf->order = get_order(vmcs_config.size); | |
1160 | vmcs_conf->revision_id = vmx_msr_low; | |
1c3d14fe | 1161 | |
002c7f7c YS |
1162 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
1163 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 1164 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
1165 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
1166 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe YS |
1167 | |
1168 | return 0; | |
c68876fd | 1169 | } |
6aa8b732 AK |
1170 | |
1171 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
1172 | { | |
1173 | int node = cpu_to_node(cpu); | |
1174 | struct page *pages; | |
1175 | struct vmcs *vmcs; | |
1176 | ||
1c3d14fe | 1177 | pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
1178 | if (!pages) |
1179 | return NULL; | |
1180 | vmcs = page_address(pages); | |
1c3d14fe YS |
1181 | memset(vmcs, 0, vmcs_config.size); |
1182 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
1183 | return vmcs; |
1184 | } | |
1185 | ||
1186 | static struct vmcs *alloc_vmcs(void) | |
1187 | { | |
d3b2c338 | 1188 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
1189 | } |
1190 | ||
1191 | static void free_vmcs(struct vmcs *vmcs) | |
1192 | { | |
1c3d14fe | 1193 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
1194 | } |
1195 | ||
39959588 | 1196 | static void free_kvm_area(void) |
6aa8b732 AK |
1197 | { |
1198 | int cpu; | |
1199 | ||
1200 | for_each_online_cpu(cpu) | |
1201 | free_vmcs(per_cpu(vmxarea, cpu)); | |
1202 | } | |
1203 | ||
6aa8b732 AK |
1204 | static __init int alloc_kvm_area(void) |
1205 | { | |
1206 | int cpu; | |
1207 | ||
1208 | for_each_online_cpu(cpu) { | |
1209 | struct vmcs *vmcs; | |
1210 | ||
1211 | vmcs = alloc_vmcs_cpu(cpu); | |
1212 | if (!vmcs) { | |
1213 | free_kvm_area(); | |
1214 | return -ENOMEM; | |
1215 | } | |
1216 | ||
1217 | per_cpu(vmxarea, cpu) = vmcs; | |
1218 | } | |
1219 | return 0; | |
1220 | } | |
1221 | ||
1222 | static __init int hardware_setup(void) | |
1223 | { | |
002c7f7c YS |
1224 | if (setup_vmcs_config(&vmcs_config) < 0) |
1225 | return -EIO; | |
50a37eb4 JR |
1226 | |
1227 | if (boot_cpu_has(X86_FEATURE_NX)) | |
1228 | kvm_enable_efer_bits(EFER_NX); | |
1229 | ||
6aa8b732 AK |
1230 | return alloc_kvm_area(); |
1231 | } | |
1232 | ||
1233 | static __exit void hardware_unsetup(void) | |
1234 | { | |
1235 | free_kvm_area(); | |
1236 | } | |
1237 | ||
6aa8b732 AK |
1238 | static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save) |
1239 | { | |
1240 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1241 | ||
6af11b9e | 1242 | if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) { |
6aa8b732 AK |
1243 | vmcs_write16(sf->selector, save->selector); |
1244 | vmcs_writel(sf->base, save->base); | |
1245 | vmcs_write32(sf->limit, save->limit); | |
1246 | vmcs_write32(sf->ar_bytes, save->ar); | |
1247 | } else { | |
1248 | u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK) | |
1249 | << AR_DPL_SHIFT; | |
1250 | vmcs_write32(sf->ar_bytes, 0x93 | dpl); | |
1251 | } | |
1252 | } | |
1253 | ||
1254 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
1255 | { | |
1256 | unsigned long flags; | |
1257 | ||
ad312c7c | 1258 | vcpu->arch.rmode.active = 0; |
6aa8b732 | 1259 | |
ad312c7c ZX |
1260 | vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base); |
1261 | vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit); | |
1262 | vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar); | |
6aa8b732 AK |
1263 | |
1264 | flags = vmcs_readl(GUEST_RFLAGS); | |
053de044 | 1265 | flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM); |
ad312c7c | 1266 | flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT); |
6aa8b732 AK |
1267 | vmcs_writel(GUEST_RFLAGS, flags); |
1268 | ||
66aee91a RR |
1269 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
1270 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
1271 | |
1272 | update_exception_bitmap(vcpu); | |
1273 | ||
ad312c7c ZX |
1274 | fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es); |
1275 | fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds); | |
1276 | fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs); | |
1277 | fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs); | |
6aa8b732 AK |
1278 | |
1279 | vmcs_write16(GUEST_SS_SELECTOR, 0); | |
1280 | vmcs_write32(GUEST_SS_AR_BYTES, 0x93); | |
1281 | ||
1282 | vmcs_write16(GUEST_CS_SELECTOR, | |
1283 | vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK); | |
1284 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
1285 | } | |
1286 | ||
d77c26fc | 1287 | static gva_t rmode_tss_base(struct kvm *kvm) |
6aa8b732 | 1288 | { |
bfc6d222 | 1289 | if (!kvm->arch.tss_addr) { |
cbc94022 IE |
1290 | gfn_t base_gfn = kvm->memslots[0].base_gfn + |
1291 | kvm->memslots[0].npages - 3; | |
1292 | return base_gfn << PAGE_SHIFT; | |
1293 | } | |
bfc6d222 | 1294 | return kvm->arch.tss_addr; |
6aa8b732 AK |
1295 | } |
1296 | ||
1297 | static void fix_rmode_seg(int seg, struct kvm_save_segment *save) | |
1298 | { | |
1299 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1300 | ||
1301 | save->selector = vmcs_read16(sf->selector); | |
1302 | save->base = vmcs_readl(sf->base); | |
1303 | save->limit = vmcs_read32(sf->limit); | |
1304 | save->ar = vmcs_read32(sf->ar_bytes); | |
15b00f32 JK |
1305 | vmcs_write16(sf->selector, save->base >> 4); |
1306 | vmcs_write32(sf->base, save->base & 0xfffff); | |
6aa8b732 AK |
1307 | vmcs_write32(sf->limit, 0xffff); |
1308 | vmcs_write32(sf->ar_bytes, 0xf3); | |
1309 | } | |
1310 | ||
1311 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
1312 | { | |
1313 | unsigned long flags; | |
1314 | ||
ad312c7c | 1315 | vcpu->arch.rmode.active = 1; |
6aa8b732 | 1316 | |
ad312c7c | 1317 | vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE); |
6aa8b732 AK |
1318 | vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm)); |
1319 | ||
ad312c7c | 1320 | vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT); |
6aa8b732 AK |
1321 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
1322 | ||
ad312c7c | 1323 | vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES); |
6aa8b732 AK |
1324 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
1325 | ||
1326 | flags = vmcs_readl(GUEST_RFLAGS); | |
ad312c7c ZX |
1327 | vcpu->arch.rmode.save_iopl |
1328 | = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
6aa8b732 | 1329 | |
053de044 | 1330 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
1331 | |
1332 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 1333 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
1334 | update_exception_bitmap(vcpu); |
1335 | ||
1336 | vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4); | |
1337 | vmcs_write32(GUEST_SS_LIMIT, 0xffff); | |
1338 | vmcs_write32(GUEST_SS_AR_BYTES, 0xf3); | |
1339 | ||
1340 | vmcs_write32(GUEST_CS_AR_BYTES, 0xf3); | |
abacf8df | 1341 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); |
8cb5b033 AK |
1342 | if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000) |
1343 | vmcs_writel(GUEST_CS_BASE, 0xf0000); | |
6aa8b732 AK |
1344 | vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4); |
1345 | ||
ad312c7c ZX |
1346 | fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es); |
1347 | fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds); | |
1348 | fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs); | |
1349 | fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs); | |
75880a01 | 1350 | |
8668a3c4 | 1351 | kvm_mmu_reset_context(vcpu); |
b7ebfb05 | 1352 | init_rmode(vcpu->kvm); |
6aa8b732 AK |
1353 | } |
1354 | ||
05b3e0c2 | 1355 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1356 | |
1357 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
1358 | { | |
1359 | u32 guest_tr_ar; | |
1360 | ||
1361 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); | |
1362 | if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { | |
1363 | printk(KERN_DEBUG "%s: tss fixup for long mode. \n", | |
b8688d51 | 1364 | __func__); |
6aa8b732 AK |
1365 | vmcs_write32(GUEST_TR_AR_BYTES, |
1366 | (guest_tr_ar & ~AR_TYPE_MASK) | |
1367 | | AR_TYPE_BUSY_64_TSS); | |
1368 | } | |
1369 | ||
ad312c7c | 1370 | vcpu->arch.shadow_efer |= EFER_LMA; |
6aa8b732 | 1371 | |
8b9cf98c | 1372 | find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1373 | vmcs_write32(VM_ENTRY_CONTROLS, |
1374 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 1375 | | VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1376 | } |
1377 | ||
1378 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
1379 | { | |
ad312c7c | 1380 | vcpu->arch.shadow_efer &= ~EFER_LMA; |
6aa8b732 AK |
1381 | |
1382 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1383 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 1384 | & ~VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1385 | } |
1386 | ||
1387 | #endif | |
1388 | ||
2384d2b3 SY |
1389 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
1390 | { | |
1391 | vpid_sync_vcpu_all(to_vmx(vcpu)); | |
1392 | } | |
1393 | ||
25c4c276 | 1394 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 1395 | { |
ad312c7c ZX |
1396 | vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK; |
1397 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK; | |
399badf3 AK |
1398 | } |
1399 | ||
1439442c SY |
1400 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
1401 | { | |
1402 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { | |
1403 | if (!load_pdptrs(vcpu, vcpu->arch.cr3)) { | |
1404 | printk(KERN_ERR "EPT: Fail to load pdptrs!\n"); | |
1405 | return; | |
1406 | } | |
1407 | vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]); | |
1408 | vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]); | |
1409 | vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]); | |
1410 | vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]); | |
1411 | } | |
1412 | } | |
1413 | ||
1414 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); | |
1415 | ||
1416 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
1417 | unsigned long cr0, | |
1418 | struct kvm_vcpu *vcpu) | |
1419 | { | |
1420 | if (!(cr0 & X86_CR0_PG)) { | |
1421 | /* From paging/starting to nonpaging */ | |
1422 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
1423 | vmcs_config.cpu_based_exec_ctrl | | |
1424 | (CPU_BASED_CR3_LOAD_EXITING | | |
1425 | CPU_BASED_CR3_STORE_EXITING)); | |
1426 | vcpu->arch.cr0 = cr0; | |
1427 | vmx_set_cr4(vcpu, vcpu->arch.cr4); | |
1428 | *hw_cr0 |= X86_CR0_PE | X86_CR0_PG; | |
1429 | *hw_cr0 &= ~X86_CR0_WP; | |
1430 | } else if (!is_paging(vcpu)) { | |
1431 | /* From nonpaging to paging */ | |
1432 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
1433 | vmcs_config.cpu_based_exec_ctrl & | |
1434 | ~(CPU_BASED_CR3_LOAD_EXITING | | |
1435 | CPU_BASED_CR3_STORE_EXITING)); | |
1436 | vcpu->arch.cr0 = cr0; | |
1437 | vmx_set_cr4(vcpu, vcpu->arch.cr4); | |
1438 | if (!(vcpu->arch.cr0 & X86_CR0_WP)) | |
1439 | *hw_cr0 &= ~X86_CR0_WP; | |
1440 | } | |
1441 | } | |
1442 | ||
1443 | static void ept_update_paging_mode_cr4(unsigned long *hw_cr4, | |
1444 | struct kvm_vcpu *vcpu) | |
1445 | { | |
1446 | if (!is_paging(vcpu)) { | |
1447 | *hw_cr4 &= ~X86_CR4_PAE; | |
1448 | *hw_cr4 |= X86_CR4_PSE; | |
1449 | } else if (!(vcpu->arch.cr4 & X86_CR4_PAE)) | |
1450 | *hw_cr4 &= ~X86_CR4_PAE; | |
1451 | } | |
1452 | ||
6aa8b732 AK |
1453 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1454 | { | |
1439442c SY |
1455 | unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | |
1456 | KVM_VM_CR0_ALWAYS_ON; | |
1457 | ||
5fd86fcf AK |
1458 | vmx_fpu_deactivate(vcpu); |
1459 | ||
ad312c7c | 1460 | if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1461 | enter_pmode(vcpu); |
1462 | ||
ad312c7c | 1463 | if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1464 | enter_rmode(vcpu); |
1465 | ||
05b3e0c2 | 1466 | #ifdef CONFIG_X86_64 |
ad312c7c | 1467 | if (vcpu->arch.shadow_efer & EFER_LME) { |
707d92fa | 1468 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 1469 | enter_lmode(vcpu); |
707d92fa | 1470 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
1471 | exit_lmode(vcpu); |
1472 | } | |
1473 | #endif | |
1474 | ||
1439442c SY |
1475 | if (vm_need_ept()) |
1476 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); | |
1477 | ||
6aa8b732 | 1478 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 1479 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 1480 | vcpu->arch.cr0 = cr0; |
5fd86fcf | 1481 | |
707d92fa | 1482 | if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE)) |
5fd86fcf | 1483 | vmx_fpu_activate(vcpu); |
6aa8b732 AK |
1484 | } |
1485 | ||
1439442c SY |
1486 | static u64 construct_eptp(unsigned long root_hpa) |
1487 | { | |
1488 | u64 eptp; | |
1489 | ||
1490 | /* TODO write the value reading from MSR */ | |
1491 | eptp = VMX_EPT_DEFAULT_MT | | |
1492 | VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT; | |
1493 | eptp |= (root_hpa & PAGE_MASK); | |
1494 | ||
1495 | return eptp; | |
1496 | } | |
1497 | ||
6aa8b732 AK |
1498 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
1499 | { | |
1439442c SY |
1500 | unsigned long guest_cr3; |
1501 | u64 eptp; | |
1502 | ||
1503 | guest_cr3 = cr3; | |
1504 | if (vm_need_ept()) { | |
1505 | eptp = construct_eptp(cr3); | |
1506 | vmcs_write64(EPT_POINTER, eptp); | |
1507 | ept_sync_context(eptp); | |
1508 | ept_load_pdptrs(vcpu); | |
1509 | guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 : | |
1510 | VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
1511 | } | |
1512 | ||
2384d2b3 | 1513 | vmx_flush_tlb(vcpu); |
1439442c | 1514 | vmcs_writel(GUEST_CR3, guest_cr3); |
ad312c7c | 1515 | if (vcpu->arch.cr0 & X86_CR0_PE) |
5fd86fcf | 1516 | vmx_fpu_deactivate(vcpu); |
6aa8b732 AK |
1517 | } |
1518 | ||
1519 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1520 | { | |
1439442c SY |
1521 | unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ? |
1522 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); | |
1523 | ||
ad312c7c | 1524 | vcpu->arch.cr4 = cr4; |
1439442c SY |
1525 | if (vm_need_ept()) |
1526 | ept_update_paging_mode_cr4(&hw_cr4, vcpu); | |
1527 | ||
1528 | vmcs_writel(CR4_READ_SHADOW, cr4); | |
1529 | vmcs_writel(GUEST_CR4, hw_cr4); | |
6aa8b732 AK |
1530 | } |
1531 | ||
6aa8b732 AK |
1532 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
1533 | { | |
8b9cf98c RR |
1534 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1535 | struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); | |
6aa8b732 | 1536 | |
ad312c7c | 1537 | vcpu->arch.shadow_efer = efer; |
9f62e19a JR |
1538 | if (!msr) |
1539 | return; | |
6aa8b732 AK |
1540 | if (efer & EFER_LMA) { |
1541 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1542 | vmcs_read32(VM_ENTRY_CONTROLS) | | |
1e4e6e00 | 1543 | VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1544 | msr->data = efer; |
1545 | ||
1546 | } else { | |
1547 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1548 | vmcs_read32(VM_ENTRY_CONTROLS) & | |
1e4e6e00 | 1549 | ~VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1550 | |
1551 | msr->data = efer & ~EFER_LME; | |
1552 | } | |
8b9cf98c | 1553 | setup_msrs(vmx); |
6aa8b732 AK |
1554 | } |
1555 | ||
6aa8b732 AK |
1556 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
1557 | { | |
1558 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1559 | ||
1560 | return vmcs_readl(sf->base); | |
1561 | } | |
1562 | ||
1563 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
1564 | struct kvm_segment *var, int seg) | |
1565 | { | |
1566 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1567 | u32 ar; | |
1568 | ||
1569 | var->base = vmcs_readl(sf->base); | |
1570 | var->limit = vmcs_read32(sf->limit); | |
1571 | var->selector = vmcs_read16(sf->selector); | |
1572 | ar = vmcs_read32(sf->ar_bytes); | |
1573 | if (ar & AR_UNUSABLE_MASK) | |
1574 | ar = 0; | |
1575 | var->type = ar & 15; | |
1576 | var->s = (ar >> 4) & 1; | |
1577 | var->dpl = (ar >> 5) & 3; | |
1578 | var->present = (ar >> 7) & 1; | |
1579 | var->avl = (ar >> 12) & 1; | |
1580 | var->l = (ar >> 13) & 1; | |
1581 | var->db = (ar >> 14) & 1; | |
1582 | var->g = (ar >> 15) & 1; | |
1583 | var->unusable = (ar >> 16) & 1; | |
1584 | } | |
1585 | ||
2e4d2653 IE |
1586 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
1587 | { | |
1588 | struct kvm_segment kvm_seg; | |
1589 | ||
1590 | if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */ | |
1591 | return 0; | |
1592 | ||
1593 | if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */ | |
1594 | return 3; | |
1595 | ||
1596 | vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS); | |
1597 | return kvm_seg.selector & 3; | |
1598 | } | |
1599 | ||
653e3108 | 1600 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 1601 | { |
6aa8b732 AK |
1602 | u32 ar; |
1603 | ||
653e3108 | 1604 | if (var->unusable) |
6aa8b732 AK |
1605 | ar = 1 << 16; |
1606 | else { | |
1607 | ar = var->type & 15; | |
1608 | ar |= (var->s & 1) << 4; | |
1609 | ar |= (var->dpl & 3) << 5; | |
1610 | ar |= (var->present & 1) << 7; | |
1611 | ar |= (var->avl & 1) << 12; | |
1612 | ar |= (var->l & 1) << 13; | |
1613 | ar |= (var->db & 1) << 14; | |
1614 | ar |= (var->g & 1) << 15; | |
1615 | } | |
f7fbf1fd UL |
1616 | if (ar == 0) /* a 0 value means unusable */ |
1617 | ar = AR_UNUSABLE_MASK; | |
653e3108 AK |
1618 | |
1619 | return ar; | |
1620 | } | |
1621 | ||
1622 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
1623 | struct kvm_segment *var, int seg) | |
1624 | { | |
1625 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1626 | u32 ar; | |
1627 | ||
ad312c7c ZX |
1628 | if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) { |
1629 | vcpu->arch.rmode.tr.selector = var->selector; | |
1630 | vcpu->arch.rmode.tr.base = var->base; | |
1631 | vcpu->arch.rmode.tr.limit = var->limit; | |
1632 | vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var); | |
653e3108 AK |
1633 | return; |
1634 | } | |
1635 | vmcs_writel(sf->base, var->base); | |
1636 | vmcs_write32(sf->limit, var->limit); | |
1637 | vmcs_write16(sf->selector, var->selector); | |
ad312c7c | 1638 | if (vcpu->arch.rmode.active && var->s) { |
653e3108 AK |
1639 | /* |
1640 | * Hack real-mode segments into vm86 compatibility. | |
1641 | */ | |
1642 | if (var->base == 0xffff0000 && var->selector == 0xf000) | |
1643 | vmcs_writel(sf->base, 0xf0000); | |
1644 | ar = 0xf3; | |
1645 | } else | |
1646 | ar = vmx_segment_access_rights(var); | |
6aa8b732 AK |
1647 | vmcs_write32(sf->ar_bytes, ar); |
1648 | } | |
1649 | ||
6aa8b732 AK |
1650 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
1651 | { | |
1652 | u32 ar = vmcs_read32(GUEST_CS_AR_BYTES); | |
1653 | ||
1654 | *db = (ar >> 14) & 1; | |
1655 | *l = (ar >> 13) & 1; | |
1656 | } | |
1657 | ||
1658 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1659 | { | |
1660 | dt->limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
1661 | dt->base = vmcs_readl(GUEST_IDTR_BASE); | |
1662 | } | |
1663 | ||
1664 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1665 | { | |
1666 | vmcs_write32(GUEST_IDTR_LIMIT, dt->limit); | |
1667 | vmcs_writel(GUEST_IDTR_BASE, dt->base); | |
1668 | } | |
1669 | ||
1670 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1671 | { | |
1672 | dt->limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
1673 | dt->base = vmcs_readl(GUEST_GDTR_BASE); | |
1674 | } | |
1675 | ||
1676 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1677 | { | |
1678 | vmcs_write32(GUEST_GDTR_LIMIT, dt->limit); | |
1679 | vmcs_writel(GUEST_GDTR_BASE, dt->base); | |
1680 | } | |
1681 | ||
d77c26fc | 1682 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 1683 | { |
6aa8b732 | 1684 | gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT; |
195aefde | 1685 | u16 data = 0; |
10589a46 | 1686 | int ret = 0; |
195aefde | 1687 | int r; |
6aa8b732 | 1688 | |
195aefde IE |
1689 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
1690 | if (r < 0) | |
10589a46 | 1691 | goto out; |
195aefde IE |
1692 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
1693 | r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16)); | |
1694 | if (r < 0) | |
10589a46 | 1695 | goto out; |
195aefde IE |
1696 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
1697 | if (r < 0) | |
10589a46 | 1698 | goto out; |
195aefde IE |
1699 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
1700 | if (r < 0) | |
10589a46 | 1701 | goto out; |
195aefde | 1702 | data = ~0; |
10589a46 MT |
1703 | r = kvm_write_guest_page(kvm, fn, &data, |
1704 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
1705 | sizeof(u8)); | |
195aefde | 1706 | if (r < 0) |
10589a46 MT |
1707 | goto out; |
1708 | ||
1709 | ret = 1; | |
1710 | out: | |
10589a46 | 1711 | return ret; |
6aa8b732 AK |
1712 | } |
1713 | ||
b7ebfb05 SY |
1714 | static int init_rmode_identity_map(struct kvm *kvm) |
1715 | { | |
1716 | int i, r, ret; | |
1717 | pfn_t identity_map_pfn; | |
1718 | u32 tmp; | |
1719 | ||
1720 | if (!vm_need_ept()) | |
1721 | return 1; | |
1722 | if (unlikely(!kvm->arch.ept_identity_pagetable)) { | |
1723 | printk(KERN_ERR "EPT: identity-mapping pagetable " | |
1724 | "haven't been allocated!\n"); | |
1725 | return 0; | |
1726 | } | |
1727 | if (likely(kvm->arch.ept_identity_pagetable_done)) | |
1728 | return 1; | |
1729 | ret = 0; | |
1730 | identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT; | |
1731 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); | |
1732 | if (r < 0) | |
1733 | goto out; | |
1734 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
1735 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
1736 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
1737 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
1738 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
1739 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
1740 | if (r < 0) | |
1741 | goto out; | |
1742 | } | |
1743 | kvm->arch.ept_identity_pagetable_done = true; | |
1744 | ret = 1; | |
1745 | out: | |
1746 | return ret; | |
1747 | } | |
1748 | ||
6aa8b732 AK |
1749 | static void seg_setup(int seg) |
1750 | { | |
1751 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1752 | ||
1753 | vmcs_write16(sf->selector, 0); | |
1754 | vmcs_writel(sf->base, 0); | |
1755 | vmcs_write32(sf->limit, 0xffff); | |
1756 | vmcs_write32(sf->ar_bytes, 0x93); | |
1757 | } | |
1758 | ||
f78e0e2e SY |
1759 | static int alloc_apic_access_page(struct kvm *kvm) |
1760 | { | |
1761 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
1762 | int r = 0; | |
1763 | ||
72dc67a6 | 1764 | down_write(&kvm->slots_lock); |
bfc6d222 | 1765 | if (kvm->arch.apic_access_page) |
f78e0e2e SY |
1766 | goto out; |
1767 | kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; | |
1768 | kvm_userspace_mem.flags = 0; | |
1769 | kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL; | |
1770 | kvm_userspace_mem.memory_size = PAGE_SIZE; | |
1771 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
1772 | if (r) | |
1773 | goto out; | |
72dc67a6 IE |
1774 | |
1775 | down_read(¤t->mm->mmap_sem); | |
bfc6d222 | 1776 | kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00); |
72dc67a6 | 1777 | up_read(¤t->mm->mmap_sem); |
f78e0e2e | 1778 | out: |
72dc67a6 | 1779 | up_write(&kvm->slots_lock); |
f78e0e2e SY |
1780 | return r; |
1781 | } | |
1782 | ||
b7ebfb05 SY |
1783 | static int alloc_identity_pagetable(struct kvm *kvm) |
1784 | { | |
1785 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
1786 | int r = 0; | |
1787 | ||
1788 | down_write(&kvm->slots_lock); | |
1789 | if (kvm->arch.ept_identity_pagetable) | |
1790 | goto out; | |
1791 | kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; | |
1792 | kvm_userspace_mem.flags = 0; | |
1793 | kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
1794 | kvm_userspace_mem.memory_size = PAGE_SIZE; | |
1795 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
1796 | if (r) | |
1797 | goto out; | |
1798 | ||
1799 | down_read(¤t->mm->mmap_sem); | |
1800 | kvm->arch.ept_identity_pagetable = gfn_to_page(kvm, | |
1801 | VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT); | |
1802 | up_read(¤t->mm->mmap_sem); | |
1803 | out: | |
1804 | up_write(&kvm->slots_lock); | |
1805 | return r; | |
1806 | } | |
1807 | ||
2384d2b3 SY |
1808 | static void allocate_vpid(struct vcpu_vmx *vmx) |
1809 | { | |
1810 | int vpid; | |
1811 | ||
1812 | vmx->vpid = 0; | |
1813 | if (!enable_vpid || !cpu_has_vmx_vpid()) | |
1814 | return; | |
1815 | spin_lock(&vmx_vpid_lock); | |
1816 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
1817 | if (vpid < VMX_NR_VPIDS) { | |
1818 | vmx->vpid = vpid; | |
1819 | __set_bit(vpid, vmx_vpid_bitmap); | |
1820 | } | |
1821 | spin_unlock(&vmx_vpid_lock); | |
1822 | } | |
1823 | ||
8b2cf73c | 1824 | static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr) |
25c5f225 SY |
1825 | { |
1826 | void *va; | |
1827 | ||
1828 | if (!cpu_has_vmx_msr_bitmap()) | |
1829 | return; | |
1830 | ||
1831 | /* | |
1832 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
1833 | * have the write-low and read-high bitmap offsets the wrong way round. | |
1834 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
1835 | */ | |
1836 | va = kmap(msr_bitmap); | |
1837 | if (msr <= 0x1fff) { | |
1838 | __clear_bit(msr, va + 0x000); /* read-low */ | |
1839 | __clear_bit(msr, va + 0x800); /* write-low */ | |
1840 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
1841 | msr &= 0x1fff; | |
1842 | __clear_bit(msr, va + 0x400); /* read-high */ | |
1843 | __clear_bit(msr, va + 0xc00); /* write-high */ | |
1844 | } | |
1845 | kunmap(msr_bitmap); | |
1846 | } | |
1847 | ||
6aa8b732 AK |
1848 | /* |
1849 | * Sets up the vmcs for emulated real mode. | |
1850 | */ | |
8b9cf98c | 1851 | static int vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 AK |
1852 | { |
1853 | u32 host_sysenter_cs; | |
1854 | u32 junk; | |
1855 | unsigned long a; | |
1856 | struct descriptor_table dt; | |
1857 | int i; | |
cd2276a7 | 1858 | unsigned long kvm_vmx_return; |
6e5d865c | 1859 | u32 exec_control; |
6aa8b732 | 1860 | |
6aa8b732 | 1861 | /* I/O */ |
fdef3ad1 HQ |
1862 | vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a)); |
1863 | vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b)); | |
6aa8b732 | 1864 | |
25c5f225 SY |
1865 | if (cpu_has_vmx_msr_bitmap()) |
1866 | vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap)); | |
1867 | ||
6aa8b732 AK |
1868 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
1869 | ||
6aa8b732 | 1870 | /* Control */ |
1c3d14fe YS |
1871 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, |
1872 | vmcs_config.pin_based_exec_ctrl); | |
6e5d865c YS |
1873 | |
1874 | exec_control = vmcs_config.cpu_based_exec_ctrl; | |
1875 | if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) { | |
1876 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
1877 | #ifdef CONFIG_X86_64 | |
1878 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
1879 | CPU_BASED_CR8_LOAD_EXITING; | |
1880 | #endif | |
1881 | } | |
d56f546d SY |
1882 | if (!vm_need_ept()) |
1883 | exec_control |= CPU_BASED_CR3_STORE_EXITING | | |
1884 | CPU_BASED_CR3_LOAD_EXITING; | |
6e5d865c | 1885 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); |
6aa8b732 | 1886 | |
83ff3b9d SY |
1887 | if (cpu_has_secondary_exec_ctrls()) { |
1888 | exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; | |
1889 | if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
1890 | exec_control &= | |
1891 | ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
2384d2b3 SY |
1892 | if (vmx->vpid == 0) |
1893 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
d56f546d SY |
1894 | if (!vm_need_ept()) |
1895 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; | |
83ff3b9d SY |
1896 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
1897 | } | |
f78e0e2e | 1898 | |
c7addb90 AK |
1899 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf); |
1900 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf); | |
6aa8b732 AK |
1901 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
1902 | ||
1903 | vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */ | |
1904 | vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */ | |
1905 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ | |
1906 | ||
1907 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ | |
1908 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
1909 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
1910 | vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */ | |
1911 | vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */ | |
1912 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
05b3e0c2 | 1913 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1914 | rdmsrl(MSR_FS_BASE, a); |
1915 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
1916 | rdmsrl(MSR_GS_BASE, a); | |
1917 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
1918 | #else | |
1919 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
1920 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
1921 | #endif | |
1922 | ||
1923 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
1924 | ||
1925 | get_idt(&dt); | |
1926 | vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */ | |
1927 | ||
d77c26fc | 1928 | asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return)); |
cd2276a7 | 1929 | vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */ |
2cc51560 ED |
1930 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
1931 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
1932 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); | |
6aa8b732 AK |
1933 | |
1934 | rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk); | |
1935 | vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs); | |
1936 | rdmsrl(MSR_IA32_SYSENTER_ESP, a); | |
1937 | vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */ | |
1938 | rdmsrl(MSR_IA32_SYSENTER_EIP, a); | |
1939 | vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */ | |
1940 | ||
6aa8b732 AK |
1941 | for (i = 0; i < NR_VMX_MSR; ++i) { |
1942 | u32 index = vmx_msr_index[i]; | |
1943 | u32 data_low, data_high; | |
1944 | u64 data; | |
a2fa3e9f | 1945 | int j = vmx->nmsrs; |
6aa8b732 AK |
1946 | |
1947 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
1948 | continue; | |
432bd6cb AK |
1949 | if (wrmsr_safe(index, data_low, data_high) < 0) |
1950 | continue; | |
6aa8b732 | 1951 | data = data_low | ((u64)data_high << 32); |
a2fa3e9f GH |
1952 | vmx->host_msrs[j].index = index; |
1953 | vmx->host_msrs[j].reserved = 0; | |
1954 | vmx->host_msrs[j].data = data; | |
1955 | vmx->guest_msrs[j] = vmx->host_msrs[j]; | |
1956 | ++vmx->nmsrs; | |
6aa8b732 | 1957 | } |
6aa8b732 | 1958 | |
1c3d14fe | 1959 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
6aa8b732 AK |
1960 | |
1961 | /* 22.2.1, 20.8.1 */ | |
1c3d14fe YS |
1962 | vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl); |
1963 | ||
e00c8cf2 AK |
1964 | vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL); |
1965 | vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK); | |
1966 | ||
f78e0e2e | 1967 | |
e00c8cf2 AK |
1968 | return 0; |
1969 | } | |
1970 | ||
b7ebfb05 SY |
1971 | static int init_rmode(struct kvm *kvm) |
1972 | { | |
1973 | if (!init_rmode_tss(kvm)) | |
1974 | return 0; | |
1975 | if (!init_rmode_identity_map(kvm)) | |
1976 | return 0; | |
1977 | return 1; | |
1978 | } | |
1979 | ||
e00c8cf2 AK |
1980 | static int vmx_vcpu_reset(struct kvm_vcpu *vcpu) |
1981 | { | |
1982 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
1983 | u64 msr; | |
1984 | int ret; | |
1985 | ||
3200f405 | 1986 | down_read(&vcpu->kvm->slots_lock); |
b7ebfb05 | 1987 | if (!init_rmode(vmx->vcpu.kvm)) { |
e00c8cf2 AK |
1988 | ret = -ENOMEM; |
1989 | goto out; | |
1990 | } | |
1991 | ||
ad312c7c | 1992 | vmx->vcpu.arch.rmode.active = 0; |
e00c8cf2 | 1993 | |
ad312c7c | 1994 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
2d3ad1f4 | 1995 | kvm_set_cr8(&vmx->vcpu, 0); |
e00c8cf2 AK |
1996 | msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
1997 | if (vmx->vcpu.vcpu_id == 0) | |
1998 | msr |= MSR_IA32_APICBASE_BSP; | |
1999 | kvm_set_apic_base(&vmx->vcpu, msr); | |
2000 | ||
2001 | fx_init(&vmx->vcpu); | |
2002 | ||
2003 | /* | |
2004 | * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode | |
2005 | * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh. | |
2006 | */ | |
2007 | if (vmx->vcpu.vcpu_id == 0) { | |
2008 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); | |
2009 | vmcs_writel(GUEST_CS_BASE, 0x000f0000); | |
2010 | } else { | |
ad312c7c ZX |
2011 | vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8); |
2012 | vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12); | |
e00c8cf2 AK |
2013 | } |
2014 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); | |
2015 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
2016 | ||
2017 | seg_setup(VCPU_SREG_DS); | |
2018 | seg_setup(VCPU_SREG_ES); | |
2019 | seg_setup(VCPU_SREG_FS); | |
2020 | seg_setup(VCPU_SREG_GS); | |
2021 | seg_setup(VCPU_SREG_SS); | |
2022 | ||
2023 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
2024 | vmcs_writel(GUEST_TR_BASE, 0); | |
2025 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
2026 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
2027 | ||
2028 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
2029 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
2030 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
2031 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
2032 | ||
2033 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
2034 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
2035 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
2036 | ||
2037 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
2038 | if (vmx->vcpu.vcpu_id == 0) | |
2039 | vmcs_writel(GUEST_RIP, 0xfff0); | |
2040 | else | |
2041 | vmcs_writel(GUEST_RIP, 0); | |
2042 | vmcs_writel(GUEST_RSP, 0); | |
2043 | ||
2044 | /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */ | |
2045 | vmcs_writel(GUEST_DR7, 0x400); | |
2046 | ||
2047 | vmcs_writel(GUEST_GDTR_BASE, 0); | |
2048 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
2049 | ||
2050 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
2051 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
2052 | ||
2053 | vmcs_write32(GUEST_ACTIVITY_STATE, 0); | |
2054 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); | |
2055 | vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0); | |
2056 | ||
2057 | guest_write_tsc(0); | |
2058 | ||
2059 | /* Special registers */ | |
2060 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
2061 | ||
2062 | setup_msrs(vmx); | |
2063 | ||
6aa8b732 AK |
2064 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
2065 | ||
f78e0e2e SY |
2066 | if (cpu_has_vmx_tpr_shadow()) { |
2067 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); | |
2068 | if (vm_need_tpr_shadow(vmx->vcpu.kvm)) | |
2069 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, | |
ad312c7c | 2070 | page_to_phys(vmx->vcpu.arch.apic->regs_page)); |
f78e0e2e SY |
2071 | vmcs_write32(TPR_THRESHOLD, 0); |
2072 | } | |
2073 | ||
2074 | if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
2075 | vmcs_write64(APIC_ACCESS_ADDR, | |
bfc6d222 | 2076 | page_to_phys(vmx->vcpu.kvm->arch.apic_access_page)); |
6aa8b732 | 2077 | |
2384d2b3 SY |
2078 | if (vmx->vpid != 0) |
2079 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
2080 | ||
ad312c7c ZX |
2081 | vmx->vcpu.arch.cr0 = 0x60000010; |
2082 | vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */ | |
8b9cf98c | 2083 | vmx_set_cr4(&vmx->vcpu, 0); |
8b9cf98c | 2084 | vmx_set_efer(&vmx->vcpu, 0); |
8b9cf98c RR |
2085 | vmx_fpu_activate(&vmx->vcpu); |
2086 | update_exception_bitmap(&vmx->vcpu); | |
6aa8b732 | 2087 | |
2384d2b3 SY |
2088 | vpid_sync_vcpu_all(vmx); |
2089 | ||
3200f405 | 2090 | ret = 0; |
6aa8b732 | 2091 | |
6aa8b732 | 2092 | out: |
3200f405 | 2093 | up_read(&vcpu->kvm->slots_lock); |
6aa8b732 AK |
2094 | return ret; |
2095 | } | |
2096 | ||
85f455f7 ED |
2097 | static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq) |
2098 | { | |
9c8cba37 AK |
2099 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2100 | ||
2714d1d3 FEL |
2101 | KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler); |
2102 | ||
ad312c7c | 2103 | if (vcpu->arch.rmode.active) { |
9c8cba37 AK |
2104 | vmx->rmode.irq.pending = true; |
2105 | vmx->rmode.irq.vector = irq; | |
2106 | vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP); | |
9c5623e3 AK |
2107 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
2108 | irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK); | |
2109 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1); | |
9c8cba37 | 2110 | vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1); |
85f455f7 ED |
2111 | return; |
2112 | } | |
2113 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
2114 | irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
2115 | } | |
2116 | ||
6aa8b732 AK |
2117 | static void kvm_do_inject_irq(struct kvm_vcpu *vcpu) |
2118 | { | |
ad312c7c ZX |
2119 | int word_index = __ffs(vcpu->arch.irq_summary); |
2120 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
6aa8b732 AK |
2121 | int irq = word_index * BITS_PER_LONG + bit_index; |
2122 | ||
ad312c7c ZX |
2123 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
2124 | if (!vcpu->arch.irq_pending[word_index]) | |
2125 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
85f455f7 | 2126 | vmx_inject_irq(vcpu, irq); |
6aa8b732 AK |
2127 | } |
2128 | ||
c1150d8c DL |
2129 | |
2130 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, | |
2131 | struct kvm_run *kvm_run) | |
6aa8b732 | 2132 | { |
c1150d8c DL |
2133 | u32 cpu_based_vm_exec_control; |
2134 | ||
ad312c7c | 2135 | vcpu->arch.interrupt_window_open = |
c1150d8c DL |
2136 | ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && |
2137 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0); | |
2138 | ||
ad312c7c ZX |
2139 | if (vcpu->arch.interrupt_window_open && |
2140 | vcpu->arch.irq_summary && | |
c1150d8c | 2141 | !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK)) |
6aa8b732 | 2142 | /* |
c1150d8c | 2143 | * If interrupts enabled, and not blocked by sti or mov ss. Good. |
6aa8b732 AK |
2144 | */ |
2145 | kvm_do_inject_irq(vcpu); | |
c1150d8c DL |
2146 | |
2147 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
ad312c7c ZX |
2148 | if (!vcpu->arch.interrupt_window_open && |
2149 | (vcpu->arch.irq_summary || kvm_run->request_interrupt_window)) | |
6aa8b732 AK |
2150 | /* |
2151 | * Interrupts blocked. Wait for unblock. | |
2152 | */ | |
c1150d8c DL |
2153 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; |
2154 | else | |
2155 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
2156 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
6aa8b732 AK |
2157 | } |
2158 | ||
cbc94022 IE |
2159 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
2160 | { | |
2161 | int ret; | |
2162 | struct kvm_userspace_memory_region tss_mem = { | |
2163 | .slot = 8, | |
2164 | .guest_phys_addr = addr, | |
2165 | .memory_size = PAGE_SIZE * 3, | |
2166 | .flags = 0, | |
2167 | }; | |
2168 | ||
2169 | ret = kvm_set_memory_region(kvm, &tss_mem, 0); | |
2170 | if (ret) | |
2171 | return ret; | |
bfc6d222 | 2172 | kvm->arch.tss_addr = addr; |
cbc94022 IE |
2173 | return 0; |
2174 | } | |
2175 | ||
6aa8b732 AK |
2176 | static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu) |
2177 | { | |
2178 | struct kvm_guest_debug *dbg = &vcpu->guest_debug; | |
2179 | ||
2180 | set_debugreg(dbg->bp[0], 0); | |
2181 | set_debugreg(dbg->bp[1], 1); | |
2182 | set_debugreg(dbg->bp[2], 2); | |
2183 | set_debugreg(dbg->bp[3], 3); | |
2184 | ||
2185 | if (dbg->singlestep) { | |
2186 | unsigned long flags; | |
2187 | ||
2188 | flags = vmcs_readl(GUEST_RFLAGS); | |
2189 | flags |= X86_EFLAGS_TF | X86_EFLAGS_RF; | |
2190 | vmcs_writel(GUEST_RFLAGS, flags); | |
2191 | } | |
2192 | } | |
2193 | ||
2194 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
2195 | int vec, u32 err_code) | |
2196 | { | |
ad312c7c | 2197 | if (!vcpu->arch.rmode.active) |
6aa8b732 AK |
2198 | return 0; |
2199 | ||
b3f37707 NK |
2200 | /* |
2201 | * Instruction with address size override prefix opcode 0x67 | |
2202 | * Cause the #SS fault with 0 error code in VM86 mode. | |
2203 | */ | |
2204 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) | |
3427318f | 2205 | if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE) |
6aa8b732 AK |
2206 | return 1; |
2207 | return 0; | |
2208 | } | |
2209 | ||
2210 | static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2211 | { | |
1155f76a | 2212 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 AK |
2213 | u32 intr_info, error_code; |
2214 | unsigned long cr2, rip; | |
2215 | u32 vect_info; | |
2216 | enum emulation_result er; | |
2217 | ||
1155f76a | 2218 | vect_info = vmx->idt_vectoring_info; |
6aa8b732 AK |
2219 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
2220 | ||
2221 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
d77c26fc | 2222 | !is_page_fault(intr_info)) |
6aa8b732 | 2223 | printk(KERN_ERR "%s: unexpected, vectoring info 0x%x " |
b8688d51 | 2224 | "intr info 0x%x\n", __func__, vect_info, intr_info); |
6aa8b732 | 2225 | |
85f455f7 | 2226 | if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) { |
6aa8b732 | 2227 | int irq = vect_info & VECTORING_INFO_VECTOR_MASK; |
ad312c7c ZX |
2228 | set_bit(irq, vcpu->arch.irq_pending); |
2229 | set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
2230 | } |
2231 | ||
1b6269db AK |
2232 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */ |
2233 | return 1; /* already handled by vmx_vcpu_run() */ | |
2ab455cc AL |
2234 | |
2235 | if (is_no_device(intr_info)) { | |
5fd86fcf | 2236 | vmx_fpu_activate(vcpu); |
2ab455cc AL |
2237 | return 1; |
2238 | } | |
2239 | ||
7aa81cc0 | 2240 | if (is_invalid_opcode(intr_info)) { |
571008da | 2241 | er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 2242 | if (er != EMULATE_DONE) |
7ee5d940 | 2243 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
2244 | return 1; |
2245 | } | |
2246 | ||
6aa8b732 AK |
2247 | error_code = 0; |
2248 | rip = vmcs_readl(GUEST_RIP); | |
2e11384c | 2249 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 AK |
2250 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
2251 | if (is_page_fault(intr_info)) { | |
1439442c SY |
2252 | /* EPT won't cause page fault directly */ |
2253 | if (vm_need_ept()) | |
2254 | BUG(); | |
6aa8b732 | 2255 | cr2 = vmcs_readl(EXIT_QUALIFICATION); |
2714d1d3 FEL |
2256 | KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2, |
2257 | (u32)((u64)cr2 >> 32), handler); | |
3067714c | 2258 | return kvm_mmu_page_fault(vcpu, cr2, error_code); |
6aa8b732 AK |
2259 | } |
2260 | ||
ad312c7c | 2261 | if (vcpu->arch.rmode.active && |
6aa8b732 | 2262 | handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK, |
72d6e5a0 | 2263 | error_code)) { |
ad312c7c ZX |
2264 | if (vcpu->arch.halt_request) { |
2265 | vcpu->arch.halt_request = 0; | |
72d6e5a0 AK |
2266 | return kvm_emulate_halt(vcpu); |
2267 | } | |
6aa8b732 | 2268 | return 1; |
72d6e5a0 | 2269 | } |
6aa8b732 | 2270 | |
d77c26fc MD |
2271 | if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == |
2272 | (INTR_TYPE_EXCEPTION | 1)) { | |
6aa8b732 AK |
2273 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
2274 | return 0; | |
2275 | } | |
2276 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; | |
2277 | kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK; | |
2278 | kvm_run->ex.error_code = error_code; | |
2279 | return 0; | |
2280 | } | |
2281 | ||
2282 | static int handle_external_interrupt(struct kvm_vcpu *vcpu, | |
2283 | struct kvm_run *kvm_run) | |
2284 | { | |
1165f5fe | 2285 | ++vcpu->stat.irq_exits; |
2714d1d3 | 2286 | KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler); |
6aa8b732 AK |
2287 | return 1; |
2288 | } | |
2289 | ||
988ad74f AK |
2290 | static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2291 | { | |
2292 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
2293 | return 0; | |
2294 | } | |
6aa8b732 | 2295 | |
6aa8b732 AK |
2296 | static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2297 | { | |
bfdaab09 | 2298 | unsigned long exit_qualification; |
039576c0 AK |
2299 | int size, down, in, string, rep; |
2300 | unsigned port; | |
6aa8b732 | 2301 | |
1165f5fe | 2302 | ++vcpu->stat.io_exits; |
bfdaab09 | 2303 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 2304 | string = (exit_qualification & 16) != 0; |
e70669ab LV |
2305 | |
2306 | if (string) { | |
3427318f LV |
2307 | if (emulate_instruction(vcpu, |
2308 | kvm_run, 0, 0, 0) == EMULATE_DO_MMIO) | |
e70669ab LV |
2309 | return 0; |
2310 | return 1; | |
2311 | } | |
2312 | ||
2313 | size = (exit_qualification & 7) + 1; | |
2314 | in = (exit_qualification & 8) != 0; | |
039576c0 | 2315 | down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0; |
039576c0 AK |
2316 | rep = (exit_qualification & 32) != 0; |
2317 | port = exit_qualification >> 16; | |
e70669ab | 2318 | |
3090dd73 | 2319 | return kvm_emulate_pio(vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
2320 | } |
2321 | ||
102d8325 IM |
2322 | static void |
2323 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
2324 | { | |
2325 | /* | |
2326 | * Patch in the VMCALL instruction: | |
2327 | */ | |
2328 | hypercall[0] = 0x0f; | |
2329 | hypercall[1] = 0x01; | |
2330 | hypercall[2] = 0xc1; | |
102d8325 IM |
2331 | } |
2332 | ||
6aa8b732 AK |
2333 | static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2334 | { | |
bfdaab09 | 2335 | unsigned long exit_qualification; |
6aa8b732 AK |
2336 | int cr; |
2337 | int reg; | |
2338 | ||
bfdaab09 | 2339 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
2340 | cr = exit_qualification & 15; |
2341 | reg = (exit_qualification >> 8) & 15; | |
2342 | switch ((exit_qualification >> 4) & 3) { | |
2343 | case 0: /* mov to cr */ | |
2714d1d3 FEL |
2344 | KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)vcpu->arch.regs[reg], |
2345 | (u32)((u64)vcpu->arch.regs[reg] >> 32), handler); | |
6aa8b732 AK |
2346 | switch (cr) { |
2347 | case 0: | |
2348 | vcpu_load_rsp_rip(vcpu); | |
2d3ad1f4 | 2349 | kvm_set_cr0(vcpu, vcpu->arch.regs[reg]); |
6aa8b732 AK |
2350 | skip_emulated_instruction(vcpu); |
2351 | return 1; | |
2352 | case 3: | |
2353 | vcpu_load_rsp_rip(vcpu); | |
2d3ad1f4 | 2354 | kvm_set_cr3(vcpu, vcpu->arch.regs[reg]); |
6aa8b732 AK |
2355 | skip_emulated_instruction(vcpu); |
2356 | return 1; | |
2357 | case 4: | |
2358 | vcpu_load_rsp_rip(vcpu); | |
2d3ad1f4 | 2359 | kvm_set_cr4(vcpu, vcpu->arch.regs[reg]); |
6aa8b732 AK |
2360 | skip_emulated_instruction(vcpu); |
2361 | return 1; | |
2362 | case 8: | |
2363 | vcpu_load_rsp_rip(vcpu); | |
2d3ad1f4 | 2364 | kvm_set_cr8(vcpu, vcpu->arch.regs[reg]); |
6aa8b732 | 2365 | skip_emulated_instruction(vcpu); |
e5314067 AK |
2366 | if (irqchip_in_kernel(vcpu->kvm)) |
2367 | return 1; | |
253abdee YS |
2368 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2369 | return 0; | |
6aa8b732 AK |
2370 | }; |
2371 | break; | |
25c4c276 AL |
2372 | case 2: /* clts */ |
2373 | vcpu_load_rsp_rip(vcpu); | |
5fd86fcf | 2374 | vmx_fpu_deactivate(vcpu); |
ad312c7c ZX |
2375 | vcpu->arch.cr0 &= ~X86_CR0_TS; |
2376 | vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0); | |
5fd86fcf | 2377 | vmx_fpu_activate(vcpu); |
2714d1d3 | 2378 | KVMTRACE_0D(CLTS, vcpu, handler); |
25c4c276 AL |
2379 | skip_emulated_instruction(vcpu); |
2380 | return 1; | |
6aa8b732 AK |
2381 | case 1: /*mov from cr*/ |
2382 | switch (cr) { | |
2383 | case 3: | |
2384 | vcpu_load_rsp_rip(vcpu); | |
ad312c7c | 2385 | vcpu->arch.regs[reg] = vcpu->arch.cr3; |
6aa8b732 | 2386 | vcpu_put_rsp_rip(vcpu); |
2714d1d3 FEL |
2387 | KVMTRACE_3D(CR_READ, vcpu, (u32)cr, |
2388 | (u32)vcpu->arch.regs[reg], | |
2389 | (u32)((u64)vcpu->arch.regs[reg] >> 32), | |
2390 | handler); | |
6aa8b732 AK |
2391 | skip_emulated_instruction(vcpu); |
2392 | return 1; | |
2393 | case 8: | |
6aa8b732 | 2394 | vcpu_load_rsp_rip(vcpu); |
2d3ad1f4 | 2395 | vcpu->arch.regs[reg] = kvm_get_cr8(vcpu); |
6aa8b732 | 2396 | vcpu_put_rsp_rip(vcpu); |
2714d1d3 FEL |
2397 | KVMTRACE_2D(CR_READ, vcpu, (u32)cr, |
2398 | (u32)vcpu->arch.regs[reg], handler); | |
6aa8b732 AK |
2399 | skip_emulated_instruction(vcpu); |
2400 | return 1; | |
2401 | } | |
2402 | break; | |
2403 | case 3: /* lmsw */ | |
2d3ad1f4 | 2404 | kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f); |
6aa8b732 AK |
2405 | |
2406 | skip_emulated_instruction(vcpu); | |
2407 | return 1; | |
2408 | default: | |
2409 | break; | |
2410 | } | |
2411 | kvm_run->exit_reason = 0; | |
f0242478 | 2412 | pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
2413 | (int)(exit_qualification >> 4) & 3, cr); |
2414 | return 0; | |
2415 | } | |
2416 | ||
2417 | static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2418 | { | |
bfdaab09 | 2419 | unsigned long exit_qualification; |
6aa8b732 AK |
2420 | unsigned long val; |
2421 | int dr, reg; | |
2422 | ||
2423 | /* | |
2424 | * FIXME: this code assumes the host is debugging the guest. | |
2425 | * need to deal with guest debugging itself too. | |
2426 | */ | |
bfdaab09 | 2427 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
2428 | dr = exit_qualification & 7; |
2429 | reg = (exit_qualification >> 8) & 15; | |
2430 | vcpu_load_rsp_rip(vcpu); | |
2431 | if (exit_qualification & 16) { | |
2432 | /* mov from dr */ | |
2433 | switch (dr) { | |
2434 | case 6: | |
2435 | val = 0xffff0ff0; | |
2436 | break; | |
2437 | case 7: | |
2438 | val = 0x400; | |
2439 | break; | |
2440 | default: | |
2441 | val = 0; | |
2442 | } | |
ad312c7c | 2443 | vcpu->arch.regs[reg] = val; |
2714d1d3 | 2444 | KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler); |
6aa8b732 AK |
2445 | } else { |
2446 | /* mov to dr */ | |
2447 | } | |
2448 | vcpu_put_rsp_rip(vcpu); | |
2449 | skip_emulated_instruction(vcpu); | |
2450 | return 1; | |
2451 | } | |
2452 | ||
2453 | static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2454 | { | |
06465c5a AK |
2455 | kvm_emulate_cpuid(vcpu); |
2456 | return 1; | |
6aa8b732 AK |
2457 | } |
2458 | ||
2459 | static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2460 | { | |
ad312c7c | 2461 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
2462 | u64 data; |
2463 | ||
2464 | if (vmx_get_msr(vcpu, ecx, &data)) { | |
c1a5d4f9 | 2465 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
2466 | return 1; |
2467 | } | |
2468 | ||
2714d1d3 FEL |
2469 | KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32), |
2470 | handler); | |
2471 | ||
6aa8b732 | 2472 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
ad312c7c ZX |
2473 | vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u; |
2474 | vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u; | |
6aa8b732 AK |
2475 | skip_emulated_instruction(vcpu); |
2476 | return 1; | |
2477 | } | |
2478 | ||
2479 | static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2480 | { | |
ad312c7c ZX |
2481 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
2482 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
2483 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 | 2484 | |
2714d1d3 FEL |
2485 | KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32), |
2486 | handler); | |
2487 | ||
6aa8b732 | 2488 | if (vmx_set_msr(vcpu, ecx, data) != 0) { |
c1a5d4f9 | 2489 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
2490 | return 1; |
2491 | } | |
2492 | ||
2493 | skip_emulated_instruction(vcpu); | |
2494 | return 1; | |
2495 | } | |
2496 | ||
6e5d865c YS |
2497 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu, |
2498 | struct kvm_run *kvm_run) | |
2499 | { | |
2500 | return 1; | |
2501 | } | |
2502 | ||
6aa8b732 AK |
2503 | static int handle_interrupt_window(struct kvm_vcpu *vcpu, |
2504 | struct kvm_run *kvm_run) | |
2505 | { | |
85f455f7 ED |
2506 | u32 cpu_based_vm_exec_control; |
2507 | ||
2508 | /* clear pending irq */ | |
2509 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2510 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
2511 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2714d1d3 FEL |
2512 | |
2513 | KVMTRACE_0D(PEND_INTR, vcpu, handler); | |
2514 | ||
c1150d8c DL |
2515 | /* |
2516 | * If the user space waits to inject interrupts, exit as soon as | |
2517 | * possible | |
2518 | */ | |
2519 | if (kvm_run->request_interrupt_window && | |
ad312c7c | 2520 | !vcpu->arch.irq_summary) { |
c1150d8c | 2521 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1165f5fe | 2522 | ++vcpu->stat.irq_window_exits; |
c1150d8c DL |
2523 | return 0; |
2524 | } | |
6aa8b732 AK |
2525 | return 1; |
2526 | } | |
2527 | ||
2528 | static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2529 | { | |
2530 | skip_emulated_instruction(vcpu); | |
d3bef15f | 2531 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
2532 | } |
2533 | ||
c21415e8 IM |
2534 | static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2535 | { | |
510043da | 2536 | skip_emulated_instruction(vcpu); |
7aa81cc0 AL |
2537 | kvm_emulate_hypercall(vcpu); |
2538 | return 1; | |
c21415e8 IM |
2539 | } |
2540 | ||
e5edaa01 ED |
2541 | static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2542 | { | |
2543 | skip_emulated_instruction(vcpu); | |
2544 | /* TODO: Add support for VT-d/pass-through device */ | |
2545 | return 1; | |
2546 | } | |
2547 | ||
f78e0e2e SY |
2548 | static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2549 | { | |
2550 | u64 exit_qualification; | |
2551 | enum emulation_result er; | |
2552 | unsigned long offset; | |
2553 | ||
2554 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
2555 | offset = exit_qualification & 0xffful; | |
2556 | ||
2557 | er = emulate_instruction(vcpu, kvm_run, 0, 0, 0); | |
2558 | ||
2559 | if (er != EMULATE_DONE) { | |
2560 | printk(KERN_ERR | |
2561 | "Fail to handle apic access vmexit! Offset is 0x%lx\n", | |
2562 | offset); | |
2563 | return -ENOTSUPP; | |
2564 | } | |
2565 | return 1; | |
2566 | } | |
2567 | ||
37817f29 IE |
2568 | static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2569 | { | |
2570 | unsigned long exit_qualification; | |
2571 | u16 tss_selector; | |
2572 | int reason; | |
2573 | ||
2574 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
2575 | ||
2576 | reason = (u32)exit_qualification >> 30; | |
2577 | tss_selector = exit_qualification; | |
2578 | ||
2579 | return kvm_task_switch(vcpu, tss_selector, reason); | |
2580 | } | |
2581 | ||
1439442c SY |
2582 | static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2583 | { | |
2584 | u64 exit_qualification; | |
2585 | enum emulation_result er; | |
2586 | gpa_t gpa; | |
2587 | unsigned long hva; | |
2588 | int gla_validity; | |
2589 | int r; | |
2590 | ||
2591 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
2592 | ||
2593 | if (exit_qualification & (1 << 6)) { | |
2594 | printk(KERN_ERR "EPT: GPA exceeds GAW!\n"); | |
2595 | return -ENOTSUPP; | |
2596 | } | |
2597 | ||
2598 | gla_validity = (exit_qualification >> 7) & 0x3; | |
2599 | if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) { | |
2600 | printk(KERN_ERR "EPT: Handling EPT violation failed!\n"); | |
2601 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | |
2602 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | |
2603 | (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS)); | |
2604 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", | |
2605 | (long unsigned int)exit_qualification); | |
2606 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
2607 | kvm_run->hw.hardware_exit_reason = 0; | |
2608 | return -ENOTSUPP; | |
2609 | } | |
2610 | ||
2611 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
2612 | hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT); | |
2613 | if (!kvm_is_error_hva(hva)) { | |
2614 | r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0); | |
2615 | if (r < 0) { | |
2616 | printk(KERN_ERR "EPT: Not enough memory!\n"); | |
2617 | return -ENOMEM; | |
2618 | } | |
2619 | return 1; | |
2620 | } else { | |
2621 | /* must be MMIO */ | |
2622 | er = emulate_instruction(vcpu, kvm_run, 0, 0, 0); | |
2623 | ||
2624 | if (er == EMULATE_FAIL) { | |
2625 | printk(KERN_ERR | |
2626 | "EPT: Fail to handle EPT violation vmexit!er is %d\n", | |
2627 | er); | |
2628 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | |
2629 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | |
2630 | (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS)); | |
2631 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", | |
2632 | (long unsigned int)exit_qualification); | |
2633 | return -ENOTSUPP; | |
2634 | } else if (er == EMULATE_DO_MMIO) | |
2635 | return 0; | |
2636 | } | |
2637 | return 1; | |
2638 | } | |
2639 | ||
6aa8b732 AK |
2640 | /* |
2641 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
2642 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
2643 | * to be done to userspace and return 0. | |
2644 | */ | |
2645 | static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu, | |
2646 | struct kvm_run *kvm_run) = { | |
2647 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, | |
2648 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 2649 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
6aa8b732 | 2650 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
2651 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
2652 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
2653 | [EXIT_REASON_CPUID] = handle_cpuid, | |
2654 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
2655 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
2656 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
2657 | [EXIT_REASON_HLT] = handle_halt, | |
c21415e8 | 2658 | [EXIT_REASON_VMCALL] = handle_vmcall, |
f78e0e2e SY |
2659 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
2660 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
e5edaa01 | 2661 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
37817f29 | 2662 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
1439442c | 2663 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
6aa8b732 AK |
2664 | }; |
2665 | ||
2666 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 2667 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 AK |
2668 | |
2669 | /* | |
2670 | * The guest has exited. See if we can fix it or if we need userspace | |
2671 | * assistance. | |
2672 | */ | |
2673 | static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) | |
2674 | { | |
6aa8b732 | 2675 | u32 exit_reason = vmcs_read32(VM_EXIT_REASON); |
29bd8a78 | 2676 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1155f76a | 2677 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 2678 | |
2714d1d3 FEL |
2679 | KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)vmcs_readl(GUEST_RIP), |
2680 | (u32)((u64)vmcs_readl(GUEST_RIP) >> 32), entryexit); | |
2681 | ||
1439442c SY |
2682 | /* Access CR3 don't cause VMExit in paging mode, so we need |
2683 | * to sync with guest real CR3. */ | |
2684 | if (vm_need_ept() && is_paging(vcpu)) { | |
2685 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); | |
2686 | ept_load_pdptrs(vcpu); | |
2687 | } | |
2688 | ||
29bd8a78 AK |
2689 | if (unlikely(vmx->fail)) { |
2690 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
2691 | kvm_run->fail_entry.hardware_entry_failure_reason | |
2692 | = vmcs_read32(VM_INSTRUCTION_ERROR); | |
2693 | return 0; | |
2694 | } | |
6aa8b732 | 2695 | |
d77c26fc | 2696 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c SY |
2697 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
2698 | exit_reason != EXIT_REASON_EPT_VIOLATION)) | |
6aa8b732 | 2699 | printk(KERN_WARNING "%s: unexpected, valid vectoring info and " |
b8688d51 | 2700 | "exit reason is 0x%x\n", __func__, exit_reason); |
6aa8b732 AK |
2701 | if (exit_reason < kvm_vmx_max_exit_handlers |
2702 | && kvm_vmx_exit_handlers[exit_reason]) | |
2703 | return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run); | |
2704 | else { | |
2705 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
2706 | kvm_run->hw.hardware_exit_reason = exit_reason; | |
2707 | } | |
2708 | return 0; | |
2709 | } | |
2710 | ||
6e5d865c YS |
2711 | static void update_tpr_threshold(struct kvm_vcpu *vcpu) |
2712 | { | |
2713 | int max_irr, tpr; | |
2714 | ||
2715 | if (!vm_need_tpr_shadow(vcpu->kvm)) | |
2716 | return; | |
2717 | ||
2718 | if (!kvm_lapic_enabled(vcpu) || | |
2719 | ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) { | |
2720 | vmcs_write32(TPR_THRESHOLD, 0); | |
2721 | return; | |
2722 | } | |
2723 | ||
2724 | tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4; | |
2725 | vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4); | |
2726 | } | |
2727 | ||
85f455f7 ED |
2728 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
2729 | { | |
2730 | u32 cpu_based_vm_exec_control; | |
2731 | ||
2732 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2733 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; | |
2734 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2735 | } | |
2736 | ||
2737 | static void vmx_intr_assist(struct kvm_vcpu *vcpu) | |
2738 | { | |
1155f76a | 2739 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
85f455f7 ED |
2740 | u32 idtv_info_field, intr_info_field; |
2741 | int has_ext_irq, interrupt_window_open; | |
1b9778da | 2742 | int vector; |
85f455f7 | 2743 | |
6e5d865c YS |
2744 | update_tpr_threshold(vcpu); |
2745 | ||
85f455f7 ED |
2746 | has_ext_irq = kvm_cpu_has_interrupt(vcpu); |
2747 | intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD); | |
1155f76a | 2748 | idtv_info_field = vmx->idt_vectoring_info; |
85f455f7 ED |
2749 | if (intr_info_field & INTR_INFO_VALID_MASK) { |
2750 | if (idtv_info_field & INTR_INFO_VALID_MASK) { | |
2751 | /* TODO: fault when IDT_Vectoring */ | |
9584bf2c RH |
2752 | if (printk_ratelimit()) |
2753 | printk(KERN_ERR "Fault when IDT_Vectoring\n"); | |
85f455f7 ED |
2754 | } |
2755 | if (has_ext_irq) | |
2756 | enable_irq_window(vcpu); | |
2757 | return; | |
2758 | } | |
2759 | if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) { | |
9c8cba37 AK |
2760 | if ((idtv_info_field & VECTORING_INFO_TYPE_MASK) |
2761 | == INTR_TYPE_EXT_INTR | |
ad312c7c | 2762 | && vcpu->arch.rmode.active) { |
9c8cba37 AK |
2763 | u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK; |
2764 | ||
2765 | vmx_inject_irq(vcpu, vect); | |
2766 | if (unlikely(has_ext_irq)) | |
2767 | enable_irq_window(vcpu); | |
2768 | return; | |
2769 | } | |
2770 | ||
2714d1d3 FEL |
2771 | KVMTRACE_1D(REDELIVER_EVT, vcpu, idtv_info_field, handler); |
2772 | ||
85f455f7 ED |
2773 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field); |
2774 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
2775 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); | |
2776 | ||
2e11384c | 2777 | if (unlikely(idtv_info_field & INTR_INFO_DELIVER_CODE_MASK)) |
85f455f7 ED |
2778 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, |
2779 | vmcs_read32(IDT_VECTORING_ERROR_CODE)); | |
2780 | if (unlikely(has_ext_irq)) | |
2781 | enable_irq_window(vcpu); | |
2782 | return; | |
2783 | } | |
2784 | if (!has_ext_irq) | |
2785 | return; | |
2786 | interrupt_window_open = | |
2787 | ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
2788 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0); | |
1b9778da ED |
2789 | if (interrupt_window_open) { |
2790 | vector = kvm_cpu_get_interrupt(vcpu); | |
2791 | vmx_inject_irq(vcpu, vector); | |
2792 | kvm_timer_intr_post(vcpu, vector); | |
2793 | } else | |
85f455f7 ED |
2794 | enable_irq_window(vcpu); |
2795 | } | |
2796 | ||
9c8cba37 AK |
2797 | /* |
2798 | * Failure to inject an interrupt should give us the information | |
2799 | * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs | |
2800 | * when fetching the interrupt redirection bitmap in the real-mode | |
2801 | * tss, this doesn't happen. So we do it ourselves. | |
2802 | */ | |
2803 | static void fixup_rmode_irq(struct vcpu_vmx *vmx) | |
2804 | { | |
2805 | vmx->rmode.irq.pending = 0; | |
2806 | if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip) | |
2807 | return; | |
2808 | vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip); | |
2809 | if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) { | |
2810 | vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK; | |
2811 | vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR; | |
2812 | return; | |
2813 | } | |
2814 | vmx->idt_vectoring_info = | |
2815 | VECTORING_INFO_VALID_MASK | |
2816 | | INTR_TYPE_EXT_INTR | |
2817 | | vmx->rmode.irq.vector; | |
2818 | } | |
2819 | ||
04d2cc77 | 2820 | static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
6aa8b732 | 2821 | { |
a2fa3e9f | 2822 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1b6269db | 2823 | u32 intr_info; |
e6adf283 AK |
2824 | |
2825 | /* | |
2826 | * Loading guest fpu may have cleared host cr0.ts | |
2827 | */ | |
2828 | vmcs_writel(HOST_CR0, read_cr0()); | |
2829 | ||
d77c26fc | 2830 | asm( |
6aa8b732 | 2831 | /* Store host registers */ |
05b3e0c2 | 2832 | #ifdef CONFIG_X86_64 |
c2036300 | 2833 | "push %%rdx; push %%rbp;" |
6aa8b732 | 2834 | "push %%rcx \n\t" |
6aa8b732 | 2835 | #else |
ff593e5a LV |
2836 | "push %%edx; push %%ebp;" |
2837 | "push %%ecx \n\t" | |
6aa8b732 | 2838 | #endif |
c2036300 | 2839 | ASM_VMX_VMWRITE_RSP_RDX "\n\t" |
6aa8b732 | 2840 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 2841 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 2842 | /* Load guest registers. Don't clobber flags. */ |
05b3e0c2 | 2843 | #ifdef CONFIG_X86_64 |
e08aa78a | 2844 | "mov %c[cr2](%0), %%rax \n\t" |
6aa8b732 | 2845 | "mov %%rax, %%cr2 \n\t" |
e08aa78a AK |
2846 | "mov %c[rax](%0), %%rax \n\t" |
2847 | "mov %c[rbx](%0), %%rbx \n\t" | |
2848 | "mov %c[rdx](%0), %%rdx \n\t" | |
2849 | "mov %c[rsi](%0), %%rsi \n\t" | |
2850 | "mov %c[rdi](%0), %%rdi \n\t" | |
2851 | "mov %c[rbp](%0), %%rbp \n\t" | |
2852 | "mov %c[r8](%0), %%r8 \n\t" | |
2853 | "mov %c[r9](%0), %%r9 \n\t" | |
2854 | "mov %c[r10](%0), %%r10 \n\t" | |
2855 | "mov %c[r11](%0), %%r11 \n\t" | |
2856 | "mov %c[r12](%0), %%r12 \n\t" | |
2857 | "mov %c[r13](%0), %%r13 \n\t" | |
2858 | "mov %c[r14](%0), %%r14 \n\t" | |
2859 | "mov %c[r15](%0), %%r15 \n\t" | |
2860 | "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */ | |
6aa8b732 | 2861 | #else |
e08aa78a | 2862 | "mov %c[cr2](%0), %%eax \n\t" |
6aa8b732 | 2863 | "mov %%eax, %%cr2 \n\t" |
e08aa78a AK |
2864 | "mov %c[rax](%0), %%eax \n\t" |
2865 | "mov %c[rbx](%0), %%ebx \n\t" | |
2866 | "mov %c[rdx](%0), %%edx \n\t" | |
2867 | "mov %c[rsi](%0), %%esi \n\t" | |
2868 | "mov %c[rdi](%0), %%edi \n\t" | |
2869 | "mov %c[rbp](%0), %%ebp \n\t" | |
2870 | "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */ | |
6aa8b732 AK |
2871 | #endif |
2872 | /* Enter guest mode */ | |
cd2276a7 | 2873 | "jne .Llaunched \n\t" |
6aa8b732 | 2874 | ASM_VMX_VMLAUNCH "\n\t" |
cd2276a7 AK |
2875 | "jmp .Lkvm_vmx_return \n\t" |
2876 | ".Llaunched: " ASM_VMX_VMRESUME "\n\t" | |
2877 | ".Lkvm_vmx_return: " | |
6aa8b732 | 2878 | /* Save guest registers, load host registers, keep flags */ |
05b3e0c2 | 2879 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
2880 | "xchg %0, (%%rsp) \n\t" |
2881 | "mov %%rax, %c[rax](%0) \n\t" | |
2882 | "mov %%rbx, %c[rbx](%0) \n\t" | |
2883 | "pushq (%%rsp); popq %c[rcx](%0) \n\t" | |
2884 | "mov %%rdx, %c[rdx](%0) \n\t" | |
2885 | "mov %%rsi, %c[rsi](%0) \n\t" | |
2886 | "mov %%rdi, %c[rdi](%0) \n\t" | |
2887 | "mov %%rbp, %c[rbp](%0) \n\t" | |
2888 | "mov %%r8, %c[r8](%0) \n\t" | |
2889 | "mov %%r9, %c[r9](%0) \n\t" | |
2890 | "mov %%r10, %c[r10](%0) \n\t" | |
2891 | "mov %%r11, %c[r11](%0) \n\t" | |
2892 | "mov %%r12, %c[r12](%0) \n\t" | |
2893 | "mov %%r13, %c[r13](%0) \n\t" | |
2894 | "mov %%r14, %c[r14](%0) \n\t" | |
2895 | "mov %%r15, %c[r15](%0) \n\t" | |
6aa8b732 | 2896 | "mov %%cr2, %%rax \n\t" |
e08aa78a | 2897 | "mov %%rax, %c[cr2](%0) \n\t" |
6aa8b732 | 2898 | |
e08aa78a | 2899 | "pop %%rbp; pop %%rbp; pop %%rdx \n\t" |
6aa8b732 | 2900 | #else |
e08aa78a AK |
2901 | "xchg %0, (%%esp) \n\t" |
2902 | "mov %%eax, %c[rax](%0) \n\t" | |
2903 | "mov %%ebx, %c[rbx](%0) \n\t" | |
2904 | "pushl (%%esp); popl %c[rcx](%0) \n\t" | |
2905 | "mov %%edx, %c[rdx](%0) \n\t" | |
2906 | "mov %%esi, %c[rsi](%0) \n\t" | |
2907 | "mov %%edi, %c[rdi](%0) \n\t" | |
2908 | "mov %%ebp, %c[rbp](%0) \n\t" | |
6aa8b732 | 2909 | "mov %%cr2, %%eax \n\t" |
e08aa78a | 2910 | "mov %%eax, %c[cr2](%0) \n\t" |
6aa8b732 | 2911 | |
e08aa78a | 2912 | "pop %%ebp; pop %%ebp; pop %%edx \n\t" |
6aa8b732 | 2913 | #endif |
e08aa78a AK |
2914 | "setbe %c[fail](%0) \n\t" |
2915 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), | |
2916 | [launched]"i"(offsetof(struct vcpu_vmx, launched)), | |
2917 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), | |
ad312c7c ZX |
2918 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
2919 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
2920 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
2921 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
2922 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
2923 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
2924 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 2925 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
2926 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
2927 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
2928 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
2929 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
2930 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
2931 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
2932 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
2933 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 2934 | #endif |
ad312c7c | 2935 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)) |
c2036300 LV |
2936 | : "cc", "memory" |
2937 | #ifdef CONFIG_X86_64 | |
2938 | , "rbx", "rdi", "rsi" | |
2939 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
ff593e5a LV |
2940 | #else |
2941 | , "ebx", "edi", "rsi" | |
c2036300 LV |
2942 | #endif |
2943 | ); | |
6aa8b732 | 2944 | |
1155f76a | 2945 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); |
9c8cba37 AK |
2946 | if (vmx->rmode.irq.pending) |
2947 | fixup_rmode_irq(vmx); | |
1155f76a | 2948 | |
ad312c7c | 2949 | vcpu->arch.interrupt_window_open = |
d77c26fc | 2950 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0; |
6aa8b732 | 2951 | |
d77c26fc | 2952 | asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS)); |
15ad7146 | 2953 | vmx->launched = 1; |
1b6269db AK |
2954 | |
2955 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
2956 | ||
2957 | /* We need to handle NMIs before interrupts are enabled */ | |
2714d1d3 FEL |
2958 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */ |
2959 | KVMTRACE_0D(NMI, vcpu, handler); | |
1b6269db | 2960 | asm("int $2"); |
2714d1d3 | 2961 | } |
6aa8b732 AK |
2962 | } |
2963 | ||
6aa8b732 AK |
2964 | static void vmx_free_vmcs(struct kvm_vcpu *vcpu) |
2965 | { | |
a2fa3e9f GH |
2966 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2967 | ||
2968 | if (vmx->vmcs) { | |
15c8b6c1 | 2969 | on_each_cpu(__vcpu_clear, vmx, 1); |
a2fa3e9f GH |
2970 | free_vmcs(vmx->vmcs); |
2971 | vmx->vmcs = NULL; | |
6aa8b732 AK |
2972 | } |
2973 | } | |
2974 | ||
2975 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) | |
2976 | { | |
fb3f0f51 RR |
2977 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2978 | ||
2384d2b3 SY |
2979 | spin_lock(&vmx_vpid_lock); |
2980 | if (vmx->vpid != 0) | |
2981 | __clear_bit(vmx->vpid, vmx_vpid_bitmap); | |
2982 | spin_unlock(&vmx_vpid_lock); | |
6aa8b732 | 2983 | vmx_free_vmcs(vcpu); |
fb3f0f51 RR |
2984 | kfree(vmx->host_msrs); |
2985 | kfree(vmx->guest_msrs); | |
2986 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 2987 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
2988 | } |
2989 | ||
fb3f0f51 | 2990 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 2991 | { |
fb3f0f51 | 2992 | int err; |
c16f862d | 2993 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
15ad7146 | 2994 | int cpu; |
6aa8b732 | 2995 | |
a2fa3e9f | 2996 | if (!vmx) |
fb3f0f51 RR |
2997 | return ERR_PTR(-ENOMEM); |
2998 | ||
2384d2b3 | 2999 | allocate_vpid(vmx); |
1439442c SY |
3000 | if (id == 0 && vm_need_ept()) { |
3001 | kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK | | |
3002 | VMX_EPT_WRITABLE_MASK | | |
3003 | VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT); | |
3004 | kvm_mmu_set_mask_ptes(0ull, VMX_EPT_FAKE_ACCESSED_MASK, | |
3005 | VMX_EPT_FAKE_DIRTY_MASK, 0ull, | |
3006 | VMX_EPT_EXECUTABLE_MASK); | |
3007 | kvm_enable_tdp(); | |
3008 | } | |
2384d2b3 | 3009 | |
fb3f0f51 RR |
3010 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
3011 | if (err) | |
3012 | goto free_vcpu; | |
965b58a5 | 3013 | |
a2fa3e9f | 3014 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
fb3f0f51 RR |
3015 | if (!vmx->guest_msrs) { |
3016 | err = -ENOMEM; | |
3017 | goto uninit_vcpu; | |
3018 | } | |
965b58a5 | 3019 | |
a2fa3e9f GH |
3020 | vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
3021 | if (!vmx->host_msrs) | |
fb3f0f51 | 3022 | goto free_guest_msrs; |
965b58a5 | 3023 | |
a2fa3e9f GH |
3024 | vmx->vmcs = alloc_vmcs(); |
3025 | if (!vmx->vmcs) | |
fb3f0f51 | 3026 | goto free_msrs; |
a2fa3e9f GH |
3027 | |
3028 | vmcs_clear(vmx->vmcs); | |
3029 | ||
15ad7146 AK |
3030 | cpu = get_cpu(); |
3031 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
8b9cf98c | 3032 | err = vmx_vcpu_setup(vmx); |
fb3f0f51 | 3033 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 3034 | put_cpu(); |
fb3f0f51 RR |
3035 | if (err) |
3036 | goto free_vmcs; | |
5e4a0b3c MT |
3037 | if (vm_need_virtualize_apic_accesses(kvm)) |
3038 | if (alloc_apic_access_page(kvm) != 0) | |
3039 | goto free_vmcs; | |
fb3f0f51 | 3040 | |
b7ebfb05 SY |
3041 | if (vm_need_ept()) |
3042 | if (alloc_identity_pagetable(kvm) != 0) | |
3043 | goto free_vmcs; | |
3044 | ||
fb3f0f51 RR |
3045 | return &vmx->vcpu; |
3046 | ||
3047 | free_vmcs: | |
3048 | free_vmcs(vmx->vmcs); | |
3049 | free_msrs: | |
3050 | kfree(vmx->host_msrs); | |
3051 | free_guest_msrs: | |
3052 | kfree(vmx->guest_msrs); | |
3053 | uninit_vcpu: | |
3054 | kvm_vcpu_uninit(&vmx->vcpu); | |
3055 | free_vcpu: | |
a4770347 | 3056 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 3057 | return ERR_PTR(err); |
6aa8b732 AK |
3058 | } |
3059 | ||
002c7f7c YS |
3060 | static void __init vmx_check_processor_compat(void *rtn) |
3061 | { | |
3062 | struct vmcs_config vmcs_conf; | |
3063 | ||
3064 | *(int *)rtn = 0; | |
3065 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
3066 | *(int *)rtn = -EIO; | |
3067 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
3068 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
3069 | smp_processor_id()); | |
3070 | *(int *)rtn = -EIO; | |
3071 | } | |
3072 | } | |
3073 | ||
67253af5 SY |
3074 | static int get_ept_level(void) |
3075 | { | |
3076 | return VMX_EPT_DEFAULT_GAW + 1; | |
3077 | } | |
3078 | ||
cbdd1bea | 3079 | static struct kvm_x86_ops vmx_x86_ops = { |
6aa8b732 AK |
3080 | .cpu_has_kvm_support = cpu_has_kvm_support, |
3081 | .disabled_by_bios = vmx_disabled_by_bios, | |
3082 | .hardware_setup = hardware_setup, | |
3083 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 3084 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
3085 | .hardware_enable = hardware_enable, |
3086 | .hardware_disable = hardware_disable, | |
774ead3a | 3087 | .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses, |
6aa8b732 AK |
3088 | |
3089 | .vcpu_create = vmx_create_vcpu, | |
3090 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 3091 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 3092 | |
04d2cc77 | 3093 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
3094 | .vcpu_load = vmx_vcpu_load, |
3095 | .vcpu_put = vmx_vcpu_put, | |
774c47f1 | 3096 | .vcpu_decache = vmx_vcpu_decache, |
6aa8b732 AK |
3097 | |
3098 | .set_guest_debug = set_guest_debug, | |
04d2cc77 | 3099 | .guest_debug_pre = kvm_guest_debug_pre, |
6aa8b732 AK |
3100 | .get_msr = vmx_get_msr, |
3101 | .set_msr = vmx_set_msr, | |
3102 | .get_segment_base = vmx_get_segment_base, | |
3103 | .get_segment = vmx_get_segment, | |
3104 | .set_segment = vmx_set_segment, | |
2e4d2653 | 3105 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 3106 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
25c4c276 | 3107 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 3108 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
3109 | .set_cr3 = vmx_set_cr3, |
3110 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 3111 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
3112 | .get_idt = vmx_get_idt, |
3113 | .set_idt = vmx_set_idt, | |
3114 | .get_gdt = vmx_get_gdt, | |
3115 | .set_gdt = vmx_set_gdt, | |
3116 | .cache_regs = vcpu_load_rsp_rip, | |
3117 | .decache_regs = vcpu_put_rsp_rip, | |
3118 | .get_rflags = vmx_get_rflags, | |
3119 | .set_rflags = vmx_set_rflags, | |
3120 | ||
3121 | .tlb_flush = vmx_flush_tlb, | |
6aa8b732 | 3122 | |
6aa8b732 | 3123 | .run = vmx_vcpu_run, |
04d2cc77 | 3124 | .handle_exit = kvm_handle_exit, |
6aa8b732 | 3125 | .skip_emulated_instruction = skip_emulated_instruction, |
102d8325 | 3126 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 ED |
3127 | .get_irq = vmx_get_irq, |
3128 | .set_irq = vmx_inject_irq, | |
298101da AK |
3129 | .queue_exception = vmx_queue_exception, |
3130 | .exception_injected = vmx_exception_injected, | |
04d2cc77 AK |
3131 | .inject_pending_irq = vmx_intr_assist, |
3132 | .inject_pending_vectors = do_interrupt_requests, | |
cbc94022 IE |
3133 | |
3134 | .set_tss_addr = vmx_set_tss_addr, | |
67253af5 | 3135 | .get_tdp_level = get_ept_level, |
6aa8b732 AK |
3136 | }; |
3137 | ||
3138 | static int __init vmx_init(void) | |
3139 | { | |
25c5f225 | 3140 | void *va; |
fdef3ad1 HQ |
3141 | int r; |
3142 | ||
3143 | vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
3144 | if (!vmx_io_bitmap_a) | |
3145 | return -ENOMEM; | |
3146 | ||
3147 | vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
3148 | if (!vmx_io_bitmap_b) { | |
3149 | r = -ENOMEM; | |
3150 | goto out; | |
3151 | } | |
3152 | ||
25c5f225 SY |
3153 | vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); |
3154 | if (!vmx_msr_bitmap) { | |
3155 | r = -ENOMEM; | |
3156 | goto out1; | |
3157 | } | |
3158 | ||
fdef3ad1 HQ |
3159 | /* |
3160 | * Allow direct access to the PC debug port (it is often used for I/O | |
3161 | * delays, but the vmexits simply slow things down). | |
3162 | */ | |
25c5f225 SY |
3163 | va = kmap(vmx_io_bitmap_a); |
3164 | memset(va, 0xff, PAGE_SIZE); | |
3165 | clear_bit(0x80, va); | |
cd0536d7 | 3166 | kunmap(vmx_io_bitmap_a); |
fdef3ad1 | 3167 | |
25c5f225 SY |
3168 | va = kmap(vmx_io_bitmap_b); |
3169 | memset(va, 0xff, PAGE_SIZE); | |
cd0536d7 | 3170 | kunmap(vmx_io_bitmap_b); |
fdef3ad1 | 3171 | |
25c5f225 SY |
3172 | va = kmap(vmx_msr_bitmap); |
3173 | memset(va, 0xff, PAGE_SIZE); | |
3174 | kunmap(vmx_msr_bitmap); | |
3175 | ||
2384d2b3 SY |
3176 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
3177 | ||
cb498ea2 | 3178 | r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE); |
fdef3ad1 | 3179 | if (r) |
25c5f225 SY |
3180 | goto out2; |
3181 | ||
3182 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE); | |
3183 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE); | |
3184 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS); | |
3185 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP); | |
3186 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP); | |
fdef3ad1 | 3187 | |
1439442c SY |
3188 | if (cpu_has_vmx_ept()) |
3189 | bypass_guest_pf = 0; | |
3190 | ||
c7addb90 AK |
3191 | if (bypass_guest_pf) |
3192 | kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull); | |
3193 | ||
1439442c SY |
3194 | ept_sync_global(); |
3195 | ||
fdef3ad1 HQ |
3196 | return 0; |
3197 | ||
25c5f225 SY |
3198 | out2: |
3199 | __free_page(vmx_msr_bitmap); | |
fdef3ad1 HQ |
3200 | out1: |
3201 | __free_page(vmx_io_bitmap_b); | |
3202 | out: | |
3203 | __free_page(vmx_io_bitmap_a); | |
3204 | return r; | |
6aa8b732 AK |
3205 | } |
3206 | ||
3207 | static void __exit vmx_exit(void) | |
3208 | { | |
25c5f225 | 3209 | __free_page(vmx_msr_bitmap); |
fdef3ad1 HQ |
3210 | __free_page(vmx_io_bitmap_b); |
3211 | __free_page(vmx_io_bitmap_a); | |
3212 | ||
cb498ea2 | 3213 | kvm_exit(); |
6aa8b732 AK |
3214 | } |
3215 | ||
3216 | module_init(vmx_init) | |
3217 | module_exit(vmx_exit) |