Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 8 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
9 | * |
10 | * Authors: | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * | |
14 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
15 | * the COPYING file in the top-level directory. | |
16 | * | |
17 | */ | |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
e495606d | 21 | |
edf88417 | 22 | #include <linux/kvm_host.h> |
6aa8b732 | 23 | #include <linux/module.h> |
9d8f549d | 24 | #include <linux/kernel.h> |
6aa8b732 AK |
25 | #include <linux/mm.h> |
26 | #include <linux/highmem.h> | |
e8edc6e0 | 27 | #include <linux/sched.h> |
c7addb90 | 28 | #include <linux/moduleparam.h> |
229456fc | 29 | #include <linux/ftrace_event.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
cafd6659 | 31 | #include <linux/tboot.h> |
5fdbf976 | 32 | #include "kvm_cache_regs.h" |
35920a35 | 33 | #include "x86.h" |
e495606d | 34 | |
6aa8b732 | 35 | #include <asm/io.h> |
3b3be0d1 | 36 | #include <asm/desc.h> |
13673a90 | 37 | #include <asm/vmx.h> |
6210e37b | 38 | #include <asm/virtext.h> |
a0861c02 | 39 | #include <asm/mce.h> |
2acf923e DC |
40 | #include <asm/i387.h> |
41 | #include <asm/xcr.h> | |
6aa8b732 | 42 | |
229456fc MT |
43 | #include "trace.h" |
44 | ||
4ecac3fd | 45 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
5e520e62 AK |
46 | #define __ex_clear(x, reg) \ |
47 | ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg) | |
4ecac3fd | 48 | |
6aa8b732 AK |
49 | MODULE_AUTHOR("Qumranet"); |
50 | MODULE_LICENSE("GPL"); | |
51 | ||
4462d21a | 52 | static int __read_mostly bypass_guest_pf = 1; |
c1f8bc04 | 53 | module_param(bypass_guest_pf, bool, S_IRUGO); |
c7addb90 | 54 | |
4462d21a | 55 | static int __read_mostly enable_vpid = 1; |
736caefe | 56 | module_param_named(vpid, enable_vpid, bool, 0444); |
2384d2b3 | 57 | |
4462d21a | 58 | static int __read_mostly flexpriority_enabled = 1; |
736caefe | 59 | module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); |
4c9fc8ef | 60 | |
4462d21a | 61 | static int __read_mostly enable_ept = 1; |
736caefe | 62 | module_param_named(ept, enable_ept, bool, S_IRUGO); |
d56f546d | 63 | |
3a624e29 NK |
64 | static int __read_mostly enable_unrestricted_guest = 1; |
65 | module_param_named(unrestricted_guest, | |
66 | enable_unrestricted_guest, bool, S_IRUGO); | |
67 | ||
4462d21a | 68 | static int __read_mostly emulate_invalid_guest_state = 0; |
c1f8bc04 | 69 | module_param(emulate_invalid_guest_state, bool, S_IRUGO); |
04fa4d32 | 70 | |
b923e62e DX |
71 | static int __read_mostly vmm_exclusive = 1; |
72 | module_param(vmm_exclusive, bool, S_IRUGO); | |
73 | ||
443381a8 AL |
74 | static int __read_mostly yield_on_hlt = 1; |
75 | module_param(yield_on_hlt, bool, S_IRUGO); | |
76 | ||
801d3424 NHE |
77 | /* |
78 | * If nested=1, nested virtualization is supported, i.e., guests may use | |
79 | * VMX and be a hypervisor for its own guests. If nested=0, guests may not | |
80 | * use VMX instructions. | |
81 | */ | |
82 | static int __read_mostly nested = 0; | |
83 | module_param(nested, bool, S_IRUGO); | |
84 | ||
cdc0e244 AK |
85 | #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \ |
86 | (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD) | |
87 | #define KVM_GUEST_CR0_MASK \ | |
88 | (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) | |
89 | #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \ | |
81231c69 | 90 | (X86_CR0_WP | X86_CR0_NE) |
cdc0e244 AK |
91 | #define KVM_VM_CR0_ALWAYS_ON \ |
92 | (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) | |
4c38609a AK |
93 | #define KVM_CR4_GUEST_OWNED_BITS \ |
94 | (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
95 | | X86_CR4_OSXMMEXCPT) | |
96 | ||
cdc0e244 AK |
97 | #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) |
98 | #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) | |
99 | ||
78ac8b47 AK |
100 | #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) |
101 | ||
4b8d54f9 ZE |
102 | /* |
103 | * These 2 parameters are used to config the controls for Pause-Loop Exiting: | |
104 | * ple_gap: upper bound on the amount of time between two successive | |
105 | * executions of PAUSE in a loop. Also indicate if ple enabled. | |
00c25bce | 106 | * According to test, this time is usually smaller than 128 cycles. |
4b8d54f9 ZE |
107 | * ple_window: upper bound on the amount of time a guest is allowed to execute |
108 | * in a PAUSE loop. Tests indicate that most spinlocks are held for | |
109 | * less than 2^12 cycles | |
110 | * Time is measured based on a counter that runs at the same rate as the TSC, | |
111 | * refer SDM volume 3b section 21.6.13 & 22.1.3. | |
112 | */ | |
00c25bce | 113 | #define KVM_VMX_DEFAULT_PLE_GAP 128 |
4b8d54f9 ZE |
114 | #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 |
115 | static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP; | |
116 | module_param(ple_gap, int, S_IRUGO); | |
117 | ||
118 | static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; | |
119 | module_param(ple_window, int, S_IRUGO); | |
120 | ||
61d2ef2c AK |
121 | #define NR_AUTOLOAD_MSRS 1 |
122 | ||
a2fa3e9f GH |
123 | struct vmcs { |
124 | u32 revision_id; | |
125 | u32 abort; | |
126 | char data[0]; | |
127 | }; | |
128 | ||
d462b819 NHE |
129 | /* |
130 | * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also | |
131 | * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs | |
132 | * loaded on this CPU (so we can clear them if the CPU goes down). | |
133 | */ | |
134 | struct loaded_vmcs { | |
135 | struct vmcs *vmcs; | |
136 | int cpu; | |
137 | int launched; | |
138 | struct list_head loaded_vmcss_on_cpu_link; | |
139 | }; | |
140 | ||
26bb0981 AK |
141 | struct shared_msr_entry { |
142 | unsigned index; | |
143 | u64 data; | |
d5696725 | 144 | u64 mask; |
26bb0981 AK |
145 | }; |
146 | ||
a9d30f33 NHE |
147 | /* |
148 | * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a | |
149 | * single nested guest (L2), hence the name vmcs12. Any VMX implementation has | |
150 | * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is | |
151 | * stored in guest memory specified by VMPTRLD, but is opaque to the guest, | |
152 | * which must access it using VMREAD/VMWRITE/VMCLEAR instructions. | |
153 | * More than one of these structures may exist, if L1 runs multiple L2 guests. | |
154 | * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the | |
155 | * underlying hardware which will be used to run L2. | |
156 | * This structure is packed to ensure that its layout is identical across | |
157 | * machines (necessary for live migration). | |
158 | * If there are changes in this struct, VMCS12_REVISION must be changed. | |
159 | */ | |
160 | struct __packed vmcs12 { | |
161 | /* According to the Intel spec, a VMCS region must start with the | |
162 | * following two fields. Then follow implementation-specific data. | |
163 | */ | |
164 | u32 revision_id; | |
165 | u32 abort; | |
166 | }; | |
167 | ||
168 | /* | |
169 | * VMCS12_REVISION is an arbitrary id that should be changed if the content or | |
170 | * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and | |
171 | * VMPTRLD verifies that the VMCS region that L1 is loading contains this id. | |
172 | */ | |
173 | #define VMCS12_REVISION 0x11e57ed0 | |
174 | ||
175 | /* | |
176 | * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region | |
177 | * and any VMCS region. Although only sizeof(struct vmcs12) are used by the | |
178 | * current implementation, 4K are reserved to avoid future complications. | |
179 | */ | |
180 | #define VMCS12_SIZE 0x1000 | |
181 | ||
ec378aee NHE |
182 | /* |
183 | * The nested_vmx structure is part of vcpu_vmx, and holds information we need | |
184 | * for correct emulation of VMX (i.e., nested VMX) on this vcpu. | |
185 | */ | |
186 | struct nested_vmx { | |
187 | /* Has the level1 guest done vmxon? */ | |
188 | bool vmxon; | |
a9d30f33 NHE |
189 | |
190 | /* The guest-physical address of the current VMCS L1 keeps for L2 */ | |
191 | gpa_t current_vmptr; | |
192 | /* The host-usable pointer to the above */ | |
193 | struct page *current_vmcs12_page; | |
194 | struct vmcs12 *current_vmcs12; | |
ec378aee NHE |
195 | }; |
196 | ||
a2fa3e9f | 197 | struct vcpu_vmx { |
fb3f0f51 | 198 | struct kvm_vcpu vcpu; |
313dbd49 | 199 | unsigned long host_rsp; |
29bd8a78 | 200 | u8 fail; |
69c73028 | 201 | u8 cpl; |
9d58b931 | 202 | bool nmi_known_unmasked; |
51aa01d1 | 203 | u32 exit_intr_info; |
1155f76a | 204 | u32 idt_vectoring_info; |
6de12732 | 205 | ulong rflags; |
26bb0981 | 206 | struct shared_msr_entry *guest_msrs; |
a2fa3e9f GH |
207 | int nmsrs; |
208 | int save_nmsrs; | |
a2fa3e9f | 209 | #ifdef CONFIG_X86_64 |
44ea2b17 AK |
210 | u64 msr_host_kernel_gs_base; |
211 | u64 msr_guest_kernel_gs_base; | |
a2fa3e9f | 212 | #endif |
d462b819 NHE |
213 | /* |
214 | * loaded_vmcs points to the VMCS currently used in this vcpu. For a | |
215 | * non-nested (L1) guest, it always points to vmcs01. For a nested | |
216 | * guest (L2), it points to a different VMCS. | |
217 | */ | |
218 | struct loaded_vmcs vmcs01; | |
219 | struct loaded_vmcs *loaded_vmcs; | |
220 | bool __launched; /* temporary, used in vmx_vcpu_run */ | |
61d2ef2c AK |
221 | struct msr_autoload { |
222 | unsigned nr; | |
223 | struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS]; | |
224 | struct vmx_msr_entry host[NR_AUTOLOAD_MSRS]; | |
225 | } msr_autoload; | |
a2fa3e9f GH |
226 | struct { |
227 | int loaded; | |
228 | u16 fs_sel, gs_sel, ldt_sel; | |
152d3f2f LV |
229 | int gs_ldt_reload_needed; |
230 | int fs_reload_needed; | |
d77c26fc | 231 | } host_state; |
9c8cba37 | 232 | struct { |
7ffd92c5 | 233 | int vm86_active; |
78ac8b47 | 234 | ulong save_rflags; |
7ffd92c5 AK |
235 | struct kvm_save_segment { |
236 | u16 selector; | |
237 | unsigned long base; | |
238 | u32 limit; | |
239 | u32 ar; | |
240 | } tr, es, ds, fs, gs; | |
9c8cba37 | 241 | } rmode; |
2fb92db1 AK |
242 | struct { |
243 | u32 bitmask; /* 4 bits per segment (1 bit per field) */ | |
244 | struct kvm_save_segment seg[8]; | |
245 | } segment_cache; | |
2384d2b3 | 246 | int vpid; |
04fa4d32 | 247 | bool emulation_required; |
3b86cd99 JK |
248 | |
249 | /* Support for vnmi-less CPUs */ | |
250 | int soft_vnmi_blocked; | |
251 | ktime_t entry_time; | |
252 | s64 vnmi_blocked_time; | |
a0861c02 | 253 | u32 exit_reason; |
4e47c7a6 SY |
254 | |
255 | bool rdtscp_enabled; | |
ec378aee NHE |
256 | |
257 | /* Support for a guest hypervisor (nested VMX) */ | |
258 | struct nested_vmx nested; | |
a2fa3e9f GH |
259 | }; |
260 | ||
2fb92db1 AK |
261 | enum segment_cache_field { |
262 | SEG_FIELD_SEL = 0, | |
263 | SEG_FIELD_BASE = 1, | |
264 | SEG_FIELD_LIMIT = 2, | |
265 | SEG_FIELD_AR = 3, | |
266 | ||
267 | SEG_FIELD_NR = 4 | |
268 | }; | |
269 | ||
a2fa3e9f GH |
270 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) |
271 | { | |
fb3f0f51 | 272 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
273 | } |
274 | ||
a9d30f33 NHE |
275 | static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu) |
276 | { | |
277 | return to_vmx(vcpu)->nested.current_vmcs12; | |
278 | } | |
279 | ||
280 | static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr) | |
281 | { | |
282 | struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT); | |
283 | if (is_error_page(page)) { | |
284 | kvm_release_page_clean(page); | |
285 | return NULL; | |
286 | } | |
287 | return page; | |
288 | } | |
289 | ||
290 | static void nested_release_page(struct page *page) | |
291 | { | |
292 | kvm_release_page_dirty(page); | |
293 | } | |
294 | ||
295 | static void nested_release_page_clean(struct page *page) | |
296 | { | |
297 | kvm_release_page_clean(page); | |
298 | } | |
299 | ||
4e1096d2 | 300 | static u64 construct_eptp(unsigned long root_hpa); |
4610c9cc DX |
301 | static void kvm_cpu_vmxon(u64 addr); |
302 | static void kvm_cpu_vmxoff(void); | |
aff48baa | 303 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); |
776e58ea | 304 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr); |
75880a01 | 305 | |
6aa8b732 AK |
306 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
307 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
d462b819 NHE |
308 | /* |
309 | * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed | |
310 | * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. | |
311 | */ | |
312 | static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); | |
3444d7da | 313 | static DEFINE_PER_CPU(struct desc_ptr, host_gdt); |
6aa8b732 | 314 | |
3e7c73e9 AK |
315 | static unsigned long *vmx_io_bitmap_a; |
316 | static unsigned long *vmx_io_bitmap_b; | |
5897297b AK |
317 | static unsigned long *vmx_msr_bitmap_legacy; |
318 | static unsigned long *vmx_msr_bitmap_longmode; | |
fdef3ad1 | 319 | |
110312c8 AK |
320 | static bool cpu_has_load_ia32_efer; |
321 | ||
2384d2b3 SY |
322 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
323 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
324 | ||
1c3d14fe | 325 | static struct vmcs_config { |
6aa8b732 AK |
326 | int size; |
327 | int order; | |
328 | u32 revision_id; | |
1c3d14fe YS |
329 | u32 pin_based_exec_ctrl; |
330 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 331 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
332 | u32 vmexit_ctrl; |
333 | u32 vmentry_ctrl; | |
334 | } vmcs_config; | |
6aa8b732 | 335 | |
efff9e53 | 336 | static struct vmx_capability { |
d56f546d SY |
337 | u32 ept; |
338 | u32 vpid; | |
339 | } vmx_capability; | |
340 | ||
6aa8b732 AK |
341 | #define VMX_SEGMENT_FIELD(seg) \ |
342 | [VCPU_SREG_##seg] = { \ | |
343 | .selector = GUEST_##seg##_SELECTOR, \ | |
344 | .base = GUEST_##seg##_BASE, \ | |
345 | .limit = GUEST_##seg##_LIMIT, \ | |
346 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
347 | } | |
348 | ||
349 | static struct kvm_vmx_segment_field { | |
350 | unsigned selector; | |
351 | unsigned base; | |
352 | unsigned limit; | |
353 | unsigned ar_bytes; | |
354 | } kvm_vmx_segment_fields[] = { | |
355 | VMX_SEGMENT_FIELD(CS), | |
356 | VMX_SEGMENT_FIELD(DS), | |
357 | VMX_SEGMENT_FIELD(ES), | |
358 | VMX_SEGMENT_FIELD(FS), | |
359 | VMX_SEGMENT_FIELD(GS), | |
360 | VMX_SEGMENT_FIELD(SS), | |
361 | VMX_SEGMENT_FIELD(TR), | |
362 | VMX_SEGMENT_FIELD(LDTR), | |
363 | }; | |
364 | ||
26bb0981 AK |
365 | static u64 host_efer; |
366 | ||
6de4f3ad AK |
367 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu); |
368 | ||
4d56c8a7 | 369 | /* |
8c06585d | 370 | * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it |
4d56c8a7 AK |
371 | * away by decrementing the array size. |
372 | */ | |
6aa8b732 | 373 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 374 | #ifdef CONFIG_X86_64 |
44ea2b17 | 375 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, |
6aa8b732 | 376 | #endif |
8c06585d | 377 | MSR_EFER, MSR_TSC_AUX, MSR_STAR, |
6aa8b732 | 378 | }; |
9d8f549d | 379 | #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index) |
6aa8b732 | 380 | |
31299944 | 381 | static inline bool is_page_fault(u32 intr_info) |
6aa8b732 AK |
382 | { |
383 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
384 | INTR_INFO_VALID_MASK)) == | |
8ab2d2e2 | 385 | (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK); |
6aa8b732 AK |
386 | } |
387 | ||
31299944 | 388 | static inline bool is_no_device(u32 intr_info) |
2ab455cc AL |
389 | { |
390 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
391 | INTR_INFO_VALID_MASK)) == | |
8ab2d2e2 | 392 | (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK); |
2ab455cc AL |
393 | } |
394 | ||
31299944 | 395 | static inline bool is_invalid_opcode(u32 intr_info) |
7aa81cc0 AL |
396 | { |
397 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
398 | INTR_INFO_VALID_MASK)) == | |
8ab2d2e2 | 399 | (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK); |
7aa81cc0 AL |
400 | } |
401 | ||
31299944 | 402 | static inline bool is_external_interrupt(u32 intr_info) |
6aa8b732 AK |
403 | { |
404 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
405 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
406 | } | |
407 | ||
31299944 | 408 | static inline bool is_machine_check(u32 intr_info) |
a0861c02 AK |
409 | { |
410 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
411 | INTR_INFO_VALID_MASK)) == | |
412 | (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK); | |
413 | } | |
414 | ||
31299944 | 415 | static inline bool cpu_has_vmx_msr_bitmap(void) |
25c5f225 | 416 | { |
04547156 | 417 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; |
25c5f225 SY |
418 | } |
419 | ||
31299944 | 420 | static inline bool cpu_has_vmx_tpr_shadow(void) |
6e5d865c | 421 | { |
04547156 | 422 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; |
6e5d865c YS |
423 | } |
424 | ||
31299944 | 425 | static inline bool vm_need_tpr_shadow(struct kvm *kvm) |
6e5d865c | 426 | { |
04547156 | 427 | return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)); |
6e5d865c YS |
428 | } |
429 | ||
31299944 | 430 | static inline bool cpu_has_secondary_exec_ctrls(void) |
f78e0e2e | 431 | { |
04547156 SY |
432 | return vmcs_config.cpu_based_exec_ctrl & |
433 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
f78e0e2e SY |
434 | } |
435 | ||
774ead3a | 436 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 437 | { |
04547156 SY |
438 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
439 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
440 | } | |
441 | ||
442 | static inline bool cpu_has_vmx_flexpriority(void) | |
443 | { | |
444 | return cpu_has_vmx_tpr_shadow() && | |
445 | cpu_has_vmx_virtualize_apic_accesses(); | |
f78e0e2e SY |
446 | } |
447 | ||
e799794e MT |
448 | static inline bool cpu_has_vmx_ept_execute_only(void) |
449 | { | |
31299944 | 450 | return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT; |
e799794e MT |
451 | } |
452 | ||
453 | static inline bool cpu_has_vmx_eptp_uncacheable(void) | |
454 | { | |
31299944 | 455 | return vmx_capability.ept & VMX_EPTP_UC_BIT; |
e799794e MT |
456 | } |
457 | ||
458 | static inline bool cpu_has_vmx_eptp_writeback(void) | |
459 | { | |
31299944 | 460 | return vmx_capability.ept & VMX_EPTP_WB_BIT; |
e799794e MT |
461 | } |
462 | ||
463 | static inline bool cpu_has_vmx_ept_2m_page(void) | |
464 | { | |
31299944 | 465 | return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT; |
e799794e MT |
466 | } |
467 | ||
878403b7 SY |
468 | static inline bool cpu_has_vmx_ept_1g_page(void) |
469 | { | |
31299944 | 470 | return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT; |
878403b7 SY |
471 | } |
472 | ||
4bc9b982 SY |
473 | static inline bool cpu_has_vmx_ept_4levels(void) |
474 | { | |
475 | return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT; | |
476 | } | |
477 | ||
31299944 | 478 | static inline bool cpu_has_vmx_invept_individual_addr(void) |
d56f546d | 479 | { |
31299944 | 480 | return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT; |
d56f546d SY |
481 | } |
482 | ||
31299944 | 483 | static inline bool cpu_has_vmx_invept_context(void) |
d56f546d | 484 | { |
31299944 | 485 | return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT; |
d56f546d SY |
486 | } |
487 | ||
31299944 | 488 | static inline bool cpu_has_vmx_invept_global(void) |
d56f546d | 489 | { |
31299944 | 490 | return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; |
d56f546d SY |
491 | } |
492 | ||
518c8aee GJ |
493 | static inline bool cpu_has_vmx_invvpid_single(void) |
494 | { | |
495 | return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT; | |
496 | } | |
497 | ||
b9d762fa GJ |
498 | static inline bool cpu_has_vmx_invvpid_global(void) |
499 | { | |
500 | return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; | |
501 | } | |
502 | ||
31299944 | 503 | static inline bool cpu_has_vmx_ept(void) |
d56f546d | 504 | { |
04547156 SY |
505 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
506 | SECONDARY_EXEC_ENABLE_EPT; | |
d56f546d SY |
507 | } |
508 | ||
31299944 | 509 | static inline bool cpu_has_vmx_unrestricted_guest(void) |
3a624e29 NK |
510 | { |
511 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
512 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
513 | } | |
514 | ||
31299944 | 515 | static inline bool cpu_has_vmx_ple(void) |
4b8d54f9 ZE |
516 | { |
517 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
518 | SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
519 | } | |
520 | ||
31299944 | 521 | static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm) |
f78e0e2e | 522 | { |
6d3e435e | 523 | return flexpriority_enabled && irqchip_in_kernel(kvm); |
f78e0e2e SY |
524 | } |
525 | ||
31299944 | 526 | static inline bool cpu_has_vmx_vpid(void) |
2384d2b3 | 527 | { |
04547156 SY |
528 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
529 | SECONDARY_EXEC_ENABLE_VPID; | |
2384d2b3 SY |
530 | } |
531 | ||
31299944 | 532 | static inline bool cpu_has_vmx_rdtscp(void) |
4e47c7a6 SY |
533 | { |
534 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
535 | SECONDARY_EXEC_RDTSCP; | |
536 | } | |
537 | ||
31299944 | 538 | static inline bool cpu_has_virtual_nmis(void) |
f08864b4 SY |
539 | { |
540 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; | |
541 | } | |
542 | ||
f5f48ee1 SY |
543 | static inline bool cpu_has_vmx_wbinvd_exit(void) |
544 | { | |
545 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
546 | SECONDARY_EXEC_WBINVD_EXITING; | |
547 | } | |
548 | ||
04547156 SY |
549 | static inline bool report_flexpriority(void) |
550 | { | |
551 | return flexpriority_enabled; | |
552 | } | |
553 | ||
8b9cf98c | 554 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
555 | { |
556 | int i; | |
557 | ||
a2fa3e9f | 558 | for (i = 0; i < vmx->nmsrs; ++i) |
26bb0981 | 559 | if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) |
a75beee6 ED |
560 | return i; |
561 | return -1; | |
562 | } | |
563 | ||
2384d2b3 SY |
564 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
565 | { | |
566 | struct { | |
567 | u64 vpid : 16; | |
568 | u64 rsvd : 48; | |
569 | u64 gva; | |
570 | } operand = { vpid, 0, gva }; | |
571 | ||
4ecac3fd | 572 | asm volatile (__ex(ASM_VMX_INVVPID) |
2384d2b3 SY |
573 | /* CF==1 or ZF==1 --> rc = -1 */ |
574 | "; ja 1f ; ud2 ; 1:" | |
575 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
576 | } | |
577 | ||
1439442c SY |
578 | static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
579 | { | |
580 | struct { | |
581 | u64 eptp, gpa; | |
582 | } operand = {eptp, gpa}; | |
583 | ||
4ecac3fd | 584 | asm volatile (__ex(ASM_VMX_INVEPT) |
1439442c SY |
585 | /* CF==1 or ZF==1 --> rc = -1 */ |
586 | "; ja 1f ; ud2 ; 1:\n" | |
587 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
588 | } | |
589 | ||
26bb0981 | 590 | static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
591 | { |
592 | int i; | |
593 | ||
8b9cf98c | 594 | i = __find_msr_index(vmx, msr); |
a75beee6 | 595 | if (i >= 0) |
a2fa3e9f | 596 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 597 | return NULL; |
7725f0ba AK |
598 | } |
599 | ||
6aa8b732 AK |
600 | static void vmcs_clear(struct vmcs *vmcs) |
601 | { | |
602 | u64 phys_addr = __pa(vmcs); | |
603 | u8 error; | |
604 | ||
4ecac3fd | 605 | asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
16d8f72f | 606 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
6aa8b732 AK |
607 | : "cc", "memory"); |
608 | if (error) | |
609 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
610 | vmcs, phys_addr); | |
611 | } | |
612 | ||
d462b819 NHE |
613 | static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) |
614 | { | |
615 | vmcs_clear(loaded_vmcs->vmcs); | |
616 | loaded_vmcs->cpu = -1; | |
617 | loaded_vmcs->launched = 0; | |
618 | } | |
619 | ||
7725b894 DX |
620 | static void vmcs_load(struct vmcs *vmcs) |
621 | { | |
622 | u64 phys_addr = __pa(vmcs); | |
623 | u8 error; | |
624 | ||
625 | asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" | |
16d8f72f | 626 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
7725b894 DX |
627 | : "cc", "memory"); |
628 | if (error) | |
629 | printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n", | |
630 | vmcs, phys_addr); | |
631 | } | |
632 | ||
d462b819 | 633 | static void __loaded_vmcs_clear(void *arg) |
6aa8b732 | 634 | { |
d462b819 | 635 | struct loaded_vmcs *loaded_vmcs = arg; |
d3b2c338 | 636 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 637 | |
d462b819 NHE |
638 | if (loaded_vmcs->cpu != cpu) |
639 | return; /* vcpu migration can race with cpu offline */ | |
640 | if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) | |
6aa8b732 | 641 | per_cpu(current_vmcs, cpu) = NULL; |
d462b819 NHE |
642 | list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); |
643 | loaded_vmcs_init(loaded_vmcs); | |
6aa8b732 AK |
644 | } |
645 | ||
d462b819 | 646 | static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) |
8d0be2b3 | 647 | { |
d462b819 NHE |
648 | if (loaded_vmcs->cpu != -1) |
649 | smp_call_function_single( | |
650 | loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1); | |
8d0be2b3 AK |
651 | } |
652 | ||
1760dd49 | 653 | static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx) |
2384d2b3 SY |
654 | { |
655 | if (vmx->vpid == 0) | |
656 | return; | |
657 | ||
518c8aee GJ |
658 | if (cpu_has_vmx_invvpid_single()) |
659 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0); | |
2384d2b3 SY |
660 | } |
661 | ||
b9d762fa GJ |
662 | static inline void vpid_sync_vcpu_global(void) |
663 | { | |
664 | if (cpu_has_vmx_invvpid_global()) | |
665 | __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0); | |
666 | } | |
667 | ||
668 | static inline void vpid_sync_context(struct vcpu_vmx *vmx) | |
669 | { | |
670 | if (cpu_has_vmx_invvpid_single()) | |
1760dd49 | 671 | vpid_sync_vcpu_single(vmx); |
b9d762fa GJ |
672 | else |
673 | vpid_sync_vcpu_global(); | |
674 | } | |
675 | ||
1439442c SY |
676 | static inline void ept_sync_global(void) |
677 | { | |
678 | if (cpu_has_vmx_invept_global()) | |
679 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); | |
680 | } | |
681 | ||
682 | static inline void ept_sync_context(u64 eptp) | |
683 | { | |
089d034e | 684 | if (enable_ept) { |
1439442c SY |
685 | if (cpu_has_vmx_invept_context()) |
686 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
687 | else | |
688 | ept_sync_global(); | |
689 | } | |
690 | } | |
691 | ||
692 | static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa) | |
693 | { | |
089d034e | 694 | if (enable_ept) { |
1439442c SY |
695 | if (cpu_has_vmx_invept_individual_addr()) |
696 | __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR, | |
697 | eptp, gpa); | |
698 | else | |
699 | ept_sync_context(eptp); | |
700 | } | |
701 | } | |
702 | ||
96304217 | 703 | static __always_inline unsigned long vmcs_readl(unsigned long field) |
6aa8b732 | 704 | { |
5e520e62 | 705 | unsigned long value; |
6aa8b732 | 706 | |
5e520e62 AK |
707 | asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0") |
708 | : "=a"(value) : "d"(field) : "cc"); | |
6aa8b732 AK |
709 | return value; |
710 | } | |
711 | ||
96304217 | 712 | static __always_inline u16 vmcs_read16(unsigned long field) |
6aa8b732 AK |
713 | { |
714 | return vmcs_readl(field); | |
715 | } | |
716 | ||
96304217 | 717 | static __always_inline u32 vmcs_read32(unsigned long field) |
6aa8b732 AK |
718 | { |
719 | return vmcs_readl(field); | |
720 | } | |
721 | ||
96304217 | 722 | static __always_inline u64 vmcs_read64(unsigned long field) |
6aa8b732 | 723 | { |
05b3e0c2 | 724 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
725 | return vmcs_readl(field); |
726 | #else | |
727 | return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32); | |
728 | #endif | |
729 | } | |
730 | ||
e52de1b8 AK |
731 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
732 | { | |
733 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
734 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
735 | dump_stack(); | |
736 | } | |
737 | ||
6aa8b732 AK |
738 | static void vmcs_writel(unsigned long field, unsigned long value) |
739 | { | |
740 | u8 error; | |
741 | ||
4ecac3fd | 742 | asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
d77c26fc | 743 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
744 | if (unlikely(error)) |
745 | vmwrite_error(field, value); | |
6aa8b732 AK |
746 | } |
747 | ||
748 | static void vmcs_write16(unsigned long field, u16 value) | |
749 | { | |
750 | vmcs_writel(field, value); | |
751 | } | |
752 | ||
753 | static void vmcs_write32(unsigned long field, u32 value) | |
754 | { | |
755 | vmcs_writel(field, value); | |
756 | } | |
757 | ||
758 | static void vmcs_write64(unsigned long field, u64 value) | |
759 | { | |
6aa8b732 | 760 | vmcs_writel(field, value); |
7682f2d0 | 761 | #ifndef CONFIG_X86_64 |
6aa8b732 AK |
762 | asm volatile (""); |
763 | vmcs_writel(field+1, value >> 32); | |
764 | #endif | |
765 | } | |
766 | ||
2ab455cc AL |
767 | static void vmcs_clear_bits(unsigned long field, u32 mask) |
768 | { | |
769 | vmcs_writel(field, vmcs_readl(field) & ~mask); | |
770 | } | |
771 | ||
772 | static void vmcs_set_bits(unsigned long field, u32 mask) | |
773 | { | |
774 | vmcs_writel(field, vmcs_readl(field) | mask); | |
775 | } | |
776 | ||
2fb92db1 AK |
777 | static void vmx_segment_cache_clear(struct vcpu_vmx *vmx) |
778 | { | |
779 | vmx->segment_cache.bitmask = 0; | |
780 | } | |
781 | ||
782 | static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, | |
783 | unsigned field) | |
784 | { | |
785 | bool ret; | |
786 | u32 mask = 1 << (seg * SEG_FIELD_NR + field); | |
787 | ||
788 | if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) { | |
789 | vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS); | |
790 | vmx->segment_cache.bitmask = 0; | |
791 | } | |
792 | ret = vmx->segment_cache.bitmask & mask; | |
793 | vmx->segment_cache.bitmask |= mask; | |
794 | return ret; | |
795 | } | |
796 | ||
797 | static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) | |
798 | { | |
799 | u16 *p = &vmx->segment_cache.seg[seg].selector; | |
800 | ||
801 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) | |
802 | *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); | |
803 | return *p; | |
804 | } | |
805 | ||
806 | static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) | |
807 | { | |
808 | ulong *p = &vmx->segment_cache.seg[seg].base; | |
809 | ||
810 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) | |
811 | *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); | |
812 | return *p; | |
813 | } | |
814 | ||
815 | static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) | |
816 | { | |
817 | u32 *p = &vmx->segment_cache.seg[seg].limit; | |
818 | ||
819 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) | |
820 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); | |
821 | return *p; | |
822 | } | |
823 | ||
824 | static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) | |
825 | { | |
826 | u32 *p = &vmx->segment_cache.seg[seg].ar; | |
827 | ||
828 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) | |
829 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); | |
830 | return *p; | |
831 | } | |
832 | ||
abd3f2d6 AK |
833 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
834 | { | |
835 | u32 eb; | |
836 | ||
fd7373cc JK |
837 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | |
838 | (1u << NM_VECTOR) | (1u << DB_VECTOR); | |
839 | if ((vcpu->guest_debug & | |
840 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == | |
841 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) | |
842 | eb |= 1u << BP_VECTOR; | |
7ffd92c5 | 843 | if (to_vmx(vcpu)->rmode.vm86_active) |
abd3f2d6 | 844 | eb = ~0; |
089d034e | 845 | if (enable_ept) |
1439442c | 846 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ |
02daab21 AK |
847 | if (vcpu->fpu_active) |
848 | eb &= ~(1u << NM_VECTOR); | |
abd3f2d6 AK |
849 | vmcs_write32(EXCEPTION_BITMAP, eb); |
850 | } | |
851 | ||
61d2ef2c AK |
852 | static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) |
853 | { | |
854 | unsigned i; | |
855 | struct msr_autoload *m = &vmx->msr_autoload; | |
856 | ||
110312c8 AK |
857 | if (msr == MSR_EFER && cpu_has_load_ia32_efer) { |
858 | vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER); | |
859 | vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER); | |
860 | return; | |
861 | } | |
862 | ||
61d2ef2c AK |
863 | for (i = 0; i < m->nr; ++i) |
864 | if (m->guest[i].index == msr) | |
865 | break; | |
866 | ||
867 | if (i == m->nr) | |
868 | return; | |
869 | --m->nr; | |
870 | m->guest[i] = m->guest[m->nr]; | |
871 | m->host[i] = m->host[m->nr]; | |
872 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
873 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
874 | } | |
875 | ||
876 | static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, | |
877 | u64 guest_val, u64 host_val) | |
878 | { | |
879 | unsigned i; | |
880 | struct msr_autoload *m = &vmx->msr_autoload; | |
881 | ||
110312c8 AK |
882 | if (msr == MSR_EFER && cpu_has_load_ia32_efer) { |
883 | vmcs_write64(GUEST_IA32_EFER, guest_val); | |
884 | vmcs_write64(HOST_IA32_EFER, host_val); | |
885 | vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER); | |
886 | vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER); | |
887 | return; | |
888 | } | |
889 | ||
61d2ef2c AK |
890 | for (i = 0; i < m->nr; ++i) |
891 | if (m->guest[i].index == msr) | |
892 | break; | |
893 | ||
894 | if (i == m->nr) { | |
895 | ++m->nr; | |
896 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
897 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
898 | } | |
899 | ||
900 | m->guest[i].index = msr; | |
901 | m->guest[i].value = guest_val; | |
902 | m->host[i].index = msr; | |
903 | m->host[i].value = host_val; | |
904 | } | |
905 | ||
33ed6329 AK |
906 | static void reload_tss(void) |
907 | { | |
33ed6329 AK |
908 | /* |
909 | * VT restores TR but not its size. Useless. | |
910 | */ | |
d359192f | 911 | struct desc_ptr *gdt = &__get_cpu_var(host_gdt); |
a5f61300 | 912 | struct desc_struct *descs; |
33ed6329 | 913 | |
d359192f | 914 | descs = (void *)gdt->address; |
33ed6329 AK |
915 | descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ |
916 | load_TR_desc(); | |
33ed6329 AK |
917 | } |
918 | ||
92c0d900 | 919 | static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) |
2cc51560 | 920 | { |
3a34a881 | 921 | u64 guest_efer; |
51c6cf66 AK |
922 | u64 ignore_bits; |
923 | ||
f6801dff | 924 | guest_efer = vmx->vcpu.arch.efer; |
3a34a881 | 925 | |
51c6cf66 AK |
926 | /* |
927 | * NX is emulated; LMA and LME handled by hardware; SCE meaninless | |
928 | * outside long mode | |
929 | */ | |
930 | ignore_bits = EFER_NX | EFER_SCE; | |
931 | #ifdef CONFIG_X86_64 | |
932 | ignore_bits |= EFER_LMA | EFER_LME; | |
933 | /* SCE is meaningful only in long mode on Intel */ | |
934 | if (guest_efer & EFER_LMA) | |
935 | ignore_bits &= ~(u64)EFER_SCE; | |
936 | #endif | |
51c6cf66 AK |
937 | guest_efer &= ~ignore_bits; |
938 | guest_efer |= host_efer & ignore_bits; | |
26bb0981 | 939 | vmx->guest_msrs[efer_offset].data = guest_efer; |
d5696725 | 940 | vmx->guest_msrs[efer_offset].mask = ~ignore_bits; |
84ad33ef AK |
941 | |
942 | clear_atomic_switch_msr(vmx, MSR_EFER); | |
943 | /* On ept, can't emulate nx, and must switch nx atomically */ | |
944 | if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) { | |
945 | guest_efer = vmx->vcpu.arch.efer; | |
946 | if (!(guest_efer & EFER_LMA)) | |
947 | guest_efer &= ~EFER_LME; | |
948 | add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer); | |
949 | return false; | |
950 | } | |
951 | ||
26bb0981 | 952 | return true; |
51c6cf66 AK |
953 | } |
954 | ||
2d49ec72 GN |
955 | static unsigned long segment_base(u16 selector) |
956 | { | |
d359192f | 957 | struct desc_ptr *gdt = &__get_cpu_var(host_gdt); |
2d49ec72 GN |
958 | struct desc_struct *d; |
959 | unsigned long table_base; | |
960 | unsigned long v; | |
961 | ||
962 | if (!(selector & ~3)) | |
963 | return 0; | |
964 | ||
d359192f | 965 | table_base = gdt->address; |
2d49ec72 GN |
966 | |
967 | if (selector & 4) { /* from ldt */ | |
968 | u16 ldt_selector = kvm_read_ldt(); | |
969 | ||
970 | if (!(ldt_selector & ~3)) | |
971 | return 0; | |
972 | ||
973 | table_base = segment_base(ldt_selector); | |
974 | } | |
975 | d = (struct desc_struct *)(table_base + (selector & ~7)); | |
976 | v = get_desc_base(d); | |
977 | #ifdef CONFIG_X86_64 | |
978 | if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11)) | |
979 | v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32; | |
980 | #endif | |
981 | return v; | |
982 | } | |
983 | ||
984 | static inline unsigned long kvm_read_tr_base(void) | |
985 | { | |
986 | u16 tr; | |
987 | asm("str %0" : "=g"(tr)); | |
988 | return segment_base(tr); | |
989 | } | |
990 | ||
04d2cc77 | 991 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 992 | { |
04d2cc77 | 993 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 994 | int i; |
04d2cc77 | 995 | |
a2fa3e9f | 996 | if (vmx->host_state.loaded) |
33ed6329 AK |
997 | return; |
998 | ||
a2fa3e9f | 999 | vmx->host_state.loaded = 1; |
33ed6329 AK |
1000 | /* |
1001 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
1002 | * allow segment selectors with cpl > 0 or ti == 1. | |
1003 | */ | |
d6e88aec | 1004 | vmx->host_state.ldt_sel = kvm_read_ldt(); |
152d3f2f | 1005 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
9581d442 | 1006 | savesegment(fs, vmx->host_state.fs_sel); |
152d3f2f | 1007 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 1008 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
1009 | vmx->host_state.fs_reload_needed = 0; |
1010 | } else { | |
33ed6329 | 1011 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 1012 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 1013 | } |
9581d442 | 1014 | savesegment(gs, vmx->host_state.gs_sel); |
a2fa3e9f GH |
1015 | if (!(vmx->host_state.gs_sel & 7)) |
1016 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
1017 | else { |
1018 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 1019 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
1020 | } |
1021 | ||
1022 | #ifdef CONFIG_X86_64 | |
1023 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
1024 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
1025 | #else | |
a2fa3e9f GH |
1026 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
1027 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 1028 | #endif |
707c0874 AK |
1029 | |
1030 | #ifdef CONFIG_X86_64 | |
c8770e7b AK |
1031 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
1032 | if (is_long_mode(&vmx->vcpu)) | |
44ea2b17 | 1033 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); |
707c0874 | 1034 | #endif |
26bb0981 AK |
1035 | for (i = 0; i < vmx->save_nmsrs; ++i) |
1036 | kvm_set_shared_msr(vmx->guest_msrs[i].index, | |
d5696725 AK |
1037 | vmx->guest_msrs[i].data, |
1038 | vmx->guest_msrs[i].mask); | |
33ed6329 AK |
1039 | } |
1040 | ||
a9b21b62 | 1041 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 1042 | { |
a2fa3e9f | 1043 | if (!vmx->host_state.loaded) |
33ed6329 AK |
1044 | return; |
1045 | ||
e1beb1d3 | 1046 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 1047 | vmx->host_state.loaded = 0; |
c8770e7b AK |
1048 | #ifdef CONFIG_X86_64 |
1049 | if (is_long_mode(&vmx->vcpu)) | |
1050 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); | |
1051 | #endif | |
152d3f2f | 1052 | if (vmx->host_state.gs_ldt_reload_needed) { |
d6e88aec | 1053 | kvm_load_ldt(vmx->host_state.ldt_sel); |
33ed6329 | 1054 | #ifdef CONFIG_X86_64 |
9581d442 | 1055 | load_gs_index(vmx->host_state.gs_sel); |
9581d442 AK |
1056 | #else |
1057 | loadsegment(gs, vmx->host_state.gs_sel); | |
33ed6329 | 1058 | #endif |
33ed6329 | 1059 | } |
0a77fe4c AK |
1060 | if (vmx->host_state.fs_reload_needed) |
1061 | loadsegment(fs, vmx->host_state.fs_sel); | |
152d3f2f | 1062 | reload_tss(); |
44ea2b17 | 1063 | #ifdef CONFIG_X86_64 |
c8770e7b | 1064 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
44ea2b17 | 1065 | #endif |
1c11e713 AK |
1066 | if (current_thread_info()->status & TS_USEDFPU) |
1067 | clts(); | |
3444d7da | 1068 | load_gdt(&__get_cpu_var(host_gdt)); |
33ed6329 AK |
1069 | } |
1070 | ||
a9b21b62 AK |
1071 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
1072 | { | |
1073 | preempt_disable(); | |
1074 | __vmx_load_host_state(vmx); | |
1075 | preempt_enable(); | |
1076 | } | |
1077 | ||
6aa8b732 AK |
1078 | /* |
1079 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
1080 | * vcpu mutex is already taken. | |
1081 | */ | |
15ad7146 | 1082 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 1083 | { |
a2fa3e9f | 1084 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4610c9cc | 1085 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); |
6aa8b732 | 1086 | |
4610c9cc DX |
1087 | if (!vmm_exclusive) |
1088 | kvm_cpu_vmxon(phys_addr); | |
d462b819 NHE |
1089 | else if (vmx->loaded_vmcs->cpu != cpu) |
1090 | loaded_vmcs_clear(vmx->loaded_vmcs); | |
6aa8b732 | 1091 | |
d462b819 NHE |
1092 | if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { |
1093 | per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; | |
1094 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
6aa8b732 AK |
1095 | } |
1096 | ||
d462b819 | 1097 | if (vmx->loaded_vmcs->cpu != cpu) { |
d359192f | 1098 | struct desc_ptr *gdt = &__get_cpu_var(host_gdt); |
6aa8b732 AK |
1099 | unsigned long sysenter_esp; |
1100 | ||
a8eeb04a | 1101 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
92fe13be | 1102 | local_irq_disable(); |
d462b819 NHE |
1103 | list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, |
1104 | &per_cpu(loaded_vmcss_on_cpu, cpu)); | |
92fe13be DX |
1105 | local_irq_enable(); |
1106 | ||
6aa8b732 AK |
1107 | /* |
1108 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
1109 | * processors. | |
1110 | */ | |
d6e88aec | 1111 | vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */ |
d359192f | 1112 | vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */ |
6aa8b732 AK |
1113 | |
1114 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
1115 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
d462b819 | 1116 | vmx->loaded_vmcs->cpu = cpu; |
6aa8b732 | 1117 | } |
6aa8b732 AK |
1118 | } |
1119 | ||
1120 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
1121 | { | |
a9b21b62 | 1122 | __vmx_load_host_state(to_vmx(vcpu)); |
4610c9cc | 1123 | if (!vmm_exclusive) { |
d462b819 NHE |
1124 | __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs); |
1125 | vcpu->cpu = -1; | |
4610c9cc DX |
1126 | kvm_cpu_vmxoff(); |
1127 | } | |
6aa8b732 AK |
1128 | } |
1129 | ||
5fd86fcf AK |
1130 | static void vmx_fpu_activate(struct kvm_vcpu *vcpu) |
1131 | { | |
81231c69 AK |
1132 | ulong cr0; |
1133 | ||
5fd86fcf AK |
1134 | if (vcpu->fpu_active) |
1135 | return; | |
1136 | vcpu->fpu_active = 1; | |
81231c69 AK |
1137 | cr0 = vmcs_readl(GUEST_CR0); |
1138 | cr0 &= ~(X86_CR0_TS | X86_CR0_MP); | |
1139 | cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP); | |
1140 | vmcs_writel(GUEST_CR0, cr0); | |
5fd86fcf | 1141 | update_exception_bitmap(vcpu); |
edcafe3c AK |
1142 | vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS; |
1143 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
5fd86fcf AK |
1144 | } |
1145 | ||
edcafe3c AK |
1146 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); |
1147 | ||
5fd86fcf AK |
1148 | static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu) |
1149 | { | |
edcafe3c | 1150 | vmx_decache_cr0_guest_bits(vcpu); |
81231c69 | 1151 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP); |
5fd86fcf | 1152 | update_exception_bitmap(vcpu); |
edcafe3c AK |
1153 | vcpu->arch.cr0_guest_owned_bits = 0; |
1154 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
1155 | vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0); | |
5fd86fcf AK |
1156 | } |
1157 | ||
6aa8b732 AK |
1158 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
1159 | { | |
78ac8b47 | 1160 | unsigned long rflags, save_rflags; |
345dcaa8 | 1161 | |
6de12732 AK |
1162 | if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) { |
1163 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); | |
1164 | rflags = vmcs_readl(GUEST_RFLAGS); | |
1165 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
1166 | rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; | |
1167 | save_rflags = to_vmx(vcpu)->rmode.save_rflags; | |
1168 | rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
1169 | } | |
1170 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 | 1171 | } |
6de12732 | 1172 | return to_vmx(vcpu)->rflags; |
6aa8b732 AK |
1173 | } |
1174 | ||
1175 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
1176 | { | |
6de12732 | 1177 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); |
69c73028 | 1178 | __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail); |
6de12732 | 1179 | to_vmx(vcpu)->rflags = rflags; |
78ac8b47 AK |
1180 | if (to_vmx(vcpu)->rmode.vm86_active) { |
1181 | to_vmx(vcpu)->rmode.save_rflags = rflags; | |
053de044 | 1182 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
78ac8b47 | 1183 | } |
6aa8b732 AK |
1184 | vmcs_writel(GUEST_RFLAGS, rflags); |
1185 | } | |
1186 | ||
2809f5d2 GC |
1187 | static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
1188 | { | |
1189 | u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
1190 | int ret = 0; | |
1191 | ||
1192 | if (interruptibility & GUEST_INTR_STATE_STI) | |
48005f64 | 1193 | ret |= KVM_X86_SHADOW_INT_STI; |
2809f5d2 | 1194 | if (interruptibility & GUEST_INTR_STATE_MOV_SS) |
48005f64 | 1195 | ret |= KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 GC |
1196 | |
1197 | return ret & mask; | |
1198 | } | |
1199 | ||
1200 | static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
1201 | { | |
1202 | u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
1203 | u32 interruptibility = interruptibility_old; | |
1204 | ||
1205 | interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); | |
1206 | ||
48005f64 | 1207 | if (mask & KVM_X86_SHADOW_INT_MOV_SS) |
2809f5d2 | 1208 | interruptibility |= GUEST_INTR_STATE_MOV_SS; |
48005f64 | 1209 | else if (mask & KVM_X86_SHADOW_INT_STI) |
2809f5d2 GC |
1210 | interruptibility |= GUEST_INTR_STATE_STI; |
1211 | ||
1212 | if ((interruptibility != interruptibility_old)) | |
1213 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); | |
1214 | } | |
1215 | ||
6aa8b732 AK |
1216 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
1217 | { | |
1218 | unsigned long rip; | |
6aa8b732 | 1219 | |
5fdbf976 | 1220 | rip = kvm_rip_read(vcpu); |
6aa8b732 | 1221 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
5fdbf976 | 1222 | kvm_rip_write(vcpu, rip); |
6aa8b732 | 1223 | |
2809f5d2 GC |
1224 | /* skipping an emulated instruction also counts */ |
1225 | vmx_set_interrupt_shadow(vcpu, 0); | |
6aa8b732 AK |
1226 | } |
1227 | ||
443381a8 AL |
1228 | static void vmx_clear_hlt(struct kvm_vcpu *vcpu) |
1229 | { | |
1230 | /* Ensure that we clear the HLT state in the VMCS. We don't need to | |
1231 | * explicitly skip the instruction because if the HLT state is set, then | |
1232 | * the instruction is already executing and RIP has already been | |
1233 | * advanced. */ | |
1234 | if (!yield_on_hlt && | |
1235 | vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT) | |
1236 | vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); | |
1237 | } | |
1238 | ||
298101da | 1239 | static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
1240 | bool has_error_code, u32 error_code, |
1241 | bool reinject) | |
298101da | 1242 | { |
77ab6db0 | 1243 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8ab2d2e2 | 1244 | u32 intr_info = nr | INTR_INFO_VALID_MASK; |
77ab6db0 | 1245 | |
8ab2d2e2 | 1246 | if (has_error_code) { |
77ab6db0 | 1247 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); |
8ab2d2e2 JK |
1248 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; |
1249 | } | |
77ab6db0 | 1250 | |
7ffd92c5 | 1251 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
1252 | int inc_eip = 0; |
1253 | if (kvm_exception_is_soft(nr)) | |
1254 | inc_eip = vcpu->arch.event_exit_inst_len; | |
1255 | if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE) | |
a92601bb | 1256 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
77ab6db0 JK |
1257 | return; |
1258 | } | |
1259 | ||
66fd3f7f GN |
1260 | if (kvm_exception_is_soft(nr)) { |
1261 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
1262 | vmx->vcpu.arch.event_exit_inst_len); | |
8ab2d2e2 JK |
1263 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; |
1264 | } else | |
1265 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
1266 | ||
1267 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | |
443381a8 | 1268 | vmx_clear_hlt(vcpu); |
298101da AK |
1269 | } |
1270 | ||
4e47c7a6 SY |
1271 | static bool vmx_rdtscp_supported(void) |
1272 | { | |
1273 | return cpu_has_vmx_rdtscp(); | |
1274 | } | |
1275 | ||
a75beee6 ED |
1276 | /* |
1277 | * Swap MSR entry in host/guest MSR entry array. | |
1278 | */ | |
8b9cf98c | 1279 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 1280 | { |
26bb0981 | 1281 | struct shared_msr_entry tmp; |
a2fa3e9f GH |
1282 | |
1283 | tmp = vmx->guest_msrs[to]; | |
1284 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
1285 | vmx->guest_msrs[from] = tmp; | |
a75beee6 ED |
1286 | } |
1287 | ||
e38aea3e AK |
1288 | /* |
1289 | * Set up the vmcs to automatically save and restore system | |
1290 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
1291 | * mode, as fiddling with msrs is very expensive. | |
1292 | */ | |
8b9cf98c | 1293 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 1294 | { |
26bb0981 | 1295 | int save_nmsrs, index; |
5897297b | 1296 | unsigned long *msr_bitmap; |
e38aea3e | 1297 | |
33f9c505 | 1298 | vmx_load_host_state(vmx); |
a75beee6 ED |
1299 | save_nmsrs = 0; |
1300 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 1301 | if (is_long_mode(&vmx->vcpu)) { |
8b9cf98c | 1302 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 1303 | if (index >= 0) |
8b9cf98c RR |
1304 | move_msr_up(vmx, index, save_nmsrs++); |
1305 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 1306 | if (index >= 0) |
8b9cf98c RR |
1307 | move_msr_up(vmx, index, save_nmsrs++); |
1308 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 1309 | if (index >= 0) |
8b9cf98c | 1310 | move_msr_up(vmx, index, save_nmsrs++); |
4e47c7a6 SY |
1311 | index = __find_msr_index(vmx, MSR_TSC_AUX); |
1312 | if (index >= 0 && vmx->rdtscp_enabled) | |
1313 | move_msr_up(vmx, index, save_nmsrs++); | |
a75beee6 | 1314 | /* |
8c06585d | 1315 | * MSR_STAR is only needed on long mode guests, and only |
a75beee6 ED |
1316 | * if efer.sce is enabled. |
1317 | */ | |
8c06585d | 1318 | index = __find_msr_index(vmx, MSR_STAR); |
f6801dff | 1319 | if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE)) |
8b9cf98c | 1320 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
1321 | } |
1322 | #endif | |
92c0d900 AK |
1323 | index = __find_msr_index(vmx, MSR_EFER); |
1324 | if (index >= 0 && update_transition_efer(vmx, index)) | |
26bb0981 | 1325 | move_msr_up(vmx, index, save_nmsrs++); |
e38aea3e | 1326 | |
26bb0981 | 1327 | vmx->save_nmsrs = save_nmsrs; |
5897297b AK |
1328 | |
1329 | if (cpu_has_vmx_msr_bitmap()) { | |
1330 | if (is_long_mode(&vmx->vcpu)) | |
1331 | msr_bitmap = vmx_msr_bitmap_longmode; | |
1332 | else | |
1333 | msr_bitmap = vmx_msr_bitmap_legacy; | |
1334 | ||
1335 | vmcs_write64(MSR_BITMAP, __pa(msr_bitmap)); | |
1336 | } | |
e38aea3e AK |
1337 | } |
1338 | ||
6aa8b732 AK |
1339 | /* |
1340 | * reads and returns guest's timestamp counter "register" | |
1341 | * guest_tsc = host_tsc + tsc_offset -- 21.3 | |
1342 | */ | |
1343 | static u64 guest_read_tsc(void) | |
1344 | { | |
1345 | u64 host_tsc, tsc_offset; | |
1346 | ||
1347 | rdtscll(host_tsc); | |
1348 | tsc_offset = vmcs_read64(TSC_OFFSET); | |
1349 | return host_tsc + tsc_offset; | |
1350 | } | |
1351 | ||
4051b188 JR |
1352 | /* |
1353 | * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ | |
1354 | * ioctl. In this case the call-back should update internal vmx state to make | |
1355 | * the changes effective. | |
1356 | */ | |
1357 | static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) | |
1358 | { | |
1359 | /* Nothing to do here */ | |
1360 | } | |
1361 | ||
6aa8b732 | 1362 | /* |
99e3e30a | 1363 | * writes 'offset' into guest's timestamp counter offset register |
6aa8b732 | 1364 | */ |
99e3e30a | 1365 | static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
6aa8b732 | 1366 | { |
f4e1b3c8 | 1367 | vmcs_write64(TSC_OFFSET, offset); |
6aa8b732 AK |
1368 | } |
1369 | ||
e48672fa ZA |
1370 | static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment) |
1371 | { | |
1372 | u64 offset = vmcs_read64(TSC_OFFSET); | |
1373 | vmcs_write64(TSC_OFFSET, offset + adjustment); | |
1374 | } | |
1375 | ||
857e4099 JR |
1376 | static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
1377 | { | |
1378 | return target_tsc - native_read_tsc(); | |
1379 | } | |
1380 | ||
801d3424 NHE |
1381 | static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu) |
1382 | { | |
1383 | struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0); | |
1384 | return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31))); | |
1385 | } | |
1386 | ||
1387 | /* | |
1388 | * nested_vmx_allowed() checks whether a guest should be allowed to use VMX | |
1389 | * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for | |
1390 | * all guests if the "nested" module option is off, and can also be disabled | |
1391 | * for a single guest by disabling its VMX cpuid bit. | |
1392 | */ | |
1393 | static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu) | |
1394 | { | |
1395 | return nested && guest_cpuid_has_vmx(vcpu); | |
1396 | } | |
1397 | ||
b87a51ae NHE |
1398 | /* |
1399 | * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be | |
1400 | * returned for the various VMX controls MSRs when nested VMX is enabled. | |
1401 | * The same values should also be used to verify that vmcs12 control fields are | |
1402 | * valid during nested entry from L1 to L2. | |
1403 | * Each of these control msrs has a low and high 32-bit half: A low bit is on | |
1404 | * if the corresponding bit in the (32-bit) control field *must* be on, and a | |
1405 | * bit in the high half is on if the corresponding bit in the control field | |
1406 | * may be on. See also vmx_control_verify(). | |
1407 | * TODO: allow these variables to be modified (downgraded) by module options | |
1408 | * or other means. | |
1409 | */ | |
1410 | static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high; | |
1411 | static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high; | |
1412 | static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high; | |
1413 | static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high; | |
1414 | static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high; | |
1415 | static __init void nested_vmx_setup_ctls_msrs(void) | |
1416 | { | |
1417 | /* | |
1418 | * Note that as a general rule, the high half of the MSRs (bits in | |
1419 | * the control fields which may be 1) should be initialized by the | |
1420 | * intersection of the underlying hardware's MSR (i.e., features which | |
1421 | * can be supported) and the list of features we want to expose - | |
1422 | * because they are known to be properly supported in our code. | |
1423 | * Also, usually, the low half of the MSRs (bits which must be 1) can | |
1424 | * be set to 0, meaning that L1 may turn off any of these bits. The | |
1425 | * reason is that if one of these bits is necessary, it will appear | |
1426 | * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control | |
1427 | * fields of vmcs01 and vmcs02, will turn these bits off - and | |
1428 | * nested_vmx_exit_handled() will not pass related exits to L1. | |
1429 | * These rules have exceptions below. | |
1430 | */ | |
1431 | ||
1432 | /* pin-based controls */ | |
1433 | /* | |
1434 | * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is | |
1435 | * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR. | |
1436 | */ | |
1437 | nested_vmx_pinbased_ctls_low = 0x16 ; | |
1438 | nested_vmx_pinbased_ctls_high = 0x16 | | |
1439 | PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING | | |
1440 | PIN_BASED_VIRTUAL_NMIS; | |
1441 | ||
1442 | /* exit controls */ | |
1443 | nested_vmx_exit_ctls_low = 0; | |
1444 | #ifdef CONFIG_X86_64 | |
1445 | nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
1446 | #else | |
1447 | nested_vmx_exit_ctls_high = 0; | |
1448 | #endif | |
1449 | ||
1450 | /* entry controls */ | |
1451 | rdmsr(MSR_IA32_VMX_ENTRY_CTLS, | |
1452 | nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high); | |
1453 | nested_vmx_entry_ctls_low = 0; | |
1454 | nested_vmx_entry_ctls_high &= | |
1455 | VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE; | |
1456 | ||
1457 | /* cpu-based controls */ | |
1458 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, | |
1459 | nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high); | |
1460 | nested_vmx_procbased_ctls_low = 0; | |
1461 | nested_vmx_procbased_ctls_high &= | |
1462 | CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING | | |
1463 | CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING | | |
1464 | CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING | | |
1465 | CPU_BASED_CR3_STORE_EXITING | | |
1466 | #ifdef CONFIG_X86_64 | |
1467 | CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING | | |
1468 | #endif | |
1469 | CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING | | |
1470 | CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING | | |
1471 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
1472 | /* | |
1473 | * We can allow some features even when not supported by the | |
1474 | * hardware. For example, L1 can specify an MSR bitmap - and we | |
1475 | * can use it to avoid exits to L1 - even when L0 runs L2 | |
1476 | * without MSR bitmaps. | |
1477 | */ | |
1478 | nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS; | |
1479 | ||
1480 | /* secondary cpu-based controls */ | |
1481 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, | |
1482 | nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high); | |
1483 | nested_vmx_secondary_ctls_low = 0; | |
1484 | nested_vmx_secondary_ctls_high &= | |
1485 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
1486 | } | |
1487 | ||
1488 | static inline bool vmx_control_verify(u32 control, u32 low, u32 high) | |
1489 | { | |
1490 | /* | |
1491 | * Bits 0 in high must be 0, and bits 1 in low must be 1. | |
1492 | */ | |
1493 | return ((control & high) | low) == control; | |
1494 | } | |
1495 | ||
1496 | static inline u64 vmx_control_msr(u32 low, u32 high) | |
1497 | { | |
1498 | return low | ((u64)high << 32); | |
1499 | } | |
1500 | ||
1501 | /* | |
1502 | * If we allow our guest to use VMX instructions (i.e., nested VMX), we should | |
1503 | * also let it use VMX-specific MSRs. | |
1504 | * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a | |
1505 | * VMX-specific MSR, or 0 when we haven't (and the caller should handle it | |
1506 | * like all other MSRs). | |
1507 | */ | |
1508 | static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
1509 | { | |
1510 | if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC && | |
1511 | msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) { | |
1512 | /* | |
1513 | * According to the spec, processors which do not support VMX | |
1514 | * should throw a #GP(0) when VMX capability MSRs are read. | |
1515 | */ | |
1516 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
1517 | return 1; | |
1518 | } | |
1519 | ||
1520 | switch (msr_index) { | |
1521 | case MSR_IA32_FEATURE_CONTROL: | |
1522 | *pdata = 0; | |
1523 | break; | |
1524 | case MSR_IA32_VMX_BASIC: | |
1525 | /* | |
1526 | * This MSR reports some information about VMX support. We | |
1527 | * should return information about the VMX we emulate for the | |
1528 | * guest, and the VMCS structure we give it - not about the | |
1529 | * VMX support of the underlying hardware. | |
1530 | */ | |
1531 | *pdata = VMCS12_REVISION | | |
1532 | ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) | | |
1533 | (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT); | |
1534 | break; | |
1535 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
1536 | case MSR_IA32_VMX_PINBASED_CTLS: | |
1537 | *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low, | |
1538 | nested_vmx_pinbased_ctls_high); | |
1539 | break; | |
1540 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
1541 | case MSR_IA32_VMX_PROCBASED_CTLS: | |
1542 | *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low, | |
1543 | nested_vmx_procbased_ctls_high); | |
1544 | break; | |
1545 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
1546 | case MSR_IA32_VMX_EXIT_CTLS: | |
1547 | *pdata = vmx_control_msr(nested_vmx_exit_ctls_low, | |
1548 | nested_vmx_exit_ctls_high); | |
1549 | break; | |
1550 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
1551 | case MSR_IA32_VMX_ENTRY_CTLS: | |
1552 | *pdata = vmx_control_msr(nested_vmx_entry_ctls_low, | |
1553 | nested_vmx_entry_ctls_high); | |
1554 | break; | |
1555 | case MSR_IA32_VMX_MISC: | |
1556 | *pdata = 0; | |
1557 | break; | |
1558 | /* | |
1559 | * These MSRs specify bits which the guest must keep fixed (on or off) | |
1560 | * while L1 is in VMXON mode (in L1's root mode, or running an L2). | |
1561 | * We picked the standard core2 setting. | |
1562 | */ | |
1563 | #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE) | |
1564 | #define VMXON_CR4_ALWAYSON X86_CR4_VMXE | |
1565 | case MSR_IA32_VMX_CR0_FIXED0: | |
1566 | *pdata = VMXON_CR0_ALWAYSON; | |
1567 | break; | |
1568 | case MSR_IA32_VMX_CR0_FIXED1: | |
1569 | *pdata = -1ULL; | |
1570 | break; | |
1571 | case MSR_IA32_VMX_CR4_FIXED0: | |
1572 | *pdata = VMXON_CR4_ALWAYSON; | |
1573 | break; | |
1574 | case MSR_IA32_VMX_CR4_FIXED1: | |
1575 | *pdata = -1ULL; | |
1576 | break; | |
1577 | case MSR_IA32_VMX_VMCS_ENUM: | |
1578 | *pdata = 0x1f; | |
1579 | break; | |
1580 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
1581 | *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low, | |
1582 | nested_vmx_secondary_ctls_high); | |
1583 | break; | |
1584 | case MSR_IA32_VMX_EPT_VPID_CAP: | |
1585 | /* Currently, no nested ept or nested vpid */ | |
1586 | *pdata = 0; | |
1587 | break; | |
1588 | default: | |
1589 | return 0; | |
1590 | } | |
1591 | ||
1592 | return 1; | |
1593 | } | |
1594 | ||
1595 | static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
1596 | { | |
1597 | if (!nested_vmx_allowed(vcpu)) | |
1598 | return 0; | |
1599 | ||
1600 | if (msr_index == MSR_IA32_FEATURE_CONTROL) | |
1601 | /* TODO: the right thing. */ | |
1602 | return 1; | |
1603 | /* | |
1604 | * No need to treat VMX capability MSRs specially: If we don't handle | |
1605 | * them, handle_wrmsr will #GP(0), which is correct (they are readonly) | |
1606 | */ | |
1607 | return 0; | |
1608 | } | |
1609 | ||
6aa8b732 AK |
1610 | /* |
1611 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
1612 | * Returns 0 on success, non-0 otherwise. | |
1613 | * Assumes vcpu_load() was already called. | |
1614 | */ | |
1615 | static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
1616 | { | |
1617 | u64 data; | |
26bb0981 | 1618 | struct shared_msr_entry *msr; |
6aa8b732 AK |
1619 | |
1620 | if (!pdata) { | |
1621 | printk(KERN_ERR "BUG: get_msr called with NULL pdata\n"); | |
1622 | return -EINVAL; | |
1623 | } | |
1624 | ||
1625 | switch (msr_index) { | |
05b3e0c2 | 1626 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1627 | case MSR_FS_BASE: |
1628 | data = vmcs_readl(GUEST_FS_BASE); | |
1629 | break; | |
1630 | case MSR_GS_BASE: | |
1631 | data = vmcs_readl(GUEST_GS_BASE); | |
1632 | break; | |
44ea2b17 AK |
1633 | case MSR_KERNEL_GS_BASE: |
1634 | vmx_load_host_state(to_vmx(vcpu)); | |
1635 | data = to_vmx(vcpu)->msr_guest_kernel_gs_base; | |
1636 | break; | |
26bb0981 | 1637 | #endif |
6aa8b732 | 1638 | case MSR_EFER: |
3bab1f5d | 1639 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
af24a4e4 | 1640 | case MSR_IA32_TSC: |
6aa8b732 AK |
1641 | data = guest_read_tsc(); |
1642 | break; | |
1643 | case MSR_IA32_SYSENTER_CS: | |
1644 | data = vmcs_read32(GUEST_SYSENTER_CS); | |
1645 | break; | |
1646 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 1647 | data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
1648 | break; |
1649 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 1650 | data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 1651 | break; |
4e47c7a6 SY |
1652 | case MSR_TSC_AUX: |
1653 | if (!to_vmx(vcpu)->rdtscp_enabled) | |
1654 | return 1; | |
1655 | /* Otherwise falls through */ | |
6aa8b732 | 1656 | default: |
26bb0981 | 1657 | vmx_load_host_state(to_vmx(vcpu)); |
b87a51ae NHE |
1658 | if (vmx_get_vmx_msr(vcpu, msr_index, pdata)) |
1659 | return 0; | |
8b9cf98c | 1660 | msr = find_msr_entry(to_vmx(vcpu), msr_index); |
3bab1f5d | 1661 | if (msr) { |
542423b0 | 1662 | vmx_load_host_state(to_vmx(vcpu)); |
3bab1f5d AK |
1663 | data = msr->data; |
1664 | break; | |
6aa8b732 | 1665 | } |
3bab1f5d | 1666 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
1667 | } |
1668 | ||
1669 | *pdata = data; | |
1670 | return 0; | |
1671 | } | |
1672 | ||
1673 | /* | |
1674 | * Writes msr value into into the appropriate "register". | |
1675 | * Returns 0 on success, non-0 otherwise. | |
1676 | * Assumes vcpu_load() was already called. | |
1677 | */ | |
1678 | static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
1679 | { | |
a2fa3e9f | 1680 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 1681 | struct shared_msr_entry *msr; |
2cc51560 ED |
1682 | int ret = 0; |
1683 | ||
6aa8b732 | 1684 | switch (msr_index) { |
3bab1f5d | 1685 | case MSR_EFER: |
a9b21b62 | 1686 | vmx_load_host_state(vmx); |
2cc51560 | 1687 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
2cc51560 | 1688 | break; |
16175a79 | 1689 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1690 | case MSR_FS_BASE: |
2fb92db1 | 1691 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
1692 | vmcs_writel(GUEST_FS_BASE, data); |
1693 | break; | |
1694 | case MSR_GS_BASE: | |
2fb92db1 | 1695 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
1696 | vmcs_writel(GUEST_GS_BASE, data); |
1697 | break; | |
44ea2b17 AK |
1698 | case MSR_KERNEL_GS_BASE: |
1699 | vmx_load_host_state(vmx); | |
1700 | vmx->msr_guest_kernel_gs_base = data; | |
1701 | break; | |
6aa8b732 AK |
1702 | #endif |
1703 | case MSR_IA32_SYSENTER_CS: | |
1704 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
1705 | break; | |
1706 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 1707 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
1708 | break; |
1709 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 1710 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 1711 | break; |
af24a4e4 | 1712 | case MSR_IA32_TSC: |
99e3e30a | 1713 | kvm_write_tsc(vcpu, data); |
6aa8b732 | 1714 | break; |
468d472f SY |
1715 | case MSR_IA32_CR_PAT: |
1716 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
1717 | vmcs_write64(GUEST_IA32_PAT, data); | |
1718 | vcpu->arch.pat = data; | |
1719 | break; | |
1720 | } | |
4e47c7a6 SY |
1721 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
1722 | break; | |
1723 | case MSR_TSC_AUX: | |
1724 | if (!vmx->rdtscp_enabled) | |
1725 | return 1; | |
1726 | /* Check reserved bit, higher 32 bits should be zero */ | |
1727 | if ((data >> 32) != 0) | |
1728 | return 1; | |
1729 | /* Otherwise falls through */ | |
6aa8b732 | 1730 | default: |
b87a51ae NHE |
1731 | if (vmx_set_vmx_msr(vcpu, msr_index, data)) |
1732 | break; | |
8b9cf98c | 1733 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d | 1734 | if (msr) { |
542423b0 | 1735 | vmx_load_host_state(vmx); |
3bab1f5d AK |
1736 | msr->data = data; |
1737 | break; | |
6aa8b732 | 1738 | } |
2cc51560 | 1739 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
6aa8b732 AK |
1740 | } |
1741 | ||
2cc51560 | 1742 | return ret; |
6aa8b732 AK |
1743 | } |
1744 | ||
5fdbf976 | 1745 | static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
6aa8b732 | 1746 | { |
5fdbf976 MT |
1747 | __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); |
1748 | switch (reg) { | |
1749 | case VCPU_REGS_RSP: | |
1750 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
1751 | break; | |
1752 | case VCPU_REGS_RIP: | |
1753 | vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); | |
1754 | break; | |
6de4f3ad AK |
1755 | case VCPU_EXREG_PDPTR: |
1756 | if (enable_ept) | |
1757 | ept_save_pdptrs(vcpu); | |
1758 | break; | |
5fdbf976 MT |
1759 | default: |
1760 | break; | |
1761 | } | |
6aa8b732 AK |
1762 | } |
1763 | ||
355be0b9 | 1764 | static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) |
6aa8b732 | 1765 | { |
ae675ef0 JK |
1766 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
1767 | vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]); | |
1768 | else | |
1769 | vmcs_writel(GUEST_DR7, vcpu->arch.dr7); | |
1770 | ||
abd3f2d6 | 1771 | update_exception_bitmap(vcpu); |
6aa8b732 AK |
1772 | } |
1773 | ||
1774 | static __init int cpu_has_kvm_support(void) | |
1775 | { | |
6210e37b | 1776 | return cpu_has_vmx(); |
6aa8b732 AK |
1777 | } |
1778 | ||
1779 | static __init int vmx_disabled_by_bios(void) | |
1780 | { | |
1781 | u64 msr; | |
1782 | ||
1783 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
cafd6659 | 1784 | if (msr & FEATURE_CONTROL_LOCKED) { |
23f3e991 | 1785 | /* launched w/ TXT and VMX disabled */ |
cafd6659 SW |
1786 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
1787 | && tboot_enabled()) | |
1788 | return 1; | |
23f3e991 | 1789 | /* launched w/o TXT and VMX only enabled w/ TXT */ |
cafd6659 | 1790 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) |
23f3e991 | 1791 | && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
f9335afe SW |
1792 | && !tboot_enabled()) { |
1793 | printk(KERN_WARNING "kvm: disable TXT in the BIOS or " | |
23f3e991 | 1794 | "activate TXT before enabling KVM\n"); |
cafd6659 | 1795 | return 1; |
f9335afe | 1796 | } |
23f3e991 JC |
1797 | /* launched w/o TXT and VMX disabled */ |
1798 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) | |
1799 | && !tboot_enabled()) | |
1800 | return 1; | |
cafd6659 SW |
1801 | } |
1802 | ||
1803 | return 0; | |
6aa8b732 AK |
1804 | } |
1805 | ||
7725b894 DX |
1806 | static void kvm_cpu_vmxon(u64 addr) |
1807 | { | |
1808 | asm volatile (ASM_VMX_VMXON_RAX | |
1809 | : : "a"(&addr), "m"(addr) | |
1810 | : "memory", "cc"); | |
1811 | } | |
1812 | ||
10474ae8 | 1813 | static int hardware_enable(void *garbage) |
6aa8b732 AK |
1814 | { |
1815 | int cpu = raw_smp_processor_id(); | |
1816 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
cafd6659 | 1817 | u64 old, test_bits; |
6aa8b732 | 1818 | |
10474ae8 AG |
1819 | if (read_cr4() & X86_CR4_VMXE) |
1820 | return -EBUSY; | |
1821 | ||
d462b819 | 1822 | INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); |
6aa8b732 | 1823 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
cafd6659 SW |
1824 | |
1825 | test_bits = FEATURE_CONTROL_LOCKED; | |
1826 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
1827 | if (tboot_enabled()) | |
1828 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; | |
1829 | ||
1830 | if ((old & test_bits) != test_bits) { | |
6aa8b732 | 1831 | /* enable and lock */ |
cafd6659 SW |
1832 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); |
1833 | } | |
66aee91a | 1834 | write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */ |
10474ae8 | 1835 | |
4610c9cc DX |
1836 | if (vmm_exclusive) { |
1837 | kvm_cpu_vmxon(phys_addr); | |
1838 | ept_sync_global(); | |
1839 | } | |
10474ae8 | 1840 | |
3444d7da AK |
1841 | store_gdt(&__get_cpu_var(host_gdt)); |
1842 | ||
10474ae8 | 1843 | return 0; |
6aa8b732 AK |
1844 | } |
1845 | ||
d462b819 | 1846 | static void vmclear_local_loaded_vmcss(void) |
543e4243 AK |
1847 | { |
1848 | int cpu = raw_smp_processor_id(); | |
d462b819 | 1849 | struct loaded_vmcs *v, *n; |
543e4243 | 1850 | |
d462b819 NHE |
1851 | list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), |
1852 | loaded_vmcss_on_cpu_link) | |
1853 | __loaded_vmcs_clear(v); | |
543e4243 AK |
1854 | } |
1855 | ||
710ff4a8 EH |
1856 | |
1857 | /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() | |
1858 | * tricks. | |
1859 | */ | |
1860 | static void kvm_cpu_vmxoff(void) | |
6aa8b732 | 1861 | { |
4ecac3fd | 1862 | asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
6aa8b732 AK |
1863 | } |
1864 | ||
710ff4a8 EH |
1865 | static void hardware_disable(void *garbage) |
1866 | { | |
4610c9cc | 1867 | if (vmm_exclusive) { |
d462b819 | 1868 | vmclear_local_loaded_vmcss(); |
4610c9cc DX |
1869 | kvm_cpu_vmxoff(); |
1870 | } | |
7725b894 | 1871 | write_cr4(read_cr4() & ~X86_CR4_VMXE); |
710ff4a8 EH |
1872 | } |
1873 | ||
1c3d14fe | 1874 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 1875 | u32 msr, u32 *result) |
1c3d14fe YS |
1876 | { |
1877 | u32 vmx_msr_low, vmx_msr_high; | |
1878 | u32 ctl = ctl_min | ctl_opt; | |
1879 | ||
1880 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
1881 | ||
1882 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
1883 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
1884 | ||
1885 | /* Ensure minimum (required) set of control bits are supported. */ | |
1886 | if (ctl_min & ~ctl) | |
002c7f7c | 1887 | return -EIO; |
1c3d14fe YS |
1888 | |
1889 | *result = ctl; | |
1890 | return 0; | |
1891 | } | |
1892 | ||
110312c8 AK |
1893 | static __init bool allow_1_setting(u32 msr, u32 ctl) |
1894 | { | |
1895 | u32 vmx_msr_low, vmx_msr_high; | |
1896 | ||
1897 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
1898 | return vmx_msr_high & ctl; | |
1899 | } | |
1900 | ||
002c7f7c | 1901 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
1902 | { |
1903 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 1904 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
1905 | u32 _pin_based_exec_control = 0; |
1906 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 1907 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
1908 | u32 _vmexit_control = 0; |
1909 | u32 _vmentry_control = 0; | |
1910 | ||
1911 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; | |
f08864b4 | 1912 | opt = PIN_BASED_VIRTUAL_NMIS; |
1c3d14fe YS |
1913 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
1914 | &_pin_based_exec_control) < 0) | |
002c7f7c | 1915 | return -EIO; |
1c3d14fe | 1916 | |
443381a8 | 1917 | min = |
1c3d14fe YS |
1918 | #ifdef CONFIG_X86_64 |
1919 | CPU_BASED_CR8_LOAD_EXITING | | |
1920 | CPU_BASED_CR8_STORE_EXITING | | |
1921 | #endif | |
d56f546d SY |
1922 | CPU_BASED_CR3_LOAD_EXITING | |
1923 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
1924 | CPU_BASED_USE_IO_BITMAPS | |
1925 | CPU_BASED_MOV_DR_EXITING | | |
a7052897 | 1926 | CPU_BASED_USE_TSC_OFFSETING | |
59708670 SY |
1927 | CPU_BASED_MWAIT_EXITING | |
1928 | CPU_BASED_MONITOR_EXITING | | |
a7052897 | 1929 | CPU_BASED_INVLPG_EXITING; |
443381a8 AL |
1930 | |
1931 | if (yield_on_hlt) | |
1932 | min |= CPU_BASED_HLT_EXITING; | |
1933 | ||
f78e0e2e | 1934 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 1935 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 1936 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
1937 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
1938 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 1939 | return -EIO; |
6e5d865c YS |
1940 | #ifdef CONFIG_X86_64 |
1941 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
1942 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
1943 | ~CPU_BASED_CR8_STORE_EXITING; | |
1944 | #endif | |
f78e0e2e | 1945 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
1946 | min2 = 0; |
1947 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
2384d2b3 | 1948 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d | 1949 | SECONDARY_EXEC_ENABLE_VPID | |
3a624e29 | 1950 | SECONDARY_EXEC_ENABLE_EPT | |
4b8d54f9 | 1951 | SECONDARY_EXEC_UNRESTRICTED_GUEST | |
4e47c7a6 SY |
1952 | SECONDARY_EXEC_PAUSE_LOOP_EXITING | |
1953 | SECONDARY_EXEC_RDTSCP; | |
d56f546d SY |
1954 | if (adjust_vmx_controls(min2, opt2, |
1955 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
1956 | &_cpu_based_2nd_exec_control) < 0) |
1957 | return -EIO; | |
1958 | } | |
1959 | #ifndef CONFIG_X86_64 | |
1960 | if (!(_cpu_based_2nd_exec_control & | |
1961 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
1962 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
1963 | #endif | |
d56f546d | 1964 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
a7052897 MT |
1965 | /* CR3 accesses and invlpg don't need to cause VM Exits when EPT |
1966 | enabled */ | |
5fff7d27 GN |
1967 | _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | |
1968 | CPU_BASED_CR3_STORE_EXITING | | |
1969 | CPU_BASED_INVLPG_EXITING); | |
d56f546d SY |
1970 | rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, |
1971 | vmx_capability.ept, vmx_capability.vpid); | |
1972 | } | |
1c3d14fe YS |
1973 | |
1974 | min = 0; | |
1975 | #ifdef CONFIG_X86_64 | |
1976 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
1977 | #endif | |
468d472f | 1978 | opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT; |
1c3d14fe YS |
1979 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, |
1980 | &_vmexit_control) < 0) | |
002c7f7c | 1981 | return -EIO; |
1c3d14fe | 1982 | |
468d472f SY |
1983 | min = 0; |
1984 | opt = VM_ENTRY_LOAD_IA32_PAT; | |
1c3d14fe YS |
1985 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, |
1986 | &_vmentry_control) < 0) | |
002c7f7c | 1987 | return -EIO; |
6aa8b732 | 1988 | |
c68876fd | 1989 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
1990 | |
1991 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
1992 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 1993 | return -EIO; |
1c3d14fe YS |
1994 | |
1995 | #ifdef CONFIG_X86_64 | |
1996 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
1997 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 1998 | return -EIO; |
1c3d14fe YS |
1999 | #endif |
2000 | ||
2001 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
2002 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 2003 | return -EIO; |
1c3d14fe | 2004 | |
002c7f7c YS |
2005 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
2006 | vmcs_conf->order = get_order(vmcs_config.size); | |
2007 | vmcs_conf->revision_id = vmx_msr_low; | |
1c3d14fe | 2008 | |
002c7f7c YS |
2009 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
2010 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 2011 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
2012 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
2013 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe | 2014 | |
110312c8 AK |
2015 | cpu_has_load_ia32_efer = |
2016 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
2017 | VM_ENTRY_LOAD_IA32_EFER) | |
2018 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
2019 | VM_EXIT_LOAD_IA32_EFER); | |
2020 | ||
1c3d14fe | 2021 | return 0; |
c68876fd | 2022 | } |
6aa8b732 AK |
2023 | |
2024 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
2025 | { | |
2026 | int node = cpu_to_node(cpu); | |
2027 | struct page *pages; | |
2028 | struct vmcs *vmcs; | |
2029 | ||
6484eb3e | 2030 | pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
2031 | if (!pages) |
2032 | return NULL; | |
2033 | vmcs = page_address(pages); | |
1c3d14fe YS |
2034 | memset(vmcs, 0, vmcs_config.size); |
2035 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
2036 | return vmcs; |
2037 | } | |
2038 | ||
2039 | static struct vmcs *alloc_vmcs(void) | |
2040 | { | |
d3b2c338 | 2041 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
2042 | } |
2043 | ||
2044 | static void free_vmcs(struct vmcs *vmcs) | |
2045 | { | |
1c3d14fe | 2046 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
2047 | } |
2048 | ||
d462b819 NHE |
2049 | /* |
2050 | * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded | |
2051 | */ | |
2052 | static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) | |
2053 | { | |
2054 | if (!loaded_vmcs->vmcs) | |
2055 | return; | |
2056 | loaded_vmcs_clear(loaded_vmcs); | |
2057 | free_vmcs(loaded_vmcs->vmcs); | |
2058 | loaded_vmcs->vmcs = NULL; | |
2059 | } | |
2060 | ||
39959588 | 2061 | static void free_kvm_area(void) |
6aa8b732 AK |
2062 | { |
2063 | int cpu; | |
2064 | ||
3230bb47 | 2065 | for_each_possible_cpu(cpu) { |
6aa8b732 | 2066 | free_vmcs(per_cpu(vmxarea, cpu)); |
3230bb47 ZA |
2067 | per_cpu(vmxarea, cpu) = NULL; |
2068 | } | |
6aa8b732 AK |
2069 | } |
2070 | ||
6aa8b732 AK |
2071 | static __init int alloc_kvm_area(void) |
2072 | { | |
2073 | int cpu; | |
2074 | ||
3230bb47 | 2075 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
2076 | struct vmcs *vmcs; |
2077 | ||
2078 | vmcs = alloc_vmcs_cpu(cpu); | |
2079 | if (!vmcs) { | |
2080 | free_kvm_area(); | |
2081 | return -ENOMEM; | |
2082 | } | |
2083 | ||
2084 | per_cpu(vmxarea, cpu) = vmcs; | |
2085 | } | |
2086 | return 0; | |
2087 | } | |
2088 | ||
2089 | static __init int hardware_setup(void) | |
2090 | { | |
002c7f7c YS |
2091 | if (setup_vmcs_config(&vmcs_config) < 0) |
2092 | return -EIO; | |
50a37eb4 JR |
2093 | |
2094 | if (boot_cpu_has(X86_FEATURE_NX)) | |
2095 | kvm_enable_efer_bits(EFER_NX); | |
2096 | ||
93ba03c2 SY |
2097 | if (!cpu_has_vmx_vpid()) |
2098 | enable_vpid = 0; | |
2099 | ||
4bc9b982 SY |
2100 | if (!cpu_has_vmx_ept() || |
2101 | !cpu_has_vmx_ept_4levels()) { | |
93ba03c2 | 2102 | enable_ept = 0; |
3a624e29 NK |
2103 | enable_unrestricted_guest = 0; |
2104 | } | |
2105 | ||
2106 | if (!cpu_has_vmx_unrestricted_guest()) | |
2107 | enable_unrestricted_guest = 0; | |
93ba03c2 SY |
2108 | |
2109 | if (!cpu_has_vmx_flexpriority()) | |
2110 | flexpriority_enabled = 0; | |
2111 | ||
95ba8273 GN |
2112 | if (!cpu_has_vmx_tpr_shadow()) |
2113 | kvm_x86_ops->update_cr8_intercept = NULL; | |
2114 | ||
54dee993 MT |
2115 | if (enable_ept && !cpu_has_vmx_ept_2m_page()) |
2116 | kvm_disable_largepages(); | |
2117 | ||
4b8d54f9 ZE |
2118 | if (!cpu_has_vmx_ple()) |
2119 | ple_gap = 0; | |
2120 | ||
b87a51ae NHE |
2121 | if (nested) |
2122 | nested_vmx_setup_ctls_msrs(); | |
2123 | ||
6aa8b732 AK |
2124 | return alloc_kvm_area(); |
2125 | } | |
2126 | ||
2127 | static __exit void hardware_unsetup(void) | |
2128 | { | |
2129 | free_kvm_area(); | |
2130 | } | |
2131 | ||
6aa8b732 AK |
2132 | static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save) |
2133 | { | |
2134 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
2135 | ||
6af11b9e | 2136 | if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) { |
6aa8b732 AK |
2137 | vmcs_write16(sf->selector, save->selector); |
2138 | vmcs_writel(sf->base, save->base); | |
2139 | vmcs_write32(sf->limit, save->limit); | |
2140 | vmcs_write32(sf->ar_bytes, save->ar); | |
2141 | } else { | |
2142 | u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK) | |
2143 | << AR_DPL_SHIFT; | |
2144 | vmcs_write32(sf->ar_bytes, 0x93 | dpl); | |
2145 | } | |
2146 | } | |
2147 | ||
2148 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
2149 | { | |
2150 | unsigned long flags; | |
a89a8fb9 | 2151 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 2152 | |
a89a8fb9 | 2153 | vmx->emulation_required = 1; |
7ffd92c5 | 2154 | vmx->rmode.vm86_active = 0; |
6aa8b732 | 2155 | |
2fb92db1 AK |
2156 | vmx_segment_cache_clear(vmx); |
2157 | ||
d0ba64f9 | 2158 | vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector); |
7ffd92c5 AK |
2159 | vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base); |
2160 | vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit); | |
2161 | vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar); | |
6aa8b732 AK |
2162 | |
2163 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 AK |
2164 | flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; |
2165 | flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
6aa8b732 AK |
2166 | vmcs_writel(GUEST_RFLAGS, flags); |
2167 | ||
66aee91a RR |
2168 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
2169 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
2170 | |
2171 | update_exception_bitmap(vcpu); | |
2172 | ||
a89a8fb9 MG |
2173 | if (emulate_invalid_guest_state) |
2174 | return; | |
2175 | ||
7ffd92c5 AK |
2176 | fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es); |
2177 | fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds); | |
2178 | fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs); | |
2179 | fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs); | |
6aa8b732 | 2180 | |
2fb92db1 AK |
2181 | vmx_segment_cache_clear(vmx); |
2182 | ||
6aa8b732 AK |
2183 | vmcs_write16(GUEST_SS_SELECTOR, 0); |
2184 | vmcs_write32(GUEST_SS_AR_BYTES, 0x93); | |
2185 | ||
2186 | vmcs_write16(GUEST_CS_SELECTOR, | |
2187 | vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK); | |
2188 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
2189 | } | |
2190 | ||
d77c26fc | 2191 | static gva_t rmode_tss_base(struct kvm *kvm) |
6aa8b732 | 2192 | { |
bfc6d222 | 2193 | if (!kvm->arch.tss_addr) { |
bc6678a3 MT |
2194 | struct kvm_memslots *slots; |
2195 | gfn_t base_gfn; | |
2196 | ||
90d83dc3 | 2197 | slots = kvm_memslots(kvm); |
f495c6e5 | 2198 | base_gfn = slots->memslots[0].base_gfn + |
46a26bf5 | 2199 | kvm->memslots->memslots[0].npages - 3; |
cbc94022 IE |
2200 | return base_gfn << PAGE_SHIFT; |
2201 | } | |
bfc6d222 | 2202 | return kvm->arch.tss_addr; |
6aa8b732 AK |
2203 | } |
2204 | ||
2205 | static void fix_rmode_seg(int seg, struct kvm_save_segment *save) | |
2206 | { | |
2207 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
2208 | ||
2209 | save->selector = vmcs_read16(sf->selector); | |
2210 | save->base = vmcs_readl(sf->base); | |
2211 | save->limit = vmcs_read32(sf->limit); | |
2212 | save->ar = vmcs_read32(sf->ar_bytes); | |
15b00f32 | 2213 | vmcs_write16(sf->selector, save->base >> 4); |
444e863d | 2214 | vmcs_write32(sf->base, save->base & 0xffff0); |
6aa8b732 AK |
2215 | vmcs_write32(sf->limit, 0xffff); |
2216 | vmcs_write32(sf->ar_bytes, 0xf3); | |
444e863d GN |
2217 | if (save->base & 0xf) |
2218 | printk_once(KERN_WARNING "kvm: segment base is not paragraph" | |
2219 | " aligned when entering protected mode (seg=%d)", | |
2220 | seg); | |
6aa8b732 AK |
2221 | } |
2222 | ||
2223 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
2224 | { | |
2225 | unsigned long flags; | |
a89a8fb9 | 2226 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 2227 | |
3a624e29 NK |
2228 | if (enable_unrestricted_guest) |
2229 | return; | |
2230 | ||
a89a8fb9 | 2231 | vmx->emulation_required = 1; |
7ffd92c5 | 2232 | vmx->rmode.vm86_active = 1; |
6aa8b732 | 2233 | |
776e58ea GN |
2234 | /* |
2235 | * Very old userspace does not call KVM_SET_TSS_ADDR before entering | |
2236 | * vcpu. Call it here with phys address pointing 16M below 4G. | |
2237 | */ | |
2238 | if (!vcpu->kvm->arch.tss_addr) { | |
2239 | printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " | |
2240 | "called before entering vcpu\n"); | |
2241 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); | |
2242 | vmx_set_tss_addr(vcpu->kvm, 0xfeffd000); | |
2243 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); | |
2244 | } | |
2245 | ||
2fb92db1 AK |
2246 | vmx_segment_cache_clear(vmx); |
2247 | ||
d0ba64f9 | 2248 | vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR); |
7ffd92c5 | 2249 | vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE); |
6aa8b732 AK |
2250 | vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm)); |
2251 | ||
7ffd92c5 | 2252 | vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT); |
6aa8b732 AK |
2253 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
2254 | ||
7ffd92c5 | 2255 | vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES); |
6aa8b732 AK |
2256 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
2257 | ||
2258 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 | 2259 | vmx->rmode.save_rflags = flags; |
6aa8b732 | 2260 | |
053de044 | 2261 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
2262 | |
2263 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 2264 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
2265 | update_exception_bitmap(vcpu); |
2266 | ||
a89a8fb9 MG |
2267 | if (emulate_invalid_guest_state) |
2268 | goto continue_rmode; | |
2269 | ||
6aa8b732 AK |
2270 | vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4); |
2271 | vmcs_write32(GUEST_SS_LIMIT, 0xffff); | |
2272 | vmcs_write32(GUEST_SS_AR_BYTES, 0xf3); | |
2273 | ||
2274 | vmcs_write32(GUEST_CS_AR_BYTES, 0xf3); | |
abacf8df | 2275 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); |
8cb5b033 AK |
2276 | if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000) |
2277 | vmcs_writel(GUEST_CS_BASE, 0xf0000); | |
6aa8b732 AK |
2278 | vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4); |
2279 | ||
7ffd92c5 AK |
2280 | fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es); |
2281 | fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds); | |
2282 | fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs); | |
2283 | fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs); | |
75880a01 | 2284 | |
a89a8fb9 | 2285 | continue_rmode: |
8668a3c4 | 2286 | kvm_mmu_reset_context(vcpu); |
6aa8b732 AK |
2287 | } |
2288 | ||
401d10de AS |
2289 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
2290 | { | |
2291 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
26bb0981 AK |
2292 | struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); |
2293 | ||
2294 | if (!msr) | |
2295 | return; | |
401d10de | 2296 | |
44ea2b17 AK |
2297 | /* |
2298 | * Force kernel_gs_base reloading before EFER changes, as control | |
2299 | * of this msr depends on is_long_mode(). | |
2300 | */ | |
2301 | vmx_load_host_state(to_vmx(vcpu)); | |
f6801dff | 2302 | vcpu->arch.efer = efer; |
401d10de AS |
2303 | if (efer & EFER_LMA) { |
2304 | vmcs_write32(VM_ENTRY_CONTROLS, | |
2305 | vmcs_read32(VM_ENTRY_CONTROLS) | | |
2306 | VM_ENTRY_IA32E_MODE); | |
2307 | msr->data = efer; | |
2308 | } else { | |
2309 | vmcs_write32(VM_ENTRY_CONTROLS, | |
2310 | vmcs_read32(VM_ENTRY_CONTROLS) & | |
2311 | ~VM_ENTRY_IA32E_MODE); | |
2312 | ||
2313 | msr->data = efer & ~EFER_LME; | |
2314 | } | |
2315 | setup_msrs(vmx); | |
2316 | } | |
2317 | ||
05b3e0c2 | 2318 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
2319 | |
2320 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
2321 | { | |
2322 | u32 guest_tr_ar; | |
2323 | ||
2fb92db1 AK |
2324 | vmx_segment_cache_clear(to_vmx(vcpu)); |
2325 | ||
6aa8b732 AK |
2326 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); |
2327 | if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { | |
2328 | printk(KERN_DEBUG "%s: tss fixup for long mode. \n", | |
b8688d51 | 2329 | __func__); |
6aa8b732 AK |
2330 | vmcs_write32(GUEST_TR_AR_BYTES, |
2331 | (guest_tr_ar & ~AR_TYPE_MASK) | |
2332 | | AR_TYPE_BUSY_64_TSS); | |
2333 | } | |
da38f438 | 2334 | vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); |
6aa8b732 AK |
2335 | } |
2336 | ||
2337 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
2338 | { | |
6aa8b732 AK |
2339 | vmcs_write32(VM_ENTRY_CONTROLS, |
2340 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 2341 | & ~VM_ENTRY_IA32E_MODE); |
da38f438 | 2342 | vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); |
6aa8b732 AK |
2343 | } |
2344 | ||
2345 | #endif | |
2346 | ||
2384d2b3 SY |
2347 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
2348 | { | |
b9d762fa | 2349 | vpid_sync_context(to_vmx(vcpu)); |
dd180b3e XG |
2350 | if (enable_ept) { |
2351 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
2352 | return; | |
4e1096d2 | 2353 | ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa)); |
dd180b3e | 2354 | } |
2384d2b3 SY |
2355 | } |
2356 | ||
e8467fda AK |
2357 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
2358 | { | |
2359 | ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; | |
2360 | ||
2361 | vcpu->arch.cr0 &= ~cr0_guest_owned_bits; | |
2362 | vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; | |
2363 | } | |
2364 | ||
aff48baa AK |
2365 | static void vmx_decache_cr3(struct kvm_vcpu *vcpu) |
2366 | { | |
2367 | if (enable_ept && is_paging(vcpu)) | |
2368 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); | |
2369 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
2370 | } | |
2371 | ||
25c4c276 | 2372 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 2373 | { |
fc78f519 AK |
2374 | ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; |
2375 | ||
2376 | vcpu->arch.cr4 &= ~cr4_guest_owned_bits; | |
2377 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; | |
399badf3 AK |
2378 | } |
2379 | ||
1439442c SY |
2380 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
2381 | { | |
6de4f3ad AK |
2382 | if (!test_bit(VCPU_EXREG_PDPTR, |
2383 | (unsigned long *)&vcpu->arch.regs_dirty)) | |
2384 | return; | |
2385 | ||
1439442c | 2386 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
ff03a073 JR |
2387 | vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]); |
2388 | vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]); | |
2389 | vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]); | |
2390 | vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]); | |
1439442c SY |
2391 | } |
2392 | } | |
2393 | ||
8f5d549f AK |
2394 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu) |
2395 | { | |
2396 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { | |
ff03a073 JR |
2397 | vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0); |
2398 | vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1); | |
2399 | vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2); | |
2400 | vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3); | |
8f5d549f | 2401 | } |
6de4f3ad AK |
2402 | |
2403 | __set_bit(VCPU_EXREG_PDPTR, | |
2404 | (unsigned long *)&vcpu->arch.regs_avail); | |
2405 | __set_bit(VCPU_EXREG_PDPTR, | |
2406 | (unsigned long *)&vcpu->arch.regs_dirty); | |
8f5d549f AK |
2407 | } |
2408 | ||
5e1746d6 | 2409 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
1439442c SY |
2410 | |
2411 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
2412 | unsigned long cr0, | |
2413 | struct kvm_vcpu *vcpu) | |
2414 | { | |
5233dd51 MT |
2415 | if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) |
2416 | vmx_decache_cr3(vcpu); | |
1439442c SY |
2417 | if (!(cr0 & X86_CR0_PG)) { |
2418 | /* From paging/starting to nonpaging */ | |
2419 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 2420 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
1439442c SY |
2421 | (CPU_BASED_CR3_LOAD_EXITING | |
2422 | CPU_BASED_CR3_STORE_EXITING)); | |
2423 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 2424 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c SY |
2425 | } else if (!is_paging(vcpu)) { |
2426 | /* From nonpaging to paging */ | |
2427 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 2428 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
1439442c SY |
2429 | ~(CPU_BASED_CR3_LOAD_EXITING | |
2430 | CPU_BASED_CR3_STORE_EXITING)); | |
2431 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 2432 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c | 2433 | } |
95eb84a7 SY |
2434 | |
2435 | if (!(cr0 & X86_CR0_WP)) | |
2436 | *hw_cr0 &= ~X86_CR0_WP; | |
1439442c SY |
2437 | } |
2438 | ||
6aa8b732 AK |
2439 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
2440 | { | |
7ffd92c5 | 2441 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3a624e29 NK |
2442 | unsigned long hw_cr0; |
2443 | ||
2444 | if (enable_unrestricted_guest) | |
2445 | hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST) | |
2446 | | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; | |
2447 | else | |
2448 | hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON; | |
1439442c | 2449 | |
7ffd92c5 | 2450 | if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) |
6aa8b732 AK |
2451 | enter_pmode(vcpu); |
2452 | ||
7ffd92c5 | 2453 | if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) |
6aa8b732 AK |
2454 | enter_rmode(vcpu); |
2455 | ||
05b3e0c2 | 2456 | #ifdef CONFIG_X86_64 |
f6801dff | 2457 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 2458 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 2459 | enter_lmode(vcpu); |
707d92fa | 2460 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
2461 | exit_lmode(vcpu); |
2462 | } | |
2463 | #endif | |
2464 | ||
089d034e | 2465 | if (enable_ept) |
1439442c SY |
2466 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); |
2467 | ||
02daab21 | 2468 | if (!vcpu->fpu_active) |
81231c69 | 2469 | hw_cr0 |= X86_CR0_TS | X86_CR0_MP; |
02daab21 | 2470 | |
6aa8b732 | 2471 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 2472 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 2473 | vcpu->arch.cr0 = cr0; |
69c73028 | 2474 | __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail); |
6aa8b732 AK |
2475 | } |
2476 | ||
1439442c SY |
2477 | static u64 construct_eptp(unsigned long root_hpa) |
2478 | { | |
2479 | u64 eptp; | |
2480 | ||
2481 | /* TODO write the value reading from MSR */ | |
2482 | eptp = VMX_EPT_DEFAULT_MT | | |
2483 | VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT; | |
2484 | eptp |= (root_hpa & PAGE_MASK); | |
2485 | ||
2486 | return eptp; | |
2487 | } | |
2488 | ||
6aa8b732 AK |
2489 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
2490 | { | |
1439442c SY |
2491 | unsigned long guest_cr3; |
2492 | u64 eptp; | |
2493 | ||
2494 | guest_cr3 = cr3; | |
089d034e | 2495 | if (enable_ept) { |
1439442c SY |
2496 | eptp = construct_eptp(cr3); |
2497 | vmcs_write64(EPT_POINTER, eptp); | |
9f8fe504 | 2498 | guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) : |
b927a3ce | 2499 | vcpu->kvm->arch.ept_identity_map_addr; |
7c93be44 | 2500 | ept_load_pdptrs(vcpu); |
1439442c SY |
2501 | } |
2502 | ||
2384d2b3 | 2503 | vmx_flush_tlb(vcpu); |
1439442c | 2504 | vmcs_writel(GUEST_CR3, guest_cr3); |
6aa8b732 AK |
2505 | } |
2506 | ||
5e1746d6 | 2507 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 2508 | { |
7ffd92c5 | 2509 | unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ? |
1439442c SY |
2510 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); |
2511 | ||
5e1746d6 NHE |
2512 | if (cr4 & X86_CR4_VMXE) { |
2513 | /* | |
2514 | * To use VMXON (and later other VMX instructions), a guest | |
2515 | * must first be able to turn on cr4.VMXE (see handle_vmon()). | |
2516 | * So basically the check on whether to allow nested VMX | |
2517 | * is here. | |
2518 | */ | |
2519 | if (!nested_vmx_allowed(vcpu)) | |
2520 | return 1; | |
2521 | } else if (to_vmx(vcpu)->nested.vmxon) | |
2522 | return 1; | |
2523 | ||
ad312c7c | 2524 | vcpu->arch.cr4 = cr4; |
bc23008b AK |
2525 | if (enable_ept) { |
2526 | if (!is_paging(vcpu)) { | |
2527 | hw_cr4 &= ~X86_CR4_PAE; | |
2528 | hw_cr4 |= X86_CR4_PSE; | |
2529 | } else if (!(cr4 & X86_CR4_PAE)) { | |
2530 | hw_cr4 &= ~X86_CR4_PAE; | |
2531 | } | |
2532 | } | |
1439442c SY |
2533 | |
2534 | vmcs_writel(CR4_READ_SHADOW, cr4); | |
2535 | vmcs_writel(GUEST_CR4, hw_cr4); | |
5e1746d6 | 2536 | return 0; |
6aa8b732 AK |
2537 | } |
2538 | ||
6aa8b732 AK |
2539 | static void vmx_get_segment(struct kvm_vcpu *vcpu, |
2540 | struct kvm_segment *var, int seg) | |
2541 | { | |
a9179499 | 2542 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
a9179499 | 2543 | struct kvm_save_segment *save; |
6aa8b732 AK |
2544 | u32 ar; |
2545 | ||
a9179499 AK |
2546 | if (vmx->rmode.vm86_active |
2547 | && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES | |
2548 | || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS | |
2549 | || seg == VCPU_SREG_GS) | |
2550 | && !emulate_invalid_guest_state) { | |
2551 | switch (seg) { | |
2552 | case VCPU_SREG_TR: save = &vmx->rmode.tr; break; | |
2553 | case VCPU_SREG_ES: save = &vmx->rmode.es; break; | |
2554 | case VCPU_SREG_DS: save = &vmx->rmode.ds; break; | |
2555 | case VCPU_SREG_FS: save = &vmx->rmode.fs; break; | |
2556 | case VCPU_SREG_GS: save = &vmx->rmode.gs; break; | |
2557 | default: BUG(); | |
2558 | } | |
2559 | var->selector = save->selector; | |
2560 | var->base = save->base; | |
2561 | var->limit = save->limit; | |
2562 | ar = save->ar; | |
2563 | if (seg == VCPU_SREG_TR | |
2fb92db1 | 2564 | || var->selector == vmx_read_guest_seg_selector(vmx, seg)) |
a9179499 AK |
2565 | goto use_saved_rmode_seg; |
2566 | } | |
2fb92db1 AK |
2567 | var->base = vmx_read_guest_seg_base(vmx, seg); |
2568 | var->limit = vmx_read_guest_seg_limit(vmx, seg); | |
2569 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
2570 | ar = vmx_read_guest_seg_ar(vmx, seg); | |
a9179499 | 2571 | use_saved_rmode_seg: |
9fd4a3b7 | 2572 | if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state) |
6aa8b732 AK |
2573 | ar = 0; |
2574 | var->type = ar & 15; | |
2575 | var->s = (ar >> 4) & 1; | |
2576 | var->dpl = (ar >> 5) & 3; | |
2577 | var->present = (ar >> 7) & 1; | |
2578 | var->avl = (ar >> 12) & 1; | |
2579 | var->l = (ar >> 13) & 1; | |
2580 | var->db = (ar >> 14) & 1; | |
2581 | var->g = (ar >> 15) & 1; | |
2582 | var->unusable = (ar >> 16) & 1; | |
2583 | } | |
2584 | ||
a9179499 AK |
2585 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
2586 | { | |
a9179499 AK |
2587 | struct kvm_segment s; |
2588 | ||
2589 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
2590 | vmx_get_segment(vcpu, &s, seg); | |
2591 | return s.base; | |
2592 | } | |
2fb92db1 | 2593 | return vmx_read_guest_seg_base(to_vmx(vcpu), seg); |
a9179499 AK |
2594 | } |
2595 | ||
69c73028 | 2596 | static int __vmx_get_cpl(struct kvm_vcpu *vcpu) |
2e4d2653 | 2597 | { |
3eeb3288 | 2598 | if (!is_protmode(vcpu)) |
2e4d2653 IE |
2599 | return 0; |
2600 | ||
f4c63e5d AK |
2601 | if (!is_long_mode(vcpu) |
2602 | && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */ | |
2e4d2653 IE |
2603 | return 3; |
2604 | ||
2fb92db1 | 2605 | return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3; |
2e4d2653 IE |
2606 | } |
2607 | ||
69c73028 AK |
2608 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
2609 | { | |
2610 | if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) { | |
2611 | __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail); | |
2612 | to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu); | |
2613 | } | |
2614 | return to_vmx(vcpu)->cpl; | |
2615 | } | |
2616 | ||
2617 | ||
653e3108 | 2618 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 2619 | { |
6aa8b732 AK |
2620 | u32 ar; |
2621 | ||
653e3108 | 2622 | if (var->unusable) |
6aa8b732 AK |
2623 | ar = 1 << 16; |
2624 | else { | |
2625 | ar = var->type & 15; | |
2626 | ar |= (var->s & 1) << 4; | |
2627 | ar |= (var->dpl & 3) << 5; | |
2628 | ar |= (var->present & 1) << 7; | |
2629 | ar |= (var->avl & 1) << 12; | |
2630 | ar |= (var->l & 1) << 13; | |
2631 | ar |= (var->db & 1) << 14; | |
2632 | ar |= (var->g & 1) << 15; | |
2633 | } | |
f7fbf1fd UL |
2634 | if (ar == 0) /* a 0 value means unusable */ |
2635 | ar = AR_UNUSABLE_MASK; | |
653e3108 AK |
2636 | |
2637 | return ar; | |
2638 | } | |
2639 | ||
2640 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
2641 | struct kvm_segment *var, int seg) | |
2642 | { | |
7ffd92c5 | 2643 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
653e3108 AK |
2644 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
2645 | u32 ar; | |
2646 | ||
2fb92db1 AK |
2647 | vmx_segment_cache_clear(vmx); |
2648 | ||
7ffd92c5 | 2649 | if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) { |
a8ba6c26 | 2650 | vmcs_write16(sf->selector, var->selector); |
7ffd92c5 AK |
2651 | vmx->rmode.tr.selector = var->selector; |
2652 | vmx->rmode.tr.base = var->base; | |
2653 | vmx->rmode.tr.limit = var->limit; | |
2654 | vmx->rmode.tr.ar = vmx_segment_access_rights(var); | |
653e3108 AK |
2655 | return; |
2656 | } | |
2657 | vmcs_writel(sf->base, var->base); | |
2658 | vmcs_write32(sf->limit, var->limit); | |
2659 | vmcs_write16(sf->selector, var->selector); | |
7ffd92c5 | 2660 | if (vmx->rmode.vm86_active && var->s) { |
653e3108 AK |
2661 | /* |
2662 | * Hack real-mode segments into vm86 compatibility. | |
2663 | */ | |
2664 | if (var->base == 0xffff0000 && var->selector == 0xf000) | |
2665 | vmcs_writel(sf->base, 0xf0000); | |
2666 | ar = 0xf3; | |
2667 | } else | |
2668 | ar = vmx_segment_access_rights(var); | |
3a624e29 NK |
2669 | |
2670 | /* | |
2671 | * Fix the "Accessed" bit in AR field of segment registers for older | |
2672 | * qemu binaries. | |
2673 | * IA32 arch specifies that at the time of processor reset the | |
2674 | * "Accessed" bit in the AR field of segment registers is 1. And qemu | |
2675 | * is setting it to 0 in the usedland code. This causes invalid guest | |
2676 | * state vmexit when "unrestricted guest" mode is turned on. | |
2677 | * Fix for this setup issue in cpu_reset is being pushed in the qemu | |
2678 | * tree. Newer qemu binaries with that qemu fix would not need this | |
2679 | * kvm hack. | |
2680 | */ | |
2681 | if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) | |
2682 | ar |= 0x1; /* Accessed */ | |
2683 | ||
6aa8b732 | 2684 | vmcs_write32(sf->ar_bytes, ar); |
69c73028 | 2685 | __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail); |
6aa8b732 AK |
2686 | } |
2687 | ||
6aa8b732 AK |
2688 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
2689 | { | |
2fb92db1 | 2690 | u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); |
6aa8b732 AK |
2691 | |
2692 | *db = (ar >> 14) & 1; | |
2693 | *l = (ar >> 13) & 1; | |
2694 | } | |
2695 | ||
89a27f4d | 2696 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2697 | { |
89a27f4d GN |
2698 | dt->size = vmcs_read32(GUEST_IDTR_LIMIT); |
2699 | dt->address = vmcs_readl(GUEST_IDTR_BASE); | |
6aa8b732 AK |
2700 | } |
2701 | ||
89a27f4d | 2702 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2703 | { |
89a27f4d GN |
2704 | vmcs_write32(GUEST_IDTR_LIMIT, dt->size); |
2705 | vmcs_writel(GUEST_IDTR_BASE, dt->address); | |
6aa8b732 AK |
2706 | } |
2707 | ||
89a27f4d | 2708 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2709 | { |
89a27f4d GN |
2710 | dt->size = vmcs_read32(GUEST_GDTR_LIMIT); |
2711 | dt->address = vmcs_readl(GUEST_GDTR_BASE); | |
6aa8b732 AK |
2712 | } |
2713 | ||
89a27f4d | 2714 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2715 | { |
89a27f4d GN |
2716 | vmcs_write32(GUEST_GDTR_LIMIT, dt->size); |
2717 | vmcs_writel(GUEST_GDTR_BASE, dt->address); | |
6aa8b732 AK |
2718 | } |
2719 | ||
648dfaa7 MG |
2720 | static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) |
2721 | { | |
2722 | struct kvm_segment var; | |
2723 | u32 ar; | |
2724 | ||
2725 | vmx_get_segment(vcpu, &var, seg); | |
2726 | ar = vmx_segment_access_rights(&var); | |
2727 | ||
2728 | if (var.base != (var.selector << 4)) | |
2729 | return false; | |
2730 | if (var.limit != 0xffff) | |
2731 | return false; | |
2732 | if (ar != 0xf3) | |
2733 | return false; | |
2734 | ||
2735 | return true; | |
2736 | } | |
2737 | ||
2738 | static bool code_segment_valid(struct kvm_vcpu *vcpu) | |
2739 | { | |
2740 | struct kvm_segment cs; | |
2741 | unsigned int cs_rpl; | |
2742 | ||
2743 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
2744 | cs_rpl = cs.selector & SELECTOR_RPL_MASK; | |
2745 | ||
1872a3f4 AK |
2746 | if (cs.unusable) |
2747 | return false; | |
648dfaa7 MG |
2748 | if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK)) |
2749 | return false; | |
2750 | if (!cs.s) | |
2751 | return false; | |
1872a3f4 | 2752 | if (cs.type & AR_TYPE_WRITEABLE_MASK) { |
648dfaa7 MG |
2753 | if (cs.dpl > cs_rpl) |
2754 | return false; | |
1872a3f4 | 2755 | } else { |
648dfaa7 MG |
2756 | if (cs.dpl != cs_rpl) |
2757 | return false; | |
2758 | } | |
2759 | if (!cs.present) | |
2760 | return false; | |
2761 | ||
2762 | /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ | |
2763 | return true; | |
2764 | } | |
2765 | ||
2766 | static bool stack_segment_valid(struct kvm_vcpu *vcpu) | |
2767 | { | |
2768 | struct kvm_segment ss; | |
2769 | unsigned int ss_rpl; | |
2770 | ||
2771 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
2772 | ss_rpl = ss.selector & SELECTOR_RPL_MASK; | |
2773 | ||
1872a3f4 AK |
2774 | if (ss.unusable) |
2775 | return true; | |
2776 | if (ss.type != 3 && ss.type != 7) | |
648dfaa7 MG |
2777 | return false; |
2778 | if (!ss.s) | |
2779 | return false; | |
2780 | if (ss.dpl != ss_rpl) /* DPL != RPL */ | |
2781 | return false; | |
2782 | if (!ss.present) | |
2783 | return false; | |
2784 | ||
2785 | return true; | |
2786 | } | |
2787 | ||
2788 | static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) | |
2789 | { | |
2790 | struct kvm_segment var; | |
2791 | unsigned int rpl; | |
2792 | ||
2793 | vmx_get_segment(vcpu, &var, seg); | |
2794 | rpl = var.selector & SELECTOR_RPL_MASK; | |
2795 | ||
1872a3f4 AK |
2796 | if (var.unusable) |
2797 | return true; | |
648dfaa7 MG |
2798 | if (!var.s) |
2799 | return false; | |
2800 | if (!var.present) | |
2801 | return false; | |
2802 | if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) { | |
2803 | if (var.dpl < rpl) /* DPL < RPL */ | |
2804 | return false; | |
2805 | } | |
2806 | ||
2807 | /* TODO: Add other members to kvm_segment_field to allow checking for other access | |
2808 | * rights flags | |
2809 | */ | |
2810 | return true; | |
2811 | } | |
2812 | ||
2813 | static bool tr_valid(struct kvm_vcpu *vcpu) | |
2814 | { | |
2815 | struct kvm_segment tr; | |
2816 | ||
2817 | vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); | |
2818 | ||
1872a3f4 AK |
2819 | if (tr.unusable) |
2820 | return false; | |
648dfaa7 MG |
2821 | if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */ |
2822 | return false; | |
1872a3f4 | 2823 | if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ |
648dfaa7 MG |
2824 | return false; |
2825 | if (!tr.present) | |
2826 | return false; | |
2827 | ||
2828 | return true; | |
2829 | } | |
2830 | ||
2831 | static bool ldtr_valid(struct kvm_vcpu *vcpu) | |
2832 | { | |
2833 | struct kvm_segment ldtr; | |
2834 | ||
2835 | vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); | |
2836 | ||
1872a3f4 AK |
2837 | if (ldtr.unusable) |
2838 | return true; | |
648dfaa7 MG |
2839 | if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */ |
2840 | return false; | |
2841 | if (ldtr.type != 2) | |
2842 | return false; | |
2843 | if (!ldtr.present) | |
2844 | return false; | |
2845 | ||
2846 | return true; | |
2847 | } | |
2848 | ||
2849 | static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) | |
2850 | { | |
2851 | struct kvm_segment cs, ss; | |
2852 | ||
2853 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
2854 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
2855 | ||
2856 | return ((cs.selector & SELECTOR_RPL_MASK) == | |
2857 | (ss.selector & SELECTOR_RPL_MASK)); | |
2858 | } | |
2859 | ||
2860 | /* | |
2861 | * Check if guest state is valid. Returns true if valid, false if | |
2862 | * not. | |
2863 | * We assume that registers are always usable | |
2864 | */ | |
2865 | static bool guest_state_valid(struct kvm_vcpu *vcpu) | |
2866 | { | |
2867 | /* real mode guest state checks */ | |
3eeb3288 | 2868 | if (!is_protmode(vcpu)) { |
648dfaa7 MG |
2869 | if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) |
2870 | return false; | |
2871 | if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) | |
2872 | return false; | |
2873 | if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) | |
2874 | return false; | |
2875 | if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) | |
2876 | return false; | |
2877 | if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) | |
2878 | return false; | |
2879 | if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) | |
2880 | return false; | |
2881 | } else { | |
2882 | /* protected mode guest state checks */ | |
2883 | if (!cs_ss_rpl_check(vcpu)) | |
2884 | return false; | |
2885 | if (!code_segment_valid(vcpu)) | |
2886 | return false; | |
2887 | if (!stack_segment_valid(vcpu)) | |
2888 | return false; | |
2889 | if (!data_segment_valid(vcpu, VCPU_SREG_DS)) | |
2890 | return false; | |
2891 | if (!data_segment_valid(vcpu, VCPU_SREG_ES)) | |
2892 | return false; | |
2893 | if (!data_segment_valid(vcpu, VCPU_SREG_FS)) | |
2894 | return false; | |
2895 | if (!data_segment_valid(vcpu, VCPU_SREG_GS)) | |
2896 | return false; | |
2897 | if (!tr_valid(vcpu)) | |
2898 | return false; | |
2899 | if (!ldtr_valid(vcpu)) | |
2900 | return false; | |
2901 | } | |
2902 | /* TODO: | |
2903 | * - Add checks on RIP | |
2904 | * - Add checks on RFLAGS | |
2905 | */ | |
2906 | ||
2907 | return true; | |
2908 | } | |
2909 | ||
d77c26fc | 2910 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 2911 | { |
40dcaa9f | 2912 | gfn_t fn; |
195aefde | 2913 | u16 data = 0; |
40dcaa9f | 2914 | int r, idx, ret = 0; |
6aa8b732 | 2915 | |
40dcaa9f XG |
2916 | idx = srcu_read_lock(&kvm->srcu); |
2917 | fn = rmode_tss_base(kvm) >> PAGE_SHIFT; | |
195aefde IE |
2918 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
2919 | if (r < 0) | |
10589a46 | 2920 | goto out; |
195aefde | 2921 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
464d17c8 SY |
2922 | r = kvm_write_guest_page(kvm, fn++, &data, |
2923 | TSS_IOPB_BASE_OFFSET, sizeof(u16)); | |
195aefde | 2924 | if (r < 0) |
10589a46 | 2925 | goto out; |
195aefde IE |
2926 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
2927 | if (r < 0) | |
10589a46 | 2928 | goto out; |
195aefde IE |
2929 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
2930 | if (r < 0) | |
10589a46 | 2931 | goto out; |
195aefde | 2932 | data = ~0; |
10589a46 MT |
2933 | r = kvm_write_guest_page(kvm, fn, &data, |
2934 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
2935 | sizeof(u8)); | |
195aefde | 2936 | if (r < 0) |
10589a46 MT |
2937 | goto out; |
2938 | ||
2939 | ret = 1; | |
2940 | out: | |
40dcaa9f | 2941 | srcu_read_unlock(&kvm->srcu, idx); |
10589a46 | 2942 | return ret; |
6aa8b732 AK |
2943 | } |
2944 | ||
b7ebfb05 SY |
2945 | static int init_rmode_identity_map(struct kvm *kvm) |
2946 | { | |
40dcaa9f | 2947 | int i, idx, r, ret; |
b7ebfb05 SY |
2948 | pfn_t identity_map_pfn; |
2949 | u32 tmp; | |
2950 | ||
089d034e | 2951 | if (!enable_ept) |
b7ebfb05 SY |
2952 | return 1; |
2953 | if (unlikely(!kvm->arch.ept_identity_pagetable)) { | |
2954 | printk(KERN_ERR "EPT: identity-mapping pagetable " | |
2955 | "haven't been allocated!\n"); | |
2956 | return 0; | |
2957 | } | |
2958 | if (likely(kvm->arch.ept_identity_pagetable_done)) | |
2959 | return 1; | |
2960 | ret = 0; | |
b927a3ce | 2961 | identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT; |
40dcaa9f | 2962 | idx = srcu_read_lock(&kvm->srcu); |
b7ebfb05 SY |
2963 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); |
2964 | if (r < 0) | |
2965 | goto out; | |
2966 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
2967 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
2968 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
2969 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
2970 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
2971 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
2972 | if (r < 0) | |
2973 | goto out; | |
2974 | } | |
2975 | kvm->arch.ept_identity_pagetable_done = true; | |
2976 | ret = 1; | |
2977 | out: | |
40dcaa9f | 2978 | srcu_read_unlock(&kvm->srcu, idx); |
b7ebfb05 SY |
2979 | return ret; |
2980 | } | |
2981 | ||
6aa8b732 AK |
2982 | static void seg_setup(int seg) |
2983 | { | |
2984 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
3a624e29 | 2985 | unsigned int ar; |
6aa8b732 AK |
2986 | |
2987 | vmcs_write16(sf->selector, 0); | |
2988 | vmcs_writel(sf->base, 0); | |
2989 | vmcs_write32(sf->limit, 0xffff); | |
3a624e29 NK |
2990 | if (enable_unrestricted_guest) { |
2991 | ar = 0x93; | |
2992 | if (seg == VCPU_SREG_CS) | |
2993 | ar |= 0x08; /* code segment */ | |
2994 | } else | |
2995 | ar = 0xf3; | |
2996 | ||
2997 | vmcs_write32(sf->ar_bytes, ar); | |
6aa8b732 AK |
2998 | } |
2999 | ||
f78e0e2e SY |
3000 | static int alloc_apic_access_page(struct kvm *kvm) |
3001 | { | |
3002 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
3003 | int r = 0; | |
3004 | ||
79fac95e | 3005 | mutex_lock(&kvm->slots_lock); |
bfc6d222 | 3006 | if (kvm->arch.apic_access_page) |
f78e0e2e SY |
3007 | goto out; |
3008 | kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; | |
3009 | kvm_userspace_mem.flags = 0; | |
3010 | kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL; | |
3011 | kvm_userspace_mem.memory_size = PAGE_SIZE; | |
3012 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
3013 | if (r) | |
3014 | goto out; | |
72dc67a6 | 3015 | |
bfc6d222 | 3016 | kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00); |
f78e0e2e | 3017 | out: |
79fac95e | 3018 | mutex_unlock(&kvm->slots_lock); |
f78e0e2e SY |
3019 | return r; |
3020 | } | |
3021 | ||
b7ebfb05 SY |
3022 | static int alloc_identity_pagetable(struct kvm *kvm) |
3023 | { | |
3024 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
3025 | int r = 0; | |
3026 | ||
79fac95e | 3027 | mutex_lock(&kvm->slots_lock); |
b7ebfb05 SY |
3028 | if (kvm->arch.ept_identity_pagetable) |
3029 | goto out; | |
3030 | kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; | |
3031 | kvm_userspace_mem.flags = 0; | |
b927a3ce SY |
3032 | kvm_userspace_mem.guest_phys_addr = |
3033 | kvm->arch.ept_identity_map_addr; | |
b7ebfb05 SY |
3034 | kvm_userspace_mem.memory_size = PAGE_SIZE; |
3035 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
3036 | if (r) | |
3037 | goto out; | |
3038 | ||
b7ebfb05 | 3039 | kvm->arch.ept_identity_pagetable = gfn_to_page(kvm, |
b927a3ce | 3040 | kvm->arch.ept_identity_map_addr >> PAGE_SHIFT); |
b7ebfb05 | 3041 | out: |
79fac95e | 3042 | mutex_unlock(&kvm->slots_lock); |
b7ebfb05 SY |
3043 | return r; |
3044 | } | |
3045 | ||
2384d2b3 SY |
3046 | static void allocate_vpid(struct vcpu_vmx *vmx) |
3047 | { | |
3048 | int vpid; | |
3049 | ||
3050 | vmx->vpid = 0; | |
919818ab | 3051 | if (!enable_vpid) |
2384d2b3 SY |
3052 | return; |
3053 | spin_lock(&vmx_vpid_lock); | |
3054 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
3055 | if (vpid < VMX_NR_VPIDS) { | |
3056 | vmx->vpid = vpid; | |
3057 | __set_bit(vpid, vmx_vpid_bitmap); | |
3058 | } | |
3059 | spin_unlock(&vmx_vpid_lock); | |
3060 | } | |
3061 | ||
cdbecfc3 LJ |
3062 | static void free_vpid(struct vcpu_vmx *vmx) |
3063 | { | |
3064 | if (!enable_vpid) | |
3065 | return; | |
3066 | spin_lock(&vmx_vpid_lock); | |
3067 | if (vmx->vpid != 0) | |
3068 | __clear_bit(vmx->vpid, vmx_vpid_bitmap); | |
3069 | spin_unlock(&vmx_vpid_lock); | |
3070 | } | |
3071 | ||
5897297b | 3072 | static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr) |
25c5f225 | 3073 | { |
3e7c73e9 | 3074 | int f = sizeof(unsigned long); |
25c5f225 SY |
3075 | |
3076 | if (!cpu_has_vmx_msr_bitmap()) | |
3077 | return; | |
3078 | ||
3079 | /* | |
3080 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
3081 | * have the write-low and read-high bitmap offsets the wrong way round. | |
3082 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
3083 | */ | |
25c5f225 | 3084 | if (msr <= 0x1fff) { |
3e7c73e9 AK |
3085 | __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */ |
3086 | __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */ | |
25c5f225 SY |
3087 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { |
3088 | msr &= 0x1fff; | |
3e7c73e9 AK |
3089 | __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */ |
3090 | __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */ | |
25c5f225 | 3091 | } |
25c5f225 SY |
3092 | } |
3093 | ||
5897297b AK |
3094 | static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only) |
3095 | { | |
3096 | if (!longmode_only) | |
3097 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr); | |
3098 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr); | |
3099 | } | |
3100 | ||
6aa8b732 AK |
3101 | /* |
3102 | * Sets up the vmcs for emulated real mode. | |
3103 | */ | |
8b9cf98c | 3104 | static int vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 | 3105 | { |
468d472f | 3106 | u32 host_sysenter_cs, msr_low, msr_high; |
6aa8b732 | 3107 | u32 junk; |
f4e1b3c8 | 3108 | u64 host_pat; |
6aa8b732 | 3109 | unsigned long a; |
89a27f4d | 3110 | struct desc_ptr dt; |
6aa8b732 | 3111 | int i; |
cd2276a7 | 3112 | unsigned long kvm_vmx_return; |
6e5d865c | 3113 | u32 exec_control; |
6aa8b732 | 3114 | |
6aa8b732 | 3115 | /* I/O */ |
3e7c73e9 AK |
3116 | vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a)); |
3117 | vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b)); | |
6aa8b732 | 3118 | |
25c5f225 | 3119 | if (cpu_has_vmx_msr_bitmap()) |
5897297b | 3120 | vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy)); |
25c5f225 | 3121 | |
6aa8b732 AK |
3122 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
3123 | ||
6aa8b732 | 3124 | /* Control */ |
1c3d14fe YS |
3125 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, |
3126 | vmcs_config.pin_based_exec_ctrl); | |
6e5d865c YS |
3127 | |
3128 | exec_control = vmcs_config.cpu_based_exec_ctrl; | |
3129 | if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) { | |
3130 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
3131 | #ifdef CONFIG_X86_64 | |
3132 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
3133 | CPU_BASED_CR8_LOAD_EXITING; | |
3134 | #endif | |
3135 | } | |
089d034e | 3136 | if (!enable_ept) |
d56f546d | 3137 | exec_control |= CPU_BASED_CR3_STORE_EXITING | |
83dbc83a MT |
3138 | CPU_BASED_CR3_LOAD_EXITING | |
3139 | CPU_BASED_INVLPG_EXITING; | |
6e5d865c | 3140 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); |
6aa8b732 | 3141 | |
83ff3b9d SY |
3142 | if (cpu_has_secondary_exec_ctrls()) { |
3143 | exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; | |
3144 | if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
3145 | exec_control &= | |
3146 | ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
2384d2b3 SY |
3147 | if (vmx->vpid == 0) |
3148 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
046d8710 | 3149 | if (!enable_ept) { |
d56f546d | 3150 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; |
046d8710 SY |
3151 | enable_unrestricted_guest = 0; |
3152 | } | |
3a624e29 NK |
3153 | if (!enable_unrestricted_guest) |
3154 | exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
4b8d54f9 ZE |
3155 | if (!ple_gap) |
3156 | exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
83ff3b9d SY |
3157 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
3158 | } | |
f78e0e2e | 3159 | |
4b8d54f9 ZE |
3160 | if (ple_gap) { |
3161 | vmcs_write32(PLE_GAP, ple_gap); | |
3162 | vmcs_write32(PLE_WINDOW, ple_window); | |
3163 | } | |
3164 | ||
c7addb90 AK |
3165 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf); |
3166 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf); | |
6aa8b732 AK |
3167 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
3168 | ||
1c11e713 | 3169 | vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */ |
6aa8b732 AK |
3170 | vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */ |
3171 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ | |
3172 | ||
3173 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ | |
3174 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
3175 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
9581d442 AK |
3176 | vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ |
3177 | vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ | |
6aa8b732 | 3178 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
05b3e0c2 | 3179 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
3180 | rdmsrl(MSR_FS_BASE, a); |
3181 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
3182 | rdmsrl(MSR_GS_BASE, a); | |
3183 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
3184 | #else | |
3185 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
3186 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
3187 | #endif | |
3188 | ||
3189 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
3190 | ||
ec68798c | 3191 | native_store_idt(&dt); |
89a27f4d | 3192 | vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */ |
6aa8b732 | 3193 | |
d77c26fc | 3194 | asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return)); |
cd2276a7 | 3195 | vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */ |
2cc51560 ED |
3196 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
3197 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
61d2ef2c | 3198 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host)); |
2cc51560 | 3199 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); |
61d2ef2c | 3200 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); |
6aa8b732 AK |
3201 | |
3202 | rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk); | |
3203 | vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs); | |
3204 | rdmsrl(MSR_IA32_SYSENTER_ESP, a); | |
3205 | vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */ | |
3206 | rdmsrl(MSR_IA32_SYSENTER_EIP, a); | |
3207 | vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */ | |
3208 | ||
468d472f SY |
3209 | if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { |
3210 | rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high); | |
3211 | host_pat = msr_low | ((u64) msr_high << 32); | |
3212 | vmcs_write64(HOST_IA32_PAT, host_pat); | |
3213 | } | |
3214 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
3215 | rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high); | |
3216 | host_pat = msr_low | ((u64) msr_high << 32); | |
3217 | /* Write the default value follow host pat */ | |
3218 | vmcs_write64(GUEST_IA32_PAT, host_pat); | |
3219 | /* Keep arch.pat sync with GUEST_IA32_PAT */ | |
3220 | vmx->vcpu.arch.pat = host_pat; | |
3221 | } | |
3222 | ||
6aa8b732 AK |
3223 | for (i = 0; i < NR_VMX_MSR; ++i) { |
3224 | u32 index = vmx_msr_index[i]; | |
3225 | u32 data_low, data_high; | |
a2fa3e9f | 3226 | int j = vmx->nmsrs; |
6aa8b732 AK |
3227 | |
3228 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
3229 | continue; | |
432bd6cb AK |
3230 | if (wrmsr_safe(index, data_low, data_high) < 0) |
3231 | continue; | |
26bb0981 AK |
3232 | vmx->guest_msrs[j].index = i; |
3233 | vmx->guest_msrs[j].data = 0; | |
d5696725 | 3234 | vmx->guest_msrs[j].mask = -1ull; |
a2fa3e9f | 3235 | ++vmx->nmsrs; |
6aa8b732 | 3236 | } |
6aa8b732 | 3237 | |
1c3d14fe | 3238 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
6aa8b732 AK |
3239 | |
3240 | /* 22.2.1, 20.8.1 */ | |
1c3d14fe YS |
3241 | vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl); |
3242 | ||
e00c8cf2 | 3243 | vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL); |
4c38609a | 3244 | vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; |
ce03e4f2 AK |
3245 | if (enable_ept) |
3246 | vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; | |
4c38609a | 3247 | vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); |
e00c8cf2 | 3248 | |
99e3e30a | 3249 | kvm_write_tsc(&vmx->vcpu, 0); |
f78e0e2e | 3250 | |
e00c8cf2 AK |
3251 | return 0; |
3252 | } | |
3253 | ||
3254 | static int vmx_vcpu_reset(struct kvm_vcpu *vcpu) | |
3255 | { | |
3256 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
3257 | u64 msr; | |
4b9d3a04 | 3258 | int ret; |
e00c8cf2 | 3259 | |
5fdbf976 | 3260 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)); |
e00c8cf2 | 3261 | |
7ffd92c5 | 3262 | vmx->rmode.vm86_active = 0; |
e00c8cf2 | 3263 | |
3b86cd99 JK |
3264 | vmx->soft_vnmi_blocked = 0; |
3265 | ||
ad312c7c | 3266 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
2d3ad1f4 | 3267 | kvm_set_cr8(&vmx->vcpu, 0); |
e00c8cf2 | 3268 | msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 3269 | if (kvm_vcpu_is_bsp(&vmx->vcpu)) |
e00c8cf2 AK |
3270 | msr |= MSR_IA32_APICBASE_BSP; |
3271 | kvm_set_apic_base(&vmx->vcpu, msr); | |
3272 | ||
10ab25cd JK |
3273 | ret = fx_init(&vmx->vcpu); |
3274 | if (ret != 0) | |
3275 | goto out; | |
e00c8cf2 | 3276 | |
2fb92db1 AK |
3277 | vmx_segment_cache_clear(vmx); |
3278 | ||
5706be0d | 3279 | seg_setup(VCPU_SREG_CS); |
e00c8cf2 AK |
3280 | /* |
3281 | * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode | |
3282 | * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh. | |
3283 | */ | |
c5af89b6 | 3284 | if (kvm_vcpu_is_bsp(&vmx->vcpu)) { |
e00c8cf2 AK |
3285 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); |
3286 | vmcs_writel(GUEST_CS_BASE, 0x000f0000); | |
3287 | } else { | |
ad312c7c ZX |
3288 | vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8); |
3289 | vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12); | |
e00c8cf2 | 3290 | } |
e00c8cf2 AK |
3291 | |
3292 | seg_setup(VCPU_SREG_DS); | |
3293 | seg_setup(VCPU_SREG_ES); | |
3294 | seg_setup(VCPU_SREG_FS); | |
3295 | seg_setup(VCPU_SREG_GS); | |
3296 | seg_setup(VCPU_SREG_SS); | |
3297 | ||
3298 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
3299 | vmcs_writel(GUEST_TR_BASE, 0); | |
3300 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
3301 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
3302 | ||
3303 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
3304 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
3305 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
3306 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
3307 | ||
3308 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
3309 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
3310 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
3311 | ||
3312 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
c5af89b6 | 3313 | if (kvm_vcpu_is_bsp(&vmx->vcpu)) |
5fdbf976 | 3314 | kvm_rip_write(vcpu, 0xfff0); |
e00c8cf2 | 3315 | else |
5fdbf976 MT |
3316 | kvm_rip_write(vcpu, 0); |
3317 | kvm_register_write(vcpu, VCPU_REGS_RSP, 0); | |
e00c8cf2 | 3318 | |
e00c8cf2 AK |
3319 | vmcs_writel(GUEST_DR7, 0x400); |
3320 | ||
3321 | vmcs_writel(GUEST_GDTR_BASE, 0); | |
3322 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
3323 | ||
3324 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
3325 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
3326 | ||
443381a8 | 3327 | vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); |
e00c8cf2 AK |
3328 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); |
3329 | vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0); | |
3330 | ||
e00c8cf2 AK |
3331 | /* Special registers */ |
3332 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
3333 | ||
3334 | setup_msrs(vmx); | |
3335 | ||
6aa8b732 AK |
3336 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
3337 | ||
f78e0e2e SY |
3338 | if (cpu_has_vmx_tpr_shadow()) { |
3339 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); | |
3340 | if (vm_need_tpr_shadow(vmx->vcpu.kvm)) | |
3341 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, | |
afc20184 | 3342 | __pa(vmx->vcpu.arch.apic->regs)); |
f78e0e2e SY |
3343 | vmcs_write32(TPR_THRESHOLD, 0); |
3344 | } | |
3345 | ||
3346 | if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
3347 | vmcs_write64(APIC_ACCESS_ADDR, | |
bfc6d222 | 3348 | page_to_phys(vmx->vcpu.kvm->arch.apic_access_page)); |
6aa8b732 | 3349 | |
2384d2b3 SY |
3350 | if (vmx->vpid != 0) |
3351 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
3352 | ||
fa40052c | 3353 | vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; |
4d4ec087 | 3354 | vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */ |
8b9cf98c | 3355 | vmx_set_cr4(&vmx->vcpu, 0); |
8b9cf98c | 3356 | vmx_set_efer(&vmx->vcpu, 0); |
8b9cf98c RR |
3357 | vmx_fpu_activate(&vmx->vcpu); |
3358 | update_exception_bitmap(&vmx->vcpu); | |
6aa8b732 | 3359 | |
b9d762fa | 3360 | vpid_sync_context(vmx); |
2384d2b3 | 3361 | |
3200f405 | 3362 | ret = 0; |
6aa8b732 | 3363 | |
a89a8fb9 MG |
3364 | /* HACK: Don't enable emulation on guest boot/reset */ |
3365 | vmx->emulation_required = 0; | |
3366 | ||
6aa8b732 AK |
3367 | out: |
3368 | return ret; | |
3369 | } | |
3370 | ||
3b86cd99 JK |
3371 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
3372 | { | |
3373 | u32 cpu_based_vm_exec_control; | |
3374 | ||
3375 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
3376 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; | |
3377 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
3378 | } | |
3379 | ||
3380 | static void enable_nmi_window(struct kvm_vcpu *vcpu) | |
3381 | { | |
3382 | u32 cpu_based_vm_exec_control; | |
3383 | ||
3384 | if (!cpu_has_virtual_nmis()) { | |
3385 | enable_irq_window(vcpu); | |
3386 | return; | |
3387 | } | |
3388 | ||
30bd0c4c AK |
3389 | if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { |
3390 | enable_irq_window(vcpu); | |
3391 | return; | |
3392 | } | |
3b86cd99 JK |
3393 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); |
3394 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING; | |
3395 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
3396 | } | |
3397 | ||
66fd3f7f | 3398 | static void vmx_inject_irq(struct kvm_vcpu *vcpu) |
85f455f7 | 3399 | { |
9c8cba37 | 3400 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
66fd3f7f GN |
3401 | uint32_t intr; |
3402 | int irq = vcpu->arch.interrupt.nr; | |
9c8cba37 | 3403 | |
229456fc | 3404 | trace_kvm_inj_virq(irq); |
2714d1d3 | 3405 | |
fa89a817 | 3406 | ++vcpu->stat.irq_injections; |
7ffd92c5 | 3407 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
3408 | int inc_eip = 0; |
3409 | if (vcpu->arch.interrupt.soft) | |
3410 | inc_eip = vcpu->arch.event_exit_inst_len; | |
3411 | if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE) | |
a92601bb | 3412 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
85f455f7 ED |
3413 | return; |
3414 | } | |
66fd3f7f GN |
3415 | intr = irq | INTR_INFO_VALID_MASK; |
3416 | if (vcpu->arch.interrupt.soft) { | |
3417 | intr |= INTR_TYPE_SOFT_INTR; | |
3418 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
3419 | vmx->vcpu.arch.event_exit_inst_len); | |
3420 | } else | |
3421 | intr |= INTR_TYPE_EXT_INTR; | |
3422 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); | |
443381a8 | 3423 | vmx_clear_hlt(vcpu); |
85f455f7 ED |
3424 | } |
3425 | ||
f08864b4 SY |
3426 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
3427 | { | |
66a5a347 JK |
3428 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3429 | ||
3b86cd99 JK |
3430 | if (!cpu_has_virtual_nmis()) { |
3431 | /* | |
3432 | * Tracking the NMI-blocked state in software is built upon | |
3433 | * finding the next open IRQ window. This, in turn, depends on | |
3434 | * well-behaving guests: They have to keep IRQs disabled at | |
3435 | * least as long as the NMI handler runs. Otherwise we may | |
3436 | * cause NMI nesting, maybe breaking the guest. But as this is | |
3437 | * highly unlikely, we can live with the residual risk. | |
3438 | */ | |
3439 | vmx->soft_vnmi_blocked = 1; | |
3440 | vmx->vnmi_blocked_time = 0; | |
3441 | } | |
3442 | ||
487b391d | 3443 | ++vcpu->stat.nmi_injections; |
9d58b931 | 3444 | vmx->nmi_known_unmasked = false; |
7ffd92c5 | 3445 | if (vmx->rmode.vm86_active) { |
71f9833b | 3446 | if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE) |
a92601bb | 3447 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
66a5a347 JK |
3448 | return; |
3449 | } | |
f08864b4 SY |
3450 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
3451 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
443381a8 | 3452 | vmx_clear_hlt(vcpu); |
f08864b4 SY |
3453 | } |
3454 | ||
c4282df9 | 3455 | static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) |
33f089ca | 3456 | { |
3b86cd99 | 3457 | if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked) |
c4282df9 | 3458 | return 0; |
33f089ca | 3459 | |
c4282df9 | 3460 | return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
30bd0c4c AK |
3461 | (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI |
3462 | | GUEST_INTR_STATE_NMI)); | |
33f089ca JK |
3463 | } |
3464 | ||
3cfc3092 JK |
3465 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) |
3466 | { | |
3467 | if (!cpu_has_virtual_nmis()) | |
3468 | return to_vmx(vcpu)->soft_vnmi_blocked; | |
9d58b931 AK |
3469 | if (to_vmx(vcpu)->nmi_known_unmasked) |
3470 | return false; | |
c332c83a | 3471 | return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; |
3cfc3092 JK |
3472 | } |
3473 | ||
3474 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
3475 | { | |
3476 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
3477 | ||
3478 | if (!cpu_has_virtual_nmis()) { | |
3479 | if (vmx->soft_vnmi_blocked != masked) { | |
3480 | vmx->soft_vnmi_blocked = masked; | |
3481 | vmx->vnmi_blocked_time = 0; | |
3482 | } | |
3483 | } else { | |
9d58b931 | 3484 | vmx->nmi_known_unmasked = !masked; |
3cfc3092 JK |
3485 | if (masked) |
3486 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
3487 | GUEST_INTR_STATE_NMI); | |
3488 | else | |
3489 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
3490 | GUEST_INTR_STATE_NMI); | |
3491 | } | |
3492 | } | |
3493 | ||
78646121 GN |
3494 | static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) |
3495 | { | |
c4282df9 GN |
3496 | return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && |
3497 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & | |
3498 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); | |
78646121 GN |
3499 | } |
3500 | ||
cbc94022 IE |
3501 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
3502 | { | |
3503 | int ret; | |
3504 | struct kvm_userspace_memory_region tss_mem = { | |
6fe63979 | 3505 | .slot = TSS_PRIVATE_MEMSLOT, |
cbc94022 IE |
3506 | .guest_phys_addr = addr, |
3507 | .memory_size = PAGE_SIZE * 3, | |
3508 | .flags = 0, | |
3509 | }; | |
3510 | ||
3511 | ret = kvm_set_memory_region(kvm, &tss_mem, 0); | |
3512 | if (ret) | |
3513 | return ret; | |
bfc6d222 | 3514 | kvm->arch.tss_addr = addr; |
93ea5388 GN |
3515 | if (!init_rmode_tss(kvm)) |
3516 | return -ENOMEM; | |
3517 | ||
cbc94022 IE |
3518 | return 0; |
3519 | } | |
3520 | ||
6aa8b732 AK |
3521 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, |
3522 | int vec, u32 err_code) | |
3523 | { | |
b3f37707 NK |
3524 | /* |
3525 | * Instruction with address size override prefix opcode 0x67 | |
3526 | * Cause the #SS fault with 0 error code in VM86 mode. | |
3527 | */ | |
3528 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) | |
51d8b661 | 3529 | if (emulate_instruction(vcpu, 0) == EMULATE_DONE) |
6aa8b732 | 3530 | return 1; |
77ab6db0 JK |
3531 | /* |
3532 | * Forward all other exceptions that are valid in real mode. | |
3533 | * FIXME: Breaks guest debugging in real mode, needs to be fixed with | |
3534 | * the required debugging infrastructure rework. | |
3535 | */ | |
3536 | switch (vec) { | |
77ab6db0 | 3537 | case DB_VECTOR: |
d0bfb940 JK |
3538 | if (vcpu->guest_debug & |
3539 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
3540 | return 0; | |
3541 | kvm_queue_exception(vcpu, vec); | |
3542 | return 1; | |
77ab6db0 | 3543 | case BP_VECTOR: |
c573cd22 JK |
3544 | /* |
3545 | * Update instruction length as we may reinject the exception | |
3546 | * from user space while in guest debugging mode. | |
3547 | */ | |
3548 | to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = | |
3549 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
d0bfb940 JK |
3550 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
3551 | return 0; | |
3552 | /* fall through */ | |
3553 | case DE_VECTOR: | |
77ab6db0 JK |
3554 | case OF_VECTOR: |
3555 | case BR_VECTOR: | |
3556 | case UD_VECTOR: | |
3557 | case DF_VECTOR: | |
3558 | case SS_VECTOR: | |
3559 | case GP_VECTOR: | |
3560 | case MF_VECTOR: | |
3561 | kvm_queue_exception(vcpu, vec); | |
3562 | return 1; | |
3563 | } | |
6aa8b732 AK |
3564 | return 0; |
3565 | } | |
3566 | ||
a0861c02 AK |
3567 | /* |
3568 | * Trigger machine check on the host. We assume all the MSRs are already set up | |
3569 | * by the CPU and that we still run on the same CPU as the MCE occurred on. | |
3570 | * We pass a fake environment to the machine check handler because we want | |
3571 | * the guest to be always treated like user space, no matter what context | |
3572 | * it used internally. | |
3573 | */ | |
3574 | static void kvm_machine_check(void) | |
3575 | { | |
3576 | #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) | |
3577 | struct pt_regs regs = { | |
3578 | .cs = 3, /* Fake ring 3 no matter what the guest ran on */ | |
3579 | .flags = X86_EFLAGS_IF, | |
3580 | }; | |
3581 | ||
3582 | do_machine_check(®s, 0); | |
3583 | #endif | |
3584 | } | |
3585 | ||
851ba692 | 3586 | static int handle_machine_check(struct kvm_vcpu *vcpu) |
a0861c02 AK |
3587 | { |
3588 | /* already handled by vcpu_run */ | |
3589 | return 1; | |
3590 | } | |
3591 | ||
851ba692 | 3592 | static int handle_exception(struct kvm_vcpu *vcpu) |
6aa8b732 | 3593 | { |
1155f76a | 3594 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
851ba692 | 3595 | struct kvm_run *kvm_run = vcpu->run; |
d0bfb940 | 3596 | u32 intr_info, ex_no, error_code; |
42dbaa5a | 3597 | unsigned long cr2, rip, dr6; |
6aa8b732 AK |
3598 | u32 vect_info; |
3599 | enum emulation_result er; | |
3600 | ||
1155f76a | 3601 | vect_info = vmx->idt_vectoring_info; |
88786475 | 3602 | intr_info = vmx->exit_intr_info; |
6aa8b732 | 3603 | |
a0861c02 | 3604 | if (is_machine_check(intr_info)) |
851ba692 | 3605 | return handle_machine_check(vcpu); |
a0861c02 | 3606 | |
6aa8b732 | 3607 | if ((vect_info & VECTORING_INFO_VALID_MASK) && |
65ac7264 AK |
3608 | !is_page_fault(intr_info)) { |
3609 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
3610 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; | |
3611 | vcpu->run->internal.ndata = 2; | |
3612 | vcpu->run->internal.data[0] = vect_info; | |
3613 | vcpu->run->internal.data[1] = intr_info; | |
3614 | return 0; | |
3615 | } | |
6aa8b732 | 3616 | |
e4a41889 | 3617 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR) |
1b6269db | 3618 | return 1; /* already handled by vmx_vcpu_run() */ |
2ab455cc AL |
3619 | |
3620 | if (is_no_device(intr_info)) { | |
5fd86fcf | 3621 | vmx_fpu_activate(vcpu); |
2ab455cc AL |
3622 | return 1; |
3623 | } | |
3624 | ||
7aa81cc0 | 3625 | if (is_invalid_opcode(intr_info)) { |
51d8b661 | 3626 | er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 3627 | if (er != EMULATE_DONE) |
7ee5d940 | 3628 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
3629 | return 1; |
3630 | } | |
3631 | ||
6aa8b732 | 3632 | error_code = 0; |
2e11384c | 3633 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 AK |
3634 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
3635 | if (is_page_fault(intr_info)) { | |
1439442c | 3636 | /* EPT won't cause page fault directly */ |
089d034e | 3637 | if (enable_ept) |
1439442c | 3638 | BUG(); |
6aa8b732 | 3639 | cr2 = vmcs_readl(EXIT_QUALIFICATION); |
229456fc MT |
3640 | trace_kvm_page_fault(cr2, error_code); |
3641 | ||
3298b75c | 3642 | if (kvm_event_needs_reinjection(vcpu)) |
577bdc49 | 3643 | kvm_mmu_unprotect_page_virt(vcpu, cr2); |
dc25e89e | 3644 | return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0); |
6aa8b732 AK |
3645 | } |
3646 | ||
7ffd92c5 | 3647 | if (vmx->rmode.vm86_active && |
6aa8b732 | 3648 | handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK, |
72d6e5a0 | 3649 | error_code)) { |
ad312c7c ZX |
3650 | if (vcpu->arch.halt_request) { |
3651 | vcpu->arch.halt_request = 0; | |
72d6e5a0 AK |
3652 | return kvm_emulate_halt(vcpu); |
3653 | } | |
6aa8b732 | 3654 | return 1; |
72d6e5a0 | 3655 | } |
6aa8b732 | 3656 | |
d0bfb940 | 3657 | ex_no = intr_info & INTR_INFO_VECTOR_MASK; |
42dbaa5a JK |
3658 | switch (ex_no) { |
3659 | case DB_VECTOR: | |
3660 | dr6 = vmcs_readl(EXIT_QUALIFICATION); | |
3661 | if (!(vcpu->guest_debug & | |
3662 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { | |
3663 | vcpu->arch.dr6 = dr6 | DR6_FIXED_1; | |
3664 | kvm_queue_exception(vcpu, DB_VECTOR); | |
3665 | return 1; | |
3666 | } | |
3667 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; | |
3668 | kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); | |
3669 | /* fall through */ | |
3670 | case BP_VECTOR: | |
c573cd22 JK |
3671 | /* |
3672 | * Update instruction length as we may reinject #BP from | |
3673 | * user space while in guest debugging mode. Reading it for | |
3674 | * #DB as well causes no harm, it is not used in that case. | |
3675 | */ | |
3676 | vmx->vcpu.arch.event_exit_inst_len = | |
3677 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
6aa8b732 | 3678 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
0a434bb2 | 3679 | rip = kvm_rip_read(vcpu); |
d0bfb940 JK |
3680 | kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; |
3681 | kvm_run->debug.arch.exception = ex_no; | |
42dbaa5a JK |
3682 | break; |
3683 | default: | |
d0bfb940 JK |
3684 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; |
3685 | kvm_run->ex.exception = ex_no; | |
3686 | kvm_run->ex.error_code = error_code; | |
42dbaa5a | 3687 | break; |
6aa8b732 | 3688 | } |
6aa8b732 AK |
3689 | return 0; |
3690 | } | |
3691 | ||
851ba692 | 3692 | static int handle_external_interrupt(struct kvm_vcpu *vcpu) |
6aa8b732 | 3693 | { |
1165f5fe | 3694 | ++vcpu->stat.irq_exits; |
6aa8b732 AK |
3695 | return 1; |
3696 | } | |
3697 | ||
851ba692 | 3698 | static int handle_triple_fault(struct kvm_vcpu *vcpu) |
988ad74f | 3699 | { |
851ba692 | 3700 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
988ad74f AK |
3701 | return 0; |
3702 | } | |
6aa8b732 | 3703 | |
851ba692 | 3704 | static int handle_io(struct kvm_vcpu *vcpu) |
6aa8b732 | 3705 | { |
bfdaab09 | 3706 | unsigned long exit_qualification; |
34c33d16 | 3707 | int size, in, string; |
039576c0 | 3708 | unsigned port; |
6aa8b732 | 3709 | |
bfdaab09 | 3710 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 3711 | string = (exit_qualification & 16) != 0; |
cf8f70bf | 3712 | in = (exit_qualification & 8) != 0; |
e70669ab | 3713 | |
cf8f70bf | 3714 | ++vcpu->stat.io_exits; |
e70669ab | 3715 | |
cf8f70bf | 3716 | if (string || in) |
51d8b661 | 3717 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
e70669ab | 3718 | |
cf8f70bf GN |
3719 | port = exit_qualification >> 16; |
3720 | size = (exit_qualification & 7) + 1; | |
e93f36bc | 3721 | skip_emulated_instruction(vcpu); |
cf8f70bf GN |
3722 | |
3723 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
3724 | } |
3725 | ||
102d8325 IM |
3726 | static void |
3727 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
3728 | { | |
3729 | /* | |
3730 | * Patch in the VMCALL instruction: | |
3731 | */ | |
3732 | hypercall[0] = 0x0f; | |
3733 | hypercall[1] = 0x01; | |
3734 | hypercall[2] = 0xc1; | |
102d8325 IM |
3735 | } |
3736 | ||
851ba692 | 3737 | static int handle_cr(struct kvm_vcpu *vcpu) |
6aa8b732 | 3738 | { |
229456fc | 3739 | unsigned long exit_qualification, val; |
6aa8b732 AK |
3740 | int cr; |
3741 | int reg; | |
49a9b07e | 3742 | int err; |
6aa8b732 | 3743 | |
bfdaab09 | 3744 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
3745 | cr = exit_qualification & 15; |
3746 | reg = (exit_qualification >> 8) & 15; | |
3747 | switch ((exit_qualification >> 4) & 3) { | |
3748 | case 0: /* mov to cr */ | |
229456fc MT |
3749 | val = kvm_register_read(vcpu, reg); |
3750 | trace_kvm_cr_write(cr, val); | |
6aa8b732 AK |
3751 | switch (cr) { |
3752 | case 0: | |
49a9b07e | 3753 | err = kvm_set_cr0(vcpu, val); |
db8fcefa | 3754 | kvm_complete_insn_gp(vcpu, err); |
6aa8b732 AK |
3755 | return 1; |
3756 | case 3: | |
2390218b | 3757 | err = kvm_set_cr3(vcpu, val); |
db8fcefa | 3758 | kvm_complete_insn_gp(vcpu, err); |
6aa8b732 AK |
3759 | return 1; |
3760 | case 4: | |
a83b29c6 | 3761 | err = kvm_set_cr4(vcpu, val); |
db8fcefa | 3762 | kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 3763 | return 1; |
0a5fff19 GN |
3764 | case 8: { |
3765 | u8 cr8_prev = kvm_get_cr8(vcpu); | |
3766 | u8 cr8 = kvm_register_read(vcpu, reg); | |
eea1cff9 | 3767 | err = kvm_set_cr8(vcpu, cr8); |
db8fcefa | 3768 | kvm_complete_insn_gp(vcpu, err); |
0a5fff19 GN |
3769 | if (irqchip_in_kernel(vcpu->kvm)) |
3770 | return 1; | |
3771 | if (cr8_prev <= cr8) | |
3772 | return 1; | |
851ba692 | 3773 | vcpu->run->exit_reason = KVM_EXIT_SET_TPR; |
0a5fff19 GN |
3774 | return 0; |
3775 | } | |
6aa8b732 AK |
3776 | }; |
3777 | break; | |
25c4c276 | 3778 | case 2: /* clts */ |
edcafe3c | 3779 | vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); |
4d4ec087 | 3780 | trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); |
25c4c276 | 3781 | skip_emulated_instruction(vcpu); |
6b52d186 | 3782 | vmx_fpu_activate(vcpu); |
25c4c276 | 3783 | return 1; |
6aa8b732 AK |
3784 | case 1: /*mov from cr*/ |
3785 | switch (cr) { | |
3786 | case 3: | |
9f8fe504 AK |
3787 | val = kvm_read_cr3(vcpu); |
3788 | kvm_register_write(vcpu, reg, val); | |
3789 | trace_kvm_cr_read(cr, val); | |
6aa8b732 AK |
3790 | skip_emulated_instruction(vcpu); |
3791 | return 1; | |
3792 | case 8: | |
229456fc MT |
3793 | val = kvm_get_cr8(vcpu); |
3794 | kvm_register_write(vcpu, reg, val); | |
3795 | trace_kvm_cr_read(cr, val); | |
6aa8b732 AK |
3796 | skip_emulated_instruction(vcpu); |
3797 | return 1; | |
3798 | } | |
3799 | break; | |
3800 | case 3: /* lmsw */ | |
a1f83a74 | 3801 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
4d4ec087 | 3802 | trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); |
a1f83a74 | 3803 | kvm_lmsw(vcpu, val); |
6aa8b732 AK |
3804 | |
3805 | skip_emulated_instruction(vcpu); | |
3806 | return 1; | |
3807 | default: | |
3808 | break; | |
3809 | } | |
851ba692 | 3810 | vcpu->run->exit_reason = 0; |
f0242478 | 3811 | pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
3812 | (int)(exit_qualification >> 4) & 3, cr); |
3813 | return 0; | |
3814 | } | |
3815 | ||
851ba692 | 3816 | static int handle_dr(struct kvm_vcpu *vcpu) |
6aa8b732 | 3817 | { |
bfdaab09 | 3818 | unsigned long exit_qualification; |
6aa8b732 AK |
3819 | int dr, reg; |
3820 | ||
f2483415 | 3821 | /* Do not handle if the CPL > 0, will trigger GP on re-entry */ |
0a79b009 AK |
3822 | if (!kvm_require_cpl(vcpu, 0)) |
3823 | return 1; | |
42dbaa5a JK |
3824 | dr = vmcs_readl(GUEST_DR7); |
3825 | if (dr & DR7_GD) { | |
3826 | /* | |
3827 | * As the vm-exit takes precedence over the debug trap, we | |
3828 | * need to emulate the latter, either for the host or the | |
3829 | * guest debugging itself. | |
3830 | */ | |
3831 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
851ba692 AK |
3832 | vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; |
3833 | vcpu->run->debug.arch.dr7 = dr; | |
3834 | vcpu->run->debug.arch.pc = | |
42dbaa5a JK |
3835 | vmcs_readl(GUEST_CS_BASE) + |
3836 | vmcs_readl(GUEST_RIP); | |
851ba692 AK |
3837 | vcpu->run->debug.arch.exception = DB_VECTOR; |
3838 | vcpu->run->exit_reason = KVM_EXIT_DEBUG; | |
42dbaa5a JK |
3839 | return 0; |
3840 | } else { | |
3841 | vcpu->arch.dr7 &= ~DR7_GD; | |
3842 | vcpu->arch.dr6 |= DR6_BD; | |
3843 | vmcs_writel(GUEST_DR7, vcpu->arch.dr7); | |
3844 | kvm_queue_exception(vcpu, DB_VECTOR); | |
3845 | return 1; | |
3846 | } | |
3847 | } | |
3848 | ||
bfdaab09 | 3849 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
42dbaa5a JK |
3850 | dr = exit_qualification & DEBUG_REG_ACCESS_NUM; |
3851 | reg = DEBUG_REG_ACCESS_REG(exit_qualification); | |
3852 | if (exit_qualification & TYPE_MOV_FROM_DR) { | |
020df079 GN |
3853 | unsigned long val; |
3854 | if (!kvm_get_dr(vcpu, dr, &val)) | |
3855 | kvm_register_write(vcpu, reg, val); | |
3856 | } else | |
3857 | kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]); | |
6aa8b732 AK |
3858 | skip_emulated_instruction(vcpu); |
3859 | return 1; | |
3860 | } | |
3861 | ||
020df079 GN |
3862 | static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) |
3863 | { | |
3864 | vmcs_writel(GUEST_DR7, val); | |
3865 | } | |
3866 | ||
851ba692 | 3867 | static int handle_cpuid(struct kvm_vcpu *vcpu) |
6aa8b732 | 3868 | { |
06465c5a AK |
3869 | kvm_emulate_cpuid(vcpu); |
3870 | return 1; | |
6aa8b732 AK |
3871 | } |
3872 | ||
851ba692 | 3873 | static int handle_rdmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 3874 | { |
ad312c7c | 3875 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
3876 | u64 data; |
3877 | ||
3878 | if (vmx_get_msr(vcpu, ecx, &data)) { | |
59200273 | 3879 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 3880 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
3881 | return 1; |
3882 | } | |
3883 | ||
229456fc | 3884 | trace_kvm_msr_read(ecx, data); |
2714d1d3 | 3885 | |
6aa8b732 | 3886 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
ad312c7c ZX |
3887 | vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u; |
3888 | vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u; | |
6aa8b732 AK |
3889 | skip_emulated_instruction(vcpu); |
3890 | return 1; | |
3891 | } | |
3892 | ||
851ba692 | 3893 | static int handle_wrmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 3894 | { |
ad312c7c ZX |
3895 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
3896 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
3897 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 AK |
3898 | |
3899 | if (vmx_set_msr(vcpu, ecx, data) != 0) { | |
59200273 | 3900 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 3901 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
3902 | return 1; |
3903 | } | |
3904 | ||
59200273 | 3905 | trace_kvm_msr_write(ecx, data); |
6aa8b732 AK |
3906 | skip_emulated_instruction(vcpu); |
3907 | return 1; | |
3908 | } | |
3909 | ||
851ba692 | 3910 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) |
6e5d865c | 3911 | { |
3842d135 | 3912 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6e5d865c YS |
3913 | return 1; |
3914 | } | |
3915 | ||
851ba692 | 3916 | static int handle_interrupt_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 3917 | { |
85f455f7 ED |
3918 | u32 cpu_based_vm_exec_control; |
3919 | ||
3920 | /* clear pending irq */ | |
3921 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
3922 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
3923 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2714d1d3 | 3924 | |
3842d135 AK |
3925 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3926 | ||
a26bf12a | 3927 | ++vcpu->stat.irq_window_exits; |
2714d1d3 | 3928 | |
c1150d8c DL |
3929 | /* |
3930 | * If the user space waits to inject interrupts, exit as soon as | |
3931 | * possible | |
3932 | */ | |
8061823a | 3933 | if (!irqchip_in_kernel(vcpu->kvm) && |
851ba692 | 3934 | vcpu->run->request_interrupt_window && |
8061823a | 3935 | !kvm_cpu_has_interrupt(vcpu)) { |
851ba692 | 3936 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
c1150d8c DL |
3937 | return 0; |
3938 | } | |
6aa8b732 AK |
3939 | return 1; |
3940 | } | |
3941 | ||
851ba692 | 3942 | static int handle_halt(struct kvm_vcpu *vcpu) |
6aa8b732 AK |
3943 | { |
3944 | skip_emulated_instruction(vcpu); | |
d3bef15f | 3945 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
3946 | } |
3947 | ||
851ba692 | 3948 | static int handle_vmcall(struct kvm_vcpu *vcpu) |
c21415e8 | 3949 | { |
510043da | 3950 | skip_emulated_instruction(vcpu); |
7aa81cc0 AL |
3951 | kvm_emulate_hypercall(vcpu); |
3952 | return 1; | |
c21415e8 IM |
3953 | } |
3954 | ||
851ba692 | 3955 | static int handle_vmx_insn(struct kvm_vcpu *vcpu) |
e3c7cb6a AK |
3956 | { |
3957 | kvm_queue_exception(vcpu, UD_VECTOR); | |
3958 | return 1; | |
3959 | } | |
3960 | ||
ec25d5e6 GN |
3961 | static int handle_invd(struct kvm_vcpu *vcpu) |
3962 | { | |
51d8b661 | 3963 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
ec25d5e6 GN |
3964 | } |
3965 | ||
851ba692 | 3966 | static int handle_invlpg(struct kvm_vcpu *vcpu) |
a7052897 | 3967 | { |
f9c617f6 | 3968 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
a7052897 MT |
3969 | |
3970 | kvm_mmu_invlpg(vcpu, exit_qualification); | |
3971 | skip_emulated_instruction(vcpu); | |
3972 | return 1; | |
3973 | } | |
3974 | ||
851ba692 | 3975 | static int handle_wbinvd(struct kvm_vcpu *vcpu) |
e5edaa01 ED |
3976 | { |
3977 | skip_emulated_instruction(vcpu); | |
f5f48ee1 | 3978 | kvm_emulate_wbinvd(vcpu); |
e5edaa01 ED |
3979 | return 1; |
3980 | } | |
3981 | ||
2acf923e DC |
3982 | static int handle_xsetbv(struct kvm_vcpu *vcpu) |
3983 | { | |
3984 | u64 new_bv = kvm_read_edx_eax(vcpu); | |
3985 | u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
3986 | ||
3987 | if (kvm_set_xcr(vcpu, index, new_bv) == 0) | |
3988 | skip_emulated_instruction(vcpu); | |
3989 | return 1; | |
3990 | } | |
3991 | ||
851ba692 | 3992 | static int handle_apic_access(struct kvm_vcpu *vcpu) |
f78e0e2e | 3993 | { |
51d8b661 | 3994 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
f78e0e2e SY |
3995 | } |
3996 | ||
851ba692 | 3997 | static int handle_task_switch(struct kvm_vcpu *vcpu) |
37817f29 | 3998 | { |
60637aac | 3999 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
37817f29 | 4000 | unsigned long exit_qualification; |
e269fb21 JK |
4001 | bool has_error_code = false; |
4002 | u32 error_code = 0; | |
37817f29 | 4003 | u16 tss_selector; |
64a7ec06 GN |
4004 | int reason, type, idt_v; |
4005 | ||
4006 | idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | |
4007 | type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); | |
37817f29 IE |
4008 | |
4009 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
4010 | ||
4011 | reason = (u32)exit_qualification >> 30; | |
64a7ec06 GN |
4012 | if (reason == TASK_SWITCH_GATE && idt_v) { |
4013 | switch (type) { | |
4014 | case INTR_TYPE_NMI_INTR: | |
4015 | vcpu->arch.nmi_injected = false; | |
654f06fc | 4016 | vmx_set_nmi_mask(vcpu, true); |
64a7ec06 GN |
4017 | break; |
4018 | case INTR_TYPE_EXT_INTR: | |
66fd3f7f | 4019 | case INTR_TYPE_SOFT_INTR: |
64a7ec06 GN |
4020 | kvm_clear_interrupt_queue(vcpu); |
4021 | break; | |
4022 | case INTR_TYPE_HARD_EXCEPTION: | |
e269fb21 JK |
4023 | if (vmx->idt_vectoring_info & |
4024 | VECTORING_INFO_DELIVER_CODE_MASK) { | |
4025 | has_error_code = true; | |
4026 | error_code = | |
4027 | vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
4028 | } | |
4029 | /* fall through */ | |
64a7ec06 GN |
4030 | case INTR_TYPE_SOFT_EXCEPTION: |
4031 | kvm_clear_exception_queue(vcpu); | |
4032 | break; | |
4033 | default: | |
4034 | break; | |
4035 | } | |
60637aac | 4036 | } |
37817f29 IE |
4037 | tss_selector = exit_qualification; |
4038 | ||
64a7ec06 GN |
4039 | if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && |
4040 | type != INTR_TYPE_EXT_INTR && | |
4041 | type != INTR_TYPE_NMI_INTR)) | |
4042 | skip_emulated_instruction(vcpu); | |
4043 | ||
acb54517 GN |
4044 | if (kvm_task_switch(vcpu, tss_selector, reason, |
4045 | has_error_code, error_code) == EMULATE_FAIL) { | |
4046 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
4047 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
4048 | vcpu->run->internal.ndata = 0; | |
42dbaa5a | 4049 | return 0; |
acb54517 | 4050 | } |
42dbaa5a JK |
4051 | |
4052 | /* clear all local breakpoint enable flags */ | |
4053 | vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55); | |
4054 | ||
4055 | /* | |
4056 | * TODO: What about debug traps on tss switch? | |
4057 | * Are we supposed to inject them and update dr6? | |
4058 | */ | |
4059 | ||
4060 | return 1; | |
37817f29 IE |
4061 | } |
4062 | ||
851ba692 | 4063 | static int handle_ept_violation(struct kvm_vcpu *vcpu) |
1439442c | 4064 | { |
f9c617f6 | 4065 | unsigned long exit_qualification; |
1439442c | 4066 | gpa_t gpa; |
1439442c | 4067 | int gla_validity; |
1439442c | 4068 | |
f9c617f6 | 4069 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
1439442c SY |
4070 | |
4071 | if (exit_qualification & (1 << 6)) { | |
4072 | printk(KERN_ERR "EPT: GPA exceeds GAW!\n"); | |
7f582ab6 | 4073 | return -EINVAL; |
1439442c SY |
4074 | } |
4075 | ||
4076 | gla_validity = (exit_qualification >> 7) & 0x3; | |
4077 | if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) { | |
4078 | printk(KERN_ERR "EPT: Handling EPT violation failed!\n"); | |
4079 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | |
4080 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | |
f9c617f6 | 4081 | vmcs_readl(GUEST_LINEAR_ADDRESS)); |
1439442c SY |
4082 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", |
4083 | (long unsigned int)exit_qualification); | |
851ba692 AK |
4084 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
4085 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION; | |
596ae895 | 4086 | return 0; |
1439442c SY |
4087 | } |
4088 | ||
4089 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
229456fc | 4090 | trace_kvm_page_fault(gpa, exit_qualification); |
dc25e89e | 4091 | return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0); |
1439442c SY |
4092 | } |
4093 | ||
68f89400 MT |
4094 | static u64 ept_rsvd_mask(u64 spte, int level) |
4095 | { | |
4096 | int i; | |
4097 | u64 mask = 0; | |
4098 | ||
4099 | for (i = 51; i > boot_cpu_data.x86_phys_bits; i--) | |
4100 | mask |= (1ULL << i); | |
4101 | ||
4102 | if (level > 2) | |
4103 | /* bits 7:3 reserved */ | |
4104 | mask |= 0xf8; | |
4105 | else if (level == 2) { | |
4106 | if (spte & (1ULL << 7)) | |
4107 | /* 2MB ref, bits 20:12 reserved */ | |
4108 | mask |= 0x1ff000; | |
4109 | else | |
4110 | /* bits 6:3 reserved */ | |
4111 | mask |= 0x78; | |
4112 | } | |
4113 | ||
4114 | return mask; | |
4115 | } | |
4116 | ||
4117 | static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte, | |
4118 | int level) | |
4119 | { | |
4120 | printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level); | |
4121 | ||
4122 | /* 010b (write-only) */ | |
4123 | WARN_ON((spte & 0x7) == 0x2); | |
4124 | ||
4125 | /* 110b (write/execute) */ | |
4126 | WARN_ON((spte & 0x7) == 0x6); | |
4127 | ||
4128 | /* 100b (execute-only) and value not supported by logical processor */ | |
4129 | if (!cpu_has_vmx_ept_execute_only()) | |
4130 | WARN_ON((spte & 0x7) == 0x4); | |
4131 | ||
4132 | /* not 000b */ | |
4133 | if ((spte & 0x7)) { | |
4134 | u64 rsvd_bits = spte & ept_rsvd_mask(spte, level); | |
4135 | ||
4136 | if (rsvd_bits != 0) { | |
4137 | printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n", | |
4138 | __func__, rsvd_bits); | |
4139 | WARN_ON(1); | |
4140 | } | |
4141 | ||
4142 | if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) { | |
4143 | u64 ept_mem_type = (spte & 0x38) >> 3; | |
4144 | ||
4145 | if (ept_mem_type == 2 || ept_mem_type == 3 || | |
4146 | ept_mem_type == 7) { | |
4147 | printk(KERN_ERR "%s: ept_mem_type=0x%llx\n", | |
4148 | __func__, ept_mem_type); | |
4149 | WARN_ON(1); | |
4150 | } | |
4151 | } | |
4152 | } | |
4153 | } | |
4154 | ||
851ba692 | 4155 | static int handle_ept_misconfig(struct kvm_vcpu *vcpu) |
68f89400 MT |
4156 | { |
4157 | u64 sptes[4]; | |
4158 | int nr_sptes, i; | |
4159 | gpa_t gpa; | |
4160 | ||
4161 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
4162 | ||
4163 | printk(KERN_ERR "EPT: Misconfiguration.\n"); | |
4164 | printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa); | |
4165 | ||
4166 | nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes); | |
4167 | ||
4168 | for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i) | |
4169 | ept_misconfig_inspect_spte(vcpu, sptes[i-1], i); | |
4170 | ||
851ba692 AK |
4171 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
4172 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG; | |
68f89400 MT |
4173 | |
4174 | return 0; | |
4175 | } | |
4176 | ||
851ba692 | 4177 | static int handle_nmi_window(struct kvm_vcpu *vcpu) |
f08864b4 SY |
4178 | { |
4179 | u32 cpu_based_vm_exec_control; | |
4180 | ||
4181 | /* clear pending NMI */ | |
4182 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
4183 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
4184 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
4185 | ++vcpu->stat.nmi_window_exits; | |
3842d135 | 4186 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f08864b4 SY |
4187 | |
4188 | return 1; | |
4189 | } | |
4190 | ||
80ced186 | 4191 | static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) |
ea953ef0 | 4192 | { |
8b3079a5 AK |
4193 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4194 | enum emulation_result err = EMULATE_DONE; | |
80ced186 | 4195 | int ret = 1; |
49e9d557 AK |
4196 | u32 cpu_exec_ctrl; |
4197 | bool intr_window_requested; | |
4198 | ||
4199 | cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
4200 | intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING; | |
ea953ef0 MG |
4201 | |
4202 | while (!guest_state_valid(vcpu)) { | |
49e9d557 AK |
4203 | if (intr_window_requested |
4204 | && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF)) | |
4205 | return handle_interrupt_window(&vmx->vcpu); | |
4206 | ||
51d8b661 | 4207 | err = emulate_instruction(vcpu, 0); |
ea953ef0 | 4208 | |
80ced186 MG |
4209 | if (err == EMULATE_DO_MMIO) { |
4210 | ret = 0; | |
4211 | goto out; | |
4212 | } | |
1d5a4d9b | 4213 | |
6d77dbfc GN |
4214 | if (err != EMULATE_DONE) |
4215 | return 0; | |
ea953ef0 MG |
4216 | |
4217 | if (signal_pending(current)) | |
80ced186 | 4218 | goto out; |
ea953ef0 MG |
4219 | if (need_resched()) |
4220 | schedule(); | |
4221 | } | |
4222 | ||
80ced186 MG |
4223 | vmx->emulation_required = 0; |
4224 | out: | |
4225 | return ret; | |
ea953ef0 MG |
4226 | } |
4227 | ||
4b8d54f9 ZE |
4228 | /* |
4229 | * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE | |
4230 | * exiting, so only get here on cpu with PAUSE-Loop-Exiting. | |
4231 | */ | |
9fb41ba8 | 4232 | static int handle_pause(struct kvm_vcpu *vcpu) |
4b8d54f9 ZE |
4233 | { |
4234 | skip_emulated_instruction(vcpu); | |
4235 | kvm_vcpu_on_spin(vcpu); | |
4236 | ||
4237 | return 1; | |
4238 | } | |
4239 | ||
59708670 SY |
4240 | static int handle_invalid_op(struct kvm_vcpu *vcpu) |
4241 | { | |
4242 | kvm_queue_exception(vcpu, UD_VECTOR); | |
4243 | return 1; | |
4244 | } | |
4245 | ||
ec378aee NHE |
4246 | /* |
4247 | * Emulate the VMXON instruction. | |
4248 | * Currently, we just remember that VMX is active, and do not save or even | |
4249 | * inspect the argument to VMXON (the so-called "VMXON pointer") because we | |
4250 | * do not currently need to store anything in that guest-allocated memory | |
4251 | * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their | |
4252 | * argument is different from the VMXON pointer (which the spec says they do). | |
4253 | */ | |
4254 | static int handle_vmon(struct kvm_vcpu *vcpu) | |
4255 | { | |
4256 | struct kvm_segment cs; | |
4257 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4258 | ||
4259 | /* The Intel VMX Instruction Reference lists a bunch of bits that | |
4260 | * are prerequisite to running VMXON, most notably cr4.VMXE must be | |
4261 | * set to 1 (see vmx_set_cr4() for when we allow the guest to set this). | |
4262 | * Otherwise, we should fail with #UD. We test these now: | |
4263 | */ | |
4264 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) || | |
4265 | !kvm_read_cr0_bits(vcpu, X86_CR0_PE) || | |
4266 | (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { | |
4267 | kvm_queue_exception(vcpu, UD_VECTOR); | |
4268 | return 1; | |
4269 | } | |
4270 | ||
4271 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
4272 | if (is_long_mode(vcpu) && !cs.l) { | |
4273 | kvm_queue_exception(vcpu, UD_VECTOR); | |
4274 | return 1; | |
4275 | } | |
4276 | ||
4277 | if (vmx_get_cpl(vcpu)) { | |
4278 | kvm_inject_gp(vcpu, 0); | |
4279 | return 1; | |
4280 | } | |
4281 | ||
4282 | vmx->nested.vmxon = true; | |
4283 | ||
4284 | skip_emulated_instruction(vcpu); | |
4285 | return 1; | |
4286 | } | |
4287 | ||
4288 | /* | |
4289 | * Intel's VMX Instruction Reference specifies a common set of prerequisites | |
4290 | * for running VMX instructions (except VMXON, whose prerequisites are | |
4291 | * slightly different). It also specifies what exception to inject otherwise. | |
4292 | */ | |
4293 | static int nested_vmx_check_permission(struct kvm_vcpu *vcpu) | |
4294 | { | |
4295 | struct kvm_segment cs; | |
4296 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4297 | ||
4298 | if (!vmx->nested.vmxon) { | |
4299 | kvm_queue_exception(vcpu, UD_VECTOR); | |
4300 | return 0; | |
4301 | } | |
4302 | ||
4303 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
4304 | if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) || | |
4305 | (is_long_mode(vcpu) && !cs.l)) { | |
4306 | kvm_queue_exception(vcpu, UD_VECTOR); | |
4307 | return 0; | |
4308 | } | |
4309 | ||
4310 | if (vmx_get_cpl(vcpu)) { | |
4311 | kvm_inject_gp(vcpu, 0); | |
4312 | return 0; | |
4313 | } | |
4314 | ||
4315 | return 1; | |
4316 | } | |
4317 | ||
4318 | /* | |
4319 | * Free whatever needs to be freed from vmx->nested when L1 goes down, or | |
4320 | * just stops using VMX. | |
4321 | */ | |
4322 | static void free_nested(struct vcpu_vmx *vmx) | |
4323 | { | |
4324 | if (!vmx->nested.vmxon) | |
4325 | return; | |
4326 | vmx->nested.vmxon = false; | |
a9d30f33 NHE |
4327 | if (vmx->nested.current_vmptr != -1ull) { |
4328 | kunmap(vmx->nested.current_vmcs12_page); | |
4329 | nested_release_page(vmx->nested.current_vmcs12_page); | |
4330 | vmx->nested.current_vmptr = -1ull; | |
4331 | vmx->nested.current_vmcs12 = NULL; | |
4332 | } | |
ec378aee NHE |
4333 | } |
4334 | ||
4335 | /* Emulate the VMXOFF instruction */ | |
4336 | static int handle_vmoff(struct kvm_vcpu *vcpu) | |
4337 | { | |
4338 | if (!nested_vmx_check_permission(vcpu)) | |
4339 | return 1; | |
4340 | free_nested(to_vmx(vcpu)); | |
4341 | skip_emulated_instruction(vcpu); | |
4342 | return 1; | |
4343 | } | |
4344 | ||
064aea77 NHE |
4345 | /* |
4346 | * Decode the memory-address operand of a vmx instruction, as recorded on an | |
4347 | * exit caused by such an instruction (run by a guest hypervisor). | |
4348 | * On success, returns 0. When the operand is invalid, returns 1 and throws | |
4349 | * #UD or #GP. | |
4350 | */ | |
4351 | static int get_vmx_mem_address(struct kvm_vcpu *vcpu, | |
4352 | unsigned long exit_qualification, | |
4353 | u32 vmx_instruction_info, gva_t *ret) | |
4354 | { | |
4355 | /* | |
4356 | * According to Vol. 3B, "Information for VM Exits Due to Instruction | |
4357 | * Execution", on an exit, vmx_instruction_info holds most of the | |
4358 | * addressing components of the operand. Only the displacement part | |
4359 | * is put in exit_qualification (see 3B, "Basic VM-Exit Information"). | |
4360 | * For how an actual address is calculated from all these components, | |
4361 | * refer to Vol. 1, "Operand Addressing". | |
4362 | */ | |
4363 | int scaling = vmx_instruction_info & 3; | |
4364 | int addr_size = (vmx_instruction_info >> 7) & 7; | |
4365 | bool is_reg = vmx_instruction_info & (1u << 10); | |
4366 | int seg_reg = (vmx_instruction_info >> 15) & 7; | |
4367 | int index_reg = (vmx_instruction_info >> 18) & 0xf; | |
4368 | bool index_is_valid = !(vmx_instruction_info & (1u << 22)); | |
4369 | int base_reg = (vmx_instruction_info >> 23) & 0xf; | |
4370 | bool base_is_valid = !(vmx_instruction_info & (1u << 27)); | |
4371 | ||
4372 | if (is_reg) { | |
4373 | kvm_queue_exception(vcpu, UD_VECTOR); | |
4374 | return 1; | |
4375 | } | |
4376 | ||
4377 | /* Addr = segment_base + offset */ | |
4378 | /* offset = base + [index * scale] + displacement */ | |
4379 | *ret = vmx_get_segment_base(vcpu, seg_reg); | |
4380 | if (base_is_valid) | |
4381 | *ret += kvm_register_read(vcpu, base_reg); | |
4382 | if (index_is_valid) | |
4383 | *ret += kvm_register_read(vcpu, index_reg)<<scaling; | |
4384 | *ret += exit_qualification; /* holds the displacement */ | |
4385 | ||
4386 | if (addr_size == 1) /* 32 bit */ | |
4387 | *ret &= 0xffffffff; | |
4388 | ||
4389 | /* | |
4390 | * TODO: throw #GP (and return 1) in various cases that the VM* | |
4391 | * instructions require it - e.g., offset beyond segment limit, | |
4392 | * unusable or unreadable/unwritable segment, non-canonical 64-bit | |
4393 | * address, and so on. Currently these are not checked. | |
4394 | */ | |
4395 | return 0; | |
4396 | } | |
4397 | ||
6aa8b732 AK |
4398 | /* |
4399 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
4400 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
4401 | * to be done to userspace and return 0. | |
4402 | */ | |
851ba692 | 4403 | static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { |
6aa8b732 AK |
4404 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, |
4405 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 4406 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
f08864b4 | 4407 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, |
6aa8b732 | 4408 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
4409 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
4410 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
4411 | [EXIT_REASON_CPUID] = handle_cpuid, | |
4412 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
4413 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
4414 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
4415 | [EXIT_REASON_HLT] = handle_halt, | |
ec25d5e6 | 4416 | [EXIT_REASON_INVD] = handle_invd, |
a7052897 | 4417 | [EXIT_REASON_INVLPG] = handle_invlpg, |
c21415e8 | 4418 | [EXIT_REASON_VMCALL] = handle_vmcall, |
e3c7cb6a AK |
4419 | [EXIT_REASON_VMCLEAR] = handle_vmx_insn, |
4420 | [EXIT_REASON_VMLAUNCH] = handle_vmx_insn, | |
4421 | [EXIT_REASON_VMPTRLD] = handle_vmx_insn, | |
4422 | [EXIT_REASON_VMPTRST] = handle_vmx_insn, | |
4423 | [EXIT_REASON_VMREAD] = handle_vmx_insn, | |
4424 | [EXIT_REASON_VMRESUME] = handle_vmx_insn, | |
4425 | [EXIT_REASON_VMWRITE] = handle_vmx_insn, | |
ec378aee NHE |
4426 | [EXIT_REASON_VMOFF] = handle_vmoff, |
4427 | [EXIT_REASON_VMON] = handle_vmon, | |
f78e0e2e SY |
4428 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
4429 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
e5edaa01 | 4430 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
2acf923e | 4431 | [EXIT_REASON_XSETBV] = handle_xsetbv, |
37817f29 | 4432 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
a0861c02 | 4433 | [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, |
68f89400 MT |
4434 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
4435 | [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, | |
4b8d54f9 | 4436 | [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, |
59708670 SY |
4437 | [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op, |
4438 | [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op, | |
6aa8b732 AK |
4439 | }; |
4440 | ||
4441 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 4442 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 | 4443 | |
586f9607 AK |
4444 | static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
4445 | { | |
4446 | *info1 = vmcs_readl(EXIT_QUALIFICATION); | |
4447 | *info2 = vmcs_read32(VM_EXIT_INTR_INFO); | |
4448 | } | |
4449 | ||
6aa8b732 AK |
4450 | /* |
4451 | * The guest has exited. See if we can fix it or if we need userspace | |
4452 | * assistance. | |
4453 | */ | |
851ba692 | 4454 | static int vmx_handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 4455 | { |
29bd8a78 | 4456 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
a0861c02 | 4457 | u32 exit_reason = vmx->exit_reason; |
1155f76a | 4458 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 4459 | |
aa17911e | 4460 | trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); |
2714d1d3 | 4461 | |
80ced186 MG |
4462 | /* If guest state is invalid, start emulating */ |
4463 | if (vmx->emulation_required && emulate_invalid_guest_state) | |
4464 | return handle_invalid_guest_state(vcpu); | |
1d5a4d9b | 4465 | |
5120702e MG |
4466 | if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { |
4467 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
4468 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
4469 | = exit_reason; | |
4470 | return 0; | |
4471 | } | |
4472 | ||
29bd8a78 | 4473 | if (unlikely(vmx->fail)) { |
851ba692 AK |
4474 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
4475 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
29bd8a78 AK |
4476 | = vmcs_read32(VM_INSTRUCTION_ERROR); |
4477 | return 0; | |
4478 | } | |
6aa8b732 | 4479 | |
d77c26fc | 4480 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c | 4481 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
60637aac JK |
4482 | exit_reason != EXIT_REASON_EPT_VIOLATION && |
4483 | exit_reason != EXIT_REASON_TASK_SWITCH)) | |
4484 | printk(KERN_WARNING "%s: unexpected, valid vectoring info " | |
4485 | "(0x%x) and exit reason is 0x%x\n", | |
4486 | __func__, vectoring_info, exit_reason); | |
3b86cd99 JK |
4487 | |
4488 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) { | |
c4282df9 | 4489 | if (vmx_interrupt_allowed(vcpu)) { |
3b86cd99 | 4490 | vmx->soft_vnmi_blocked = 0; |
3b86cd99 | 4491 | } else if (vmx->vnmi_blocked_time > 1000000000LL && |
4531220b | 4492 | vcpu->arch.nmi_pending) { |
3b86cd99 JK |
4493 | /* |
4494 | * This CPU don't support us in finding the end of an | |
4495 | * NMI-blocked window if the guest runs with IRQs | |
4496 | * disabled. So we pull the trigger after 1 s of | |
4497 | * futile waiting, but inform the user about this. | |
4498 | */ | |
4499 | printk(KERN_WARNING "%s: Breaking out of NMI-blocked " | |
4500 | "state on VCPU %d after 1 s timeout\n", | |
4501 | __func__, vcpu->vcpu_id); | |
4502 | vmx->soft_vnmi_blocked = 0; | |
3b86cd99 | 4503 | } |
3b86cd99 JK |
4504 | } |
4505 | ||
6aa8b732 AK |
4506 | if (exit_reason < kvm_vmx_max_exit_handlers |
4507 | && kvm_vmx_exit_handlers[exit_reason]) | |
851ba692 | 4508 | return kvm_vmx_exit_handlers[exit_reason](vcpu); |
6aa8b732 | 4509 | else { |
851ba692 AK |
4510 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
4511 | vcpu->run->hw.hardware_exit_reason = exit_reason; | |
6aa8b732 AK |
4512 | } |
4513 | return 0; | |
4514 | } | |
4515 | ||
95ba8273 | 4516 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
6e5d865c | 4517 | { |
95ba8273 | 4518 | if (irr == -1 || tpr < irr) { |
6e5d865c YS |
4519 | vmcs_write32(TPR_THRESHOLD, 0); |
4520 | return; | |
4521 | } | |
4522 | ||
95ba8273 | 4523 | vmcs_write32(TPR_THRESHOLD, irr); |
6e5d865c YS |
4524 | } |
4525 | ||
51aa01d1 | 4526 | static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx) |
cf393f75 | 4527 | { |
00eba012 AK |
4528 | u32 exit_intr_info; |
4529 | ||
4530 | if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY | |
4531 | || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)) | |
4532 | return; | |
4533 | ||
c5ca8e57 | 4534 | vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
00eba012 | 4535 | exit_intr_info = vmx->exit_intr_info; |
a0861c02 AK |
4536 | |
4537 | /* Handle machine checks before interrupts are enabled */ | |
00eba012 | 4538 | if (is_machine_check(exit_intr_info)) |
a0861c02 AK |
4539 | kvm_machine_check(); |
4540 | ||
20f65983 | 4541 | /* We need to handle NMIs before interrupts are enabled */ |
00eba012 | 4542 | if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR && |
ff9d07a0 ZY |
4543 | (exit_intr_info & INTR_INFO_VALID_MASK)) { |
4544 | kvm_before_handle_nmi(&vmx->vcpu); | |
20f65983 | 4545 | asm("int $2"); |
ff9d07a0 ZY |
4546 | kvm_after_handle_nmi(&vmx->vcpu); |
4547 | } | |
51aa01d1 | 4548 | } |
20f65983 | 4549 | |
51aa01d1 AK |
4550 | static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) |
4551 | { | |
c5ca8e57 | 4552 | u32 exit_intr_info; |
51aa01d1 AK |
4553 | bool unblock_nmi; |
4554 | u8 vector; | |
4555 | bool idtv_info_valid; | |
4556 | ||
4557 | idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
20f65983 | 4558 | |
cf393f75 | 4559 | if (cpu_has_virtual_nmis()) { |
9d58b931 AK |
4560 | if (vmx->nmi_known_unmasked) |
4561 | return; | |
c5ca8e57 AK |
4562 | /* |
4563 | * Can't use vmx->exit_intr_info since we're not sure what | |
4564 | * the exit reason is. | |
4565 | */ | |
4566 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
cf393f75 AK |
4567 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; |
4568 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
4569 | /* | |
7b4a25cb | 4570 | * SDM 3: 27.7.1.2 (September 2008) |
cf393f75 AK |
4571 | * Re-set bit "block by NMI" before VM entry if vmexit caused by |
4572 | * a guest IRET fault. | |
7b4a25cb GN |
4573 | * SDM 3: 23.2.2 (September 2008) |
4574 | * Bit 12 is undefined in any of the following cases: | |
4575 | * If the VM exit sets the valid bit in the IDT-vectoring | |
4576 | * information field. | |
4577 | * If the VM exit is due to a double fault. | |
cf393f75 | 4578 | */ |
7b4a25cb GN |
4579 | if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && |
4580 | vector != DF_VECTOR && !idtv_info_valid) | |
cf393f75 AK |
4581 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, |
4582 | GUEST_INTR_STATE_NMI); | |
9d58b931 AK |
4583 | else |
4584 | vmx->nmi_known_unmasked = | |
4585 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) | |
4586 | & GUEST_INTR_STATE_NMI); | |
3b86cd99 JK |
4587 | } else if (unlikely(vmx->soft_vnmi_blocked)) |
4588 | vmx->vnmi_blocked_time += | |
4589 | ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time)); | |
51aa01d1 AK |
4590 | } |
4591 | ||
83422e17 AK |
4592 | static void __vmx_complete_interrupts(struct vcpu_vmx *vmx, |
4593 | u32 idt_vectoring_info, | |
4594 | int instr_len_field, | |
4595 | int error_code_field) | |
51aa01d1 | 4596 | { |
51aa01d1 AK |
4597 | u8 vector; |
4598 | int type; | |
4599 | bool idtv_info_valid; | |
4600 | ||
4601 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
668f612f | 4602 | |
37b96e98 GN |
4603 | vmx->vcpu.arch.nmi_injected = false; |
4604 | kvm_clear_exception_queue(&vmx->vcpu); | |
4605 | kvm_clear_interrupt_queue(&vmx->vcpu); | |
4606 | ||
4607 | if (!idtv_info_valid) | |
4608 | return; | |
4609 | ||
3842d135 AK |
4610 | kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu); |
4611 | ||
668f612f AK |
4612 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; |
4613 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | |
37b96e98 | 4614 | |
64a7ec06 | 4615 | switch (type) { |
37b96e98 GN |
4616 | case INTR_TYPE_NMI_INTR: |
4617 | vmx->vcpu.arch.nmi_injected = true; | |
668f612f | 4618 | /* |
7b4a25cb | 4619 | * SDM 3: 27.7.1.2 (September 2008) |
37b96e98 GN |
4620 | * Clear bit "block by NMI" before VM entry if a NMI |
4621 | * delivery faulted. | |
668f612f | 4622 | */ |
654f06fc | 4623 | vmx_set_nmi_mask(&vmx->vcpu, false); |
37b96e98 | 4624 | break; |
37b96e98 | 4625 | case INTR_TYPE_SOFT_EXCEPTION: |
66fd3f7f | 4626 | vmx->vcpu.arch.event_exit_inst_len = |
83422e17 | 4627 | vmcs_read32(instr_len_field); |
66fd3f7f GN |
4628 | /* fall through */ |
4629 | case INTR_TYPE_HARD_EXCEPTION: | |
35920a35 | 4630 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { |
83422e17 | 4631 | u32 err = vmcs_read32(error_code_field); |
37b96e98 | 4632 | kvm_queue_exception_e(&vmx->vcpu, vector, err); |
35920a35 AK |
4633 | } else |
4634 | kvm_queue_exception(&vmx->vcpu, vector); | |
37b96e98 | 4635 | break; |
66fd3f7f GN |
4636 | case INTR_TYPE_SOFT_INTR: |
4637 | vmx->vcpu.arch.event_exit_inst_len = | |
83422e17 | 4638 | vmcs_read32(instr_len_field); |
66fd3f7f | 4639 | /* fall through */ |
37b96e98 | 4640 | case INTR_TYPE_EXT_INTR: |
66fd3f7f GN |
4641 | kvm_queue_interrupt(&vmx->vcpu, vector, |
4642 | type == INTR_TYPE_SOFT_INTR); | |
37b96e98 GN |
4643 | break; |
4644 | default: | |
4645 | break; | |
f7d9238f | 4646 | } |
cf393f75 AK |
4647 | } |
4648 | ||
83422e17 AK |
4649 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
4650 | { | |
4651 | __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info, | |
4652 | VM_EXIT_INSTRUCTION_LEN, | |
4653 | IDT_VECTORING_ERROR_CODE); | |
4654 | } | |
4655 | ||
b463a6f7 AK |
4656 | static void vmx_cancel_injection(struct kvm_vcpu *vcpu) |
4657 | { | |
4658 | __vmx_complete_interrupts(to_vmx(vcpu), | |
4659 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), | |
4660 | VM_ENTRY_INSTRUCTION_LEN, | |
4661 | VM_ENTRY_EXCEPTION_ERROR_CODE); | |
4662 | ||
4663 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); | |
4664 | } | |
4665 | ||
c801949d AK |
4666 | #ifdef CONFIG_X86_64 |
4667 | #define R "r" | |
4668 | #define Q "q" | |
4669 | #else | |
4670 | #define R "e" | |
4671 | #define Q "l" | |
4672 | #endif | |
4673 | ||
a3b5ba49 | 4674 | static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 4675 | { |
a2fa3e9f | 4676 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
104f226b AK |
4677 | |
4678 | /* Record the guest's net vcpu time for enforced NMI injections. */ | |
4679 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) | |
4680 | vmx->entry_time = ktime_get(); | |
4681 | ||
4682 | /* Don't enter VMX if guest state is invalid, let the exit handler | |
4683 | start emulation until we arrive back to a valid state */ | |
4684 | if (vmx->emulation_required && emulate_invalid_guest_state) | |
4685 | return; | |
4686 | ||
4687 | if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
4688 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); | |
4689 | if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
4690 | vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); | |
4691 | ||
4692 | /* When single-stepping over STI and MOV SS, we must clear the | |
4693 | * corresponding interruptibility bits in the guest state. Otherwise | |
4694 | * vmentry fails as it then expects bit 14 (BS) in pending debug | |
4695 | * exceptions being set, but that's not correct for the guest debugging | |
4696 | * case. */ | |
4697 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
4698 | vmx_set_interrupt_shadow(vcpu, 0); | |
4699 | ||
d462b819 | 4700 | vmx->__launched = vmx->loaded_vmcs->launched; |
104f226b | 4701 | asm( |
6aa8b732 | 4702 | /* Store host registers */ |
c801949d | 4703 | "push %%"R"dx; push %%"R"bp;" |
40712fae | 4704 | "push %%"R"cx \n\t" /* placeholder for guest rcx */ |
c801949d | 4705 | "push %%"R"cx \n\t" |
313dbd49 AK |
4706 | "cmp %%"R"sp, %c[host_rsp](%0) \n\t" |
4707 | "je 1f \n\t" | |
4708 | "mov %%"R"sp, %c[host_rsp](%0) \n\t" | |
4ecac3fd | 4709 | __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t" |
313dbd49 | 4710 | "1: \n\t" |
d3edefc0 AK |
4711 | /* Reload cr2 if changed */ |
4712 | "mov %c[cr2](%0), %%"R"ax \n\t" | |
4713 | "mov %%cr2, %%"R"dx \n\t" | |
4714 | "cmp %%"R"ax, %%"R"dx \n\t" | |
4715 | "je 2f \n\t" | |
4716 | "mov %%"R"ax, %%cr2 \n\t" | |
4717 | "2: \n\t" | |
6aa8b732 | 4718 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 4719 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 4720 | /* Load guest registers. Don't clobber flags. */ |
c801949d AK |
4721 | "mov %c[rax](%0), %%"R"ax \n\t" |
4722 | "mov %c[rbx](%0), %%"R"bx \n\t" | |
4723 | "mov %c[rdx](%0), %%"R"dx \n\t" | |
4724 | "mov %c[rsi](%0), %%"R"si \n\t" | |
4725 | "mov %c[rdi](%0), %%"R"di \n\t" | |
4726 | "mov %c[rbp](%0), %%"R"bp \n\t" | |
05b3e0c2 | 4727 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
4728 | "mov %c[r8](%0), %%r8 \n\t" |
4729 | "mov %c[r9](%0), %%r9 \n\t" | |
4730 | "mov %c[r10](%0), %%r10 \n\t" | |
4731 | "mov %c[r11](%0), %%r11 \n\t" | |
4732 | "mov %c[r12](%0), %%r12 \n\t" | |
4733 | "mov %c[r13](%0), %%r13 \n\t" | |
4734 | "mov %c[r14](%0), %%r14 \n\t" | |
4735 | "mov %c[r15](%0), %%r15 \n\t" | |
6aa8b732 | 4736 | #endif |
c801949d AK |
4737 | "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */ |
4738 | ||
6aa8b732 | 4739 | /* Enter guest mode */ |
cd2276a7 | 4740 | "jne .Llaunched \n\t" |
4ecac3fd | 4741 | __ex(ASM_VMX_VMLAUNCH) "\n\t" |
cd2276a7 | 4742 | "jmp .Lkvm_vmx_return \n\t" |
4ecac3fd | 4743 | ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t" |
cd2276a7 | 4744 | ".Lkvm_vmx_return: " |
6aa8b732 | 4745 | /* Save guest registers, load host registers, keep flags */ |
40712fae AK |
4746 | "mov %0, %c[wordsize](%%"R"sp) \n\t" |
4747 | "pop %0 \n\t" | |
c801949d AK |
4748 | "mov %%"R"ax, %c[rax](%0) \n\t" |
4749 | "mov %%"R"bx, %c[rbx](%0) \n\t" | |
1c696d0e | 4750 | "pop"Q" %c[rcx](%0) \n\t" |
c801949d AK |
4751 | "mov %%"R"dx, %c[rdx](%0) \n\t" |
4752 | "mov %%"R"si, %c[rsi](%0) \n\t" | |
4753 | "mov %%"R"di, %c[rdi](%0) \n\t" | |
4754 | "mov %%"R"bp, %c[rbp](%0) \n\t" | |
05b3e0c2 | 4755 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
4756 | "mov %%r8, %c[r8](%0) \n\t" |
4757 | "mov %%r9, %c[r9](%0) \n\t" | |
4758 | "mov %%r10, %c[r10](%0) \n\t" | |
4759 | "mov %%r11, %c[r11](%0) \n\t" | |
4760 | "mov %%r12, %c[r12](%0) \n\t" | |
4761 | "mov %%r13, %c[r13](%0) \n\t" | |
4762 | "mov %%r14, %c[r14](%0) \n\t" | |
4763 | "mov %%r15, %c[r15](%0) \n\t" | |
6aa8b732 | 4764 | #endif |
c801949d AK |
4765 | "mov %%cr2, %%"R"ax \n\t" |
4766 | "mov %%"R"ax, %c[cr2](%0) \n\t" | |
4767 | ||
1c696d0e | 4768 | "pop %%"R"bp; pop %%"R"dx \n\t" |
e08aa78a AK |
4769 | "setbe %c[fail](%0) \n\t" |
4770 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), | |
d462b819 | 4771 | [launched]"i"(offsetof(struct vcpu_vmx, __launched)), |
e08aa78a | 4772 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), |
313dbd49 | 4773 | [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)), |
ad312c7c ZX |
4774 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
4775 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
4776 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
4777 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
4778 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
4779 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
4780 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 4781 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
4782 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
4783 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
4784 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
4785 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
4786 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
4787 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
4788 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
4789 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 4790 | #endif |
40712fae AK |
4791 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)), |
4792 | [wordsize]"i"(sizeof(ulong)) | |
c2036300 | 4793 | : "cc", "memory" |
07d6f555 | 4794 | , R"ax", R"bx", R"di", R"si" |
c2036300 | 4795 | #ifdef CONFIG_X86_64 |
c2036300 LV |
4796 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
4797 | #endif | |
4798 | ); | |
6aa8b732 | 4799 | |
6de4f3ad | 4800 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) |
6de12732 | 4801 | | (1 << VCPU_EXREG_RFLAGS) |
69c73028 | 4802 | | (1 << VCPU_EXREG_CPL) |
aff48baa | 4803 | | (1 << VCPU_EXREG_PDPTR) |
2fb92db1 | 4804 | | (1 << VCPU_EXREG_SEGMENTS) |
aff48baa | 4805 | | (1 << VCPU_EXREG_CR3)); |
5fdbf976 MT |
4806 | vcpu->arch.regs_dirty = 0; |
4807 | ||
1155f76a AK |
4808 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); |
4809 | ||
d77c26fc | 4810 | asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS)); |
d462b819 | 4811 | vmx->loaded_vmcs->launched = 1; |
1b6269db | 4812 | |
51aa01d1 | 4813 | vmx->exit_reason = vmcs_read32(VM_EXIT_REASON); |
51aa01d1 AK |
4814 | |
4815 | vmx_complete_atomic_exit(vmx); | |
4816 | vmx_recover_nmi_blocking(vmx); | |
cf393f75 | 4817 | vmx_complete_interrupts(vmx); |
6aa8b732 AK |
4818 | } |
4819 | ||
c801949d AK |
4820 | #undef R |
4821 | #undef Q | |
4822 | ||
6aa8b732 AK |
4823 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) |
4824 | { | |
fb3f0f51 RR |
4825 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4826 | ||
cdbecfc3 | 4827 | free_vpid(vmx); |
ec378aee | 4828 | free_nested(vmx); |
d462b819 | 4829 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 RR |
4830 | kfree(vmx->guest_msrs); |
4831 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 4832 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
4833 | } |
4834 | ||
fb3f0f51 | 4835 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 4836 | { |
fb3f0f51 | 4837 | int err; |
c16f862d | 4838 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
15ad7146 | 4839 | int cpu; |
6aa8b732 | 4840 | |
a2fa3e9f | 4841 | if (!vmx) |
fb3f0f51 RR |
4842 | return ERR_PTR(-ENOMEM); |
4843 | ||
2384d2b3 SY |
4844 | allocate_vpid(vmx); |
4845 | ||
fb3f0f51 RR |
4846 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
4847 | if (err) | |
4848 | goto free_vcpu; | |
965b58a5 | 4849 | |
a2fa3e9f | 4850 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
be6d05cf | 4851 | err = -ENOMEM; |
fb3f0f51 | 4852 | if (!vmx->guest_msrs) { |
fb3f0f51 RR |
4853 | goto uninit_vcpu; |
4854 | } | |
965b58a5 | 4855 | |
d462b819 NHE |
4856 | vmx->loaded_vmcs = &vmx->vmcs01; |
4857 | vmx->loaded_vmcs->vmcs = alloc_vmcs(); | |
4858 | if (!vmx->loaded_vmcs->vmcs) | |
fb3f0f51 | 4859 | goto free_msrs; |
d462b819 NHE |
4860 | if (!vmm_exclusive) |
4861 | kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id()))); | |
4862 | loaded_vmcs_init(vmx->loaded_vmcs); | |
4863 | if (!vmm_exclusive) | |
4864 | kvm_cpu_vmxoff(); | |
a2fa3e9f | 4865 | |
15ad7146 AK |
4866 | cpu = get_cpu(); |
4867 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
e48672fa | 4868 | vmx->vcpu.cpu = cpu; |
8b9cf98c | 4869 | err = vmx_vcpu_setup(vmx); |
fb3f0f51 | 4870 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 4871 | put_cpu(); |
fb3f0f51 RR |
4872 | if (err) |
4873 | goto free_vmcs; | |
5e4a0b3c | 4874 | if (vm_need_virtualize_apic_accesses(kvm)) |
be6d05cf JK |
4875 | err = alloc_apic_access_page(kvm); |
4876 | if (err) | |
5e4a0b3c | 4877 | goto free_vmcs; |
fb3f0f51 | 4878 | |
b927a3ce SY |
4879 | if (enable_ept) { |
4880 | if (!kvm->arch.ept_identity_map_addr) | |
4881 | kvm->arch.ept_identity_map_addr = | |
4882 | VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
93ea5388 | 4883 | err = -ENOMEM; |
b7ebfb05 SY |
4884 | if (alloc_identity_pagetable(kvm) != 0) |
4885 | goto free_vmcs; | |
93ea5388 GN |
4886 | if (!init_rmode_identity_map(kvm)) |
4887 | goto free_vmcs; | |
b927a3ce | 4888 | } |
b7ebfb05 | 4889 | |
a9d30f33 NHE |
4890 | vmx->nested.current_vmptr = -1ull; |
4891 | vmx->nested.current_vmcs12 = NULL; | |
4892 | ||
fb3f0f51 RR |
4893 | return &vmx->vcpu; |
4894 | ||
4895 | free_vmcs: | |
d462b819 | 4896 | free_vmcs(vmx->loaded_vmcs->vmcs); |
fb3f0f51 | 4897 | free_msrs: |
fb3f0f51 RR |
4898 | kfree(vmx->guest_msrs); |
4899 | uninit_vcpu: | |
4900 | kvm_vcpu_uninit(&vmx->vcpu); | |
4901 | free_vcpu: | |
cdbecfc3 | 4902 | free_vpid(vmx); |
a4770347 | 4903 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 4904 | return ERR_PTR(err); |
6aa8b732 AK |
4905 | } |
4906 | ||
002c7f7c YS |
4907 | static void __init vmx_check_processor_compat(void *rtn) |
4908 | { | |
4909 | struct vmcs_config vmcs_conf; | |
4910 | ||
4911 | *(int *)rtn = 0; | |
4912 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
4913 | *(int *)rtn = -EIO; | |
4914 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
4915 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
4916 | smp_processor_id()); | |
4917 | *(int *)rtn = -EIO; | |
4918 | } | |
4919 | } | |
4920 | ||
67253af5 SY |
4921 | static int get_ept_level(void) |
4922 | { | |
4923 | return VMX_EPT_DEFAULT_GAW + 1; | |
4924 | } | |
4925 | ||
4b12f0de | 4926 | static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 | 4927 | { |
4b12f0de SY |
4928 | u64 ret; |
4929 | ||
522c68c4 SY |
4930 | /* For VT-d and EPT combination |
4931 | * 1. MMIO: always map as UC | |
4932 | * 2. EPT with VT-d: | |
4933 | * a. VT-d without snooping control feature: can't guarantee the | |
4934 | * result, try to trust guest. | |
4935 | * b. VT-d with snooping control feature: snooping control feature of | |
4936 | * VT-d engine can guarantee the cache correctness. Just set it | |
4937 | * to WB to keep consistent with host. So the same as item 3. | |
a19a6d11 | 4938 | * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep |
522c68c4 SY |
4939 | * consistent with host MTRR |
4940 | */ | |
4b12f0de SY |
4941 | if (is_mmio) |
4942 | ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT; | |
522c68c4 SY |
4943 | else if (vcpu->kvm->arch.iommu_domain && |
4944 | !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY)) | |
4945 | ret = kvm_get_guest_memory_type(vcpu, gfn) << | |
4946 | VMX_EPT_MT_EPTE_SHIFT; | |
4b12f0de | 4947 | else |
522c68c4 | 4948 | ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT) |
a19a6d11 | 4949 | | VMX_EPT_IPAT_BIT; |
4b12f0de SY |
4950 | |
4951 | return ret; | |
64d4d521 SY |
4952 | } |
4953 | ||
f4c9e87c AK |
4954 | #define _ER(x) { EXIT_REASON_##x, #x } |
4955 | ||
229456fc | 4956 | static const struct trace_print_flags vmx_exit_reasons_str[] = { |
f4c9e87c AK |
4957 | _ER(EXCEPTION_NMI), |
4958 | _ER(EXTERNAL_INTERRUPT), | |
4959 | _ER(TRIPLE_FAULT), | |
4960 | _ER(PENDING_INTERRUPT), | |
4961 | _ER(NMI_WINDOW), | |
4962 | _ER(TASK_SWITCH), | |
4963 | _ER(CPUID), | |
4964 | _ER(HLT), | |
4965 | _ER(INVLPG), | |
4966 | _ER(RDPMC), | |
4967 | _ER(RDTSC), | |
4968 | _ER(VMCALL), | |
4969 | _ER(VMCLEAR), | |
4970 | _ER(VMLAUNCH), | |
4971 | _ER(VMPTRLD), | |
4972 | _ER(VMPTRST), | |
4973 | _ER(VMREAD), | |
4974 | _ER(VMRESUME), | |
4975 | _ER(VMWRITE), | |
4976 | _ER(VMOFF), | |
4977 | _ER(VMON), | |
4978 | _ER(CR_ACCESS), | |
4979 | _ER(DR_ACCESS), | |
4980 | _ER(IO_INSTRUCTION), | |
4981 | _ER(MSR_READ), | |
4982 | _ER(MSR_WRITE), | |
4983 | _ER(MWAIT_INSTRUCTION), | |
4984 | _ER(MONITOR_INSTRUCTION), | |
4985 | _ER(PAUSE_INSTRUCTION), | |
4986 | _ER(MCE_DURING_VMENTRY), | |
4987 | _ER(TPR_BELOW_THRESHOLD), | |
4988 | _ER(APIC_ACCESS), | |
4989 | _ER(EPT_VIOLATION), | |
4990 | _ER(EPT_MISCONFIG), | |
4991 | _ER(WBINVD), | |
229456fc MT |
4992 | { -1, NULL } |
4993 | }; | |
4994 | ||
f4c9e87c AK |
4995 | #undef _ER |
4996 | ||
17cc3935 | 4997 | static int vmx_get_lpage_level(void) |
344f414f | 4998 | { |
878403b7 SY |
4999 | if (enable_ept && !cpu_has_vmx_ept_1g_page()) |
5000 | return PT_DIRECTORY_LEVEL; | |
5001 | else | |
5002 | /* For shadow and EPT supported 1GB page */ | |
5003 | return PT_PDPE_LEVEL; | |
344f414f JR |
5004 | } |
5005 | ||
0e851880 SY |
5006 | static void vmx_cpuid_update(struct kvm_vcpu *vcpu) |
5007 | { | |
4e47c7a6 SY |
5008 | struct kvm_cpuid_entry2 *best; |
5009 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5010 | u32 exec_control; | |
5011 | ||
5012 | vmx->rdtscp_enabled = false; | |
5013 | if (vmx_rdtscp_supported()) { | |
5014 | exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
5015 | if (exec_control & SECONDARY_EXEC_RDTSCP) { | |
5016 | best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
5017 | if (best && (best->edx & bit(X86_FEATURE_RDTSCP))) | |
5018 | vmx->rdtscp_enabled = true; | |
5019 | else { | |
5020 | exec_control &= ~SECONDARY_EXEC_RDTSCP; | |
5021 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, | |
5022 | exec_control); | |
5023 | } | |
5024 | } | |
5025 | } | |
0e851880 SY |
5026 | } |
5027 | ||
d4330ef2 JR |
5028 | static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
5029 | { | |
5030 | } | |
5031 | ||
8a76d7f2 JR |
5032 | static int vmx_check_intercept(struct kvm_vcpu *vcpu, |
5033 | struct x86_instruction_info *info, | |
5034 | enum x86_intercept_stage stage) | |
5035 | { | |
5036 | return X86EMUL_CONTINUE; | |
5037 | } | |
5038 | ||
cbdd1bea | 5039 | static struct kvm_x86_ops vmx_x86_ops = { |
6aa8b732 AK |
5040 | .cpu_has_kvm_support = cpu_has_kvm_support, |
5041 | .disabled_by_bios = vmx_disabled_by_bios, | |
5042 | .hardware_setup = hardware_setup, | |
5043 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 5044 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
5045 | .hardware_enable = hardware_enable, |
5046 | .hardware_disable = hardware_disable, | |
04547156 | 5047 | .cpu_has_accelerated_tpr = report_flexpriority, |
6aa8b732 AK |
5048 | |
5049 | .vcpu_create = vmx_create_vcpu, | |
5050 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 5051 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 5052 | |
04d2cc77 | 5053 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
5054 | .vcpu_load = vmx_vcpu_load, |
5055 | .vcpu_put = vmx_vcpu_put, | |
5056 | ||
5057 | .set_guest_debug = set_guest_debug, | |
5058 | .get_msr = vmx_get_msr, | |
5059 | .set_msr = vmx_set_msr, | |
5060 | .get_segment_base = vmx_get_segment_base, | |
5061 | .get_segment = vmx_get_segment, | |
5062 | .set_segment = vmx_set_segment, | |
2e4d2653 | 5063 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 5064 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
e8467fda | 5065 | .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, |
aff48baa | 5066 | .decache_cr3 = vmx_decache_cr3, |
25c4c276 | 5067 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 5068 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
5069 | .set_cr3 = vmx_set_cr3, |
5070 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 5071 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
5072 | .get_idt = vmx_get_idt, |
5073 | .set_idt = vmx_set_idt, | |
5074 | .get_gdt = vmx_get_gdt, | |
5075 | .set_gdt = vmx_set_gdt, | |
020df079 | 5076 | .set_dr7 = vmx_set_dr7, |
5fdbf976 | 5077 | .cache_reg = vmx_cache_reg, |
6aa8b732 AK |
5078 | .get_rflags = vmx_get_rflags, |
5079 | .set_rflags = vmx_set_rflags, | |
ebcbab4c | 5080 | .fpu_activate = vmx_fpu_activate, |
02daab21 | 5081 | .fpu_deactivate = vmx_fpu_deactivate, |
6aa8b732 AK |
5082 | |
5083 | .tlb_flush = vmx_flush_tlb, | |
6aa8b732 | 5084 | |
6aa8b732 | 5085 | .run = vmx_vcpu_run, |
6062d012 | 5086 | .handle_exit = vmx_handle_exit, |
6aa8b732 | 5087 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
5088 | .set_interrupt_shadow = vmx_set_interrupt_shadow, |
5089 | .get_interrupt_shadow = vmx_get_interrupt_shadow, | |
102d8325 | 5090 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 | 5091 | .set_irq = vmx_inject_irq, |
95ba8273 | 5092 | .set_nmi = vmx_inject_nmi, |
298101da | 5093 | .queue_exception = vmx_queue_exception, |
b463a6f7 | 5094 | .cancel_injection = vmx_cancel_injection, |
78646121 | 5095 | .interrupt_allowed = vmx_interrupt_allowed, |
95ba8273 | 5096 | .nmi_allowed = vmx_nmi_allowed, |
3cfc3092 JK |
5097 | .get_nmi_mask = vmx_get_nmi_mask, |
5098 | .set_nmi_mask = vmx_set_nmi_mask, | |
95ba8273 GN |
5099 | .enable_nmi_window = enable_nmi_window, |
5100 | .enable_irq_window = enable_irq_window, | |
5101 | .update_cr8_intercept = update_cr8_intercept, | |
95ba8273 | 5102 | |
cbc94022 | 5103 | .set_tss_addr = vmx_set_tss_addr, |
67253af5 | 5104 | .get_tdp_level = get_ept_level, |
4b12f0de | 5105 | .get_mt_mask = vmx_get_mt_mask, |
229456fc | 5106 | |
586f9607 | 5107 | .get_exit_info = vmx_get_exit_info, |
229456fc | 5108 | .exit_reasons_str = vmx_exit_reasons_str, |
586f9607 | 5109 | |
17cc3935 | 5110 | .get_lpage_level = vmx_get_lpage_level, |
0e851880 SY |
5111 | |
5112 | .cpuid_update = vmx_cpuid_update, | |
4e47c7a6 SY |
5113 | |
5114 | .rdtscp_supported = vmx_rdtscp_supported, | |
d4330ef2 JR |
5115 | |
5116 | .set_supported_cpuid = vmx_set_supported_cpuid, | |
f5f48ee1 SY |
5117 | |
5118 | .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, | |
99e3e30a | 5119 | |
4051b188 | 5120 | .set_tsc_khz = vmx_set_tsc_khz, |
99e3e30a | 5121 | .write_tsc_offset = vmx_write_tsc_offset, |
e48672fa | 5122 | .adjust_tsc_offset = vmx_adjust_tsc_offset, |
857e4099 | 5123 | .compute_tsc_offset = vmx_compute_tsc_offset, |
1c97f0a0 JR |
5124 | |
5125 | .set_tdp_cr3 = vmx_set_cr3, | |
8a76d7f2 JR |
5126 | |
5127 | .check_intercept = vmx_check_intercept, | |
6aa8b732 AK |
5128 | }; |
5129 | ||
5130 | static int __init vmx_init(void) | |
5131 | { | |
26bb0981 AK |
5132 | int r, i; |
5133 | ||
5134 | rdmsrl_safe(MSR_EFER, &host_efer); | |
5135 | ||
5136 | for (i = 0; i < NR_VMX_MSR; ++i) | |
5137 | kvm_define_shared_msr(i, vmx_msr_index[i]); | |
fdef3ad1 | 5138 | |
3e7c73e9 | 5139 | vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL); |
fdef3ad1 HQ |
5140 | if (!vmx_io_bitmap_a) |
5141 | return -ENOMEM; | |
5142 | ||
3e7c73e9 | 5143 | vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL); |
fdef3ad1 HQ |
5144 | if (!vmx_io_bitmap_b) { |
5145 | r = -ENOMEM; | |
5146 | goto out; | |
5147 | } | |
5148 | ||
5897297b AK |
5149 | vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL); |
5150 | if (!vmx_msr_bitmap_legacy) { | |
25c5f225 SY |
5151 | r = -ENOMEM; |
5152 | goto out1; | |
5153 | } | |
5154 | ||
5897297b AK |
5155 | vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL); |
5156 | if (!vmx_msr_bitmap_longmode) { | |
5157 | r = -ENOMEM; | |
5158 | goto out2; | |
5159 | } | |
5160 | ||
fdef3ad1 HQ |
5161 | /* |
5162 | * Allow direct access to the PC debug port (it is often used for I/O | |
5163 | * delays, but the vmexits simply slow things down). | |
5164 | */ | |
3e7c73e9 AK |
5165 | memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE); |
5166 | clear_bit(0x80, vmx_io_bitmap_a); | |
fdef3ad1 | 5167 | |
3e7c73e9 | 5168 | memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE); |
fdef3ad1 | 5169 | |
5897297b AK |
5170 | memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE); |
5171 | memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE); | |
25c5f225 | 5172 | |
2384d2b3 SY |
5173 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
5174 | ||
0ee75bea AK |
5175 | r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), |
5176 | __alignof__(struct vcpu_vmx), THIS_MODULE); | |
fdef3ad1 | 5177 | if (r) |
5897297b | 5178 | goto out3; |
25c5f225 | 5179 | |
5897297b AK |
5180 | vmx_disable_intercept_for_msr(MSR_FS_BASE, false); |
5181 | vmx_disable_intercept_for_msr(MSR_GS_BASE, false); | |
5182 | vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true); | |
5183 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false); | |
5184 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false); | |
5185 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false); | |
fdef3ad1 | 5186 | |
089d034e | 5187 | if (enable_ept) { |
1439442c | 5188 | bypass_guest_pf = 0; |
534e38b4 | 5189 | kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull, |
4b12f0de | 5190 | VMX_EPT_EXECUTABLE_MASK); |
5fdbcb9d SY |
5191 | kvm_enable_tdp(); |
5192 | } else | |
5193 | kvm_disable_tdp(); | |
1439442c | 5194 | |
c7addb90 AK |
5195 | if (bypass_guest_pf) |
5196 | kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull); | |
5197 | ||
fdef3ad1 HQ |
5198 | return 0; |
5199 | ||
5897297b AK |
5200 | out3: |
5201 | free_page((unsigned long)vmx_msr_bitmap_longmode); | |
25c5f225 | 5202 | out2: |
5897297b | 5203 | free_page((unsigned long)vmx_msr_bitmap_legacy); |
fdef3ad1 | 5204 | out1: |
3e7c73e9 | 5205 | free_page((unsigned long)vmx_io_bitmap_b); |
fdef3ad1 | 5206 | out: |
3e7c73e9 | 5207 | free_page((unsigned long)vmx_io_bitmap_a); |
fdef3ad1 | 5208 | return r; |
6aa8b732 AK |
5209 | } |
5210 | ||
5211 | static void __exit vmx_exit(void) | |
5212 | { | |
5897297b AK |
5213 | free_page((unsigned long)vmx_msr_bitmap_legacy); |
5214 | free_page((unsigned long)vmx_msr_bitmap_longmode); | |
3e7c73e9 AK |
5215 | free_page((unsigned long)vmx_io_bitmap_b); |
5216 | free_page((unsigned long)vmx_io_bitmap_a); | |
fdef3ad1 | 5217 | |
cb498ea2 | 5218 | kvm_exit(); |
6aa8b732 AK |
5219 | } |
5220 | ||
5221 | module_init(vmx_init) | |
5222 | module_exit(vmx_exit) |