Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 8 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
9 | * |
10 | * Authors: | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * | |
14 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
15 | * the COPYING file in the top-level directory. | |
16 | * | |
17 | */ | |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
00b27a3e | 21 | #include "cpuid.h" |
d62caabb | 22 | #include "lapic.h" |
e495606d | 23 | |
edf88417 | 24 | #include <linux/kvm_host.h> |
6aa8b732 | 25 | #include <linux/module.h> |
9d8f549d | 26 | #include <linux/kernel.h> |
6aa8b732 AK |
27 | #include <linux/mm.h> |
28 | #include <linux/highmem.h> | |
e8edc6e0 | 29 | #include <linux/sched.h> |
c7addb90 | 30 | #include <linux/moduleparam.h> |
e9bda3b3 | 31 | #include <linux/mod_devicetable.h> |
af658dca | 32 | #include <linux/trace_events.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
cafd6659 | 34 | #include <linux/tboot.h> |
f4124500 | 35 | #include <linux/hrtimer.h> |
5fdbf976 | 36 | #include "kvm_cache_regs.h" |
35920a35 | 37 | #include "x86.h" |
e495606d | 38 | |
28b835d6 | 39 | #include <asm/cpu.h> |
6aa8b732 | 40 | #include <asm/io.h> |
3b3be0d1 | 41 | #include <asm/desc.h> |
13673a90 | 42 | #include <asm/vmx.h> |
6210e37b | 43 | #include <asm/virtext.h> |
a0861c02 | 44 | #include <asm/mce.h> |
952f07ec | 45 | #include <asm/fpu/internal.h> |
d7cd9796 | 46 | #include <asm/perf_event.h> |
81908bf4 | 47 | #include <asm/debugreg.h> |
8f536b76 | 48 | #include <asm/kexec.h> |
dab2087d | 49 | #include <asm/apic.h> |
efc64404 | 50 | #include <asm/irq_remapping.h> |
6aa8b732 | 51 | |
229456fc | 52 | #include "trace.h" |
25462f7f | 53 | #include "pmu.h" |
229456fc | 54 | |
4ecac3fd | 55 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
5e520e62 AK |
56 | #define __ex_clear(x, reg) \ |
57 | ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg) | |
4ecac3fd | 58 | |
6aa8b732 AK |
59 | MODULE_AUTHOR("Qumranet"); |
60 | MODULE_LICENSE("GPL"); | |
61 | ||
e9bda3b3 JT |
62 | static const struct x86_cpu_id vmx_cpu_id[] = { |
63 | X86_FEATURE_MATCH(X86_FEATURE_VMX), | |
64 | {} | |
65 | }; | |
66 | MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); | |
67 | ||
476bc001 | 68 | static bool __read_mostly enable_vpid = 1; |
736caefe | 69 | module_param_named(vpid, enable_vpid, bool, 0444); |
2384d2b3 | 70 | |
476bc001 | 71 | static bool __read_mostly flexpriority_enabled = 1; |
736caefe | 72 | module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); |
4c9fc8ef | 73 | |
476bc001 | 74 | static bool __read_mostly enable_ept = 1; |
736caefe | 75 | module_param_named(ept, enable_ept, bool, S_IRUGO); |
d56f546d | 76 | |
476bc001 | 77 | static bool __read_mostly enable_unrestricted_guest = 1; |
3a624e29 NK |
78 | module_param_named(unrestricted_guest, |
79 | enable_unrestricted_guest, bool, S_IRUGO); | |
80 | ||
83c3a331 XH |
81 | static bool __read_mostly enable_ept_ad_bits = 1; |
82 | module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); | |
83 | ||
a27685c3 | 84 | static bool __read_mostly emulate_invalid_guest_state = true; |
c1f8bc04 | 85 | module_param(emulate_invalid_guest_state, bool, S_IRUGO); |
04fa4d32 | 86 | |
476bc001 | 87 | static bool __read_mostly fasteoi = 1; |
58fbbf26 KT |
88 | module_param(fasteoi, bool, S_IRUGO); |
89 | ||
5a71785d | 90 | static bool __read_mostly enable_apicv = 1; |
01e439be | 91 | module_param(enable_apicv, bool, S_IRUGO); |
83d4c286 | 92 | |
abc4fc58 AG |
93 | static bool __read_mostly enable_shadow_vmcs = 1; |
94 | module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO); | |
801d3424 NHE |
95 | /* |
96 | * If nested=1, nested virtualization is supported, i.e., guests may use | |
97 | * VMX and be a hypervisor for its own guests. If nested=0, guests may not | |
98 | * use VMX instructions. | |
99 | */ | |
476bc001 | 100 | static bool __read_mostly nested = 0; |
801d3424 NHE |
101 | module_param(nested, bool, S_IRUGO); |
102 | ||
20300099 WL |
103 | static u64 __read_mostly host_xss; |
104 | ||
843e4330 KH |
105 | static bool __read_mostly enable_pml = 1; |
106 | module_param_named(pml, enable_pml, bool, S_IRUGO); | |
107 | ||
64903d61 HZ |
108 | #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL |
109 | ||
64672c95 YJ |
110 | /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ |
111 | static int __read_mostly cpu_preemption_timer_multi; | |
112 | static bool __read_mostly enable_preemption_timer = 1; | |
113 | #ifdef CONFIG_X86_64 | |
114 | module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); | |
115 | #endif | |
116 | ||
5037878e GN |
117 | #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD) |
118 | #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE) | |
cdc0e244 AK |
119 | #define KVM_VM_CR0_ALWAYS_ON \ |
120 | (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) | |
4c38609a AK |
121 | #define KVM_CR4_GUEST_OWNED_BITS \ |
122 | (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
52ce3c21 | 123 | | X86_CR4_OSXMMEXCPT | X86_CR4_TSD) |
4c38609a | 124 | |
cdc0e244 AK |
125 | #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) |
126 | #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) | |
127 | ||
78ac8b47 AK |
128 | #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) |
129 | ||
f4124500 JK |
130 | #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5 |
131 | ||
16c2aec6 JD |
132 | /* |
133 | * Hyper-V requires all of these, so mark them as supported even though | |
134 | * they are just treated the same as all-context. | |
135 | */ | |
136 | #define VMX_VPID_EXTENT_SUPPORTED_MASK \ | |
137 | (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \ | |
138 | VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \ | |
139 | VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \ | |
140 | VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT) | |
141 | ||
4b8d54f9 ZE |
142 | /* |
143 | * These 2 parameters are used to config the controls for Pause-Loop Exiting: | |
144 | * ple_gap: upper bound on the amount of time between two successive | |
145 | * executions of PAUSE in a loop. Also indicate if ple enabled. | |
00c25bce | 146 | * According to test, this time is usually smaller than 128 cycles. |
4b8d54f9 ZE |
147 | * ple_window: upper bound on the amount of time a guest is allowed to execute |
148 | * in a PAUSE loop. Tests indicate that most spinlocks are held for | |
149 | * less than 2^12 cycles | |
150 | * Time is measured based on a counter that runs at the same rate as the TSC, | |
151 | * refer SDM volume 3b section 21.6.13 & 22.1.3. | |
152 | */ | |
b4a2d31d RK |
153 | #define KVM_VMX_DEFAULT_PLE_GAP 128 |
154 | #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 | |
155 | #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2 | |
156 | #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0 | |
157 | #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \ | |
158 | INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW | |
159 | ||
4b8d54f9 ZE |
160 | static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP; |
161 | module_param(ple_gap, int, S_IRUGO); | |
162 | ||
163 | static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; | |
164 | module_param(ple_window, int, S_IRUGO); | |
165 | ||
b4a2d31d RK |
166 | /* Default doubles per-vcpu window every exit. */ |
167 | static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW; | |
168 | module_param(ple_window_grow, int, S_IRUGO); | |
169 | ||
170 | /* Default resets per-vcpu window every exit to ple_window. */ | |
171 | static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK; | |
172 | module_param(ple_window_shrink, int, S_IRUGO); | |
173 | ||
174 | /* Default is to compute the maximum so we can never overflow. */ | |
175 | static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; | |
176 | static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; | |
177 | module_param(ple_window_max, int, S_IRUGO); | |
178 | ||
83287ea4 AK |
179 | extern const ulong vmx_return; |
180 | ||
8bf00a52 | 181 | #define NR_AUTOLOAD_MSRS 8 |
ff2f6fe9 | 182 | #define VMCS02_POOL_SIZE 1 |
61d2ef2c | 183 | |
a2fa3e9f GH |
184 | struct vmcs { |
185 | u32 revision_id; | |
186 | u32 abort; | |
187 | char data[0]; | |
188 | }; | |
189 | ||
d462b819 NHE |
190 | /* |
191 | * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also | |
192 | * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs | |
193 | * loaded on this CPU (so we can clear them if the CPU goes down). | |
194 | */ | |
195 | struct loaded_vmcs { | |
196 | struct vmcs *vmcs; | |
355f4fb1 | 197 | struct vmcs *shadow_vmcs; |
d462b819 NHE |
198 | int cpu; |
199 | int launched; | |
200 | struct list_head loaded_vmcss_on_cpu_link; | |
201 | }; | |
202 | ||
26bb0981 AK |
203 | struct shared_msr_entry { |
204 | unsigned index; | |
205 | u64 data; | |
d5696725 | 206 | u64 mask; |
26bb0981 AK |
207 | }; |
208 | ||
a9d30f33 NHE |
209 | /* |
210 | * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a | |
211 | * single nested guest (L2), hence the name vmcs12. Any VMX implementation has | |
212 | * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is | |
213 | * stored in guest memory specified by VMPTRLD, but is opaque to the guest, | |
214 | * which must access it using VMREAD/VMWRITE/VMCLEAR instructions. | |
215 | * More than one of these structures may exist, if L1 runs multiple L2 guests. | |
216 | * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the | |
217 | * underlying hardware which will be used to run L2. | |
218 | * This structure is packed to ensure that its layout is identical across | |
219 | * machines (necessary for live migration). | |
220 | * If there are changes in this struct, VMCS12_REVISION must be changed. | |
221 | */ | |
22bd0358 | 222 | typedef u64 natural_width; |
a9d30f33 NHE |
223 | struct __packed vmcs12 { |
224 | /* According to the Intel spec, a VMCS region must start with the | |
225 | * following two fields. Then follow implementation-specific data. | |
226 | */ | |
227 | u32 revision_id; | |
228 | u32 abort; | |
22bd0358 | 229 | |
27d6c865 NHE |
230 | u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */ |
231 | u32 padding[7]; /* room for future expansion */ | |
232 | ||
22bd0358 NHE |
233 | u64 io_bitmap_a; |
234 | u64 io_bitmap_b; | |
235 | u64 msr_bitmap; | |
236 | u64 vm_exit_msr_store_addr; | |
237 | u64 vm_exit_msr_load_addr; | |
238 | u64 vm_entry_msr_load_addr; | |
239 | u64 tsc_offset; | |
240 | u64 virtual_apic_page_addr; | |
241 | u64 apic_access_addr; | |
705699a1 | 242 | u64 posted_intr_desc_addr; |
22bd0358 | 243 | u64 ept_pointer; |
608406e2 WV |
244 | u64 eoi_exit_bitmap0; |
245 | u64 eoi_exit_bitmap1; | |
246 | u64 eoi_exit_bitmap2; | |
247 | u64 eoi_exit_bitmap3; | |
81dc01f7 | 248 | u64 xss_exit_bitmap; |
22bd0358 NHE |
249 | u64 guest_physical_address; |
250 | u64 vmcs_link_pointer; | |
251 | u64 guest_ia32_debugctl; | |
252 | u64 guest_ia32_pat; | |
253 | u64 guest_ia32_efer; | |
254 | u64 guest_ia32_perf_global_ctrl; | |
255 | u64 guest_pdptr0; | |
256 | u64 guest_pdptr1; | |
257 | u64 guest_pdptr2; | |
258 | u64 guest_pdptr3; | |
36be0b9d | 259 | u64 guest_bndcfgs; |
22bd0358 NHE |
260 | u64 host_ia32_pat; |
261 | u64 host_ia32_efer; | |
262 | u64 host_ia32_perf_global_ctrl; | |
263 | u64 padding64[8]; /* room for future expansion */ | |
264 | /* | |
265 | * To allow migration of L1 (complete with its L2 guests) between | |
266 | * machines of different natural widths (32 or 64 bit), we cannot have | |
267 | * unsigned long fields with no explict size. We use u64 (aliased | |
268 | * natural_width) instead. Luckily, x86 is little-endian. | |
269 | */ | |
270 | natural_width cr0_guest_host_mask; | |
271 | natural_width cr4_guest_host_mask; | |
272 | natural_width cr0_read_shadow; | |
273 | natural_width cr4_read_shadow; | |
274 | natural_width cr3_target_value0; | |
275 | natural_width cr3_target_value1; | |
276 | natural_width cr3_target_value2; | |
277 | natural_width cr3_target_value3; | |
278 | natural_width exit_qualification; | |
279 | natural_width guest_linear_address; | |
280 | natural_width guest_cr0; | |
281 | natural_width guest_cr3; | |
282 | natural_width guest_cr4; | |
283 | natural_width guest_es_base; | |
284 | natural_width guest_cs_base; | |
285 | natural_width guest_ss_base; | |
286 | natural_width guest_ds_base; | |
287 | natural_width guest_fs_base; | |
288 | natural_width guest_gs_base; | |
289 | natural_width guest_ldtr_base; | |
290 | natural_width guest_tr_base; | |
291 | natural_width guest_gdtr_base; | |
292 | natural_width guest_idtr_base; | |
293 | natural_width guest_dr7; | |
294 | natural_width guest_rsp; | |
295 | natural_width guest_rip; | |
296 | natural_width guest_rflags; | |
297 | natural_width guest_pending_dbg_exceptions; | |
298 | natural_width guest_sysenter_esp; | |
299 | natural_width guest_sysenter_eip; | |
300 | natural_width host_cr0; | |
301 | natural_width host_cr3; | |
302 | natural_width host_cr4; | |
303 | natural_width host_fs_base; | |
304 | natural_width host_gs_base; | |
305 | natural_width host_tr_base; | |
306 | natural_width host_gdtr_base; | |
307 | natural_width host_idtr_base; | |
308 | natural_width host_ia32_sysenter_esp; | |
309 | natural_width host_ia32_sysenter_eip; | |
310 | natural_width host_rsp; | |
311 | natural_width host_rip; | |
312 | natural_width paddingl[8]; /* room for future expansion */ | |
313 | u32 pin_based_vm_exec_control; | |
314 | u32 cpu_based_vm_exec_control; | |
315 | u32 exception_bitmap; | |
316 | u32 page_fault_error_code_mask; | |
317 | u32 page_fault_error_code_match; | |
318 | u32 cr3_target_count; | |
319 | u32 vm_exit_controls; | |
320 | u32 vm_exit_msr_store_count; | |
321 | u32 vm_exit_msr_load_count; | |
322 | u32 vm_entry_controls; | |
323 | u32 vm_entry_msr_load_count; | |
324 | u32 vm_entry_intr_info_field; | |
325 | u32 vm_entry_exception_error_code; | |
326 | u32 vm_entry_instruction_len; | |
327 | u32 tpr_threshold; | |
328 | u32 secondary_vm_exec_control; | |
329 | u32 vm_instruction_error; | |
330 | u32 vm_exit_reason; | |
331 | u32 vm_exit_intr_info; | |
332 | u32 vm_exit_intr_error_code; | |
333 | u32 idt_vectoring_info_field; | |
334 | u32 idt_vectoring_error_code; | |
335 | u32 vm_exit_instruction_len; | |
336 | u32 vmx_instruction_info; | |
337 | u32 guest_es_limit; | |
338 | u32 guest_cs_limit; | |
339 | u32 guest_ss_limit; | |
340 | u32 guest_ds_limit; | |
341 | u32 guest_fs_limit; | |
342 | u32 guest_gs_limit; | |
343 | u32 guest_ldtr_limit; | |
344 | u32 guest_tr_limit; | |
345 | u32 guest_gdtr_limit; | |
346 | u32 guest_idtr_limit; | |
347 | u32 guest_es_ar_bytes; | |
348 | u32 guest_cs_ar_bytes; | |
349 | u32 guest_ss_ar_bytes; | |
350 | u32 guest_ds_ar_bytes; | |
351 | u32 guest_fs_ar_bytes; | |
352 | u32 guest_gs_ar_bytes; | |
353 | u32 guest_ldtr_ar_bytes; | |
354 | u32 guest_tr_ar_bytes; | |
355 | u32 guest_interruptibility_info; | |
356 | u32 guest_activity_state; | |
357 | u32 guest_sysenter_cs; | |
358 | u32 host_ia32_sysenter_cs; | |
0238ea91 JK |
359 | u32 vmx_preemption_timer_value; |
360 | u32 padding32[7]; /* room for future expansion */ | |
22bd0358 | 361 | u16 virtual_processor_id; |
705699a1 | 362 | u16 posted_intr_nv; |
22bd0358 NHE |
363 | u16 guest_es_selector; |
364 | u16 guest_cs_selector; | |
365 | u16 guest_ss_selector; | |
366 | u16 guest_ds_selector; | |
367 | u16 guest_fs_selector; | |
368 | u16 guest_gs_selector; | |
369 | u16 guest_ldtr_selector; | |
370 | u16 guest_tr_selector; | |
608406e2 | 371 | u16 guest_intr_status; |
22bd0358 NHE |
372 | u16 host_es_selector; |
373 | u16 host_cs_selector; | |
374 | u16 host_ss_selector; | |
375 | u16 host_ds_selector; | |
376 | u16 host_fs_selector; | |
377 | u16 host_gs_selector; | |
378 | u16 host_tr_selector; | |
a9d30f33 NHE |
379 | }; |
380 | ||
381 | /* | |
382 | * VMCS12_REVISION is an arbitrary id that should be changed if the content or | |
383 | * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and | |
384 | * VMPTRLD verifies that the VMCS region that L1 is loading contains this id. | |
385 | */ | |
386 | #define VMCS12_REVISION 0x11e57ed0 | |
387 | ||
388 | /* | |
389 | * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region | |
390 | * and any VMCS region. Although only sizeof(struct vmcs12) are used by the | |
391 | * current implementation, 4K are reserved to avoid future complications. | |
392 | */ | |
393 | #define VMCS12_SIZE 0x1000 | |
394 | ||
ff2f6fe9 NHE |
395 | /* Used to remember the last vmcs02 used for some recently used vmcs12s */ |
396 | struct vmcs02_list { | |
397 | struct list_head list; | |
398 | gpa_t vmptr; | |
399 | struct loaded_vmcs vmcs02; | |
400 | }; | |
401 | ||
ec378aee NHE |
402 | /* |
403 | * The nested_vmx structure is part of vcpu_vmx, and holds information we need | |
404 | * for correct emulation of VMX (i.e., nested VMX) on this vcpu. | |
405 | */ | |
406 | struct nested_vmx { | |
407 | /* Has the level1 guest done vmxon? */ | |
408 | bool vmxon; | |
3573e22c | 409 | gpa_t vmxon_ptr; |
a9d30f33 NHE |
410 | |
411 | /* The guest-physical address of the current VMCS L1 keeps for L2 */ | |
412 | gpa_t current_vmptr; | |
413 | /* The host-usable pointer to the above */ | |
414 | struct page *current_vmcs12_page; | |
415 | struct vmcs12 *current_vmcs12; | |
4f2777bc DM |
416 | /* |
417 | * Cache of the guest's VMCS, existing outside of guest memory. | |
418 | * Loaded from guest memory during VMPTRLD. Flushed to guest | |
419 | * memory during VMXOFF, VMCLEAR, VMPTRLD. | |
420 | */ | |
421 | struct vmcs12 *cached_vmcs12; | |
012f83cb AG |
422 | /* |
423 | * Indicates if the shadow vmcs must be updated with the | |
424 | * data hold by vmcs12 | |
425 | */ | |
426 | bool sync_shadow_vmcs; | |
ff2f6fe9 NHE |
427 | |
428 | /* vmcs02_list cache of VMCSs recently used to run L2 guests */ | |
429 | struct list_head vmcs02_pool; | |
430 | int vmcs02_num; | |
dccbfcf5 | 431 | bool change_vmcs01_virtual_x2apic_mode; |
644d711a NHE |
432 | /* L2 must run next, and mustn't decide to exit to L1. */ |
433 | bool nested_run_pending; | |
fe3ef05c NHE |
434 | /* |
435 | * Guest pages referred to in vmcs02 with host-physical pointers, so | |
436 | * we must keep them pinned while L2 runs. | |
437 | */ | |
438 | struct page *apic_access_page; | |
a7c0b07d | 439 | struct page *virtual_apic_page; |
705699a1 WV |
440 | struct page *pi_desc_page; |
441 | struct pi_desc *pi_desc; | |
442 | bool pi_pending; | |
443 | u16 posted_intr_nv; | |
f4124500 | 444 | |
d048c098 RK |
445 | unsigned long *msr_bitmap; |
446 | ||
f4124500 JK |
447 | struct hrtimer preemption_timer; |
448 | bool preemption_timer_expired; | |
2996fca0 JK |
449 | |
450 | /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */ | |
451 | u64 vmcs01_debugctl; | |
b9c237bb | 452 | |
5c614b35 WL |
453 | u16 vpid02; |
454 | u16 last_vpid; | |
455 | ||
0115f9cb DM |
456 | /* |
457 | * We only store the "true" versions of the VMX capability MSRs. We | |
458 | * generate the "non-true" versions by setting the must-be-1 bits | |
459 | * according to the SDM. | |
460 | */ | |
b9c237bb WV |
461 | u32 nested_vmx_procbased_ctls_low; |
462 | u32 nested_vmx_procbased_ctls_high; | |
b9c237bb WV |
463 | u32 nested_vmx_secondary_ctls_low; |
464 | u32 nested_vmx_secondary_ctls_high; | |
465 | u32 nested_vmx_pinbased_ctls_low; | |
466 | u32 nested_vmx_pinbased_ctls_high; | |
467 | u32 nested_vmx_exit_ctls_low; | |
468 | u32 nested_vmx_exit_ctls_high; | |
b9c237bb WV |
469 | u32 nested_vmx_entry_ctls_low; |
470 | u32 nested_vmx_entry_ctls_high; | |
b9c237bb WV |
471 | u32 nested_vmx_misc_low; |
472 | u32 nested_vmx_misc_high; | |
473 | u32 nested_vmx_ept_caps; | |
99b83ac8 | 474 | u32 nested_vmx_vpid_caps; |
62cc6b9d DM |
475 | u64 nested_vmx_basic; |
476 | u64 nested_vmx_cr0_fixed0; | |
477 | u64 nested_vmx_cr0_fixed1; | |
478 | u64 nested_vmx_cr4_fixed0; | |
479 | u64 nested_vmx_cr4_fixed1; | |
480 | u64 nested_vmx_vmcs_enum; | |
ec378aee NHE |
481 | }; |
482 | ||
01e439be | 483 | #define POSTED_INTR_ON 0 |
ebbfc765 FW |
484 | #define POSTED_INTR_SN 1 |
485 | ||
01e439be YZ |
486 | /* Posted-Interrupt Descriptor */ |
487 | struct pi_desc { | |
488 | u32 pir[8]; /* Posted interrupt requested */ | |
6ef1522f FW |
489 | union { |
490 | struct { | |
491 | /* bit 256 - Outstanding Notification */ | |
492 | u16 on : 1, | |
493 | /* bit 257 - Suppress Notification */ | |
494 | sn : 1, | |
495 | /* bit 271:258 - Reserved */ | |
496 | rsvd_1 : 14; | |
497 | /* bit 279:272 - Notification Vector */ | |
498 | u8 nv; | |
499 | /* bit 287:280 - Reserved */ | |
500 | u8 rsvd_2; | |
501 | /* bit 319:288 - Notification Destination */ | |
502 | u32 ndst; | |
503 | }; | |
504 | u64 control; | |
505 | }; | |
506 | u32 rsvd[6]; | |
01e439be YZ |
507 | } __aligned(64); |
508 | ||
a20ed54d YZ |
509 | static bool pi_test_and_set_on(struct pi_desc *pi_desc) |
510 | { | |
511 | return test_and_set_bit(POSTED_INTR_ON, | |
512 | (unsigned long *)&pi_desc->control); | |
513 | } | |
514 | ||
515 | static bool pi_test_and_clear_on(struct pi_desc *pi_desc) | |
516 | { | |
517 | return test_and_clear_bit(POSTED_INTR_ON, | |
518 | (unsigned long *)&pi_desc->control); | |
519 | } | |
520 | ||
521 | static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc) | |
522 | { | |
523 | return test_and_set_bit(vector, (unsigned long *)pi_desc->pir); | |
524 | } | |
525 | ||
ebbfc765 FW |
526 | static inline void pi_clear_sn(struct pi_desc *pi_desc) |
527 | { | |
528 | return clear_bit(POSTED_INTR_SN, | |
529 | (unsigned long *)&pi_desc->control); | |
530 | } | |
531 | ||
532 | static inline void pi_set_sn(struct pi_desc *pi_desc) | |
533 | { | |
534 | return set_bit(POSTED_INTR_SN, | |
535 | (unsigned long *)&pi_desc->control); | |
536 | } | |
537 | ||
ad361091 PB |
538 | static inline void pi_clear_on(struct pi_desc *pi_desc) |
539 | { | |
540 | clear_bit(POSTED_INTR_ON, | |
541 | (unsigned long *)&pi_desc->control); | |
542 | } | |
543 | ||
ebbfc765 FW |
544 | static inline int pi_test_on(struct pi_desc *pi_desc) |
545 | { | |
546 | return test_bit(POSTED_INTR_ON, | |
547 | (unsigned long *)&pi_desc->control); | |
548 | } | |
549 | ||
550 | static inline int pi_test_sn(struct pi_desc *pi_desc) | |
551 | { | |
552 | return test_bit(POSTED_INTR_SN, | |
553 | (unsigned long *)&pi_desc->control); | |
554 | } | |
555 | ||
a2fa3e9f | 556 | struct vcpu_vmx { |
fb3f0f51 | 557 | struct kvm_vcpu vcpu; |
313dbd49 | 558 | unsigned long host_rsp; |
29bd8a78 | 559 | u8 fail; |
9d58b931 | 560 | bool nmi_known_unmasked; |
51aa01d1 | 561 | u32 exit_intr_info; |
1155f76a | 562 | u32 idt_vectoring_info; |
6de12732 | 563 | ulong rflags; |
26bb0981 | 564 | struct shared_msr_entry *guest_msrs; |
a2fa3e9f GH |
565 | int nmsrs; |
566 | int save_nmsrs; | |
a547c6db | 567 | unsigned long host_idt_base; |
a2fa3e9f | 568 | #ifdef CONFIG_X86_64 |
44ea2b17 AK |
569 | u64 msr_host_kernel_gs_base; |
570 | u64 msr_guest_kernel_gs_base; | |
a2fa3e9f | 571 | #endif |
2961e876 GN |
572 | u32 vm_entry_controls_shadow; |
573 | u32 vm_exit_controls_shadow; | |
d462b819 NHE |
574 | /* |
575 | * loaded_vmcs points to the VMCS currently used in this vcpu. For a | |
576 | * non-nested (L1) guest, it always points to vmcs01. For a nested | |
577 | * guest (L2), it points to a different VMCS. | |
578 | */ | |
579 | struct loaded_vmcs vmcs01; | |
580 | struct loaded_vmcs *loaded_vmcs; | |
581 | bool __launched; /* temporary, used in vmx_vcpu_run */ | |
61d2ef2c AK |
582 | struct msr_autoload { |
583 | unsigned nr; | |
584 | struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS]; | |
585 | struct vmx_msr_entry host[NR_AUTOLOAD_MSRS]; | |
586 | } msr_autoload; | |
a2fa3e9f GH |
587 | struct { |
588 | int loaded; | |
589 | u16 fs_sel, gs_sel, ldt_sel; | |
b2da15ac AK |
590 | #ifdef CONFIG_X86_64 |
591 | u16 ds_sel, es_sel; | |
592 | #endif | |
152d3f2f LV |
593 | int gs_ldt_reload_needed; |
594 | int fs_reload_needed; | |
da8999d3 | 595 | u64 msr_host_bndcfgs; |
d974baa3 | 596 | unsigned long vmcs_host_cr4; /* May not match real cr4 */ |
d77c26fc | 597 | } host_state; |
9c8cba37 | 598 | struct { |
7ffd92c5 | 599 | int vm86_active; |
78ac8b47 | 600 | ulong save_rflags; |
f5f7b2fe AK |
601 | struct kvm_segment segs[8]; |
602 | } rmode; | |
603 | struct { | |
604 | u32 bitmask; /* 4 bits per segment (1 bit per field) */ | |
7ffd92c5 AK |
605 | struct kvm_save_segment { |
606 | u16 selector; | |
607 | unsigned long base; | |
608 | u32 limit; | |
609 | u32 ar; | |
f5f7b2fe | 610 | } seg[8]; |
2fb92db1 | 611 | } segment_cache; |
2384d2b3 | 612 | int vpid; |
04fa4d32 | 613 | bool emulation_required; |
3b86cd99 | 614 | |
a0861c02 | 615 | u32 exit_reason; |
4e47c7a6 | 616 | |
01e439be YZ |
617 | /* Posted interrupt descriptor */ |
618 | struct pi_desc pi_desc; | |
619 | ||
ec378aee NHE |
620 | /* Support for a guest hypervisor (nested VMX) */ |
621 | struct nested_vmx nested; | |
a7653ecd RK |
622 | |
623 | /* Dynamic PLE window. */ | |
624 | int ple_window; | |
625 | bool ple_window_dirty; | |
843e4330 KH |
626 | |
627 | /* Support for PML */ | |
628 | #define PML_ENTITY_NUM 512 | |
629 | struct page *pml_pg; | |
2680d6da | 630 | |
64672c95 YJ |
631 | /* apic deadline value in host tsc */ |
632 | u64 hv_deadline_tsc; | |
633 | ||
2680d6da | 634 | u64 current_tsc_ratio; |
1be0e61c XG |
635 | |
636 | bool guest_pkru_valid; | |
637 | u32 guest_pkru; | |
638 | u32 host_pkru; | |
3b84080b | 639 | |
37e4c997 HZ |
640 | /* |
641 | * Only bits masked by msr_ia32_feature_control_valid_bits can be set in | |
642 | * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included | |
643 | * in msr_ia32_feature_control_valid_bits. | |
644 | */ | |
3b84080b | 645 | u64 msr_ia32_feature_control; |
37e4c997 | 646 | u64 msr_ia32_feature_control_valid_bits; |
a2fa3e9f GH |
647 | }; |
648 | ||
2fb92db1 AK |
649 | enum segment_cache_field { |
650 | SEG_FIELD_SEL = 0, | |
651 | SEG_FIELD_BASE = 1, | |
652 | SEG_FIELD_LIMIT = 2, | |
653 | SEG_FIELD_AR = 3, | |
654 | ||
655 | SEG_FIELD_NR = 4 | |
656 | }; | |
657 | ||
a2fa3e9f GH |
658 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) |
659 | { | |
fb3f0f51 | 660 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
661 | } |
662 | ||
efc64404 FW |
663 | static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu) |
664 | { | |
665 | return &(to_vmx(vcpu)->pi_desc); | |
666 | } | |
667 | ||
22bd0358 NHE |
668 | #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x) |
669 | #define FIELD(number, name) [number] = VMCS12_OFFSET(name) | |
670 | #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \ | |
671 | [number##_HIGH] = VMCS12_OFFSET(name)+4 | |
672 | ||
4607c2d7 | 673 | |
fe2b201b | 674 | static unsigned long shadow_read_only_fields[] = { |
4607c2d7 AG |
675 | /* |
676 | * We do NOT shadow fields that are modified when L0 | |
677 | * traps and emulates any vmx instruction (e.g. VMPTRLD, | |
678 | * VMXON...) executed by L1. | |
679 | * For example, VM_INSTRUCTION_ERROR is read | |
680 | * by L1 if a vmx instruction fails (part of the error path). | |
681 | * Note the code assumes this logic. If for some reason | |
682 | * we start shadowing these fields then we need to | |
683 | * force a shadow sync when L0 emulates vmx instructions | |
684 | * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified | |
685 | * by nested_vmx_failValid) | |
686 | */ | |
687 | VM_EXIT_REASON, | |
688 | VM_EXIT_INTR_INFO, | |
689 | VM_EXIT_INSTRUCTION_LEN, | |
690 | IDT_VECTORING_INFO_FIELD, | |
691 | IDT_VECTORING_ERROR_CODE, | |
692 | VM_EXIT_INTR_ERROR_CODE, | |
693 | EXIT_QUALIFICATION, | |
694 | GUEST_LINEAR_ADDRESS, | |
695 | GUEST_PHYSICAL_ADDRESS | |
696 | }; | |
fe2b201b | 697 | static int max_shadow_read_only_fields = |
4607c2d7 AG |
698 | ARRAY_SIZE(shadow_read_only_fields); |
699 | ||
fe2b201b | 700 | static unsigned long shadow_read_write_fields[] = { |
a7c0b07d | 701 | TPR_THRESHOLD, |
4607c2d7 AG |
702 | GUEST_RIP, |
703 | GUEST_RSP, | |
704 | GUEST_CR0, | |
705 | GUEST_CR3, | |
706 | GUEST_CR4, | |
707 | GUEST_INTERRUPTIBILITY_INFO, | |
708 | GUEST_RFLAGS, | |
709 | GUEST_CS_SELECTOR, | |
710 | GUEST_CS_AR_BYTES, | |
711 | GUEST_CS_LIMIT, | |
712 | GUEST_CS_BASE, | |
713 | GUEST_ES_BASE, | |
36be0b9d | 714 | GUEST_BNDCFGS, |
4607c2d7 AG |
715 | CR0_GUEST_HOST_MASK, |
716 | CR0_READ_SHADOW, | |
717 | CR4_READ_SHADOW, | |
718 | TSC_OFFSET, | |
719 | EXCEPTION_BITMAP, | |
720 | CPU_BASED_VM_EXEC_CONTROL, | |
721 | VM_ENTRY_EXCEPTION_ERROR_CODE, | |
722 | VM_ENTRY_INTR_INFO_FIELD, | |
723 | VM_ENTRY_INSTRUCTION_LEN, | |
724 | VM_ENTRY_EXCEPTION_ERROR_CODE, | |
725 | HOST_FS_BASE, | |
726 | HOST_GS_BASE, | |
727 | HOST_FS_SELECTOR, | |
728 | HOST_GS_SELECTOR | |
729 | }; | |
fe2b201b | 730 | static int max_shadow_read_write_fields = |
4607c2d7 AG |
731 | ARRAY_SIZE(shadow_read_write_fields); |
732 | ||
772e0318 | 733 | static const unsigned short vmcs_field_to_offset_table[] = { |
22bd0358 | 734 | FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id), |
705699a1 | 735 | FIELD(POSTED_INTR_NV, posted_intr_nv), |
22bd0358 NHE |
736 | FIELD(GUEST_ES_SELECTOR, guest_es_selector), |
737 | FIELD(GUEST_CS_SELECTOR, guest_cs_selector), | |
738 | FIELD(GUEST_SS_SELECTOR, guest_ss_selector), | |
739 | FIELD(GUEST_DS_SELECTOR, guest_ds_selector), | |
740 | FIELD(GUEST_FS_SELECTOR, guest_fs_selector), | |
741 | FIELD(GUEST_GS_SELECTOR, guest_gs_selector), | |
742 | FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector), | |
743 | FIELD(GUEST_TR_SELECTOR, guest_tr_selector), | |
608406e2 | 744 | FIELD(GUEST_INTR_STATUS, guest_intr_status), |
22bd0358 NHE |
745 | FIELD(HOST_ES_SELECTOR, host_es_selector), |
746 | FIELD(HOST_CS_SELECTOR, host_cs_selector), | |
747 | FIELD(HOST_SS_SELECTOR, host_ss_selector), | |
748 | FIELD(HOST_DS_SELECTOR, host_ds_selector), | |
749 | FIELD(HOST_FS_SELECTOR, host_fs_selector), | |
750 | FIELD(HOST_GS_SELECTOR, host_gs_selector), | |
751 | FIELD(HOST_TR_SELECTOR, host_tr_selector), | |
752 | FIELD64(IO_BITMAP_A, io_bitmap_a), | |
753 | FIELD64(IO_BITMAP_B, io_bitmap_b), | |
754 | FIELD64(MSR_BITMAP, msr_bitmap), | |
755 | FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr), | |
756 | FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr), | |
757 | FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr), | |
758 | FIELD64(TSC_OFFSET, tsc_offset), | |
759 | FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr), | |
760 | FIELD64(APIC_ACCESS_ADDR, apic_access_addr), | |
705699a1 | 761 | FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr), |
22bd0358 | 762 | FIELD64(EPT_POINTER, ept_pointer), |
608406e2 WV |
763 | FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0), |
764 | FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1), | |
765 | FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2), | |
766 | FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3), | |
81dc01f7 | 767 | FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap), |
22bd0358 NHE |
768 | FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address), |
769 | FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer), | |
770 | FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl), | |
771 | FIELD64(GUEST_IA32_PAT, guest_ia32_pat), | |
772 | FIELD64(GUEST_IA32_EFER, guest_ia32_efer), | |
773 | FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl), | |
774 | FIELD64(GUEST_PDPTR0, guest_pdptr0), | |
775 | FIELD64(GUEST_PDPTR1, guest_pdptr1), | |
776 | FIELD64(GUEST_PDPTR2, guest_pdptr2), | |
777 | FIELD64(GUEST_PDPTR3, guest_pdptr3), | |
36be0b9d | 778 | FIELD64(GUEST_BNDCFGS, guest_bndcfgs), |
22bd0358 NHE |
779 | FIELD64(HOST_IA32_PAT, host_ia32_pat), |
780 | FIELD64(HOST_IA32_EFER, host_ia32_efer), | |
781 | FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl), | |
782 | FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control), | |
783 | FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control), | |
784 | FIELD(EXCEPTION_BITMAP, exception_bitmap), | |
785 | FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask), | |
786 | FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match), | |
787 | FIELD(CR3_TARGET_COUNT, cr3_target_count), | |
788 | FIELD(VM_EXIT_CONTROLS, vm_exit_controls), | |
789 | FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count), | |
790 | FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count), | |
791 | FIELD(VM_ENTRY_CONTROLS, vm_entry_controls), | |
792 | FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count), | |
793 | FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field), | |
794 | FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code), | |
795 | FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len), | |
796 | FIELD(TPR_THRESHOLD, tpr_threshold), | |
797 | FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control), | |
798 | FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error), | |
799 | FIELD(VM_EXIT_REASON, vm_exit_reason), | |
800 | FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info), | |
801 | FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code), | |
802 | FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field), | |
803 | FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code), | |
804 | FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len), | |
805 | FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info), | |
806 | FIELD(GUEST_ES_LIMIT, guest_es_limit), | |
807 | FIELD(GUEST_CS_LIMIT, guest_cs_limit), | |
808 | FIELD(GUEST_SS_LIMIT, guest_ss_limit), | |
809 | FIELD(GUEST_DS_LIMIT, guest_ds_limit), | |
810 | FIELD(GUEST_FS_LIMIT, guest_fs_limit), | |
811 | FIELD(GUEST_GS_LIMIT, guest_gs_limit), | |
812 | FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit), | |
813 | FIELD(GUEST_TR_LIMIT, guest_tr_limit), | |
814 | FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit), | |
815 | FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit), | |
816 | FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes), | |
817 | FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes), | |
818 | FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes), | |
819 | FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes), | |
820 | FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes), | |
821 | FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes), | |
822 | FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes), | |
823 | FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes), | |
824 | FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info), | |
825 | FIELD(GUEST_ACTIVITY_STATE, guest_activity_state), | |
826 | FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs), | |
827 | FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs), | |
0238ea91 | 828 | FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value), |
22bd0358 NHE |
829 | FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask), |
830 | FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask), | |
831 | FIELD(CR0_READ_SHADOW, cr0_read_shadow), | |
832 | FIELD(CR4_READ_SHADOW, cr4_read_shadow), | |
833 | FIELD(CR3_TARGET_VALUE0, cr3_target_value0), | |
834 | FIELD(CR3_TARGET_VALUE1, cr3_target_value1), | |
835 | FIELD(CR3_TARGET_VALUE2, cr3_target_value2), | |
836 | FIELD(CR3_TARGET_VALUE3, cr3_target_value3), | |
837 | FIELD(EXIT_QUALIFICATION, exit_qualification), | |
838 | FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address), | |
839 | FIELD(GUEST_CR0, guest_cr0), | |
840 | FIELD(GUEST_CR3, guest_cr3), | |
841 | FIELD(GUEST_CR4, guest_cr4), | |
842 | FIELD(GUEST_ES_BASE, guest_es_base), | |
843 | FIELD(GUEST_CS_BASE, guest_cs_base), | |
844 | FIELD(GUEST_SS_BASE, guest_ss_base), | |
845 | FIELD(GUEST_DS_BASE, guest_ds_base), | |
846 | FIELD(GUEST_FS_BASE, guest_fs_base), | |
847 | FIELD(GUEST_GS_BASE, guest_gs_base), | |
848 | FIELD(GUEST_LDTR_BASE, guest_ldtr_base), | |
849 | FIELD(GUEST_TR_BASE, guest_tr_base), | |
850 | FIELD(GUEST_GDTR_BASE, guest_gdtr_base), | |
851 | FIELD(GUEST_IDTR_BASE, guest_idtr_base), | |
852 | FIELD(GUEST_DR7, guest_dr7), | |
853 | FIELD(GUEST_RSP, guest_rsp), | |
854 | FIELD(GUEST_RIP, guest_rip), | |
855 | FIELD(GUEST_RFLAGS, guest_rflags), | |
856 | FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions), | |
857 | FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp), | |
858 | FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip), | |
859 | FIELD(HOST_CR0, host_cr0), | |
860 | FIELD(HOST_CR3, host_cr3), | |
861 | FIELD(HOST_CR4, host_cr4), | |
862 | FIELD(HOST_FS_BASE, host_fs_base), | |
863 | FIELD(HOST_GS_BASE, host_gs_base), | |
864 | FIELD(HOST_TR_BASE, host_tr_base), | |
865 | FIELD(HOST_GDTR_BASE, host_gdtr_base), | |
866 | FIELD(HOST_IDTR_BASE, host_idtr_base), | |
867 | FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp), | |
868 | FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip), | |
869 | FIELD(HOST_RSP, host_rsp), | |
870 | FIELD(HOST_RIP, host_rip), | |
871 | }; | |
22bd0358 NHE |
872 | |
873 | static inline short vmcs_field_to_offset(unsigned long field) | |
874 | { | |
a2ae9df7 PB |
875 | BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX); |
876 | ||
877 | if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) || | |
878 | vmcs_field_to_offset_table[field] == 0) | |
879 | return -ENOENT; | |
880 | ||
22bd0358 NHE |
881 | return vmcs_field_to_offset_table[field]; |
882 | } | |
883 | ||
a9d30f33 NHE |
884 | static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu) |
885 | { | |
4f2777bc | 886 | return to_vmx(vcpu)->nested.cached_vmcs12; |
a9d30f33 NHE |
887 | } |
888 | ||
889 | static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr) | |
890 | { | |
54bf36aa | 891 | struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT); |
32cad84f | 892 | if (is_error_page(page)) |
a9d30f33 | 893 | return NULL; |
32cad84f | 894 | |
a9d30f33 NHE |
895 | return page; |
896 | } | |
897 | ||
898 | static void nested_release_page(struct page *page) | |
899 | { | |
900 | kvm_release_page_dirty(page); | |
901 | } | |
902 | ||
903 | static void nested_release_page_clean(struct page *page) | |
904 | { | |
905 | kvm_release_page_clean(page); | |
906 | } | |
907 | ||
bfd0a56b | 908 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu); |
4e1096d2 | 909 | static u64 construct_eptp(unsigned long root_hpa); |
f53cd63c | 910 | static bool vmx_xsaves_supported(void); |
776e58ea | 911 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr); |
b246dd5d OW |
912 | static void vmx_set_segment(struct kvm_vcpu *vcpu, |
913 | struct kvm_segment *var, int seg); | |
914 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
915 | struct kvm_segment *var, int seg); | |
d99e4152 GN |
916 | static bool guest_state_valid(struct kvm_vcpu *vcpu); |
917 | static u32 vmx_segment_access_rights(struct kvm_segment *var); | |
c3114420 | 918 | static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx); |
16f5b903 | 919 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx); |
a255d479 | 920 | static int alloc_identity_pagetable(struct kvm *kvm); |
75880a01 | 921 | |
6aa8b732 AK |
922 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
923 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
d462b819 NHE |
924 | /* |
925 | * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed | |
926 | * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. | |
927 | */ | |
928 | static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); | |
3444d7da | 929 | static DEFINE_PER_CPU(struct desc_ptr, host_gdt); |
6aa8b732 | 930 | |
bf9f6ac8 FW |
931 | /* |
932 | * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we | |
933 | * can find which vCPU should be waken up. | |
934 | */ | |
935 | static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); | |
936 | static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); | |
937 | ||
23611332 RK |
938 | enum { |
939 | VMX_IO_BITMAP_A, | |
940 | VMX_IO_BITMAP_B, | |
941 | VMX_MSR_BITMAP_LEGACY, | |
942 | VMX_MSR_BITMAP_LONGMODE, | |
943 | VMX_MSR_BITMAP_LEGACY_X2APIC_APICV, | |
944 | VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV, | |
945 | VMX_MSR_BITMAP_LEGACY_X2APIC, | |
946 | VMX_MSR_BITMAP_LONGMODE_X2APIC, | |
947 | VMX_VMREAD_BITMAP, | |
948 | VMX_VMWRITE_BITMAP, | |
949 | VMX_BITMAP_NR | |
950 | }; | |
951 | ||
952 | static unsigned long *vmx_bitmap[VMX_BITMAP_NR]; | |
953 | ||
954 | #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A]) | |
955 | #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B]) | |
956 | #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY]) | |
957 | #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE]) | |
958 | #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV]) | |
959 | #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV]) | |
960 | #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC]) | |
961 | #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC]) | |
962 | #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP]) | |
963 | #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP]) | |
fdef3ad1 | 964 | |
110312c8 | 965 | static bool cpu_has_load_ia32_efer; |
8bf00a52 | 966 | static bool cpu_has_load_perf_global_ctrl; |
110312c8 | 967 | |
2384d2b3 SY |
968 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
969 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
970 | ||
1c3d14fe | 971 | static struct vmcs_config { |
6aa8b732 AK |
972 | int size; |
973 | int order; | |
9ac7e3e8 | 974 | u32 basic_cap; |
6aa8b732 | 975 | u32 revision_id; |
1c3d14fe YS |
976 | u32 pin_based_exec_ctrl; |
977 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 978 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
979 | u32 vmexit_ctrl; |
980 | u32 vmentry_ctrl; | |
981 | } vmcs_config; | |
6aa8b732 | 982 | |
efff9e53 | 983 | static struct vmx_capability { |
d56f546d SY |
984 | u32 ept; |
985 | u32 vpid; | |
986 | } vmx_capability; | |
987 | ||
6aa8b732 AK |
988 | #define VMX_SEGMENT_FIELD(seg) \ |
989 | [VCPU_SREG_##seg] = { \ | |
990 | .selector = GUEST_##seg##_SELECTOR, \ | |
991 | .base = GUEST_##seg##_BASE, \ | |
992 | .limit = GUEST_##seg##_LIMIT, \ | |
993 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
994 | } | |
995 | ||
772e0318 | 996 | static const struct kvm_vmx_segment_field { |
6aa8b732 AK |
997 | unsigned selector; |
998 | unsigned base; | |
999 | unsigned limit; | |
1000 | unsigned ar_bytes; | |
1001 | } kvm_vmx_segment_fields[] = { | |
1002 | VMX_SEGMENT_FIELD(CS), | |
1003 | VMX_SEGMENT_FIELD(DS), | |
1004 | VMX_SEGMENT_FIELD(ES), | |
1005 | VMX_SEGMENT_FIELD(FS), | |
1006 | VMX_SEGMENT_FIELD(GS), | |
1007 | VMX_SEGMENT_FIELD(SS), | |
1008 | VMX_SEGMENT_FIELD(TR), | |
1009 | VMX_SEGMENT_FIELD(LDTR), | |
1010 | }; | |
1011 | ||
26bb0981 AK |
1012 | static u64 host_efer; |
1013 | ||
6de4f3ad AK |
1014 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu); |
1015 | ||
4d56c8a7 | 1016 | /* |
8c06585d | 1017 | * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it |
4d56c8a7 AK |
1018 | * away by decrementing the array size. |
1019 | */ | |
6aa8b732 | 1020 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 1021 | #ifdef CONFIG_X86_64 |
44ea2b17 | 1022 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, |
6aa8b732 | 1023 | #endif |
8c06585d | 1024 | MSR_EFER, MSR_TSC_AUX, MSR_STAR, |
6aa8b732 | 1025 | }; |
6aa8b732 | 1026 | |
5bb16016 | 1027 | static inline bool is_exception_n(u32 intr_info, u8 vector) |
6aa8b732 AK |
1028 | { |
1029 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
1030 | INTR_INFO_VALID_MASK)) == | |
5bb16016 JK |
1031 | (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK); |
1032 | } | |
1033 | ||
6f05485d JK |
1034 | static inline bool is_debug(u32 intr_info) |
1035 | { | |
1036 | return is_exception_n(intr_info, DB_VECTOR); | |
1037 | } | |
1038 | ||
1039 | static inline bool is_breakpoint(u32 intr_info) | |
1040 | { | |
1041 | return is_exception_n(intr_info, BP_VECTOR); | |
1042 | } | |
1043 | ||
5bb16016 JK |
1044 | static inline bool is_page_fault(u32 intr_info) |
1045 | { | |
1046 | return is_exception_n(intr_info, PF_VECTOR); | |
6aa8b732 AK |
1047 | } |
1048 | ||
31299944 | 1049 | static inline bool is_no_device(u32 intr_info) |
2ab455cc | 1050 | { |
5bb16016 | 1051 | return is_exception_n(intr_info, NM_VECTOR); |
2ab455cc AL |
1052 | } |
1053 | ||
31299944 | 1054 | static inline bool is_invalid_opcode(u32 intr_info) |
7aa81cc0 | 1055 | { |
5bb16016 | 1056 | return is_exception_n(intr_info, UD_VECTOR); |
7aa81cc0 AL |
1057 | } |
1058 | ||
31299944 | 1059 | static inline bool is_external_interrupt(u32 intr_info) |
6aa8b732 AK |
1060 | { |
1061 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
1062 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
1063 | } | |
1064 | ||
31299944 | 1065 | static inline bool is_machine_check(u32 intr_info) |
a0861c02 AK |
1066 | { |
1067 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
1068 | INTR_INFO_VALID_MASK)) == | |
1069 | (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK); | |
1070 | } | |
1071 | ||
31299944 | 1072 | static inline bool cpu_has_vmx_msr_bitmap(void) |
25c5f225 | 1073 | { |
04547156 | 1074 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; |
25c5f225 SY |
1075 | } |
1076 | ||
31299944 | 1077 | static inline bool cpu_has_vmx_tpr_shadow(void) |
6e5d865c | 1078 | { |
04547156 | 1079 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; |
6e5d865c YS |
1080 | } |
1081 | ||
35754c98 | 1082 | static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu) |
6e5d865c | 1083 | { |
35754c98 | 1084 | return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu); |
6e5d865c YS |
1085 | } |
1086 | ||
31299944 | 1087 | static inline bool cpu_has_secondary_exec_ctrls(void) |
f78e0e2e | 1088 | { |
04547156 SY |
1089 | return vmcs_config.cpu_based_exec_ctrl & |
1090 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
f78e0e2e SY |
1091 | } |
1092 | ||
774ead3a | 1093 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 1094 | { |
04547156 SY |
1095 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1096 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
1097 | } | |
1098 | ||
8d14695f YZ |
1099 | static inline bool cpu_has_vmx_virtualize_x2apic_mode(void) |
1100 | { | |
1101 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1102 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
1103 | } | |
1104 | ||
83d4c286 YZ |
1105 | static inline bool cpu_has_vmx_apic_register_virt(void) |
1106 | { | |
1107 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1108 | SECONDARY_EXEC_APIC_REGISTER_VIRT; | |
1109 | } | |
1110 | ||
c7c9c56c YZ |
1111 | static inline bool cpu_has_vmx_virtual_intr_delivery(void) |
1112 | { | |
1113 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1114 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY; | |
1115 | } | |
1116 | ||
64672c95 YJ |
1117 | /* |
1118 | * Comment's format: document - errata name - stepping - processor name. | |
1119 | * Refer from | |
1120 | * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp | |
1121 | */ | |
1122 | static u32 vmx_preemption_cpu_tfms[] = { | |
1123 | /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ | |
1124 | 0x000206E6, | |
1125 | /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ | |
1126 | /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ | |
1127 | /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
1128 | 0x00020652, | |
1129 | /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
1130 | 0x00020655, | |
1131 | /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ | |
1132 | /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ | |
1133 | /* | |
1134 | * 320767.pdf - AAP86 - B1 - | |
1135 | * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile | |
1136 | */ | |
1137 | 0x000106E5, | |
1138 | /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ | |
1139 | 0x000106A0, | |
1140 | /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ | |
1141 | 0x000106A1, | |
1142 | /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ | |
1143 | 0x000106A4, | |
1144 | /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ | |
1145 | /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ | |
1146 | /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ | |
1147 | 0x000106A5, | |
1148 | }; | |
1149 | ||
1150 | static inline bool cpu_has_broken_vmx_preemption_timer(void) | |
1151 | { | |
1152 | u32 eax = cpuid_eax(0x00000001), i; | |
1153 | ||
1154 | /* Clear the reserved bits */ | |
1155 | eax &= ~(0x3U << 14 | 0xfU << 28); | |
03f6a22a | 1156 | for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) |
64672c95 YJ |
1157 | if (eax == vmx_preemption_cpu_tfms[i]) |
1158 | return true; | |
1159 | ||
1160 | return false; | |
1161 | } | |
1162 | ||
1163 | static inline bool cpu_has_vmx_preemption_timer(void) | |
1164 | { | |
64672c95 YJ |
1165 | return vmcs_config.pin_based_exec_ctrl & |
1166 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1167 | } | |
1168 | ||
01e439be YZ |
1169 | static inline bool cpu_has_vmx_posted_intr(void) |
1170 | { | |
d6a858d1 PB |
1171 | return IS_ENABLED(CONFIG_X86_LOCAL_APIC) && |
1172 | vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR; | |
01e439be YZ |
1173 | } |
1174 | ||
1175 | static inline bool cpu_has_vmx_apicv(void) | |
1176 | { | |
1177 | return cpu_has_vmx_apic_register_virt() && | |
1178 | cpu_has_vmx_virtual_intr_delivery() && | |
1179 | cpu_has_vmx_posted_intr(); | |
1180 | } | |
1181 | ||
04547156 SY |
1182 | static inline bool cpu_has_vmx_flexpriority(void) |
1183 | { | |
1184 | return cpu_has_vmx_tpr_shadow() && | |
1185 | cpu_has_vmx_virtualize_apic_accesses(); | |
f78e0e2e SY |
1186 | } |
1187 | ||
e799794e MT |
1188 | static inline bool cpu_has_vmx_ept_execute_only(void) |
1189 | { | |
31299944 | 1190 | return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT; |
e799794e MT |
1191 | } |
1192 | ||
e799794e MT |
1193 | static inline bool cpu_has_vmx_ept_2m_page(void) |
1194 | { | |
31299944 | 1195 | return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT; |
e799794e MT |
1196 | } |
1197 | ||
878403b7 SY |
1198 | static inline bool cpu_has_vmx_ept_1g_page(void) |
1199 | { | |
31299944 | 1200 | return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT; |
878403b7 SY |
1201 | } |
1202 | ||
4bc9b982 SY |
1203 | static inline bool cpu_has_vmx_ept_4levels(void) |
1204 | { | |
1205 | return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT; | |
1206 | } | |
1207 | ||
83c3a331 XH |
1208 | static inline bool cpu_has_vmx_ept_ad_bits(void) |
1209 | { | |
1210 | return vmx_capability.ept & VMX_EPT_AD_BIT; | |
1211 | } | |
1212 | ||
31299944 | 1213 | static inline bool cpu_has_vmx_invept_context(void) |
d56f546d | 1214 | { |
31299944 | 1215 | return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT; |
d56f546d SY |
1216 | } |
1217 | ||
31299944 | 1218 | static inline bool cpu_has_vmx_invept_global(void) |
d56f546d | 1219 | { |
31299944 | 1220 | return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; |
d56f546d SY |
1221 | } |
1222 | ||
518c8aee GJ |
1223 | static inline bool cpu_has_vmx_invvpid_single(void) |
1224 | { | |
1225 | return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT; | |
1226 | } | |
1227 | ||
b9d762fa GJ |
1228 | static inline bool cpu_has_vmx_invvpid_global(void) |
1229 | { | |
1230 | return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; | |
1231 | } | |
1232 | ||
08d839c4 WL |
1233 | static inline bool cpu_has_vmx_invvpid(void) |
1234 | { | |
1235 | return vmx_capability.vpid & VMX_VPID_INVVPID_BIT; | |
1236 | } | |
1237 | ||
31299944 | 1238 | static inline bool cpu_has_vmx_ept(void) |
d56f546d | 1239 | { |
04547156 SY |
1240 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1241 | SECONDARY_EXEC_ENABLE_EPT; | |
d56f546d SY |
1242 | } |
1243 | ||
31299944 | 1244 | static inline bool cpu_has_vmx_unrestricted_guest(void) |
3a624e29 NK |
1245 | { |
1246 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1247 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
1248 | } | |
1249 | ||
31299944 | 1250 | static inline bool cpu_has_vmx_ple(void) |
4b8d54f9 ZE |
1251 | { |
1252 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1253 | SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
1254 | } | |
1255 | ||
9ac7e3e8 JD |
1256 | static inline bool cpu_has_vmx_basic_inout(void) |
1257 | { | |
1258 | return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT); | |
1259 | } | |
1260 | ||
35754c98 | 1261 | static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) |
f78e0e2e | 1262 | { |
35754c98 | 1263 | return flexpriority_enabled && lapic_in_kernel(vcpu); |
f78e0e2e SY |
1264 | } |
1265 | ||
31299944 | 1266 | static inline bool cpu_has_vmx_vpid(void) |
2384d2b3 | 1267 | { |
04547156 SY |
1268 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1269 | SECONDARY_EXEC_ENABLE_VPID; | |
2384d2b3 SY |
1270 | } |
1271 | ||
31299944 | 1272 | static inline bool cpu_has_vmx_rdtscp(void) |
4e47c7a6 SY |
1273 | { |
1274 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1275 | SECONDARY_EXEC_RDTSCP; | |
1276 | } | |
1277 | ||
ad756a16 MJ |
1278 | static inline bool cpu_has_vmx_invpcid(void) |
1279 | { | |
1280 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1281 | SECONDARY_EXEC_ENABLE_INVPCID; | |
1282 | } | |
1283 | ||
f5f48ee1 SY |
1284 | static inline bool cpu_has_vmx_wbinvd_exit(void) |
1285 | { | |
1286 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1287 | SECONDARY_EXEC_WBINVD_EXITING; | |
1288 | } | |
1289 | ||
abc4fc58 AG |
1290 | static inline bool cpu_has_vmx_shadow_vmcs(void) |
1291 | { | |
1292 | u64 vmx_msr; | |
1293 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
1294 | /* check if the cpu supports writing r/o exit information fields */ | |
1295 | if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) | |
1296 | return false; | |
1297 | ||
1298 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1299 | SECONDARY_EXEC_SHADOW_VMCS; | |
1300 | } | |
1301 | ||
843e4330 KH |
1302 | static inline bool cpu_has_vmx_pml(void) |
1303 | { | |
1304 | return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML; | |
1305 | } | |
1306 | ||
64903d61 HZ |
1307 | static inline bool cpu_has_vmx_tsc_scaling(void) |
1308 | { | |
1309 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1310 | SECONDARY_EXEC_TSC_SCALING; | |
1311 | } | |
1312 | ||
04547156 SY |
1313 | static inline bool report_flexpriority(void) |
1314 | { | |
1315 | return flexpriority_enabled; | |
1316 | } | |
1317 | ||
fe3ef05c NHE |
1318 | static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit) |
1319 | { | |
1320 | return vmcs12->cpu_based_vm_exec_control & bit; | |
1321 | } | |
1322 | ||
1323 | static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit) | |
1324 | { | |
1325 | return (vmcs12->cpu_based_vm_exec_control & | |
1326 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && | |
1327 | (vmcs12->secondary_vm_exec_control & bit); | |
1328 | } | |
1329 | ||
f5c4368f | 1330 | static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12) |
644d711a NHE |
1331 | { |
1332 | return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS; | |
1333 | } | |
1334 | ||
f4124500 JK |
1335 | static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12) |
1336 | { | |
1337 | return vmcs12->pin_based_vm_exec_control & | |
1338 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1339 | } | |
1340 | ||
155a97a3 NHE |
1341 | static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12) |
1342 | { | |
1343 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT); | |
1344 | } | |
1345 | ||
81dc01f7 WL |
1346 | static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12) |
1347 | { | |
1348 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) && | |
1349 | vmx_xsaves_supported(); | |
1350 | } | |
1351 | ||
f2b93280 WV |
1352 | static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12) |
1353 | { | |
1354 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); | |
1355 | } | |
1356 | ||
5c614b35 WL |
1357 | static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12) |
1358 | { | |
1359 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID); | |
1360 | } | |
1361 | ||
82f0dd4b WV |
1362 | static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12) |
1363 | { | |
1364 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT); | |
1365 | } | |
1366 | ||
608406e2 WV |
1367 | static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12) |
1368 | { | |
1369 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
1370 | } | |
1371 | ||
705699a1 WV |
1372 | static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12) |
1373 | { | |
1374 | return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR; | |
1375 | } | |
1376 | ||
ef85b673 | 1377 | static inline bool is_nmi(u32 intr_info) |
644d711a NHE |
1378 | { |
1379 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
ef85b673 | 1380 | == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK); |
644d711a NHE |
1381 | } |
1382 | ||
533558bc JK |
1383 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
1384 | u32 exit_intr_info, | |
1385 | unsigned long exit_qualification); | |
7c177938 NHE |
1386 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, |
1387 | struct vmcs12 *vmcs12, | |
1388 | u32 reason, unsigned long qualification); | |
1389 | ||
8b9cf98c | 1390 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
1391 | { |
1392 | int i; | |
1393 | ||
a2fa3e9f | 1394 | for (i = 0; i < vmx->nmsrs; ++i) |
26bb0981 | 1395 | if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) |
a75beee6 ED |
1396 | return i; |
1397 | return -1; | |
1398 | } | |
1399 | ||
2384d2b3 SY |
1400 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
1401 | { | |
1402 | struct { | |
1403 | u64 vpid : 16; | |
1404 | u64 rsvd : 48; | |
1405 | u64 gva; | |
1406 | } operand = { vpid, 0, gva }; | |
1407 | ||
4ecac3fd | 1408 | asm volatile (__ex(ASM_VMX_INVVPID) |
2384d2b3 SY |
1409 | /* CF==1 or ZF==1 --> rc = -1 */ |
1410 | "; ja 1f ; ud2 ; 1:" | |
1411 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
1412 | } | |
1413 | ||
1439442c SY |
1414 | static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
1415 | { | |
1416 | struct { | |
1417 | u64 eptp, gpa; | |
1418 | } operand = {eptp, gpa}; | |
1419 | ||
4ecac3fd | 1420 | asm volatile (__ex(ASM_VMX_INVEPT) |
1439442c SY |
1421 | /* CF==1 or ZF==1 --> rc = -1 */ |
1422 | "; ja 1f ; ud2 ; 1:\n" | |
1423 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
1424 | } | |
1425 | ||
26bb0981 | 1426 | static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
1427 | { |
1428 | int i; | |
1429 | ||
8b9cf98c | 1430 | i = __find_msr_index(vmx, msr); |
a75beee6 | 1431 | if (i >= 0) |
a2fa3e9f | 1432 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 1433 | return NULL; |
7725f0ba AK |
1434 | } |
1435 | ||
6aa8b732 AK |
1436 | static void vmcs_clear(struct vmcs *vmcs) |
1437 | { | |
1438 | u64 phys_addr = __pa(vmcs); | |
1439 | u8 error; | |
1440 | ||
4ecac3fd | 1441 | asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
16d8f72f | 1442 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
6aa8b732 AK |
1443 | : "cc", "memory"); |
1444 | if (error) | |
1445 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
1446 | vmcs, phys_addr); | |
1447 | } | |
1448 | ||
d462b819 NHE |
1449 | static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) |
1450 | { | |
1451 | vmcs_clear(loaded_vmcs->vmcs); | |
355f4fb1 JM |
1452 | if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) |
1453 | vmcs_clear(loaded_vmcs->shadow_vmcs); | |
d462b819 NHE |
1454 | loaded_vmcs->cpu = -1; |
1455 | loaded_vmcs->launched = 0; | |
1456 | } | |
1457 | ||
7725b894 DX |
1458 | static void vmcs_load(struct vmcs *vmcs) |
1459 | { | |
1460 | u64 phys_addr = __pa(vmcs); | |
1461 | u8 error; | |
1462 | ||
1463 | asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" | |
16d8f72f | 1464 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
7725b894 DX |
1465 | : "cc", "memory"); |
1466 | if (error) | |
2844d849 | 1467 | printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n", |
7725b894 DX |
1468 | vmcs, phys_addr); |
1469 | } | |
1470 | ||
2965faa5 | 1471 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
1472 | /* |
1473 | * This bitmap is used to indicate whether the vmclear | |
1474 | * operation is enabled on all cpus. All disabled by | |
1475 | * default. | |
1476 | */ | |
1477 | static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE; | |
1478 | ||
1479 | static inline void crash_enable_local_vmclear(int cpu) | |
1480 | { | |
1481 | cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1482 | } | |
1483 | ||
1484 | static inline void crash_disable_local_vmclear(int cpu) | |
1485 | { | |
1486 | cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1487 | } | |
1488 | ||
1489 | static inline int crash_local_vmclear_enabled(int cpu) | |
1490 | { | |
1491 | return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1492 | } | |
1493 | ||
1494 | static void crash_vmclear_local_loaded_vmcss(void) | |
1495 | { | |
1496 | int cpu = raw_smp_processor_id(); | |
1497 | struct loaded_vmcs *v; | |
1498 | ||
1499 | if (!crash_local_vmclear_enabled(cpu)) | |
1500 | return; | |
1501 | ||
1502 | list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), | |
1503 | loaded_vmcss_on_cpu_link) | |
1504 | vmcs_clear(v->vmcs); | |
1505 | } | |
1506 | #else | |
1507 | static inline void crash_enable_local_vmclear(int cpu) { } | |
1508 | static inline void crash_disable_local_vmclear(int cpu) { } | |
2965faa5 | 1509 | #endif /* CONFIG_KEXEC_CORE */ |
8f536b76 | 1510 | |
d462b819 | 1511 | static void __loaded_vmcs_clear(void *arg) |
6aa8b732 | 1512 | { |
d462b819 | 1513 | struct loaded_vmcs *loaded_vmcs = arg; |
d3b2c338 | 1514 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 1515 | |
d462b819 NHE |
1516 | if (loaded_vmcs->cpu != cpu) |
1517 | return; /* vcpu migration can race with cpu offline */ | |
1518 | if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) | |
6aa8b732 | 1519 | per_cpu(current_vmcs, cpu) = NULL; |
8f536b76 | 1520 | crash_disable_local_vmclear(cpu); |
d462b819 | 1521 | list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); |
5a560f8b XG |
1522 | |
1523 | /* | |
1524 | * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link | |
1525 | * is before setting loaded_vmcs->vcpu to -1 which is done in | |
1526 | * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist | |
1527 | * then adds the vmcs into percpu list before it is deleted. | |
1528 | */ | |
1529 | smp_wmb(); | |
1530 | ||
d462b819 | 1531 | loaded_vmcs_init(loaded_vmcs); |
8f536b76 | 1532 | crash_enable_local_vmclear(cpu); |
6aa8b732 AK |
1533 | } |
1534 | ||
d462b819 | 1535 | static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) |
8d0be2b3 | 1536 | { |
e6c7d321 XG |
1537 | int cpu = loaded_vmcs->cpu; |
1538 | ||
1539 | if (cpu != -1) | |
1540 | smp_call_function_single(cpu, | |
1541 | __loaded_vmcs_clear, loaded_vmcs, 1); | |
8d0be2b3 AK |
1542 | } |
1543 | ||
dd5f5341 | 1544 | static inline void vpid_sync_vcpu_single(int vpid) |
2384d2b3 | 1545 | { |
dd5f5341 | 1546 | if (vpid == 0) |
2384d2b3 SY |
1547 | return; |
1548 | ||
518c8aee | 1549 | if (cpu_has_vmx_invvpid_single()) |
dd5f5341 | 1550 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0); |
2384d2b3 SY |
1551 | } |
1552 | ||
b9d762fa GJ |
1553 | static inline void vpid_sync_vcpu_global(void) |
1554 | { | |
1555 | if (cpu_has_vmx_invvpid_global()) | |
1556 | __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0); | |
1557 | } | |
1558 | ||
dd5f5341 | 1559 | static inline void vpid_sync_context(int vpid) |
b9d762fa GJ |
1560 | { |
1561 | if (cpu_has_vmx_invvpid_single()) | |
dd5f5341 | 1562 | vpid_sync_vcpu_single(vpid); |
b9d762fa GJ |
1563 | else |
1564 | vpid_sync_vcpu_global(); | |
1565 | } | |
1566 | ||
1439442c SY |
1567 | static inline void ept_sync_global(void) |
1568 | { | |
1569 | if (cpu_has_vmx_invept_global()) | |
1570 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); | |
1571 | } | |
1572 | ||
1573 | static inline void ept_sync_context(u64 eptp) | |
1574 | { | |
089d034e | 1575 | if (enable_ept) { |
1439442c SY |
1576 | if (cpu_has_vmx_invept_context()) |
1577 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
1578 | else | |
1579 | ept_sync_global(); | |
1580 | } | |
1581 | } | |
1582 | ||
8a86aea9 PB |
1583 | static __always_inline void vmcs_check16(unsigned long field) |
1584 | { | |
1585 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000, | |
1586 | "16-bit accessor invalid for 64-bit field"); | |
1587 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1588 | "16-bit accessor invalid for 64-bit high field"); | |
1589 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1590 | "16-bit accessor invalid for 32-bit high field"); | |
1591 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1592 | "16-bit accessor invalid for natural width field"); | |
1593 | } | |
1594 | ||
1595 | static __always_inline void vmcs_check32(unsigned long field) | |
1596 | { | |
1597 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1598 | "32-bit accessor invalid for 16-bit field"); | |
1599 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1600 | "32-bit accessor invalid for natural width field"); | |
1601 | } | |
1602 | ||
1603 | static __always_inline void vmcs_check64(unsigned long field) | |
1604 | { | |
1605 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1606 | "64-bit accessor invalid for 16-bit field"); | |
1607 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1608 | "64-bit accessor invalid for 64-bit high field"); | |
1609 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1610 | "64-bit accessor invalid for 32-bit field"); | |
1611 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1612 | "64-bit accessor invalid for natural width field"); | |
1613 | } | |
1614 | ||
1615 | static __always_inline void vmcs_checkl(unsigned long field) | |
1616 | { | |
1617 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1618 | "Natural width accessor invalid for 16-bit field"); | |
1619 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000, | |
1620 | "Natural width accessor invalid for 64-bit field"); | |
1621 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1622 | "Natural width accessor invalid for 64-bit high field"); | |
1623 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1624 | "Natural width accessor invalid for 32-bit field"); | |
1625 | } | |
1626 | ||
1627 | static __always_inline unsigned long __vmcs_readl(unsigned long field) | |
6aa8b732 | 1628 | { |
5e520e62 | 1629 | unsigned long value; |
6aa8b732 | 1630 | |
5e520e62 AK |
1631 | asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0") |
1632 | : "=a"(value) : "d"(field) : "cc"); | |
6aa8b732 AK |
1633 | return value; |
1634 | } | |
1635 | ||
96304217 | 1636 | static __always_inline u16 vmcs_read16(unsigned long field) |
6aa8b732 | 1637 | { |
8a86aea9 PB |
1638 | vmcs_check16(field); |
1639 | return __vmcs_readl(field); | |
6aa8b732 AK |
1640 | } |
1641 | ||
96304217 | 1642 | static __always_inline u32 vmcs_read32(unsigned long field) |
6aa8b732 | 1643 | { |
8a86aea9 PB |
1644 | vmcs_check32(field); |
1645 | return __vmcs_readl(field); | |
6aa8b732 AK |
1646 | } |
1647 | ||
96304217 | 1648 | static __always_inline u64 vmcs_read64(unsigned long field) |
6aa8b732 | 1649 | { |
8a86aea9 | 1650 | vmcs_check64(field); |
05b3e0c2 | 1651 | #ifdef CONFIG_X86_64 |
8a86aea9 | 1652 | return __vmcs_readl(field); |
6aa8b732 | 1653 | #else |
8a86aea9 | 1654 | return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32); |
6aa8b732 AK |
1655 | #endif |
1656 | } | |
1657 | ||
8a86aea9 PB |
1658 | static __always_inline unsigned long vmcs_readl(unsigned long field) |
1659 | { | |
1660 | vmcs_checkl(field); | |
1661 | return __vmcs_readl(field); | |
1662 | } | |
1663 | ||
e52de1b8 AK |
1664 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
1665 | { | |
1666 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
1667 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
1668 | dump_stack(); | |
1669 | } | |
1670 | ||
8a86aea9 | 1671 | static __always_inline void __vmcs_writel(unsigned long field, unsigned long value) |
6aa8b732 AK |
1672 | { |
1673 | u8 error; | |
1674 | ||
4ecac3fd | 1675 | asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
d77c26fc | 1676 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
1677 | if (unlikely(error)) |
1678 | vmwrite_error(field, value); | |
6aa8b732 AK |
1679 | } |
1680 | ||
8a86aea9 | 1681 | static __always_inline void vmcs_write16(unsigned long field, u16 value) |
6aa8b732 | 1682 | { |
8a86aea9 PB |
1683 | vmcs_check16(field); |
1684 | __vmcs_writel(field, value); | |
6aa8b732 AK |
1685 | } |
1686 | ||
8a86aea9 | 1687 | static __always_inline void vmcs_write32(unsigned long field, u32 value) |
6aa8b732 | 1688 | { |
8a86aea9 PB |
1689 | vmcs_check32(field); |
1690 | __vmcs_writel(field, value); | |
6aa8b732 AK |
1691 | } |
1692 | ||
8a86aea9 | 1693 | static __always_inline void vmcs_write64(unsigned long field, u64 value) |
6aa8b732 | 1694 | { |
8a86aea9 PB |
1695 | vmcs_check64(field); |
1696 | __vmcs_writel(field, value); | |
7682f2d0 | 1697 | #ifndef CONFIG_X86_64 |
6aa8b732 | 1698 | asm volatile (""); |
8a86aea9 | 1699 | __vmcs_writel(field+1, value >> 32); |
6aa8b732 AK |
1700 | #endif |
1701 | } | |
1702 | ||
8a86aea9 | 1703 | static __always_inline void vmcs_writel(unsigned long field, unsigned long value) |
2ab455cc | 1704 | { |
8a86aea9 PB |
1705 | vmcs_checkl(field); |
1706 | __vmcs_writel(field, value); | |
2ab455cc AL |
1707 | } |
1708 | ||
8a86aea9 | 1709 | static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask) |
2ab455cc | 1710 | { |
8a86aea9 PB |
1711 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000, |
1712 | "vmcs_clear_bits does not support 64-bit fields"); | |
1713 | __vmcs_writel(field, __vmcs_readl(field) & ~mask); | |
2ab455cc AL |
1714 | } |
1715 | ||
8a86aea9 | 1716 | static __always_inline void vmcs_set_bits(unsigned long field, u32 mask) |
2ab455cc | 1717 | { |
8a86aea9 PB |
1718 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000, |
1719 | "vmcs_set_bits does not support 64-bit fields"); | |
1720 | __vmcs_writel(field, __vmcs_readl(field) | mask); | |
2ab455cc AL |
1721 | } |
1722 | ||
8391ce44 PB |
1723 | static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx) |
1724 | { | |
1725 | vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS); | |
1726 | } | |
1727 | ||
2961e876 GN |
1728 | static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val) |
1729 | { | |
1730 | vmcs_write32(VM_ENTRY_CONTROLS, val); | |
1731 | vmx->vm_entry_controls_shadow = val; | |
1732 | } | |
1733 | ||
1734 | static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1735 | { | |
1736 | if (vmx->vm_entry_controls_shadow != val) | |
1737 | vm_entry_controls_init(vmx, val); | |
1738 | } | |
1739 | ||
1740 | static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx) | |
1741 | { | |
1742 | return vmx->vm_entry_controls_shadow; | |
1743 | } | |
1744 | ||
1745 | ||
1746 | static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1747 | { | |
1748 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val); | |
1749 | } | |
1750 | ||
1751 | static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1752 | { | |
1753 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val); | |
1754 | } | |
1755 | ||
8391ce44 PB |
1756 | static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx) |
1757 | { | |
1758 | vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS); | |
1759 | } | |
1760 | ||
2961e876 GN |
1761 | static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val) |
1762 | { | |
1763 | vmcs_write32(VM_EXIT_CONTROLS, val); | |
1764 | vmx->vm_exit_controls_shadow = val; | |
1765 | } | |
1766 | ||
1767 | static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1768 | { | |
1769 | if (vmx->vm_exit_controls_shadow != val) | |
1770 | vm_exit_controls_init(vmx, val); | |
1771 | } | |
1772 | ||
1773 | static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx) | |
1774 | { | |
1775 | return vmx->vm_exit_controls_shadow; | |
1776 | } | |
1777 | ||
1778 | ||
1779 | static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1780 | { | |
1781 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val); | |
1782 | } | |
1783 | ||
1784 | static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1785 | { | |
1786 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val); | |
1787 | } | |
1788 | ||
2fb92db1 AK |
1789 | static void vmx_segment_cache_clear(struct vcpu_vmx *vmx) |
1790 | { | |
1791 | vmx->segment_cache.bitmask = 0; | |
1792 | } | |
1793 | ||
1794 | static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, | |
1795 | unsigned field) | |
1796 | { | |
1797 | bool ret; | |
1798 | u32 mask = 1 << (seg * SEG_FIELD_NR + field); | |
1799 | ||
1800 | if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) { | |
1801 | vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS); | |
1802 | vmx->segment_cache.bitmask = 0; | |
1803 | } | |
1804 | ret = vmx->segment_cache.bitmask & mask; | |
1805 | vmx->segment_cache.bitmask |= mask; | |
1806 | return ret; | |
1807 | } | |
1808 | ||
1809 | static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) | |
1810 | { | |
1811 | u16 *p = &vmx->segment_cache.seg[seg].selector; | |
1812 | ||
1813 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) | |
1814 | *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); | |
1815 | return *p; | |
1816 | } | |
1817 | ||
1818 | static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) | |
1819 | { | |
1820 | ulong *p = &vmx->segment_cache.seg[seg].base; | |
1821 | ||
1822 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) | |
1823 | *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); | |
1824 | return *p; | |
1825 | } | |
1826 | ||
1827 | static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) | |
1828 | { | |
1829 | u32 *p = &vmx->segment_cache.seg[seg].limit; | |
1830 | ||
1831 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) | |
1832 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); | |
1833 | return *p; | |
1834 | } | |
1835 | ||
1836 | static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) | |
1837 | { | |
1838 | u32 *p = &vmx->segment_cache.seg[seg].ar; | |
1839 | ||
1840 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) | |
1841 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); | |
1842 | return *p; | |
1843 | } | |
1844 | ||
abd3f2d6 AK |
1845 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
1846 | { | |
1847 | u32 eb; | |
1848 | ||
fd7373cc | 1849 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | |
bd7e5b08 | 1850 | (1u << DB_VECTOR) | (1u << AC_VECTOR); |
fd7373cc JK |
1851 | if ((vcpu->guest_debug & |
1852 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == | |
1853 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) | |
1854 | eb |= 1u << BP_VECTOR; | |
7ffd92c5 | 1855 | if (to_vmx(vcpu)->rmode.vm86_active) |
abd3f2d6 | 1856 | eb = ~0; |
089d034e | 1857 | if (enable_ept) |
1439442c | 1858 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ |
36cf24e0 NHE |
1859 | |
1860 | /* When we are running a nested L2 guest and L1 specified for it a | |
1861 | * certain exception bitmap, we must trap the same exceptions and pass | |
1862 | * them to L1. When running L2, we will only handle the exceptions | |
1863 | * specified above if L1 did not want them. | |
1864 | */ | |
1865 | if (is_guest_mode(vcpu)) | |
1866 | eb |= get_vmcs12(vcpu)->exception_bitmap; | |
1867 | ||
abd3f2d6 AK |
1868 | vmcs_write32(EXCEPTION_BITMAP, eb); |
1869 | } | |
1870 | ||
2961e876 GN |
1871 | static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
1872 | unsigned long entry, unsigned long exit) | |
8bf00a52 | 1873 | { |
2961e876 GN |
1874 | vm_entry_controls_clearbit(vmx, entry); |
1875 | vm_exit_controls_clearbit(vmx, exit); | |
8bf00a52 GN |
1876 | } |
1877 | ||
61d2ef2c AK |
1878 | static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) |
1879 | { | |
1880 | unsigned i; | |
1881 | struct msr_autoload *m = &vmx->msr_autoload; | |
1882 | ||
8bf00a52 GN |
1883 | switch (msr) { |
1884 | case MSR_EFER: | |
1885 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
1886 | clear_atomic_switch_msr_special(vmx, |
1887 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
1888 | VM_EXIT_LOAD_IA32_EFER); |
1889 | return; | |
1890 | } | |
1891 | break; | |
1892 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
1893 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 1894 | clear_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
1895 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
1896 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
1897 | return; | |
1898 | } | |
1899 | break; | |
110312c8 AK |
1900 | } |
1901 | ||
61d2ef2c AK |
1902 | for (i = 0; i < m->nr; ++i) |
1903 | if (m->guest[i].index == msr) | |
1904 | break; | |
1905 | ||
1906 | if (i == m->nr) | |
1907 | return; | |
1908 | --m->nr; | |
1909 | m->guest[i] = m->guest[m->nr]; | |
1910 | m->host[i] = m->host[m->nr]; | |
1911 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
1912 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
1913 | } | |
1914 | ||
2961e876 GN |
1915 | static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
1916 | unsigned long entry, unsigned long exit, | |
1917 | unsigned long guest_val_vmcs, unsigned long host_val_vmcs, | |
1918 | u64 guest_val, u64 host_val) | |
8bf00a52 GN |
1919 | { |
1920 | vmcs_write64(guest_val_vmcs, guest_val); | |
1921 | vmcs_write64(host_val_vmcs, host_val); | |
2961e876 GN |
1922 | vm_entry_controls_setbit(vmx, entry); |
1923 | vm_exit_controls_setbit(vmx, exit); | |
8bf00a52 GN |
1924 | } |
1925 | ||
61d2ef2c AK |
1926 | static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, |
1927 | u64 guest_val, u64 host_val) | |
1928 | { | |
1929 | unsigned i; | |
1930 | struct msr_autoload *m = &vmx->msr_autoload; | |
1931 | ||
8bf00a52 GN |
1932 | switch (msr) { |
1933 | case MSR_EFER: | |
1934 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
1935 | add_atomic_switch_msr_special(vmx, |
1936 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
1937 | VM_EXIT_LOAD_IA32_EFER, |
1938 | GUEST_IA32_EFER, | |
1939 | HOST_IA32_EFER, | |
1940 | guest_val, host_val); | |
1941 | return; | |
1942 | } | |
1943 | break; | |
1944 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
1945 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 1946 | add_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
1947 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
1948 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, | |
1949 | GUEST_IA32_PERF_GLOBAL_CTRL, | |
1950 | HOST_IA32_PERF_GLOBAL_CTRL, | |
1951 | guest_val, host_val); | |
1952 | return; | |
1953 | } | |
1954 | break; | |
7099e2e1 RK |
1955 | case MSR_IA32_PEBS_ENABLE: |
1956 | /* PEBS needs a quiescent period after being disabled (to write | |
1957 | * a record). Disabling PEBS through VMX MSR swapping doesn't | |
1958 | * provide that period, so a CPU could write host's record into | |
1959 | * guest's memory. | |
1960 | */ | |
1961 | wrmsrl(MSR_IA32_PEBS_ENABLE, 0); | |
110312c8 AK |
1962 | } |
1963 | ||
61d2ef2c AK |
1964 | for (i = 0; i < m->nr; ++i) |
1965 | if (m->guest[i].index == msr) | |
1966 | break; | |
1967 | ||
e7fc6f93 | 1968 | if (i == NR_AUTOLOAD_MSRS) { |
60266204 | 1969 | printk_once(KERN_WARNING "Not enough msr switch entries. " |
e7fc6f93 GN |
1970 | "Can't add msr %x\n", msr); |
1971 | return; | |
1972 | } else if (i == m->nr) { | |
61d2ef2c AK |
1973 | ++m->nr; |
1974 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
1975 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
1976 | } | |
1977 | ||
1978 | m->guest[i].index = msr; | |
1979 | m->guest[i].value = guest_val; | |
1980 | m->host[i].index = msr; | |
1981 | m->host[i].value = host_val; | |
1982 | } | |
1983 | ||
92c0d900 | 1984 | static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) |
2cc51560 | 1985 | { |
844a5fe2 PB |
1986 | u64 guest_efer = vmx->vcpu.arch.efer; |
1987 | u64 ignore_bits = 0; | |
1988 | ||
1989 | if (!enable_ept) { | |
1990 | /* | |
1991 | * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing | |
1992 | * host CPUID is more efficient than testing guest CPUID | |
1993 | * or CR4. Host SMEP is anyway a requirement for guest SMEP. | |
1994 | */ | |
1995 | if (boot_cpu_has(X86_FEATURE_SMEP)) | |
1996 | guest_efer |= EFER_NX; | |
1997 | else if (!(guest_efer & EFER_NX)) | |
1998 | ignore_bits |= EFER_NX; | |
1999 | } | |
3a34a881 | 2000 | |
51c6cf66 | 2001 | /* |
844a5fe2 | 2002 | * LMA and LME handled by hardware; SCE meaningless outside long mode. |
51c6cf66 | 2003 | */ |
844a5fe2 | 2004 | ignore_bits |= EFER_SCE; |
51c6cf66 AK |
2005 | #ifdef CONFIG_X86_64 |
2006 | ignore_bits |= EFER_LMA | EFER_LME; | |
2007 | /* SCE is meaningful only in long mode on Intel */ | |
2008 | if (guest_efer & EFER_LMA) | |
2009 | ignore_bits &= ~(u64)EFER_SCE; | |
2010 | #endif | |
84ad33ef AK |
2011 | |
2012 | clear_atomic_switch_msr(vmx, MSR_EFER); | |
f6577a5f AL |
2013 | |
2014 | /* | |
2015 | * On EPT, we can't emulate NX, so we must switch EFER atomically. | |
2016 | * On CPUs that support "load IA32_EFER", always switch EFER | |
2017 | * atomically, since it's faster than switching it manually. | |
2018 | */ | |
2019 | if (cpu_has_load_ia32_efer || | |
2020 | (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { | |
84ad33ef AK |
2021 | if (!(guest_efer & EFER_LMA)) |
2022 | guest_efer &= ~EFER_LME; | |
54b98bff AL |
2023 | if (guest_efer != host_efer) |
2024 | add_atomic_switch_msr(vmx, MSR_EFER, | |
2025 | guest_efer, host_efer); | |
84ad33ef | 2026 | return false; |
844a5fe2 PB |
2027 | } else { |
2028 | guest_efer &= ~ignore_bits; | |
2029 | guest_efer |= host_efer & ignore_bits; | |
2030 | ||
2031 | vmx->guest_msrs[efer_offset].data = guest_efer; | |
2032 | vmx->guest_msrs[efer_offset].mask = ~ignore_bits; | |
84ad33ef | 2033 | |
844a5fe2 PB |
2034 | return true; |
2035 | } | |
51c6cf66 AK |
2036 | } |
2037 | ||
e28baead AL |
2038 | #ifdef CONFIG_X86_32 |
2039 | /* | |
2040 | * On 32-bit kernels, VM exits still load the FS and GS bases from the | |
2041 | * VMCS rather than the segment table. KVM uses this helper to figure | |
2042 | * out the current bases to poke them into the VMCS before entry. | |
2043 | */ | |
2d49ec72 GN |
2044 | static unsigned long segment_base(u16 selector) |
2045 | { | |
89cbc767 | 2046 | struct desc_ptr *gdt = this_cpu_ptr(&host_gdt); |
8c2e41f7 | 2047 | struct desc_struct *table; |
2d49ec72 GN |
2048 | unsigned long v; |
2049 | ||
8c2e41f7 | 2050 | if (!(selector & ~SEGMENT_RPL_MASK)) |
2d49ec72 GN |
2051 | return 0; |
2052 | ||
8c2e41f7 | 2053 | table = (struct desc_struct *)gdt->address; |
2d49ec72 | 2054 | |
8c2e41f7 | 2055 | if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) { |
2d49ec72 GN |
2056 | u16 ldt_selector = kvm_read_ldt(); |
2057 | ||
8c2e41f7 | 2058 | if (!(ldt_selector & ~SEGMENT_RPL_MASK)) |
2d49ec72 GN |
2059 | return 0; |
2060 | ||
8c2e41f7 | 2061 | table = (struct desc_struct *)segment_base(ldt_selector); |
2d49ec72 | 2062 | } |
8c2e41f7 | 2063 | v = get_desc_base(&table[selector >> 3]); |
2d49ec72 GN |
2064 | return v; |
2065 | } | |
e28baead | 2066 | #endif |
2d49ec72 | 2067 | |
04d2cc77 | 2068 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 2069 | { |
04d2cc77 | 2070 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 2071 | int i; |
04d2cc77 | 2072 | |
a2fa3e9f | 2073 | if (vmx->host_state.loaded) |
33ed6329 AK |
2074 | return; |
2075 | ||
a2fa3e9f | 2076 | vmx->host_state.loaded = 1; |
33ed6329 AK |
2077 | /* |
2078 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
2079 | * allow segment selectors with cpl > 0 or ti == 1. | |
2080 | */ | |
d6e88aec | 2081 | vmx->host_state.ldt_sel = kvm_read_ldt(); |
152d3f2f | 2082 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
9581d442 | 2083 | savesegment(fs, vmx->host_state.fs_sel); |
152d3f2f | 2084 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 2085 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
2086 | vmx->host_state.fs_reload_needed = 0; |
2087 | } else { | |
33ed6329 | 2088 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 2089 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 2090 | } |
9581d442 | 2091 | savesegment(gs, vmx->host_state.gs_sel); |
a2fa3e9f GH |
2092 | if (!(vmx->host_state.gs_sel & 7)) |
2093 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
2094 | else { |
2095 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 2096 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
2097 | } |
2098 | ||
b2da15ac AK |
2099 | #ifdef CONFIG_X86_64 |
2100 | savesegment(ds, vmx->host_state.ds_sel); | |
2101 | savesegment(es, vmx->host_state.es_sel); | |
2102 | #endif | |
2103 | ||
33ed6329 AK |
2104 | #ifdef CONFIG_X86_64 |
2105 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
2106 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
2107 | #else | |
a2fa3e9f GH |
2108 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
2109 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 2110 | #endif |
707c0874 AK |
2111 | |
2112 | #ifdef CONFIG_X86_64 | |
c8770e7b AK |
2113 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
2114 | if (is_long_mode(&vmx->vcpu)) | |
44ea2b17 | 2115 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); |
707c0874 | 2116 | #endif |
da8999d3 LJ |
2117 | if (boot_cpu_has(X86_FEATURE_MPX)) |
2118 | rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
26bb0981 AK |
2119 | for (i = 0; i < vmx->save_nmsrs; ++i) |
2120 | kvm_set_shared_msr(vmx->guest_msrs[i].index, | |
d5696725 AK |
2121 | vmx->guest_msrs[i].data, |
2122 | vmx->guest_msrs[i].mask); | |
33ed6329 AK |
2123 | } |
2124 | ||
a9b21b62 | 2125 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 2126 | { |
a2fa3e9f | 2127 | if (!vmx->host_state.loaded) |
33ed6329 AK |
2128 | return; |
2129 | ||
e1beb1d3 | 2130 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 2131 | vmx->host_state.loaded = 0; |
c8770e7b AK |
2132 | #ifdef CONFIG_X86_64 |
2133 | if (is_long_mode(&vmx->vcpu)) | |
2134 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); | |
2135 | #endif | |
152d3f2f | 2136 | if (vmx->host_state.gs_ldt_reload_needed) { |
d6e88aec | 2137 | kvm_load_ldt(vmx->host_state.ldt_sel); |
33ed6329 | 2138 | #ifdef CONFIG_X86_64 |
9581d442 | 2139 | load_gs_index(vmx->host_state.gs_sel); |
9581d442 AK |
2140 | #else |
2141 | loadsegment(gs, vmx->host_state.gs_sel); | |
33ed6329 | 2142 | #endif |
33ed6329 | 2143 | } |
0a77fe4c AK |
2144 | if (vmx->host_state.fs_reload_needed) |
2145 | loadsegment(fs, vmx->host_state.fs_sel); | |
b2da15ac AK |
2146 | #ifdef CONFIG_X86_64 |
2147 | if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) { | |
2148 | loadsegment(ds, vmx->host_state.ds_sel); | |
2149 | loadsegment(es, vmx->host_state.es_sel); | |
2150 | } | |
b2da15ac | 2151 | #endif |
b7ffc44d | 2152 | invalidate_tss_limit(); |
44ea2b17 | 2153 | #ifdef CONFIG_X86_64 |
c8770e7b | 2154 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
44ea2b17 | 2155 | #endif |
da8999d3 LJ |
2156 | if (vmx->host_state.msr_host_bndcfgs) |
2157 | wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
89cbc767 | 2158 | load_gdt(this_cpu_ptr(&host_gdt)); |
33ed6329 AK |
2159 | } |
2160 | ||
a9b21b62 AK |
2161 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
2162 | { | |
2163 | preempt_disable(); | |
2164 | __vmx_load_host_state(vmx); | |
2165 | preempt_enable(); | |
2166 | } | |
2167 | ||
28b835d6 FW |
2168 | static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) |
2169 | { | |
2170 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
2171 | struct pi_desc old, new; | |
2172 | unsigned int dest; | |
2173 | ||
2174 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
2175 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
2176 | !kvm_vcpu_apicv_active(vcpu)) | |
28b835d6 FW |
2177 | return; |
2178 | ||
2179 | do { | |
2180 | old.control = new.control = pi_desc->control; | |
2181 | ||
2182 | /* | |
2183 | * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there | |
2184 | * are two possible cases: | |
2185 | * 1. After running 'pre_block', context switch | |
2186 | * happened. For this case, 'sn' was set in | |
2187 | * vmx_vcpu_put(), so we need to clear it here. | |
2188 | * 2. After running 'pre_block', we were blocked, | |
2189 | * and woken up by some other guy. For this case, | |
2190 | * we don't need to do anything, 'pi_post_block' | |
2191 | * will do everything for us. However, we cannot | |
2192 | * check whether it is case #1 or case #2 here | |
2193 | * (maybe, not needed), so we also clear sn here, | |
2194 | * I think it is not a big deal. | |
2195 | */ | |
2196 | if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) { | |
2197 | if (vcpu->cpu != cpu) { | |
2198 | dest = cpu_physical_id(cpu); | |
2199 | ||
2200 | if (x2apic_enabled()) | |
2201 | new.ndst = dest; | |
2202 | else | |
2203 | new.ndst = (dest << 8) & 0xFF00; | |
2204 | } | |
2205 | ||
2206 | /* set 'NV' to 'notification vector' */ | |
2207 | new.nv = POSTED_INTR_VECTOR; | |
2208 | } | |
2209 | ||
2210 | /* Allow posting non-urgent interrupts */ | |
2211 | new.sn = 0; | |
2212 | } while (cmpxchg(&pi_desc->control, old.control, | |
2213 | new.control) != old.control); | |
2214 | } | |
1be0e61c | 2215 | |
c95ba92a PF |
2216 | static void decache_tsc_multiplier(struct vcpu_vmx *vmx) |
2217 | { | |
2218 | vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio; | |
2219 | vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio); | |
2220 | } | |
2221 | ||
6aa8b732 AK |
2222 | /* |
2223 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
2224 | * vcpu mutex is already taken. | |
2225 | */ | |
15ad7146 | 2226 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 2227 | { |
a2fa3e9f | 2228 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
b80c76ec | 2229 | bool already_loaded = vmx->loaded_vmcs->cpu == cpu; |
6aa8b732 | 2230 | |
b80c76ec | 2231 | if (!already_loaded) { |
fe0e80be | 2232 | loaded_vmcs_clear(vmx->loaded_vmcs); |
92fe13be | 2233 | local_irq_disable(); |
8f536b76 | 2234 | crash_disable_local_vmclear(cpu); |
5a560f8b XG |
2235 | |
2236 | /* | |
2237 | * Read loaded_vmcs->cpu should be before fetching | |
2238 | * loaded_vmcs->loaded_vmcss_on_cpu_link. | |
2239 | * See the comments in __loaded_vmcs_clear(). | |
2240 | */ | |
2241 | smp_rmb(); | |
2242 | ||
d462b819 NHE |
2243 | list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, |
2244 | &per_cpu(loaded_vmcss_on_cpu, cpu)); | |
8f536b76 | 2245 | crash_enable_local_vmclear(cpu); |
92fe13be | 2246 | local_irq_enable(); |
b80c76ec JM |
2247 | } |
2248 | ||
2249 | if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { | |
2250 | per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; | |
2251 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
2252 | } | |
2253 | ||
2254 | if (!already_loaded) { | |
2255 | struct desc_ptr *gdt = this_cpu_ptr(&host_gdt); | |
2256 | unsigned long sysenter_esp; | |
2257 | ||
2258 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
92fe13be | 2259 | |
6aa8b732 AK |
2260 | /* |
2261 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
e0c23063 | 2262 | * processors. See 22.2.4. |
6aa8b732 | 2263 | */ |
e0c23063 AL |
2264 | vmcs_writel(HOST_TR_BASE, |
2265 | (unsigned long)this_cpu_ptr(&cpu_tss)); | |
2266 | vmcs_writel(HOST_GDTR_BASE, gdt->address); | |
6aa8b732 | 2267 | |
b7ffc44d AL |
2268 | /* |
2269 | * VM exits change the host TR limit to 0x67 after a VM | |
2270 | * exit. This is okay, since 0x67 covers everything except | |
2271 | * the IO bitmap and have have code to handle the IO bitmap | |
2272 | * being lost after a VM exit. | |
2273 | */ | |
2274 | BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67); | |
2275 | ||
6aa8b732 AK |
2276 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); |
2277 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
ff2c3a18 | 2278 | |
d462b819 | 2279 | vmx->loaded_vmcs->cpu = cpu; |
6aa8b732 | 2280 | } |
28b835d6 | 2281 | |
2680d6da OH |
2282 | /* Setup TSC multiplier */ |
2283 | if (kvm_has_tsc_control && | |
c95ba92a PF |
2284 | vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) |
2285 | decache_tsc_multiplier(vmx); | |
2680d6da | 2286 | |
28b835d6 | 2287 | vmx_vcpu_pi_load(vcpu, cpu); |
1be0e61c | 2288 | vmx->host_pkru = read_pkru(); |
28b835d6 FW |
2289 | } |
2290 | ||
2291 | static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) | |
2292 | { | |
2293 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
2294 | ||
2295 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
2296 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
2297 | !kvm_vcpu_apicv_active(vcpu)) | |
28b835d6 FW |
2298 | return; |
2299 | ||
2300 | /* Set SN when the vCPU is preempted */ | |
2301 | if (vcpu->preempted) | |
2302 | pi_set_sn(pi_desc); | |
6aa8b732 AK |
2303 | } |
2304 | ||
2305 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
2306 | { | |
28b835d6 FW |
2307 | vmx_vcpu_pi_put(vcpu); |
2308 | ||
a9b21b62 | 2309 | __vmx_load_host_state(to_vmx(vcpu)); |
6aa8b732 AK |
2310 | } |
2311 | ||
edcafe3c AK |
2312 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); |
2313 | ||
fe3ef05c NHE |
2314 | /* |
2315 | * Return the cr0 value that a nested guest would read. This is a combination | |
2316 | * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by | |
2317 | * its hypervisor (cr0_read_shadow). | |
2318 | */ | |
2319 | static inline unsigned long nested_read_cr0(struct vmcs12 *fields) | |
2320 | { | |
2321 | return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) | | |
2322 | (fields->cr0_read_shadow & fields->cr0_guest_host_mask); | |
2323 | } | |
2324 | static inline unsigned long nested_read_cr4(struct vmcs12 *fields) | |
2325 | { | |
2326 | return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) | | |
2327 | (fields->cr4_read_shadow & fields->cr4_guest_host_mask); | |
2328 | } | |
2329 | ||
6aa8b732 AK |
2330 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
2331 | { | |
78ac8b47 | 2332 | unsigned long rflags, save_rflags; |
345dcaa8 | 2333 | |
6de12732 AK |
2334 | if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) { |
2335 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); | |
2336 | rflags = vmcs_readl(GUEST_RFLAGS); | |
2337 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
2338 | rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; | |
2339 | save_rflags = to_vmx(vcpu)->rmode.save_rflags; | |
2340 | rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
2341 | } | |
2342 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 | 2343 | } |
6de12732 | 2344 | return to_vmx(vcpu)->rflags; |
6aa8b732 AK |
2345 | } |
2346 | ||
2347 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
2348 | { | |
6de12732 AK |
2349 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); |
2350 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 AK |
2351 | if (to_vmx(vcpu)->rmode.vm86_active) { |
2352 | to_vmx(vcpu)->rmode.save_rflags = rflags; | |
053de044 | 2353 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
78ac8b47 | 2354 | } |
6aa8b732 AK |
2355 | vmcs_writel(GUEST_RFLAGS, rflags); |
2356 | } | |
2357 | ||
be94f6b7 HH |
2358 | static u32 vmx_get_pkru(struct kvm_vcpu *vcpu) |
2359 | { | |
2360 | return to_vmx(vcpu)->guest_pkru; | |
2361 | } | |
2362 | ||
37ccdcbe | 2363 | static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
2364 | { |
2365 | u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2366 | int ret = 0; | |
2367 | ||
2368 | if (interruptibility & GUEST_INTR_STATE_STI) | |
48005f64 | 2369 | ret |= KVM_X86_SHADOW_INT_STI; |
2809f5d2 | 2370 | if (interruptibility & GUEST_INTR_STATE_MOV_SS) |
48005f64 | 2371 | ret |= KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 | 2372 | |
37ccdcbe | 2373 | return ret; |
2809f5d2 GC |
2374 | } |
2375 | ||
2376 | static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
2377 | { | |
2378 | u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2379 | u32 interruptibility = interruptibility_old; | |
2380 | ||
2381 | interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); | |
2382 | ||
48005f64 | 2383 | if (mask & KVM_X86_SHADOW_INT_MOV_SS) |
2809f5d2 | 2384 | interruptibility |= GUEST_INTR_STATE_MOV_SS; |
48005f64 | 2385 | else if (mask & KVM_X86_SHADOW_INT_STI) |
2809f5d2 GC |
2386 | interruptibility |= GUEST_INTR_STATE_STI; |
2387 | ||
2388 | if ((interruptibility != interruptibility_old)) | |
2389 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); | |
2390 | } | |
2391 | ||
6aa8b732 AK |
2392 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
2393 | { | |
2394 | unsigned long rip; | |
6aa8b732 | 2395 | |
5fdbf976 | 2396 | rip = kvm_rip_read(vcpu); |
6aa8b732 | 2397 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
5fdbf976 | 2398 | kvm_rip_write(vcpu, rip); |
6aa8b732 | 2399 | |
2809f5d2 GC |
2400 | /* skipping an emulated instruction also counts */ |
2401 | vmx_set_interrupt_shadow(vcpu, 0); | |
6aa8b732 AK |
2402 | } |
2403 | ||
0b6ac343 NHE |
2404 | /* |
2405 | * KVM wants to inject page-faults which it got to the guest. This function | |
2406 | * checks whether in a nested guest, we need to inject them to L1 or L2. | |
0b6ac343 | 2407 | */ |
e011c663 | 2408 | static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr) |
0b6ac343 NHE |
2409 | { |
2410 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
2411 | ||
e011c663 | 2412 | if (!(vmcs12->exception_bitmap & (1u << nr))) |
0b6ac343 NHE |
2413 | return 0; |
2414 | ||
533558bc JK |
2415 | nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason, |
2416 | vmcs_read32(VM_EXIT_INTR_INFO), | |
2417 | vmcs_readl(EXIT_QUALIFICATION)); | |
0b6ac343 NHE |
2418 | return 1; |
2419 | } | |
2420 | ||
298101da | 2421 | static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
2422 | bool has_error_code, u32 error_code, |
2423 | bool reinject) | |
298101da | 2424 | { |
77ab6db0 | 2425 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8ab2d2e2 | 2426 | u32 intr_info = nr | INTR_INFO_VALID_MASK; |
77ab6db0 | 2427 | |
e011c663 GN |
2428 | if (!reinject && is_guest_mode(vcpu) && |
2429 | nested_vmx_check_exception(vcpu, nr)) | |
0b6ac343 NHE |
2430 | return; |
2431 | ||
8ab2d2e2 | 2432 | if (has_error_code) { |
77ab6db0 | 2433 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); |
8ab2d2e2 JK |
2434 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; |
2435 | } | |
77ab6db0 | 2436 | |
7ffd92c5 | 2437 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
2438 | int inc_eip = 0; |
2439 | if (kvm_exception_is_soft(nr)) | |
2440 | inc_eip = vcpu->arch.event_exit_inst_len; | |
2441 | if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE) | |
a92601bb | 2442 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
77ab6db0 JK |
2443 | return; |
2444 | } | |
2445 | ||
66fd3f7f GN |
2446 | if (kvm_exception_is_soft(nr)) { |
2447 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
2448 | vmx->vcpu.arch.event_exit_inst_len); | |
8ab2d2e2 JK |
2449 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; |
2450 | } else | |
2451 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
2452 | ||
2453 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | |
298101da AK |
2454 | } |
2455 | ||
4e47c7a6 SY |
2456 | static bool vmx_rdtscp_supported(void) |
2457 | { | |
2458 | return cpu_has_vmx_rdtscp(); | |
2459 | } | |
2460 | ||
ad756a16 MJ |
2461 | static bool vmx_invpcid_supported(void) |
2462 | { | |
2463 | return cpu_has_vmx_invpcid() && enable_ept; | |
2464 | } | |
2465 | ||
a75beee6 ED |
2466 | /* |
2467 | * Swap MSR entry in host/guest MSR entry array. | |
2468 | */ | |
8b9cf98c | 2469 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 2470 | { |
26bb0981 | 2471 | struct shared_msr_entry tmp; |
a2fa3e9f GH |
2472 | |
2473 | tmp = vmx->guest_msrs[to]; | |
2474 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
2475 | vmx->guest_msrs[from] = tmp; | |
a75beee6 ED |
2476 | } |
2477 | ||
8d14695f YZ |
2478 | static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu) |
2479 | { | |
2480 | unsigned long *msr_bitmap; | |
2481 | ||
670125bd | 2482 | if (is_guest_mode(vcpu)) |
d048c098 | 2483 | msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap; |
3ce424e4 RK |
2484 | else if (cpu_has_secondary_exec_ctrls() && |
2485 | (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) & | |
2486 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { | |
f6e90f9e WL |
2487 | if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) { |
2488 | if (is_long_mode(vcpu)) | |
c63e4563 | 2489 | msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv; |
f6e90f9e | 2490 | else |
c63e4563 | 2491 | msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv; |
f6e90f9e WL |
2492 | } else { |
2493 | if (is_long_mode(vcpu)) | |
c63e4563 | 2494 | msr_bitmap = vmx_msr_bitmap_longmode_x2apic; |
f6e90f9e | 2495 | else |
c63e4563 | 2496 | msr_bitmap = vmx_msr_bitmap_legacy_x2apic; |
f6e90f9e | 2497 | } |
8d14695f YZ |
2498 | } else { |
2499 | if (is_long_mode(vcpu)) | |
2500 | msr_bitmap = vmx_msr_bitmap_longmode; | |
2501 | else | |
2502 | msr_bitmap = vmx_msr_bitmap_legacy; | |
2503 | } | |
2504 | ||
2505 | vmcs_write64(MSR_BITMAP, __pa(msr_bitmap)); | |
2506 | } | |
2507 | ||
e38aea3e AK |
2508 | /* |
2509 | * Set up the vmcs to automatically save and restore system | |
2510 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
2511 | * mode, as fiddling with msrs is very expensive. | |
2512 | */ | |
8b9cf98c | 2513 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 2514 | { |
26bb0981 | 2515 | int save_nmsrs, index; |
e38aea3e | 2516 | |
a75beee6 ED |
2517 | save_nmsrs = 0; |
2518 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 2519 | if (is_long_mode(&vmx->vcpu)) { |
8b9cf98c | 2520 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 2521 | if (index >= 0) |
8b9cf98c RR |
2522 | move_msr_up(vmx, index, save_nmsrs++); |
2523 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 2524 | if (index >= 0) |
8b9cf98c RR |
2525 | move_msr_up(vmx, index, save_nmsrs++); |
2526 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 2527 | if (index >= 0) |
8b9cf98c | 2528 | move_msr_up(vmx, index, save_nmsrs++); |
4e47c7a6 | 2529 | index = __find_msr_index(vmx, MSR_TSC_AUX); |
1cea0ce6 | 2530 | if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu)) |
4e47c7a6 | 2531 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 | 2532 | /* |
8c06585d | 2533 | * MSR_STAR is only needed on long mode guests, and only |
a75beee6 ED |
2534 | * if efer.sce is enabled. |
2535 | */ | |
8c06585d | 2536 | index = __find_msr_index(vmx, MSR_STAR); |
f6801dff | 2537 | if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE)) |
8b9cf98c | 2538 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
2539 | } |
2540 | #endif | |
92c0d900 AK |
2541 | index = __find_msr_index(vmx, MSR_EFER); |
2542 | if (index >= 0 && update_transition_efer(vmx, index)) | |
26bb0981 | 2543 | move_msr_up(vmx, index, save_nmsrs++); |
e38aea3e | 2544 | |
26bb0981 | 2545 | vmx->save_nmsrs = save_nmsrs; |
5897297b | 2546 | |
8d14695f YZ |
2547 | if (cpu_has_vmx_msr_bitmap()) |
2548 | vmx_set_msr_bitmap(&vmx->vcpu); | |
e38aea3e AK |
2549 | } |
2550 | ||
6aa8b732 AK |
2551 | /* |
2552 | * reads and returns guest's timestamp counter "register" | |
be7b263e HZ |
2553 | * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset |
2554 | * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3 | |
6aa8b732 | 2555 | */ |
be7b263e | 2556 | static u64 guest_read_tsc(struct kvm_vcpu *vcpu) |
6aa8b732 AK |
2557 | { |
2558 | u64 host_tsc, tsc_offset; | |
2559 | ||
4ea1636b | 2560 | host_tsc = rdtsc(); |
6aa8b732 | 2561 | tsc_offset = vmcs_read64(TSC_OFFSET); |
be7b263e | 2562 | return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset; |
6aa8b732 AK |
2563 | } |
2564 | ||
2565 | /* | |
99e3e30a | 2566 | * writes 'offset' into guest's timestamp counter offset register |
6aa8b732 | 2567 | */ |
99e3e30a | 2568 | static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
6aa8b732 | 2569 | { |
27fc51b2 | 2570 | if (is_guest_mode(vcpu)) { |
7991825b | 2571 | /* |
27fc51b2 NHE |
2572 | * We're here if L1 chose not to trap WRMSR to TSC. According |
2573 | * to the spec, this should set L1's TSC; The offset that L1 | |
2574 | * set for L2 remains unchanged, and still needs to be added | |
2575 | * to the newly set TSC to get L2's TSC. | |
7991825b | 2576 | */ |
27fc51b2 | 2577 | struct vmcs12 *vmcs12; |
27fc51b2 NHE |
2578 | /* recalculate vmcs02.TSC_OFFSET: */ |
2579 | vmcs12 = get_vmcs12(vcpu); | |
2580 | vmcs_write64(TSC_OFFSET, offset + | |
2581 | (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ? | |
2582 | vmcs12->tsc_offset : 0)); | |
2583 | } else { | |
489223ed YY |
2584 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, |
2585 | vmcs_read64(TSC_OFFSET), offset); | |
27fc51b2 NHE |
2586 | vmcs_write64(TSC_OFFSET, offset); |
2587 | } | |
6aa8b732 AK |
2588 | } |
2589 | ||
801d3424 NHE |
2590 | static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu) |
2591 | { | |
2592 | struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0); | |
2593 | return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31))); | |
2594 | } | |
2595 | ||
2596 | /* | |
2597 | * nested_vmx_allowed() checks whether a guest should be allowed to use VMX | |
2598 | * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for | |
2599 | * all guests if the "nested" module option is off, and can also be disabled | |
2600 | * for a single guest by disabling its VMX cpuid bit. | |
2601 | */ | |
2602 | static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu) | |
2603 | { | |
2604 | return nested && guest_cpuid_has_vmx(vcpu); | |
2605 | } | |
2606 | ||
b87a51ae NHE |
2607 | /* |
2608 | * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be | |
2609 | * returned for the various VMX controls MSRs when nested VMX is enabled. | |
2610 | * The same values should also be used to verify that vmcs12 control fields are | |
2611 | * valid during nested entry from L1 to L2. | |
2612 | * Each of these control msrs has a low and high 32-bit half: A low bit is on | |
2613 | * if the corresponding bit in the (32-bit) control field *must* be on, and a | |
2614 | * bit in the high half is on if the corresponding bit in the control field | |
2615 | * may be on. See also vmx_control_verify(). | |
b87a51ae | 2616 | */ |
b9c237bb | 2617 | static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx) |
b87a51ae NHE |
2618 | { |
2619 | /* | |
2620 | * Note that as a general rule, the high half of the MSRs (bits in | |
2621 | * the control fields which may be 1) should be initialized by the | |
2622 | * intersection of the underlying hardware's MSR (i.e., features which | |
2623 | * can be supported) and the list of features we want to expose - | |
2624 | * because they are known to be properly supported in our code. | |
2625 | * Also, usually, the low half of the MSRs (bits which must be 1) can | |
2626 | * be set to 0, meaning that L1 may turn off any of these bits. The | |
2627 | * reason is that if one of these bits is necessary, it will appear | |
2628 | * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control | |
2629 | * fields of vmcs01 and vmcs02, will turn these bits off - and | |
2630 | * nested_vmx_exit_handled() will not pass related exits to L1. | |
2631 | * These rules have exceptions below. | |
2632 | */ | |
2633 | ||
2634 | /* pin-based controls */ | |
eabeaacc | 2635 | rdmsr(MSR_IA32_VMX_PINBASED_CTLS, |
b9c237bb WV |
2636 | vmx->nested.nested_vmx_pinbased_ctls_low, |
2637 | vmx->nested.nested_vmx_pinbased_ctls_high); | |
2638 | vmx->nested.nested_vmx_pinbased_ctls_low |= | |
2639 | PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
2640 | vmx->nested.nested_vmx_pinbased_ctls_high &= | |
2641 | PIN_BASED_EXT_INTR_MASK | | |
2642 | PIN_BASED_NMI_EXITING | | |
2643 | PIN_BASED_VIRTUAL_NMIS; | |
2644 | vmx->nested.nested_vmx_pinbased_ctls_high |= | |
2645 | PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR | | |
0238ea91 | 2646 | PIN_BASED_VMX_PREEMPTION_TIMER; |
d62caabb | 2647 | if (kvm_vcpu_apicv_active(&vmx->vcpu)) |
705699a1 WV |
2648 | vmx->nested.nested_vmx_pinbased_ctls_high |= |
2649 | PIN_BASED_POSTED_INTR; | |
b87a51ae | 2650 | |
3dbcd8da | 2651 | /* exit controls */ |
c0dfee58 | 2652 | rdmsr(MSR_IA32_VMX_EXIT_CTLS, |
b9c237bb WV |
2653 | vmx->nested.nested_vmx_exit_ctls_low, |
2654 | vmx->nested.nested_vmx_exit_ctls_high); | |
2655 | vmx->nested.nested_vmx_exit_ctls_low = | |
2656 | VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; | |
e0ba1a6f | 2657 | |
b9c237bb | 2658 | vmx->nested.nested_vmx_exit_ctls_high &= |
b87a51ae | 2659 | #ifdef CONFIG_X86_64 |
c0dfee58 | 2660 | VM_EXIT_HOST_ADDR_SPACE_SIZE | |
b87a51ae | 2661 | #endif |
f4124500 | 2662 | VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT; |
b9c237bb WV |
2663 | vmx->nested.nested_vmx_exit_ctls_high |= |
2664 | VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR | | |
f4124500 | 2665 | VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER | |
e0ba1a6f BD |
2666 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT; |
2667 | ||
a87036ad | 2668 | if (kvm_mpx_supported()) |
b9c237bb | 2669 | vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; |
b87a51ae | 2670 | |
2996fca0 | 2671 | /* We support free control of debug control saving. */ |
0115f9cb | 2672 | vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS; |
2996fca0 | 2673 | |
b87a51ae NHE |
2674 | /* entry controls */ |
2675 | rdmsr(MSR_IA32_VMX_ENTRY_CTLS, | |
b9c237bb WV |
2676 | vmx->nested.nested_vmx_entry_ctls_low, |
2677 | vmx->nested.nested_vmx_entry_ctls_high); | |
2678 | vmx->nested.nested_vmx_entry_ctls_low = | |
2679 | VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; | |
2680 | vmx->nested.nested_vmx_entry_ctls_high &= | |
57435349 JK |
2681 | #ifdef CONFIG_X86_64 |
2682 | VM_ENTRY_IA32E_MODE | | |
2683 | #endif | |
2684 | VM_ENTRY_LOAD_IA32_PAT; | |
b9c237bb WV |
2685 | vmx->nested.nested_vmx_entry_ctls_high |= |
2686 | (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER); | |
a87036ad | 2687 | if (kvm_mpx_supported()) |
b9c237bb | 2688 | vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; |
57435349 | 2689 | |
2996fca0 | 2690 | /* We support free control of debug control loading. */ |
0115f9cb | 2691 | vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS; |
2996fca0 | 2692 | |
b87a51ae NHE |
2693 | /* cpu-based controls */ |
2694 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, | |
b9c237bb WV |
2695 | vmx->nested.nested_vmx_procbased_ctls_low, |
2696 | vmx->nested.nested_vmx_procbased_ctls_high); | |
2697 | vmx->nested.nested_vmx_procbased_ctls_low = | |
2698 | CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
2699 | vmx->nested.nested_vmx_procbased_ctls_high &= | |
a294c9bb JK |
2700 | CPU_BASED_VIRTUAL_INTR_PENDING | |
2701 | CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING | | |
b87a51ae NHE |
2702 | CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING | |
2703 | CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING | | |
2704 | CPU_BASED_CR3_STORE_EXITING | | |
2705 | #ifdef CONFIG_X86_64 | |
2706 | CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING | | |
2707 | #endif | |
2708 | CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING | | |
5f3d45e7 MD |
2709 | CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG | |
2710 | CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING | | |
2711 | CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING | | |
2712 | CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
b87a51ae NHE |
2713 | /* |
2714 | * We can allow some features even when not supported by the | |
2715 | * hardware. For example, L1 can specify an MSR bitmap - and we | |
2716 | * can use it to avoid exits to L1 - even when L0 runs L2 | |
2717 | * without MSR bitmaps. | |
2718 | */ | |
b9c237bb WV |
2719 | vmx->nested.nested_vmx_procbased_ctls_high |= |
2720 | CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR | | |
560b7ee1 | 2721 | CPU_BASED_USE_MSR_BITMAPS; |
b87a51ae | 2722 | |
3dcdf3ec | 2723 | /* We support free control of CR3 access interception. */ |
0115f9cb | 2724 | vmx->nested.nested_vmx_procbased_ctls_low &= |
3dcdf3ec JK |
2725 | ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING); |
2726 | ||
b87a51ae NHE |
2727 | /* secondary cpu-based controls */ |
2728 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, | |
b9c237bb WV |
2729 | vmx->nested.nested_vmx_secondary_ctls_low, |
2730 | vmx->nested.nested_vmx_secondary_ctls_high); | |
2731 | vmx->nested.nested_vmx_secondary_ctls_low = 0; | |
2732 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
a5f46457 | 2733 | SECONDARY_EXEC_RDRAND | SECONDARY_EXEC_RDSEED | |
d6851fbe | 2734 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
b3a2a907 | 2735 | SECONDARY_EXEC_RDTSCP | |
1b07304c | 2736 | SECONDARY_EXEC_DESC | |
f2b93280 | 2737 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
82f0dd4b | 2738 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
608406e2 | 2739 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
81dc01f7 | 2740 | SECONDARY_EXEC_WBINVD_EXITING | |
dfa169bb | 2741 | SECONDARY_EXEC_XSAVES; |
c18911a2 | 2742 | |
afa61f75 NHE |
2743 | if (enable_ept) { |
2744 | /* nested EPT: emulate EPT also to L1 */ | |
b9c237bb | 2745 | vmx->nested.nested_vmx_secondary_ctls_high |= |
0790ec17 | 2746 | SECONDARY_EXEC_ENABLE_EPT; |
b9c237bb | 2747 | vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT | |
7db74265 | 2748 | VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT; |
02120c45 BD |
2749 | if (cpu_has_vmx_ept_execute_only()) |
2750 | vmx->nested.nested_vmx_ept_caps |= | |
2751 | VMX_EPT_EXECUTE_ONLY_BIT; | |
b9c237bb | 2752 | vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept; |
45e11817 | 2753 | vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT | |
7db74265 PB |
2754 | VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT | |
2755 | VMX_EPT_1GB_PAGE_BIT; | |
ae1e2d10 PB |
2756 | if (enable_ept_ad_bits) |
2757 | vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT; | |
afa61f75 | 2758 | } else |
b9c237bb | 2759 | vmx->nested.nested_vmx_ept_caps = 0; |
afa61f75 | 2760 | |
ef697a71 PB |
2761 | /* |
2762 | * Old versions of KVM use the single-context version without | |
2763 | * checking for support, so declare that it is supported even | |
2764 | * though it is treated as global context. The alternative is | |
2765 | * not failing the single-context invvpid, and it is worse. | |
2766 | */ | |
63cb6d5f WL |
2767 | if (enable_vpid) { |
2768 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
2769 | SECONDARY_EXEC_ENABLE_VPID; | |
089d7b6e | 2770 | vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT | |
bcdde302 | 2771 | VMX_VPID_EXTENT_SUPPORTED_MASK; |
63cb6d5f | 2772 | } else |
089d7b6e | 2773 | vmx->nested.nested_vmx_vpid_caps = 0; |
99b83ac8 | 2774 | |
0790ec17 RK |
2775 | if (enable_unrestricted_guest) |
2776 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
2777 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
2778 | ||
c18911a2 | 2779 | /* miscellaneous data */ |
b9c237bb WV |
2780 | rdmsr(MSR_IA32_VMX_MISC, |
2781 | vmx->nested.nested_vmx_misc_low, | |
2782 | vmx->nested.nested_vmx_misc_high); | |
2783 | vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA; | |
2784 | vmx->nested.nested_vmx_misc_low |= | |
2785 | VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE | | |
f4124500 | 2786 | VMX_MISC_ACTIVITY_HLT; |
b9c237bb | 2787 | vmx->nested.nested_vmx_misc_high = 0; |
62cc6b9d DM |
2788 | |
2789 | /* | |
2790 | * This MSR reports some information about VMX support. We | |
2791 | * should return information about the VMX we emulate for the | |
2792 | * guest, and the VMCS structure we give it - not about the | |
2793 | * VMX support of the underlying hardware. | |
2794 | */ | |
2795 | vmx->nested.nested_vmx_basic = | |
2796 | VMCS12_REVISION | | |
2797 | VMX_BASIC_TRUE_CTLS | | |
2798 | ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) | | |
2799 | (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT); | |
2800 | ||
2801 | if (cpu_has_vmx_basic_inout()) | |
2802 | vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT; | |
2803 | ||
2804 | /* | |
8322ebbb | 2805 | * These MSRs specify bits which the guest must keep fixed on |
62cc6b9d DM |
2806 | * while L1 is in VMXON mode (in L1's root mode, or running an L2). |
2807 | * We picked the standard core2 setting. | |
2808 | */ | |
2809 | #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE) | |
2810 | #define VMXON_CR4_ALWAYSON X86_CR4_VMXE | |
2811 | vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON; | |
62cc6b9d | 2812 | vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON; |
8322ebbb DM |
2813 | |
2814 | /* These MSRs specify bits which the guest must keep fixed off. */ | |
2815 | rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1); | |
2816 | rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1); | |
62cc6b9d DM |
2817 | |
2818 | /* highest index: VMX_PREEMPTION_TIMER_VALUE */ | |
2819 | vmx->nested.nested_vmx_vmcs_enum = 0x2e; | |
b87a51ae NHE |
2820 | } |
2821 | ||
3899152c DM |
2822 | /* |
2823 | * if fixed0[i] == 1: val[i] must be 1 | |
2824 | * if fixed1[i] == 0: val[i] must be 0 | |
2825 | */ | |
2826 | static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1) | |
2827 | { | |
2828 | return ((val & fixed1) | fixed0) == val; | |
b87a51ae NHE |
2829 | } |
2830 | ||
2831 | static inline bool vmx_control_verify(u32 control, u32 low, u32 high) | |
2832 | { | |
3899152c | 2833 | return fixed_bits_valid(control, low, high); |
b87a51ae NHE |
2834 | } |
2835 | ||
2836 | static inline u64 vmx_control_msr(u32 low, u32 high) | |
2837 | { | |
2838 | return low | ((u64)high << 32); | |
2839 | } | |
2840 | ||
62cc6b9d DM |
2841 | static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask) |
2842 | { | |
2843 | superset &= mask; | |
2844 | subset &= mask; | |
2845 | ||
2846 | return (superset | subset) == superset; | |
2847 | } | |
2848 | ||
2849 | static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data) | |
2850 | { | |
2851 | const u64 feature_and_reserved = | |
2852 | /* feature (except bit 48; see below) */ | |
2853 | BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) | | |
2854 | /* reserved */ | |
2855 | BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56); | |
2856 | u64 vmx_basic = vmx->nested.nested_vmx_basic; | |
2857 | ||
2858 | if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved)) | |
2859 | return -EINVAL; | |
2860 | ||
2861 | /* | |
2862 | * KVM does not emulate a version of VMX that constrains physical | |
2863 | * addresses of VMX structures (e.g. VMCS) to 32-bits. | |
2864 | */ | |
2865 | if (data & BIT_ULL(48)) | |
2866 | return -EINVAL; | |
2867 | ||
2868 | if (vmx_basic_vmcs_revision_id(vmx_basic) != | |
2869 | vmx_basic_vmcs_revision_id(data)) | |
2870 | return -EINVAL; | |
2871 | ||
2872 | if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data)) | |
2873 | return -EINVAL; | |
2874 | ||
2875 | vmx->nested.nested_vmx_basic = data; | |
2876 | return 0; | |
2877 | } | |
2878 | ||
2879 | static int | |
2880 | vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) | |
2881 | { | |
2882 | u64 supported; | |
2883 | u32 *lowp, *highp; | |
2884 | ||
2885 | switch (msr_index) { | |
2886 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
2887 | lowp = &vmx->nested.nested_vmx_pinbased_ctls_low; | |
2888 | highp = &vmx->nested.nested_vmx_pinbased_ctls_high; | |
2889 | break; | |
2890 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
2891 | lowp = &vmx->nested.nested_vmx_procbased_ctls_low; | |
2892 | highp = &vmx->nested.nested_vmx_procbased_ctls_high; | |
2893 | break; | |
2894 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
2895 | lowp = &vmx->nested.nested_vmx_exit_ctls_low; | |
2896 | highp = &vmx->nested.nested_vmx_exit_ctls_high; | |
2897 | break; | |
2898 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
2899 | lowp = &vmx->nested.nested_vmx_entry_ctls_low; | |
2900 | highp = &vmx->nested.nested_vmx_entry_ctls_high; | |
2901 | break; | |
2902 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
2903 | lowp = &vmx->nested.nested_vmx_secondary_ctls_low; | |
2904 | highp = &vmx->nested.nested_vmx_secondary_ctls_high; | |
2905 | break; | |
2906 | default: | |
2907 | BUG(); | |
2908 | } | |
2909 | ||
2910 | supported = vmx_control_msr(*lowp, *highp); | |
2911 | ||
2912 | /* Check must-be-1 bits are still 1. */ | |
2913 | if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0))) | |
2914 | return -EINVAL; | |
2915 | ||
2916 | /* Check must-be-0 bits are still 0. */ | |
2917 | if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32))) | |
2918 | return -EINVAL; | |
2919 | ||
2920 | *lowp = data; | |
2921 | *highp = data >> 32; | |
2922 | return 0; | |
2923 | } | |
2924 | ||
2925 | static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data) | |
2926 | { | |
2927 | const u64 feature_and_reserved_bits = | |
2928 | /* feature */ | |
2929 | BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) | | |
2930 | BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) | | |
2931 | /* reserved */ | |
2932 | GENMASK_ULL(13, 9) | BIT_ULL(31); | |
2933 | u64 vmx_misc; | |
2934 | ||
2935 | vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low, | |
2936 | vmx->nested.nested_vmx_misc_high); | |
2937 | ||
2938 | if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits)) | |
2939 | return -EINVAL; | |
2940 | ||
2941 | if ((vmx->nested.nested_vmx_pinbased_ctls_high & | |
2942 | PIN_BASED_VMX_PREEMPTION_TIMER) && | |
2943 | vmx_misc_preemption_timer_rate(data) != | |
2944 | vmx_misc_preemption_timer_rate(vmx_misc)) | |
2945 | return -EINVAL; | |
2946 | ||
2947 | if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc)) | |
2948 | return -EINVAL; | |
2949 | ||
2950 | if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc)) | |
2951 | return -EINVAL; | |
2952 | ||
2953 | if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc)) | |
2954 | return -EINVAL; | |
2955 | ||
2956 | vmx->nested.nested_vmx_misc_low = data; | |
2957 | vmx->nested.nested_vmx_misc_high = data >> 32; | |
2958 | return 0; | |
2959 | } | |
2960 | ||
2961 | static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data) | |
2962 | { | |
2963 | u64 vmx_ept_vpid_cap; | |
2964 | ||
2965 | vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps, | |
2966 | vmx->nested.nested_vmx_vpid_caps); | |
2967 | ||
2968 | /* Every bit is either reserved or a feature bit. */ | |
2969 | if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL)) | |
2970 | return -EINVAL; | |
2971 | ||
2972 | vmx->nested.nested_vmx_ept_caps = data; | |
2973 | vmx->nested.nested_vmx_vpid_caps = data >> 32; | |
2974 | return 0; | |
2975 | } | |
2976 | ||
2977 | static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) | |
2978 | { | |
2979 | u64 *msr; | |
2980 | ||
2981 | switch (msr_index) { | |
2982 | case MSR_IA32_VMX_CR0_FIXED0: | |
2983 | msr = &vmx->nested.nested_vmx_cr0_fixed0; | |
2984 | break; | |
2985 | case MSR_IA32_VMX_CR4_FIXED0: | |
2986 | msr = &vmx->nested.nested_vmx_cr4_fixed0; | |
2987 | break; | |
2988 | default: | |
2989 | BUG(); | |
2990 | } | |
2991 | ||
2992 | /* | |
2993 | * 1 bits (which indicates bits which "must-be-1" during VMX operation) | |
2994 | * must be 1 in the restored value. | |
2995 | */ | |
2996 | if (!is_bitwise_subset(data, *msr, -1ULL)) | |
2997 | return -EINVAL; | |
2998 | ||
2999 | *msr = data; | |
3000 | return 0; | |
3001 | } | |
3002 | ||
3003 | /* | |
3004 | * Called when userspace is restoring VMX MSRs. | |
3005 | * | |
3006 | * Returns 0 on success, non-0 otherwise. | |
3007 | */ | |
3008 | static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
b87a51ae | 3009 | { |
b9c237bb WV |
3010 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3011 | ||
b87a51ae | 3012 | switch (msr_index) { |
b87a51ae | 3013 | case MSR_IA32_VMX_BASIC: |
62cc6b9d DM |
3014 | return vmx_restore_vmx_basic(vmx, data); |
3015 | case MSR_IA32_VMX_PINBASED_CTLS: | |
3016 | case MSR_IA32_VMX_PROCBASED_CTLS: | |
3017 | case MSR_IA32_VMX_EXIT_CTLS: | |
3018 | case MSR_IA32_VMX_ENTRY_CTLS: | |
b87a51ae | 3019 | /* |
62cc6b9d DM |
3020 | * The "non-true" VMX capability MSRs are generated from the |
3021 | * "true" MSRs, so we do not support restoring them directly. | |
3022 | * | |
3023 | * If userspace wants to emulate VMX_BASIC[55]=0, userspace | |
3024 | * should restore the "true" MSRs with the must-be-1 bits | |
3025 | * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND | |
3026 | * DEFAULT SETTINGS". | |
b87a51ae | 3027 | */ |
62cc6b9d DM |
3028 | return -EINVAL; |
3029 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
3030 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
3031 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
3032 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
3033 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
3034 | return vmx_restore_control_msr(vmx, msr_index, data); | |
3035 | case MSR_IA32_VMX_MISC: | |
3036 | return vmx_restore_vmx_misc(vmx, data); | |
3037 | case MSR_IA32_VMX_CR0_FIXED0: | |
3038 | case MSR_IA32_VMX_CR4_FIXED0: | |
3039 | return vmx_restore_fixed0_msr(vmx, msr_index, data); | |
3040 | case MSR_IA32_VMX_CR0_FIXED1: | |
3041 | case MSR_IA32_VMX_CR4_FIXED1: | |
3042 | /* | |
3043 | * These MSRs are generated based on the vCPU's CPUID, so we | |
3044 | * do not support restoring them directly. | |
3045 | */ | |
3046 | return -EINVAL; | |
3047 | case MSR_IA32_VMX_EPT_VPID_CAP: | |
3048 | return vmx_restore_vmx_ept_vpid_cap(vmx, data); | |
3049 | case MSR_IA32_VMX_VMCS_ENUM: | |
3050 | vmx->nested.nested_vmx_vmcs_enum = data; | |
3051 | return 0; | |
3052 | default: | |
b87a51ae | 3053 | /* |
62cc6b9d | 3054 | * The rest of the VMX capability MSRs do not support restore. |
b87a51ae | 3055 | */ |
62cc6b9d DM |
3056 | return -EINVAL; |
3057 | } | |
3058 | } | |
3059 | ||
3060 | /* Returns 0 on success, non-0 otherwise. */ | |
3061 | static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
3062 | { | |
3063 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
3064 | ||
3065 | switch (msr_index) { | |
3066 | case MSR_IA32_VMX_BASIC: | |
3067 | *pdata = vmx->nested.nested_vmx_basic; | |
b87a51ae NHE |
3068 | break; |
3069 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
3070 | case MSR_IA32_VMX_PINBASED_CTLS: | |
b9c237bb WV |
3071 | *pdata = vmx_control_msr( |
3072 | vmx->nested.nested_vmx_pinbased_ctls_low, | |
3073 | vmx->nested.nested_vmx_pinbased_ctls_high); | |
0115f9cb DM |
3074 | if (msr_index == MSR_IA32_VMX_PINBASED_CTLS) |
3075 | *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3076 | break; |
3077 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
3078 | case MSR_IA32_VMX_PROCBASED_CTLS: | |
b9c237bb WV |
3079 | *pdata = vmx_control_msr( |
3080 | vmx->nested.nested_vmx_procbased_ctls_low, | |
3081 | vmx->nested.nested_vmx_procbased_ctls_high); | |
0115f9cb DM |
3082 | if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS) |
3083 | *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3084 | break; |
3085 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
3086 | case MSR_IA32_VMX_EXIT_CTLS: | |
b9c237bb WV |
3087 | *pdata = vmx_control_msr( |
3088 | vmx->nested.nested_vmx_exit_ctls_low, | |
3089 | vmx->nested.nested_vmx_exit_ctls_high); | |
0115f9cb DM |
3090 | if (msr_index == MSR_IA32_VMX_EXIT_CTLS) |
3091 | *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3092 | break; |
3093 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
3094 | case MSR_IA32_VMX_ENTRY_CTLS: | |
b9c237bb WV |
3095 | *pdata = vmx_control_msr( |
3096 | vmx->nested.nested_vmx_entry_ctls_low, | |
3097 | vmx->nested.nested_vmx_entry_ctls_high); | |
0115f9cb DM |
3098 | if (msr_index == MSR_IA32_VMX_ENTRY_CTLS) |
3099 | *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3100 | break; |
3101 | case MSR_IA32_VMX_MISC: | |
b9c237bb WV |
3102 | *pdata = vmx_control_msr( |
3103 | vmx->nested.nested_vmx_misc_low, | |
3104 | vmx->nested.nested_vmx_misc_high); | |
b87a51ae | 3105 | break; |
b87a51ae | 3106 | case MSR_IA32_VMX_CR0_FIXED0: |
62cc6b9d | 3107 | *pdata = vmx->nested.nested_vmx_cr0_fixed0; |
b87a51ae NHE |
3108 | break; |
3109 | case MSR_IA32_VMX_CR0_FIXED1: | |
62cc6b9d | 3110 | *pdata = vmx->nested.nested_vmx_cr0_fixed1; |
b87a51ae NHE |
3111 | break; |
3112 | case MSR_IA32_VMX_CR4_FIXED0: | |
62cc6b9d | 3113 | *pdata = vmx->nested.nested_vmx_cr4_fixed0; |
b87a51ae NHE |
3114 | break; |
3115 | case MSR_IA32_VMX_CR4_FIXED1: | |
62cc6b9d | 3116 | *pdata = vmx->nested.nested_vmx_cr4_fixed1; |
b87a51ae NHE |
3117 | break; |
3118 | case MSR_IA32_VMX_VMCS_ENUM: | |
62cc6b9d | 3119 | *pdata = vmx->nested.nested_vmx_vmcs_enum; |
b87a51ae NHE |
3120 | break; |
3121 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
b9c237bb WV |
3122 | *pdata = vmx_control_msr( |
3123 | vmx->nested.nested_vmx_secondary_ctls_low, | |
3124 | vmx->nested.nested_vmx_secondary_ctls_high); | |
b87a51ae NHE |
3125 | break; |
3126 | case MSR_IA32_VMX_EPT_VPID_CAP: | |
089d7b6e WL |
3127 | *pdata = vmx->nested.nested_vmx_ept_caps | |
3128 | ((u64)vmx->nested.nested_vmx_vpid_caps << 32); | |
b87a51ae NHE |
3129 | break; |
3130 | default: | |
b87a51ae | 3131 | return 1; |
b3897a49 NHE |
3132 | } |
3133 | ||
b87a51ae NHE |
3134 | return 0; |
3135 | } | |
3136 | ||
37e4c997 HZ |
3137 | static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, |
3138 | uint64_t val) | |
3139 | { | |
3140 | uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; | |
3141 | ||
3142 | return !(val & ~valid_bits); | |
3143 | } | |
3144 | ||
6aa8b732 AK |
3145 | /* |
3146 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
3147 | * Returns 0 on success, non-0 otherwise. | |
3148 | * Assumes vcpu_load() was already called. | |
3149 | */ | |
609e36d3 | 3150 | static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3151 | { |
26bb0981 | 3152 | struct shared_msr_entry *msr; |
6aa8b732 | 3153 | |
609e36d3 | 3154 | switch (msr_info->index) { |
05b3e0c2 | 3155 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3156 | case MSR_FS_BASE: |
609e36d3 | 3157 | msr_info->data = vmcs_readl(GUEST_FS_BASE); |
6aa8b732 AK |
3158 | break; |
3159 | case MSR_GS_BASE: | |
609e36d3 | 3160 | msr_info->data = vmcs_readl(GUEST_GS_BASE); |
6aa8b732 | 3161 | break; |
44ea2b17 AK |
3162 | case MSR_KERNEL_GS_BASE: |
3163 | vmx_load_host_state(to_vmx(vcpu)); | |
609e36d3 | 3164 | msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base; |
44ea2b17 | 3165 | break; |
26bb0981 | 3166 | #endif |
6aa8b732 | 3167 | case MSR_EFER: |
609e36d3 | 3168 | return kvm_get_msr_common(vcpu, msr_info); |
af24a4e4 | 3169 | case MSR_IA32_TSC: |
be7b263e | 3170 | msr_info->data = guest_read_tsc(vcpu); |
6aa8b732 AK |
3171 | break; |
3172 | case MSR_IA32_SYSENTER_CS: | |
609e36d3 | 3173 | msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); |
6aa8b732 AK |
3174 | break; |
3175 | case MSR_IA32_SYSENTER_EIP: | |
609e36d3 | 3176 | msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
3177 | break; |
3178 | case MSR_IA32_SYSENTER_ESP: | |
609e36d3 | 3179 | msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 3180 | break; |
0dd376e7 | 3181 | case MSR_IA32_BNDCFGS: |
a87036ad | 3182 | if (!kvm_mpx_supported()) |
93c4adc7 | 3183 | return 1; |
609e36d3 | 3184 | msr_info->data = vmcs_read64(GUEST_BNDCFGS); |
0dd376e7 | 3185 | break; |
c45dcc71 AR |
3186 | case MSR_IA32_MCG_EXT_CTL: |
3187 | if (!msr_info->host_initiated && | |
3188 | !(to_vmx(vcpu)->msr_ia32_feature_control & | |
3189 | FEATURE_CONTROL_LMCE)) | |
cae50139 | 3190 | return 1; |
c45dcc71 AR |
3191 | msr_info->data = vcpu->arch.mcg_ext_ctl; |
3192 | break; | |
cae50139 | 3193 | case MSR_IA32_FEATURE_CONTROL: |
3b84080b | 3194 | msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control; |
cae50139 JK |
3195 | break; |
3196 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
3197 | if (!nested_vmx_allowed(vcpu)) | |
3198 | return 1; | |
609e36d3 | 3199 | return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data); |
20300099 WL |
3200 | case MSR_IA32_XSS: |
3201 | if (!vmx_xsaves_supported()) | |
3202 | return 1; | |
609e36d3 | 3203 | msr_info->data = vcpu->arch.ia32_xss; |
20300099 | 3204 | break; |
4e47c7a6 | 3205 | case MSR_TSC_AUX: |
81b1b9ca | 3206 | if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated) |
4e47c7a6 SY |
3207 | return 1; |
3208 | /* Otherwise falls through */ | |
6aa8b732 | 3209 | default: |
609e36d3 | 3210 | msr = find_msr_entry(to_vmx(vcpu), msr_info->index); |
3bab1f5d | 3211 | if (msr) { |
609e36d3 | 3212 | msr_info->data = msr->data; |
3bab1f5d | 3213 | break; |
6aa8b732 | 3214 | } |
609e36d3 | 3215 | return kvm_get_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3216 | } |
3217 | ||
6aa8b732 AK |
3218 | return 0; |
3219 | } | |
3220 | ||
cae50139 JK |
3221 | static void vmx_leave_nested(struct kvm_vcpu *vcpu); |
3222 | ||
6aa8b732 AK |
3223 | /* |
3224 | * Writes msr value into into the appropriate "register". | |
3225 | * Returns 0 on success, non-0 otherwise. | |
3226 | * Assumes vcpu_load() was already called. | |
3227 | */ | |
8fe8ab46 | 3228 | static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3229 | { |
a2fa3e9f | 3230 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 3231 | struct shared_msr_entry *msr; |
2cc51560 | 3232 | int ret = 0; |
8fe8ab46 WA |
3233 | u32 msr_index = msr_info->index; |
3234 | u64 data = msr_info->data; | |
2cc51560 | 3235 | |
6aa8b732 | 3236 | switch (msr_index) { |
3bab1f5d | 3237 | case MSR_EFER: |
8fe8ab46 | 3238 | ret = kvm_set_msr_common(vcpu, msr_info); |
2cc51560 | 3239 | break; |
16175a79 | 3240 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3241 | case MSR_FS_BASE: |
2fb92db1 | 3242 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
3243 | vmcs_writel(GUEST_FS_BASE, data); |
3244 | break; | |
3245 | case MSR_GS_BASE: | |
2fb92db1 | 3246 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
3247 | vmcs_writel(GUEST_GS_BASE, data); |
3248 | break; | |
44ea2b17 AK |
3249 | case MSR_KERNEL_GS_BASE: |
3250 | vmx_load_host_state(vmx); | |
3251 | vmx->msr_guest_kernel_gs_base = data; | |
3252 | break; | |
6aa8b732 AK |
3253 | #endif |
3254 | case MSR_IA32_SYSENTER_CS: | |
3255 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
3256 | break; | |
3257 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 3258 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
3259 | break; |
3260 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 3261 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 3262 | break; |
0dd376e7 | 3263 | case MSR_IA32_BNDCFGS: |
a87036ad | 3264 | if (!kvm_mpx_supported()) |
93c4adc7 | 3265 | return 1; |
0dd376e7 LJ |
3266 | vmcs_write64(GUEST_BNDCFGS, data); |
3267 | break; | |
af24a4e4 | 3268 | case MSR_IA32_TSC: |
8fe8ab46 | 3269 | kvm_write_tsc(vcpu, msr_info); |
6aa8b732 | 3270 | break; |
468d472f SY |
3271 | case MSR_IA32_CR_PAT: |
3272 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
4566654b NA |
3273 | if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data)) |
3274 | return 1; | |
468d472f SY |
3275 | vmcs_write64(GUEST_IA32_PAT, data); |
3276 | vcpu->arch.pat = data; | |
3277 | break; | |
3278 | } | |
8fe8ab46 | 3279 | ret = kvm_set_msr_common(vcpu, msr_info); |
4e47c7a6 | 3280 | break; |
ba904635 WA |
3281 | case MSR_IA32_TSC_ADJUST: |
3282 | ret = kvm_set_msr_common(vcpu, msr_info); | |
4e47c7a6 | 3283 | break; |
c45dcc71 AR |
3284 | case MSR_IA32_MCG_EXT_CTL: |
3285 | if ((!msr_info->host_initiated && | |
3286 | !(to_vmx(vcpu)->msr_ia32_feature_control & | |
3287 | FEATURE_CONTROL_LMCE)) || | |
3288 | (data & ~MCG_EXT_CTL_LMCE_EN)) | |
3289 | return 1; | |
3290 | vcpu->arch.mcg_ext_ctl = data; | |
3291 | break; | |
cae50139 | 3292 | case MSR_IA32_FEATURE_CONTROL: |
37e4c997 | 3293 | if (!vmx_feature_control_msr_valid(vcpu, data) || |
3b84080b | 3294 | (to_vmx(vcpu)->msr_ia32_feature_control & |
cae50139 JK |
3295 | FEATURE_CONTROL_LOCKED && !msr_info->host_initiated)) |
3296 | return 1; | |
3b84080b | 3297 | vmx->msr_ia32_feature_control = data; |
cae50139 JK |
3298 | if (msr_info->host_initiated && data == 0) |
3299 | vmx_leave_nested(vcpu); | |
3300 | break; | |
3301 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
62cc6b9d DM |
3302 | if (!msr_info->host_initiated) |
3303 | return 1; /* they are read-only */ | |
3304 | if (!nested_vmx_allowed(vcpu)) | |
3305 | return 1; | |
3306 | return vmx_set_vmx_msr(vcpu, msr_index, data); | |
20300099 WL |
3307 | case MSR_IA32_XSS: |
3308 | if (!vmx_xsaves_supported()) | |
3309 | return 1; | |
3310 | /* | |
3311 | * The only supported bit as of Skylake is bit 8, but | |
3312 | * it is not supported on KVM. | |
3313 | */ | |
3314 | if (data != 0) | |
3315 | return 1; | |
3316 | vcpu->arch.ia32_xss = data; | |
3317 | if (vcpu->arch.ia32_xss != host_xss) | |
3318 | add_atomic_switch_msr(vmx, MSR_IA32_XSS, | |
3319 | vcpu->arch.ia32_xss, host_xss); | |
3320 | else | |
3321 | clear_atomic_switch_msr(vmx, MSR_IA32_XSS); | |
3322 | break; | |
4e47c7a6 | 3323 | case MSR_TSC_AUX: |
81b1b9ca | 3324 | if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated) |
4e47c7a6 SY |
3325 | return 1; |
3326 | /* Check reserved bit, higher 32 bits should be zero */ | |
3327 | if ((data >> 32) != 0) | |
3328 | return 1; | |
3329 | /* Otherwise falls through */ | |
6aa8b732 | 3330 | default: |
8b9cf98c | 3331 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d | 3332 | if (msr) { |
8b3c3104 | 3333 | u64 old_msr_data = msr->data; |
3bab1f5d | 3334 | msr->data = data; |
2225fd56 AK |
3335 | if (msr - vmx->guest_msrs < vmx->save_nmsrs) { |
3336 | preempt_disable(); | |
8b3c3104 AH |
3337 | ret = kvm_set_shared_msr(msr->index, msr->data, |
3338 | msr->mask); | |
2225fd56 | 3339 | preempt_enable(); |
8b3c3104 AH |
3340 | if (ret) |
3341 | msr->data = old_msr_data; | |
2225fd56 | 3342 | } |
3bab1f5d | 3343 | break; |
6aa8b732 | 3344 | } |
8fe8ab46 | 3345 | ret = kvm_set_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3346 | } |
3347 | ||
2cc51560 | 3348 | return ret; |
6aa8b732 AK |
3349 | } |
3350 | ||
5fdbf976 | 3351 | static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
6aa8b732 | 3352 | { |
5fdbf976 MT |
3353 | __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); |
3354 | switch (reg) { | |
3355 | case VCPU_REGS_RSP: | |
3356 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
3357 | break; | |
3358 | case VCPU_REGS_RIP: | |
3359 | vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); | |
3360 | break; | |
6de4f3ad AK |
3361 | case VCPU_EXREG_PDPTR: |
3362 | if (enable_ept) | |
3363 | ept_save_pdptrs(vcpu); | |
3364 | break; | |
5fdbf976 MT |
3365 | default: |
3366 | break; | |
3367 | } | |
6aa8b732 AK |
3368 | } |
3369 | ||
6aa8b732 AK |
3370 | static __init int cpu_has_kvm_support(void) |
3371 | { | |
6210e37b | 3372 | return cpu_has_vmx(); |
6aa8b732 AK |
3373 | } |
3374 | ||
3375 | static __init int vmx_disabled_by_bios(void) | |
3376 | { | |
3377 | u64 msr; | |
3378 | ||
3379 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
cafd6659 | 3380 | if (msr & FEATURE_CONTROL_LOCKED) { |
23f3e991 | 3381 | /* launched w/ TXT and VMX disabled */ |
cafd6659 SW |
3382 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
3383 | && tboot_enabled()) | |
3384 | return 1; | |
23f3e991 | 3385 | /* launched w/o TXT and VMX only enabled w/ TXT */ |
cafd6659 | 3386 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) |
23f3e991 | 3387 | && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
f9335afe SW |
3388 | && !tboot_enabled()) { |
3389 | printk(KERN_WARNING "kvm: disable TXT in the BIOS or " | |
23f3e991 | 3390 | "activate TXT before enabling KVM\n"); |
cafd6659 | 3391 | return 1; |
f9335afe | 3392 | } |
23f3e991 JC |
3393 | /* launched w/o TXT and VMX disabled */ |
3394 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) | |
3395 | && !tboot_enabled()) | |
3396 | return 1; | |
cafd6659 SW |
3397 | } |
3398 | ||
3399 | return 0; | |
6aa8b732 AK |
3400 | } |
3401 | ||
7725b894 DX |
3402 | static void kvm_cpu_vmxon(u64 addr) |
3403 | { | |
fe0e80be | 3404 | cr4_set_bits(X86_CR4_VMXE); |
1c5ac21a AS |
3405 | intel_pt_handle_vmx(1); |
3406 | ||
7725b894 DX |
3407 | asm volatile (ASM_VMX_VMXON_RAX |
3408 | : : "a"(&addr), "m"(addr) | |
3409 | : "memory", "cc"); | |
3410 | } | |
3411 | ||
13a34e06 | 3412 | static int hardware_enable(void) |
6aa8b732 AK |
3413 | { |
3414 | int cpu = raw_smp_processor_id(); | |
3415 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
cafd6659 | 3416 | u64 old, test_bits; |
6aa8b732 | 3417 | |
1e02ce4c | 3418 | if (cr4_read_shadow() & X86_CR4_VMXE) |
10474ae8 AG |
3419 | return -EBUSY; |
3420 | ||
d462b819 | 3421 | INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); |
bf9f6ac8 FW |
3422 | INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); |
3423 | spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
8f536b76 ZY |
3424 | |
3425 | /* | |
3426 | * Now we can enable the vmclear operation in kdump | |
3427 | * since the loaded_vmcss_on_cpu list on this cpu | |
3428 | * has been initialized. | |
3429 | * | |
3430 | * Though the cpu is not in VMX operation now, there | |
3431 | * is no problem to enable the vmclear operation | |
3432 | * for the loaded_vmcss_on_cpu list is empty! | |
3433 | */ | |
3434 | crash_enable_local_vmclear(cpu); | |
3435 | ||
6aa8b732 | 3436 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
cafd6659 SW |
3437 | |
3438 | test_bits = FEATURE_CONTROL_LOCKED; | |
3439 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
3440 | if (tboot_enabled()) | |
3441 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; | |
3442 | ||
3443 | if ((old & test_bits) != test_bits) { | |
6aa8b732 | 3444 | /* enable and lock */ |
cafd6659 SW |
3445 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); |
3446 | } | |
fe0e80be DH |
3447 | kvm_cpu_vmxon(phys_addr); |
3448 | ept_sync_global(); | |
10474ae8 | 3449 | |
89cbc767 | 3450 | native_store_gdt(this_cpu_ptr(&host_gdt)); |
3444d7da | 3451 | |
10474ae8 | 3452 | return 0; |
6aa8b732 AK |
3453 | } |
3454 | ||
d462b819 | 3455 | static void vmclear_local_loaded_vmcss(void) |
543e4243 AK |
3456 | { |
3457 | int cpu = raw_smp_processor_id(); | |
d462b819 | 3458 | struct loaded_vmcs *v, *n; |
543e4243 | 3459 | |
d462b819 NHE |
3460 | list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), |
3461 | loaded_vmcss_on_cpu_link) | |
3462 | __loaded_vmcs_clear(v); | |
543e4243 AK |
3463 | } |
3464 | ||
710ff4a8 EH |
3465 | |
3466 | /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() | |
3467 | * tricks. | |
3468 | */ | |
3469 | static void kvm_cpu_vmxoff(void) | |
6aa8b732 | 3470 | { |
4ecac3fd | 3471 | asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
1c5ac21a AS |
3472 | |
3473 | intel_pt_handle_vmx(0); | |
fe0e80be | 3474 | cr4_clear_bits(X86_CR4_VMXE); |
6aa8b732 AK |
3475 | } |
3476 | ||
13a34e06 | 3477 | static void hardware_disable(void) |
710ff4a8 | 3478 | { |
fe0e80be DH |
3479 | vmclear_local_loaded_vmcss(); |
3480 | kvm_cpu_vmxoff(); | |
710ff4a8 EH |
3481 | } |
3482 | ||
1c3d14fe | 3483 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 3484 | u32 msr, u32 *result) |
1c3d14fe YS |
3485 | { |
3486 | u32 vmx_msr_low, vmx_msr_high; | |
3487 | u32 ctl = ctl_min | ctl_opt; | |
3488 | ||
3489 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
3490 | ||
3491 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
3492 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
3493 | ||
3494 | /* Ensure minimum (required) set of control bits are supported. */ | |
3495 | if (ctl_min & ~ctl) | |
002c7f7c | 3496 | return -EIO; |
1c3d14fe YS |
3497 | |
3498 | *result = ctl; | |
3499 | return 0; | |
3500 | } | |
3501 | ||
110312c8 AK |
3502 | static __init bool allow_1_setting(u32 msr, u32 ctl) |
3503 | { | |
3504 | u32 vmx_msr_low, vmx_msr_high; | |
3505 | ||
3506 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
3507 | return vmx_msr_high & ctl; | |
3508 | } | |
3509 | ||
002c7f7c | 3510 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
3511 | { |
3512 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 3513 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
3514 | u32 _pin_based_exec_control = 0; |
3515 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 3516 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
3517 | u32 _vmexit_control = 0; |
3518 | u32 _vmentry_control = 0; | |
3519 | ||
10166744 | 3520 | min = CPU_BASED_HLT_EXITING | |
1c3d14fe YS |
3521 | #ifdef CONFIG_X86_64 |
3522 | CPU_BASED_CR8_LOAD_EXITING | | |
3523 | CPU_BASED_CR8_STORE_EXITING | | |
3524 | #endif | |
d56f546d SY |
3525 | CPU_BASED_CR3_LOAD_EXITING | |
3526 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
3527 | CPU_BASED_USE_IO_BITMAPS | |
3528 | CPU_BASED_MOV_DR_EXITING | | |
a7052897 | 3529 | CPU_BASED_USE_TSC_OFFSETING | |
fee84b07 AK |
3530 | CPU_BASED_INVLPG_EXITING | |
3531 | CPU_BASED_RDPMC_EXITING; | |
443381a8 | 3532 | |
668fffa3 MT |
3533 | if (!kvm_mwait_in_guest()) |
3534 | min |= CPU_BASED_MWAIT_EXITING | | |
3535 | CPU_BASED_MONITOR_EXITING; | |
3536 | ||
f78e0e2e | 3537 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 3538 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 3539 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
3540 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
3541 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 3542 | return -EIO; |
6e5d865c YS |
3543 | #ifdef CONFIG_X86_64 |
3544 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
3545 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
3546 | ~CPU_BASED_CR8_STORE_EXITING; | |
3547 | #endif | |
f78e0e2e | 3548 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
3549 | min2 = 0; |
3550 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
8d14695f | 3551 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
2384d2b3 | 3552 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d | 3553 | SECONDARY_EXEC_ENABLE_VPID | |
3a624e29 | 3554 | SECONDARY_EXEC_ENABLE_EPT | |
4b8d54f9 | 3555 | SECONDARY_EXEC_UNRESTRICTED_GUEST | |
4e47c7a6 | 3556 | SECONDARY_EXEC_PAUSE_LOOP_EXITING | |
ad756a16 | 3557 | SECONDARY_EXEC_RDTSCP | |
83d4c286 | 3558 | SECONDARY_EXEC_ENABLE_INVPCID | |
c7c9c56c | 3559 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
abc4fc58 | 3560 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
20300099 | 3561 | SECONDARY_EXEC_SHADOW_VMCS | |
843e4330 | 3562 | SECONDARY_EXEC_XSAVES | |
8b3e34e4 | 3563 | SECONDARY_EXEC_ENABLE_PML | |
64903d61 | 3564 | SECONDARY_EXEC_TSC_SCALING; |
d56f546d SY |
3565 | if (adjust_vmx_controls(min2, opt2, |
3566 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
3567 | &_cpu_based_2nd_exec_control) < 0) |
3568 | return -EIO; | |
3569 | } | |
3570 | #ifndef CONFIG_X86_64 | |
3571 | if (!(_cpu_based_2nd_exec_control & | |
3572 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
3573 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
3574 | #endif | |
83d4c286 YZ |
3575 | |
3576 | if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
3577 | _cpu_based_2nd_exec_control &= ~( | |
8d14695f | 3578 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
c7c9c56c YZ |
3579 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
3580 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
83d4c286 | 3581 | |
d56f546d | 3582 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
a7052897 MT |
3583 | /* CR3 accesses and invlpg don't need to cause VM Exits when EPT |
3584 | enabled */ | |
5fff7d27 GN |
3585 | _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | |
3586 | CPU_BASED_CR3_STORE_EXITING | | |
3587 | CPU_BASED_INVLPG_EXITING); | |
d56f546d SY |
3588 | rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, |
3589 | vmx_capability.ept, vmx_capability.vpid); | |
3590 | } | |
1c3d14fe | 3591 | |
91fa0f8e | 3592 | min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; |
1c3d14fe YS |
3593 | #ifdef CONFIG_X86_64 |
3594 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
3595 | #endif | |
a547c6db | 3596 | opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT | |
91fa0f8e | 3597 | VM_EXIT_CLEAR_BNDCFGS; |
1c3d14fe YS |
3598 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, |
3599 | &_vmexit_control) < 0) | |
002c7f7c | 3600 | return -EIO; |
1c3d14fe | 3601 | |
2c82878b PB |
3602 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING | |
3603 | PIN_BASED_VIRTUAL_NMIS; | |
3604 | opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
3605 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
3606 | &_pin_based_exec_control) < 0) | |
3607 | return -EIO; | |
3608 | ||
1c17c3e6 PB |
3609 | if (cpu_has_broken_vmx_preemption_timer()) |
3610 | _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be | 3611 | if (!(_cpu_based_2nd_exec_control & |
91fa0f8e | 3612 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) |
01e439be YZ |
3613 | _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; |
3614 | ||
c845f9c6 | 3615 | min = VM_ENTRY_LOAD_DEBUG_CONTROLS; |
da8999d3 | 3616 | opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS; |
1c3d14fe YS |
3617 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, |
3618 | &_vmentry_control) < 0) | |
002c7f7c | 3619 | return -EIO; |
6aa8b732 | 3620 | |
c68876fd | 3621 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
3622 | |
3623 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
3624 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 3625 | return -EIO; |
1c3d14fe YS |
3626 | |
3627 | #ifdef CONFIG_X86_64 | |
3628 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
3629 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 3630 | return -EIO; |
1c3d14fe YS |
3631 | #endif |
3632 | ||
3633 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
3634 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 3635 | return -EIO; |
1c3d14fe | 3636 | |
002c7f7c | 3637 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
16cb0255 | 3638 | vmcs_conf->order = get_order(vmcs_conf->size); |
9ac7e3e8 | 3639 | vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; |
002c7f7c | 3640 | vmcs_conf->revision_id = vmx_msr_low; |
1c3d14fe | 3641 | |
002c7f7c YS |
3642 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
3643 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 3644 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
3645 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
3646 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe | 3647 | |
110312c8 AK |
3648 | cpu_has_load_ia32_efer = |
3649 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
3650 | VM_ENTRY_LOAD_IA32_EFER) | |
3651 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
3652 | VM_EXIT_LOAD_IA32_EFER); | |
3653 | ||
8bf00a52 GN |
3654 | cpu_has_load_perf_global_ctrl = |
3655 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
3656 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
3657 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
3658 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
3659 | ||
3660 | /* | |
3661 | * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL | |
bb3541f1 | 3662 | * but due to errata below it can't be used. Workaround is to use |
8bf00a52 GN |
3663 | * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL. |
3664 | * | |
3665 | * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32] | |
3666 | * | |
3667 | * AAK155 (model 26) | |
3668 | * AAP115 (model 30) | |
3669 | * AAT100 (model 37) | |
3670 | * BC86,AAY89,BD102 (model 44) | |
3671 | * BA97 (model 46) | |
3672 | * | |
3673 | */ | |
3674 | if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) { | |
3675 | switch (boot_cpu_data.x86_model) { | |
3676 | case 26: | |
3677 | case 30: | |
3678 | case 37: | |
3679 | case 44: | |
3680 | case 46: | |
3681 | cpu_has_load_perf_global_ctrl = false; | |
3682 | printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " | |
3683 | "does not work properly. Using workaround\n"); | |
3684 | break; | |
3685 | default: | |
3686 | break; | |
3687 | } | |
3688 | } | |
3689 | ||
782511b0 | 3690 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
20300099 WL |
3691 | rdmsrl(MSR_IA32_XSS, host_xss); |
3692 | ||
1c3d14fe | 3693 | return 0; |
c68876fd | 3694 | } |
6aa8b732 AK |
3695 | |
3696 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
3697 | { | |
3698 | int node = cpu_to_node(cpu); | |
3699 | struct page *pages; | |
3700 | struct vmcs *vmcs; | |
3701 | ||
96db800f | 3702 | pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
3703 | if (!pages) |
3704 | return NULL; | |
3705 | vmcs = page_address(pages); | |
1c3d14fe YS |
3706 | memset(vmcs, 0, vmcs_config.size); |
3707 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
3708 | return vmcs; |
3709 | } | |
3710 | ||
3711 | static struct vmcs *alloc_vmcs(void) | |
3712 | { | |
d3b2c338 | 3713 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
3714 | } |
3715 | ||
3716 | static void free_vmcs(struct vmcs *vmcs) | |
3717 | { | |
1c3d14fe | 3718 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
3719 | } |
3720 | ||
d462b819 NHE |
3721 | /* |
3722 | * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded | |
3723 | */ | |
3724 | static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) | |
3725 | { | |
3726 | if (!loaded_vmcs->vmcs) | |
3727 | return; | |
3728 | loaded_vmcs_clear(loaded_vmcs); | |
3729 | free_vmcs(loaded_vmcs->vmcs); | |
3730 | loaded_vmcs->vmcs = NULL; | |
355f4fb1 | 3731 | WARN_ON(loaded_vmcs->shadow_vmcs != NULL); |
d462b819 NHE |
3732 | } |
3733 | ||
39959588 | 3734 | static void free_kvm_area(void) |
6aa8b732 AK |
3735 | { |
3736 | int cpu; | |
3737 | ||
3230bb47 | 3738 | for_each_possible_cpu(cpu) { |
6aa8b732 | 3739 | free_vmcs(per_cpu(vmxarea, cpu)); |
3230bb47 ZA |
3740 | per_cpu(vmxarea, cpu) = NULL; |
3741 | } | |
6aa8b732 AK |
3742 | } |
3743 | ||
fe2b201b BD |
3744 | static void init_vmcs_shadow_fields(void) |
3745 | { | |
3746 | int i, j; | |
3747 | ||
3748 | /* No checks for read only fields yet */ | |
3749 | ||
3750 | for (i = j = 0; i < max_shadow_read_write_fields; i++) { | |
3751 | switch (shadow_read_write_fields[i]) { | |
3752 | case GUEST_BNDCFGS: | |
a87036ad | 3753 | if (!kvm_mpx_supported()) |
fe2b201b BD |
3754 | continue; |
3755 | break; | |
3756 | default: | |
3757 | break; | |
3758 | } | |
3759 | ||
3760 | if (j < i) | |
3761 | shadow_read_write_fields[j] = | |
3762 | shadow_read_write_fields[i]; | |
3763 | j++; | |
3764 | } | |
3765 | max_shadow_read_write_fields = j; | |
3766 | ||
3767 | /* shadowed fields guest access without vmexit */ | |
3768 | for (i = 0; i < max_shadow_read_write_fields; i++) { | |
3769 | clear_bit(shadow_read_write_fields[i], | |
3770 | vmx_vmwrite_bitmap); | |
3771 | clear_bit(shadow_read_write_fields[i], | |
3772 | vmx_vmread_bitmap); | |
3773 | } | |
3774 | for (i = 0; i < max_shadow_read_only_fields; i++) | |
3775 | clear_bit(shadow_read_only_fields[i], | |
3776 | vmx_vmread_bitmap); | |
3777 | } | |
3778 | ||
6aa8b732 AK |
3779 | static __init int alloc_kvm_area(void) |
3780 | { | |
3781 | int cpu; | |
3782 | ||
3230bb47 | 3783 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
3784 | struct vmcs *vmcs; |
3785 | ||
3786 | vmcs = alloc_vmcs_cpu(cpu); | |
3787 | if (!vmcs) { | |
3788 | free_kvm_area(); | |
3789 | return -ENOMEM; | |
3790 | } | |
3791 | ||
3792 | per_cpu(vmxarea, cpu) = vmcs; | |
3793 | } | |
3794 | return 0; | |
3795 | } | |
3796 | ||
14168786 GN |
3797 | static bool emulation_required(struct kvm_vcpu *vcpu) |
3798 | { | |
3799 | return emulate_invalid_guest_state && !guest_state_valid(vcpu); | |
3800 | } | |
3801 | ||
91b0aa2c | 3802 | static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, |
d99e4152 | 3803 | struct kvm_segment *save) |
6aa8b732 | 3804 | { |
d99e4152 GN |
3805 | if (!emulate_invalid_guest_state) { |
3806 | /* | |
3807 | * CS and SS RPL should be equal during guest entry according | |
3808 | * to VMX spec, but in reality it is not always so. Since vcpu | |
3809 | * is in the middle of the transition from real mode to | |
3810 | * protected mode it is safe to assume that RPL 0 is a good | |
3811 | * default value. | |
3812 | */ | |
3813 | if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) | |
b32a9918 NA |
3814 | save->selector &= ~SEGMENT_RPL_MASK; |
3815 | save->dpl = save->selector & SEGMENT_RPL_MASK; | |
d99e4152 | 3816 | save->s = 1; |
6aa8b732 | 3817 | } |
d99e4152 | 3818 | vmx_set_segment(vcpu, save, seg); |
6aa8b732 AK |
3819 | } |
3820 | ||
3821 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
3822 | { | |
3823 | unsigned long flags; | |
a89a8fb9 | 3824 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 3825 | |
d99e4152 GN |
3826 | /* |
3827 | * Update real mode segment cache. It may be not up-to-date if sement | |
3828 | * register was written while vcpu was in a guest mode. | |
3829 | */ | |
3830 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
3831 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
3832 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
3833 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
3834 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); | |
3835 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
3836 | ||
7ffd92c5 | 3837 | vmx->rmode.vm86_active = 0; |
6aa8b732 | 3838 | |
2fb92db1 AK |
3839 | vmx_segment_cache_clear(vmx); |
3840 | ||
f5f7b2fe | 3841 | vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
6aa8b732 AK |
3842 | |
3843 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 AK |
3844 | flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; |
3845 | flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
6aa8b732 AK |
3846 | vmcs_writel(GUEST_RFLAGS, flags); |
3847 | ||
66aee91a RR |
3848 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
3849 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
3850 | |
3851 | update_exception_bitmap(vcpu); | |
3852 | ||
91b0aa2c GN |
3853 | fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); |
3854 | fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); | |
3855 | fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
3856 | fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
3857 | fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
3858 | fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
6aa8b732 AK |
3859 | } |
3860 | ||
f5f7b2fe | 3861 | static void fix_rmode_seg(int seg, struct kvm_segment *save) |
6aa8b732 | 3862 | { |
772e0318 | 3863 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
d99e4152 GN |
3864 | struct kvm_segment var = *save; |
3865 | ||
3866 | var.dpl = 0x3; | |
3867 | if (seg == VCPU_SREG_CS) | |
3868 | var.type = 0x3; | |
3869 | ||
3870 | if (!emulate_invalid_guest_state) { | |
3871 | var.selector = var.base >> 4; | |
3872 | var.base = var.base & 0xffff0; | |
3873 | var.limit = 0xffff; | |
3874 | var.g = 0; | |
3875 | var.db = 0; | |
3876 | var.present = 1; | |
3877 | var.s = 1; | |
3878 | var.l = 0; | |
3879 | var.unusable = 0; | |
3880 | var.type = 0x3; | |
3881 | var.avl = 0; | |
3882 | if (save->base & 0xf) | |
3883 | printk_once(KERN_WARNING "kvm: segment base is not " | |
3884 | "paragraph aligned when entering " | |
3885 | "protected mode (seg=%d)", seg); | |
3886 | } | |
6aa8b732 | 3887 | |
d99e4152 | 3888 | vmcs_write16(sf->selector, var.selector); |
96794e4e | 3889 | vmcs_writel(sf->base, var.base); |
d99e4152 GN |
3890 | vmcs_write32(sf->limit, var.limit); |
3891 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); | |
6aa8b732 AK |
3892 | } |
3893 | ||
3894 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
3895 | { | |
3896 | unsigned long flags; | |
a89a8fb9 | 3897 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 3898 | |
f5f7b2fe AK |
3899 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
3900 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
3901 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
3902 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
3903 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
c6ad1153 GN |
3904 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); |
3905 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
f5f7b2fe | 3906 | |
7ffd92c5 | 3907 | vmx->rmode.vm86_active = 1; |
6aa8b732 | 3908 | |
776e58ea GN |
3909 | /* |
3910 | * Very old userspace does not call KVM_SET_TSS_ADDR before entering | |
4918c6ca | 3911 | * vcpu. Warn the user that an update is overdue. |
776e58ea | 3912 | */ |
4918c6ca | 3913 | if (!vcpu->kvm->arch.tss_addr) |
776e58ea GN |
3914 | printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " |
3915 | "called before entering vcpu\n"); | |
776e58ea | 3916 | |
2fb92db1 AK |
3917 | vmx_segment_cache_clear(vmx); |
3918 | ||
4918c6ca | 3919 | vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr); |
6aa8b732 | 3920 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
6aa8b732 AK |
3921 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
3922 | ||
3923 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 | 3924 | vmx->rmode.save_rflags = flags; |
6aa8b732 | 3925 | |
053de044 | 3926 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
3927 | |
3928 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 3929 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
3930 | update_exception_bitmap(vcpu); |
3931 | ||
d99e4152 GN |
3932 | fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); |
3933 | fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); | |
3934 | fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
3935 | fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
3936 | fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
3937 | fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
b246dd5d | 3938 | |
8668a3c4 | 3939 | kvm_mmu_reset_context(vcpu); |
6aa8b732 AK |
3940 | } |
3941 | ||
401d10de AS |
3942 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
3943 | { | |
3944 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
26bb0981 AK |
3945 | struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); |
3946 | ||
3947 | if (!msr) | |
3948 | return; | |
401d10de | 3949 | |
44ea2b17 AK |
3950 | /* |
3951 | * Force kernel_gs_base reloading before EFER changes, as control | |
3952 | * of this msr depends on is_long_mode(). | |
3953 | */ | |
3954 | vmx_load_host_state(to_vmx(vcpu)); | |
f6801dff | 3955 | vcpu->arch.efer = efer; |
401d10de | 3956 | if (efer & EFER_LMA) { |
2961e876 | 3957 | vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
3958 | msr->data = efer; |
3959 | } else { | |
2961e876 | 3960 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
3961 | |
3962 | msr->data = efer & ~EFER_LME; | |
3963 | } | |
3964 | setup_msrs(vmx); | |
3965 | } | |
3966 | ||
05b3e0c2 | 3967 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
3968 | |
3969 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
3970 | { | |
3971 | u32 guest_tr_ar; | |
3972 | ||
2fb92db1 AK |
3973 | vmx_segment_cache_clear(to_vmx(vcpu)); |
3974 | ||
6aa8b732 | 3975 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); |
4d283ec9 | 3976 | if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { |
bd80158a JK |
3977 | pr_debug_ratelimited("%s: tss fixup for long mode. \n", |
3978 | __func__); | |
6aa8b732 | 3979 | vmcs_write32(GUEST_TR_AR_BYTES, |
4d283ec9 AL |
3980 | (guest_tr_ar & ~VMX_AR_TYPE_MASK) |
3981 | | VMX_AR_TYPE_BUSY_64_TSS); | |
6aa8b732 | 3982 | } |
da38f438 | 3983 | vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); |
6aa8b732 AK |
3984 | } |
3985 | ||
3986 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
3987 | { | |
2961e876 | 3988 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
da38f438 | 3989 | vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); |
6aa8b732 AK |
3990 | } |
3991 | ||
3992 | #endif | |
3993 | ||
dd5f5341 | 3994 | static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid) |
2384d2b3 | 3995 | { |
dd180b3e XG |
3996 | if (enable_ept) { |
3997 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
3998 | return; | |
4e1096d2 | 3999 | ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa)); |
f0b98c02 JM |
4000 | } else { |
4001 | vpid_sync_context(vpid); | |
dd180b3e | 4002 | } |
2384d2b3 SY |
4003 | } |
4004 | ||
dd5f5341 WL |
4005 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
4006 | { | |
4007 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid); | |
4008 | } | |
4009 | ||
fb6c8198 JM |
4010 | static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu) |
4011 | { | |
4012 | if (enable_ept) | |
4013 | vmx_flush_tlb(vcpu); | |
4014 | } | |
4015 | ||
e8467fda AK |
4016 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
4017 | { | |
4018 | ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; | |
4019 | ||
4020 | vcpu->arch.cr0 &= ~cr0_guest_owned_bits; | |
4021 | vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; | |
4022 | } | |
4023 | ||
aff48baa AK |
4024 | static void vmx_decache_cr3(struct kvm_vcpu *vcpu) |
4025 | { | |
4026 | if (enable_ept && is_paging(vcpu)) | |
4027 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); | |
4028 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
4029 | } | |
4030 | ||
25c4c276 | 4031 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 4032 | { |
fc78f519 AK |
4033 | ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; |
4034 | ||
4035 | vcpu->arch.cr4 &= ~cr4_guest_owned_bits; | |
4036 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; | |
399badf3 AK |
4037 | } |
4038 | ||
1439442c SY |
4039 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
4040 | { | |
d0d538b9 GN |
4041 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
4042 | ||
6de4f3ad AK |
4043 | if (!test_bit(VCPU_EXREG_PDPTR, |
4044 | (unsigned long *)&vcpu->arch.regs_dirty)) | |
4045 | return; | |
4046 | ||
1439442c | 4047 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
d0d538b9 GN |
4048 | vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); |
4049 | vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); | |
4050 | vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); | |
4051 | vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); | |
1439442c SY |
4052 | } |
4053 | } | |
4054 | ||
8f5d549f AK |
4055 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu) |
4056 | { | |
d0d538b9 GN |
4057 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
4058 | ||
8f5d549f | 4059 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
d0d538b9 GN |
4060 | mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); |
4061 | mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); | |
4062 | mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); | |
4063 | mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); | |
8f5d549f | 4064 | } |
6de4f3ad AK |
4065 | |
4066 | __set_bit(VCPU_EXREG_PDPTR, | |
4067 | (unsigned long *)&vcpu->arch.regs_avail); | |
4068 | __set_bit(VCPU_EXREG_PDPTR, | |
4069 | (unsigned long *)&vcpu->arch.regs_dirty); | |
8f5d549f AK |
4070 | } |
4071 | ||
3899152c DM |
4072 | static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) |
4073 | { | |
4074 | u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0; | |
4075 | u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1; | |
4076 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
4077 | ||
4078 | if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high & | |
4079 | SECONDARY_EXEC_UNRESTRICTED_GUEST && | |
4080 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST)) | |
4081 | fixed0 &= ~(X86_CR0_PE | X86_CR0_PG); | |
4082 | ||
4083 | return fixed_bits_valid(val, fixed0, fixed1); | |
4084 | } | |
4085 | ||
4086 | static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) | |
4087 | { | |
4088 | u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0; | |
4089 | u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1; | |
4090 | ||
4091 | return fixed_bits_valid(val, fixed0, fixed1); | |
4092 | } | |
4093 | ||
4094 | static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val) | |
4095 | { | |
4096 | u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0; | |
4097 | u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1; | |
4098 | ||
4099 | return fixed_bits_valid(val, fixed0, fixed1); | |
4100 | } | |
4101 | ||
4102 | /* No difference in the restrictions on guest and host CR4 in VMX operation. */ | |
4103 | #define nested_guest_cr4_valid nested_cr4_valid | |
4104 | #define nested_host_cr4_valid nested_cr4_valid | |
4105 | ||
5e1746d6 | 4106 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
1439442c SY |
4107 | |
4108 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
4109 | unsigned long cr0, | |
4110 | struct kvm_vcpu *vcpu) | |
4111 | { | |
5233dd51 MT |
4112 | if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) |
4113 | vmx_decache_cr3(vcpu); | |
1439442c SY |
4114 | if (!(cr0 & X86_CR0_PG)) { |
4115 | /* From paging/starting to nonpaging */ | |
4116 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 4117 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
1439442c SY |
4118 | (CPU_BASED_CR3_LOAD_EXITING | |
4119 | CPU_BASED_CR3_STORE_EXITING)); | |
4120 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 4121 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c SY |
4122 | } else if (!is_paging(vcpu)) { |
4123 | /* From nonpaging to paging */ | |
4124 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 4125 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
1439442c SY |
4126 | ~(CPU_BASED_CR3_LOAD_EXITING | |
4127 | CPU_BASED_CR3_STORE_EXITING)); | |
4128 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 4129 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c | 4130 | } |
95eb84a7 SY |
4131 | |
4132 | if (!(cr0 & X86_CR0_WP)) | |
4133 | *hw_cr0 &= ~X86_CR0_WP; | |
1439442c SY |
4134 | } |
4135 | ||
6aa8b732 AK |
4136 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
4137 | { | |
7ffd92c5 | 4138 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3a624e29 NK |
4139 | unsigned long hw_cr0; |
4140 | ||
5037878e | 4141 | hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK); |
3a624e29 | 4142 | if (enable_unrestricted_guest) |
5037878e | 4143 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; |
218e763f | 4144 | else { |
5037878e | 4145 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; |
1439442c | 4146 | |
218e763f GN |
4147 | if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) |
4148 | enter_pmode(vcpu); | |
6aa8b732 | 4149 | |
218e763f GN |
4150 | if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) |
4151 | enter_rmode(vcpu); | |
4152 | } | |
6aa8b732 | 4153 | |
05b3e0c2 | 4154 | #ifdef CONFIG_X86_64 |
f6801dff | 4155 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 4156 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 4157 | enter_lmode(vcpu); |
707d92fa | 4158 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
4159 | exit_lmode(vcpu); |
4160 | } | |
4161 | #endif | |
4162 | ||
089d034e | 4163 | if (enable_ept) |
1439442c SY |
4164 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); |
4165 | ||
6aa8b732 | 4166 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 4167 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 4168 | vcpu->arch.cr0 = cr0; |
14168786 GN |
4169 | |
4170 | /* depends on vcpu->arch.cr0 to be set to a new value */ | |
4171 | vmx->emulation_required = emulation_required(vcpu); | |
6aa8b732 AK |
4172 | } |
4173 | ||
1439442c SY |
4174 | static u64 construct_eptp(unsigned long root_hpa) |
4175 | { | |
4176 | u64 eptp; | |
4177 | ||
4178 | /* TODO write the value reading from MSR */ | |
4179 | eptp = VMX_EPT_DEFAULT_MT | | |
4180 | VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT; | |
b38f9934 XH |
4181 | if (enable_ept_ad_bits) |
4182 | eptp |= VMX_EPT_AD_ENABLE_BIT; | |
1439442c SY |
4183 | eptp |= (root_hpa & PAGE_MASK); |
4184 | ||
4185 | return eptp; | |
4186 | } | |
4187 | ||
6aa8b732 AK |
4188 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
4189 | { | |
1439442c SY |
4190 | unsigned long guest_cr3; |
4191 | u64 eptp; | |
4192 | ||
4193 | guest_cr3 = cr3; | |
089d034e | 4194 | if (enable_ept) { |
1439442c SY |
4195 | eptp = construct_eptp(cr3); |
4196 | vmcs_write64(EPT_POINTER, eptp); | |
59ab5a8f JK |
4197 | if (is_paging(vcpu) || is_guest_mode(vcpu)) |
4198 | guest_cr3 = kvm_read_cr3(vcpu); | |
4199 | else | |
4200 | guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr; | |
7c93be44 | 4201 | ept_load_pdptrs(vcpu); |
1439442c SY |
4202 | } |
4203 | ||
2384d2b3 | 4204 | vmx_flush_tlb(vcpu); |
1439442c | 4205 | vmcs_writel(GUEST_CR3, guest_cr3); |
6aa8b732 AK |
4206 | } |
4207 | ||
5e1746d6 | 4208 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 4209 | { |
085e68ee BS |
4210 | /* |
4211 | * Pass through host's Machine Check Enable value to hw_cr4, which | |
4212 | * is in force while we are in guest mode. Do not let guests control | |
4213 | * this bit, even if host CR4.MCE == 0. | |
4214 | */ | |
4215 | unsigned long hw_cr4 = | |
4216 | (cr4_read_shadow() & X86_CR4_MCE) | | |
4217 | (cr4 & ~X86_CR4_MCE) | | |
4218 | (to_vmx(vcpu)->rmode.vm86_active ? | |
4219 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); | |
1439442c | 4220 | |
5e1746d6 NHE |
4221 | if (cr4 & X86_CR4_VMXE) { |
4222 | /* | |
4223 | * To use VMXON (and later other VMX instructions), a guest | |
4224 | * must first be able to turn on cr4.VMXE (see handle_vmon()). | |
4225 | * So basically the check on whether to allow nested VMX | |
4226 | * is here. | |
4227 | */ | |
4228 | if (!nested_vmx_allowed(vcpu)) | |
4229 | return 1; | |
1a0d74e6 | 4230 | } |
3899152c DM |
4231 | |
4232 | if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) | |
5e1746d6 NHE |
4233 | return 1; |
4234 | ||
ad312c7c | 4235 | vcpu->arch.cr4 = cr4; |
bc23008b AK |
4236 | if (enable_ept) { |
4237 | if (!is_paging(vcpu)) { | |
4238 | hw_cr4 &= ~X86_CR4_PAE; | |
4239 | hw_cr4 |= X86_CR4_PSE; | |
4240 | } else if (!(cr4 & X86_CR4_PAE)) { | |
4241 | hw_cr4 &= ~X86_CR4_PAE; | |
4242 | } | |
4243 | } | |
1439442c | 4244 | |
656ec4a4 RK |
4245 | if (!enable_unrestricted_guest && !is_paging(vcpu)) |
4246 | /* | |
ddba2628 HH |
4247 | * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in |
4248 | * hardware. To emulate this behavior, SMEP/SMAP/PKU needs | |
4249 | * to be manually disabled when guest switches to non-paging | |
4250 | * mode. | |
4251 | * | |
4252 | * If !enable_unrestricted_guest, the CPU is always running | |
4253 | * with CR0.PG=1 and CR4 needs to be modified. | |
4254 | * If enable_unrestricted_guest, the CPU automatically | |
4255 | * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. | |
656ec4a4 | 4256 | */ |
ddba2628 | 4257 | hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); |
656ec4a4 | 4258 | |
1439442c SY |
4259 | vmcs_writel(CR4_READ_SHADOW, cr4); |
4260 | vmcs_writel(GUEST_CR4, hw_cr4); | |
5e1746d6 | 4261 | return 0; |
6aa8b732 AK |
4262 | } |
4263 | ||
6aa8b732 AK |
4264 | static void vmx_get_segment(struct kvm_vcpu *vcpu, |
4265 | struct kvm_segment *var, int seg) | |
4266 | { | |
a9179499 | 4267 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 AK |
4268 | u32 ar; |
4269 | ||
c6ad1153 | 4270 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
f5f7b2fe | 4271 | *var = vmx->rmode.segs[seg]; |
a9179499 | 4272 | if (seg == VCPU_SREG_TR |
2fb92db1 | 4273 | || var->selector == vmx_read_guest_seg_selector(vmx, seg)) |
f5f7b2fe | 4274 | return; |
1390a28b AK |
4275 | var->base = vmx_read_guest_seg_base(vmx, seg); |
4276 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
4277 | return; | |
a9179499 | 4278 | } |
2fb92db1 AK |
4279 | var->base = vmx_read_guest_seg_base(vmx, seg); |
4280 | var->limit = vmx_read_guest_seg_limit(vmx, seg); | |
4281 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
4282 | ar = vmx_read_guest_seg_ar(vmx, seg); | |
03617c18 | 4283 | var->unusable = (ar >> 16) & 1; |
6aa8b732 AK |
4284 | var->type = ar & 15; |
4285 | var->s = (ar >> 4) & 1; | |
4286 | var->dpl = (ar >> 5) & 3; | |
03617c18 GN |
4287 | /* |
4288 | * Some userspaces do not preserve unusable property. Since usable | |
4289 | * segment has to be present according to VMX spec we can use present | |
4290 | * property to amend userspace bug by making unusable segment always | |
4291 | * nonpresent. vmx_segment_access_rights() already marks nonpresent | |
4292 | * segment as unusable. | |
4293 | */ | |
4294 | var->present = !var->unusable; | |
6aa8b732 AK |
4295 | var->avl = (ar >> 12) & 1; |
4296 | var->l = (ar >> 13) & 1; | |
4297 | var->db = (ar >> 14) & 1; | |
4298 | var->g = (ar >> 15) & 1; | |
6aa8b732 AK |
4299 | } |
4300 | ||
a9179499 AK |
4301 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4302 | { | |
a9179499 AK |
4303 | struct kvm_segment s; |
4304 | ||
4305 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
4306 | vmx_get_segment(vcpu, &s, seg); | |
4307 | return s.base; | |
4308 | } | |
2fb92db1 | 4309 | return vmx_read_guest_seg_base(to_vmx(vcpu), seg); |
a9179499 AK |
4310 | } |
4311 | ||
b09408d0 | 4312 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
2e4d2653 | 4313 | { |
b09408d0 MT |
4314 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4315 | ||
ae9fedc7 | 4316 | if (unlikely(vmx->rmode.vm86_active)) |
2e4d2653 | 4317 | return 0; |
ae9fedc7 PB |
4318 | else { |
4319 | int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); | |
4d283ec9 | 4320 | return VMX_AR_DPL(ar); |
69c73028 | 4321 | } |
69c73028 AK |
4322 | } |
4323 | ||
653e3108 | 4324 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 4325 | { |
6aa8b732 AK |
4326 | u32 ar; |
4327 | ||
f0495f9b | 4328 | if (var->unusable || !var->present) |
6aa8b732 AK |
4329 | ar = 1 << 16; |
4330 | else { | |
4331 | ar = var->type & 15; | |
4332 | ar |= (var->s & 1) << 4; | |
4333 | ar |= (var->dpl & 3) << 5; | |
4334 | ar |= (var->present & 1) << 7; | |
4335 | ar |= (var->avl & 1) << 12; | |
4336 | ar |= (var->l & 1) << 13; | |
4337 | ar |= (var->db & 1) << 14; | |
4338 | ar |= (var->g & 1) << 15; | |
4339 | } | |
653e3108 AK |
4340 | |
4341 | return ar; | |
4342 | } | |
4343 | ||
4344 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
4345 | struct kvm_segment *var, int seg) | |
4346 | { | |
7ffd92c5 | 4347 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
772e0318 | 4348 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
653e3108 | 4349 | |
2fb92db1 AK |
4350 | vmx_segment_cache_clear(vmx); |
4351 | ||
1ecd50a9 GN |
4352 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
4353 | vmx->rmode.segs[seg] = *var; | |
4354 | if (seg == VCPU_SREG_TR) | |
4355 | vmcs_write16(sf->selector, var->selector); | |
4356 | else if (var->s) | |
4357 | fix_rmode_seg(seg, &vmx->rmode.segs[seg]); | |
d99e4152 | 4358 | goto out; |
653e3108 | 4359 | } |
1ecd50a9 | 4360 | |
653e3108 AK |
4361 | vmcs_writel(sf->base, var->base); |
4362 | vmcs_write32(sf->limit, var->limit); | |
4363 | vmcs_write16(sf->selector, var->selector); | |
3a624e29 NK |
4364 | |
4365 | /* | |
4366 | * Fix the "Accessed" bit in AR field of segment registers for older | |
4367 | * qemu binaries. | |
4368 | * IA32 arch specifies that at the time of processor reset the | |
4369 | * "Accessed" bit in the AR field of segment registers is 1. And qemu | |
0fa06071 | 4370 | * is setting it to 0 in the userland code. This causes invalid guest |
3a624e29 NK |
4371 | * state vmexit when "unrestricted guest" mode is turned on. |
4372 | * Fix for this setup issue in cpu_reset is being pushed in the qemu | |
4373 | * tree. Newer qemu binaries with that qemu fix would not need this | |
4374 | * kvm hack. | |
4375 | */ | |
4376 | if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) | |
f924d66d | 4377 | var->type |= 0x1; /* Accessed */ |
3a624e29 | 4378 | |
f924d66d | 4379 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); |
d99e4152 GN |
4380 | |
4381 | out: | |
98eb2f8b | 4382 | vmx->emulation_required = emulation_required(vcpu); |
6aa8b732 AK |
4383 | } |
4384 | ||
6aa8b732 AK |
4385 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
4386 | { | |
2fb92db1 | 4387 | u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); |
6aa8b732 AK |
4388 | |
4389 | *db = (ar >> 14) & 1; | |
4390 | *l = (ar >> 13) & 1; | |
4391 | } | |
4392 | ||
89a27f4d | 4393 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4394 | { |
89a27f4d GN |
4395 | dt->size = vmcs_read32(GUEST_IDTR_LIMIT); |
4396 | dt->address = vmcs_readl(GUEST_IDTR_BASE); | |
6aa8b732 AK |
4397 | } |
4398 | ||
89a27f4d | 4399 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4400 | { |
89a27f4d GN |
4401 | vmcs_write32(GUEST_IDTR_LIMIT, dt->size); |
4402 | vmcs_writel(GUEST_IDTR_BASE, dt->address); | |
6aa8b732 AK |
4403 | } |
4404 | ||
89a27f4d | 4405 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4406 | { |
89a27f4d GN |
4407 | dt->size = vmcs_read32(GUEST_GDTR_LIMIT); |
4408 | dt->address = vmcs_readl(GUEST_GDTR_BASE); | |
6aa8b732 AK |
4409 | } |
4410 | ||
89a27f4d | 4411 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4412 | { |
89a27f4d GN |
4413 | vmcs_write32(GUEST_GDTR_LIMIT, dt->size); |
4414 | vmcs_writel(GUEST_GDTR_BASE, dt->address); | |
6aa8b732 AK |
4415 | } |
4416 | ||
648dfaa7 MG |
4417 | static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) |
4418 | { | |
4419 | struct kvm_segment var; | |
4420 | u32 ar; | |
4421 | ||
4422 | vmx_get_segment(vcpu, &var, seg); | |
07f42f5f | 4423 | var.dpl = 0x3; |
0647f4aa GN |
4424 | if (seg == VCPU_SREG_CS) |
4425 | var.type = 0x3; | |
648dfaa7 MG |
4426 | ar = vmx_segment_access_rights(&var); |
4427 | ||
4428 | if (var.base != (var.selector << 4)) | |
4429 | return false; | |
89efbed0 | 4430 | if (var.limit != 0xffff) |
648dfaa7 | 4431 | return false; |
07f42f5f | 4432 | if (ar != 0xf3) |
648dfaa7 MG |
4433 | return false; |
4434 | ||
4435 | return true; | |
4436 | } | |
4437 | ||
4438 | static bool code_segment_valid(struct kvm_vcpu *vcpu) | |
4439 | { | |
4440 | struct kvm_segment cs; | |
4441 | unsigned int cs_rpl; | |
4442 | ||
4443 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
b32a9918 | 4444 | cs_rpl = cs.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4445 | |
1872a3f4 AK |
4446 | if (cs.unusable) |
4447 | return false; | |
4d283ec9 | 4448 | if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) |
648dfaa7 MG |
4449 | return false; |
4450 | if (!cs.s) | |
4451 | return false; | |
4d283ec9 | 4452 | if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { |
648dfaa7 MG |
4453 | if (cs.dpl > cs_rpl) |
4454 | return false; | |
1872a3f4 | 4455 | } else { |
648dfaa7 MG |
4456 | if (cs.dpl != cs_rpl) |
4457 | return false; | |
4458 | } | |
4459 | if (!cs.present) | |
4460 | return false; | |
4461 | ||
4462 | /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ | |
4463 | return true; | |
4464 | } | |
4465 | ||
4466 | static bool stack_segment_valid(struct kvm_vcpu *vcpu) | |
4467 | { | |
4468 | struct kvm_segment ss; | |
4469 | unsigned int ss_rpl; | |
4470 | ||
4471 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
b32a9918 | 4472 | ss_rpl = ss.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4473 | |
1872a3f4 AK |
4474 | if (ss.unusable) |
4475 | return true; | |
4476 | if (ss.type != 3 && ss.type != 7) | |
648dfaa7 MG |
4477 | return false; |
4478 | if (!ss.s) | |
4479 | return false; | |
4480 | if (ss.dpl != ss_rpl) /* DPL != RPL */ | |
4481 | return false; | |
4482 | if (!ss.present) | |
4483 | return false; | |
4484 | ||
4485 | return true; | |
4486 | } | |
4487 | ||
4488 | static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) | |
4489 | { | |
4490 | struct kvm_segment var; | |
4491 | unsigned int rpl; | |
4492 | ||
4493 | vmx_get_segment(vcpu, &var, seg); | |
b32a9918 | 4494 | rpl = var.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4495 | |
1872a3f4 AK |
4496 | if (var.unusable) |
4497 | return true; | |
648dfaa7 MG |
4498 | if (!var.s) |
4499 | return false; | |
4500 | if (!var.present) | |
4501 | return false; | |
4d283ec9 | 4502 | if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { |
648dfaa7 MG |
4503 | if (var.dpl < rpl) /* DPL < RPL */ |
4504 | return false; | |
4505 | } | |
4506 | ||
4507 | /* TODO: Add other members to kvm_segment_field to allow checking for other access | |
4508 | * rights flags | |
4509 | */ | |
4510 | return true; | |
4511 | } | |
4512 | ||
4513 | static bool tr_valid(struct kvm_vcpu *vcpu) | |
4514 | { | |
4515 | struct kvm_segment tr; | |
4516 | ||
4517 | vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); | |
4518 | ||
1872a3f4 AK |
4519 | if (tr.unusable) |
4520 | return false; | |
b32a9918 | 4521 | if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 | 4522 | return false; |
1872a3f4 | 4523 | if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ |
648dfaa7 MG |
4524 | return false; |
4525 | if (!tr.present) | |
4526 | return false; | |
4527 | ||
4528 | return true; | |
4529 | } | |
4530 | ||
4531 | static bool ldtr_valid(struct kvm_vcpu *vcpu) | |
4532 | { | |
4533 | struct kvm_segment ldtr; | |
4534 | ||
4535 | vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); | |
4536 | ||
1872a3f4 AK |
4537 | if (ldtr.unusable) |
4538 | return true; | |
b32a9918 | 4539 | if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 MG |
4540 | return false; |
4541 | if (ldtr.type != 2) | |
4542 | return false; | |
4543 | if (!ldtr.present) | |
4544 | return false; | |
4545 | ||
4546 | return true; | |
4547 | } | |
4548 | ||
4549 | static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) | |
4550 | { | |
4551 | struct kvm_segment cs, ss; | |
4552 | ||
4553 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
4554 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
4555 | ||
b32a9918 NA |
4556 | return ((cs.selector & SEGMENT_RPL_MASK) == |
4557 | (ss.selector & SEGMENT_RPL_MASK)); | |
648dfaa7 MG |
4558 | } |
4559 | ||
4560 | /* | |
4561 | * Check if guest state is valid. Returns true if valid, false if | |
4562 | * not. | |
4563 | * We assume that registers are always usable | |
4564 | */ | |
4565 | static bool guest_state_valid(struct kvm_vcpu *vcpu) | |
4566 | { | |
c5e97c80 GN |
4567 | if (enable_unrestricted_guest) |
4568 | return true; | |
4569 | ||
648dfaa7 | 4570 | /* real mode guest state checks */ |
f13882d8 | 4571 | if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { |
648dfaa7 MG |
4572 | if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) |
4573 | return false; | |
4574 | if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) | |
4575 | return false; | |
4576 | if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) | |
4577 | return false; | |
4578 | if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) | |
4579 | return false; | |
4580 | if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) | |
4581 | return false; | |
4582 | if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) | |
4583 | return false; | |
4584 | } else { | |
4585 | /* protected mode guest state checks */ | |
4586 | if (!cs_ss_rpl_check(vcpu)) | |
4587 | return false; | |
4588 | if (!code_segment_valid(vcpu)) | |
4589 | return false; | |
4590 | if (!stack_segment_valid(vcpu)) | |
4591 | return false; | |
4592 | if (!data_segment_valid(vcpu, VCPU_SREG_DS)) | |
4593 | return false; | |
4594 | if (!data_segment_valid(vcpu, VCPU_SREG_ES)) | |
4595 | return false; | |
4596 | if (!data_segment_valid(vcpu, VCPU_SREG_FS)) | |
4597 | return false; | |
4598 | if (!data_segment_valid(vcpu, VCPU_SREG_GS)) | |
4599 | return false; | |
4600 | if (!tr_valid(vcpu)) | |
4601 | return false; | |
4602 | if (!ldtr_valid(vcpu)) | |
4603 | return false; | |
4604 | } | |
4605 | /* TODO: | |
4606 | * - Add checks on RIP | |
4607 | * - Add checks on RFLAGS | |
4608 | */ | |
4609 | ||
4610 | return true; | |
4611 | } | |
4612 | ||
d77c26fc | 4613 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 4614 | { |
40dcaa9f | 4615 | gfn_t fn; |
195aefde | 4616 | u16 data = 0; |
1f755a82 | 4617 | int idx, r; |
6aa8b732 | 4618 | |
40dcaa9f | 4619 | idx = srcu_read_lock(&kvm->srcu); |
4918c6ca | 4620 | fn = kvm->arch.tss_addr >> PAGE_SHIFT; |
195aefde IE |
4621 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
4622 | if (r < 0) | |
10589a46 | 4623 | goto out; |
195aefde | 4624 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
464d17c8 SY |
4625 | r = kvm_write_guest_page(kvm, fn++, &data, |
4626 | TSS_IOPB_BASE_OFFSET, sizeof(u16)); | |
195aefde | 4627 | if (r < 0) |
10589a46 | 4628 | goto out; |
195aefde IE |
4629 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
4630 | if (r < 0) | |
10589a46 | 4631 | goto out; |
195aefde IE |
4632 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
4633 | if (r < 0) | |
10589a46 | 4634 | goto out; |
195aefde | 4635 | data = ~0; |
10589a46 MT |
4636 | r = kvm_write_guest_page(kvm, fn, &data, |
4637 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
4638 | sizeof(u8)); | |
10589a46 | 4639 | out: |
40dcaa9f | 4640 | srcu_read_unlock(&kvm->srcu, idx); |
1f755a82 | 4641 | return r; |
6aa8b732 AK |
4642 | } |
4643 | ||
b7ebfb05 SY |
4644 | static int init_rmode_identity_map(struct kvm *kvm) |
4645 | { | |
f51770ed | 4646 | int i, idx, r = 0; |
ba049e93 | 4647 | kvm_pfn_t identity_map_pfn; |
b7ebfb05 SY |
4648 | u32 tmp; |
4649 | ||
089d034e | 4650 | if (!enable_ept) |
f51770ed | 4651 | return 0; |
a255d479 TC |
4652 | |
4653 | /* Protect kvm->arch.ept_identity_pagetable_done. */ | |
4654 | mutex_lock(&kvm->slots_lock); | |
4655 | ||
f51770ed | 4656 | if (likely(kvm->arch.ept_identity_pagetable_done)) |
a255d479 | 4657 | goto out2; |
a255d479 | 4658 | |
b927a3ce | 4659 | identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT; |
a255d479 TC |
4660 | |
4661 | r = alloc_identity_pagetable(kvm); | |
f51770ed | 4662 | if (r < 0) |
a255d479 TC |
4663 | goto out2; |
4664 | ||
40dcaa9f | 4665 | idx = srcu_read_lock(&kvm->srcu); |
b7ebfb05 SY |
4666 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); |
4667 | if (r < 0) | |
4668 | goto out; | |
4669 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
4670 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
4671 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
4672 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
4673 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
4674 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
4675 | if (r < 0) | |
4676 | goto out; | |
4677 | } | |
4678 | kvm->arch.ept_identity_pagetable_done = true; | |
f51770ed | 4679 | |
b7ebfb05 | 4680 | out: |
40dcaa9f | 4681 | srcu_read_unlock(&kvm->srcu, idx); |
a255d479 TC |
4682 | |
4683 | out2: | |
4684 | mutex_unlock(&kvm->slots_lock); | |
f51770ed | 4685 | return r; |
b7ebfb05 SY |
4686 | } |
4687 | ||
6aa8b732 AK |
4688 | static void seg_setup(int seg) |
4689 | { | |
772e0318 | 4690 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
3a624e29 | 4691 | unsigned int ar; |
6aa8b732 AK |
4692 | |
4693 | vmcs_write16(sf->selector, 0); | |
4694 | vmcs_writel(sf->base, 0); | |
4695 | vmcs_write32(sf->limit, 0xffff); | |
d54d07b2 GN |
4696 | ar = 0x93; |
4697 | if (seg == VCPU_SREG_CS) | |
4698 | ar |= 0x08; /* code segment */ | |
3a624e29 NK |
4699 | |
4700 | vmcs_write32(sf->ar_bytes, ar); | |
6aa8b732 AK |
4701 | } |
4702 | ||
f78e0e2e SY |
4703 | static int alloc_apic_access_page(struct kvm *kvm) |
4704 | { | |
4484141a | 4705 | struct page *page; |
f78e0e2e SY |
4706 | int r = 0; |
4707 | ||
79fac95e | 4708 | mutex_lock(&kvm->slots_lock); |
c24ae0dc | 4709 | if (kvm->arch.apic_access_page_done) |
f78e0e2e | 4710 | goto out; |
1d8007bd PB |
4711 | r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, |
4712 | APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); | |
f78e0e2e SY |
4713 | if (r) |
4714 | goto out; | |
72dc67a6 | 4715 | |
73a6d941 | 4716 | page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
4484141a XG |
4717 | if (is_error_page(page)) { |
4718 | r = -EFAULT; | |
4719 | goto out; | |
4720 | } | |
4721 | ||
c24ae0dc TC |
4722 | /* |
4723 | * Do not pin the page in memory, so that memory hot-unplug | |
4724 | * is able to migrate it. | |
4725 | */ | |
4726 | put_page(page); | |
4727 | kvm->arch.apic_access_page_done = true; | |
f78e0e2e | 4728 | out: |
79fac95e | 4729 | mutex_unlock(&kvm->slots_lock); |
f78e0e2e SY |
4730 | return r; |
4731 | } | |
4732 | ||
b7ebfb05 SY |
4733 | static int alloc_identity_pagetable(struct kvm *kvm) |
4734 | { | |
a255d479 TC |
4735 | /* Called with kvm->slots_lock held. */ |
4736 | ||
b7ebfb05 SY |
4737 | int r = 0; |
4738 | ||
a255d479 TC |
4739 | BUG_ON(kvm->arch.ept_identity_pagetable_done); |
4740 | ||
1d8007bd PB |
4741 | r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, |
4742 | kvm->arch.ept_identity_map_addr, PAGE_SIZE); | |
b7ebfb05 | 4743 | |
b7ebfb05 SY |
4744 | return r; |
4745 | } | |
4746 | ||
991e7a0e | 4747 | static int allocate_vpid(void) |
2384d2b3 SY |
4748 | { |
4749 | int vpid; | |
4750 | ||
919818ab | 4751 | if (!enable_vpid) |
991e7a0e | 4752 | return 0; |
2384d2b3 SY |
4753 | spin_lock(&vmx_vpid_lock); |
4754 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
991e7a0e | 4755 | if (vpid < VMX_NR_VPIDS) |
2384d2b3 | 4756 | __set_bit(vpid, vmx_vpid_bitmap); |
991e7a0e WL |
4757 | else |
4758 | vpid = 0; | |
2384d2b3 | 4759 | spin_unlock(&vmx_vpid_lock); |
991e7a0e | 4760 | return vpid; |
2384d2b3 SY |
4761 | } |
4762 | ||
991e7a0e | 4763 | static void free_vpid(int vpid) |
cdbecfc3 | 4764 | { |
991e7a0e | 4765 | if (!enable_vpid || vpid == 0) |
cdbecfc3 LJ |
4766 | return; |
4767 | spin_lock(&vmx_vpid_lock); | |
991e7a0e | 4768 | __clear_bit(vpid, vmx_vpid_bitmap); |
cdbecfc3 LJ |
4769 | spin_unlock(&vmx_vpid_lock); |
4770 | } | |
4771 | ||
8d14695f YZ |
4772 | #define MSR_TYPE_R 1 |
4773 | #define MSR_TYPE_W 2 | |
4774 | static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, | |
4775 | u32 msr, int type) | |
25c5f225 | 4776 | { |
3e7c73e9 | 4777 | int f = sizeof(unsigned long); |
25c5f225 SY |
4778 | |
4779 | if (!cpu_has_vmx_msr_bitmap()) | |
4780 | return; | |
4781 | ||
4782 | /* | |
4783 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
4784 | * have the write-low and read-high bitmap offsets the wrong way round. | |
4785 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
4786 | */ | |
25c5f225 | 4787 | if (msr <= 0x1fff) { |
8d14695f YZ |
4788 | if (type & MSR_TYPE_R) |
4789 | /* read-low */ | |
4790 | __clear_bit(msr, msr_bitmap + 0x000 / f); | |
4791 | ||
4792 | if (type & MSR_TYPE_W) | |
4793 | /* write-low */ | |
4794 | __clear_bit(msr, msr_bitmap + 0x800 / f); | |
4795 | ||
25c5f225 SY |
4796 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { |
4797 | msr &= 0x1fff; | |
8d14695f YZ |
4798 | if (type & MSR_TYPE_R) |
4799 | /* read-high */ | |
4800 | __clear_bit(msr, msr_bitmap + 0x400 / f); | |
4801 | ||
4802 | if (type & MSR_TYPE_W) | |
4803 | /* write-high */ | |
4804 | __clear_bit(msr, msr_bitmap + 0xc00 / f); | |
4805 | ||
4806 | } | |
4807 | } | |
4808 | ||
f2b93280 WV |
4809 | /* |
4810 | * If a msr is allowed by L0, we should check whether it is allowed by L1. | |
4811 | * The corresponding bit will be cleared unless both of L0 and L1 allow it. | |
4812 | */ | |
4813 | static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1, | |
4814 | unsigned long *msr_bitmap_nested, | |
4815 | u32 msr, int type) | |
4816 | { | |
4817 | int f = sizeof(unsigned long); | |
4818 | ||
4819 | if (!cpu_has_vmx_msr_bitmap()) { | |
4820 | WARN_ON(1); | |
4821 | return; | |
4822 | } | |
4823 | ||
4824 | /* | |
4825 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
4826 | * have the write-low and read-high bitmap offsets the wrong way round. | |
4827 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
4828 | */ | |
4829 | if (msr <= 0x1fff) { | |
4830 | if (type & MSR_TYPE_R && | |
4831 | !test_bit(msr, msr_bitmap_l1 + 0x000 / f)) | |
4832 | /* read-low */ | |
4833 | __clear_bit(msr, msr_bitmap_nested + 0x000 / f); | |
4834 | ||
4835 | if (type & MSR_TYPE_W && | |
4836 | !test_bit(msr, msr_bitmap_l1 + 0x800 / f)) | |
4837 | /* write-low */ | |
4838 | __clear_bit(msr, msr_bitmap_nested + 0x800 / f); | |
4839 | ||
4840 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
4841 | msr &= 0x1fff; | |
4842 | if (type & MSR_TYPE_R && | |
4843 | !test_bit(msr, msr_bitmap_l1 + 0x400 / f)) | |
4844 | /* read-high */ | |
4845 | __clear_bit(msr, msr_bitmap_nested + 0x400 / f); | |
4846 | ||
4847 | if (type & MSR_TYPE_W && | |
4848 | !test_bit(msr, msr_bitmap_l1 + 0xc00 / f)) | |
4849 | /* write-high */ | |
4850 | __clear_bit(msr, msr_bitmap_nested + 0xc00 / f); | |
4851 | ||
4852 | } | |
4853 | } | |
4854 | ||
5897297b AK |
4855 | static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only) |
4856 | { | |
4857 | if (!longmode_only) | |
8d14695f YZ |
4858 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, |
4859 | msr, MSR_TYPE_R | MSR_TYPE_W); | |
4860 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, | |
4861 | msr, MSR_TYPE_R | MSR_TYPE_W); | |
4862 | } | |
4863 | ||
2e69f865 | 4864 | static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active) |
8d14695f | 4865 | { |
f6e90f9e | 4866 | if (apicv_active) { |
c63e4563 | 4867 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv, |
2e69f865 | 4868 | msr, type); |
c63e4563 | 4869 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv, |
2e69f865 | 4870 | msr, type); |
f6e90f9e | 4871 | } else { |
f6e90f9e | 4872 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic, |
2e69f865 | 4873 | msr, type); |
f6e90f9e | 4874 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic, |
2e69f865 | 4875 | msr, type); |
f6e90f9e | 4876 | } |
5897297b AK |
4877 | } |
4878 | ||
d62caabb | 4879 | static bool vmx_get_enable_apicv(void) |
d50ab6c1 | 4880 | { |
d62caabb | 4881 | return enable_apicv; |
d50ab6c1 PB |
4882 | } |
4883 | ||
6342c50a | 4884 | static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu) |
705699a1 WV |
4885 | { |
4886 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4887 | int max_irr; | |
4888 | void *vapic_page; | |
4889 | u16 status; | |
4890 | ||
4891 | if (vmx->nested.pi_desc && | |
4892 | vmx->nested.pi_pending) { | |
4893 | vmx->nested.pi_pending = false; | |
4894 | if (!pi_test_and_clear_on(vmx->nested.pi_desc)) | |
6342c50a | 4895 | return; |
705699a1 WV |
4896 | |
4897 | max_irr = find_last_bit( | |
4898 | (unsigned long *)vmx->nested.pi_desc->pir, 256); | |
4899 | ||
4900 | if (max_irr == 256) | |
6342c50a | 4901 | return; |
705699a1 WV |
4902 | |
4903 | vapic_page = kmap(vmx->nested.virtual_apic_page); | |
705699a1 WV |
4904 | __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page); |
4905 | kunmap(vmx->nested.virtual_apic_page); | |
4906 | ||
4907 | status = vmcs_read16(GUEST_INTR_STATUS); | |
4908 | if ((u8)max_irr > ((u8)status & 0xff)) { | |
4909 | status &= ~0xff; | |
4910 | status |= (u8)max_irr; | |
4911 | vmcs_write16(GUEST_INTR_STATUS, status); | |
4912 | } | |
4913 | } | |
705699a1 WV |
4914 | } |
4915 | ||
21bc8dc5 RK |
4916 | static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu) |
4917 | { | |
4918 | #ifdef CONFIG_SMP | |
4919 | if (vcpu->mode == IN_GUEST_MODE) { | |
28b835d6 FW |
4920 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4921 | ||
4922 | /* | |
4923 | * Currently, we don't support urgent interrupt, | |
4924 | * all interrupts are recognized as non-urgent | |
4925 | * interrupt, so we cannot post interrupts when | |
4926 | * 'SN' is set. | |
4927 | * | |
4928 | * If the vcpu is in guest mode, it means it is | |
4929 | * running instead of being scheduled out and | |
4930 | * waiting in the run queue, and that's the only | |
4931 | * case when 'SN' is set currently, warning if | |
4932 | * 'SN' is set. | |
4933 | */ | |
4934 | WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc)); | |
4935 | ||
21bc8dc5 RK |
4936 | apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), |
4937 | POSTED_INTR_VECTOR); | |
4938 | return true; | |
4939 | } | |
4940 | #endif | |
4941 | return false; | |
4942 | } | |
4943 | ||
705699a1 WV |
4944 | static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, |
4945 | int vector) | |
4946 | { | |
4947 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4948 | ||
4949 | if (is_guest_mode(vcpu) && | |
4950 | vector == vmx->nested.posted_intr_nv) { | |
4951 | /* the PIR and ON have been set by L1. */ | |
21bc8dc5 | 4952 | kvm_vcpu_trigger_posted_interrupt(vcpu); |
705699a1 WV |
4953 | /* |
4954 | * If a posted intr is not recognized by hardware, | |
4955 | * we will accomplish it in the next vmentry. | |
4956 | */ | |
4957 | vmx->nested.pi_pending = true; | |
4958 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
4959 | return 0; | |
4960 | } | |
4961 | return -1; | |
4962 | } | |
a20ed54d YZ |
4963 | /* |
4964 | * Send interrupt to vcpu via posted interrupt way. | |
4965 | * 1. If target vcpu is running(non-root mode), send posted interrupt | |
4966 | * notification to vcpu and hardware will sync PIR to vIRR atomically. | |
4967 | * 2. If target vcpu isn't running(root mode), kick it to pick up the | |
4968 | * interrupt from PIR in next vmentry. | |
4969 | */ | |
4970 | static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) | |
4971 | { | |
4972 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4973 | int r; | |
4974 | ||
705699a1 WV |
4975 | r = vmx_deliver_nested_posted_interrupt(vcpu, vector); |
4976 | if (!r) | |
4977 | return; | |
4978 | ||
a20ed54d YZ |
4979 | if (pi_test_and_set_pir(vector, &vmx->pi_desc)) |
4980 | return; | |
4981 | ||
b95234c8 PB |
4982 | /* If a previous notification has sent the IPI, nothing to do. */ |
4983 | if (pi_test_and_set_on(&vmx->pi_desc)) | |
4984 | return; | |
4985 | ||
4986 | if (!kvm_vcpu_trigger_posted_interrupt(vcpu)) | |
a20ed54d YZ |
4987 | kvm_vcpu_kick(vcpu); |
4988 | } | |
4989 | ||
a3a8ff8e NHE |
4990 | /* |
4991 | * Set up the vmcs's constant host-state fields, i.e., host-state fields that | |
4992 | * will not change in the lifetime of the guest. | |
4993 | * Note that host-state that does change is set elsewhere. E.g., host-state | |
4994 | * that is set differently for each CPU is set in vmx_vcpu_load(), not here. | |
4995 | */ | |
a547c6db | 4996 | static void vmx_set_constant_host_state(struct vcpu_vmx *vmx) |
a3a8ff8e NHE |
4997 | { |
4998 | u32 low32, high32; | |
4999 | unsigned long tmpl; | |
5000 | struct desc_ptr dt; | |
04ac88ab | 5001 | unsigned long cr0, cr4; |
a3a8ff8e | 5002 | |
04ac88ab AL |
5003 | cr0 = read_cr0(); |
5004 | WARN_ON(cr0 & X86_CR0_TS); | |
5005 | vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */ | |
a3a8ff8e NHE |
5006 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ |
5007 | ||
d974baa3 | 5008 | /* Save the most likely value for this task's CR4 in the VMCS. */ |
1e02ce4c | 5009 | cr4 = cr4_read_shadow(); |
d974baa3 AL |
5010 | vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ |
5011 | vmx->host_state.vmcs_host_cr4 = cr4; | |
5012 | ||
a3a8ff8e | 5013 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ |
b2da15ac AK |
5014 | #ifdef CONFIG_X86_64 |
5015 | /* | |
5016 | * Load null selectors, so we can avoid reloading them in | |
5017 | * __vmx_load_host_state(), in case userspace uses the null selectors | |
5018 | * too (the expected case). | |
5019 | */ | |
5020 | vmcs_write16(HOST_DS_SELECTOR, 0); | |
5021 | vmcs_write16(HOST_ES_SELECTOR, 0); | |
5022 | #else | |
a3a8ff8e NHE |
5023 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
5024 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
b2da15ac | 5025 | #endif |
a3a8ff8e NHE |
5026 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
5027 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
5028 | ||
5029 | native_store_idt(&dt); | |
5030 | vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */ | |
a547c6db | 5031 | vmx->host_idt_base = dt.address; |
a3a8ff8e | 5032 | |
83287ea4 | 5033 | vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */ |
a3a8ff8e NHE |
5034 | |
5035 | rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); | |
5036 | vmcs_write32(HOST_IA32_SYSENTER_CS, low32); | |
5037 | rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); | |
5038 | vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ | |
5039 | ||
5040 | if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { | |
5041 | rdmsr(MSR_IA32_CR_PAT, low32, high32); | |
5042 | vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); | |
5043 | } | |
5044 | } | |
5045 | ||
bf8179a0 NHE |
5046 | static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) |
5047 | { | |
5048 | vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; | |
5049 | if (enable_ept) | |
5050 | vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; | |
fe3ef05c NHE |
5051 | if (is_guest_mode(&vmx->vcpu)) |
5052 | vmx->vcpu.arch.cr4_guest_owned_bits &= | |
5053 | ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; | |
bf8179a0 NHE |
5054 | vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); |
5055 | } | |
5056 | ||
01e439be YZ |
5057 | static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) |
5058 | { | |
5059 | u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; | |
5060 | ||
d62caabb | 5061 | if (!kvm_vcpu_apicv_active(&vmx->vcpu)) |
01e439be | 5062 | pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; |
64672c95 YJ |
5063 | /* Enable the preemption timer dynamically */ |
5064 | pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
5065 | return pin_based_exec_ctrl; |
5066 | } | |
5067 | ||
d62caabb AS |
5068 | static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) |
5069 | { | |
5070 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5071 | ||
5072 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); | |
3ce424e4 RK |
5073 | if (cpu_has_secondary_exec_ctrls()) { |
5074 | if (kvm_vcpu_apicv_active(vcpu)) | |
5075 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
5076 | SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
5077 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
5078 | else | |
5079 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, | |
5080 | SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
5081 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
5082 | } | |
5083 | ||
5084 | if (cpu_has_vmx_msr_bitmap()) | |
5085 | vmx_set_msr_bitmap(vcpu); | |
d62caabb AS |
5086 | } |
5087 | ||
bf8179a0 NHE |
5088 | static u32 vmx_exec_control(struct vcpu_vmx *vmx) |
5089 | { | |
5090 | u32 exec_control = vmcs_config.cpu_based_exec_ctrl; | |
d16c293e PB |
5091 | |
5092 | if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) | |
5093 | exec_control &= ~CPU_BASED_MOV_DR_EXITING; | |
5094 | ||
35754c98 | 5095 | if (!cpu_need_tpr_shadow(&vmx->vcpu)) { |
bf8179a0 NHE |
5096 | exec_control &= ~CPU_BASED_TPR_SHADOW; |
5097 | #ifdef CONFIG_X86_64 | |
5098 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
5099 | CPU_BASED_CR8_LOAD_EXITING; | |
5100 | #endif | |
5101 | } | |
5102 | if (!enable_ept) | |
5103 | exec_control |= CPU_BASED_CR3_STORE_EXITING | | |
5104 | CPU_BASED_CR3_LOAD_EXITING | | |
5105 | CPU_BASED_INVLPG_EXITING; | |
5106 | return exec_control; | |
5107 | } | |
5108 | ||
5109 | static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx) | |
5110 | { | |
5111 | u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; | |
35754c98 | 5112 | if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu)) |
bf8179a0 NHE |
5113 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; |
5114 | if (vmx->vpid == 0) | |
5115 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
5116 | if (!enable_ept) { | |
5117 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; | |
5118 | enable_unrestricted_guest = 0; | |
ad756a16 MJ |
5119 | /* Enable INVPCID for non-ept guests may cause performance regression. */ |
5120 | exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; | |
bf8179a0 NHE |
5121 | } |
5122 | if (!enable_unrestricted_guest) | |
5123 | exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
5124 | if (!ple_gap) | |
5125 | exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
d62caabb | 5126 | if (!kvm_vcpu_apicv_active(&vmx->vcpu)) |
c7c9c56c YZ |
5127 | exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | |
5128 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
8d14695f | 5129 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; |
abc4fc58 AG |
5130 | /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD |
5131 | (handle_vmptrld). | |
5132 | We can NOT enable shadow_vmcs here because we don't have yet | |
5133 | a current VMCS12 | |
5134 | */ | |
5135 | exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; | |
a3eaa864 KH |
5136 | |
5137 | if (!enable_pml) | |
5138 | exec_control &= ~SECONDARY_EXEC_ENABLE_PML; | |
843e4330 | 5139 | |
bf8179a0 NHE |
5140 | return exec_control; |
5141 | } | |
5142 | ||
ce88decf XG |
5143 | static void ept_set_mmio_spte_mask(void) |
5144 | { | |
5145 | /* | |
5146 | * EPT Misconfigurations can be generated if the value of bits 2:0 | |
5147 | * of an EPT paging-structure entry is 110b (write/execute). | |
ce88decf | 5148 | */ |
312b616b | 5149 | kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE); |
ce88decf XG |
5150 | } |
5151 | ||
f53cd63c | 5152 | #define VMX_XSS_EXIT_BITMAP 0 |
6aa8b732 AK |
5153 | /* |
5154 | * Sets up the vmcs for emulated real mode. | |
5155 | */ | |
8b9cf98c | 5156 | static int vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 | 5157 | { |
2e4ce7f5 | 5158 | #ifdef CONFIG_X86_64 |
6aa8b732 | 5159 | unsigned long a; |
2e4ce7f5 | 5160 | #endif |
6aa8b732 | 5161 | int i; |
6aa8b732 | 5162 | |
6aa8b732 | 5163 | /* I/O */ |
3e7c73e9 AK |
5164 | vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a)); |
5165 | vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b)); | |
6aa8b732 | 5166 | |
4607c2d7 AG |
5167 | if (enable_shadow_vmcs) { |
5168 | vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap)); | |
5169 | vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap)); | |
5170 | } | |
25c5f225 | 5171 | if (cpu_has_vmx_msr_bitmap()) |
5897297b | 5172 | vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy)); |
25c5f225 | 5173 | |
6aa8b732 AK |
5174 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
5175 | ||
6aa8b732 | 5176 | /* Control */ |
01e439be | 5177 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); |
64672c95 | 5178 | vmx->hv_deadline_tsc = -1; |
6e5d865c | 5179 | |
bf8179a0 | 5180 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx)); |
6aa8b732 | 5181 | |
dfa169bb | 5182 | if (cpu_has_secondary_exec_ctrls()) { |
bf8179a0 NHE |
5183 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, |
5184 | vmx_secondary_exec_control(vmx)); | |
dfa169bb | 5185 | } |
f78e0e2e | 5186 | |
d62caabb | 5187 | if (kvm_vcpu_apicv_active(&vmx->vcpu)) { |
c7c9c56c YZ |
5188 | vmcs_write64(EOI_EXIT_BITMAP0, 0); |
5189 | vmcs_write64(EOI_EXIT_BITMAP1, 0); | |
5190 | vmcs_write64(EOI_EXIT_BITMAP2, 0); | |
5191 | vmcs_write64(EOI_EXIT_BITMAP3, 0); | |
5192 | ||
5193 | vmcs_write16(GUEST_INTR_STATUS, 0); | |
01e439be | 5194 | |
0bcf261c | 5195 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); |
01e439be | 5196 | vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); |
c7c9c56c YZ |
5197 | } |
5198 | ||
4b8d54f9 ZE |
5199 | if (ple_gap) { |
5200 | vmcs_write32(PLE_GAP, ple_gap); | |
a7653ecd RK |
5201 | vmx->ple_window = ple_window; |
5202 | vmx->ple_window_dirty = true; | |
4b8d54f9 ZE |
5203 | } |
5204 | ||
c3707958 XG |
5205 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); |
5206 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); | |
6aa8b732 AK |
5207 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
5208 | ||
9581d442 AK |
5209 | vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ |
5210 | vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ | |
a547c6db | 5211 | vmx_set_constant_host_state(vmx); |
05b3e0c2 | 5212 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
5213 | rdmsrl(MSR_FS_BASE, a); |
5214 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
5215 | rdmsrl(MSR_GS_BASE, a); | |
5216 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
5217 | #else | |
5218 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
5219 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
5220 | #endif | |
5221 | ||
2cc51560 ED |
5222 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
5223 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
61d2ef2c | 5224 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host)); |
2cc51560 | 5225 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); |
61d2ef2c | 5226 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); |
6aa8b732 | 5227 | |
74545705 RK |
5228 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) |
5229 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); | |
468d472f | 5230 | |
03916db9 | 5231 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { |
6aa8b732 AK |
5232 | u32 index = vmx_msr_index[i]; |
5233 | u32 data_low, data_high; | |
a2fa3e9f | 5234 | int j = vmx->nmsrs; |
6aa8b732 AK |
5235 | |
5236 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
5237 | continue; | |
432bd6cb AK |
5238 | if (wrmsr_safe(index, data_low, data_high) < 0) |
5239 | continue; | |
26bb0981 AK |
5240 | vmx->guest_msrs[j].index = i; |
5241 | vmx->guest_msrs[j].data = 0; | |
d5696725 | 5242 | vmx->guest_msrs[j].mask = -1ull; |
a2fa3e9f | 5243 | ++vmx->nmsrs; |
6aa8b732 | 5244 | } |
6aa8b732 | 5245 | |
2961e876 GN |
5246 | |
5247 | vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl); | |
6aa8b732 AK |
5248 | |
5249 | /* 22.2.1, 20.8.1 */ | |
2961e876 | 5250 | vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl); |
1c3d14fe | 5251 | |
bd7e5b08 PB |
5252 | vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS; |
5253 | vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS); | |
5254 | ||
bf8179a0 | 5255 | set_cr4_guest_host_mask(vmx); |
e00c8cf2 | 5256 | |
f53cd63c WL |
5257 | if (vmx_xsaves_supported()) |
5258 | vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); | |
5259 | ||
4e59516a PF |
5260 | if (enable_pml) { |
5261 | ASSERT(vmx->pml_pg); | |
5262 | vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); | |
5263 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
5264 | } | |
5265 | ||
e00c8cf2 AK |
5266 | return 0; |
5267 | } | |
5268 | ||
d28bc9dd | 5269 | static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e00c8cf2 AK |
5270 | { |
5271 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
58cb628d | 5272 | struct msr_data apic_base_msr; |
d28bc9dd | 5273 | u64 cr0; |
e00c8cf2 | 5274 | |
7ffd92c5 | 5275 | vmx->rmode.vm86_active = 0; |
e00c8cf2 | 5276 | |
ad312c7c | 5277 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
d28bc9dd NA |
5278 | kvm_set_cr8(vcpu, 0); |
5279 | ||
5280 | if (!init_event) { | |
5281 | apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | | |
5282 | MSR_IA32_APICBASE_ENABLE; | |
5283 | if (kvm_vcpu_is_reset_bsp(vcpu)) | |
5284 | apic_base_msr.data |= MSR_IA32_APICBASE_BSP; | |
5285 | apic_base_msr.host_initiated = true; | |
5286 | kvm_set_apic_base(vcpu, &apic_base_msr); | |
5287 | } | |
e00c8cf2 | 5288 | |
2fb92db1 AK |
5289 | vmx_segment_cache_clear(vmx); |
5290 | ||
5706be0d | 5291 | seg_setup(VCPU_SREG_CS); |
66450a21 | 5292 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); |
f3531054 | 5293 | vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); |
e00c8cf2 AK |
5294 | |
5295 | seg_setup(VCPU_SREG_DS); | |
5296 | seg_setup(VCPU_SREG_ES); | |
5297 | seg_setup(VCPU_SREG_FS); | |
5298 | seg_setup(VCPU_SREG_GS); | |
5299 | seg_setup(VCPU_SREG_SS); | |
5300 | ||
5301 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
5302 | vmcs_writel(GUEST_TR_BASE, 0); | |
5303 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
5304 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
5305 | ||
5306 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
5307 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
5308 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
5309 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
5310 | ||
d28bc9dd NA |
5311 | if (!init_event) { |
5312 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
5313 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
5314 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
5315 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
5316 | } | |
e00c8cf2 AK |
5317 | |
5318 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
66450a21 | 5319 | kvm_rip_write(vcpu, 0xfff0); |
e00c8cf2 | 5320 | |
e00c8cf2 AK |
5321 | vmcs_writel(GUEST_GDTR_BASE, 0); |
5322 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
5323 | ||
5324 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
5325 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
5326 | ||
443381a8 | 5327 | vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); |
e00c8cf2 | 5328 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); |
f3531054 | 5329 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); |
e00c8cf2 | 5330 | |
e00c8cf2 AK |
5331 | setup_msrs(vmx); |
5332 | ||
6aa8b732 AK |
5333 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
5334 | ||
d28bc9dd | 5335 | if (cpu_has_vmx_tpr_shadow() && !init_event) { |
f78e0e2e | 5336 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); |
35754c98 | 5337 | if (cpu_need_tpr_shadow(vcpu)) |
f78e0e2e | 5338 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, |
d28bc9dd | 5339 | __pa(vcpu->arch.apic->regs)); |
f78e0e2e SY |
5340 | vmcs_write32(TPR_THRESHOLD, 0); |
5341 | } | |
5342 | ||
a73896cb | 5343 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
6aa8b732 | 5344 | |
d62caabb | 5345 | if (kvm_vcpu_apicv_active(vcpu)) |
01e439be YZ |
5346 | memset(&vmx->pi_desc, 0, sizeof(struct pi_desc)); |
5347 | ||
2384d2b3 SY |
5348 | if (vmx->vpid != 0) |
5349 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
5350 | ||
d28bc9dd | 5351 | cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; |
d28bc9dd | 5352 | vmx->vcpu.arch.cr0 = cr0; |
f2463247 | 5353 | vmx_set_cr0(vcpu, cr0); /* enter rmode */ |
d28bc9dd | 5354 | vmx_set_cr4(vcpu, 0); |
5690891b | 5355 | vmx_set_efer(vcpu, 0); |
bd7e5b08 | 5356 | |
d28bc9dd | 5357 | update_exception_bitmap(vcpu); |
6aa8b732 | 5358 | |
dd5f5341 | 5359 | vpid_sync_context(vmx->vpid); |
6aa8b732 AK |
5360 | } |
5361 | ||
b6f1250e NHE |
5362 | /* |
5363 | * In nested virtualization, check if L1 asked to exit on external interrupts. | |
5364 | * For most existing hypervisors, this will always return true. | |
5365 | */ | |
5366 | static bool nested_exit_on_intr(struct kvm_vcpu *vcpu) | |
5367 | { | |
5368 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
5369 | PIN_BASED_EXT_INTR_MASK; | |
5370 | } | |
5371 | ||
77b0f5d6 BD |
5372 | /* |
5373 | * In nested virtualization, check if L1 has set | |
5374 | * VM_EXIT_ACK_INTR_ON_EXIT | |
5375 | */ | |
5376 | static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu) | |
5377 | { | |
5378 | return get_vmcs12(vcpu)->vm_exit_controls & | |
5379 | VM_EXIT_ACK_INTR_ON_EXIT; | |
5380 | } | |
5381 | ||
ea8ceb83 JK |
5382 | static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu) |
5383 | { | |
5384 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
5385 | PIN_BASED_NMI_EXITING; | |
5386 | } | |
5387 | ||
c9a7953f | 5388 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
3b86cd99 | 5389 | { |
47c0152e PB |
5390 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, |
5391 | CPU_BASED_VIRTUAL_INTR_PENDING); | |
3b86cd99 JK |
5392 | } |
5393 | ||
c9a7953f | 5394 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
3b86cd99 | 5395 | { |
2c82878b | 5396 | if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { |
c9a7953f JK |
5397 | enable_irq_window(vcpu); |
5398 | return; | |
5399 | } | |
3b86cd99 | 5400 | |
47c0152e PB |
5401 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, |
5402 | CPU_BASED_VIRTUAL_NMI_PENDING); | |
3b86cd99 JK |
5403 | } |
5404 | ||
66fd3f7f | 5405 | static void vmx_inject_irq(struct kvm_vcpu *vcpu) |
85f455f7 | 5406 | { |
9c8cba37 | 5407 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
66fd3f7f GN |
5408 | uint32_t intr; |
5409 | int irq = vcpu->arch.interrupt.nr; | |
9c8cba37 | 5410 | |
229456fc | 5411 | trace_kvm_inj_virq(irq); |
2714d1d3 | 5412 | |
fa89a817 | 5413 | ++vcpu->stat.irq_injections; |
7ffd92c5 | 5414 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
5415 | int inc_eip = 0; |
5416 | if (vcpu->arch.interrupt.soft) | |
5417 | inc_eip = vcpu->arch.event_exit_inst_len; | |
5418 | if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE) | |
a92601bb | 5419 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
85f455f7 ED |
5420 | return; |
5421 | } | |
66fd3f7f GN |
5422 | intr = irq | INTR_INFO_VALID_MASK; |
5423 | if (vcpu->arch.interrupt.soft) { | |
5424 | intr |= INTR_TYPE_SOFT_INTR; | |
5425 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
5426 | vmx->vcpu.arch.event_exit_inst_len); | |
5427 | } else | |
5428 | intr |= INTR_TYPE_EXT_INTR; | |
5429 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); | |
85f455f7 ED |
5430 | } |
5431 | ||
f08864b4 SY |
5432 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
5433 | { | |
66a5a347 JK |
5434 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
5435 | ||
c5a6d5f7 | 5436 | if (!is_guest_mode(vcpu)) { |
c5a6d5f7 WL |
5437 | ++vcpu->stat.nmi_injections; |
5438 | vmx->nmi_known_unmasked = false; | |
3b86cd99 JK |
5439 | } |
5440 | ||
7ffd92c5 | 5441 | if (vmx->rmode.vm86_active) { |
71f9833b | 5442 | if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE) |
a92601bb | 5443 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
66a5a347 JK |
5444 | return; |
5445 | } | |
c5a6d5f7 | 5446 | |
f08864b4 SY |
5447 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
5448 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
f08864b4 SY |
5449 | } |
5450 | ||
3cfc3092 JK |
5451 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) |
5452 | { | |
9d58b931 AK |
5453 | if (to_vmx(vcpu)->nmi_known_unmasked) |
5454 | return false; | |
c332c83a | 5455 | return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; |
3cfc3092 JK |
5456 | } |
5457 | ||
5458 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
5459 | { | |
5460 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5461 | ||
2c82878b PB |
5462 | vmx->nmi_known_unmasked = !masked; |
5463 | if (masked) | |
5464 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
5465 | GUEST_INTR_STATE_NMI); | |
5466 | else | |
5467 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
5468 | GUEST_INTR_STATE_NMI); | |
3cfc3092 JK |
5469 | } |
5470 | ||
2505dc9f JK |
5471 | static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) |
5472 | { | |
b6b8a145 JK |
5473 | if (to_vmx(vcpu)->nested.nested_run_pending) |
5474 | return 0; | |
ea8ceb83 | 5475 | |
2505dc9f JK |
5476 | return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
5477 | (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI | |
5478 | | GUEST_INTR_STATE_NMI)); | |
5479 | } | |
5480 | ||
78646121 GN |
5481 | static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) |
5482 | { | |
b6b8a145 JK |
5483 | return (!to_vmx(vcpu)->nested.nested_run_pending && |
5484 | vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
c4282df9 GN |
5485 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
5486 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); | |
78646121 GN |
5487 | } |
5488 | ||
cbc94022 IE |
5489 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
5490 | { | |
5491 | int ret; | |
cbc94022 | 5492 | |
1d8007bd PB |
5493 | ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, |
5494 | PAGE_SIZE * 3); | |
cbc94022 IE |
5495 | if (ret) |
5496 | return ret; | |
bfc6d222 | 5497 | kvm->arch.tss_addr = addr; |
1f755a82 | 5498 | return init_rmode_tss(kvm); |
cbc94022 IE |
5499 | } |
5500 | ||
0ca1b4f4 | 5501 | static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) |
6aa8b732 | 5502 | { |
77ab6db0 | 5503 | switch (vec) { |
77ab6db0 | 5504 | case BP_VECTOR: |
c573cd22 JK |
5505 | /* |
5506 | * Update instruction length as we may reinject the exception | |
5507 | * from user space while in guest debugging mode. | |
5508 | */ | |
5509 | to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = | |
5510 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
d0bfb940 | 5511 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
0ca1b4f4 GN |
5512 | return false; |
5513 | /* fall through */ | |
5514 | case DB_VECTOR: | |
5515 | if (vcpu->guest_debug & | |
5516 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
5517 | return false; | |
d0bfb940 JK |
5518 | /* fall through */ |
5519 | case DE_VECTOR: | |
77ab6db0 JK |
5520 | case OF_VECTOR: |
5521 | case BR_VECTOR: | |
5522 | case UD_VECTOR: | |
5523 | case DF_VECTOR: | |
5524 | case SS_VECTOR: | |
5525 | case GP_VECTOR: | |
5526 | case MF_VECTOR: | |
0ca1b4f4 GN |
5527 | return true; |
5528 | break; | |
77ab6db0 | 5529 | } |
0ca1b4f4 GN |
5530 | return false; |
5531 | } | |
5532 | ||
5533 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
5534 | int vec, u32 err_code) | |
5535 | { | |
5536 | /* | |
5537 | * Instruction with address size override prefix opcode 0x67 | |
5538 | * Cause the #SS fault with 0 error code in VM86 mode. | |
5539 | */ | |
5540 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { | |
5541 | if (emulate_instruction(vcpu, 0) == EMULATE_DONE) { | |
5542 | if (vcpu->arch.halt_request) { | |
5543 | vcpu->arch.halt_request = 0; | |
5cb56059 | 5544 | return kvm_vcpu_halt(vcpu); |
0ca1b4f4 GN |
5545 | } |
5546 | return 1; | |
5547 | } | |
5548 | return 0; | |
5549 | } | |
5550 | ||
5551 | /* | |
5552 | * Forward all other exceptions that are valid in real mode. | |
5553 | * FIXME: Breaks guest debugging in real mode, needs to be fixed with | |
5554 | * the required debugging infrastructure rework. | |
5555 | */ | |
5556 | kvm_queue_exception(vcpu, vec); | |
5557 | return 1; | |
6aa8b732 AK |
5558 | } |
5559 | ||
a0861c02 AK |
5560 | /* |
5561 | * Trigger machine check on the host. We assume all the MSRs are already set up | |
5562 | * by the CPU and that we still run on the same CPU as the MCE occurred on. | |
5563 | * We pass a fake environment to the machine check handler because we want | |
5564 | * the guest to be always treated like user space, no matter what context | |
5565 | * it used internally. | |
5566 | */ | |
5567 | static void kvm_machine_check(void) | |
5568 | { | |
5569 | #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) | |
5570 | struct pt_regs regs = { | |
5571 | .cs = 3, /* Fake ring 3 no matter what the guest ran on */ | |
5572 | .flags = X86_EFLAGS_IF, | |
5573 | }; | |
5574 | ||
5575 | do_machine_check(®s, 0); | |
5576 | #endif | |
5577 | } | |
5578 | ||
851ba692 | 5579 | static int handle_machine_check(struct kvm_vcpu *vcpu) |
a0861c02 AK |
5580 | { |
5581 | /* already handled by vcpu_run */ | |
5582 | return 1; | |
5583 | } | |
5584 | ||
851ba692 | 5585 | static int handle_exception(struct kvm_vcpu *vcpu) |
6aa8b732 | 5586 | { |
1155f76a | 5587 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
851ba692 | 5588 | struct kvm_run *kvm_run = vcpu->run; |
d0bfb940 | 5589 | u32 intr_info, ex_no, error_code; |
42dbaa5a | 5590 | unsigned long cr2, rip, dr6; |
6aa8b732 AK |
5591 | u32 vect_info; |
5592 | enum emulation_result er; | |
5593 | ||
1155f76a | 5594 | vect_info = vmx->idt_vectoring_info; |
88786475 | 5595 | intr_info = vmx->exit_intr_info; |
6aa8b732 | 5596 | |
a0861c02 | 5597 | if (is_machine_check(intr_info)) |
851ba692 | 5598 | return handle_machine_check(vcpu); |
a0861c02 | 5599 | |
ef85b673 | 5600 | if (is_nmi(intr_info)) |
1b6269db | 5601 | return 1; /* already handled by vmx_vcpu_run() */ |
2ab455cc | 5602 | |
7aa81cc0 | 5603 | if (is_invalid_opcode(intr_info)) { |
ae1f5767 JK |
5604 | if (is_guest_mode(vcpu)) { |
5605 | kvm_queue_exception(vcpu, UD_VECTOR); | |
5606 | return 1; | |
5607 | } | |
51d8b661 | 5608 | er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 5609 | if (er != EMULATE_DONE) |
7ee5d940 | 5610 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
5611 | return 1; |
5612 | } | |
5613 | ||
6aa8b732 | 5614 | error_code = 0; |
2e11384c | 5615 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 | 5616 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
bf4ca23e XG |
5617 | |
5618 | /* | |
5619 | * The #PF with PFEC.RSVD = 1 indicates the guest is accessing | |
5620 | * MMIO, it is better to report an internal error. | |
5621 | * See the comments in vmx_handle_exit. | |
5622 | */ | |
5623 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
5624 | !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { | |
5625 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
5626 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; | |
80f0e95d | 5627 | vcpu->run->internal.ndata = 3; |
bf4ca23e XG |
5628 | vcpu->run->internal.data[0] = vect_info; |
5629 | vcpu->run->internal.data[1] = intr_info; | |
80f0e95d | 5630 | vcpu->run->internal.data[2] = error_code; |
bf4ca23e XG |
5631 | return 0; |
5632 | } | |
5633 | ||
6aa8b732 | 5634 | if (is_page_fault(intr_info)) { |
1439442c | 5635 | /* EPT won't cause page fault directly */ |
cf3ace79 | 5636 | BUG_ON(enable_ept); |
6aa8b732 | 5637 | cr2 = vmcs_readl(EXIT_QUALIFICATION); |
229456fc MT |
5638 | trace_kvm_page_fault(cr2, error_code); |
5639 | ||
3298b75c | 5640 | if (kvm_event_needs_reinjection(vcpu)) |
577bdc49 | 5641 | kvm_mmu_unprotect_page_virt(vcpu, cr2); |
dc25e89e | 5642 | return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0); |
6aa8b732 AK |
5643 | } |
5644 | ||
d0bfb940 | 5645 | ex_no = intr_info & INTR_INFO_VECTOR_MASK; |
0ca1b4f4 GN |
5646 | |
5647 | if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) | |
5648 | return handle_rmode_exception(vcpu, ex_no, error_code); | |
5649 | ||
42dbaa5a | 5650 | switch (ex_no) { |
54a20552 EN |
5651 | case AC_VECTOR: |
5652 | kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); | |
5653 | return 1; | |
42dbaa5a JK |
5654 | case DB_VECTOR: |
5655 | dr6 = vmcs_readl(EXIT_QUALIFICATION); | |
5656 | if (!(vcpu->guest_debug & | |
5657 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { | |
8246bf52 | 5658 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 5659 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
fd2a445a HD |
5660 | if (!(dr6 & ~DR6_RESERVED)) /* icebp */ |
5661 | skip_emulated_instruction(vcpu); | |
5662 | ||
42dbaa5a JK |
5663 | kvm_queue_exception(vcpu, DB_VECTOR); |
5664 | return 1; | |
5665 | } | |
5666 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; | |
5667 | kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); | |
5668 | /* fall through */ | |
5669 | case BP_VECTOR: | |
c573cd22 JK |
5670 | /* |
5671 | * Update instruction length as we may reinject #BP from | |
5672 | * user space while in guest debugging mode. Reading it for | |
5673 | * #DB as well causes no harm, it is not used in that case. | |
5674 | */ | |
5675 | vmx->vcpu.arch.event_exit_inst_len = | |
5676 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
6aa8b732 | 5677 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
0a434bb2 | 5678 | rip = kvm_rip_read(vcpu); |
d0bfb940 JK |
5679 | kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; |
5680 | kvm_run->debug.arch.exception = ex_no; | |
42dbaa5a JK |
5681 | break; |
5682 | default: | |
d0bfb940 JK |
5683 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; |
5684 | kvm_run->ex.exception = ex_no; | |
5685 | kvm_run->ex.error_code = error_code; | |
42dbaa5a | 5686 | break; |
6aa8b732 | 5687 | } |
6aa8b732 AK |
5688 | return 0; |
5689 | } | |
5690 | ||
851ba692 | 5691 | static int handle_external_interrupt(struct kvm_vcpu *vcpu) |
6aa8b732 | 5692 | { |
1165f5fe | 5693 | ++vcpu->stat.irq_exits; |
6aa8b732 AK |
5694 | return 1; |
5695 | } | |
5696 | ||
851ba692 | 5697 | static int handle_triple_fault(struct kvm_vcpu *vcpu) |
988ad74f | 5698 | { |
851ba692 | 5699 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
988ad74f AK |
5700 | return 0; |
5701 | } | |
6aa8b732 | 5702 | |
851ba692 | 5703 | static int handle_io(struct kvm_vcpu *vcpu) |
6aa8b732 | 5704 | { |
bfdaab09 | 5705 | unsigned long exit_qualification; |
6affcbed | 5706 | int size, in, string, ret; |
039576c0 | 5707 | unsigned port; |
6aa8b732 | 5708 | |
bfdaab09 | 5709 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 5710 | string = (exit_qualification & 16) != 0; |
cf8f70bf | 5711 | in = (exit_qualification & 8) != 0; |
e70669ab | 5712 | |
cf8f70bf | 5713 | ++vcpu->stat.io_exits; |
e70669ab | 5714 | |
cf8f70bf | 5715 | if (string || in) |
51d8b661 | 5716 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
e70669ab | 5717 | |
cf8f70bf GN |
5718 | port = exit_qualification >> 16; |
5719 | size = (exit_qualification & 7) + 1; | |
cf8f70bf | 5720 | |
6affcbed KH |
5721 | ret = kvm_skip_emulated_instruction(vcpu); |
5722 | ||
5723 | /* | |
5724 | * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered | |
5725 | * KVM_EXIT_DEBUG here. | |
5726 | */ | |
5727 | return kvm_fast_pio_out(vcpu, size, port) && ret; | |
6aa8b732 AK |
5728 | } |
5729 | ||
102d8325 IM |
5730 | static void |
5731 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
5732 | { | |
5733 | /* | |
5734 | * Patch in the VMCALL instruction: | |
5735 | */ | |
5736 | hypercall[0] = 0x0f; | |
5737 | hypercall[1] = 0x01; | |
5738 | hypercall[2] = 0xc1; | |
102d8325 IM |
5739 | } |
5740 | ||
0fa06071 | 5741 | /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ |
eeadf9e7 NHE |
5742 | static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) |
5743 | { | |
eeadf9e7 | 5744 | if (is_guest_mode(vcpu)) { |
1a0d74e6 JK |
5745 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
5746 | unsigned long orig_val = val; | |
5747 | ||
eeadf9e7 NHE |
5748 | /* |
5749 | * We get here when L2 changed cr0 in a way that did not change | |
5750 | * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), | |
1a0d74e6 JK |
5751 | * but did change L0 shadowed bits. So we first calculate the |
5752 | * effective cr0 value that L1 would like to write into the | |
5753 | * hardware. It consists of the L2-owned bits from the new | |
5754 | * value combined with the L1-owned bits from L1's guest_cr0. | |
eeadf9e7 | 5755 | */ |
1a0d74e6 JK |
5756 | val = (val & ~vmcs12->cr0_guest_host_mask) | |
5757 | (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); | |
5758 | ||
3899152c | 5759 | if (!nested_guest_cr0_valid(vcpu, val)) |
eeadf9e7 | 5760 | return 1; |
1a0d74e6 JK |
5761 | |
5762 | if (kvm_set_cr0(vcpu, val)) | |
5763 | return 1; | |
5764 | vmcs_writel(CR0_READ_SHADOW, orig_val); | |
eeadf9e7 | 5765 | return 0; |
1a0d74e6 JK |
5766 | } else { |
5767 | if (to_vmx(vcpu)->nested.vmxon && | |
3899152c | 5768 | !nested_host_cr0_valid(vcpu, val)) |
1a0d74e6 | 5769 | return 1; |
3899152c | 5770 | |
eeadf9e7 | 5771 | return kvm_set_cr0(vcpu, val); |
1a0d74e6 | 5772 | } |
eeadf9e7 NHE |
5773 | } |
5774 | ||
5775 | static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) | |
5776 | { | |
5777 | if (is_guest_mode(vcpu)) { | |
1a0d74e6 JK |
5778 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
5779 | unsigned long orig_val = val; | |
5780 | ||
5781 | /* analogously to handle_set_cr0 */ | |
5782 | val = (val & ~vmcs12->cr4_guest_host_mask) | | |
5783 | (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); | |
5784 | if (kvm_set_cr4(vcpu, val)) | |
eeadf9e7 | 5785 | return 1; |
1a0d74e6 | 5786 | vmcs_writel(CR4_READ_SHADOW, orig_val); |
eeadf9e7 NHE |
5787 | return 0; |
5788 | } else | |
5789 | return kvm_set_cr4(vcpu, val); | |
5790 | } | |
5791 | ||
851ba692 | 5792 | static int handle_cr(struct kvm_vcpu *vcpu) |
6aa8b732 | 5793 | { |
229456fc | 5794 | unsigned long exit_qualification, val; |
6aa8b732 AK |
5795 | int cr; |
5796 | int reg; | |
49a9b07e | 5797 | int err; |
6affcbed | 5798 | int ret; |
6aa8b732 | 5799 | |
bfdaab09 | 5800 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
5801 | cr = exit_qualification & 15; |
5802 | reg = (exit_qualification >> 8) & 15; | |
5803 | switch ((exit_qualification >> 4) & 3) { | |
5804 | case 0: /* mov to cr */ | |
1e32c079 | 5805 | val = kvm_register_readl(vcpu, reg); |
229456fc | 5806 | trace_kvm_cr_write(cr, val); |
6aa8b732 AK |
5807 | switch (cr) { |
5808 | case 0: | |
eeadf9e7 | 5809 | err = handle_set_cr0(vcpu, val); |
6affcbed | 5810 | return kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 5811 | case 3: |
2390218b | 5812 | err = kvm_set_cr3(vcpu, val); |
6affcbed | 5813 | return kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 5814 | case 4: |
eeadf9e7 | 5815 | err = handle_set_cr4(vcpu, val); |
6affcbed | 5816 | return kvm_complete_insn_gp(vcpu, err); |
0a5fff19 GN |
5817 | case 8: { |
5818 | u8 cr8_prev = kvm_get_cr8(vcpu); | |
1e32c079 | 5819 | u8 cr8 = (u8)val; |
eea1cff9 | 5820 | err = kvm_set_cr8(vcpu, cr8); |
6affcbed | 5821 | ret = kvm_complete_insn_gp(vcpu, err); |
35754c98 | 5822 | if (lapic_in_kernel(vcpu)) |
6affcbed | 5823 | return ret; |
0a5fff19 | 5824 | if (cr8_prev <= cr8) |
6affcbed KH |
5825 | return ret; |
5826 | /* | |
5827 | * TODO: we might be squashing a | |
5828 | * KVM_GUESTDBG_SINGLESTEP-triggered | |
5829 | * KVM_EXIT_DEBUG here. | |
5830 | */ | |
851ba692 | 5831 | vcpu->run->exit_reason = KVM_EXIT_SET_TPR; |
0a5fff19 GN |
5832 | return 0; |
5833 | } | |
4b8073e4 | 5834 | } |
6aa8b732 | 5835 | break; |
25c4c276 | 5836 | case 2: /* clts */ |
bd7e5b08 PB |
5837 | WARN_ONCE(1, "Guest should always own CR0.TS"); |
5838 | vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); | |
4d4ec087 | 5839 | trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); |
6affcbed | 5840 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
5841 | case 1: /*mov from cr*/ |
5842 | switch (cr) { | |
5843 | case 3: | |
9f8fe504 AK |
5844 | val = kvm_read_cr3(vcpu); |
5845 | kvm_register_write(vcpu, reg, val); | |
5846 | trace_kvm_cr_read(cr, val); | |
6affcbed | 5847 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 | 5848 | case 8: |
229456fc MT |
5849 | val = kvm_get_cr8(vcpu); |
5850 | kvm_register_write(vcpu, reg, val); | |
5851 | trace_kvm_cr_read(cr, val); | |
6affcbed | 5852 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
5853 | } |
5854 | break; | |
5855 | case 3: /* lmsw */ | |
a1f83a74 | 5856 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
4d4ec087 | 5857 | trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); |
a1f83a74 | 5858 | kvm_lmsw(vcpu, val); |
6aa8b732 | 5859 | |
6affcbed | 5860 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
5861 | default: |
5862 | break; | |
5863 | } | |
851ba692 | 5864 | vcpu->run->exit_reason = 0; |
a737f256 | 5865 | vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
5866 | (int)(exit_qualification >> 4) & 3, cr); |
5867 | return 0; | |
5868 | } | |
5869 | ||
851ba692 | 5870 | static int handle_dr(struct kvm_vcpu *vcpu) |
6aa8b732 | 5871 | { |
bfdaab09 | 5872 | unsigned long exit_qualification; |
16f8a6f9 NA |
5873 | int dr, dr7, reg; |
5874 | ||
5875 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
5876 | dr = exit_qualification & DEBUG_REG_ACCESS_NUM; | |
5877 | ||
5878 | /* First, if DR does not exist, trigger UD */ | |
5879 | if (!kvm_require_dr(vcpu, dr)) | |
5880 | return 1; | |
6aa8b732 | 5881 | |
f2483415 | 5882 | /* Do not handle if the CPL > 0, will trigger GP on re-entry */ |
0a79b009 AK |
5883 | if (!kvm_require_cpl(vcpu, 0)) |
5884 | return 1; | |
16f8a6f9 NA |
5885 | dr7 = vmcs_readl(GUEST_DR7); |
5886 | if (dr7 & DR7_GD) { | |
42dbaa5a JK |
5887 | /* |
5888 | * As the vm-exit takes precedence over the debug trap, we | |
5889 | * need to emulate the latter, either for the host or the | |
5890 | * guest debugging itself. | |
5891 | */ | |
5892 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
851ba692 | 5893 | vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; |
16f8a6f9 | 5894 | vcpu->run->debug.arch.dr7 = dr7; |
82b32774 | 5895 | vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
851ba692 AK |
5896 | vcpu->run->debug.arch.exception = DB_VECTOR; |
5897 | vcpu->run->exit_reason = KVM_EXIT_DEBUG; | |
42dbaa5a JK |
5898 | return 0; |
5899 | } else { | |
7305eb5d | 5900 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 5901 | vcpu->arch.dr6 |= DR6_BD | DR6_RTM; |
42dbaa5a JK |
5902 | kvm_queue_exception(vcpu, DB_VECTOR); |
5903 | return 1; | |
5904 | } | |
5905 | } | |
5906 | ||
81908bf4 | 5907 | if (vcpu->guest_debug == 0) { |
8f22372f PB |
5908 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
5909 | CPU_BASED_MOV_DR_EXITING); | |
81908bf4 PB |
5910 | |
5911 | /* | |
5912 | * No more DR vmexits; force a reload of the debug registers | |
5913 | * and reenter on this instruction. The next vmexit will | |
5914 | * retrieve the full state of the debug registers. | |
5915 | */ | |
5916 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
5917 | return 1; | |
5918 | } | |
5919 | ||
42dbaa5a JK |
5920 | reg = DEBUG_REG_ACCESS_REG(exit_qualification); |
5921 | if (exit_qualification & TYPE_MOV_FROM_DR) { | |
020df079 | 5922 | unsigned long val; |
4c4d563b JK |
5923 | |
5924 | if (kvm_get_dr(vcpu, dr, &val)) | |
5925 | return 1; | |
5926 | kvm_register_write(vcpu, reg, val); | |
020df079 | 5927 | } else |
5777392e | 5928 | if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) |
4c4d563b JK |
5929 | return 1; |
5930 | ||
6affcbed | 5931 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
5932 | } |
5933 | ||
73aaf249 JK |
5934 | static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) |
5935 | { | |
5936 | return vcpu->arch.dr6; | |
5937 | } | |
5938 | ||
5939 | static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) | |
5940 | { | |
5941 | } | |
5942 | ||
81908bf4 PB |
5943 | static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
5944 | { | |
81908bf4 PB |
5945 | get_debugreg(vcpu->arch.db[0], 0); |
5946 | get_debugreg(vcpu->arch.db[1], 1); | |
5947 | get_debugreg(vcpu->arch.db[2], 2); | |
5948 | get_debugreg(vcpu->arch.db[3], 3); | |
5949 | get_debugreg(vcpu->arch.dr6, 6); | |
5950 | vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); | |
5951 | ||
5952 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
8f22372f | 5953 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING); |
81908bf4 PB |
5954 | } |
5955 | ||
020df079 GN |
5956 | static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) |
5957 | { | |
5958 | vmcs_writel(GUEST_DR7, val); | |
5959 | } | |
5960 | ||
851ba692 | 5961 | static int handle_cpuid(struct kvm_vcpu *vcpu) |
6aa8b732 | 5962 | { |
6a908b62 | 5963 | return kvm_emulate_cpuid(vcpu); |
6aa8b732 AK |
5964 | } |
5965 | ||
851ba692 | 5966 | static int handle_rdmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 5967 | { |
ad312c7c | 5968 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
609e36d3 | 5969 | struct msr_data msr_info; |
6aa8b732 | 5970 | |
609e36d3 PB |
5971 | msr_info.index = ecx; |
5972 | msr_info.host_initiated = false; | |
5973 | if (vmx_get_msr(vcpu, &msr_info)) { | |
59200273 | 5974 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 5975 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
5976 | return 1; |
5977 | } | |
5978 | ||
609e36d3 | 5979 | trace_kvm_msr_read(ecx, msr_info.data); |
2714d1d3 | 5980 | |
6aa8b732 | 5981 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
609e36d3 PB |
5982 | vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u; |
5983 | vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u; | |
6affcbed | 5984 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
5985 | } |
5986 | ||
851ba692 | 5987 | static int handle_wrmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 5988 | { |
8fe8ab46 | 5989 | struct msr_data msr; |
ad312c7c ZX |
5990 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
5991 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
5992 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 | 5993 | |
8fe8ab46 WA |
5994 | msr.data = data; |
5995 | msr.index = ecx; | |
5996 | msr.host_initiated = false; | |
854e8bb1 | 5997 | if (kvm_set_msr(vcpu, &msr) != 0) { |
59200273 | 5998 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 5999 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
6000 | return 1; |
6001 | } | |
6002 | ||
59200273 | 6003 | trace_kvm_msr_write(ecx, data); |
6affcbed | 6004 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6005 | } |
6006 | ||
851ba692 | 6007 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) |
6e5d865c | 6008 | { |
eb90f341 | 6009 | kvm_apic_update_ppr(vcpu); |
6e5d865c YS |
6010 | return 1; |
6011 | } | |
6012 | ||
851ba692 | 6013 | static int handle_interrupt_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 6014 | { |
47c0152e PB |
6015 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
6016 | CPU_BASED_VIRTUAL_INTR_PENDING); | |
2714d1d3 | 6017 | |
3842d135 AK |
6018 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6019 | ||
a26bf12a | 6020 | ++vcpu->stat.irq_window_exits; |
6aa8b732 AK |
6021 | return 1; |
6022 | } | |
6023 | ||
851ba692 | 6024 | static int handle_halt(struct kvm_vcpu *vcpu) |
6aa8b732 | 6025 | { |
d3bef15f | 6026 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
6027 | } |
6028 | ||
851ba692 | 6029 | static int handle_vmcall(struct kvm_vcpu *vcpu) |
c21415e8 | 6030 | { |
0d9c055e | 6031 | return kvm_emulate_hypercall(vcpu); |
c21415e8 IM |
6032 | } |
6033 | ||
ec25d5e6 GN |
6034 | static int handle_invd(struct kvm_vcpu *vcpu) |
6035 | { | |
51d8b661 | 6036 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
ec25d5e6 GN |
6037 | } |
6038 | ||
851ba692 | 6039 | static int handle_invlpg(struct kvm_vcpu *vcpu) |
a7052897 | 6040 | { |
f9c617f6 | 6041 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
a7052897 MT |
6042 | |
6043 | kvm_mmu_invlpg(vcpu, exit_qualification); | |
6affcbed | 6044 | return kvm_skip_emulated_instruction(vcpu); |
a7052897 MT |
6045 | } |
6046 | ||
fee84b07 AK |
6047 | static int handle_rdpmc(struct kvm_vcpu *vcpu) |
6048 | { | |
6049 | int err; | |
6050 | ||
6051 | err = kvm_rdpmc(vcpu); | |
6affcbed | 6052 | return kvm_complete_insn_gp(vcpu, err); |
fee84b07 AK |
6053 | } |
6054 | ||
851ba692 | 6055 | static int handle_wbinvd(struct kvm_vcpu *vcpu) |
e5edaa01 | 6056 | { |
6affcbed | 6057 | return kvm_emulate_wbinvd(vcpu); |
e5edaa01 ED |
6058 | } |
6059 | ||
2acf923e DC |
6060 | static int handle_xsetbv(struct kvm_vcpu *vcpu) |
6061 | { | |
6062 | u64 new_bv = kvm_read_edx_eax(vcpu); | |
6063 | u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
6064 | ||
6065 | if (kvm_set_xcr(vcpu, index, new_bv) == 0) | |
6affcbed | 6066 | return kvm_skip_emulated_instruction(vcpu); |
2acf923e DC |
6067 | return 1; |
6068 | } | |
6069 | ||
f53cd63c WL |
6070 | static int handle_xsaves(struct kvm_vcpu *vcpu) |
6071 | { | |
6affcbed | 6072 | kvm_skip_emulated_instruction(vcpu); |
f53cd63c WL |
6073 | WARN(1, "this should never happen\n"); |
6074 | return 1; | |
6075 | } | |
6076 | ||
6077 | static int handle_xrstors(struct kvm_vcpu *vcpu) | |
6078 | { | |
6affcbed | 6079 | kvm_skip_emulated_instruction(vcpu); |
f53cd63c WL |
6080 | WARN(1, "this should never happen\n"); |
6081 | return 1; | |
6082 | } | |
6083 | ||
851ba692 | 6084 | static int handle_apic_access(struct kvm_vcpu *vcpu) |
f78e0e2e | 6085 | { |
58fbbf26 KT |
6086 | if (likely(fasteoi)) { |
6087 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6088 | int access_type, offset; | |
6089 | ||
6090 | access_type = exit_qualification & APIC_ACCESS_TYPE; | |
6091 | offset = exit_qualification & APIC_ACCESS_OFFSET; | |
6092 | /* | |
6093 | * Sane guest uses MOV to write EOI, with written value | |
6094 | * not cared. So make a short-circuit here by avoiding | |
6095 | * heavy instruction emulation. | |
6096 | */ | |
6097 | if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && | |
6098 | (offset == APIC_EOI)) { | |
6099 | kvm_lapic_set_eoi(vcpu); | |
6affcbed | 6100 | return kvm_skip_emulated_instruction(vcpu); |
58fbbf26 KT |
6101 | } |
6102 | } | |
51d8b661 | 6103 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
f78e0e2e SY |
6104 | } |
6105 | ||
c7c9c56c YZ |
6106 | static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) |
6107 | { | |
6108 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6109 | int vector = exit_qualification & 0xff; | |
6110 | ||
6111 | /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ | |
6112 | kvm_apic_set_eoi_accelerated(vcpu, vector); | |
6113 | return 1; | |
6114 | } | |
6115 | ||
83d4c286 YZ |
6116 | static int handle_apic_write(struct kvm_vcpu *vcpu) |
6117 | { | |
6118 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6119 | u32 offset = exit_qualification & 0xfff; | |
6120 | ||
6121 | /* APIC-write VM exit is trap-like and thus no need to adjust IP */ | |
6122 | kvm_apic_write_nodecode(vcpu, offset); | |
6123 | return 1; | |
6124 | } | |
6125 | ||
851ba692 | 6126 | static int handle_task_switch(struct kvm_vcpu *vcpu) |
37817f29 | 6127 | { |
60637aac | 6128 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
37817f29 | 6129 | unsigned long exit_qualification; |
e269fb21 JK |
6130 | bool has_error_code = false; |
6131 | u32 error_code = 0; | |
37817f29 | 6132 | u16 tss_selector; |
7f3d35fd | 6133 | int reason, type, idt_v, idt_index; |
64a7ec06 GN |
6134 | |
6135 | idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | |
7f3d35fd | 6136 | idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); |
64a7ec06 | 6137 | type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); |
37817f29 IE |
6138 | |
6139 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6140 | ||
6141 | reason = (u32)exit_qualification >> 30; | |
64a7ec06 GN |
6142 | if (reason == TASK_SWITCH_GATE && idt_v) { |
6143 | switch (type) { | |
6144 | case INTR_TYPE_NMI_INTR: | |
6145 | vcpu->arch.nmi_injected = false; | |
654f06fc | 6146 | vmx_set_nmi_mask(vcpu, true); |
64a7ec06 GN |
6147 | break; |
6148 | case INTR_TYPE_EXT_INTR: | |
66fd3f7f | 6149 | case INTR_TYPE_SOFT_INTR: |
64a7ec06 GN |
6150 | kvm_clear_interrupt_queue(vcpu); |
6151 | break; | |
6152 | case INTR_TYPE_HARD_EXCEPTION: | |
e269fb21 JK |
6153 | if (vmx->idt_vectoring_info & |
6154 | VECTORING_INFO_DELIVER_CODE_MASK) { | |
6155 | has_error_code = true; | |
6156 | error_code = | |
6157 | vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
6158 | } | |
6159 | /* fall through */ | |
64a7ec06 GN |
6160 | case INTR_TYPE_SOFT_EXCEPTION: |
6161 | kvm_clear_exception_queue(vcpu); | |
6162 | break; | |
6163 | default: | |
6164 | break; | |
6165 | } | |
60637aac | 6166 | } |
37817f29 IE |
6167 | tss_selector = exit_qualification; |
6168 | ||
64a7ec06 GN |
6169 | if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && |
6170 | type != INTR_TYPE_EXT_INTR && | |
6171 | type != INTR_TYPE_NMI_INTR)) | |
6172 | skip_emulated_instruction(vcpu); | |
6173 | ||
7f3d35fd KW |
6174 | if (kvm_task_switch(vcpu, tss_selector, |
6175 | type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason, | |
6176 | has_error_code, error_code) == EMULATE_FAIL) { | |
acb54517 GN |
6177 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
6178 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6179 | vcpu->run->internal.ndata = 0; | |
42dbaa5a | 6180 | return 0; |
acb54517 | 6181 | } |
42dbaa5a | 6182 | |
42dbaa5a JK |
6183 | /* |
6184 | * TODO: What about debug traps on tss switch? | |
6185 | * Are we supposed to inject them and update dr6? | |
6186 | */ | |
6187 | ||
6188 | return 1; | |
37817f29 IE |
6189 | } |
6190 | ||
851ba692 | 6191 | static int handle_ept_violation(struct kvm_vcpu *vcpu) |
1439442c | 6192 | { |
f9c617f6 | 6193 | unsigned long exit_qualification; |
1439442c | 6194 | gpa_t gpa; |
4f5982a5 | 6195 | u32 error_code; |
1439442c | 6196 | |
f9c617f6 | 6197 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
1439442c | 6198 | |
ae1e2d10 PB |
6199 | if (is_guest_mode(vcpu) |
6200 | && !(exit_qualification & EPT_VIOLATION_GVA_TRANSLATED)) { | |
6201 | /* | |
6202 | * Fix up exit_qualification according to whether guest | |
6203 | * page table accesses are reads or writes. | |
6204 | */ | |
6205 | u64 eptp = nested_ept_get_cr3(vcpu); | |
33251870 | 6206 | if (!(eptp & VMX_EPT_AD_ENABLE_BIT)) |
ae1e2d10 PB |
6207 | exit_qualification &= ~EPT_VIOLATION_ACC_WRITE; |
6208 | } | |
6209 | ||
0be9c7a8 GN |
6210 | /* |
6211 | * EPT violation happened while executing iret from NMI, | |
6212 | * "blocked by NMI" bit has to be set before next VM entry. | |
6213 | * There are errata that may cause this bit to not be set: | |
6214 | * AAK134, BY25. | |
6215 | */ | |
bcd1c294 | 6216 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && |
bcd1c294 | 6217 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) |
0be9c7a8 GN |
6218 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); |
6219 | ||
1439442c | 6220 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); |
229456fc | 6221 | trace_kvm_page_fault(gpa, exit_qualification); |
4f5982a5 | 6222 | |
27959a44 | 6223 | /* Is it a read fault? */ |
ab22a473 | 6224 | error_code = (exit_qualification & EPT_VIOLATION_ACC_READ) |
27959a44 JS |
6225 | ? PFERR_USER_MASK : 0; |
6226 | /* Is it a write fault? */ | |
ab22a473 | 6227 | error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE) |
27959a44 JS |
6228 | ? PFERR_WRITE_MASK : 0; |
6229 | /* Is it a fetch fault? */ | |
ab22a473 | 6230 | error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR) |
27959a44 JS |
6231 | ? PFERR_FETCH_MASK : 0; |
6232 | /* ept page table entry is present? */ | |
6233 | error_code |= (exit_qualification & | |
6234 | (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE | | |
6235 | EPT_VIOLATION_EXECUTABLE)) | |
6236 | ? PFERR_PRESENT_MASK : 0; | |
4f5982a5 | 6237 | |
db1c056c | 6238 | vcpu->arch.gpa_available = true; |
25d92081 YZ |
6239 | vcpu->arch.exit_qualification = exit_qualification; |
6240 | ||
4f5982a5 | 6241 | return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); |
1439442c SY |
6242 | } |
6243 | ||
851ba692 | 6244 | static int handle_ept_misconfig(struct kvm_vcpu *vcpu) |
68f89400 | 6245 | { |
f735d4af | 6246 | int ret; |
68f89400 MT |
6247 | gpa_t gpa; |
6248 | ||
6249 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
e32edf4f | 6250 | if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { |
931c33b1 | 6251 | trace_kvm_fast_mmio(gpa); |
6affcbed | 6252 | return kvm_skip_emulated_instruction(vcpu); |
68c3b4d1 | 6253 | } |
68f89400 | 6254 | |
450869d6 | 6255 | ret = handle_mmio_page_fault(vcpu, gpa, true); |
db1c056c | 6256 | vcpu->arch.gpa_available = true; |
b37fbea6 | 6257 | if (likely(ret == RET_MMIO_PF_EMULATE)) |
ce88decf XG |
6258 | return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) == |
6259 | EMULATE_DONE; | |
f8f55942 XG |
6260 | |
6261 | if (unlikely(ret == RET_MMIO_PF_INVALID)) | |
6262 | return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0); | |
6263 | ||
b37fbea6 | 6264 | if (unlikely(ret == RET_MMIO_PF_RETRY)) |
ce88decf XG |
6265 | return 1; |
6266 | ||
6267 | /* It is the real ept misconfig */ | |
f735d4af | 6268 | WARN_ON(1); |
68f89400 | 6269 | |
851ba692 AK |
6270 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
6271 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG; | |
68f89400 MT |
6272 | |
6273 | return 0; | |
6274 | } | |
6275 | ||
851ba692 | 6276 | static int handle_nmi_window(struct kvm_vcpu *vcpu) |
f08864b4 | 6277 | { |
47c0152e PB |
6278 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
6279 | CPU_BASED_VIRTUAL_NMI_PENDING); | |
f08864b4 | 6280 | ++vcpu->stat.nmi_window_exits; |
3842d135 | 6281 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f08864b4 SY |
6282 | |
6283 | return 1; | |
6284 | } | |
6285 | ||
80ced186 | 6286 | static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) |
ea953ef0 | 6287 | { |
8b3079a5 AK |
6288 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6289 | enum emulation_result err = EMULATE_DONE; | |
80ced186 | 6290 | int ret = 1; |
49e9d557 AK |
6291 | u32 cpu_exec_ctrl; |
6292 | bool intr_window_requested; | |
b8405c18 | 6293 | unsigned count = 130; |
49e9d557 AK |
6294 | |
6295 | cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
6296 | intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING; | |
ea953ef0 | 6297 | |
98eb2f8b | 6298 | while (vmx->emulation_required && count-- != 0) { |
bdea48e3 | 6299 | if (intr_window_requested && vmx_interrupt_allowed(vcpu)) |
49e9d557 AK |
6300 | return handle_interrupt_window(&vmx->vcpu); |
6301 | ||
72875d8a | 6302 | if (kvm_test_request(KVM_REQ_EVENT, vcpu)) |
de87dcdd AK |
6303 | return 1; |
6304 | ||
991eebf9 | 6305 | err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE); |
ea953ef0 | 6306 | |
ac0a48c3 | 6307 | if (err == EMULATE_USER_EXIT) { |
94452b9e | 6308 | ++vcpu->stat.mmio_exits; |
80ced186 MG |
6309 | ret = 0; |
6310 | goto out; | |
6311 | } | |
1d5a4d9b | 6312 | |
de5f70e0 AK |
6313 | if (err != EMULATE_DONE) { |
6314 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
6315 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6316 | vcpu->run->internal.ndata = 0; | |
6d77dbfc | 6317 | return 0; |
de5f70e0 | 6318 | } |
ea953ef0 | 6319 | |
8d76c49e GN |
6320 | if (vcpu->arch.halt_request) { |
6321 | vcpu->arch.halt_request = 0; | |
5cb56059 | 6322 | ret = kvm_vcpu_halt(vcpu); |
8d76c49e GN |
6323 | goto out; |
6324 | } | |
6325 | ||
ea953ef0 | 6326 | if (signal_pending(current)) |
80ced186 | 6327 | goto out; |
ea953ef0 MG |
6328 | if (need_resched()) |
6329 | schedule(); | |
6330 | } | |
6331 | ||
80ced186 MG |
6332 | out: |
6333 | return ret; | |
ea953ef0 MG |
6334 | } |
6335 | ||
b4a2d31d RK |
6336 | static int __grow_ple_window(int val) |
6337 | { | |
6338 | if (ple_window_grow < 1) | |
6339 | return ple_window; | |
6340 | ||
6341 | val = min(val, ple_window_actual_max); | |
6342 | ||
6343 | if (ple_window_grow < ple_window) | |
6344 | val *= ple_window_grow; | |
6345 | else | |
6346 | val += ple_window_grow; | |
6347 | ||
6348 | return val; | |
6349 | } | |
6350 | ||
6351 | static int __shrink_ple_window(int val, int modifier, int minimum) | |
6352 | { | |
6353 | if (modifier < 1) | |
6354 | return ple_window; | |
6355 | ||
6356 | if (modifier < ple_window) | |
6357 | val /= modifier; | |
6358 | else | |
6359 | val -= modifier; | |
6360 | ||
6361 | return max(val, minimum); | |
6362 | } | |
6363 | ||
6364 | static void grow_ple_window(struct kvm_vcpu *vcpu) | |
6365 | { | |
6366 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6367 | int old = vmx->ple_window; | |
6368 | ||
6369 | vmx->ple_window = __grow_ple_window(old); | |
6370 | ||
6371 | if (vmx->ple_window != old) | |
6372 | vmx->ple_window_dirty = true; | |
7b46268d RK |
6373 | |
6374 | trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
6375 | } |
6376 | ||
6377 | static void shrink_ple_window(struct kvm_vcpu *vcpu) | |
6378 | { | |
6379 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6380 | int old = vmx->ple_window; | |
6381 | ||
6382 | vmx->ple_window = __shrink_ple_window(old, | |
6383 | ple_window_shrink, ple_window); | |
6384 | ||
6385 | if (vmx->ple_window != old) | |
6386 | vmx->ple_window_dirty = true; | |
7b46268d RK |
6387 | |
6388 | trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
6389 | } |
6390 | ||
6391 | /* | |
6392 | * ple_window_actual_max is computed to be one grow_ple_window() below | |
6393 | * ple_window_max. (See __grow_ple_window for the reason.) | |
6394 | * This prevents overflows, because ple_window_max is int. | |
6395 | * ple_window_max effectively rounded down to a multiple of ple_window_grow in | |
6396 | * this process. | |
6397 | * ple_window_max is also prevented from setting vmx->ple_window < ple_window. | |
6398 | */ | |
6399 | static void update_ple_window_actual_max(void) | |
6400 | { | |
6401 | ple_window_actual_max = | |
6402 | __shrink_ple_window(max(ple_window_max, ple_window), | |
6403 | ple_window_grow, INT_MIN); | |
6404 | } | |
6405 | ||
bf9f6ac8 FW |
6406 | /* |
6407 | * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. | |
6408 | */ | |
6409 | static void wakeup_handler(void) | |
6410 | { | |
6411 | struct kvm_vcpu *vcpu; | |
6412 | int cpu = smp_processor_id(); | |
6413 | ||
6414 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
6415 | list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), | |
6416 | blocked_vcpu_list) { | |
6417 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
6418 | ||
6419 | if (pi_test_on(pi_desc) == 1) | |
6420 | kvm_vcpu_kick(vcpu); | |
6421 | } | |
6422 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
6423 | } | |
6424 | ||
f160c7b7 JS |
6425 | void vmx_enable_tdp(void) |
6426 | { | |
6427 | kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, | |
6428 | enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull, | |
6429 | enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull, | |
6430 | 0ull, VMX_EPT_EXECUTABLE_MASK, | |
6431 | cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK, | |
312b616b | 6432 | enable_ept_ad_bits ? 0ull : VMX_EPT_RWX_MASK); |
f160c7b7 JS |
6433 | |
6434 | ept_set_mmio_spte_mask(); | |
6435 | kvm_enable_tdp(); | |
6436 | } | |
6437 | ||
f2c7648d TC |
6438 | static __init int hardware_setup(void) |
6439 | { | |
34a1cd60 TC |
6440 | int r = -ENOMEM, i, msr; |
6441 | ||
6442 | rdmsrl_safe(MSR_EFER, &host_efer); | |
6443 | ||
6444 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) | |
6445 | kvm_define_shared_msr(i, vmx_msr_index[i]); | |
6446 | ||
23611332 RK |
6447 | for (i = 0; i < VMX_BITMAP_NR; i++) { |
6448 | vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL); | |
6449 | if (!vmx_bitmap[i]) | |
6450 | goto out; | |
6451 | } | |
34a1cd60 TC |
6452 | |
6453 | vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL); | |
34a1cd60 TC |
6454 | memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE); |
6455 | memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE); | |
6456 | ||
6457 | /* | |
6458 | * Allow direct access to the PC debug port (it is often used for I/O | |
6459 | * delays, but the vmexits simply slow things down). | |
6460 | */ | |
6461 | memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE); | |
6462 | clear_bit(0x80, vmx_io_bitmap_a); | |
6463 | ||
6464 | memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE); | |
6465 | ||
6466 | memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE); | |
6467 | memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE); | |
6468 | ||
34a1cd60 TC |
6469 | if (setup_vmcs_config(&vmcs_config) < 0) { |
6470 | r = -EIO; | |
23611332 | 6471 | goto out; |
baa03522 | 6472 | } |
f2c7648d TC |
6473 | |
6474 | if (boot_cpu_has(X86_FEATURE_NX)) | |
6475 | kvm_enable_efer_bits(EFER_NX); | |
6476 | ||
08d839c4 WL |
6477 | if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || |
6478 | !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) | |
f2c7648d | 6479 | enable_vpid = 0; |
08d839c4 | 6480 | |
f2c7648d TC |
6481 | if (!cpu_has_vmx_shadow_vmcs()) |
6482 | enable_shadow_vmcs = 0; | |
6483 | if (enable_shadow_vmcs) | |
6484 | init_vmcs_shadow_fields(); | |
6485 | ||
6486 | if (!cpu_has_vmx_ept() || | |
6487 | !cpu_has_vmx_ept_4levels()) { | |
6488 | enable_ept = 0; | |
6489 | enable_unrestricted_guest = 0; | |
6490 | enable_ept_ad_bits = 0; | |
6491 | } | |
6492 | ||
6493 | if (!cpu_has_vmx_ept_ad_bits()) | |
6494 | enable_ept_ad_bits = 0; | |
6495 | ||
6496 | if (!cpu_has_vmx_unrestricted_guest()) | |
6497 | enable_unrestricted_guest = 0; | |
6498 | ||
ad15a296 | 6499 | if (!cpu_has_vmx_flexpriority()) |
f2c7648d TC |
6500 | flexpriority_enabled = 0; |
6501 | ||
ad15a296 PB |
6502 | /* |
6503 | * set_apic_access_page_addr() is used to reload apic access | |
6504 | * page upon invalidation. No need to do anything if not | |
6505 | * using the APIC_ACCESS_ADDR VMCS field. | |
6506 | */ | |
6507 | if (!flexpriority_enabled) | |
f2c7648d | 6508 | kvm_x86_ops->set_apic_access_page_addr = NULL; |
f2c7648d TC |
6509 | |
6510 | if (!cpu_has_vmx_tpr_shadow()) | |
6511 | kvm_x86_ops->update_cr8_intercept = NULL; | |
6512 | ||
6513 | if (enable_ept && !cpu_has_vmx_ept_2m_page()) | |
6514 | kvm_disable_largepages(); | |
6515 | ||
6516 | if (!cpu_has_vmx_ple()) | |
6517 | ple_gap = 0; | |
6518 | ||
76dfafd5 | 6519 | if (!cpu_has_vmx_apicv()) { |
f2c7648d | 6520 | enable_apicv = 0; |
76dfafd5 PB |
6521 | kvm_x86_ops->sync_pir_to_irr = NULL; |
6522 | } | |
f2c7648d | 6523 | |
64903d61 HZ |
6524 | if (cpu_has_vmx_tsc_scaling()) { |
6525 | kvm_has_tsc_control = true; | |
6526 | kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; | |
6527 | kvm_tsc_scaling_ratio_frac_bits = 48; | |
6528 | } | |
6529 | ||
baa03522 TC |
6530 | vmx_disable_intercept_for_msr(MSR_FS_BASE, false); |
6531 | vmx_disable_intercept_for_msr(MSR_GS_BASE, false); | |
6532 | vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true); | |
6533 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false); | |
6534 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false); | |
6535 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false); | |
6536 | vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true); | |
6537 | ||
c63e4563 | 6538 | memcpy(vmx_msr_bitmap_legacy_x2apic_apicv, |
baa03522 | 6539 | vmx_msr_bitmap_legacy, PAGE_SIZE); |
c63e4563 | 6540 | memcpy(vmx_msr_bitmap_longmode_x2apic_apicv, |
baa03522 | 6541 | vmx_msr_bitmap_longmode, PAGE_SIZE); |
c63e4563 | 6542 | memcpy(vmx_msr_bitmap_legacy_x2apic, |
f6e90f9e | 6543 | vmx_msr_bitmap_legacy, PAGE_SIZE); |
c63e4563 | 6544 | memcpy(vmx_msr_bitmap_longmode_x2apic, |
f6e90f9e | 6545 | vmx_msr_bitmap_longmode, PAGE_SIZE); |
baa03522 | 6546 | |
04bb92e4 WL |
6547 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
6548 | ||
40d8338d RK |
6549 | for (msr = 0x800; msr <= 0x8ff; msr++) { |
6550 | if (msr == 0x839 /* TMCCT */) | |
6551 | continue; | |
2e69f865 | 6552 | vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true); |
40d8338d | 6553 | } |
3ce424e4 | 6554 | |
f6e90f9e | 6555 | /* |
2e69f865 RK |
6556 | * TPR reads and writes can be virtualized even if virtual interrupt |
6557 | * delivery is not in use. | |
f6e90f9e | 6558 | */ |
2e69f865 RK |
6559 | vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true); |
6560 | vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false); | |
3ce424e4 | 6561 | |
3ce424e4 | 6562 | /* EOI */ |
2e69f865 | 6563 | vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true); |
3ce424e4 | 6564 | /* SELF-IPI */ |
2e69f865 | 6565 | vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true); |
baa03522 | 6566 | |
f160c7b7 JS |
6567 | if (enable_ept) |
6568 | vmx_enable_tdp(); | |
6569 | else | |
baa03522 TC |
6570 | kvm_disable_tdp(); |
6571 | ||
6572 | update_ple_window_actual_max(); | |
6573 | ||
843e4330 KH |
6574 | /* |
6575 | * Only enable PML when hardware supports PML feature, and both EPT | |
6576 | * and EPT A/D bit features are enabled -- PML depends on them to work. | |
6577 | */ | |
6578 | if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) | |
6579 | enable_pml = 0; | |
6580 | ||
6581 | if (!enable_pml) { | |
6582 | kvm_x86_ops->slot_enable_log_dirty = NULL; | |
6583 | kvm_x86_ops->slot_disable_log_dirty = NULL; | |
6584 | kvm_x86_ops->flush_log_dirty = NULL; | |
6585 | kvm_x86_ops->enable_log_dirty_pt_masked = NULL; | |
6586 | } | |
6587 | ||
64672c95 YJ |
6588 | if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) { |
6589 | u64 vmx_msr; | |
6590 | ||
6591 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
6592 | cpu_preemption_timer_multi = | |
6593 | vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; | |
6594 | } else { | |
6595 | kvm_x86_ops->set_hv_timer = NULL; | |
6596 | kvm_x86_ops->cancel_hv_timer = NULL; | |
6597 | } | |
6598 | ||
bf9f6ac8 FW |
6599 | kvm_set_posted_intr_wakeup_handler(wakeup_handler); |
6600 | ||
c45dcc71 AR |
6601 | kvm_mce_cap_supported |= MCG_LMCE_P; |
6602 | ||
f2c7648d | 6603 | return alloc_kvm_area(); |
34a1cd60 | 6604 | |
34a1cd60 | 6605 | out: |
23611332 RK |
6606 | for (i = 0; i < VMX_BITMAP_NR; i++) |
6607 | free_page((unsigned long)vmx_bitmap[i]); | |
34a1cd60 TC |
6608 | |
6609 | return r; | |
f2c7648d TC |
6610 | } |
6611 | ||
6612 | static __exit void hardware_unsetup(void) | |
6613 | { | |
23611332 RK |
6614 | int i; |
6615 | ||
6616 | for (i = 0; i < VMX_BITMAP_NR; i++) | |
6617 | free_page((unsigned long)vmx_bitmap[i]); | |
34a1cd60 | 6618 | |
f2c7648d TC |
6619 | free_kvm_area(); |
6620 | } | |
6621 | ||
4b8d54f9 ZE |
6622 | /* |
6623 | * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE | |
6624 | * exiting, so only get here on cpu with PAUSE-Loop-Exiting. | |
6625 | */ | |
9fb41ba8 | 6626 | static int handle_pause(struct kvm_vcpu *vcpu) |
4b8d54f9 | 6627 | { |
b4a2d31d RK |
6628 | if (ple_gap) |
6629 | grow_ple_window(vcpu); | |
6630 | ||
4b8d54f9 | 6631 | kvm_vcpu_on_spin(vcpu); |
6affcbed | 6632 | return kvm_skip_emulated_instruction(vcpu); |
4b8d54f9 ZE |
6633 | } |
6634 | ||
87c00572 | 6635 | static int handle_nop(struct kvm_vcpu *vcpu) |
59708670 | 6636 | { |
6affcbed | 6637 | return kvm_skip_emulated_instruction(vcpu); |
59708670 SY |
6638 | } |
6639 | ||
87c00572 GS |
6640 | static int handle_mwait(struct kvm_vcpu *vcpu) |
6641 | { | |
6642 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
6643 | return handle_nop(vcpu); | |
6644 | } | |
6645 | ||
5f3d45e7 MD |
6646 | static int handle_monitor_trap(struct kvm_vcpu *vcpu) |
6647 | { | |
6648 | return 1; | |
6649 | } | |
6650 | ||
87c00572 GS |
6651 | static int handle_monitor(struct kvm_vcpu *vcpu) |
6652 | { | |
6653 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
6654 | return handle_nop(vcpu); | |
6655 | } | |
6656 | ||
ff2f6fe9 NHE |
6657 | /* |
6658 | * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12. | |
6659 | * We could reuse a single VMCS for all the L2 guests, but we also want the | |
6660 | * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this | |
6661 | * allows keeping them loaded on the processor, and in the future will allow | |
6662 | * optimizations where prepare_vmcs02 doesn't need to set all the fields on | |
6663 | * every entry if they never change. | |
6664 | * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE | |
6665 | * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first. | |
6666 | * | |
6667 | * The following functions allocate and free a vmcs02 in this pool. | |
6668 | */ | |
6669 | ||
6670 | /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */ | |
6671 | static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx) | |
6672 | { | |
6673 | struct vmcs02_list *item; | |
6674 | list_for_each_entry(item, &vmx->nested.vmcs02_pool, list) | |
6675 | if (item->vmptr == vmx->nested.current_vmptr) { | |
6676 | list_move(&item->list, &vmx->nested.vmcs02_pool); | |
6677 | return &item->vmcs02; | |
6678 | } | |
6679 | ||
6680 | if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) { | |
6681 | /* Recycle the least recently used VMCS. */ | |
d74c0e6b GT |
6682 | item = list_last_entry(&vmx->nested.vmcs02_pool, |
6683 | struct vmcs02_list, list); | |
ff2f6fe9 NHE |
6684 | item->vmptr = vmx->nested.current_vmptr; |
6685 | list_move(&item->list, &vmx->nested.vmcs02_pool); | |
6686 | return &item->vmcs02; | |
6687 | } | |
6688 | ||
6689 | /* Create a new VMCS */ | |
0fa24ce3 | 6690 | item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL); |
ff2f6fe9 NHE |
6691 | if (!item) |
6692 | return NULL; | |
6693 | item->vmcs02.vmcs = alloc_vmcs(); | |
355f4fb1 | 6694 | item->vmcs02.shadow_vmcs = NULL; |
ff2f6fe9 NHE |
6695 | if (!item->vmcs02.vmcs) { |
6696 | kfree(item); | |
6697 | return NULL; | |
6698 | } | |
6699 | loaded_vmcs_init(&item->vmcs02); | |
6700 | item->vmptr = vmx->nested.current_vmptr; | |
6701 | list_add(&(item->list), &(vmx->nested.vmcs02_pool)); | |
6702 | vmx->nested.vmcs02_num++; | |
6703 | return &item->vmcs02; | |
6704 | } | |
6705 | ||
6706 | /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */ | |
6707 | static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr) | |
6708 | { | |
6709 | struct vmcs02_list *item; | |
6710 | list_for_each_entry(item, &vmx->nested.vmcs02_pool, list) | |
6711 | if (item->vmptr == vmptr) { | |
6712 | free_loaded_vmcs(&item->vmcs02); | |
6713 | list_del(&item->list); | |
6714 | kfree(item); | |
6715 | vmx->nested.vmcs02_num--; | |
6716 | return; | |
6717 | } | |
6718 | } | |
6719 | ||
6720 | /* | |
6721 | * Free all VMCSs saved for this vcpu, except the one pointed by | |
4fa7734c PB |
6722 | * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs |
6723 | * must be &vmx->vmcs01. | |
ff2f6fe9 NHE |
6724 | */ |
6725 | static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx) | |
6726 | { | |
6727 | struct vmcs02_list *item, *n; | |
4fa7734c PB |
6728 | |
6729 | WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01); | |
ff2f6fe9 | 6730 | list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) { |
4fa7734c PB |
6731 | /* |
6732 | * Something will leak if the above WARN triggers. Better than | |
6733 | * a use-after-free. | |
6734 | */ | |
6735 | if (vmx->loaded_vmcs == &item->vmcs02) | |
6736 | continue; | |
6737 | ||
6738 | free_loaded_vmcs(&item->vmcs02); | |
ff2f6fe9 NHE |
6739 | list_del(&item->list); |
6740 | kfree(item); | |
4fa7734c | 6741 | vmx->nested.vmcs02_num--; |
ff2f6fe9 | 6742 | } |
ff2f6fe9 NHE |
6743 | } |
6744 | ||
0658fbaa ACL |
6745 | /* |
6746 | * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(), | |
6747 | * set the success or error code of an emulated VMX instruction, as specified | |
6748 | * by Vol 2B, VMX Instruction Reference, "Conventions". | |
6749 | */ | |
6750 | static void nested_vmx_succeed(struct kvm_vcpu *vcpu) | |
6751 | { | |
6752 | vmx_set_rflags(vcpu, vmx_get_rflags(vcpu) | |
6753 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
6754 | X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF)); | |
6755 | } | |
6756 | ||
6757 | static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu) | |
6758 | { | |
6759 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
6760 | & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | | |
6761 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
6762 | | X86_EFLAGS_CF); | |
6763 | } | |
6764 | ||
145c28dd | 6765 | static void nested_vmx_failValid(struct kvm_vcpu *vcpu, |
0658fbaa ACL |
6766 | u32 vm_instruction_error) |
6767 | { | |
6768 | if (to_vmx(vcpu)->nested.current_vmptr == -1ull) { | |
6769 | /* | |
6770 | * failValid writes the error number to the current VMCS, which | |
6771 | * can't be done there isn't a current VMCS. | |
6772 | */ | |
6773 | nested_vmx_failInvalid(vcpu); | |
6774 | return; | |
6775 | } | |
6776 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
6777 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
6778 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
6779 | | X86_EFLAGS_ZF); | |
6780 | get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error; | |
6781 | /* | |
6782 | * We don't need to force a shadow sync because | |
6783 | * VM_INSTRUCTION_ERROR is not shadowed | |
6784 | */ | |
6785 | } | |
145c28dd | 6786 | |
ff651cb6 WV |
6787 | static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator) |
6788 | { | |
6789 | /* TODO: not to reset guest simply here. */ | |
6790 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
bbe41b95 | 6791 | pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator); |
ff651cb6 WV |
6792 | } |
6793 | ||
f4124500 JK |
6794 | static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer) |
6795 | { | |
6796 | struct vcpu_vmx *vmx = | |
6797 | container_of(timer, struct vcpu_vmx, nested.preemption_timer); | |
6798 | ||
6799 | vmx->nested.preemption_timer_expired = true; | |
6800 | kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu); | |
6801 | kvm_vcpu_kick(&vmx->vcpu); | |
6802 | ||
6803 | return HRTIMER_NORESTART; | |
6804 | } | |
6805 | ||
19677e32 BD |
6806 | /* |
6807 | * Decode the memory-address operand of a vmx instruction, as recorded on an | |
6808 | * exit caused by such an instruction (run by a guest hypervisor). | |
6809 | * On success, returns 0. When the operand is invalid, returns 1 and throws | |
6810 | * #UD or #GP. | |
6811 | */ | |
6812 | static int get_vmx_mem_address(struct kvm_vcpu *vcpu, | |
6813 | unsigned long exit_qualification, | |
f9eb4af6 | 6814 | u32 vmx_instruction_info, bool wr, gva_t *ret) |
19677e32 | 6815 | { |
f9eb4af6 EK |
6816 | gva_t off; |
6817 | bool exn; | |
6818 | struct kvm_segment s; | |
6819 | ||
19677e32 BD |
6820 | /* |
6821 | * According to Vol. 3B, "Information for VM Exits Due to Instruction | |
6822 | * Execution", on an exit, vmx_instruction_info holds most of the | |
6823 | * addressing components of the operand. Only the displacement part | |
6824 | * is put in exit_qualification (see 3B, "Basic VM-Exit Information"). | |
6825 | * For how an actual address is calculated from all these components, | |
6826 | * refer to Vol. 1, "Operand Addressing". | |
6827 | */ | |
6828 | int scaling = vmx_instruction_info & 3; | |
6829 | int addr_size = (vmx_instruction_info >> 7) & 7; | |
6830 | bool is_reg = vmx_instruction_info & (1u << 10); | |
6831 | int seg_reg = (vmx_instruction_info >> 15) & 7; | |
6832 | int index_reg = (vmx_instruction_info >> 18) & 0xf; | |
6833 | bool index_is_valid = !(vmx_instruction_info & (1u << 22)); | |
6834 | int base_reg = (vmx_instruction_info >> 23) & 0xf; | |
6835 | bool base_is_valid = !(vmx_instruction_info & (1u << 27)); | |
6836 | ||
6837 | if (is_reg) { | |
6838 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6839 | return 1; | |
6840 | } | |
6841 | ||
6842 | /* Addr = segment_base + offset */ | |
6843 | /* offset = base + [index * scale] + displacement */ | |
f9eb4af6 | 6844 | off = exit_qualification; /* holds the displacement */ |
19677e32 | 6845 | if (base_is_valid) |
f9eb4af6 | 6846 | off += kvm_register_read(vcpu, base_reg); |
19677e32 | 6847 | if (index_is_valid) |
f9eb4af6 EK |
6848 | off += kvm_register_read(vcpu, index_reg)<<scaling; |
6849 | vmx_get_segment(vcpu, &s, seg_reg); | |
6850 | *ret = s.base + off; | |
19677e32 BD |
6851 | |
6852 | if (addr_size == 1) /* 32 bit */ | |
6853 | *ret &= 0xffffffff; | |
6854 | ||
f9eb4af6 EK |
6855 | /* Checks for #GP/#SS exceptions. */ |
6856 | exn = false; | |
ff30ef40 QC |
6857 | if (is_long_mode(vcpu)) { |
6858 | /* Long mode: #GP(0)/#SS(0) if the memory address is in a | |
6859 | * non-canonical form. This is the only check on the memory | |
6860 | * destination for long mode! | |
6861 | */ | |
6862 | exn = is_noncanonical_address(*ret); | |
6863 | } else if (is_protmode(vcpu)) { | |
f9eb4af6 EK |
6864 | /* Protected mode: apply checks for segment validity in the |
6865 | * following order: | |
6866 | * - segment type check (#GP(0) may be thrown) | |
6867 | * - usability check (#GP(0)/#SS(0)) | |
6868 | * - limit check (#GP(0)/#SS(0)) | |
6869 | */ | |
6870 | if (wr) | |
6871 | /* #GP(0) if the destination operand is located in a | |
6872 | * read-only data segment or any code segment. | |
6873 | */ | |
6874 | exn = ((s.type & 0xa) == 0 || (s.type & 8)); | |
6875 | else | |
6876 | /* #GP(0) if the source operand is located in an | |
6877 | * execute-only code segment | |
6878 | */ | |
6879 | exn = ((s.type & 0xa) == 8); | |
ff30ef40 QC |
6880 | if (exn) { |
6881 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
6882 | return 1; | |
6883 | } | |
f9eb4af6 EK |
6884 | /* Protected mode: #GP(0)/#SS(0) if the segment is unusable. |
6885 | */ | |
6886 | exn = (s.unusable != 0); | |
6887 | /* Protected mode: #GP(0)/#SS(0) if the memory | |
6888 | * operand is outside the segment limit. | |
6889 | */ | |
6890 | exn = exn || (off + sizeof(u64) > s.limit); | |
6891 | } | |
6892 | if (exn) { | |
6893 | kvm_queue_exception_e(vcpu, | |
6894 | seg_reg == VCPU_SREG_SS ? | |
6895 | SS_VECTOR : GP_VECTOR, | |
6896 | 0); | |
6897 | return 1; | |
6898 | } | |
6899 | ||
19677e32 BD |
6900 | return 0; |
6901 | } | |
6902 | ||
3573e22c BD |
6903 | /* |
6904 | * This function performs the various checks including | |
6905 | * - if it's 4KB aligned | |
6906 | * - No bits beyond the physical address width are set | |
6907 | * - Returns 0 on success or else 1 | |
4291b588 | 6908 | * (Intel SDM Section 30.3) |
3573e22c | 6909 | */ |
4291b588 BD |
6910 | static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason, |
6911 | gpa_t *vmpointer) | |
3573e22c BD |
6912 | { |
6913 | gva_t gva; | |
6914 | gpa_t vmptr; | |
6915 | struct x86_exception e; | |
6916 | struct page *page; | |
6917 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6918 | int maxphyaddr = cpuid_maxphyaddr(vcpu); | |
6919 | ||
6920 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
f9eb4af6 | 6921 | vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva)) |
3573e22c BD |
6922 | return 1; |
6923 | ||
6924 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr, | |
6925 | sizeof(vmptr), &e)) { | |
6926 | kvm_inject_page_fault(vcpu, &e); | |
6927 | return 1; | |
6928 | } | |
6929 | ||
6930 | switch (exit_reason) { | |
6931 | case EXIT_REASON_VMON: | |
6932 | /* | |
6933 | * SDM 3: 24.11.5 | |
6934 | * The first 4 bytes of VMXON region contain the supported | |
6935 | * VMCS revision identifier | |
6936 | * | |
6937 | * Note - IA32_VMX_BASIC[48] will never be 1 | |
6938 | * for the nested case; | |
6939 | * which replaces physical address width with 32 | |
6940 | * | |
6941 | */ | |
bc39c4db | 6942 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) { |
3573e22c | 6943 | nested_vmx_failInvalid(vcpu); |
6affcbed | 6944 | return kvm_skip_emulated_instruction(vcpu); |
3573e22c BD |
6945 | } |
6946 | ||
6947 | page = nested_get_page(vcpu, vmptr); | |
06ce521a | 6948 | if (page == NULL) { |
3573e22c | 6949 | nested_vmx_failInvalid(vcpu); |
06ce521a PB |
6950 | return kvm_skip_emulated_instruction(vcpu); |
6951 | } | |
6952 | if (*(u32 *)kmap(page) != VMCS12_REVISION) { | |
3573e22c | 6953 | kunmap(page); |
06ce521a PB |
6954 | nested_release_page_clean(page); |
6955 | nested_vmx_failInvalid(vcpu); | |
6affcbed | 6956 | return kvm_skip_emulated_instruction(vcpu); |
3573e22c BD |
6957 | } |
6958 | kunmap(page); | |
06ce521a | 6959 | nested_release_page_clean(page); |
3573e22c BD |
6960 | vmx->nested.vmxon_ptr = vmptr; |
6961 | break; | |
4291b588 | 6962 | case EXIT_REASON_VMCLEAR: |
bc39c4db | 6963 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) { |
4291b588 BD |
6964 | nested_vmx_failValid(vcpu, |
6965 | VMXERR_VMCLEAR_INVALID_ADDRESS); | |
6affcbed | 6966 | return kvm_skip_emulated_instruction(vcpu); |
4291b588 BD |
6967 | } |
6968 | ||
6969 | if (vmptr == vmx->nested.vmxon_ptr) { | |
6970 | nested_vmx_failValid(vcpu, | |
6971 | VMXERR_VMCLEAR_VMXON_POINTER); | |
6affcbed | 6972 | return kvm_skip_emulated_instruction(vcpu); |
4291b588 BD |
6973 | } |
6974 | break; | |
6975 | case EXIT_REASON_VMPTRLD: | |
bc39c4db | 6976 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) { |
4291b588 BD |
6977 | nested_vmx_failValid(vcpu, |
6978 | VMXERR_VMPTRLD_INVALID_ADDRESS); | |
6affcbed | 6979 | return kvm_skip_emulated_instruction(vcpu); |
4291b588 | 6980 | } |
3573e22c | 6981 | |
4291b588 BD |
6982 | if (vmptr == vmx->nested.vmxon_ptr) { |
6983 | nested_vmx_failValid(vcpu, | |
37b9a671 | 6984 | VMXERR_VMPTRLD_VMXON_POINTER); |
6affcbed | 6985 | return kvm_skip_emulated_instruction(vcpu); |
4291b588 BD |
6986 | } |
6987 | break; | |
3573e22c BD |
6988 | default: |
6989 | return 1; /* shouldn't happen */ | |
6990 | } | |
6991 | ||
4291b588 BD |
6992 | if (vmpointer) |
6993 | *vmpointer = vmptr; | |
3573e22c BD |
6994 | return 0; |
6995 | } | |
6996 | ||
e29acc55 JM |
6997 | static int enter_vmx_operation(struct kvm_vcpu *vcpu) |
6998 | { | |
6999 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7000 | struct vmcs *shadow_vmcs; | |
7001 | ||
7002 | if (cpu_has_vmx_msr_bitmap()) { | |
7003 | vmx->nested.msr_bitmap = | |
7004 | (unsigned long *)__get_free_page(GFP_KERNEL); | |
7005 | if (!vmx->nested.msr_bitmap) | |
7006 | goto out_msr_bitmap; | |
7007 | } | |
7008 | ||
7009 | vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL); | |
7010 | if (!vmx->nested.cached_vmcs12) | |
7011 | goto out_cached_vmcs12; | |
7012 | ||
7013 | if (enable_shadow_vmcs) { | |
7014 | shadow_vmcs = alloc_vmcs(); | |
7015 | if (!shadow_vmcs) | |
7016 | goto out_shadow_vmcs; | |
7017 | /* mark vmcs as shadow */ | |
7018 | shadow_vmcs->revision_id |= (1u << 31); | |
7019 | /* init shadow vmcs */ | |
7020 | vmcs_clear(shadow_vmcs); | |
7021 | vmx->vmcs01.shadow_vmcs = shadow_vmcs; | |
7022 | } | |
7023 | ||
7024 | INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool)); | |
7025 | vmx->nested.vmcs02_num = 0; | |
7026 | ||
7027 | hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC, | |
7028 | HRTIMER_MODE_REL_PINNED); | |
7029 | vmx->nested.preemption_timer.function = vmx_preemption_timer_fn; | |
7030 | ||
7031 | vmx->nested.vmxon = true; | |
7032 | return 0; | |
7033 | ||
7034 | out_shadow_vmcs: | |
7035 | kfree(vmx->nested.cached_vmcs12); | |
7036 | ||
7037 | out_cached_vmcs12: | |
7038 | free_page((unsigned long)vmx->nested.msr_bitmap); | |
7039 | ||
7040 | out_msr_bitmap: | |
7041 | return -ENOMEM; | |
7042 | } | |
7043 | ||
ec378aee NHE |
7044 | /* |
7045 | * Emulate the VMXON instruction. | |
7046 | * Currently, we just remember that VMX is active, and do not save or even | |
7047 | * inspect the argument to VMXON (the so-called "VMXON pointer") because we | |
7048 | * do not currently need to store anything in that guest-allocated memory | |
7049 | * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their | |
7050 | * argument is different from the VMXON pointer (which the spec says they do). | |
7051 | */ | |
7052 | static int handle_vmon(struct kvm_vcpu *vcpu) | |
7053 | { | |
e29acc55 | 7054 | int ret; |
ec378aee | 7055 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
b3897a49 NHE |
7056 | const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED |
7057 | | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
ec378aee | 7058 | |
70f3aac9 JM |
7059 | /* |
7060 | * The Intel VMX Instruction Reference lists a bunch of bits that are | |
7061 | * prerequisite to running VMXON, most notably cr4.VMXE must be set to | |
7062 | * 1 (see vmx_set_cr4() for when we allow the guest to set this). | |
7063 | * Otherwise, we should fail with #UD. But most faulting conditions | |
7064 | * have already been checked by hardware, prior to the VM-exit for | |
7065 | * VMXON. We do test guest cr4.VMXE because processor CR4 always has | |
7066 | * that bit set to 1 in non-root mode. | |
ec378aee | 7067 | */ |
70f3aac9 | 7068 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) { |
ec378aee NHE |
7069 | kvm_queue_exception(vcpu, UD_VECTOR); |
7070 | return 1; | |
7071 | } | |
7072 | ||
145c28dd AG |
7073 | if (vmx->nested.vmxon) { |
7074 | nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION); | |
6affcbed | 7075 | return kvm_skip_emulated_instruction(vcpu); |
145c28dd | 7076 | } |
b3897a49 | 7077 | |
3b84080b | 7078 | if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES) |
b3897a49 NHE |
7079 | != VMXON_NEEDED_FEATURES) { |
7080 | kvm_inject_gp(vcpu, 0); | |
7081 | return 1; | |
7082 | } | |
7083 | ||
21e7fbe7 JM |
7084 | if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL)) |
7085 | return 1; | |
e29acc55 JM |
7086 | |
7087 | ret = enter_vmx_operation(vcpu); | |
7088 | if (ret) | |
7089 | return ret; | |
ec378aee | 7090 | |
a25eb114 | 7091 | nested_vmx_succeed(vcpu); |
6affcbed | 7092 | return kvm_skip_emulated_instruction(vcpu); |
ec378aee NHE |
7093 | } |
7094 | ||
7095 | /* | |
7096 | * Intel's VMX Instruction Reference specifies a common set of prerequisites | |
7097 | * for running VMX instructions (except VMXON, whose prerequisites are | |
7098 | * slightly different). It also specifies what exception to inject otherwise. | |
70f3aac9 JM |
7099 | * Note that many of these exceptions have priority over VM exits, so they |
7100 | * don't have to be checked again here. | |
ec378aee NHE |
7101 | */ |
7102 | static int nested_vmx_check_permission(struct kvm_vcpu *vcpu) | |
7103 | { | |
70f3aac9 | 7104 | if (!to_vmx(vcpu)->nested.vmxon) { |
ec378aee NHE |
7105 | kvm_queue_exception(vcpu, UD_VECTOR); |
7106 | return 0; | |
7107 | } | |
ec378aee NHE |
7108 | return 1; |
7109 | } | |
7110 | ||
e7953d7f AG |
7111 | static inline void nested_release_vmcs12(struct vcpu_vmx *vmx) |
7112 | { | |
9a2a05b9 PB |
7113 | if (vmx->nested.current_vmptr == -1ull) |
7114 | return; | |
7115 | ||
7116 | /* current_vmptr and current_vmcs12 are always set/reset together */ | |
7117 | if (WARN_ON(vmx->nested.current_vmcs12 == NULL)) | |
7118 | return; | |
7119 | ||
012f83cb | 7120 | if (enable_shadow_vmcs) { |
9a2a05b9 PB |
7121 | /* copy to memory all shadowed fields in case |
7122 | they were modified */ | |
7123 | copy_shadow_to_vmcs12(vmx); | |
7124 | vmx->nested.sync_shadow_vmcs = false; | |
7ec36296 XG |
7125 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, |
7126 | SECONDARY_EXEC_SHADOW_VMCS); | |
9a2a05b9 | 7127 | vmcs_write64(VMCS_LINK_POINTER, -1ull); |
012f83cb | 7128 | } |
705699a1 | 7129 | vmx->nested.posted_intr_nv = -1; |
4f2777bc DM |
7130 | |
7131 | /* Flush VMCS12 to guest memory */ | |
7132 | memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12, | |
7133 | VMCS12_SIZE); | |
7134 | ||
e7953d7f AG |
7135 | kunmap(vmx->nested.current_vmcs12_page); |
7136 | nested_release_page(vmx->nested.current_vmcs12_page); | |
9a2a05b9 PB |
7137 | vmx->nested.current_vmptr = -1ull; |
7138 | vmx->nested.current_vmcs12 = NULL; | |
e7953d7f AG |
7139 | } |
7140 | ||
ec378aee NHE |
7141 | /* |
7142 | * Free whatever needs to be freed from vmx->nested when L1 goes down, or | |
7143 | * just stops using VMX. | |
7144 | */ | |
7145 | static void free_nested(struct vcpu_vmx *vmx) | |
7146 | { | |
7147 | if (!vmx->nested.vmxon) | |
7148 | return; | |
9a2a05b9 | 7149 | |
ec378aee | 7150 | vmx->nested.vmxon = false; |
5c614b35 | 7151 | free_vpid(vmx->nested.vpid02); |
9a2a05b9 | 7152 | nested_release_vmcs12(vmx); |
d048c098 RK |
7153 | if (vmx->nested.msr_bitmap) { |
7154 | free_page((unsigned long)vmx->nested.msr_bitmap); | |
7155 | vmx->nested.msr_bitmap = NULL; | |
7156 | } | |
355f4fb1 JM |
7157 | if (enable_shadow_vmcs) { |
7158 | vmcs_clear(vmx->vmcs01.shadow_vmcs); | |
7159 | free_vmcs(vmx->vmcs01.shadow_vmcs); | |
7160 | vmx->vmcs01.shadow_vmcs = NULL; | |
7161 | } | |
4f2777bc | 7162 | kfree(vmx->nested.cached_vmcs12); |
fe3ef05c NHE |
7163 | /* Unpin physical memory we referred to in current vmcs02 */ |
7164 | if (vmx->nested.apic_access_page) { | |
7165 | nested_release_page(vmx->nested.apic_access_page); | |
48d89b92 | 7166 | vmx->nested.apic_access_page = NULL; |
fe3ef05c | 7167 | } |
a7c0b07d WL |
7168 | if (vmx->nested.virtual_apic_page) { |
7169 | nested_release_page(vmx->nested.virtual_apic_page); | |
48d89b92 | 7170 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 7171 | } |
705699a1 WV |
7172 | if (vmx->nested.pi_desc_page) { |
7173 | kunmap(vmx->nested.pi_desc_page); | |
7174 | nested_release_page(vmx->nested.pi_desc_page); | |
7175 | vmx->nested.pi_desc_page = NULL; | |
7176 | vmx->nested.pi_desc = NULL; | |
7177 | } | |
ff2f6fe9 NHE |
7178 | |
7179 | nested_free_all_saved_vmcss(vmx); | |
ec378aee NHE |
7180 | } |
7181 | ||
7182 | /* Emulate the VMXOFF instruction */ | |
7183 | static int handle_vmoff(struct kvm_vcpu *vcpu) | |
7184 | { | |
7185 | if (!nested_vmx_check_permission(vcpu)) | |
7186 | return 1; | |
7187 | free_nested(to_vmx(vcpu)); | |
a25eb114 | 7188 | nested_vmx_succeed(vcpu); |
6affcbed | 7189 | return kvm_skip_emulated_instruction(vcpu); |
ec378aee NHE |
7190 | } |
7191 | ||
27d6c865 NHE |
7192 | /* Emulate the VMCLEAR instruction */ |
7193 | static int handle_vmclear(struct kvm_vcpu *vcpu) | |
7194 | { | |
7195 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
587d7e72 | 7196 | u32 zero = 0; |
27d6c865 | 7197 | gpa_t vmptr; |
27d6c865 NHE |
7198 | |
7199 | if (!nested_vmx_check_permission(vcpu)) | |
7200 | return 1; | |
7201 | ||
4291b588 | 7202 | if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr)) |
27d6c865 | 7203 | return 1; |
27d6c865 | 7204 | |
9a2a05b9 | 7205 | if (vmptr == vmx->nested.current_vmptr) |
e7953d7f | 7206 | nested_release_vmcs12(vmx); |
27d6c865 | 7207 | |
587d7e72 JM |
7208 | kvm_vcpu_write_guest(vcpu, |
7209 | vmptr + offsetof(struct vmcs12, launch_state), | |
7210 | &zero, sizeof(zero)); | |
27d6c865 NHE |
7211 | |
7212 | nested_free_vmcs02(vmx, vmptr); | |
7213 | ||
27d6c865 | 7214 | nested_vmx_succeed(vcpu); |
6affcbed | 7215 | return kvm_skip_emulated_instruction(vcpu); |
27d6c865 NHE |
7216 | } |
7217 | ||
cd232ad0 NHE |
7218 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch); |
7219 | ||
7220 | /* Emulate the VMLAUNCH instruction */ | |
7221 | static int handle_vmlaunch(struct kvm_vcpu *vcpu) | |
7222 | { | |
7223 | return nested_vmx_run(vcpu, true); | |
7224 | } | |
7225 | ||
7226 | /* Emulate the VMRESUME instruction */ | |
7227 | static int handle_vmresume(struct kvm_vcpu *vcpu) | |
7228 | { | |
7229 | ||
7230 | return nested_vmx_run(vcpu, false); | |
7231 | } | |
7232 | ||
49f705c5 NHE |
7233 | enum vmcs_field_type { |
7234 | VMCS_FIELD_TYPE_U16 = 0, | |
7235 | VMCS_FIELD_TYPE_U64 = 1, | |
7236 | VMCS_FIELD_TYPE_U32 = 2, | |
7237 | VMCS_FIELD_TYPE_NATURAL_WIDTH = 3 | |
7238 | }; | |
7239 | ||
7240 | static inline int vmcs_field_type(unsigned long field) | |
7241 | { | |
7242 | if (0x1 & field) /* the *_HIGH fields are all 32 bit */ | |
7243 | return VMCS_FIELD_TYPE_U32; | |
7244 | return (field >> 13) & 0x3 ; | |
7245 | } | |
7246 | ||
7247 | static inline int vmcs_field_readonly(unsigned long field) | |
7248 | { | |
7249 | return (((field >> 10) & 0x3) == 1); | |
7250 | } | |
7251 | ||
7252 | /* | |
7253 | * Read a vmcs12 field. Since these can have varying lengths and we return | |
7254 | * one type, we chose the biggest type (u64) and zero-extend the return value | |
7255 | * to that size. Note that the caller, handle_vmread, might need to use only | |
7256 | * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of | |
7257 | * 64-bit fields are to be returned). | |
7258 | */ | |
a2ae9df7 PB |
7259 | static inline int vmcs12_read_any(struct kvm_vcpu *vcpu, |
7260 | unsigned long field, u64 *ret) | |
49f705c5 NHE |
7261 | { |
7262 | short offset = vmcs_field_to_offset(field); | |
7263 | char *p; | |
7264 | ||
7265 | if (offset < 0) | |
a2ae9df7 | 7266 | return offset; |
49f705c5 NHE |
7267 | |
7268 | p = ((char *)(get_vmcs12(vcpu))) + offset; | |
7269 | ||
7270 | switch (vmcs_field_type(field)) { | |
7271 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7272 | *ret = *((natural_width *)p); | |
a2ae9df7 | 7273 | return 0; |
49f705c5 NHE |
7274 | case VMCS_FIELD_TYPE_U16: |
7275 | *ret = *((u16 *)p); | |
a2ae9df7 | 7276 | return 0; |
49f705c5 NHE |
7277 | case VMCS_FIELD_TYPE_U32: |
7278 | *ret = *((u32 *)p); | |
a2ae9df7 | 7279 | return 0; |
49f705c5 NHE |
7280 | case VMCS_FIELD_TYPE_U64: |
7281 | *ret = *((u64 *)p); | |
a2ae9df7 | 7282 | return 0; |
49f705c5 | 7283 | default: |
a2ae9df7 PB |
7284 | WARN_ON(1); |
7285 | return -ENOENT; | |
49f705c5 NHE |
7286 | } |
7287 | } | |
7288 | ||
20b97fea | 7289 | |
a2ae9df7 PB |
7290 | static inline int vmcs12_write_any(struct kvm_vcpu *vcpu, |
7291 | unsigned long field, u64 field_value){ | |
20b97fea AG |
7292 | short offset = vmcs_field_to_offset(field); |
7293 | char *p = ((char *) get_vmcs12(vcpu)) + offset; | |
7294 | if (offset < 0) | |
a2ae9df7 | 7295 | return offset; |
20b97fea AG |
7296 | |
7297 | switch (vmcs_field_type(field)) { | |
7298 | case VMCS_FIELD_TYPE_U16: | |
7299 | *(u16 *)p = field_value; | |
a2ae9df7 | 7300 | return 0; |
20b97fea AG |
7301 | case VMCS_FIELD_TYPE_U32: |
7302 | *(u32 *)p = field_value; | |
a2ae9df7 | 7303 | return 0; |
20b97fea AG |
7304 | case VMCS_FIELD_TYPE_U64: |
7305 | *(u64 *)p = field_value; | |
a2ae9df7 | 7306 | return 0; |
20b97fea AG |
7307 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: |
7308 | *(natural_width *)p = field_value; | |
a2ae9df7 | 7309 | return 0; |
20b97fea | 7310 | default: |
a2ae9df7 PB |
7311 | WARN_ON(1); |
7312 | return -ENOENT; | |
20b97fea AG |
7313 | } |
7314 | ||
7315 | } | |
7316 | ||
16f5b903 AG |
7317 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx) |
7318 | { | |
7319 | int i; | |
7320 | unsigned long field; | |
7321 | u64 field_value; | |
355f4fb1 | 7322 | struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; |
c2bae893 MK |
7323 | const unsigned long *fields = shadow_read_write_fields; |
7324 | const int num_fields = max_shadow_read_write_fields; | |
16f5b903 | 7325 | |
282da870 JK |
7326 | preempt_disable(); |
7327 | ||
16f5b903 AG |
7328 | vmcs_load(shadow_vmcs); |
7329 | ||
7330 | for (i = 0; i < num_fields; i++) { | |
7331 | field = fields[i]; | |
7332 | switch (vmcs_field_type(field)) { | |
7333 | case VMCS_FIELD_TYPE_U16: | |
7334 | field_value = vmcs_read16(field); | |
7335 | break; | |
7336 | case VMCS_FIELD_TYPE_U32: | |
7337 | field_value = vmcs_read32(field); | |
7338 | break; | |
7339 | case VMCS_FIELD_TYPE_U64: | |
7340 | field_value = vmcs_read64(field); | |
7341 | break; | |
7342 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7343 | field_value = vmcs_readl(field); | |
7344 | break; | |
a2ae9df7 PB |
7345 | default: |
7346 | WARN_ON(1); | |
7347 | continue; | |
16f5b903 AG |
7348 | } |
7349 | vmcs12_write_any(&vmx->vcpu, field, field_value); | |
7350 | } | |
7351 | ||
7352 | vmcs_clear(shadow_vmcs); | |
7353 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
282da870 JK |
7354 | |
7355 | preempt_enable(); | |
16f5b903 AG |
7356 | } |
7357 | ||
c3114420 AG |
7358 | static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx) |
7359 | { | |
c2bae893 MK |
7360 | const unsigned long *fields[] = { |
7361 | shadow_read_write_fields, | |
7362 | shadow_read_only_fields | |
c3114420 | 7363 | }; |
c2bae893 | 7364 | const int max_fields[] = { |
c3114420 AG |
7365 | max_shadow_read_write_fields, |
7366 | max_shadow_read_only_fields | |
7367 | }; | |
7368 | int i, q; | |
7369 | unsigned long field; | |
7370 | u64 field_value = 0; | |
355f4fb1 | 7371 | struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; |
c3114420 AG |
7372 | |
7373 | vmcs_load(shadow_vmcs); | |
7374 | ||
c2bae893 | 7375 | for (q = 0; q < ARRAY_SIZE(fields); q++) { |
c3114420 AG |
7376 | for (i = 0; i < max_fields[q]; i++) { |
7377 | field = fields[q][i]; | |
7378 | vmcs12_read_any(&vmx->vcpu, field, &field_value); | |
7379 | ||
7380 | switch (vmcs_field_type(field)) { | |
7381 | case VMCS_FIELD_TYPE_U16: | |
7382 | vmcs_write16(field, (u16)field_value); | |
7383 | break; | |
7384 | case VMCS_FIELD_TYPE_U32: | |
7385 | vmcs_write32(field, (u32)field_value); | |
7386 | break; | |
7387 | case VMCS_FIELD_TYPE_U64: | |
7388 | vmcs_write64(field, (u64)field_value); | |
7389 | break; | |
7390 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7391 | vmcs_writel(field, (long)field_value); | |
7392 | break; | |
a2ae9df7 PB |
7393 | default: |
7394 | WARN_ON(1); | |
7395 | break; | |
c3114420 AG |
7396 | } |
7397 | } | |
7398 | } | |
7399 | ||
7400 | vmcs_clear(shadow_vmcs); | |
7401 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
7402 | } | |
7403 | ||
49f705c5 NHE |
7404 | /* |
7405 | * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was | |
7406 | * used before) all generate the same failure when it is missing. | |
7407 | */ | |
7408 | static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu) | |
7409 | { | |
7410 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7411 | if (vmx->nested.current_vmptr == -1ull) { | |
7412 | nested_vmx_failInvalid(vcpu); | |
49f705c5 NHE |
7413 | return 0; |
7414 | } | |
7415 | return 1; | |
7416 | } | |
7417 | ||
7418 | static int handle_vmread(struct kvm_vcpu *vcpu) | |
7419 | { | |
7420 | unsigned long field; | |
7421 | u64 field_value; | |
7422 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7423 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7424 | gva_t gva = 0; | |
7425 | ||
eb277562 | 7426 | if (!nested_vmx_check_permission(vcpu)) |
49f705c5 NHE |
7427 | return 1; |
7428 | ||
6affcbed KH |
7429 | if (!nested_vmx_check_vmcs12(vcpu)) |
7430 | return kvm_skip_emulated_instruction(vcpu); | |
49f705c5 NHE |
7431 | |
7432 | /* Decode instruction info and find the field to read */ | |
27e6fb5d | 7433 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 | 7434 | /* Read the field, zero-extended to a u64 field_value */ |
a2ae9df7 | 7435 | if (vmcs12_read_any(vcpu, field, &field_value) < 0) { |
49f705c5 | 7436 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
6affcbed | 7437 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7438 | } |
7439 | /* | |
7440 | * Now copy part of this value to register or memory, as requested. | |
7441 | * Note that the number of bits actually copied is 32 or 64 depending | |
7442 | * on the guest's mode (32 or 64 bit), not on the given field's length. | |
7443 | */ | |
7444 | if (vmx_instruction_info & (1u << 10)) { | |
27e6fb5d | 7445 | kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf), |
49f705c5 NHE |
7446 | field_value); |
7447 | } else { | |
7448 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7449 | vmx_instruction_info, true, &gva)) |
49f705c5 | 7450 | return 1; |
70f3aac9 | 7451 | /* _system ok, as hardware has verified cpl=0 */ |
49f705c5 NHE |
7452 | kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva, |
7453 | &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL); | |
7454 | } | |
7455 | ||
7456 | nested_vmx_succeed(vcpu); | |
6affcbed | 7457 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7458 | } |
7459 | ||
7460 | ||
7461 | static int handle_vmwrite(struct kvm_vcpu *vcpu) | |
7462 | { | |
7463 | unsigned long field; | |
7464 | gva_t gva; | |
7465 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7466 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
49f705c5 NHE |
7467 | /* The value to write might be 32 or 64 bits, depending on L1's long |
7468 | * mode, and eventually we need to write that into a field of several | |
7469 | * possible lengths. The code below first zero-extends the value to 64 | |
6a6256f9 | 7470 | * bit (field_value), and then copies only the appropriate number of |
49f705c5 NHE |
7471 | * bits into the vmcs12 field. |
7472 | */ | |
7473 | u64 field_value = 0; | |
7474 | struct x86_exception e; | |
7475 | ||
eb277562 | 7476 | if (!nested_vmx_check_permission(vcpu)) |
49f705c5 NHE |
7477 | return 1; |
7478 | ||
6affcbed KH |
7479 | if (!nested_vmx_check_vmcs12(vcpu)) |
7480 | return kvm_skip_emulated_instruction(vcpu); | |
eb277562 | 7481 | |
49f705c5 | 7482 | if (vmx_instruction_info & (1u << 10)) |
27e6fb5d | 7483 | field_value = kvm_register_readl(vcpu, |
49f705c5 NHE |
7484 | (((vmx_instruction_info) >> 3) & 0xf)); |
7485 | else { | |
7486 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7487 | vmx_instruction_info, false, &gva)) |
49f705c5 NHE |
7488 | return 1; |
7489 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, | |
27e6fb5d | 7490 | &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) { |
49f705c5 NHE |
7491 | kvm_inject_page_fault(vcpu, &e); |
7492 | return 1; | |
7493 | } | |
7494 | } | |
7495 | ||
7496 | ||
27e6fb5d | 7497 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 NHE |
7498 | if (vmcs_field_readonly(field)) { |
7499 | nested_vmx_failValid(vcpu, | |
7500 | VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT); | |
6affcbed | 7501 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7502 | } |
7503 | ||
a2ae9df7 | 7504 | if (vmcs12_write_any(vcpu, field, field_value) < 0) { |
49f705c5 | 7505 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
6affcbed | 7506 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7507 | } |
7508 | ||
7509 | nested_vmx_succeed(vcpu); | |
6affcbed | 7510 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7511 | } |
7512 | ||
a8bc284e JM |
7513 | static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr) |
7514 | { | |
7515 | vmx->nested.current_vmptr = vmptr; | |
7516 | if (enable_shadow_vmcs) { | |
7517 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
7518 | SECONDARY_EXEC_SHADOW_VMCS); | |
7519 | vmcs_write64(VMCS_LINK_POINTER, | |
7520 | __pa(vmx->vmcs01.shadow_vmcs)); | |
7521 | vmx->nested.sync_shadow_vmcs = true; | |
7522 | } | |
7523 | } | |
7524 | ||
63846663 NHE |
7525 | /* Emulate the VMPTRLD instruction */ |
7526 | static int handle_vmptrld(struct kvm_vcpu *vcpu) | |
7527 | { | |
7528 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
63846663 | 7529 | gpa_t vmptr; |
63846663 NHE |
7530 | |
7531 | if (!nested_vmx_check_permission(vcpu)) | |
7532 | return 1; | |
7533 | ||
4291b588 | 7534 | if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr)) |
63846663 | 7535 | return 1; |
63846663 NHE |
7536 | |
7537 | if (vmx->nested.current_vmptr != vmptr) { | |
7538 | struct vmcs12 *new_vmcs12; | |
7539 | struct page *page; | |
7540 | page = nested_get_page(vcpu, vmptr); | |
7541 | if (page == NULL) { | |
7542 | nested_vmx_failInvalid(vcpu); | |
6affcbed | 7543 | return kvm_skip_emulated_instruction(vcpu); |
63846663 NHE |
7544 | } |
7545 | new_vmcs12 = kmap(page); | |
7546 | if (new_vmcs12->revision_id != VMCS12_REVISION) { | |
7547 | kunmap(page); | |
7548 | nested_release_page_clean(page); | |
7549 | nested_vmx_failValid(vcpu, | |
7550 | VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID); | |
6affcbed | 7551 | return kvm_skip_emulated_instruction(vcpu); |
63846663 | 7552 | } |
63846663 | 7553 | |
9a2a05b9 | 7554 | nested_release_vmcs12(vmx); |
63846663 NHE |
7555 | vmx->nested.current_vmcs12 = new_vmcs12; |
7556 | vmx->nested.current_vmcs12_page = page; | |
4f2777bc DM |
7557 | /* |
7558 | * Load VMCS12 from guest memory since it is not already | |
7559 | * cached. | |
7560 | */ | |
7561 | memcpy(vmx->nested.cached_vmcs12, | |
7562 | vmx->nested.current_vmcs12, VMCS12_SIZE); | |
a8bc284e | 7563 | set_current_vmptr(vmx, vmptr); |
63846663 NHE |
7564 | } |
7565 | ||
7566 | nested_vmx_succeed(vcpu); | |
6affcbed | 7567 | return kvm_skip_emulated_instruction(vcpu); |
63846663 NHE |
7568 | } |
7569 | ||
6a4d7550 NHE |
7570 | /* Emulate the VMPTRST instruction */ |
7571 | static int handle_vmptrst(struct kvm_vcpu *vcpu) | |
7572 | { | |
7573 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7574 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7575 | gva_t vmcs_gva; | |
7576 | struct x86_exception e; | |
7577 | ||
7578 | if (!nested_vmx_check_permission(vcpu)) | |
7579 | return 1; | |
7580 | ||
7581 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7582 | vmx_instruction_info, true, &vmcs_gva)) |
6a4d7550 | 7583 | return 1; |
70f3aac9 | 7584 | /* ok to use *_system, as hardware has verified cpl=0 */ |
6a4d7550 NHE |
7585 | if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva, |
7586 | (void *)&to_vmx(vcpu)->nested.current_vmptr, | |
7587 | sizeof(u64), &e)) { | |
7588 | kvm_inject_page_fault(vcpu, &e); | |
7589 | return 1; | |
7590 | } | |
7591 | nested_vmx_succeed(vcpu); | |
6affcbed | 7592 | return kvm_skip_emulated_instruction(vcpu); |
6a4d7550 NHE |
7593 | } |
7594 | ||
bfd0a56b NHE |
7595 | /* Emulate the INVEPT instruction */ |
7596 | static int handle_invept(struct kvm_vcpu *vcpu) | |
7597 | { | |
b9c237bb | 7598 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
bfd0a56b NHE |
7599 | u32 vmx_instruction_info, types; |
7600 | unsigned long type; | |
7601 | gva_t gva; | |
7602 | struct x86_exception e; | |
7603 | struct { | |
7604 | u64 eptp, gpa; | |
7605 | } operand; | |
bfd0a56b | 7606 | |
b9c237bb WV |
7607 | if (!(vmx->nested.nested_vmx_secondary_ctls_high & |
7608 | SECONDARY_EXEC_ENABLE_EPT) || | |
7609 | !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) { | |
bfd0a56b NHE |
7610 | kvm_queue_exception(vcpu, UD_VECTOR); |
7611 | return 1; | |
7612 | } | |
7613 | ||
7614 | if (!nested_vmx_check_permission(vcpu)) | |
7615 | return 1; | |
7616 | ||
bfd0a56b | 7617 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); |
27e6fb5d | 7618 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); |
bfd0a56b | 7619 | |
b9c237bb | 7620 | types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6; |
bfd0a56b | 7621 | |
85c856b3 | 7622 | if (type >= 32 || !(types & (1 << type))) { |
bfd0a56b NHE |
7623 | nested_vmx_failValid(vcpu, |
7624 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 7625 | return kvm_skip_emulated_instruction(vcpu); |
bfd0a56b NHE |
7626 | } |
7627 | ||
7628 | /* According to the Intel VMX instruction reference, the memory | |
7629 | * operand is read even if it isn't needed (e.g., for type==global) | |
7630 | */ | |
7631 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
f9eb4af6 | 7632 | vmx_instruction_info, false, &gva)) |
bfd0a56b NHE |
7633 | return 1; |
7634 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand, | |
7635 | sizeof(operand), &e)) { | |
7636 | kvm_inject_page_fault(vcpu, &e); | |
7637 | return 1; | |
7638 | } | |
7639 | ||
7640 | switch (type) { | |
bfd0a56b | 7641 | case VMX_EPT_EXTENT_GLOBAL: |
45e11817 BD |
7642 | /* |
7643 | * TODO: track mappings and invalidate | |
7644 | * single context requests appropriately | |
7645 | */ | |
7646 | case VMX_EPT_EXTENT_CONTEXT: | |
bfd0a56b | 7647 | kvm_mmu_sync_roots(vcpu); |
77c3913b | 7648 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
bfd0a56b NHE |
7649 | nested_vmx_succeed(vcpu); |
7650 | break; | |
7651 | default: | |
7652 | BUG_ON(1); | |
7653 | break; | |
7654 | } | |
7655 | ||
6affcbed | 7656 | return kvm_skip_emulated_instruction(vcpu); |
bfd0a56b NHE |
7657 | } |
7658 | ||
a642fc30 PM |
7659 | static int handle_invvpid(struct kvm_vcpu *vcpu) |
7660 | { | |
99b83ac8 WL |
7661 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
7662 | u32 vmx_instruction_info; | |
7663 | unsigned long type, types; | |
7664 | gva_t gva; | |
7665 | struct x86_exception e; | |
7666 | int vpid; | |
7667 | ||
7668 | if (!(vmx->nested.nested_vmx_secondary_ctls_high & | |
7669 | SECONDARY_EXEC_ENABLE_VPID) || | |
7670 | !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) { | |
7671 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7672 | return 1; | |
7673 | } | |
7674 | ||
7675 | if (!nested_vmx_check_permission(vcpu)) | |
7676 | return 1; | |
7677 | ||
7678 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7679 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); | |
7680 | ||
bcdde302 JD |
7681 | types = (vmx->nested.nested_vmx_vpid_caps & |
7682 | VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8; | |
99b83ac8 | 7683 | |
85c856b3 | 7684 | if (type >= 32 || !(types & (1 << type))) { |
99b83ac8 WL |
7685 | nested_vmx_failValid(vcpu, |
7686 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 7687 | return kvm_skip_emulated_instruction(vcpu); |
99b83ac8 WL |
7688 | } |
7689 | ||
7690 | /* according to the intel vmx instruction reference, the memory | |
7691 | * operand is read even if it isn't needed (e.g., for type==global) | |
7692 | */ | |
7693 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
7694 | vmx_instruction_info, false, &gva)) | |
7695 | return 1; | |
7696 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid, | |
7697 | sizeof(u32), &e)) { | |
7698 | kvm_inject_page_fault(vcpu, &e); | |
7699 | return 1; | |
7700 | } | |
7701 | ||
7702 | switch (type) { | |
bcdde302 | 7703 | case VMX_VPID_EXTENT_INDIVIDUAL_ADDR: |
ef697a71 | 7704 | case VMX_VPID_EXTENT_SINGLE_CONTEXT: |
bcdde302 JD |
7705 | case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL: |
7706 | if (!vpid) { | |
7707 | nested_vmx_failValid(vcpu, | |
7708 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 7709 | return kvm_skip_emulated_instruction(vcpu); |
bcdde302 JD |
7710 | } |
7711 | break; | |
99b83ac8 | 7712 | case VMX_VPID_EXTENT_ALL_CONTEXT: |
99b83ac8 WL |
7713 | break; |
7714 | default: | |
bcdde302 | 7715 | WARN_ON_ONCE(1); |
6affcbed | 7716 | return kvm_skip_emulated_instruction(vcpu); |
99b83ac8 WL |
7717 | } |
7718 | ||
bcdde302 JD |
7719 | __vmx_flush_tlb(vcpu, vmx->nested.vpid02); |
7720 | nested_vmx_succeed(vcpu); | |
7721 | ||
6affcbed | 7722 | return kvm_skip_emulated_instruction(vcpu); |
a642fc30 PM |
7723 | } |
7724 | ||
843e4330 KH |
7725 | static int handle_pml_full(struct kvm_vcpu *vcpu) |
7726 | { | |
7727 | unsigned long exit_qualification; | |
7728 | ||
7729 | trace_kvm_pml_full(vcpu->vcpu_id); | |
7730 | ||
7731 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7732 | ||
7733 | /* | |
7734 | * PML buffer FULL happened while executing iret from NMI, | |
7735 | * "blocked by NMI" bit has to be set before next VM entry. | |
7736 | */ | |
7737 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && | |
843e4330 KH |
7738 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) |
7739 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
7740 | GUEST_INTR_STATE_NMI); | |
7741 | ||
7742 | /* | |
7743 | * PML buffer already flushed at beginning of VMEXIT. Nothing to do | |
7744 | * here.., and there's no userspace involvement needed for PML. | |
7745 | */ | |
7746 | return 1; | |
7747 | } | |
7748 | ||
64672c95 YJ |
7749 | static int handle_preemption_timer(struct kvm_vcpu *vcpu) |
7750 | { | |
7751 | kvm_lapic_expired_hv_timer(vcpu); | |
7752 | return 1; | |
7753 | } | |
7754 | ||
6aa8b732 AK |
7755 | /* |
7756 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
7757 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
7758 | * to be done to userspace and return 0. | |
7759 | */ | |
772e0318 | 7760 | static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { |
6aa8b732 AK |
7761 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, |
7762 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 7763 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
f08864b4 | 7764 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, |
6aa8b732 | 7765 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
7766 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
7767 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
7768 | [EXIT_REASON_CPUID] = handle_cpuid, | |
7769 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
7770 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
7771 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
7772 | [EXIT_REASON_HLT] = handle_halt, | |
ec25d5e6 | 7773 | [EXIT_REASON_INVD] = handle_invd, |
a7052897 | 7774 | [EXIT_REASON_INVLPG] = handle_invlpg, |
fee84b07 | 7775 | [EXIT_REASON_RDPMC] = handle_rdpmc, |
c21415e8 | 7776 | [EXIT_REASON_VMCALL] = handle_vmcall, |
27d6c865 | 7777 | [EXIT_REASON_VMCLEAR] = handle_vmclear, |
cd232ad0 | 7778 | [EXIT_REASON_VMLAUNCH] = handle_vmlaunch, |
63846663 | 7779 | [EXIT_REASON_VMPTRLD] = handle_vmptrld, |
6a4d7550 | 7780 | [EXIT_REASON_VMPTRST] = handle_vmptrst, |
49f705c5 | 7781 | [EXIT_REASON_VMREAD] = handle_vmread, |
cd232ad0 | 7782 | [EXIT_REASON_VMRESUME] = handle_vmresume, |
49f705c5 | 7783 | [EXIT_REASON_VMWRITE] = handle_vmwrite, |
ec378aee NHE |
7784 | [EXIT_REASON_VMOFF] = handle_vmoff, |
7785 | [EXIT_REASON_VMON] = handle_vmon, | |
f78e0e2e SY |
7786 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
7787 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
83d4c286 | 7788 | [EXIT_REASON_APIC_WRITE] = handle_apic_write, |
c7c9c56c | 7789 | [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, |
e5edaa01 | 7790 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
2acf923e | 7791 | [EXIT_REASON_XSETBV] = handle_xsetbv, |
37817f29 | 7792 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
a0861c02 | 7793 | [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, |
68f89400 MT |
7794 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
7795 | [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, | |
4b8d54f9 | 7796 | [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, |
87c00572 | 7797 | [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, |
5f3d45e7 | 7798 | [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, |
87c00572 | 7799 | [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, |
bfd0a56b | 7800 | [EXIT_REASON_INVEPT] = handle_invept, |
a642fc30 | 7801 | [EXIT_REASON_INVVPID] = handle_invvpid, |
f53cd63c WL |
7802 | [EXIT_REASON_XSAVES] = handle_xsaves, |
7803 | [EXIT_REASON_XRSTORS] = handle_xrstors, | |
843e4330 | 7804 | [EXIT_REASON_PML_FULL] = handle_pml_full, |
64672c95 | 7805 | [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, |
6aa8b732 AK |
7806 | }; |
7807 | ||
7808 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 7809 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 | 7810 | |
908a7bdd JK |
7811 | static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu, |
7812 | struct vmcs12 *vmcs12) | |
7813 | { | |
7814 | unsigned long exit_qualification; | |
7815 | gpa_t bitmap, last_bitmap; | |
7816 | unsigned int port; | |
7817 | int size; | |
7818 | u8 b; | |
7819 | ||
908a7bdd | 7820 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) |
2f0a6397 | 7821 | return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING); |
908a7bdd JK |
7822 | |
7823 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7824 | ||
7825 | port = exit_qualification >> 16; | |
7826 | size = (exit_qualification & 7) + 1; | |
7827 | ||
7828 | last_bitmap = (gpa_t)-1; | |
7829 | b = -1; | |
7830 | ||
7831 | while (size > 0) { | |
7832 | if (port < 0x8000) | |
7833 | bitmap = vmcs12->io_bitmap_a; | |
7834 | else if (port < 0x10000) | |
7835 | bitmap = vmcs12->io_bitmap_b; | |
7836 | else | |
1d804d07 | 7837 | return true; |
908a7bdd JK |
7838 | bitmap += (port & 0x7fff) / 8; |
7839 | ||
7840 | if (last_bitmap != bitmap) | |
54bf36aa | 7841 | if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1)) |
1d804d07 | 7842 | return true; |
908a7bdd | 7843 | if (b & (1 << (port & 7))) |
1d804d07 | 7844 | return true; |
908a7bdd JK |
7845 | |
7846 | port++; | |
7847 | size--; | |
7848 | last_bitmap = bitmap; | |
7849 | } | |
7850 | ||
1d804d07 | 7851 | return false; |
908a7bdd JK |
7852 | } |
7853 | ||
644d711a NHE |
7854 | /* |
7855 | * Return 1 if we should exit from L2 to L1 to handle an MSR access access, | |
7856 | * rather than handle it ourselves in L0. I.e., check whether L1 expressed | |
7857 | * disinterest in the current event (read or write a specific MSR) by using an | |
7858 | * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps. | |
7859 | */ | |
7860 | static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu, | |
7861 | struct vmcs12 *vmcs12, u32 exit_reason) | |
7862 | { | |
7863 | u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX]; | |
7864 | gpa_t bitmap; | |
7865 | ||
cbd29cb6 | 7866 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) |
1d804d07 | 7867 | return true; |
644d711a NHE |
7868 | |
7869 | /* | |
7870 | * The MSR_BITMAP page is divided into four 1024-byte bitmaps, | |
7871 | * for the four combinations of read/write and low/high MSR numbers. | |
7872 | * First we need to figure out which of the four to use: | |
7873 | */ | |
7874 | bitmap = vmcs12->msr_bitmap; | |
7875 | if (exit_reason == EXIT_REASON_MSR_WRITE) | |
7876 | bitmap += 2048; | |
7877 | if (msr_index >= 0xc0000000) { | |
7878 | msr_index -= 0xc0000000; | |
7879 | bitmap += 1024; | |
7880 | } | |
7881 | ||
7882 | /* Then read the msr_index'th bit from this bitmap: */ | |
7883 | if (msr_index < 1024*8) { | |
7884 | unsigned char b; | |
54bf36aa | 7885 | if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1)) |
1d804d07 | 7886 | return true; |
644d711a NHE |
7887 | return 1 & (b >> (msr_index & 7)); |
7888 | } else | |
1d804d07 | 7889 | return true; /* let L1 handle the wrong parameter */ |
644d711a NHE |
7890 | } |
7891 | ||
7892 | /* | |
7893 | * Return 1 if we should exit from L2 to L1 to handle a CR access exit, | |
7894 | * rather than handle it ourselves in L0. I.e., check if L1 wanted to | |
7895 | * intercept (via guest_host_mask etc.) the current event. | |
7896 | */ | |
7897 | static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu, | |
7898 | struct vmcs12 *vmcs12) | |
7899 | { | |
7900 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7901 | int cr = exit_qualification & 15; | |
7902 | int reg = (exit_qualification >> 8) & 15; | |
1e32c079 | 7903 | unsigned long val = kvm_register_readl(vcpu, reg); |
644d711a NHE |
7904 | |
7905 | switch ((exit_qualification >> 4) & 3) { | |
7906 | case 0: /* mov to cr */ | |
7907 | switch (cr) { | |
7908 | case 0: | |
7909 | if (vmcs12->cr0_guest_host_mask & | |
7910 | (val ^ vmcs12->cr0_read_shadow)) | |
1d804d07 | 7911 | return true; |
644d711a NHE |
7912 | break; |
7913 | case 3: | |
7914 | if ((vmcs12->cr3_target_count >= 1 && | |
7915 | vmcs12->cr3_target_value0 == val) || | |
7916 | (vmcs12->cr3_target_count >= 2 && | |
7917 | vmcs12->cr3_target_value1 == val) || | |
7918 | (vmcs12->cr3_target_count >= 3 && | |
7919 | vmcs12->cr3_target_value2 == val) || | |
7920 | (vmcs12->cr3_target_count >= 4 && | |
7921 | vmcs12->cr3_target_value3 == val)) | |
1d804d07 | 7922 | return false; |
644d711a | 7923 | if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING)) |
1d804d07 | 7924 | return true; |
644d711a NHE |
7925 | break; |
7926 | case 4: | |
7927 | if (vmcs12->cr4_guest_host_mask & | |
7928 | (vmcs12->cr4_read_shadow ^ val)) | |
1d804d07 | 7929 | return true; |
644d711a NHE |
7930 | break; |
7931 | case 8: | |
7932 | if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING)) | |
1d804d07 | 7933 | return true; |
644d711a NHE |
7934 | break; |
7935 | } | |
7936 | break; | |
7937 | case 2: /* clts */ | |
7938 | if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) && | |
7939 | (vmcs12->cr0_read_shadow & X86_CR0_TS)) | |
1d804d07 | 7940 | return true; |
644d711a NHE |
7941 | break; |
7942 | case 1: /* mov from cr */ | |
7943 | switch (cr) { | |
7944 | case 3: | |
7945 | if (vmcs12->cpu_based_vm_exec_control & | |
7946 | CPU_BASED_CR3_STORE_EXITING) | |
1d804d07 | 7947 | return true; |
644d711a NHE |
7948 | break; |
7949 | case 8: | |
7950 | if (vmcs12->cpu_based_vm_exec_control & | |
7951 | CPU_BASED_CR8_STORE_EXITING) | |
1d804d07 | 7952 | return true; |
644d711a NHE |
7953 | break; |
7954 | } | |
7955 | break; | |
7956 | case 3: /* lmsw */ | |
7957 | /* | |
7958 | * lmsw can change bits 1..3 of cr0, and only set bit 0 of | |
7959 | * cr0. Other attempted changes are ignored, with no exit. | |
7960 | */ | |
7961 | if (vmcs12->cr0_guest_host_mask & 0xe & | |
7962 | (val ^ vmcs12->cr0_read_shadow)) | |
1d804d07 | 7963 | return true; |
644d711a NHE |
7964 | if ((vmcs12->cr0_guest_host_mask & 0x1) && |
7965 | !(vmcs12->cr0_read_shadow & 0x1) && | |
7966 | (val & 0x1)) | |
1d804d07 | 7967 | return true; |
644d711a NHE |
7968 | break; |
7969 | } | |
1d804d07 | 7970 | return false; |
644d711a NHE |
7971 | } |
7972 | ||
7973 | /* | |
7974 | * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we | |
7975 | * should handle it ourselves in L0 (and then continue L2). Only call this | |
7976 | * when in is_guest_mode (L2). | |
7977 | */ | |
7978 | static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu) | |
7979 | { | |
644d711a NHE |
7980 | u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
7981 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7982 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
957c897e | 7983 | u32 exit_reason = vmx->exit_reason; |
644d711a | 7984 | |
542060ea JK |
7985 | trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason, |
7986 | vmcs_readl(EXIT_QUALIFICATION), | |
7987 | vmx->idt_vectoring_info, | |
7988 | intr_info, | |
7989 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
7990 | KVM_ISA_VMX); | |
7991 | ||
644d711a | 7992 | if (vmx->nested.nested_run_pending) |
1d804d07 | 7993 | return false; |
644d711a NHE |
7994 | |
7995 | if (unlikely(vmx->fail)) { | |
bd80158a JK |
7996 | pr_info_ratelimited("%s failed vm entry %x\n", __func__, |
7997 | vmcs_read32(VM_INSTRUCTION_ERROR)); | |
1d804d07 | 7998 | return true; |
644d711a NHE |
7999 | } |
8000 | ||
8001 | switch (exit_reason) { | |
8002 | case EXIT_REASON_EXCEPTION_NMI: | |
ef85b673 | 8003 | if (is_nmi(intr_info)) |
1d804d07 | 8004 | return false; |
644d711a NHE |
8005 | else if (is_page_fault(intr_info)) |
8006 | return enable_ept; | |
e504c909 | 8007 | else if (is_no_device(intr_info) && |
ccf9844e | 8008 | !(vmcs12->guest_cr0 & X86_CR0_TS)) |
1d804d07 | 8009 | return false; |
6f05485d JK |
8010 | else if (is_debug(intr_info) && |
8011 | vcpu->guest_debug & | |
8012 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
8013 | return false; | |
8014 | else if (is_breakpoint(intr_info) && | |
8015 | vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) | |
8016 | return false; | |
644d711a NHE |
8017 | return vmcs12->exception_bitmap & |
8018 | (1u << (intr_info & INTR_INFO_VECTOR_MASK)); | |
8019 | case EXIT_REASON_EXTERNAL_INTERRUPT: | |
1d804d07 | 8020 | return false; |
644d711a | 8021 | case EXIT_REASON_TRIPLE_FAULT: |
1d804d07 | 8022 | return true; |
644d711a | 8023 | case EXIT_REASON_PENDING_INTERRUPT: |
3b656cf7 | 8024 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING); |
644d711a | 8025 | case EXIT_REASON_NMI_WINDOW: |
3b656cf7 | 8026 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING); |
644d711a | 8027 | case EXIT_REASON_TASK_SWITCH: |
1d804d07 | 8028 | return true; |
644d711a | 8029 | case EXIT_REASON_CPUID: |
1d804d07 | 8030 | return true; |
644d711a NHE |
8031 | case EXIT_REASON_HLT: |
8032 | return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING); | |
8033 | case EXIT_REASON_INVD: | |
1d804d07 | 8034 | return true; |
644d711a NHE |
8035 | case EXIT_REASON_INVLPG: |
8036 | return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); | |
8037 | case EXIT_REASON_RDPMC: | |
8038 | return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING); | |
a5f46457 PB |
8039 | case EXIT_REASON_RDRAND: |
8040 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND); | |
8041 | case EXIT_REASON_RDSEED: | |
8042 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED); | |
b3a2a907 | 8043 | case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP: |
644d711a NHE |
8044 | return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING); |
8045 | case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR: | |
8046 | case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD: | |
8047 | case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD: | |
8048 | case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE: | |
8049 | case EXIT_REASON_VMOFF: case EXIT_REASON_VMON: | |
a642fc30 | 8050 | case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID: |
644d711a NHE |
8051 | /* |
8052 | * VMX instructions trap unconditionally. This allows L1 to | |
8053 | * emulate them for its L2 guest, i.e., allows 3-level nesting! | |
8054 | */ | |
1d804d07 | 8055 | return true; |
644d711a NHE |
8056 | case EXIT_REASON_CR_ACCESS: |
8057 | return nested_vmx_exit_handled_cr(vcpu, vmcs12); | |
8058 | case EXIT_REASON_DR_ACCESS: | |
8059 | return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING); | |
8060 | case EXIT_REASON_IO_INSTRUCTION: | |
908a7bdd | 8061 | return nested_vmx_exit_handled_io(vcpu, vmcs12); |
1b07304c PB |
8062 | case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR: |
8063 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC); | |
644d711a NHE |
8064 | case EXIT_REASON_MSR_READ: |
8065 | case EXIT_REASON_MSR_WRITE: | |
8066 | return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason); | |
8067 | case EXIT_REASON_INVALID_STATE: | |
1d804d07 | 8068 | return true; |
644d711a NHE |
8069 | case EXIT_REASON_MWAIT_INSTRUCTION: |
8070 | return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING); | |
5f3d45e7 MD |
8071 | case EXIT_REASON_MONITOR_TRAP_FLAG: |
8072 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG); | |
644d711a NHE |
8073 | case EXIT_REASON_MONITOR_INSTRUCTION: |
8074 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING); | |
8075 | case EXIT_REASON_PAUSE_INSTRUCTION: | |
8076 | return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) || | |
8077 | nested_cpu_has2(vmcs12, | |
8078 | SECONDARY_EXEC_PAUSE_LOOP_EXITING); | |
8079 | case EXIT_REASON_MCE_DURING_VMENTRY: | |
1d804d07 | 8080 | return false; |
644d711a | 8081 | case EXIT_REASON_TPR_BELOW_THRESHOLD: |
a7c0b07d | 8082 | return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW); |
644d711a NHE |
8083 | case EXIT_REASON_APIC_ACCESS: |
8084 | return nested_cpu_has2(vmcs12, | |
8085 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
82f0dd4b | 8086 | case EXIT_REASON_APIC_WRITE: |
608406e2 WV |
8087 | case EXIT_REASON_EOI_INDUCED: |
8088 | /* apic_write and eoi_induced should exit unconditionally. */ | |
1d804d07 | 8089 | return true; |
644d711a | 8090 | case EXIT_REASON_EPT_VIOLATION: |
2b1be677 NHE |
8091 | /* |
8092 | * L0 always deals with the EPT violation. If nested EPT is | |
8093 | * used, and the nested mmu code discovers that the address is | |
8094 | * missing in the guest EPT table (EPT12), the EPT violation | |
8095 | * will be injected with nested_ept_inject_page_fault() | |
8096 | */ | |
1d804d07 | 8097 | return false; |
644d711a | 8098 | case EXIT_REASON_EPT_MISCONFIG: |
2b1be677 NHE |
8099 | /* |
8100 | * L2 never uses directly L1's EPT, but rather L0's own EPT | |
8101 | * table (shadow on EPT) or a merged EPT table that L0 built | |
8102 | * (EPT on EPT). So any problems with the structure of the | |
8103 | * table is L0's fault. | |
8104 | */ | |
1d804d07 | 8105 | return false; |
644d711a NHE |
8106 | case EXIT_REASON_WBINVD: |
8107 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING); | |
8108 | case EXIT_REASON_XSETBV: | |
1d804d07 | 8109 | return true; |
81dc01f7 WL |
8110 | case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS: |
8111 | /* | |
8112 | * This should never happen, since it is not possible to | |
8113 | * set XSS to a non-zero value---neither in L1 nor in L2. | |
8114 | * If if it were, XSS would have to be checked against | |
8115 | * the XSS exit bitmap in vmcs12. | |
8116 | */ | |
8117 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES); | |
55123e3c WL |
8118 | case EXIT_REASON_PREEMPTION_TIMER: |
8119 | return false; | |
644d711a | 8120 | default: |
1d804d07 | 8121 | return true; |
644d711a NHE |
8122 | } |
8123 | } | |
8124 | ||
586f9607 AK |
8125 | static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
8126 | { | |
8127 | *info1 = vmcs_readl(EXIT_QUALIFICATION); | |
8128 | *info2 = vmcs_read32(VM_EXIT_INTR_INFO); | |
8129 | } | |
8130 | ||
a3eaa864 | 8131 | static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) |
843e4330 | 8132 | { |
a3eaa864 KH |
8133 | if (vmx->pml_pg) { |
8134 | __free_page(vmx->pml_pg); | |
8135 | vmx->pml_pg = NULL; | |
8136 | } | |
843e4330 KH |
8137 | } |
8138 | ||
54bf36aa | 8139 | static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) |
843e4330 | 8140 | { |
54bf36aa | 8141 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
843e4330 KH |
8142 | u64 *pml_buf; |
8143 | u16 pml_idx; | |
8144 | ||
8145 | pml_idx = vmcs_read16(GUEST_PML_INDEX); | |
8146 | ||
8147 | /* Do nothing if PML buffer is empty */ | |
8148 | if (pml_idx == (PML_ENTITY_NUM - 1)) | |
8149 | return; | |
8150 | ||
8151 | /* PML index always points to next available PML buffer entity */ | |
8152 | if (pml_idx >= PML_ENTITY_NUM) | |
8153 | pml_idx = 0; | |
8154 | else | |
8155 | pml_idx++; | |
8156 | ||
8157 | pml_buf = page_address(vmx->pml_pg); | |
8158 | for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { | |
8159 | u64 gpa; | |
8160 | ||
8161 | gpa = pml_buf[pml_idx]; | |
8162 | WARN_ON(gpa & (PAGE_SIZE - 1)); | |
54bf36aa | 8163 | kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); |
843e4330 KH |
8164 | } |
8165 | ||
8166 | /* reset PML index */ | |
8167 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
8168 | } | |
8169 | ||
8170 | /* | |
8171 | * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. | |
8172 | * Called before reporting dirty_bitmap to userspace. | |
8173 | */ | |
8174 | static void kvm_flush_pml_buffers(struct kvm *kvm) | |
8175 | { | |
8176 | int i; | |
8177 | struct kvm_vcpu *vcpu; | |
8178 | /* | |
8179 | * We only need to kick vcpu out of guest mode here, as PML buffer | |
8180 | * is flushed at beginning of all VMEXITs, and it's obvious that only | |
8181 | * vcpus running in guest are possible to have unflushed GPAs in PML | |
8182 | * buffer. | |
8183 | */ | |
8184 | kvm_for_each_vcpu(i, vcpu, kvm) | |
8185 | kvm_vcpu_kick(vcpu); | |
8186 | } | |
8187 | ||
4eb64dce PB |
8188 | static void vmx_dump_sel(char *name, uint32_t sel) |
8189 | { | |
8190 | pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", | |
96794e4e | 8191 | name, vmcs_read16(sel), |
4eb64dce PB |
8192 | vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), |
8193 | vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), | |
8194 | vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); | |
8195 | } | |
8196 | ||
8197 | static void vmx_dump_dtsel(char *name, uint32_t limit) | |
8198 | { | |
8199 | pr_err("%s limit=0x%08x, base=0x%016lx\n", | |
8200 | name, vmcs_read32(limit), | |
8201 | vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); | |
8202 | } | |
8203 | ||
8204 | static void dump_vmcs(void) | |
8205 | { | |
8206 | u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); | |
8207 | u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); | |
8208 | u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
8209 | u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); | |
8210 | u32 secondary_exec_control = 0; | |
8211 | unsigned long cr4 = vmcs_readl(GUEST_CR4); | |
f3531054 | 8212 | u64 efer = vmcs_read64(GUEST_IA32_EFER); |
4eb64dce PB |
8213 | int i, n; |
8214 | ||
8215 | if (cpu_has_secondary_exec_ctrls()) | |
8216 | secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
8217 | ||
8218 | pr_err("*** Guest State ***\n"); | |
8219 | pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
8220 | vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), | |
8221 | vmcs_readl(CR0_GUEST_HOST_MASK)); | |
8222 | pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
8223 | cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); | |
8224 | pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); | |
8225 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && | |
8226 | (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) | |
8227 | { | |
845c5b40 PB |
8228 | pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", |
8229 | vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); | |
8230 | pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", | |
8231 | vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); | |
4eb64dce PB |
8232 | } |
8233 | pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", | |
8234 | vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); | |
8235 | pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", | |
8236 | vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); | |
8237 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
8238 | vmcs_readl(GUEST_SYSENTER_ESP), | |
8239 | vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); | |
8240 | vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); | |
8241 | vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); | |
8242 | vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); | |
8243 | vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); | |
8244 | vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); | |
8245 | vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); | |
8246 | vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); | |
8247 | vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); | |
8248 | vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); | |
8249 | vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); | |
8250 | if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || | |
8251 | (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) | |
845c5b40 PB |
8252 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", |
8253 | efer, vmcs_read64(GUEST_IA32_PAT)); | |
8254 | pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", | |
8255 | vmcs_read64(GUEST_IA32_DEBUGCTL), | |
4eb64dce PB |
8256 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); |
8257 | if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
845c5b40 PB |
8258 | pr_err("PerfGlobCtl = 0x%016llx\n", |
8259 | vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); | |
4eb64dce | 8260 | if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) |
845c5b40 | 8261 | pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); |
4eb64dce PB |
8262 | pr_err("Interruptibility = %08x ActivityState = %08x\n", |
8263 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), | |
8264 | vmcs_read32(GUEST_ACTIVITY_STATE)); | |
8265 | if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) | |
8266 | pr_err("InterruptStatus = %04x\n", | |
8267 | vmcs_read16(GUEST_INTR_STATUS)); | |
8268 | ||
8269 | pr_err("*** Host State ***\n"); | |
8270 | pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", | |
8271 | vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); | |
8272 | pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", | |
8273 | vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), | |
8274 | vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), | |
8275 | vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), | |
8276 | vmcs_read16(HOST_TR_SELECTOR)); | |
8277 | pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", | |
8278 | vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), | |
8279 | vmcs_readl(HOST_TR_BASE)); | |
8280 | pr_err("GDTBase=%016lx IDTBase=%016lx\n", | |
8281 | vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); | |
8282 | pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", | |
8283 | vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), | |
8284 | vmcs_readl(HOST_CR4)); | |
8285 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
8286 | vmcs_readl(HOST_IA32_SYSENTER_ESP), | |
8287 | vmcs_read32(HOST_IA32_SYSENTER_CS), | |
8288 | vmcs_readl(HOST_IA32_SYSENTER_EIP)); | |
8289 | if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) | |
845c5b40 PB |
8290 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", |
8291 | vmcs_read64(HOST_IA32_EFER), | |
8292 | vmcs_read64(HOST_IA32_PAT)); | |
4eb64dce | 8293 | if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) |
845c5b40 PB |
8294 | pr_err("PerfGlobCtl = 0x%016llx\n", |
8295 | vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); | |
4eb64dce PB |
8296 | |
8297 | pr_err("*** Control State ***\n"); | |
8298 | pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", | |
8299 | pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); | |
8300 | pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); | |
8301 | pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", | |
8302 | vmcs_read32(EXCEPTION_BITMAP), | |
8303 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), | |
8304 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); | |
8305 | pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", | |
8306 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), | |
8307 | vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), | |
8308 | vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); | |
8309 | pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", | |
8310 | vmcs_read32(VM_EXIT_INTR_INFO), | |
8311 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
8312 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); | |
8313 | pr_err(" reason=%08x qualification=%016lx\n", | |
8314 | vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); | |
8315 | pr_err("IDTVectoring: info=%08x errcode=%08x\n", | |
8316 | vmcs_read32(IDT_VECTORING_INFO_FIELD), | |
8317 | vmcs_read32(IDT_VECTORING_ERROR_CODE)); | |
845c5b40 | 8318 | pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); |
8cfe9866 | 8319 | if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) |
845c5b40 PB |
8320 | pr_err("TSC Multiplier = 0x%016llx\n", |
8321 | vmcs_read64(TSC_MULTIPLIER)); | |
4eb64dce PB |
8322 | if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) |
8323 | pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); | |
8324 | if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) | |
8325 | pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); | |
8326 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) | |
845c5b40 | 8327 | pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); |
4eb64dce PB |
8328 | n = vmcs_read32(CR3_TARGET_COUNT); |
8329 | for (i = 0; i + 1 < n; i += 4) | |
8330 | pr_err("CR3 target%u=%016lx target%u=%016lx\n", | |
8331 | i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), | |
8332 | i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); | |
8333 | if (i < n) | |
8334 | pr_err("CR3 target%u=%016lx\n", | |
8335 | i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); | |
8336 | if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) | |
8337 | pr_err("PLE Gap=%08x Window=%08x\n", | |
8338 | vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); | |
8339 | if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) | |
8340 | pr_err("Virtual processor ID = 0x%04x\n", | |
8341 | vmcs_read16(VIRTUAL_PROCESSOR_ID)); | |
8342 | } | |
8343 | ||
6aa8b732 AK |
8344 | /* |
8345 | * The guest has exited. See if we can fix it or if we need userspace | |
8346 | * assistance. | |
8347 | */ | |
851ba692 | 8348 | static int vmx_handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 8349 | { |
29bd8a78 | 8350 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
a0861c02 | 8351 | u32 exit_reason = vmx->exit_reason; |
1155f76a | 8352 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 8353 | |
8b89fe1f | 8354 | trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); |
db1c056c | 8355 | vcpu->arch.gpa_available = false; |
8b89fe1f | 8356 | |
843e4330 KH |
8357 | /* |
8358 | * Flush logged GPAs PML buffer, this will make dirty_bitmap more | |
8359 | * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before | |
8360 | * querying dirty_bitmap, we only need to kick all vcpus out of guest | |
8361 | * mode as if vcpus is in root mode, the PML buffer must has been | |
8362 | * flushed already. | |
8363 | */ | |
8364 | if (enable_pml) | |
54bf36aa | 8365 | vmx_flush_pml_buffer(vcpu); |
843e4330 | 8366 | |
80ced186 | 8367 | /* If guest state is invalid, start emulating */ |
14168786 | 8368 | if (vmx->emulation_required) |
80ced186 | 8369 | return handle_invalid_guest_state(vcpu); |
1d5a4d9b | 8370 | |
644d711a | 8371 | if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) { |
533558bc JK |
8372 | nested_vmx_vmexit(vcpu, exit_reason, |
8373 | vmcs_read32(VM_EXIT_INTR_INFO), | |
8374 | vmcs_readl(EXIT_QUALIFICATION)); | |
644d711a NHE |
8375 | return 1; |
8376 | } | |
8377 | ||
5120702e | 8378 | if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { |
4eb64dce | 8379 | dump_vmcs(); |
5120702e MG |
8380 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
8381 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
8382 | = exit_reason; | |
8383 | return 0; | |
8384 | } | |
8385 | ||
29bd8a78 | 8386 | if (unlikely(vmx->fail)) { |
851ba692 AK |
8387 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
8388 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
29bd8a78 AK |
8389 | = vmcs_read32(VM_INSTRUCTION_ERROR); |
8390 | return 0; | |
8391 | } | |
6aa8b732 | 8392 | |
b9bf6882 XG |
8393 | /* |
8394 | * Note: | |
8395 | * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by | |
8396 | * delivery event since it indicates guest is accessing MMIO. | |
8397 | * The vm-exit can be triggered again after return to guest that | |
8398 | * will cause infinite loop. | |
8399 | */ | |
d77c26fc | 8400 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c | 8401 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
60637aac | 8402 | exit_reason != EXIT_REASON_EPT_VIOLATION && |
b244c9fc | 8403 | exit_reason != EXIT_REASON_PML_FULL && |
b9bf6882 XG |
8404 | exit_reason != EXIT_REASON_TASK_SWITCH)) { |
8405 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
8406 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; | |
8407 | vcpu->run->internal.ndata = 2; | |
8408 | vcpu->run->internal.data[0] = vectoring_info; | |
8409 | vcpu->run->internal.data[1] = exit_reason; | |
8410 | return 0; | |
8411 | } | |
3b86cd99 | 8412 | |
6aa8b732 AK |
8413 | if (exit_reason < kvm_vmx_max_exit_handlers |
8414 | && kvm_vmx_exit_handlers[exit_reason]) | |
851ba692 | 8415 | return kvm_vmx_exit_handlers[exit_reason](vcpu); |
6aa8b732 | 8416 | else { |
6c6c5e03 RK |
8417 | vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", |
8418 | exit_reason); | |
2bc19dc3 MT |
8419 | kvm_queue_exception(vcpu, UD_VECTOR); |
8420 | return 1; | |
6aa8b732 | 8421 | } |
6aa8b732 AK |
8422 | } |
8423 | ||
95ba8273 | 8424 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
6e5d865c | 8425 | { |
a7c0b07d WL |
8426 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
8427 | ||
8428 | if (is_guest_mode(vcpu) && | |
8429 | nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
8430 | return; | |
8431 | ||
95ba8273 | 8432 | if (irr == -1 || tpr < irr) { |
6e5d865c YS |
8433 | vmcs_write32(TPR_THRESHOLD, 0); |
8434 | return; | |
8435 | } | |
8436 | ||
95ba8273 | 8437 | vmcs_write32(TPR_THRESHOLD, irr); |
6e5d865c YS |
8438 | } |
8439 | ||
8d14695f YZ |
8440 | static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) |
8441 | { | |
8442 | u32 sec_exec_control; | |
8443 | ||
dccbfcf5 RK |
8444 | /* Postpone execution until vmcs01 is the current VMCS. */ |
8445 | if (is_guest_mode(vcpu)) { | |
8446 | to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true; | |
8447 | return; | |
8448 | } | |
8449 | ||
f6e90f9e | 8450 | if (!cpu_has_vmx_virtualize_x2apic_mode()) |
8d14695f YZ |
8451 | return; |
8452 | ||
35754c98 | 8453 | if (!cpu_need_tpr_shadow(vcpu)) |
8d14695f YZ |
8454 | return; |
8455 | ||
8456 | sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
8457 | ||
8458 | if (set) { | |
8459 | sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
8460 | sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
8461 | } else { | |
8462 | sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
8463 | sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
fb6c8198 | 8464 | vmx_flush_tlb_ept_only(vcpu); |
8d14695f YZ |
8465 | } |
8466 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control); | |
8467 | ||
8468 | vmx_set_msr_bitmap(vcpu); | |
8469 | } | |
8470 | ||
38b99173 TC |
8471 | static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) |
8472 | { | |
8473 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8474 | ||
8475 | /* | |
8476 | * Currently we do not handle the nested case where L2 has an | |
8477 | * APIC access page of its own; that page is still pinned. | |
8478 | * Hence, we skip the case where the VCPU is in guest mode _and_ | |
8479 | * L1 prepared an APIC access page for L2. | |
8480 | * | |
8481 | * For the case where L1 and L2 share the same APIC access page | |
8482 | * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear | |
8483 | * in the vmcs12), this function will only update either the vmcs01 | |
8484 | * or the vmcs02. If the former, the vmcs02 will be updated by | |
8485 | * prepare_vmcs02. If the latter, the vmcs01 will be updated in | |
8486 | * the next L2->L1 exit. | |
8487 | */ | |
8488 | if (!is_guest_mode(vcpu) || | |
4f2777bc | 8489 | !nested_cpu_has2(get_vmcs12(&vmx->vcpu), |
fb6c8198 | 8490 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { |
38b99173 | 8491 | vmcs_write64(APIC_ACCESS_ADDR, hpa); |
fb6c8198 JM |
8492 | vmx_flush_tlb_ept_only(vcpu); |
8493 | } | |
38b99173 TC |
8494 | } |
8495 | ||
67c9dddc | 8496 | static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) |
c7c9c56c YZ |
8497 | { |
8498 | u16 status; | |
8499 | u8 old; | |
8500 | ||
67c9dddc PB |
8501 | if (max_isr == -1) |
8502 | max_isr = 0; | |
c7c9c56c YZ |
8503 | |
8504 | status = vmcs_read16(GUEST_INTR_STATUS); | |
8505 | old = status >> 8; | |
67c9dddc | 8506 | if (max_isr != old) { |
c7c9c56c | 8507 | status &= 0xff; |
67c9dddc | 8508 | status |= max_isr << 8; |
c7c9c56c YZ |
8509 | vmcs_write16(GUEST_INTR_STATUS, status); |
8510 | } | |
8511 | } | |
8512 | ||
8513 | static void vmx_set_rvi(int vector) | |
8514 | { | |
8515 | u16 status; | |
8516 | u8 old; | |
8517 | ||
4114c27d WW |
8518 | if (vector == -1) |
8519 | vector = 0; | |
8520 | ||
c7c9c56c YZ |
8521 | status = vmcs_read16(GUEST_INTR_STATUS); |
8522 | old = (u8)status & 0xff; | |
8523 | if ((u8)vector != old) { | |
8524 | status &= ~0xff; | |
8525 | status |= (u8)vector; | |
8526 | vmcs_write16(GUEST_INTR_STATUS, status); | |
8527 | } | |
8528 | } | |
8529 | ||
8530 | static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) | |
8531 | { | |
4114c27d WW |
8532 | if (!is_guest_mode(vcpu)) { |
8533 | vmx_set_rvi(max_irr); | |
8534 | return; | |
8535 | } | |
8536 | ||
c7c9c56c YZ |
8537 | if (max_irr == -1) |
8538 | return; | |
8539 | ||
963fee16 | 8540 | /* |
4114c27d WW |
8541 | * In guest mode. If a vmexit is needed, vmx_check_nested_events |
8542 | * handles it. | |
963fee16 | 8543 | */ |
4114c27d | 8544 | if (nested_exit_on_intr(vcpu)) |
963fee16 WL |
8545 | return; |
8546 | ||
963fee16 | 8547 | /* |
4114c27d | 8548 | * Else, fall back to pre-APICv interrupt injection since L2 |
963fee16 WL |
8549 | * is run without virtual interrupt delivery. |
8550 | */ | |
8551 | if (!kvm_event_needs_reinjection(vcpu) && | |
8552 | vmx_interrupt_allowed(vcpu)) { | |
8553 | kvm_queue_interrupt(vcpu, max_irr, false); | |
8554 | vmx_inject_irq(vcpu); | |
8555 | } | |
c7c9c56c YZ |
8556 | } |
8557 | ||
76dfafd5 | 8558 | static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) |
810e6def PB |
8559 | { |
8560 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
76dfafd5 | 8561 | int max_irr; |
810e6def | 8562 | |
76dfafd5 PB |
8563 | WARN_ON(!vcpu->arch.apicv_active); |
8564 | if (pi_test_on(&vmx->pi_desc)) { | |
8565 | pi_clear_on(&vmx->pi_desc); | |
8566 | /* | |
8567 | * IOMMU can write to PIR.ON, so the barrier matters even on UP. | |
8568 | * But on x86 this is just a compiler barrier anyway. | |
8569 | */ | |
8570 | smp_mb__after_atomic(); | |
8571 | max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir); | |
8572 | } else { | |
8573 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
8574 | } | |
8575 | vmx_hwapic_irr_update(vcpu, max_irr); | |
8576 | return max_irr; | |
810e6def PB |
8577 | } |
8578 | ||
6308630b | 8579 | static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
c7c9c56c | 8580 | { |
d62caabb | 8581 | if (!kvm_vcpu_apicv_active(vcpu)) |
3d81bc7e YZ |
8582 | return; |
8583 | ||
c7c9c56c YZ |
8584 | vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); |
8585 | vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); | |
8586 | vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); | |
8587 | vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); | |
8588 | } | |
8589 | ||
967235d3 PB |
8590 | static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) |
8591 | { | |
8592 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8593 | ||
8594 | pi_clear_on(&vmx->pi_desc); | |
8595 | memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); | |
8596 | } | |
8597 | ||
51aa01d1 | 8598 | static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx) |
cf393f75 | 8599 | { |
00eba012 AK |
8600 | u32 exit_intr_info; |
8601 | ||
8602 | if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY | |
8603 | || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)) | |
8604 | return; | |
8605 | ||
c5ca8e57 | 8606 | vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
00eba012 | 8607 | exit_intr_info = vmx->exit_intr_info; |
a0861c02 AK |
8608 | |
8609 | /* Handle machine checks before interrupts are enabled */ | |
00eba012 | 8610 | if (is_machine_check(exit_intr_info)) |
a0861c02 AK |
8611 | kvm_machine_check(); |
8612 | ||
20f65983 | 8613 | /* We need to handle NMIs before interrupts are enabled */ |
ef85b673 | 8614 | if (is_nmi(exit_intr_info)) { |
ff9d07a0 | 8615 | kvm_before_handle_nmi(&vmx->vcpu); |
20f65983 | 8616 | asm("int $2"); |
ff9d07a0 ZY |
8617 | kvm_after_handle_nmi(&vmx->vcpu); |
8618 | } | |
51aa01d1 | 8619 | } |
20f65983 | 8620 | |
a547c6db YZ |
8621 | static void vmx_handle_external_intr(struct kvm_vcpu *vcpu) |
8622 | { | |
8623 | u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
3f62de5f | 8624 | register void *__sp asm(_ASM_SP); |
a547c6db | 8625 | |
a547c6db YZ |
8626 | if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK)) |
8627 | == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) { | |
8628 | unsigned int vector; | |
8629 | unsigned long entry; | |
8630 | gate_desc *desc; | |
8631 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8632 | #ifdef CONFIG_X86_64 | |
8633 | unsigned long tmp; | |
8634 | #endif | |
8635 | ||
8636 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
8637 | desc = (gate_desc *)vmx->host_idt_base + vector; | |
8638 | entry = gate_offset(*desc); | |
8639 | asm volatile( | |
8640 | #ifdef CONFIG_X86_64 | |
8641 | "mov %%" _ASM_SP ", %[sp]\n\t" | |
8642 | "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" | |
8643 | "push $%c[ss]\n\t" | |
8644 | "push %[sp]\n\t" | |
8645 | #endif | |
8646 | "pushf\n\t" | |
a547c6db YZ |
8647 | __ASM_SIZE(push) " $%c[cs]\n\t" |
8648 | "call *%[entry]\n\t" | |
8649 | : | |
8650 | #ifdef CONFIG_X86_64 | |
3f62de5f | 8651 | [sp]"=&r"(tmp), |
a547c6db | 8652 | #endif |
3f62de5f | 8653 | "+r"(__sp) |
a547c6db YZ |
8654 | : |
8655 | [entry]"r"(entry), | |
8656 | [ss]"i"(__KERNEL_DS), | |
8657 | [cs]"i"(__KERNEL_CS) | |
8658 | ); | |
f2485b3e | 8659 | } |
a547c6db YZ |
8660 | } |
8661 | ||
6d396b55 PB |
8662 | static bool vmx_has_high_real_mode_segbase(void) |
8663 | { | |
8664 | return enable_unrestricted_guest || emulate_invalid_guest_state; | |
8665 | } | |
8666 | ||
da8999d3 LJ |
8667 | static bool vmx_mpx_supported(void) |
8668 | { | |
8669 | return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) && | |
8670 | (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS); | |
8671 | } | |
8672 | ||
55412b2e WL |
8673 | static bool vmx_xsaves_supported(void) |
8674 | { | |
8675 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
8676 | SECONDARY_EXEC_XSAVES; | |
8677 | } | |
8678 | ||
51aa01d1 AK |
8679 | static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) |
8680 | { | |
c5ca8e57 | 8681 | u32 exit_intr_info; |
51aa01d1 AK |
8682 | bool unblock_nmi; |
8683 | u8 vector; | |
8684 | bool idtv_info_valid; | |
8685 | ||
8686 | idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
20f65983 | 8687 | |
2c82878b PB |
8688 | if (vmx->nmi_known_unmasked) |
8689 | return; | |
8690 | /* | |
8691 | * Can't use vmx->exit_intr_info since we're not sure what | |
8692 | * the exit reason is. | |
8693 | */ | |
8694 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
8695 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; | |
8696 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
8697 | /* | |
8698 | * SDM 3: 27.7.1.2 (September 2008) | |
8699 | * Re-set bit "block by NMI" before VM entry if vmexit caused by | |
8700 | * a guest IRET fault. | |
8701 | * SDM 3: 23.2.2 (September 2008) | |
8702 | * Bit 12 is undefined in any of the following cases: | |
8703 | * If the VM exit sets the valid bit in the IDT-vectoring | |
8704 | * information field. | |
8705 | * If the VM exit is due to a double fault. | |
8706 | */ | |
8707 | if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && | |
8708 | vector != DF_VECTOR && !idtv_info_valid) | |
8709 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
8710 | GUEST_INTR_STATE_NMI); | |
8711 | else | |
8712 | vmx->nmi_known_unmasked = | |
8713 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) | |
8714 | & GUEST_INTR_STATE_NMI); | |
51aa01d1 AK |
8715 | } |
8716 | ||
3ab66e8a | 8717 | static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, |
83422e17 AK |
8718 | u32 idt_vectoring_info, |
8719 | int instr_len_field, | |
8720 | int error_code_field) | |
51aa01d1 | 8721 | { |
51aa01d1 AK |
8722 | u8 vector; |
8723 | int type; | |
8724 | bool idtv_info_valid; | |
8725 | ||
8726 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
668f612f | 8727 | |
3ab66e8a JK |
8728 | vcpu->arch.nmi_injected = false; |
8729 | kvm_clear_exception_queue(vcpu); | |
8730 | kvm_clear_interrupt_queue(vcpu); | |
37b96e98 GN |
8731 | |
8732 | if (!idtv_info_valid) | |
8733 | return; | |
8734 | ||
3ab66e8a | 8735 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3842d135 | 8736 | |
668f612f AK |
8737 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; |
8738 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | |
37b96e98 | 8739 | |
64a7ec06 | 8740 | switch (type) { |
37b96e98 | 8741 | case INTR_TYPE_NMI_INTR: |
3ab66e8a | 8742 | vcpu->arch.nmi_injected = true; |
668f612f | 8743 | /* |
7b4a25cb | 8744 | * SDM 3: 27.7.1.2 (September 2008) |
37b96e98 GN |
8745 | * Clear bit "block by NMI" before VM entry if a NMI |
8746 | * delivery faulted. | |
668f612f | 8747 | */ |
3ab66e8a | 8748 | vmx_set_nmi_mask(vcpu, false); |
37b96e98 | 8749 | break; |
37b96e98 | 8750 | case INTR_TYPE_SOFT_EXCEPTION: |
3ab66e8a | 8751 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f GN |
8752 | /* fall through */ |
8753 | case INTR_TYPE_HARD_EXCEPTION: | |
35920a35 | 8754 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { |
83422e17 | 8755 | u32 err = vmcs_read32(error_code_field); |
851eb667 | 8756 | kvm_requeue_exception_e(vcpu, vector, err); |
35920a35 | 8757 | } else |
851eb667 | 8758 | kvm_requeue_exception(vcpu, vector); |
37b96e98 | 8759 | break; |
66fd3f7f | 8760 | case INTR_TYPE_SOFT_INTR: |
3ab66e8a | 8761 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f | 8762 | /* fall through */ |
37b96e98 | 8763 | case INTR_TYPE_EXT_INTR: |
3ab66e8a | 8764 | kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); |
37b96e98 GN |
8765 | break; |
8766 | default: | |
8767 | break; | |
f7d9238f | 8768 | } |
cf393f75 AK |
8769 | } |
8770 | ||
83422e17 AK |
8771 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
8772 | { | |
3ab66e8a | 8773 | __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, |
83422e17 AK |
8774 | VM_EXIT_INSTRUCTION_LEN, |
8775 | IDT_VECTORING_ERROR_CODE); | |
8776 | } | |
8777 | ||
b463a6f7 AK |
8778 | static void vmx_cancel_injection(struct kvm_vcpu *vcpu) |
8779 | { | |
3ab66e8a | 8780 | __vmx_complete_interrupts(vcpu, |
b463a6f7 AK |
8781 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), |
8782 | VM_ENTRY_INSTRUCTION_LEN, | |
8783 | VM_ENTRY_EXCEPTION_ERROR_CODE); | |
8784 | ||
8785 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); | |
8786 | } | |
8787 | ||
d7cd9796 GN |
8788 | static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) |
8789 | { | |
8790 | int i, nr_msrs; | |
8791 | struct perf_guest_switch_msr *msrs; | |
8792 | ||
8793 | msrs = perf_guest_get_msrs(&nr_msrs); | |
8794 | ||
8795 | if (!msrs) | |
8796 | return; | |
8797 | ||
8798 | for (i = 0; i < nr_msrs; i++) | |
8799 | if (msrs[i].host == msrs[i].guest) | |
8800 | clear_atomic_switch_msr(vmx, msrs[i].msr); | |
8801 | else | |
8802 | add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, | |
8803 | msrs[i].host); | |
8804 | } | |
8805 | ||
33365e7a | 8806 | static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu) |
64672c95 YJ |
8807 | { |
8808 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8809 | u64 tscl; | |
8810 | u32 delta_tsc; | |
8811 | ||
8812 | if (vmx->hv_deadline_tsc == -1) | |
8813 | return; | |
8814 | ||
8815 | tscl = rdtsc(); | |
8816 | if (vmx->hv_deadline_tsc > tscl) | |
8817 | /* sure to be 32 bit only because checked on set_hv_timer */ | |
8818 | delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> | |
8819 | cpu_preemption_timer_multi); | |
8820 | else | |
8821 | delta_tsc = 0; | |
8822 | ||
8823 | vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); | |
8824 | } | |
8825 | ||
a3b5ba49 | 8826 | static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 8827 | { |
a2fa3e9f | 8828 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
d974baa3 | 8829 | unsigned long debugctlmsr, cr4; |
104f226b | 8830 | |
104f226b AK |
8831 | /* Don't enter VMX if guest state is invalid, let the exit handler |
8832 | start emulation until we arrive back to a valid state */ | |
14168786 | 8833 | if (vmx->emulation_required) |
104f226b AK |
8834 | return; |
8835 | ||
a7653ecd RK |
8836 | if (vmx->ple_window_dirty) { |
8837 | vmx->ple_window_dirty = false; | |
8838 | vmcs_write32(PLE_WINDOW, vmx->ple_window); | |
8839 | } | |
8840 | ||
012f83cb AG |
8841 | if (vmx->nested.sync_shadow_vmcs) { |
8842 | copy_vmcs12_to_shadow(vmx); | |
8843 | vmx->nested.sync_shadow_vmcs = false; | |
8844 | } | |
8845 | ||
104f226b AK |
8846 | if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) |
8847 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); | |
8848 | if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
8849 | vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); | |
8850 | ||
1e02ce4c | 8851 | cr4 = cr4_read_shadow(); |
d974baa3 AL |
8852 | if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) { |
8853 | vmcs_writel(HOST_CR4, cr4); | |
8854 | vmx->host_state.vmcs_host_cr4 = cr4; | |
8855 | } | |
8856 | ||
104f226b AK |
8857 | /* When single-stepping over STI and MOV SS, we must clear the |
8858 | * corresponding interruptibility bits in the guest state. Otherwise | |
8859 | * vmentry fails as it then expects bit 14 (BS) in pending debug | |
8860 | * exceptions being set, but that's not correct for the guest debugging | |
8861 | * case. */ | |
8862 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
8863 | vmx_set_interrupt_shadow(vcpu, 0); | |
8864 | ||
1be0e61c XG |
8865 | if (vmx->guest_pkru_valid) |
8866 | __write_pkru(vmx->guest_pkru); | |
8867 | ||
d7cd9796 | 8868 | atomic_switch_perf_msrs(vmx); |
2a7921b7 | 8869 | debugctlmsr = get_debugctlmsr(); |
d7cd9796 | 8870 | |
64672c95 YJ |
8871 | vmx_arm_hv_timer(vcpu); |
8872 | ||
d462b819 | 8873 | vmx->__launched = vmx->loaded_vmcs->launched; |
104f226b | 8874 | asm( |
6aa8b732 | 8875 | /* Store host registers */ |
b188c81f AK |
8876 | "push %%" _ASM_DX "; push %%" _ASM_BP ";" |
8877 | "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */ | |
8878 | "push %%" _ASM_CX " \n\t" | |
8879 | "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t" | |
313dbd49 | 8880 | "je 1f \n\t" |
b188c81f | 8881 | "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t" |
4ecac3fd | 8882 | __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t" |
313dbd49 | 8883 | "1: \n\t" |
d3edefc0 | 8884 | /* Reload cr2 if changed */ |
b188c81f AK |
8885 | "mov %c[cr2](%0), %%" _ASM_AX " \n\t" |
8886 | "mov %%cr2, %%" _ASM_DX " \n\t" | |
8887 | "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t" | |
d3edefc0 | 8888 | "je 2f \n\t" |
b188c81f | 8889 | "mov %%" _ASM_AX", %%cr2 \n\t" |
d3edefc0 | 8890 | "2: \n\t" |
6aa8b732 | 8891 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 8892 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 8893 | /* Load guest registers. Don't clobber flags. */ |
b188c81f AK |
8894 | "mov %c[rax](%0), %%" _ASM_AX " \n\t" |
8895 | "mov %c[rbx](%0), %%" _ASM_BX " \n\t" | |
8896 | "mov %c[rdx](%0), %%" _ASM_DX " \n\t" | |
8897 | "mov %c[rsi](%0), %%" _ASM_SI " \n\t" | |
8898 | "mov %c[rdi](%0), %%" _ASM_DI " \n\t" | |
8899 | "mov %c[rbp](%0), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 8900 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
8901 | "mov %c[r8](%0), %%r8 \n\t" |
8902 | "mov %c[r9](%0), %%r9 \n\t" | |
8903 | "mov %c[r10](%0), %%r10 \n\t" | |
8904 | "mov %c[r11](%0), %%r11 \n\t" | |
8905 | "mov %c[r12](%0), %%r12 \n\t" | |
8906 | "mov %c[r13](%0), %%r13 \n\t" | |
8907 | "mov %c[r14](%0), %%r14 \n\t" | |
8908 | "mov %c[r15](%0), %%r15 \n\t" | |
6aa8b732 | 8909 | #endif |
b188c81f | 8910 | "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */ |
c801949d | 8911 | |
6aa8b732 | 8912 | /* Enter guest mode */ |
83287ea4 | 8913 | "jne 1f \n\t" |
4ecac3fd | 8914 | __ex(ASM_VMX_VMLAUNCH) "\n\t" |
83287ea4 AK |
8915 | "jmp 2f \n\t" |
8916 | "1: " __ex(ASM_VMX_VMRESUME) "\n\t" | |
8917 | "2: " | |
6aa8b732 | 8918 | /* Save guest registers, load host registers, keep flags */ |
b188c81f | 8919 | "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t" |
40712fae | 8920 | "pop %0 \n\t" |
b188c81f AK |
8921 | "mov %%" _ASM_AX ", %c[rax](%0) \n\t" |
8922 | "mov %%" _ASM_BX ", %c[rbx](%0) \n\t" | |
8923 | __ASM_SIZE(pop) " %c[rcx](%0) \n\t" | |
8924 | "mov %%" _ASM_DX ", %c[rdx](%0) \n\t" | |
8925 | "mov %%" _ASM_SI ", %c[rsi](%0) \n\t" | |
8926 | "mov %%" _ASM_DI ", %c[rdi](%0) \n\t" | |
8927 | "mov %%" _ASM_BP ", %c[rbp](%0) \n\t" | |
05b3e0c2 | 8928 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
8929 | "mov %%r8, %c[r8](%0) \n\t" |
8930 | "mov %%r9, %c[r9](%0) \n\t" | |
8931 | "mov %%r10, %c[r10](%0) \n\t" | |
8932 | "mov %%r11, %c[r11](%0) \n\t" | |
8933 | "mov %%r12, %c[r12](%0) \n\t" | |
8934 | "mov %%r13, %c[r13](%0) \n\t" | |
8935 | "mov %%r14, %c[r14](%0) \n\t" | |
8936 | "mov %%r15, %c[r15](%0) \n\t" | |
6aa8b732 | 8937 | #endif |
b188c81f AK |
8938 | "mov %%cr2, %%" _ASM_AX " \n\t" |
8939 | "mov %%" _ASM_AX ", %c[cr2](%0) \n\t" | |
c801949d | 8940 | |
b188c81f | 8941 | "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t" |
e08aa78a | 8942 | "setbe %c[fail](%0) \n\t" |
83287ea4 AK |
8943 | ".pushsection .rodata \n\t" |
8944 | ".global vmx_return \n\t" | |
8945 | "vmx_return: " _ASM_PTR " 2b \n\t" | |
8946 | ".popsection" | |
e08aa78a | 8947 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), |
d462b819 | 8948 | [launched]"i"(offsetof(struct vcpu_vmx, __launched)), |
e08aa78a | 8949 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), |
313dbd49 | 8950 | [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)), |
ad312c7c ZX |
8951 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
8952 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
8953 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
8954 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
8955 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
8956 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
8957 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 8958 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
8959 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
8960 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
8961 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
8962 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
8963 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
8964 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
8965 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
8966 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 8967 | #endif |
40712fae AK |
8968 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)), |
8969 | [wordsize]"i"(sizeof(ulong)) | |
c2036300 LV |
8970 | : "cc", "memory" |
8971 | #ifdef CONFIG_X86_64 | |
b188c81f | 8972 | , "rax", "rbx", "rdi", "rsi" |
c2036300 | 8973 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
b188c81f AK |
8974 | #else |
8975 | , "eax", "ebx", "edi", "esi" | |
c2036300 LV |
8976 | #endif |
8977 | ); | |
6aa8b732 | 8978 | |
2a7921b7 GN |
8979 | /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ |
8980 | if (debugctlmsr) | |
8981 | update_debugctlmsr(debugctlmsr); | |
8982 | ||
aa67f609 AK |
8983 | #ifndef CONFIG_X86_64 |
8984 | /* | |
8985 | * The sysexit path does not restore ds/es, so we must set them to | |
8986 | * a reasonable value ourselves. | |
8987 | * | |
8988 | * We can't defer this to vmx_load_host_state() since that function | |
8989 | * may be executed in interrupt context, which saves and restore segments | |
8990 | * around it, nullifying its effect. | |
8991 | */ | |
8992 | loadsegment(ds, __USER_DS); | |
8993 | loadsegment(es, __USER_DS); | |
8994 | #endif | |
8995 | ||
6de4f3ad | 8996 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) |
6de12732 | 8997 | | (1 << VCPU_EXREG_RFLAGS) |
aff48baa | 8998 | | (1 << VCPU_EXREG_PDPTR) |
2fb92db1 | 8999 | | (1 << VCPU_EXREG_SEGMENTS) |
aff48baa | 9000 | | (1 << VCPU_EXREG_CR3)); |
5fdbf976 MT |
9001 | vcpu->arch.regs_dirty = 0; |
9002 | ||
1155f76a AK |
9003 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); |
9004 | ||
d462b819 | 9005 | vmx->loaded_vmcs->launched = 1; |
1b6269db | 9006 | |
51aa01d1 | 9007 | vmx->exit_reason = vmcs_read32(VM_EXIT_REASON); |
51aa01d1 | 9008 | |
1be0e61c XG |
9009 | /* |
9010 | * eager fpu is enabled if PKEY is supported and CR4 is switched | |
9011 | * back on host, so it is safe to read guest PKRU from current | |
9012 | * XSAVE. | |
9013 | */ | |
9014 | if (boot_cpu_has(X86_FEATURE_OSPKE)) { | |
9015 | vmx->guest_pkru = __read_pkru(); | |
9016 | if (vmx->guest_pkru != vmx->host_pkru) { | |
9017 | vmx->guest_pkru_valid = true; | |
9018 | __write_pkru(vmx->host_pkru); | |
9019 | } else | |
9020 | vmx->guest_pkru_valid = false; | |
9021 | } | |
9022 | ||
e0b890d3 GN |
9023 | /* |
9024 | * the KVM_REQ_EVENT optimization bit is only on for one entry, and if | |
9025 | * we did not inject a still-pending event to L1 now because of | |
9026 | * nested_run_pending, we need to re-enable this bit. | |
9027 | */ | |
9028 | if (vmx->nested.nested_run_pending) | |
9029 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
9030 | ||
9031 | vmx->nested.nested_run_pending = 0; | |
9032 | ||
51aa01d1 AK |
9033 | vmx_complete_atomic_exit(vmx); |
9034 | vmx_recover_nmi_blocking(vmx); | |
cf393f75 | 9035 | vmx_complete_interrupts(vmx); |
6aa8b732 AK |
9036 | } |
9037 | ||
1279a6b1 | 9038 | static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs) |
4fa7734c PB |
9039 | { |
9040 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9041 | int cpu; | |
9042 | ||
1279a6b1 | 9043 | if (vmx->loaded_vmcs == vmcs) |
4fa7734c PB |
9044 | return; |
9045 | ||
9046 | cpu = get_cpu(); | |
1279a6b1 | 9047 | vmx->loaded_vmcs = vmcs; |
4fa7734c PB |
9048 | vmx_vcpu_put(vcpu); |
9049 | vmx_vcpu_load(vcpu, cpu); | |
9050 | vcpu->cpu = cpu; | |
9051 | put_cpu(); | |
9052 | } | |
9053 | ||
2f1fe811 JM |
9054 | /* |
9055 | * Ensure that the current vmcs of the logical processor is the | |
9056 | * vmcs01 of the vcpu before calling free_nested(). | |
9057 | */ | |
9058 | static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu) | |
9059 | { | |
9060 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9061 | int r; | |
9062 | ||
9063 | r = vcpu_load(vcpu); | |
9064 | BUG_ON(r); | |
1279a6b1 | 9065 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); |
2f1fe811 JM |
9066 | free_nested(vmx); |
9067 | vcpu_put(vcpu); | |
9068 | } | |
9069 | ||
6aa8b732 AK |
9070 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) |
9071 | { | |
fb3f0f51 RR |
9072 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
9073 | ||
843e4330 | 9074 | if (enable_pml) |
a3eaa864 | 9075 | vmx_destroy_pml_buffer(vmx); |
991e7a0e | 9076 | free_vpid(vmx->vpid); |
4fa7734c | 9077 | leave_guest_mode(vcpu); |
2f1fe811 | 9078 | vmx_free_vcpu_nested(vcpu); |
4fa7734c | 9079 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 RR |
9080 | kfree(vmx->guest_msrs); |
9081 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 9082 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
9083 | } |
9084 | ||
fb3f0f51 | 9085 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 9086 | { |
fb3f0f51 | 9087 | int err; |
c16f862d | 9088 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
15ad7146 | 9089 | int cpu; |
6aa8b732 | 9090 | |
a2fa3e9f | 9091 | if (!vmx) |
fb3f0f51 RR |
9092 | return ERR_PTR(-ENOMEM); |
9093 | ||
991e7a0e | 9094 | vmx->vpid = allocate_vpid(); |
2384d2b3 | 9095 | |
fb3f0f51 RR |
9096 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
9097 | if (err) | |
9098 | goto free_vcpu; | |
965b58a5 | 9099 | |
4e59516a PF |
9100 | err = -ENOMEM; |
9101 | ||
9102 | /* | |
9103 | * If PML is turned on, failure on enabling PML just results in failure | |
9104 | * of creating the vcpu, therefore we can simplify PML logic (by | |
9105 | * avoiding dealing with cases, such as enabling PML partially on vcpus | |
9106 | * for the guest, etc. | |
9107 | */ | |
9108 | if (enable_pml) { | |
9109 | vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
9110 | if (!vmx->pml_pg) | |
9111 | goto uninit_vcpu; | |
9112 | } | |
9113 | ||
a2fa3e9f | 9114 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
03916db9 PB |
9115 | BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0]) |
9116 | > PAGE_SIZE); | |
0123be42 | 9117 | |
4e59516a PF |
9118 | if (!vmx->guest_msrs) |
9119 | goto free_pml; | |
965b58a5 | 9120 | |
d462b819 NHE |
9121 | vmx->loaded_vmcs = &vmx->vmcs01; |
9122 | vmx->loaded_vmcs->vmcs = alloc_vmcs(); | |
355f4fb1 | 9123 | vmx->loaded_vmcs->shadow_vmcs = NULL; |
d462b819 | 9124 | if (!vmx->loaded_vmcs->vmcs) |
fb3f0f51 | 9125 | goto free_msrs; |
d462b819 | 9126 | loaded_vmcs_init(vmx->loaded_vmcs); |
a2fa3e9f | 9127 | |
15ad7146 AK |
9128 | cpu = get_cpu(); |
9129 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
e48672fa | 9130 | vmx->vcpu.cpu = cpu; |
8b9cf98c | 9131 | err = vmx_vcpu_setup(vmx); |
fb3f0f51 | 9132 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 9133 | put_cpu(); |
fb3f0f51 RR |
9134 | if (err) |
9135 | goto free_vmcs; | |
35754c98 | 9136 | if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { |
be6d05cf JK |
9137 | err = alloc_apic_access_page(kvm); |
9138 | if (err) | |
5e4a0b3c | 9139 | goto free_vmcs; |
a63cb560 | 9140 | } |
fb3f0f51 | 9141 | |
b927a3ce SY |
9142 | if (enable_ept) { |
9143 | if (!kvm->arch.ept_identity_map_addr) | |
9144 | kvm->arch.ept_identity_map_addr = | |
9145 | VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
f51770ed TC |
9146 | err = init_rmode_identity_map(kvm); |
9147 | if (err) | |
93ea5388 | 9148 | goto free_vmcs; |
b927a3ce | 9149 | } |
b7ebfb05 | 9150 | |
5c614b35 | 9151 | if (nested) { |
b9c237bb | 9152 | nested_vmx_setup_ctls_msrs(vmx); |
5c614b35 WL |
9153 | vmx->nested.vpid02 = allocate_vpid(); |
9154 | } | |
b9c237bb | 9155 | |
705699a1 | 9156 | vmx->nested.posted_intr_nv = -1; |
a9d30f33 NHE |
9157 | vmx->nested.current_vmptr = -1ull; |
9158 | vmx->nested.current_vmcs12 = NULL; | |
9159 | ||
37e4c997 HZ |
9160 | vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED; |
9161 | ||
fb3f0f51 RR |
9162 | return &vmx->vcpu; |
9163 | ||
9164 | free_vmcs: | |
5c614b35 | 9165 | free_vpid(vmx->nested.vpid02); |
5f3fbc34 | 9166 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 | 9167 | free_msrs: |
fb3f0f51 | 9168 | kfree(vmx->guest_msrs); |
4e59516a PF |
9169 | free_pml: |
9170 | vmx_destroy_pml_buffer(vmx); | |
fb3f0f51 RR |
9171 | uninit_vcpu: |
9172 | kvm_vcpu_uninit(&vmx->vcpu); | |
9173 | free_vcpu: | |
991e7a0e | 9174 | free_vpid(vmx->vpid); |
a4770347 | 9175 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 9176 | return ERR_PTR(err); |
6aa8b732 AK |
9177 | } |
9178 | ||
002c7f7c YS |
9179 | static void __init vmx_check_processor_compat(void *rtn) |
9180 | { | |
9181 | struct vmcs_config vmcs_conf; | |
9182 | ||
9183 | *(int *)rtn = 0; | |
9184 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
9185 | *(int *)rtn = -EIO; | |
9186 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
9187 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
9188 | smp_processor_id()); | |
9189 | *(int *)rtn = -EIO; | |
9190 | } | |
9191 | } | |
9192 | ||
67253af5 SY |
9193 | static int get_ept_level(void) |
9194 | { | |
9195 | return VMX_EPT_DEFAULT_GAW + 1; | |
9196 | } | |
9197 | ||
4b12f0de | 9198 | static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 | 9199 | { |
b18d5431 XG |
9200 | u8 cache; |
9201 | u64 ipat = 0; | |
4b12f0de | 9202 | |
522c68c4 | 9203 | /* For VT-d and EPT combination |
606decd6 | 9204 | * 1. MMIO: always map as UC |
522c68c4 SY |
9205 | * 2. EPT with VT-d: |
9206 | * a. VT-d without snooping control feature: can't guarantee the | |
606decd6 | 9207 | * result, try to trust guest. |
522c68c4 SY |
9208 | * b. VT-d with snooping control feature: snooping control feature of |
9209 | * VT-d engine can guarantee the cache correctness. Just set it | |
9210 | * to WB to keep consistent with host. So the same as item 3. | |
a19a6d11 | 9211 | * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep |
522c68c4 SY |
9212 | * consistent with host MTRR |
9213 | */ | |
606decd6 PB |
9214 | if (is_mmio) { |
9215 | cache = MTRR_TYPE_UNCACHABLE; | |
9216 | goto exit; | |
9217 | } | |
9218 | ||
9219 | if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { | |
b18d5431 XG |
9220 | ipat = VMX_EPT_IPAT_BIT; |
9221 | cache = MTRR_TYPE_WRBACK; | |
9222 | goto exit; | |
9223 | } | |
9224 | ||
9225 | if (kvm_read_cr0(vcpu) & X86_CR0_CD) { | |
9226 | ipat = VMX_EPT_IPAT_BIT; | |
0da029ed | 9227 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) |
fb279950 XG |
9228 | cache = MTRR_TYPE_WRBACK; |
9229 | else | |
9230 | cache = MTRR_TYPE_UNCACHABLE; | |
b18d5431 XG |
9231 | goto exit; |
9232 | } | |
9233 | ||
ff53604b | 9234 | cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); |
b18d5431 XG |
9235 | |
9236 | exit: | |
9237 | return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; | |
64d4d521 SY |
9238 | } |
9239 | ||
17cc3935 | 9240 | static int vmx_get_lpage_level(void) |
344f414f | 9241 | { |
878403b7 SY |
9242 | if (enable_ept && !cpu_has_vmx_ept_1g_page()) |
9243 | return PT_DIRECTORY_LEVEL; | |
9244 | else | |
9245 | /* For shadow and EPT supported 1GB page */ | |
9246 | return PT_PDPE_LEVEL; | |
344f414f JR |
9247 | } |
9248 | ||
feda805f XG |
9249 | static void vmcs_set_secondary_exec_control(u32 new_ctl) |
9250 | { | |
9251 | /* | |
9252 | * These bits in the secondary execution controls field | |
9253 | * are dynamic, the others are mostly based on the hypervisor | |
9254 | * architecture and the guest's CPUID. Do not touch the | |
9255 | * dynamic bits. | |
9256 | */ | |
9257 | u32 mask = | |
9258 | SECONDARY_EXEC_SHADOW_VMCS | | |
9259 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | | |
9260 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
9261 | ||
9262 | u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
9263 | ||
9264 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, | |
9265 | (new_ctl & ~mask) | (cur_ctl & mask)); | |
9266 | } | |
9267 | ||
8322ebbb DM |
9268 | /* |
9269 | * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits | |
9270 | * (indicating "allowed-1") if they are supported in the guest's CPUID. | |
9271 | */ | |
9272 | static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) | |
9273 | { | |
9274 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9275 | struct kvm_cpuid_entry2 *entry; | |
9276 | ||
9277 | vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff; | |
9278 | vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE; | |
9279 | ||
9280 | #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ | |
9281 | if (entry && (entry->_reg & (_cpuid_mask))) \ | |
9282 | vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \ | |
9283 | } while (0) | |
9284 | ||
9285 | entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); | |
9286 | cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME)); | |
9287 | cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME)); | |
9288 | cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC)); | |
9289 | cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE)); | |
9290 | cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE)); | |
9291 | cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE)); | |
9292 | cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE)); | |
9293 | cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE)); | |
9294 | cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR)); | |
9295 | cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM)); | |
9296 | cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX)); | |
9297 | cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX)); | |
9298 | cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID)); | |
9299 | cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE)); | |
9300 | ||
9301 | entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); | |
9302 | cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE)); | |
9303 | cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP)); | |
9304 | cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP)); | |
9305 | cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU)); | |
9306 | /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */ | |
9307 | cr4_fixed1_update(bit(11), ecx, bit(2)); | |
9308 | ||
9309 | #undef cr4_fixed1_update | |
9310 | } | |
9311 | ||
0e851880 SY |
9312 | static void vmx_cpuid_update(struct kvm_vcpu *vcpu) |
9313 | { | |
4e47c7a6 SY |
9314 | struct kvm_cpuid_entry2 *best; |
9315 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
feda805f | 9316 | u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx); |
4e47c7a6 | 9317 | |
4e47c7a6 | 9318 | if (vmx_rdtscp_supported()) { |
1cea0ce6 XG |
9319 | bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu); |
9320 | if (!rdtscp_enabled) | |
feda805f | 9321 | secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP; |
f36201e5 | 9322 | |
8b97265a | 9323 | if (nested) { |
1cea0ce6 | 9324 | if (rdtscp_enabled) |
8b97265a PB |
9325 | vmx->nested.nested_vmx_secondary_ctls_high |= |
9326 | SECONDARY_EXEC_RDTSCP; | |
9327 | else | |
9328 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
9329 | ~SECONDARY_EXEC_RDTSCP; | |
9330 | } | |
4e47c7a6 | 9331 | } |
ad756a16 | 9332 | |
ad756a16 MJ |
9333 | /* Exposing INVPCID only when PCID is exposed */ |
9334 | best = kvm_find_cpuid_entry(vcpu, 0x7, 0); | |
9335 | if (vmx_invpcid_supported() && | |
29541bb8 XG |
9336 | (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) || |
9337 | !guest_cpuid_has_pcid(vcpu))) { | |
feda805f | 9338 | secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID; |
29541bb8 | 9339 | |
ad756a16 | 9340 | if (best) |
4f977045 | 9341 | best->ebx &= ~bit(X86_FEATURE_INVPCID); |
ad756a16 | 9342 | } |
8b3e34e4 | 9343 | |
45bdbcfd HH |
9344 | if (cpu_has_secondary_exec_ctrls()) |
9345 | vmcs_set_secondary_exec_control(secondary_exec_ctl); | |
feda805f | 9346 | |
37e4c997 HZ |
9347 | if (nested_vmx_allowed(vcpu)) |
9348 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= | |
9349 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
9350 | else | |
9351 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= | |
9352 | ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
8322ebbb DM |
9353 | |
9354 | if (nested_vmx_allowed(vcpu)) | |
9355 | nested_vmx_cr_fixed1_bits_update(vcpu); | |
0e851880 SY |
9356 | } |
9357 | ||
d4330ef2 JR |
9358 | static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
9359 | { | |
7b8050f5 NHE |
9360 | if (func == 1 && nested) |
9361 | entry->ecx |= bit(X86_FEATURE_VMX); | |
d4330ef2 JR |
9362 | } |
9363 | ||
25d92081 YZ |
9364 | static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu, |
9365 | struct x86_exception *fault) | |
9366 | { | |
533558bc JK |
9367 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
9368 | u32 exit_reason; | |
25d92081 YZ |
9369 | |
9370 | if (fault->error_code & PFERR_RSVD_MASK) | |
533558bc | 9371 | exit_reason = EXIT_REASON_EPT_MISCONFIG; |
25d92081 | 9372 | else |
533558bc JK |
9373 | exit_reason = EXIT_REASON_EPT_VIOLATION; |
9374 | nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification); | |
25d92081 YZ |
9375 | vmcs12->guest_physical_address = fault->address; |
9376 | } | |
9377 | ||
155a97a3 NHE |
9378 | /* Callbacks for nested_ept_init_mmu_context: */ |
9379 | ||
9380 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu) | |
9381 | { | |
9382 | /* return the page table to be shadowed - in our case, EPT12 */ | |
9383 | return get_vmcs12(vcpu)->ept_pointer; | |
9384 | } | |
9385 | ||
ae1e2d10 | 9386 | static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu) |
155a97a3 | 9387 | { |
ae1e2d10 PB |
9388 | u64 eptp; |
9389 | ||
ad896af0 | 9390 | WARN_ON(mmu_is_nested(vcpu)); |
ae1e2d10 PB |
9391 | eptp = nested_ept_get_cr3(vcpu); |
9392 | if ((eptp & VMX_EPT_AD_ENABLE_BIT) && !enable_ept_ad_bits) | |
9393 | return 1; | |
9394 | ||
9395 | kvm_mmu_unload(vcpu); | |
ad896af0 | 9396 | kvm_init_shadow_ept_mmu(vcpu, |
b9c237bb | 9397 | to_vmx(vcpu)->nested.nested_vmx_ept_caps & |
ae1e2d10 PB |
9398 | VMX_EPT_EXECUTE_ONLY_BIT, |
9399 | eptp & VMX_EPT_AD_ENABLE_BIT); | |
155a97a3 NHE |
9400 | vcpu->arch.mmu.set_cr3 = vmx_set_cr3; |
9401 | vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3; | |
9402 | vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault; | |
9403 | ||
9404 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
ae1e2d10 | 9405 | return 0; |
155a97a3 NHE |
9406 | } |
9407 | ||
9408 | static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
9409 | { | |
9410 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
9411 | } | |
9412 | ||
19d5f10b EK |
9413 | static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, |
9414 | u16 error_code) | |
9415 | { | |
9416 | bool inequality, bit; | |
9417 | ||
9418 | bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0; | |
9419 | inequality = | |
9420 | (error_code & vmcs12->page_fault_error_code_mask) != | |
9421 | vmcs12->page_fault_error_code_match; | |
9422 | return inequality ^ bit; | |
9423 | } | |
9424 | ||
feaf0c7d GN |
9425 | static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu, |
9426 | struct x86_exception *fault) | |
9427 | { | |
9428 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
9429 | ||
9430 | WARN_ON(!is_guest_mode(vcpu)); | |
9431 | ||
19d5f10b | 9432 | if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code)) |
533558bc JK |
9433 | nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason, |
9434 | vmcs_read32(VM_EXIT_INTR_INFO), | |
9435 | vmcs_readl(EXIT_QUALIFICATION)); | |
feaf0c7d GN |
9436 | else |
9437 | kvm_inject_page_fault(vcpu, fault); | |
9438 | } | |
9439 | ||
6beb7bd5 JM |
9440 | static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu, |
9441 | struct vmcs12 *vmcs12); | |
9442 | ||
9443 | static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu, | |
a2bcba50 WL |
9444 | struct vmcs12 *vmcs12) |
9445 | { | |
9446 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6beb7bd5 | 9447 | u64 hpa; |
a2bcba50 WL |
9448 | |
9449 | if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
a2bcba50 WL |
9450 | /* |
9451 | * Translate L1 physical address to host physical | |
9452 | * address for vmcs02. Keep the page pinned, so this | |
9453 | * physical address remains valid. We keep a reference | |
9454 | * to it so we can release it later. | |
9455 | */ | |
9456 | if (vmx->nested.apic_access_page) /* shouldn't happen */ | |
9457 | nested_release_page(vmx->nested.apic_access_page); | |
9458 | vmx->nested.apic_access_page = | |
9459 | nested_get_page(vcpu, vmcs12->apic_access_addr); | |
6beb7bd5 JM |
9460 | /* |
9461 | * If translation failed, no matter: This feature asks | |
9462 | * to exit when accessing the given address, and if it | |
9463 | * can never be accessed, this feature won't do | |
9464 | * anything anyway. | |
9465 | */ | |
9466 | if (vmx->nested.apic_access_page) { | |
9467 | hpa = page_to_phys(vmx->nested.apic_access_page); | |
9468 | vmcs_write64(APIC_ACCESS_ADDR, hpa); | |
9469 | } else { | |
9470 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, | |
9471 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
9472 | } | |
9473 | } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) && | |
9474 | cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { | |
9475 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
9476 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
9477 | kvm_vcpu_reload_apic_access_page(vcpu); | |
a2bcba50 | 9478 | } |
a7c0b07d WL |
9479 | |
9480 | if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { | |
a7c0b07d WL |
9481 | if (vmx->nested.virtual_apic_page) /* shouldn't happen */ |
9482 | nested_release_page(vmx->nested.virtual_apic_page); | |
9483 | vmx->nested.virtual_apic_page = | |
9484 | nested_get_page(vcpu, vmcs12->virtual_apic_page_addr); | |
9485 | ||
9486 | /* | |
6beb7bd5 JM |
9487 | * If translation failed, VM entry will fail because |
9488 | * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull. | |
9489 | * Failing the vm entry is _not_ what the processor | |
9490 | * does but it's basically the only possibility we | |
9491 | * have. We could still enter the guest if CR8 load | |
9492 | * exits are enabled, CR8 store exits are enabled, and | |
9493 | * virtualize APIC access is disabled; in this case | |
9494 | * the processor would never use the TPR shadow and we | |
9495 | * could simply clear the bit from the execution | |
9496 | * control. But such a configuration is useless, so | |
9497 | * let's keep the code simple. | |
a7c0b07d | 9498 | */ |
6beb7bd5 JM |
9499 | if (vmx->nested.virtual_apic_page) { |
9500 | hpa = page_to_phys(vmx->nested.virtual_apic_page); | |
9501 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa); | |
9502 | } | |
a7c0b07d WL |
9503 | } |
9504 | ||
705699a1 | 9505 | if (nested_cpu_has_posted_intr(vmcs12)) { |
705699a1 WV |
9506 | if (vmx->nested.pi_desc_page) { /* shouldn't happen */ |
9507 | kunmap(vmx->nested.pi_desc_page); | |
9508 | nested_release_page(vmx->nested.pi_desc_page); | |
9509 | } | |
9510 | vmx->nested.pi_desc_page = | |
9511 | nested_get_page(vcpu, vmcs12->posted_intr_desc_addr); | |
705699a1 WV |
9512 | vmx->nested.pi_desc = |
9513 | (struct pi_desc *)kmap(vmx->nested.pi_desc_page); | |
9514 | if (!vmx->nested.pi_desc) { | |
9515 | nested_release_page_clean(vmx->nested.pi_desc_page); | |
6beb7bd5 | 9516 | return; |
705699a1 WV |
9517 | } |
9518 | vmx->nested.pi_desc = | |
9519 | (struct pi_desc *)((void *)vmx->nested.pi_desc + | |
9520 | (unsigned long)(vmcs12->posted_intr_desc_addr & | |
9521 | (PAGE_SIZE - 1))); | |
6beb7bd5 JM |
9522 | vmcs_write64(POSTED_INTR_DESC_ADDR, |
9523 | page_to_phys(vmx->nested.pi_desc_page) + | |
9524 | (unsigned long)(vmcs12->posted_intr_desc_addr & | |
9525 | (PAGE_SIZE - 1))); | |
705699a1 | 9526 | } |
6beb7bd5 JM |
9527 | if (cpu_has_vmx_msr_bitmap() && |
9528 | nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) && | |
9529 | nested_vmx_merge_msr_bitmap(vcpu, vmcs12)) | |
9530 | ; | |
9531 | else | |
9532 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, | |
9533 | CPU_BASED_USE_MSR_BITMAPS); | |
a2bcba50 WL |
9534 | } |
9535 | ||
f4124500 JK |
9536 | static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu) |
9537 | { | |
9538 | u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value; | |
9539 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9540 | ||
9541 | if (vcpu->arch.virtual_tsc_khz == 0) | |
9542 | return; | |
9543 | ||
9544 | /* Make sure short timeouts reliably trigger an immediate vmexit. | |
9545 | * hrtimer_start does not guarantee this. */ | |
9546 | if (preemption_timeout <= 1) { | |
9547 | vmx_preemption_timer_fn(&vmx->nested.preemption_timer); | |
9548 | return; | |
9549 | } | |
9550 | ||
9551 | preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
9552 | preemption_timeout *= 1000000; | |
9553 | do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz); | |
9554 | hrtimer_start(&vmx->nested.preemption_timer, | |
9555 | ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL); | |
9556 | } | |
9557 | ||
3af18d9c WV |
9558 | static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, |
9559 | struct vmcs12 *vmcs12) | |
9560 | { | |
9561 | int maxphyaddr; | |
9562 | u64 addr; | |
9563 | ||
9564 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) | |
9565 | return 0; | |
9566 | ||
9567 | if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) { | |
9568 | WARN_ON(1); | |
9569 | return -EINVAL; | |
9570 | } | |
9571 | maxphyaddr = cpuid_maxphyaddr(vcpu); | |
9572 | ||
9573 | if (!PAGE_ALIGNED(vmcs12->msr_bitmap) || | |
9574 | ((addr + PAGE_SIZE) >> maxphyaddr)) | |
9575 | return -EINVAL; | |
9576 | ||
9577 | return 0; | |
9578 | } | |
9579 | ||
9580 | /* | |
9581 | * Merge L0's and L1's MSR bitmap, return false to indicate that | |
9582 | * we do not use the hardware. | |
9583 | */ | |
9584 | static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu, | |
9585 | struct vmcs12 *vmcs12) | |
9586 | { | |
82f0dd4b | 9587 | int msr; |
f2b93280 | 9588 | struct page *page; |
d048c098 RK |
9589 | unsigned long *msr_bitmap_l1; |
9590 | unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap; | |
f2b93280 | 9591 | |
d048c098 | 9592 | /* This shortcut is ok because we support only x2APIC MSRs so far. */ |
f2b93280 WV |
9593 | if (!nested_cpu_has_virt_x2apic_mode(vmcs12)) |
9594 | return false; | |
9595 | ||
9596 | page = nested_get_page(vcpu, vmcs12->msr_bitmap); | |
05d8d346 | 9597 | if (!page) |
f2b93280 | 9598 | return false; |
d048c098 | 9599 | msr_bitmap_l1 = (unsigned long *)kmap(page); |
f2b93280 | 9600 | |
d048c098 RK |
9601 | memset(msr_bitmap_l0, 0xff, PAGE_SIZE); |
9602 | ||
f2b93280 | 9603 | if (nested_cpu_has_virt_x2apic_mode(vmcs12)) { |
82f0dd4b WV |
9604 | if (nested_cpu_has_apic_reg_virt(vmcs12)) |
9605 | for (msr = 0x800; msr <= 0x8ff; msr++) | |
9606 | nested_vmx_disable_intercept_for_msr( | |
d048c098 | 9607 | msr_bitmap_l1, msr_bitmap_l0, |
82f0dd4b | 9608 | msr, MSR_TYPE_R); |
d048c098 RK |
9609 | |
9610 | nested_vmx_disable_intercept_for_msr( | |
9611 | msr_bitmap_l1, msr_bitmap_l0, | |
f2b93280 WV |
9612 | APIC_BASE_MSR + (APIC_TASKPRI >> 4), |
9613 | MSR_TYPE_R | MSR_TYPE_W); | |
d048c098 | 9614 | |
608406e2 | 9615 | if (nested_cpu_has_vid(vmcs12)) { |
608406e2 | 9616 | nested_vmx_disable_intercept_for_msr( |
d048c098 | 9617 | msr_bitmap_l1, msr_bitmap_l0, |
608406e2 WV |
9618 | APIC_BASE_MSR + (APIC_EOI >> 4), |
9619 | MSR_TYPE_W); | |
9620 | nested_vmx_disable_intercept_for_msr( | |
d048c098 | 9621 | msr_bitmap_l1, msr_bitmap_l0, |
608406e2 WV |
9622 | APIC_BASE_MSR + (APIC_SELF_IPI >> 4), |
9623 | MSR_TYPE_W); | |
9624 | } | |
82f0dd4b | 9625 | } |
f2b93280 WV |
9626 | kunmap(page); |
9627 | nested_release_page_clean(page); | |
9628 | ||
9629 | return true; | |
9630 | } | |
9631 | ||
9632 | static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu, | |
9633 | struct vmcs12 *vmcs12) | |
9634 | { | |
82f0dd4b | 9635 | if (!nested_cpu_has_virt_x2apic_mode(vmcs12) && |
608406e2 | 9636 | !nested_cpu_has_apic_reg_virt(vmcs12) && |
705699a1 WV |
9637 | !nested_cpu_has_vid(vmcs12) && |
9638 | !nested_cpu_has_posted_intr(vmcs12)) | |
f2b93280 WV |
9639 | return 0; |
9640 | ||
9641 | /* | |
9642 | * If virtualize x2apic mode is enabled, | |
9643 | * virtualize apic access must be disabled. | |
9644 | */ | |
82f0dd4b WV |
9645 | if (nested_cpu_has_virt_x2apic_mode(vmcs12) && |
9646 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
f2b93280 WV |
9647 | return -EINVAL; |
9648 | ||
608406e2 WV |
9649 | /* |
9650 | * If virtual interrupt delivery is enabled, | |
9651 | * we must exit on external interrupts. | |
9652 | */ | |
9653 | if (nested_cpu_has_vid(vmcs12) && | |
9654 | !nested_exit_on_intr(vcpu)) | |
9655 | return -EINVAL; | |
9656 | ||
705699a1 WV |
9657 | /* |
9658 | * bits 15:8 should be zero in posted_intr_nv, | |
9659 | * the descriptor address has been already checked | |
9660 | * in nested_get_vmcs12_pages. | |
9661 | */ | |
9662 | if (nested_cpu_has_posted_intr(vmcs12) && | |
9663 | (!nested_cpu_has_vid(vmcs12) || | |
9664 | !nested_exit_intr_ack_set(vcpu) || | |
9665 | vmcs12->posted_intr_nv & 0xff00)) | |
9666 | return -EINVAL; | |
9667 | ||
f2b93280 WV |
9668 | /* tpr shadow is needed by all apicv features. */ |
9669 | if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
9670 | return -EINVAL; | |
9671 | ||
9672 | return 0; | |
3af18d9c WV |
9673 | } |
9674 | ||
e9ac033e EK |
9675 | static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu, |
9676 | unsigned long count_field, | |
92d71bc6 | 9677 | unsigned long addr_field) |
ff651cb6 | 9678 | { |
92d71bc6 | 9679 | int maxphyaddr; |
e9ac033e EK |
9680 | u64 count, addr; |
9681 | ||
9682 | if (vmcs12_read_any(vcpu, count_field, &count) || | |
9683 | vmcs12_read_any(vcpu, addr_field, &addr)) { | |
9684 | WARN_ON(1); | |
9685 | return -EINVAL; | |
9686 | } | |
9687 | if (count == 0) | |
9688 | return 0; | |
92d71bc6 | 9689 | maxphyaddr = cpuid_maxphyaddr(vcpu); |
e9ac033e EK |
9690 | if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr || |
9691 | (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) { | |
bbe41b95 | 9692 | pr_debug_ratelimited( |
e9ac033e EK |
9693 | "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)", |
9694 | addr_field, maxphyaddr, count, addr); | |
9695 | return -EINVAL; | |
9696 | } | |
9697 | return 0; | |
9698 | } | |
9699 | ||
9700 | static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu, | |
9701 | struct vmcs12 *vmcs12) | |
9702 | { | |
e9ac033e EK |
9703 | if (vmcs12->vm_exit_msr_load_count == 0 && |
9704 | vmcs12->vm_exit_msr_store_count == 0 && | |
9705 | vmcs12->vm_entry_msr_load_count == 0) | |
9706 | return 0; /* Fast path */ | |
e9ac033e | 9707 | if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT, |
92d71bc6 | 9708 | VM_EXIT_MSR_LOAD_ADDR) || |
e9ac033e | 9709 | nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT, |
92d71bc6 | 9710 | VM_EXIT_MSR_STORE_ADDR) || |
e9ac033e | 9711 | nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT, |
92d71bc6 | 9712 | VM_ENTRY_MSR_LOAD_ADDR)) |
e9ac033e EK |
9713 | return -EINVAL; |
9714 | return 0; | |
9715 | } | |
9716 | ||
9717 | static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu, | |
9718 | struct vmx_msr_entry *e) | |
9719 | { | |
9720 | /* x2APIC MSR accesses are not allowed */ | |
8a9781f7 | 9721 | if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8) |
e9ac033e EK |
9722 | return -EINVAL; |
9723 | if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */ | |
9724 | e->index == MSR_IA32_UCODE_REV) | |
9725 | return -EINVAL; | |
9726 | if (e->reserved != 0) | |
ff651cb6 WV |
9727 | return -EINVAL; |
9728 | return 0; | |
9729 | } | |
9730 | ||
e9ac033e EK |
9731 | static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu, |
9732 | struct vmx_msr_entry *e) | |
ff651cb6 WV |
9733 | { |
9734 | if (e->index == MSR_FS_BASE || | |
9735 | e->index == MSR_GS_BASE || | |
e9ac033e EK |
9736 | e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */ |
9737 | nested_vmx_msr_check_common(vcpu, e)) | |
9738 | return -EINVAL; | |
9739 | return 0; | |
9740 | } | |
9741 | ||
9742 | static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu, | |
9743 | struct vmx_msr_entry *e) | |
9744 | { | |
9745 | if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */ | |
9746 | nested_vmx_msr_check_common(vcpu, e)) | |
ff651cb6 WV |
9747 | return -EINVAL; |
9748 | return 0; | |
9749 | } | |
9750 | ||
9751 | /* | |
9752 | * Load guest's/host's msr at nested entry/exit. | |
9753 | * return 0 for success, entry index for failure. | |
9754 | */ | |
9755 | static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) | |
9756 | { | |
9757 | u32 i; | |
9758 | struct vmx_msr_entry e; | |
9759 | struct msr_data msr; | |
9760 | ||
9761 | msr.host_initiated = false; | |
9762 | for (i = 0; i < count; i++) { | |
54bf36aa PB |
9763 | if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e), |
9764 | &e, sizeof(e))) { | |
bbe41b95 | 9765 | pr_debug_ratelimited( |
e9ac033e EK |
9766 | "%s cannot read MSR entry (%u, 0x%08llx)\n", |
9767 | __func__, i, gpa + i * sizeof(e)); | |
ff651cb6 | 9768 | goto fail; |
e9ac033e EK |
9769 | } |
9770 | if (nested_vmx_load_msr_check(vcpu, &e)) { | |
bbe41b95 | 9771 | pr_debug_ratelimited( |
e9ac033e EK |
9772 | "%s check failed (%u, 0x%x, 0x%x)\n", |
9773 | __func__, i, e.index, e.reserved); | |
9774 | goto fail; | |
9775 | } | |
ff651cb6 WV |
9776 | msr.index = e.index; |
9777 | msr.data = e.value; | |
e9ac033e | 9778 | if (kvm_set_msr(vcpu, &msr)) { |
bbe41b95 | 9779 | pr_debug_ratelimited( |
e9ac033e EK |
9780 | "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", |
9781 | __func__, i, e.index, e.value); | |
ff651cb6 | 9782 | goto fail; |
e9ac033e | 9783 | } |
ff651cb6 WV |
9784 | } |
9785 | return 0; | |
9786 | fail: | |
9787 | return i + 1; | |
9788 | } | |
9789 | ||
9790 | static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) | |
9791 | { | |
9792 | u32 i; | |
9793 | struct vmx_msr_entry e; | |
9794 | ||
9795 | for (i = 0; i < count; i++) { | |
609e36d3 | 9796 | struct msr_data msr_info; |
54bf36aa PB |
9797 | if (kvm_vcpu_read_guest(vcpu, |
9798 | gpa + i * sizeof(e), | |
9799 | &e, 2 * sizeof(u32))) { | |
bbe41b95 | 9800 | pr_debug_ratelimited( |
e9ac033e EK |
9801 | "%s cannot read MSR entry (%u, 0x%08llx)\n", |
9802 | __func__, i, gpa + i * sizeof(e)); | |
ff651cb6 | 9803 | return -EINVAL; |
e9ac033e EK |
9804 | } |
9805 | if (nested_vmx_store_msr_check(vcpu, &e)) { | |
bbe41b95 | 9806 | pr_debug_ratelimited( |
e9ac033e EK |
9807 | "%s check failed (%u, 0x%x, 0x%x)\n", |
9808 | __func__, i, e.index, e.reserved); | |
ff651cb6 | 9809 | return -EINVAL; |
e9ac033e | 9810 | } |
609e36d3 PB |
9811 | msr_info.host_initiated = false; |
9812 | msr_info.index = e.index; | |
9813 | if (kvm_get_msr(vcpu, &msr_info)) { | |
bbe41b95 | 9814 | pr_debug_ratelimited( |
e9ac033e EK |
9815 | "%s cannot read MSR (%u, 0x%x)\n", |
9816 | __func__, i, e.index); | |
9817 | return -EINVAL; | |
9818 | } | |
54bf36aa PB |
9819 | if (kvm_vcpu_write_guest(vcpu, |
9820 | gpa + i * sizeof(e) + | |
9821 | offsetof(struct vmx_msr_entry, value), | |
9822 | &msr_info.data, sizeof(msr_info.data))) { | |
bbe41b95 | 9823 | pr_debug_ratelimited( |
e9ac033e | 9824 | "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", |
609e36d3 | 9825 | __func__, i, e.index, msr_info.data); |
e9ac033e EK |
9826 | return -EINVAL; |
9827 | } | |
ff651cb6 WV |
9828 | } |
9829 | return 0; | |
9830 | } | |
9831 | ||
1dc35dac LP |
9832 | static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val) |
9833 | { | |
9834 | unsigned long invalid_mask; | |
9835 | ||
9836 | invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu); | |
9837 | return (val & invalid_mask) == 0; | |
9838 | } | |
9839 | ||
9ed38ffa LP |
9840 | /* |
9841 | * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are | |
9842 | * emulating VM entry into a guest with EPT enabled. | |
9843 | * Returns 0 on success, 1 on failure. Invalid state exit qualification code | |
9844 | * is assigned to entry_failure_code on failure. | |
9845 | */ | |
9846 | static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept, | |
ca0bde28 | 9847 | u32 *entry_failure_code) |
9ed38ffa | 9848 | { |
9ed38ffa | 9849 | if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) { |
1dc35dac | 9850 | if (!nested_cr3_valid(vcpu, cr3)) { |
9ed38ffa LP |
9851 | *entry_failure_code = ENTRY_FAIL_DEFAULT; |
9852 | return 1; | |
9853 | } | |
9854 | ||
9855 | /* | |
9856 | * If PAE paging and EPT are both on, CR3 is not used by the CPU and | |
9857 | * must not be dereferenced. | |
9858 | */ | |
9859 | if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) && | |
9860 | !nested_ept) { | |
9861 | if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) { | |
9862 | *entry_failure_code = ENTRY_FAIL_PDPTE; | |
9863 | return 1; | |
9864 | } | |
9865 | } | |
9866 | ||
9867 | vcpu->arch.cr3 = cr3; | |
9868 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
9869 | } | |
9870 | ||
9871 | kvm_mmu_reset_context(vcpu); | |
9872 | return 0; | |
9873 | } | |
9874 | ||
fe3ef05c NHE |
9875 | /* |
9876 | * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested | |
9877 | * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it | |
b4619660 | 9878 | * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2 |
fe3ef05c NHE |
9879 | * guest in a way that will both be appropriate to L1's requests, and our |
9880 | * needs. In addition to modifying the active vmcs (which is vmcs02), this | |
9881 | * function also has additional necessary side-effects, like setting various | |
9882 | * vcpu->arch fields. | |
ee146c1c LP |
9883 | * Returns 0 on success, 1 on failure. Invalid state exit qualification code |
9884 | * is assigned to entry_failure_code on failure. | |
fe3ef05c | 9885 | */ |
ee146c1c | 9886 | static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, |
ca0bde28 | 9887 | bool from_vmentry, u32 *entry_failure_code) |
fe3ef05c NHE |
9888 | { |
9889 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9890 | u32 exec_control; | |
9891 | ||
9892 | vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector); | |
9893 | vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector); | |
9894 | vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector); | |
9895 | vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector); | |
9896 | vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector); | |
9897 | vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector); | |
9898 | vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector); | |
9899 | vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector); | |
9900 | vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit); | |
9901 | vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit); | |
9902 | vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit); | |
9903 | vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit); | |
9904 | vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit); | |
9905 | vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit); | |
9906 | vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit); | |
9907 | vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit); | |
9908 | vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit); | |
9909 | vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit); | |
9910 | vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes); | |
9911 | vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes); | |
9912 | vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes); | |
9913 | vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes); | |
9914 | vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes); | |
9915 | vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes); | |
9916 | vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes); | |
9917 | vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes); | |
9918 | vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base); | |
9919 | vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base); | |
9920 | vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base); | |
9921 | vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base); | |
9922 | vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base); | |
9923 | vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base); | |
9924 | vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base); | |
9925 | vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base); | |
9926 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base); | |
9927 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base); | |
9928 | ||
cf8b84f4 JM |
9929 | if (from_vmentry && |
9930 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) { | |
2996fca0 JK |
9931 | kvm_set_dr(vcpu, 7, vmcs12->guest_dr7); |
9932 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl); | |
9933 | } else { | |
9934 | kvm_set_dr(vcpu, 7, vcpu->arch.dr7); | |
9935 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl); | |
9936 | } | |
cf8b84f4 JM |
9937 | if (from_vmentry) { |
9938 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
9939 | vmcs12->vm_entry_intr_info_field); | |
9940 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, | |
9941 | vmcs12->vm_entry_exception_error_code); | |
9942 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
9943 | vmcs12->vm_entry_instruction_len); | |
9944 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
9945 | vmcs12->guest_interruptibility_info); | |
9946 | } else { | |
9947 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); | |
9948 | } | |
fe3ef05c | 9949 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs); |
63fbf59f | 9950 | vmx_set_rflags(vcpu, vmcs12->guest_rflags); |
fe3ef05c NHE |
9951 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, |
9952 | vmcs12->guest_pending_dbg_exceptions); | |
9953 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp); | |
9954 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip); | |
9955 | ||
81dc01f7 WL |
9956 | if (nested_cpu_has_xsaves(vmcs12)) |
9957 | vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap); | |
fe3ef05c NHE |
9958 | vmcs_write64(VMCS_LINK_POINTER, -1ull); |
9959 | ||
f4124500 | 9960 | exec_control = vmcs12->pin_based_vm_exec_control; |
9314006d PB |
9961 | |
9962 | /* Preemption timer setting is only taken from vmcs01. */ | |
705699a1 | 9963 | exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; |
9314006d PB |
9964 | exec_control |= vmcs_config.pin_based_exec_ctrl; |
9965 | if (vmx->hv_deadline_tsc == -1) | |
9966 | exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
705699a1 | 9967 | |
9314006d | 9968 | /* Posted interrupts setting is only taken from vmcs12. */ |
705699a1 WV |
9969 | if (nested_cpu_has_posted_intr(vmcs12)) { |
9970 | /* | |
9971 | * Note that we use L0's vector here and in | |
9972 | * vmx_deliver_nested_posted_interrupt. | |
9973 | */ | |
9974 | vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv; | |
9975 | vmx->nested.pi_pending = false; | |
0bcf261c | 9976 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); |
6beb7bd5 | 9977 | } else { |
705699a1 | 9978 | exec_control &= ~PIN_BASED_POSTED_INTR; |
6beb7bd5 | 9979 | } |
705699a1 | 9980 | |
f4124500 | 9981 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control); |
fe3ef05c | 9982 | |
f4124500 JK |
9983 | vmx->nested.preemption_timer_expired = false; |
9984 | if (nested_cpu_has_preemption_timer(vmcs12)) | |
9985 | vmx_start_preemption_timer(vcpu); | |
0238ea91 | 9986 | |
fe3ef05c NHE |
9987 | /* |
9988 | * Whether page-faults are trapped is determined by a combination of | |
9989 | * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF. | |
9990 | * If enable_ept, L0 doesn't care about page faults and we should | |
9991 | * set all of these to L1's desires. However, if !enable_ept, L0 does | |
9992 | * care about (at least some) page faults, and because it is not easy | |
9993 | * (if at all possible?) to merge L0 and L1's desires, we simply ask | |
9994 | * to exit on each and every L2 page fault. This is done by setting | |
9995 | * MASK=MATCH=0 and (see below) EB.PF=1. | |
9996 | * Note that below we don't need special code to set EB.PF beyond the | |
9997 | * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept, | |
9998 | * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when | |
9999 | * !enable_ept, EB.PF is 1, so the "or" will always be 1. | |
10000 | * | |
10001 | * A problem with this approach (when !enable_ept) is that L1 may be | |
10002 | * injected with more page faults than it asked for. This could have | |
10003 | * caused problems, but in practice existing hypervisors don't care. | |
10004 | * To fix this, we will need to emulate the PFEC checking (on the L1 | |
10005 | * page tables), using walk_addr(), when injecting PFs to L1. | |
10006 | */ | |
10007 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, | |
10008 | enable_ept ? vmcs12->page_fault_error_code_mask : 0); | |
10009 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, | |
10010 | enable_ept ? vmcs12->page_fault_error_code_match : 0); | |
10011 | ||
10012 | if (cpu_has_secondary_exec_ctrls()) { | |
f4124500 | 10013 | exec_control = vmx_secondary_exec_control(vmx); |
e2821620 | 10014 | |
fe3ef05c | 10015 | /* Take the following fields only from vmcs12 */ |
696dfd95 | 10016 | exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
b3a2a907 | 10017 | SECONDARY_EXEC_RDTSCP | |
696dfd95 | 10018 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
dfa169bb | 10019 | SECONDARY_EXEC_APIC_REGISTER_VIRT); |
fe3ef05c NHE |
10020 | if (nested_cpu_has(vmcs12, |
10021 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) | |
10022 | exec_control |= vmcs12->secondary_vm_exec_control; | |
10023 | ||
608406e2 WV |
10024 | if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { |
10025 | vmcs_write64(EOI_EXIT_BITMAP0, | |
10026 | vmcs12->eoi_exit_bitmap0); | |
10027 | vmcs_write64(EOI_EXIT_BITMAP1, | |
10028 | vmcs12->eoi_exit_bitmap1); | |
10029 | vmcs_write64(EOI_EXIT_BITMAP2, | |
10030 | vmcs12->eoi_exit_bitmap2); | |
10031 | vmcs_write64(EOI_EXIT_BITMAP3, | |
10032 | vmcs12->eoi_exit_bitmap3); | |
10033 | vmcs_write16(GUEST_INTR_STATUS, | |
10034 | vmcs12->guest_intr_status); | |
10035 | } | |
10036 | ||
6beb7bd5 JM |
10037 | /* |
10038 | * Write an illegal value to APIC_ACCESS_ADDR. Later, | |
10039 | * nested_get_vmcs12_pages will either fix it up or | |
10040 | * remove the VM execution control. | |
10041 | */ | |
10042 | if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) | |
10043 | vmcs_write64(APIC_ACCESS_ADDR, -1ull); | |
10044 | ||
fe3ef05c NHE |
10045 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
10046 | } | |
10047 | ||
10048 | ||
10049 | /* | |
10050 | * Set host-state according to L0's settings (vmcs12 is irrelevant here) | |
10051 | * Some constant fields are set here by vmx_set_constant_host_state(). | |
10052 | * Other fields are different per CPU, and will be set later when | |
10053 | * vmx_vcpu_load() is called, and when vmx_save_host_state() is called. | |
10054 | */ | |
a547c6db | 10055 | vmx_set_constant_host_state(vmx); |
fe3ef05c | 10056 | |
83bafef1 JM |
10057 | /* |
10058 | * Set the MSR load/store lists to match L0's settings. | |
10059 | */ | |
10060 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); | |
10061 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr); | |
10062 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host)); | |
10063 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr); | |
10064 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); | |
10065 | ||
fe3ef05c NHE |
10066 | /* |
10067 | * HOST_RSP is normally set correctly in vmx_vcpu_run() just before | |
10068 | * entry, but only if the current (host) sp changed from the value | |
10069 | * we wrote last (vmx->host_rsp). This cache is no longer relevant | |
10070 | * if we switch vmcs, and rather than hold a separate cache per vmcs, | |
10071 | * here we just force the write to happen on entry. | |
10072 | */ | |
10073 | vmx->host_rsp = 0; | |
10074 | ||
10075 | exec_control = vmx_exec_control(vmx); /* L0's desires */ | |
10076 | exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
10077 | exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
10078 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
10079 | exec_control |= vmcs12->cpu_based_vm_exec_control; | |
a7c0b07d | 10080 | |
6beb7bd5 JM |
10081 | /* |
10082 | * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if | |
10083 | * nested_get_vmcs12_pages can't fix it up, the illegal value | |
10084 | * will result in a VM entry failure. | |
10085 | */ | |
a7c0b07d | 10086 | if (exec_control & CPU_BASED_TPR_SHADOW) { |
6beb7bd5 | 10087 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull); |
a7c0b07d WL |
10088 | vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold); |
10089 | } | |
10090 | ||
fe3ef05c | 10091 | /* |
3af18d9c | 10092 | * Merging of IO bitmap not currently supported. |
fe3ef05c NHE |
10093 | * Rather, exit every time. |
10094 | */ | |
fe3ef05c NHE |
10095 | exec_control &= ~CPU_BASED_USE_IO_BITMAPS; |
10096 | exec_control |= CPU_BASED_UNCOND_IO_EXITING; | |
10097 | ||
10098 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); | |
10099 | ||
10100 | /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the | |
10101 | * bitwise-or of what L1 wants to trap for L2, and what we want to | |
10102 | * trap. Note that CR0.TS also needs updating - we do this later. | |
10103 | */ | |
10104 | update_exception_bitmap(vcpu); | |
10105 | vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask; | |
10106 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
10107 | ||
8049d651 NHE |
10108 | /* L2->L1 exit controls are emulated - the hardware exit is to L0 so |
10109 | * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER | |
10110 | * bits are further modified by vmx_set_efer() below. | |
10111 | */ | |
f4124500 | 10112 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
8049d651 NHE |
10113 | |
10114 | /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are | |
10115 | * emulated by vmx_set_efer(), below. | |
10116 | */ | |
2961e876 | 10117 | vm_entry_controls_init(vmx, |
8049d651 NHE |
10118 | (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER & |
10119 | ~VM_ENTRY_IA32E_MODE) | | |
fe3ef05c NHE |
10120 | (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE)); |
10121 | ||
cf8b84f4 JM |
10122 | if (from_vmentry && |
10123 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) { | |
fe3ef05c | 10124 | vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat); |
44811c02 | 10125 | vcpu->arch.pat = vmcs12->guest_ia32_pat; |
cf8b84f4 | 10126 | } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { |
fe3ef05c | 10127 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); |
cf8b84f4 | 10128 | } |
fe3ef05c NHE |
10129 | |
10130 | set_cr4_guest_host_mask(vmx); | |
10131 | ||
cf8b84f4 JM |
10132 | if (from_vmentry && |
10133 | vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) | |
36be0b9d PB |
10134 | vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs); |
10135 | ||
27fc51b2 NHE |
10136 | if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING) |
10137 | vmcs_write64(TSC_OFFSET, | |
ea26e4ec | 10138 | vcpu->arch.tsc_offset + vmcs12->tsc_offset); |
27fc51b2 | 10139 | else |
ea26e4ec | 10140 | vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); |
c95ba92a PF |
10141 | if (kvm_has_tsc_control) |
10142 | decache_tsc_multiplier(vmx); | |
fe3ef05c NHE |
10143 | |
10144 | if (enable_vpid) { | |
10145 | /* | |
5c614b35 WL |
10146 | * There is no direct mapping between vpid02 and vpid12, the |
10147 | * vpid02 is per-vCPU for L0 and reused while the value of | |
10148 | * vpid12 is changed w/ one invvpid during nested vmentry. | |
10149 | * The vpid12 is allocated by L1 for L2, so it will not | |
10150 | * influence global bitmap(for vpid01 and vpid02 allocation) | |
10151 | * even if spawn a lot of nested vCPUs. | |
fe3ef05c | 10152 | */ |
5c614b35 WL |
10153 | if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) { |
10154 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02); | |
10155 | if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) { | |
10156 | vmx->nested.last_vpid = vmcs12->virtual_processor_id; | |
10157 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02); | |
10158 | } | |
10159 | } else { | |
10160 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
10161 | vmx_flush_tlb(vcpu); | |
10162 | } | |
10163 | ||
fe3ef05c NHE |
10164 | } |
10165 | ||
155a97a3 | 10166 | if (nested_cpu_has_ept(vmcs12)) { |
ae1e2d10 PB |
10167 | if (nested_ept_init_mmu_context(vcpu)) { |
10168 | *entry_failure_code = ENTRY_FAIL_DEFAULT; | |
10169 | return 1; | |
10170 | } | |
fb6c8198 JM |
10171 | } else if (nested_cpu_has2(vmcs12, |
10172 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
10173 | vmx_flush_tlb_ept_only(vcpu); | |
155a97a3 NHE |
10174 | } |
10175 | ||
fe3ef05c | 10176 | /* |
bd7e5b08 PB |
10177 | * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those |
10178 | * bits which we consider mandatory enabled. | |
fe3ef05c NHE |
10179 | * The CR0_READ_SHADOW is what L2 should have expected to read given |
10180 | * the specifications by L1; It's not enough to take | |
10181 | * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we | |
10182 | * have more bits than L1 expected. | |
10183 | */ | |
10184 | vmx_set_cr0(vcpu, vmcs12->guest_cr0); | |
10185 | vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); | |
10186 | ||
10187 | vmx_set_cr4(vcpu, vmcs12->guest_cr4); | |
10188 | vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12)); | |
10189 | ||
cf8b84f4 JM |
10190 | if (from_vmentry && |
10191 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) | |
5a6a9748 DM |
10192 | vcpu->arch.efer = vmcs12->guest_ia32_efer; |
10193 | else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) | |
10194 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); | |
10195 | else | |
10196 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
10197 | /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */ | |
10198 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
10199 | ||
9ed38ffa | 10200 | /* Shadow page tables on either EPT or shadow page tables. */ |
7ad658b6 | 10201 | if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12), |
9ed38ffa LP |
10202 | entry_failure_code)) |
10203 | return 1; | |
7ca29de2 | 10204 | |
feaf0c7d GN |
10205 | if (!enable_ept) |
10206 | vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested; | |
10207 | ||
3633cfc3 NHE |
10208 | /* |
10209 | * L1 may access the L2's PDPTR, so save them to construct vmcs12 | |
10210 | */ | |
10211 | if (enable_ept) { | |
10212 | vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0); | |
10213 | vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1); | |
10214 | vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2); | |
10215 | vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3); | |
10216 | } | |
10217 | ||
fe3ef05c NHE |
10218 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp); |
10219 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip); | |
ee146c1c | 10220 | return 0; |
fe3ef05c NHE |
10221 | } |
10222 | ||
ca0bde28 | 10223 | static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) |
cd232ad0 | 10224 | { |
cd232ad0 | 10225 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
7c177938 | 10226 | |
6dfacadd | 10227 | if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE && |
ca0bde28 JM |
10228 | vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) |
10229 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
26539bd0 | 10230 | |
ca0bde28 JM |
10231 | if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) |
10232 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
7c177938 | 10233 | |
ca0bde28 JM |
10234 | if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) |
10235 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
f2b93280 | 10236 | |
ca0bde28 JM |
10237 | if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) |
10238 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
e9ac033e | 10239 | |
7c177938 | 10240 | if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control, |
0115f9cb | 10241 | vmx->nested.nested_vmx_procbased_ctls_low, |
b9c237bb | 10242 | vmx->nested.nested_vmx_procbased_ctls_high) || |
7c177938 | 10243 | !vmx_control_verify(vmcs12->secondary_vm_exec_control, |
b9c237bb WV |
10244 | vmx->nested.nested_vmx_secondary_ctls_low, |
10245 | vmx->nested.nested_vmx_secondary_ctls_high) || | |
7c177938 | 10246 | !vmx_control_verify(vmcs12->pin_based_vm_exec_control, |
b9c237bb WV |
10247 | vmx->nested.nested_vmx_pinbased_ctls_low, |
10248 | vmx->nested.nested_vmx_pinbased_ctls_high) || | |
7c177938 | 10249 | !vmx_control_verify(vmcs12->vm_exit_controls, |
0115f9cb | 10250 | vmx->nested.nested_vmx_exit_ctls_low, |
b9c237bb | 10251 | vmx->nested.nested_vmx_exit_ctls_high) || |
7c177938 | 10252 | !vmx_control_verify(vmcs12->vm_entry_controls, |
0115f9cb | 10253 | vmx->nested.nested_vmx_entry_ctls_low, |
b9c237bb | 10254 | vmx->nested.nested_vmx_entry_ctls_high)) |
ca0bde28 | 10255 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; |
7c177938 | 10256 | |
3899152c | 10257 | if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) || |
1dc35dac | 10258 | !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) || |
ca0bde28 JM |
10259 | !nested_cr3_valid(vcpu, vmcs12->host_cr3)) |
10260 | return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; | |
10261 | ||
10262 | return 0; | |
10263 | } | |
10264 | ||
10265 | static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, | |
10266 | u32 *exit_qual) | |
10267 | { | |
10268 | bool ia32e; | |
10269 | ||
10270 | *exit_qual = ENTRY_FAIL_DEFAULT; | |
7c177938 | 10271 | |
3899152c | 10272 | if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) || |
ca0bde28 | 10273 | !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4)) |
b428018a | 10274 | return 1; |
ca0bde28 JM |
10275 | |
10276 | if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) && | |
10277 | vmcs12->vmcs_link_pointer != -1ull) { | |
10278 | *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR; | |
b428018a | 10279 | return 1; |
7c177938 NHE |
10280 | } |
10281 | ||
384bb783 | 10282 | /* |
cb0c8cda | 10283 | * If the load IA32_EFER VM-entry control is 1, the following checks |
384bb783 JK |
10284 | * are performed on the field for the IA32_EFER MSR: |
10285 | * - Bits reserved in the IA32_EFER MSR must be 0. | |
10286 | * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of | |
10287 | * the IA-32e mode guest VM-exit control. It must also be identical | |
10288 | * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to | |
10289 | * CR0.PG) is 1. | |
10290 | */ | |
ca0bde28 JM |
10291 | if (to_vmx(vcpu)->nested.nested_run_pending && |
10292 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) { | |
384bb783 JK |
10293 | ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0; |
10294 | if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) || | |
10295 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) || | |
10296 | ((vmcs12->guest_cr0 & X86_CR0_PG) && | |
ca0bde28 | 10297 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) |
b428018a | 10298 | return 1; |
384bb783 JK |
10299 | } |
10300 | ||
10301 | /* | |
10302 | * If the load IA32_EFER VM-exit control is 1, bits reserved in the | |
10303 | * IA32_EFER MSR must be 0 in the field for that register. In addition, | |
10304 | * the values of the LMA and LME bits in the field must each be that of | |
10305 | * the host address-space size VM-exit control. | |
10306 | */ | |
10307 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) { | |
10308 | ia32e = (vmcs12->vm_exit_controls & | |
10309 | VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0; | |
10310 | if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) || | |
10311 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) || | |
ca0bde28 | 10312 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) |
b428018a | 10313 | return 1; |
ca0bde28 JM |
10314 | } |
10315 | ||
10316 | return 0; | |
10317 | } | |
10318 | ||
858e25c0 JM |
10319 | static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry) |
10320 | { | |
10321 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10322 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
10323 | struct loaded_vmcs *vmcs02; | |
858e25c0 JM |
10324 | u32 msr_entry_idx; |
10325 | u32 exit_qual; | |
10326 | ||
10327 | vmcs02 = nested_get_current_vmcs02(vmx); | |
10328 | if (!vmcs02) | |
10329 | return -ENOMEM; | |
10330 | ||
10331 | enter_guest_mode(vcpu); | |
10332 | ||
10333 | if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) | |
10334 | vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
10335 | ||
1279a6b1 | 10336 | vmx_switch_vmcs(vcpu, vmcs02); |
858e25c0 JM |
10337 | vmx_segment_cache_clear(vmx); |
10338 | ||
10339 | if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) { | |
10340 | leave_guest_mode(vcpu); | |
1279a6b1 | 10341 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); |
858e25c0 JM |
10342 | nested_vmx_entry_failure(vcpu, vmcs12, |
10343 | EXIT_REASON_INVALID_STATE, exit_qual); | |
10344 | return 1; | |
10345 | } | |
10346 | ||
10347 | nested_get_vmcs12_pages(vcpu, vmcs12); | |
10348 | ||
10349 | msr_entry_idx = nested_vmx_load_msr(vcpu, | |
10350 | vmcs12->vm_entry_msr_load_addr, | |
10351 | vmcs12->vm_entry_msr_load_count); | |
10352 | if (msr_entry_idx) { | |
10353 | leave_guest_mode(vcpu); | |
1279a6b1 | 10354 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); |
858e25c0 JM |
10355 | nested_vmx_entry_failure(vcpu, vmcs12, |
10356 | EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx); | |
10357 | return 1; | |
10358 | } | |
10359 | ||
10360 | vmcs12->launch_state = 1; | |
10361 | ||
10362 | /* | |
10363 | * Note no nested_vmx_succeed or nested_vmx_fail here. At this point | |
10364 | * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet | |
10365 | * returned as far as L1 is concerned. It will only return (and set | |
10366 | * the success flag) when L2 exits (see nested_vmx_vmexit()). | |
10367 | */ | |
10368 | return 0; | |
10369 | } | |
10370 | ||
ca0bde28 JM |
10371 | /* |
10372 | * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1 | |
10373 | * for running an L2 nested guest. | |
10374 | */ | |
10375 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch) | |
10376 | { | |
10377 | struct vmcs12 *vmcs12; | |
10378 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
ca0bde28 JM |
10379 | u32 exit_qual; |
10380 | int ret; | |
10381 | ||
10382 | if (!nested_vmx_check_permission(vcpu)) | |
10383 | return 1; | |
10384 | ||
10385 | if (!nested_vmx_check_vmcs12(vcpu)) | |
10386 | goto out; | |
10387 | ||
10388 | vmcs12 = get_vmcs12(vcpu); | |
10389 | ||
10390 | if (enable_shadow_vmcs) | |
10391 | copy_shadow_to_vmcs12(vmx); | |
10392 | ||
10393 | /* | |
10394 | * The nested entry process starts with enforcing various prerequisites | |
10395 | * on vmcs12 as required by the Intel SDM, and act appropriately when | |
10396 | * they fail: As the SDM explains, some conditions should cause the | |
10397 | * instruction to fail, while others will cause the instruction to seem | |
10398 | * to succeed, but return an EXIT_REASON_INVALID_STATE. | |
10399 | * To speed up the normal (success) code path, we should avoid checking | |
10400 | * for misconfigurations which will anyway be caught by the processor | |
10401 | * when using the merged vmcs02. | |
10402 | */ | |
10403 | if (vmcs12->launch_state == launch) { | |
10404 | nested_vmx_failValid(vcpu, | |
10405 | launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS | |
10406 | : VMXERR_VMRESUME_NONLAUNCHED_VMCS); | |
10407 | goto out; | |
10408 | } | |
10409 | ||
10410 | ret = check_vmentry_prereqs(vcpu, vmcs12); | |
10411 | if (ret) { | |
10412 | nested_vmx_failValid(vcpu, ret); | |
10413 | goto out; | |
10414 | } | |
10415 | ||
10416 | /* | |
10417 | * After this point, the trap flag no longer triggers a singlestep trap | |
10418 | * on the vm entry instructions; don't call kvm_skip_emulated_instruction. | |
10419 | * This is not 100% correct; for performance reasons, we delegate most | |
10420 | * of the checks on host state to the processor. If those fail, | |
10421 | * the singlestep trap is missed. | |
10422 | */ | |
10423 | skip_emulated_instruction(vcpu); | |
10424 | ||
10425 | ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual); | |
10426 | if (ret) { | |
10427 | nested_vmx_entry_failure(vcpu, vmcs12, | |
10428 | EXIT_REASON_INVALID_STATE, exit_qual); | |
10429 | return 1; | |
384bb783 JK |
10430 | } |
10431 | ||
7c177938 NHE |
10432 | /* |
10433 | * We're finally done with prerequisite checking, and can start with | |
10434 | * the nested entry. | |
10435 | */ | |
10436 | ||
858e25c0 JM |
10437 | ret = enter_vmx_non_root_mode(vcpu, true); |
10438 | if (ret) | |
10439 | return ret; | |
ff651cb6 | 10440 | |
6dfacadd | 10441 | if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) |
5cb56059 | 10442 | return kvm_vcpu_halt(vcpu); |
6dfacadd | 10443 | |
7af40ad3 JK |
10444 | vmx->nested.nested_run_pending = 1; |
10445 | ||
cd232ad0 | 10446 | return 1; |
eb277562 KH |
10447 | |
10448 | out: | |
6affcbed | 10449 | return kvm_skip_emulated_instruction(vcpu); |
cd232ad0 NHE |
10450 | } |
10451 | ||
4704d0be NHE |
10452 | /* |
10453 | * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date | |
10454 | * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK). | |
10455 | * This function returns the new value we should put in vmcs12.guest_cr0. | |
10456 | * It's not enough to just return the vmcs02 GUEST_CR0. Rather, | |
10457 | * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now | |
10458 | * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0 | |
10459 | * didn't trap the bit, because if L1 did, so would L0). | |
10460 | * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have | |
10461 | * been modified by L2, and L1 knows it. So just leave the old value of | |
10462 | * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0 | |
10463 | * isn't relevant, because if L0 traps this bit it can set it to anything. | |
10464 | * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have | |
10465 | * changed these bits, and therefore they need to be updated, but L0 | |
10466 | * didn't necessarily allow them to be changed in GUEST_CR0 - and rather | |
10467 | * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there. | |
10468 | */ | |
10469 | static inline unsigned long | |
10470 | vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
10471 | { | |
10472 | return | |
10473 | /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) | | |
10474 | /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) | | |
10475 | /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask | | |
10476 | vcpu->arch.cr0_guest_owned_bits)); | |
10477 | } | |
10478 | ||
10479 | static inline unsigned long | |
10480 | vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
10481 | { | |
10482 | return | |
10483 | /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) | | |
10484 | /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) | | |
10485 | /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask | | |
10486 | vcpu->arch.cr4_guest_owned_bits)); | |
10487 | } | |
10488 | ||
5f3d5799 JK |
10489 | static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu, |
10490 | struct vmcs12 *vmcs12) | |
10491 | { | |
10492 | u32 idt_vectoring; | |
10493 | unsigned int nr; | |
10494 | ||
851eb667 | 10495 | if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) { |
5f3d5799 JK |
10496 | nr = vcpu->arch.exception.nr; |
10497 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
10498 | ||
10499 | if (kvm_exception_is_soft(nr)) { | |
10500 | vmcs12->vm_exit_instruction_len = | |
10501 | vcpu->arch.event_exit_inst_len; | |
10502 | idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION; | |
10503 | } else | |
10504 | idt_vectoring |= INTR_TYPE_HARD_EXCEPTION; | |
10505 | ||
10506 | if (vcpu->arch.exception.has_error_code) { | |
10507 | idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK; | |
10508 | vmcs12->idt_vectoring_error_code = | |
10509 | vcpu->arch.exception.error_code; | |
10510 | } | |
10511 | ||
10512 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
cd2633c5 | 10513 | } else if (vcpu->arch.nmi_injected) { |
5f3d5799 JK |
10514 | vmcs12->idt_vectoring_info_field = |
10515 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR; | |
10516 | } else if (vcpu->arch.interrupt.pending) { | |
10517 | nr = vcpu->arch.interrupt.nr; | |
10518 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
10519 | ||
10520 | if (vcpu->arch.interrupt.soft) { | |
10521 | idt_vectoring |= INTR_TYPE_SOFT_INTR; | |
10522 | vmcs12->vm_entry_instruction_len = | |
10523 | vcpu->arch.event_exit_inst_len; | |
10524 | } else | |
10525 | idt_vectoring |= INTR_TYPE_EXT_INTR; | |
10526 | ||
10527 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
10528 | } | |
10529 | } | |
10530 | ||
b6b8a145 JK |
10531 | static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr) |
10532 | { | |
10533 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10534 | ||
acc9ab60 WL |
10535 | if (vcpu->arch.exception.pending || |
10536 | vcpu->arch.nmi_injected || | |
10537 | vcpu->arch.interrupt.pending) | |
10538 | return -EBUSY; | |
10539 | ||
f4124500 JK |
10540 | if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) && |
10541 | vmx->nested.preemption_timer_expired) { | |
10542 | if (vmx->nested.nested_run_pending) | |
10543 | return -EBUSY; | |
10544 | nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0); | |
10545 | return 0; | |
10546 | } | |
10547 | ||
b6b8a145 | 10548 | if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) { |
acc9ab60 | 10549 | if (vmx->nested.nested_run_pending) |
b6b8a145 JK |
10550 | return -EBUSY; |
10551 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, | |
10552 | NMI_VECTOR | INTR_TYPE_NMI_INTR | | |
10553 | INTR_INFO_VALID_MASK, 0); | |
10554 | /* | |
10555 | * The NMI-triggered VM exit counts as injection: | |
10556 | * clear this one and block further NMIs. | |
10557 | */ | |
10558 | vcpu->arch.nmi_pending = 0; | |
10559 | vmx_set_nmi_mask(vcpu, true); | |
10560 | return 0; | |
10561 | } | |
10562 | ||
10563 | if ((kvm_cpu_has_interrupt(vcpu) || external_intr) && | |
10564 | nested_exit_on_intr(vcpu)) { | |
10565 | if (vmx->nested.nested_run_pending) | |
10566 | return -EBUSY; | |
10567 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0); | |
705699a1 | 10568 | return 0; |
b6b8a145 JK |
10569 | } |
10570 | ||
6342c50a DH |
10571 | vmx_complete_nested_posted_interrupt(vcpu); |
10572 | return 0; | |
b6b8a145 JK |
10573 | } |
10574 | ||
f4124500 JK |
10575 | static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu) |
10576 | { | |
10577 | ktime_t remaining = | |
10578 | hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer); | |
10579 | u64 value; | |
10580 | ||
10581 | if (ktime_to_ns(remaining) <= 0) | |
10582 | return 0; | |
10583 | ||
10584 | value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz; | |
10585 | do_div(value, 1000000); | |
10586 | return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
10587 | } | |
10588 | ||
4704d0be | 10589 | /* |
cf8b84f4 JM |
10590 | * Update the guest state fields of vmcs12 to reflect changes that |
10591 | * occurred while L2 was running. (The "IA-32e mode guest" bit of the | |
10592 | * VM-entry controls is also updated, since this is really a guest | |
10593 | * state bit.) | |
4704d0be | 10594 | */ |
cf8b84f4 | 10595 | static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) |
4704d0be | 10596 | { |
4704d0be NHE |
10597 | vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12); |
10598 | vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12); | |
10599 | ||
4704d0be NHE |
10600 | vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); |
10601 | vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP); | |
10602 | vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS); | |
10603 | ||
10604 | vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR); | |
10605 | vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR); | |
10606 | vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR); | |
10607 | vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR); | |
10608 | vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR); | |
10609 | vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR); | |
10610 | vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR); | |
10611 | vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR); | |
10612 | vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT); | |
10613 | vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT); | |
10614 | vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT); | |
10615 | vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT); | |
10616 | vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT); | |
10617 | vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT); | |
10618 | vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT); | |
10619 | vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT); | |
10620 | vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
10621 | vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
10622 | vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES); | |
10623 | vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES); | |
10624 | vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES); | |
10625 | vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES); | |
10626 | vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES); | |
10627 | vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES); | |
10628 | vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES); | |
10629 | vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES); | |
10630 | vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE); | |
10631 | vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE); | |
10632 | vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE); | |
10633 | vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE); | |
10634 | vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE); | |
10635 | vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE); | |
10636 | vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE); | |
10637 | vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE); | |
10638 | vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE); | |
10639 | vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE); | |
10640 | ||
4704d0be NHE |
10641 | vmcs12->guest_interruptibility_info = |
10642 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
10643 | vmcs12->guest_pending_dbg_exceptions = | |
10644 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS); | |
3edf1e69 JK |
10645 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) |
10646 | vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT; | |
10647 | else | |
10648 | vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE; | |
4704d0be | 10649 | |
f4124500 JK |
10650 | if (nested_cpu_has_preemption_timer(vmcs12)) { |
10651 | if (vmcs12->vm_exit_controls & | |
10652 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER) | |
10653 | vmcs12->vmx_preemption_timer_value = | |
10654 | vmx_get_preemption_timer_value(vcpu); | |
10655 | hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer); | |
10656 | } | |
7854cbca | 10657 | |
3633cfc3 NHE |
10658 | /* |
10659 | * In some cases (usually, nested EPT), L2 is allowed to change its | |
10660 | * own CR3 without exiting. If it has changed it, we must keep it. | |
10661 | * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined | |
10662 | * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12. | |
10663 | * | |
10664 | * Additionally, restore L2's PDPTR to vmcs12. | |
10665 | */ | |
10666 | if (enable_ept) { | |
f3531054 | 10667 | vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3); |
3633cfc3 NHE |
10668 | vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0); |
10669 | vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1); | |
10670 | vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2); | |
10671 | vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3); | |
10672 | } | |
10673 | ||
119a9c01 JD |
10674 | if (nested_cpu_has_ept(vmcs12)) |
10675 | vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS); | |
10676 | ||
608406e2 WV |
10677 | if (nested_cpu_has_vid(vmcs12)) |
10678 | vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS); | |
10679 | ||
c18911a2 JK |
10680 | vmcs12->vm_entry_controls = |
10681 | (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) | | |
2961e876 | 10682 | (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE); |
c18911a2 | 10683 | |
2996fca0 JK |
10684 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) { |
10685 | kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7); | |
10686 | vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
10687 | } | |
10688 | ||
4704d0be NHE |
10689 | /* TODO: These cannot have changed unless we have MSR bitmaps and |
10690 | * the relevant bit asks not to trap the change */ | |
b8c07d55 | 10691 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) |
4704d0be | 10692 | vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT); |
10ba54a5 JK |
10693 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER) |
10694 | vmcs12->guest_ia32_efer = vcpu->arch.efer; | |
4704d0be NHE |
10695 | vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS); |
10696 | vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP); | |
10697 | vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP); | |
a87036ad | 10698 | if (kvm_mpx_supported()) |
36be0b9d | 10699 | vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS); |
81dc01f7 WL |
10700 | if (nested_cpu_has_xsaves(vmcs12)) |
10701 | vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP); | |
cf8b84f4 JM |
10702 | } |
10703 | ||
10704 | /* | |
10705 | * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits | |
10706 | * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12), | |
10707 | * and this function updates it to reflect the changes to the guest state while | |
10708 | * L2 was running (and perhaps made some exits which were handled directly by L0 | |
10709 | * without going back to L1), and to reflect the exit reason. | |
10710 | * Note that we do not have to copy here all VMCS fields, just those that | |
10711 | * could have changed by the L2 guest or the exit - i.e., the guest-state and | |
10712 | * exit-information fields only. Other fields are modified by L1 with VMWRITE, | |
10713 | * which already writes to vmcs12 directly. | |
10714 | */ | |
10715 | static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, | |
10716 | u32 exit_reason, u32 exit_intr_info, | |
10717 | unsigned long exit_qualification) | |
10718 | { | |
10719 | /* update guest state fields: */ | |
10720 | sync_vmcs12(vcpu, vmcs12); | |
4704d0be NHE |
10721 | |
10722 | /* update exit information fields: */ | |
10723 | ||
533558bc JK |
10724 | vmcs12->vm_exit_reason = exit_reason; |
10725 | vmcs12->exit_qualification = exit_qualification; | |
4704d0be | 10726 | |
533558bc | 10727 | vmcs12->vm_exit_intr_info = exit_intr_info; |
c0d1c770 JK |
10728 | if ((vmcs12->vm_exit_intr_info & |
10729 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) == | |
10730 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) | |
10731 | vmcs12->vm_exit_intr_error_code = | |
10732 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE); | |
5f3d5799 | 10733 | vmcs12->idt_vectoring_info_field = 0; |
4704d0be NHE |
10734 | vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
10735 | vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
10736 | ||
5f3d5799 JK |
10737 | if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) { |
10738 | /* vm_entry_intr_info_field is cleared on exit. Emulate this | |
10739 | * instead of reading the real value. */ | |
4704d0be | 10740 | vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK; |
5f3d5799 JK |
10741 | |
10742 | /* | |
10743 | * Transfer the event that L0 or L1 may wanted to inject into | |
10744 | * L2 to IDT_VECTORING_INFO_FIELD. | |
10745 | */ | |
10746 | vmcs12_save_pending_event(vcpu, vmcs12); | |
10747 | } | |
10748 | ||
10749 | /* | |
10750 | * Drop what we picked up for L2 via vmx_complete_interrupts. It is | |
10751 | * preserved above and would only end up incorrectly in L1. | |
10752 | */ | |
10753 | vcpu->arch.nmi_injected = false; | |
10754 | kvm_clear_exception_queue(vcpu); | |
10755 | kvm_clear_interrupt_queue(vcpu); | |
4704d0be NHE |
10756 | } |
10757 | ||
10758 | /* | |
10759 | * A part of what we need to when the nested L2 guest exits and we want to | |
10760 | * run its L1 parent, is to reset L1's guest state to the host state specified | |
10761 | * in vmcs12. | |
10762 | * This function is to be called not only on normal nested exit, but also on | |
10763 | * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry | |
10764 | * Failures During or After Loading Guest State"). | |
10765 | * This function should be called when the active VMCS is L1's (vmcs01). | |
10766 | */ | |
733568f9 JK |
10767 | static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, |
10768 | struct vmcs12 *vmcs12) | |
4704d0be | 10769 | { |
21feb4eb | 10770 | struct kvm_segment seg; |
ca0bde28 | 10771 | u32 entry_failure_code; |
21feb4eb | 10772 | |
4704d0be NHE |
10773 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) |
10774 | vcpu->arch.efer = vmcs12->host_ia32_efer; | |
d1fa0352 | 10775 | else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) |
4704d0be NHE |
10776 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); |
10777 | else | |
10778 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
10779 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
10780 | ||
10781 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp); | |
10782 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip); | |
1adfa76a | 10783 | vmx_set_rflags(vcpu, X86_EFLAGS_FIXED); |
4704d0be NHE |
10784 | /* |
10785 | * Note that calling vmx_set_cr0 is important, even if cr0 hasn't | |
bd7e5b08 PB |
10786 | * actually changed, because vmx_set_cr0 refers to efer set above. |
10787 | * | |
10788 | * CR0_GUEST_HOST_MASK is already set in the original vmcs01 | |
10789 | * (KVM doesn't change it); | |
4704d0be | 10790 | */ |
bd7e5b08 | 10791 | vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS; |
9e3e4dbf | 10792 | vmx_set_cr0(vcpu, vmcs12->host_cr0); |
4704d0be | 10793 | |
bd7e5b08 | 10794 | /* Same as above - no reason to call set_cr4_guest_host_mask(). */ |
4704d0be NHE |
10795 | vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK); |
10796 | kvm_set_cr4(vcpu, vmcs12->host_cr4); | |
10797 | ||
29bf08f1 | 10798 | nested_ept_uninit_mmu_context(vcpu); |
155a97a3 | 10799 | |
1dc35dac LP |
10800 | /* |
10801 | * Only PDPTE load can fail as the value of cr3 was checked on entry and | |
10802 | * couldn't have changed. | |
10803 | */ | |
10804 | if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code)) | |
10805 | nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL); | |
4704d0be | 10806 | |
feaf0c7d GN |
10807 | if (!enable_ept) |
10808 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; | |
10809 | ||
4704d0be NHE |
10810 | if (enable_vpid) { |
10811 | /* | |
10812 | * Trivially support vpid by letting L2s share their parent | |
10813 | * L1's vpid. TODO: move to a more elaborate solution, giving | |
10814 | * each L2 its own vpid and exposing the vpid feature to L1. | |
10815 | */ | |
10816 | vmx_flush_tlb(vcpu); | |
10817 | } | |
10818 | ||
10819 | ||
10820 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs); | |
10821 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp); | |
10822 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip); | |
10823 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base); | |
10824 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base); | |
4704d0be | 10825 | |
36be0b9d PB |
10826 | /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */ |
10827 | if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS) | |
10828 | vmcs_write64(GUEST_BNDCFGS, 0); | |
10829 | ||
44811c02 | 10830 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) { |
4704d0be | 10831 | vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat); |
44811c02 JK |
10832 | vcpu->arch.pat = vmcs12->host_ia32_pat; |
10833 | } | |
4704d0be NHE |
10834 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) |
10835 | vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL, | |
10836 | vmcs12->host_ia32_perf_global_ctrl); | |
503cd0c5 | 10837 | |
21feb4eb ACL |
10838 | /* Set L1 segment info according to Intel SDM |
10839 | 27.5.2 Loading Host Segment and Descriptor-Table Registers */ | |
10840 | seg = (struct kvm_segment) { | |
10841 | .base = 0, | |
10842 | .limit = 0xFFFFFFFF, | |
10843 | .selector = vmcs12->host_cs_selector, | |
10844 | .type = 11, | |
10845 | .present = 1, | |
10846 | .s = 1, | |
10847 | .g = 1 | |
10848 | }; | |
10849 | if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) | |
10850 | seg.l = 1; | |
10851 | else | |
10852 | seg.db = 1; | |
10853 | vmx_set_segment(vcpu, &seg, VCPU_SREG_CS); | |
10854 | seg = (struct kvm_segment) { | |
10855 | .base = 0, | |
10856 | .limit = 0xFFFFFFFF, | |
10857 | .type = 3, | |
10858 | .present = 1, | |
10859 | .s = 1, | |
10860 | .db = 1, | |
10861 | .g = 1 | |
10862 | }; | |
10863 | seg.selector = vmcs12->host_ds_selector; | |
10864 | vmx_set_segment(vcpu, &seg, VCPU_SREG_DS); | |
10865 | seg.selector = vmcs12->host_es_selector; | |
10866 | vmx_set_segment(vcpu, &seg, VCPU_SREG_ES); | |
10867 | seg.selector = vmcs12->host_ss_selector; | |
10868 | vmx_set_segment(vcpu, &seg, VCPU_SREG_SS); | |
10869 | seg.selector = vmcs12->host_fs_selector; | |
10870 | seg.base = vmcs12->host_fs_base; | |
10871 | vmx_set_segment(vcpu, &seg, VCPU_SREG_FS); | |
10872 | seg.selector = vmcs12->host_gs_selector; | |
10873 | seg.base = vmcs12->host_gs_base; | |
10874 | vmx_set_segment(vcpu, &seg, VCPU_SREG_GS); | |
10875 | seg = (struct kvm_segment) { | |
205befd9 | 10876 | .base = vmcs12->host_tr_base, |
21feb4eb ACL |
10877 | .limit = 0x67, |
10878 | .selector = vmcs12->host_tr_selector, | |
10879 | .type = 11, | |
10880 | .present = 1 | |
10881 | }; | |
10882 | vmx_set_segment(vcpu, &seg, VCPU_SREG_TR); | |
10883 | ||
503cd0c5 JK |
10884 | kvm_set_dr(vcpu, 7, 0x400); |
10885 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
ff651cb6 | 10886 | |
3af18d9c WV |
10887 | if (cpu_has_vmx_msr_bitmap()) |
10888 | vmx_set_msr_bitmap(vcpu); | |
10889 | ||
ff651cb6 WV |
10890 | if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr, |
10891 | vmcs12->vm_exit_msr_load_count)) | |
10892 | nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL); | |
4704d0be NHE |
10893 | } |
10894 | ||
10895 | /* | |
10896 | * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1 | |
10897 | * and modify vmcs12 to make it see what it would expect to see there if | |
10898 | * L2 was its real guest. Must only be called when in L2 (is_guest_mode()) | |
10899 | */ | |
533558bc JK |
10900 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
10901 | u32 exit_intr_info, | |
10902 | unsigned long exit_qualification) | |
4704d0be NHE |
10903 | { |
10904 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4704d0be | 10905 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
cf3215d9 | 10906 | u32 vm_inst_error = 0; |
4704d0be | 10907 | |
5f3d5799 JK |
10908 | /* trying to cancel vmlaunch/vmresume is a bug */ |
10909 | WARN_ON_ONCE(vmx->nested.nested_run_pending); | |
10910 | ||
4704d0be | 10911 | leave_guest_mode(vcpu); |
533558bc JK |
10912 | prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info, |
10913 | exit_qualification); | |
4704d0be | 10914 | |
ff651cb6 WV |
10915 | if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr, |
10916 | vmcs12->vm_exit_msr_store_count)) | |
10917 | nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL); | |
10918 | ||
cf3215d9 JM |
10919 | if (unlikely(vmx->fail)) |
10920 | vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR); | |
10921 | ||
1279a6b1 | 10922 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); |
f3380ca5 | 10923 | |
77b0f5d6 BD |
10924 | if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) |
10925 | && nested_exit_intr_ack_set(vcpu)) { | |
10926 | int irq = kvm_cpu_get_interrupt(vcpu); | |
10927 | WARN_ON(irq < 0); | |
10928 | vmcs12->vm_exit_intr_info = irq | | |
10929 | INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR; | |
10930 | } | |
10931 | ||
542060ea JK |
10932 | trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason, |
10933 | vmcs12->exit_qualification, | |
10934 | vmcs12->idt_vectoring_info_field, | |
10935 | vmcs12->vm_exit_intr_info, | |
10936 | vmcs12->vm_exit_intr_error_code, | |
10937 | KVM_ISA_VMX); | |
4704d0be | 10938 | |
8391ce44 PB |
10939 | vm_entry_controls_reset_shadow(vmx); |
10940 | vm_exit_controls_reset_shadow(vmx); | |
36c3cc42 JK |
10941 | vmx_segment_cache_clear(vmx); |
10942 | ||
4704d0be NHE |
10943 | /* if no vmcs02 cache requested, remove the one we used */ |
10944 | if (VMCS02_POOL_SIZE == 0) | |
10945 | nested_free_vmcs02(vmx, vmx->nested.current_vmptr); | |
10946 | ||
10947 | load_vmcs12_host_state(vcpu, vmcs12); | |
10948 | ||
9314006d | 10949 | /* Update any VMCS fields that might have changed while L2 ran */ |
83bafef1 JM |
10950 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr); |
10951 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr); | |
ea26e4ec | 10952 | vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); |
9314006d PB |
10953 | if (vmx->hv_deadline_tsc == -1) |
10954 | vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL, | |
10955 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
10956 | else | |
10957 | vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL, | |
10958 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
c95ba92a PF |
10959 | if (kvm_has_tsc_control) |
10960 | decache_tsc_multiplier(vmx); | |
4704d0be | 10961 | |
dccbfcf5 RK |
10962 | if (vmx->nested.change_vmcs01_virtual_x2apic_mode) { |
10963 | vmx->nested.change_vmcs01_virtual_x2apic_mode = false; | |
10964 | vmx_set_virtual_x2apic_mode(vcpu, | |
10965 | vcpu->arch.apic_base & X2APIC_ENABLE); | |
fb6c8198 JM |
10966 | } else if (!nested_cpu_has_ept(vmcs12) && |
10967 | nested_cpu_has2(vmcs12, | |
10968 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
10969 | vmx_flush_tlb_ept_only(vcpu); | |
dccbfcf5 | 10970 | } |
4704d0be NHE |
10971 | |
10972 | /* This is needed for same reason as it was needed in prepare_vmcs02 */ | |
10973 | vmx->host_rsp = 0; | |
10974 | ||
10975 | /* Unpin physical memory we referred to in vmcs02 */ | |
10976 | if (vmx->nested.apic_access_page) { | |
10977 | nested_release_page(vmx->nested.apic_access_page); | |
48d89b92 | 10978 | vmx->nested.apic_access_page = NULL; |
4704d0be | 10979 | } |
a7c0b07d WL |
10980 | if (vmx->nested.virtual_apic_page) { |
10981 | nested_release_page(vmx->nested.virtual_apic_page); | |
48d89b92 | 10982 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 10983 | } |
705699a1 WV |
10984 | if (vmx->nested.pi_desc_page) { |
10985 | kunmap(vmx->nested.pi_desc_page); | |
10986 | nested_release_page(vmx->nested.pi_desc_page); | |
10987 | vmx->nested.pi_desc_page = NULL; | |
10988 | vmx->nested.pi_desc = NULL; | |
10989 | } | |
4704d0be | 10990 | |
38b99173 TC |
10991 | /* |
10992 | * We are now running in L2, mmu_notifier will force to reload the | |
10993 | * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1. | |
10994 | */ | |
c83b6d15 | 10995 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
38b99173 | 10996 | |
4704d0be NHE |
10997 | /* |
10998 | * Exiting from L2 to L1, we're now back to L1 which thinks it just | |
10999 | * finished a VMLAUNCH or VMRESUME instruction, so we need to set the | |
11000 | * success or failure flag accordingly. | |
11001 | */ | |
11002 | if (unlikely(vmx->fail)) { | |
11003 | vmx->fail = 0; | |
cf3215d9 | 11004 | nested_vmx_failValid(vcpu, vm_inst_error); |
4704d0be NHE |
11005 | } else |
11006 | nested_vmx_succeed(vcpu); | |
012f83cb AG |
11007 | if (enable_shadow_vmcs) |
11008 | vmx->nested.sync_shadow_vmcs = true; | |
b6b8a145 JK |
11009 | |
11010 | /* in case we halted in L2 */ | |
11011 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
4704d0be NHE |
11012 | } |
11013 | ||
42124925 JK |
11014 | /* |
11015 | * Forcibly leave nested mode in order to be able to reset the VCPU later on. | |
11016 | */ | |
11017 | static void vmx_leave_nested(struct kvm_vcpu *vcpu) | |
11018 | { | |
2f707d97 WL |
11019 | if (is_guest_mode(vcpu)) { |
11020 | to_vmx(vcpu)->nested.nested_run_pending = 0; | |
533558bc | 11021 | nested_vmx_vmexit(vcpu, -1, 0, 0); |
2f707d97 | 11022 | } |
42124925 JK |
11023 | free_nested(to_vmx(vcpu)); |
11024 | } | |
11025 | ||
7c177938 NHE |
11026 | /* |
11027 | * L1's failure to enter L2 is a subset of a normal exit, as explained in | |
11028 | * 23.7 "VM-entry failures during or after loading guest state" (this also | |
11029 | * lists the acceptable exit-reason and exit-qualification parameters). | |
11030 | * It should only be called before L2 actually succeeded to run, and when | |
11031 | * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss). | |
11032 | */ | |
11033 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, | |
11034 | struct vmcs12 *vmcs12, | |
11035 | u32 reason, unsigned long qualification) | |
11036 | { | |
11037 | load_vmcs12_host_state(vcpu, vmcs12); | |
11038 | vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY; | |
11039 | vmcs12->exit_qualification = qualification; | |
11040 | nested_vmx_succeed(vcpu); | |
012f83cb AG |
11041 | if (enable_shadow_vmcs) |
11042 | to_vmx(vcpu)->nested.sync_shadow_vmcs = true; | |
7c177938 NHE |
11043 | } |
11044 | ||
8a76d7f2 JR |
11045 | static int vmx_check_intercept(struct kvm_vcpu *vcpu, |
11046 | struct x86_instruction_info *info, | |
11047 | enum x86_intercept_stage stage) | |
11048 | { | |
11049 | return X86EMUL_CONTINUE; | |
11050 | } | |
11051 | ||
64672c95 YJ |
11052 | #ifdef CONFIG_X86_64 |
11053 | /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ | |
11054 | static inline int u64_shl_div_u64(u64 a, unsigned int shift, | |
11055 | u64 divisor, u64 *result) | |
11056 | { | |
11057 | u64 low = a << shift, high = a >> (64 - shift); | |
11058 | ||
11059 | /* To avoid the overflow on divq */ | |
11060 | if (high >= divisor) | |
11061 | return 1; | |
11062 | ||
11063 | /* Low hold the result, high hold rem which is discarded */ | |
11064 | asm("divq %2\n\t" : "=a" (low), "=d" (high) : | |
11065 | "rm" (divisor), "0" (low), "1" (high)); | |
11066 | *result = low; | |
11067 | ||
11068 | return 0; | |
11069 | } | |
11070 | ||
11071 | static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc) | |
11072 | { | |
11073 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9175d2e9 PB |
11074 | u64 tscl = rdtsc(); |
11075 | u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); | |
11076 | u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; | |
64672c95 YJ |
11077 | |
11078 | /* Convert to host delta tsc if tsc scaling is enabled */ | |
11079 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && | |
11080 | u64_shl_div_u64(delta_tsc, | |
11081 | kvm_tsc_scaling_ratio_frac_bits, | |
11082 | vcpu->arch.tsc_scaling_ratio, | |
11083 | &delta_tsc)) | |
11084 | return -ERANGE; | |
11085 | ||
11086 | /* | |
11087 | * If the delta tsc can't fit in the 32 bit after the multi shift, | |
11088 | * we can't use the preemption timer. | |
11089 | * It's possible that it fits on later vmentries, but checking | |
11090 | * on every vmentry is costly so we just use an hrtimer. | |
11091 | */ | |
11092 | if (delta_tsc >> (cpu_preemption_timer_multi + 32)) | |
11093 | return -ERANGE; | |
11094 | ||
11095 | vmx->hv_deadline_tsc = tscl + delta_tsc; | |
11096 | vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL, | |
11097 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
11098 | return 0; | |
11099 | } | |
11100 | ||
11101 | static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) | |
11102 | { | |
11103 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
11104 | vmx->hv_deadline_tsc = -1; | |
11105 | vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL, | |
11106 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
11107 | } | |
11108 | #endif | |
11109 | ||
48d89b92 | 11110 | static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) |
ae97a3b8 | 11111 | { |
b4a2d31d RK |
11112 | if (ple_gap) |
11113 | shrink_ple_window(vcpu); | |
ae97a3b8 RK |
11114 | } |
11115 | ||
843e4330 KH |
11116 | static void vmx_slot_enable_log_dirty(struct kvm *kvm, |
11117 | struct kvm_memory_slot *slot) | |
11118 | { | |
11119 | kvm_mmu_slot_leaf_clear_dirty(kvm, slot); | |
11120 | kvm_mmu_slot_largepage_remove_write_access(kvm, slot); | |
11121 | } | |
11122 | ||
11123 | static void vmx_slot_disable_log_dirty(struct kvm *kvm, | |
11124 | struct kvm_memory_slot *slot) | |
11125 | { | |
11126 | kvm_mmu_slot_set_dirty(kvm, slot); | |
11127 | } | |
11128 | ||
11129 | static void vmx_flush_log_dirty(struct kvm *kvm) | |
11130 | { | |
11131 | kvm_flush_pml_buffers(kvm); | |
11132 | } | |
11133 | ||
11134 | static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, | |
11135 | struct kvm_memory_slot *memslot, | |
11136 | gfn_t offset, unsigned long mask) | |
11137 | { | |
11138 | kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); | |
11139 | } | |
11140 | ||
bf9f6ac8 FW |
11141 | /* |
11142 | * This routine does the following things for vCPU which is going | |
11143 | * to be blocked if VT-d PI is enabled. | |
11144 | * - Store the vCPU to the wakeup list, so when interrupts happen | |
11145 | * we can find the right vCPU to wake up. | |
11146 | * - Change the Posted-interrupt descriptor as below: | |
11147 | * 'NDST' <-- vcpu->pre_pcpu | |
11148 | * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR | |
11149 | * - If 'ON' is set during this process, which means at least one | |
11150 | * interrupt is posted for this vCPU, we cannot block it, in | |
11151 | * this case, return 1, otherwise, return 0. | |
11152 | * | |
11153 | */ | |
bc22512b | 11154 | static int pi_pre_block(struct kvm_vcpu *vcpu) |
bf9f6ac8 FW |
11155 | { |
11156 | unsigned long flags; | |
11157 | unsigned int dest; | |
11158 | struct pi_desc old, new; | |
11159 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
11160 | ||
11161 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
11162 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
11163 | !kvm_vcpu_apicv_active(vcpu)) | |
bf9f6ac8 FW |
11164 | return 0; |
11165 | ||
11166 | vcpu->pre_pcpu = vcpu->cpu; | |
11167 | spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock, | |
11168 | vcpu->pre_pcpu), flags); | |
11169 | list_add_tail(&vcpu->blocked_vcpu_list, | |
11170 | &per_cpu(blocked_vcpu_on_cpu, | |
11171 | vcpu->pre_pcpu)); | |
11172 | spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock, | |
11173 | vcpu->pre_pcpu), flags); | |
11174 | ||
11175 | do { | |
11176 | old.control = new.control = pi_desc->control; | |
11177 | ||
11178 | /* | |
11179 | * We should not block the vCPU if | |
11180 | * an interrupt is posted for it. | |
11181 | */ | |
11182 | if (pi_test_on(pi_desc) == 1) { | |
11183 | spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock, | |
11184 | vcpu->pre_pcpu), flags); | |
11185 | list_del(&vcpu->blocked_vcpu_list); | |
11186 | spin_unlock_irqrestore( | |
11187 | &per_cpu(blocked_vcpu_on_cpu_lock, | |
11188 | vcpu->pre_pcpu), flags); | |
11189 | vcpu->pre_pcpu = -1; | |
11190 | ||
11191 | return 1; | |
11192 | } | |
11193 | ||
11194 | WARN((pi_desc->sn == 1), | |
11195 | "Warning: SN field of posted-interrupts " | |
11196 | "is set before blocking\n"); | |
11197 | ||
11198 | /* | |
11199 | * Since vCPU can be preempted during this process, | |
11200 | * vcpu->cpu could be different with pre_pcpu, we | |
11201 | * need to set pre_pcpu as the destination of wakeup | |
11202 | * notification event, then we can find the right vCPU | |
11203 | * to wakeup in wakeup handler if interrupts happen | |
11204 | * when the vCPU is in blocked state. | |
11205 | */ | |
11206 | dest = cpu_physical_id(vcpu->pre_pcpu); | |
11207 | ||
11208 | if (x2apic_enabled()) | |
11209 | new.ndst = dest; | |
11210 | else | |
11211 | new.ndst = (dest << 8) & 0xFF00; | |
11212 | ||
11213 | /* set 'NV' to 'wakeup vector' */ | |
11214 | new.nv = POSTED_INTR_WAKEUP_VECTOR; | |
11215 | } while (cmpxchg(&pi_desc->control, old.control, | |
11216 | new.control) != old.control); | |
11217 | ||
11218 | return 0; | |
11219 | } | |
11220 | ||
bc22512b YJ |
11221 | static int vmx_pre_block(struct kvm_vcpu *vcpu) |
11222 | { | |
11223 | if (pi_pre_block(vcpu)) | |
11224 | return 1; | |
11225 | ||
64672c95 YJ |
11226 | if (kvm_lapic_hv_timer_in_use(vcpu)) |
11227 | kvm_lapic_switch_to_sw_timer(vcpu); | |
11228 | ||
bc22512b YJ |
11229 | return 0; |
11230 | } | |
11231 | ||
11232 | static void pi_post_block(struct kvm_vcpu *vcpu) | |
bf9f6ac8 FW |
11233 | { |
11234 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
11235 | struct pi_desc old, new; | |
11236 | unsigned int dest; | |
11237 | unsigned long flags; | |
11238 | ||
11239 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
11240 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
11241 | !kvm_vcpu_apicv_active(vcpu)) | |
bf9f6ac8 FW |
11242 | return; |
11243 | ||
11244 | do { | |
11245 | old.control = new.control = pi_desc->control; | |
11246 | ||
11247 | dest = cpu_physical_id(vcpu->cpu); | |
11248 | ||
11249 | if (x2apic_enabled()) | |
11250 | new.ndst = dest; | |
11251 | else | |
11252 | new.ndst = (dest << 8) & 0xFF00; | |
11253 | ||
11254 | /* Allow posting non-urgent interrupts */ | |
11255 | new.sn = 0; | |
11256 | ||
11257 | /* set 'NV' to 'notification vector' */ | |
11258 | new.nv = POSTED_INTR_VECTOR; | |
11259 | } while (cmpxchg(&pi_desc->control, old.control, | |
11260 | new.control) != old.control); | |
11261 | ||
11262 | if(vcpu->pre_pcpu != -1) { | |
11263 | spin_lock_irqsave( | |
11264 | &per_cpu(blocked_vcpu_on_cpu_lock, | |
11265 | vcpu->pre_pcpu), flags); | |
11266 | list_del(&vcpu->blocked_vcpu_list); | |
11267 | spin_unlock_irqrestore( | |
11268 | &per_cpu(blocked_vcpu_on_cpu_lock, | |
11269 | vcpu->pre_pcpu), flags); | |
11270 | vcpu->pre_pcpu = -1; | |
11271 | } | |
11272 | } | |
11273 | ||
bc22512b YJ |
11274 | static void vmx_post_block(struct kvm_vcpu *vcpu) |
11275 | { | |
64672c95 YJ |
11276 | if (kvm_x86_ops->set_hv_timer) |
11277 | kvm_lapic_switch_to_hv_timer(vcpu); | |
11278 | ||
bc22512b YJ |
11279 | pi_post_block(vcpu); |
11280 | } | |
11281 | ||
efc64404 FW |
11282 | /* |
11283 | * vmx_update_pi_irte - set IRTE for Posted-Interrupts | |
11284 | * | |
11285 | * @kvm: kvm | |
11286 | * @host_irq: host irq of the interrupt | |
11287 | * @guest_irq: gsi of the interrupt | |
11288 | * @set: set or unset PI | |
11289 | * returns 0 on success, < 0 on failure | |
11290 | */ | |
11291 | static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, | |
11292 | uint32_t guest_irq, bool set) | |
11293 | { | |
11294 | struct kvm_kernel_irq_routing_entry *e; | |
11295 | struct kvm_irq_routing_table *irq_rt; | |
11296 | struct kvm_lapic_irq irq; | |
11297 | struct kvm_vcpu *vcpu; | |
11298 | struct vcpu_data vcpu_info; | |
11299 | int idx, ret = -EINVAL; | |
11300 | ||
11301 | if (!kvm_arch_has_assigned_device(kvm) || | |
a0052191 YZ |
11302 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
11303 | !kvm_vcpu_apicv_active(kvm->vcpus[0])) | |
efc64404 FW |
11304 | return 0; |
11305 | ||
11306 | idx = srcu_read_lock(&kvm->irq_srcu); | |
11307 | irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); | |
11308 | BUG_ON(guest_irq >= irq_rt->nr_rt_entries); | |
11309 | ||
11310 | hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { | |
11311 | if (e->type != KVM_IRQ_ROUTING_MSI) | |
11312 | continue; | |
11313 | /* | |
11314 | * VT-d PI cannot support posting multicast/broadcast | |
11315 | * interrupts to a vCPU, we still use interrupt remapping | |
11316 | * for these kind of interrupts. | |
11317 | * | |
11318 | * For lowest-priority interrupts, we only support | |
11319 | * those with single CPU as the destination, e.g. user | |
11320 | * configures the interrupts via /proc/irq or uses | |
11321 | * irqbalance to make the interrupts single-CPU. | |
11322 | * | |
11323 | * We will support full lowest-priority interrupt later. | |
11324 | */ | |
11325 | ||
37131313 | 11326 | kvm_set_msi_irq(kvm, e, &irq); |
23a1c257 FW |
11327 | if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) { |
11328 | /* | |
11329 | * Make sure the IRTE is in remapped mode if | |
11330 | * we don't handle it in posted mode. | |
11331 | */ | |
11332 | ret = irq_set_vcpu_affinity(host_irq, NULL); | |
11333 | if (ret < 0) { | |
11334 | printk(KERN_INFO | |
11335 | "failed to back to remapped mode, irq: %u\n", | |
11336 | host_irq); | |
11337 | goto out; | |
11338 | } | |
11339 | ||
efc64404 | 11340 | continue; |
23a1c257 | 11341 | } |
efc64404 FW |
11342 | |
11343 | vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); | |
11344 | vcpu_info.vector = irq.vector; | |
11345 | ||
b6ce9780 | 11346 | trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi, |
efc64404 FW |
11347 | vcpu_info.vector, vcpu_info.pi_desc_addr, set); |
11348 | ||
11349 | if (set) | |
11350 | ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); | |
11351 | else { | |
11352 | /* suppress notification event before unposting */ | |
11353 | pi_set_sn(vcpu_to_pi_desc(vcpu)); | |
11354 | ret = irq_set_vcpu_affinity(host_irq, NULL); | |
11355 | pi_clear_sn(vcpu_to_pi_desc(vcpu)); | |
11356 | } | |
11357 | ||
11358 | if (ret < 0) { | |
11359 | printk(KERN_INFO "%s: failed to update PI IRTE\n", | |
11360 | __func__); | |
11361 | goto out; | |
11362 | } | |
11363 | } | |
11364 | ||
11365 | ret = 0; | |
11366 | out: | |
11367 | srcu_read_unlock(&kvm->irq_srcu, idx); | |
11368 | return ret; | |
11369 | } | |
11370 | ||
c45dcc71 AR |
11371 | static void vmx_setup_mce(struct kvm_vcpu *vcpu) |
11372 | { | |
11373 | if (vcpu->arch.mcg_cap & MCG_LMCE_P) | |
11374 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= | |
11375 | FEATURE_CONTROL_LMCE; | |
11376 | else | |
11377 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= | |
11378 | ~FEATURE_CONTROL_LMCE; | |
11379 | } | |
11380 | ||
404f6aac | 11381 | static struct kvm_x86_ops vmx_x86_ops __ro_after_init = { |
6aa8b732 AK |
11382 | .cpu_has_kvm_support = cpu_has_kvm_support, |
11383 | .disabled_by_bios = vmx_disabled_by_bios, | |
11384 | .hardware_setup = hardware_setup, | |
11385 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 11386 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
11387 | .hardware_enable = hardware_enable, |
11388 | .hardware_disable = hardware_disable, | |
04547156 | 11389 | .cpu_has_accelerated_tpr = report_flexpriority, |
6d396b55 | 11390 | .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase, |
6aa8b732 AK |
11391 | |
11392 | .vcpu_create = vmx_create_vcpu, | |
11393 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 11394 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 11395 | |
04d2cc77 | 11396 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
11397 | .vcpu_load = vmx_vcpu_load, |
11398 | .vcpu_put = vmx_vcpu_put, | |
11399 | ||
a96036b8 | 11400 | .update_bp_intercept = update_exception_bitmap, |
6aa8b732 AK |
11401 | .get_msr = vmx_get_msr, |
11402 | .set_msr = vmx_set_msr, | |
11403 | .get_segment_base = vmx_get_segment_base, | |
11404 | .get_segment = vmx_get_segment, | |
11405 | .set_segment = vmx_set_segment, | |
2e4d2653 | 11406 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 11407 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
e8467fda | 11408 | .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, |
aff48baa | 11409 | .decache_cr3 = vmx_decache_cr3, |
25c4c276 | 11410 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 11411 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
11412 | .set_cr3 = vmx_set_cr3, |
11413 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 11414 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
11415 | .get_idt = vmx_get_idt, |
11416 | .set_idt = vmx_set_idt, | |
11417 | .get_gdt = vmx_get_gdt, | |
11418 | .set_gdt = vmx_set_gdt, | |
73aaf249 JK |
11419 | .get_dr6 = vmx_get_dr6, |
11420 | .set_dr6 = vmx_set_dr6, | |
020df079 | 11421 | .set_dr7 = vmx_set_dr7, |
81908bf4 | 11422 | .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, |
5fdbf976 | 11423 | .cache_reg = vmx_cache_reg, |
6aa8b732 AK |
11424 | .get_rflags = vmx_get_rflags, |
11425 | .set_rflags = vmx_set_rflags, | |
be94f6b7 HH |
11426 | |
11427 | .get_pkru = vmx_get_pkru, | |
11428 | ||
6aa8b732 | 11429 | .tlb_flush = vmx_flush_tlb, |
6aa8b732 | 11430 | |
6aa8b732 | 11431 | .run = vmx_vcpu_run, |
6062d012 | 11432 | .handle_exit = vmx_handle_exit, |
6aa8b732 | 11433 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
11434 | .set_interrupt_shadow = vmx_set_interrupt_shadow, |
11435 | .get_interrupt_shadow = vmx_get_interrupt_shadow, | |
102d8325 | 11436 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 | 11437 | .set_irq = vmx_inject_irq, |
95ba8273 | 11438 | .set_nmi = vmx_inject_nmi, |
298101da | 11439 | .queue_exception = vmx_queue_exception, |
b463a6f7 | 11440 | .cancel_injection = vmx_cancel_injection, |
78646121 | 11441 | .interrupt_allowed = vmx_interrupt_allowed, |
95ba8273 | 11442 | .nmi_allowed = vmx_nmi_allowed, |
3cfc3092 JK |
11443 | .get_nmi_mask = vmx_get_nmi_mask, |
11444 | .set_nmi_mask = vmx_set_nmi_mask, | |
95ba8273 GN |
11445 | .enable_nmi_window = enable_nmi_window, |
11446 | .enable_irq_window = enable_irq_window, | |
11447 | .update_cr8_intercept = update_cr8_intercept, | |
8d14695f | 11448 | .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode, |
38b99173 | 11449 | .set_apic_access_page_addr = vmx_set_apic_access_page_addr, |
d62caabb AS |
11450 | .get_enable_apicv = vmx_get_enable_apicv, |
11451 | .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, | |
c7c9c56c | 11452 | .load_eoi_exitmap = vmx_load_eoi_exitmap, |
967235d3 | 11453 | .apicv_post_state_restore = vmx_apicv_post_state_restore, |
c7c9c56c YZ |
11454 | .hwapic_irr_update = vmx_hwapic_irr_update, |
11455 | .hwapic_isr_update = vmx_hwapic_isr_update, | |
a20ed54d YZ |
11456 | .sync_pir_to_irr = vmx_sync_pir_to_irr, |
11457 | .deliver_posted_interrupt = vmx_deliver_posted_interrupt, | |
95ba8273 | 11458 | |
cbc94022 | 11459 | .set_tss_addr = vmx_set_tss_addr, |
67253af5 | 11460 | .get_tdp_level = get_ept_level, |
4b12f0de | 11461 | .get_mt_mask = vmx_get_mt_mask, |
229456fc | 11462 | |
586f9607 | 11463 | .get_exit_info = vmx_get_exit_info, |
586f9607 | 11464 | |
17cc3935 | 11465 | .get_lpage_level = vmx_get_lpage_level, |
0e851880 SY |
11466 | |
11467 | .cpuid_update = vmx_cpuid_update, | |
4e47c7a6 SY |
11468 | |
11469 | .rdtscp_supported = vmx_rdtscp_supported, | |
ad756a16 | 11470 | .invpcid_supported = vmx_invpcid_supported, |
d4330ef2 JR |
11471 | |
11472 | .set_supported_cpuid = vmx_set_supported_cpuid, | |
f5f48ee1 SY |
11473 | |
11474 | .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, | |
99e3e30a ZA |
11475 | |
11476 | .write_tsc_offset = vmx_write_tsc_offset, | |
1c97f0a0 JR |
11477 | |
11478 | .set_tdp_cr3 = vmx_set_cr3, | |
8a76d7f2 JR |
11479 | |
11480 | .check_intercept = vmx_check_intercept, | |
a547c6db | 11481 | .handle_external_intr = vmx_handle_external_intr, |
da8999d3 | 11482 | .mpx_supported = vmx_mpx_supported, |
55412b2e | 11483 | .xsaves_supported = vmx_xsaves_supported, |
b6b8a145 JK |
11484 | |
11485 | .check_nested_events = vmx_check_nested_events, | |
ae97a3b8 RK |
11486 | |
11487 | .sched_in = vmx_sched_in, | |
843e4330 KH |
11488 | |
11489 | .slot_enable_log_dirty = vmx_slot_enable_log_dirty, | |
11490 | .slot_disable_log_dirty = vmx_slot_disable_log_dirty, | |
11491 | .flush_log_dirty = vmx_flush_log_dirty, | |
11492 | .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, | |
25462f7f | 11493 | |
bf9f6ac8 FW |
11494 | .pre_block = vmx_pre_block, |
11495 | .post_block = vmx_post_block, | |
11496 | ||
25462f7f | 11497 | .pmu_ops = &intel_pmu_ops, |
efc64404 FW |
11498 | |
11499 | .update_pi_irte = vmx_update_pi_irte, | |
64672c95 YJ |
11500 | |
11501 | #ifdef CONFIG_X86_64 | |
11502 | .set_hv_timer = vmx_set_hv_timer, | |
11503 | .cancel_hv_timer = vmx_cancel_hv_timer, | |
11504 | #endif | |
c45dcc71 AR |
11505 | |
11506 | .setup_mce = vmx_setup_mce, | |
6aa8b732 AK |
11507 | }; |
11508 | ||
11509 | static int __init vmx_init(void) | |
11510 | { | |
34a1cd60 TC |
11511 | int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), |
11512 | __alignof__(struct vcpu_vmx), THIS_MODULE); | |
fdef3ad1 | 11513 | if (r) |
34a1cd60 | 11514 | return r; |
25c5f225 | 11515 | |
2965faa5 | 11516 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
11517 | rcu_assign_pointer(crash_vmclear_loaded_vmcss, |
11518 | crash_vmclear_local_loaded_vmcss); | |
11519 | #endif | |
11520 | ||
fdef3ad1 | 11521 | return 0; |
6aa8b732 AK |
11522 | } |
11523 | ||
11524 | static void __exit vmx_exit(void) | |
11525 | { | |
2965faa5 | 11526 | #ifdef CONFIG_KEXEC_CORE |
3b63a43f | 11527 | RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); |
8f536b76 ZY |
11528 | synchronize_rcu(); |
11529 | #endif | |
11530 | ||
cb498ea2 | 11531 | kvm_exit(); |
6aa8b732 AK |
11532 | } |
11533 | ||
11534 | module_init(vmx_init) | |
11535 | module_exit(vmx_exit) |