Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
8 | * | |
9 | * Authors: | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * Yaniv Kamay <yaniv@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
17 | ||
85f455f7 | 18 | #include "irq.h" |
6aa8b732 | 19 | #include "vmx.h" |
1d737c8a | 20 | #include "mmu.h" |
e495606d | 21 | |
edf88417 | 22 | #include <linux/kvm_host.h> |
6aa8b732 | 23 | #include <linux/module.h> |
9d8f549d | 24 | #include <linux/kernel.h> |
6aa8b732 AK |
25 | #include <linux/mm.h> |
26 | #include <linux/highmem.h> | |
e8edc6e0 | 27 | #include <linux/sched.h> |
c7addb90 | 28 | #include <linux/moduleparam.h> |
5fdbf976 | 29 | #include "kvm_cache_regs.h" |
35920a35 | 30 | #include "x86.h" |
e495606d | 31 | |
6aa8b732 | 32 | #include <asm/io.h> |
3b3be0d1 | 33 | #include <asm/desc.h> |
6aa8b732 | 34 | |
4ecac3fd AK |
35 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
36 | ||
6aa8b732 AK |
37 | MODULE_AUTHOR("Qumranet"); |
38 | MODULE_LICENSE("GPL"); | |
39 | ||
c7addb90 AK |
40 | static int bypass_guest_pf = 1; |
41 | module_param(bypass_guest_pf, bool, 0); | |
42 | ||
2384d2b3 SY |
43 | static int enable_vpid = 1; |
44 | module_param(enable_vpid, bool, 0); | |
45 | ||
4c9fc8ef AK |
46 | static int flexpriority_enabled = 1; |
47 | module_param(flexpriority_enabled, bool, 0); | |
48 | ||
1439442c | 49 | static int enable_ept = 1; |
d56f546d SY |
50 | module_param(enable_ept, bool, 0); |
51 | ||
04fa4d32 MG |
52 | static int emulate_invalid_guest_state = 0; |
53 | module_param(emulate_invalid_guest_state, bool, 0); | |
54 | ||
a2fa3e9f GH |
55 | struct vmcs { |
56 | u32 revision_id; | |
57 | u32 abort; | |
58 | char data[0]; | |
59 | }; | |
60 | ||
61 | struct vcpu_vmx { | |
fb3f0f51 | 62 | struct kvm_vcpu vcpu; |
543e4243 | 63 | struct list_head local_vcpus_link; |
313dbd49 | 64 | unsigned long host_rsp; |
a2fa3e9f | 65 | int launched; |
29bd8a78 | 66 | u8 fail; |
1155f76a | 67 | u32 idt_vectoring_info; |
a2fa3e9f GH |
68 | struct kvm_msr_entry *guest_msrs; |
69 | struct kvm_msr_entry *host_msrs; | |
70 | int nmsrs; | |
71 | int save_nmsrs; | |
72 | int msr_offset_efer; | |
73 | #ifdef CONFIG_X86_64 | |
74 | int msr_offset_kernel_gs_base; | |
75 | #endif | |
76 | struct vmcs *vmcs; | |
77 | struct { | |
78 | int loaded; | |
79 | u16 fs_sel, gs_sel, ldt_sel; | |
152d3f2f LV |
80 | int gs_ldt_reload_needed; |
81 | int fs_reload_needed; | |
51c6cf66 | 82 | int guest_efer_loaded; |
d77c26fc | 83 | } host_state; |
9c8cba37 AK |
84 | struct { |
85 | struct { | |
86 | bool pending; | |
87 | u8 vector; | |
88 | unsigned rip; | |
89 | } irq; | |
90 | } rmode; | |
2384d2b3 | 91 | int vpid; |
04fa4d32 | 92 | bool emulation_required; |
a2fa3e9f GH |
93 | }; |
94 | ||
95 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) | |
96 | { | |
fb3f0f51 | 97 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
98 | } |
99 | ||
b7ebfb05 | 100 | static int init_rmode(struct kvm *kvm); |
4e1096d2 | 101 | static u64 construct_eptp(unsigned long root_hpa); |
75880a01 | 102 | |
6aa8b732 AK |
103 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
104 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
543e4243 | 105 | static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu); |
6aa8b732 | 106 | |
fdef3ad1 HQ |
107 | static struct page *vmx_io_bitmap_a; |
108 | static struct page *vmx_io_bitmap_b; | |
25c5f225 | 109 | static struct page *vmx_msr_bitmap; |
fdef3ad1 | 110 | |
2384d2b3 SY |
111 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
112 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
113 | ||
1c3d14fe | 114 | static struct vmcs_config { |
6aa8b732 AK |
115 | int size; |
116 | int order; | |
117 | u32 revision_id; | |
1c3d14fe YS |
118 | u32 pin_based_exec_ctrl; |
119 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 120 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
121 | u32 vmexit_ctrl; |
122 | u32 vmentry_ctrl; | |
123 | } vmcs_config; | |
6aa8b732 | 124 | |
d56f546d SY |
125 | struct vmx_capability { |
126 | u32 ept; | |
127 | u32 vpid; | |
128 | } vmx_capability; | |
129 | ||
6aa8b732 AK |
130 | #define VMX_SEGMENT_FIELD(seg) \ |
131 | [VCPU_SREG_##seg] = { \ | |
132 | .selector = GUEST_##seg##_SELECTOR, \ | |
133 | .base = GUEST_##seg##_BASE, \ | |
134 | .limit = GUEST_##seg##_LIMIT, \ | |
135 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
136 | } | |
137 | ||
138 | static struct kvm_vmx_segment_field { | |
139 | unsigned selector; | |
140 | unsigned base; | |
141 | unsigned limit; | |
142 | unsigned ar_bytes; | |
143 | } kvm_vmx_segment_fields[] = { | |
144 | VMX_SEGMENT_FIELD(CS), | |
145 | VMX_SEGMENT_FIELD(DS), | |
146 | VMX_SEGMENT_FIELD(ES), | |
147 | VMX_SEGMENT_FIELD(FS), | |
148 | VMX_SEGMENT_FIELD(GS), | |
149 | VMX_SEGMENT_FIELD(SS), | |
150 | VMX_SEGMENT_FIELD(TR), | |
151 | VMX_SEGMENT_FIELD(LDTR), | |
152 | }; | |
153 | ||
4d56c8a7 AK |
154 | /* |
155 | * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it | |
156 | * away by decrementing the array size. | |
157 | */ | |
6aa8b732 | 158 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 159 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
160 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE, |
161 | #endif | |
162 | MSR_EFER, MSR_K6_STAR, | |
163 | }; | |
9d8f549d | 164 | #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index) |
6aa8b732 | 165 | |
a2fa3e9f GH |
166 | static void load_msrs(struct kvm_msr_entry *e, int n) |
167 | { | |
168 | int i; | |
169 | ||
170 | for (i = 0; i < n; ++i) | |
171 | wrmsrl(e[i].index, e[i].data); | |
172 | } | |
173 | ||
174 | static void save_msrs(struct kvm_msr_entry *e, int n) | |
175 | { | |
176 | int i; | |
177 | ||
178 | for (i = 0; i < n; ++i) | |
179 | rdmsrl(e[i].index, e[i].data); | |
180 | } | |
181 | ||
6aa8b732 AK |
182 | static inline int is_page_fault(u32 intr_info) |
183 | { | |
184 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
185 | INTR_INFO_VALID_MASK)) == | |
186 | (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK); | |
187 | } | |
188 | ||
2ab455cc AL |
189 | static inline int is_no_device(u32 intr_info) |
190 | { | |
191 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
192 | INTR_INFO_VALID_MASK)) == | |
193 | (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK); | |
194 | } | |
195 | ||
7aa81cc0 AL |
196 | static inline int is_invalid_opcode(u32 intr_info) |
197 | { | |
198 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
199 | INTR_INFO_VALID_MASK)) == | |
200 | (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK); | |
201 | } | |
202 | ||
6aa8b732 AK |
203 | static inline int is_external_interrupt(u32 intr_info) |
204 | { | |
205 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
206 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
207 | } | |
208 | ||
25c5f225 SY |
209 | static inline int cpu_has_vmx_msr_bitmap(void) |
210 | { | |
211 | return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS); | |
212 | } | |
213 | ||
6e5d865c YS |
214 | static inline int cpu_has_vmx_tpr_shadow(void) |
215 | { | |
216 | return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW); | |
217 | } | |
218 | ||
219 | static inline int vm_need_tpr_shadow(struct kvm *kvm) | |
220 | { | |
221 | return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm))); | |
222 | } | |
223 | ||
f78e0e2e SY |
224 | static inline int cpu_has_secondary_exec_ctrls(void) |
225 | { | |
226 | return (vmcs_config.cpu_based_exec_ctrl & | |
227 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS); | |
228 | } | |
229 | ||
774ead3a | 230 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 231 | { |
4c9fc8ef AK |
232 | return flexpriority_enabled |
233 | && (vmcs_config.cpu_based_2nd_exec_ctrl & | |
234 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
f78e0e2e SY |
235 | } |
236 | ||
d56f546d SY |
237 | static inline int cpu_has_vmx_invept_individual_addr(void) |
238 | { | |
239 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT)); | |
240 | } | |
241 | ||
242 | static inline int cpu_has_vmx_invept_context(void) | |
243 | { | |
244 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT)); | |
245 | } | |
246 | ||
247 | static inline int cpu_has_vmx_invept_global(void) | |
248 | { | |
249 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT)); | |
250 | } | |
251 | ||
252 | static inline int cpu_has_vmx_ept(void) | |
253 | { | |
254 | return (vmcs_config.cpu_based_2nd_exec_ctrl & | |
255 | SECONDARY_EXEC_ENABLE_EPT); | |
256 | } | |
257 | ||
258 | static inline int vm_need_ept(void) | |
259 | { | |
260 | return (cpu_has_vmx_ept() && enable_ept); | |
261 | } | |
262 | ||
f78e0e2e SY |
263 | static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm) |
264 | { | |
265 | return ((cpu_has_vmx_virtualize_apic_accesses()) && | |
266 | (irqchip_in_kernel(kvm))); | |
267 | } | |
268 | ||
2384d2b3 SY |
269 | static inline int cpu_has_vmx_vpid(void) |
270 | { | |
271 | return (vmcs_config.cpu_based_2nd_exec_ctrl & | |
272 | SECONDARY_EXEC_ENABLE_VPID); | |
273 | } | |
274 | ||
f08864b4 SY |
275 | static inline int cpu_has_virtual_nmis(void) |
276 | { | |
277 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; | |
278 | } | |
279 | ||
8b9cf98c | 280 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
281 | { |
282 | int i; | |
283 | ||
a2fa3e9f GH |
284 | for (i = 0; i < vmx->nmsrs; ++i) |
285 | if (vmx->guest_msrs[i].index == msr) | |
a75beee6 ED |
286 | return i; |
287 | return -1; | |
288 | } | |
289 | ||
2384d2b3 SY |
290 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
291 | { | |
292 | struct { | |
293 | u64 vpid : 16; | |
294 | u64 rsvd : 48; | |
295 | u64 gva; | |
296 | } operand = { vpid, 0, gva }; | |
297 | ||
4ecac3fd | 298 | asm volatile (__ex(ASM_VMX_INVVPID) |
2384d2b3 SY |
299 | /* CF==1 or ZF==1 --> rc = -1 */ |
300 | "; ja 1f ; ud2 ; 1:" | |
301 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
302 | } | |
303 | ||
1439442c SY |
304 | static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
305 | { | |
306 | struct { | |
307 | u64 eptp, gpa; | |
308 | } operand = {eptp, gpa}; | |
309 | ||
4ecac3fd | 310 | asm volatile (__ex(ASM_VMX_INVEPT) |
1439442c SY |
311 | /* CF==1 or ZF==1 --> rc = -1 */ |
312 | "; ja 1f ; ud2 ; 1:\n" | |
313 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
314 | } | |
315 | ||
8b9cf98c | 316 | static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
317 | { |
318 | int i; | |
319 | ||
8b9cf98c | 320 | i = __find_msr_index(vmx, msr); |
a75beee6 | 321 | if (i >= 0) |
a2fa3e9f | 322 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 323 | return NULL; |
7725f0ba AK |
324 | } |
325 | ||
6aa8b732 AK |
326 | static void vmcs_clear(struct vmcs *vmcs) |
327 | { | |
328 | u64 phys_addr = __pa(vmcs); | |
329 | u8 error; | |
330 | ||
4ecac3fd | 331 | asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
6aa8b732 AK |
332 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) |
333 | : "cc", "memory"); | |
334 | if (error) | |
335 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
336 | vmcs, phys_addr); | |
337 | } | |
338 | ||
339 | static void __vcpu_clear(void *arg) | |
340 | { | |
8b9cf98c | 341 | struct vcpu_vmx *vmx = arg; |
d3b2c338 | 342 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 343 | |
8b9cf98c | 344 | if (vmx->vcpu.cpu == cpu) |
a2fa3e9f GH |
345 | vmcs_clear(vmx->vmcs); |
346 | if (per_cpu(current_vmcs, cpu) == vmx->vmcs) | |
6aa8b732 | 347 | per_cpu(current_vmcs, cpu) = NULL; |
ad312c7c | 348 | rdtscll(vmx->vcpu.arch.host_tsc); |
543e4243 AK |
349 | list_del(&vmx->local_vcpus_link); |
350 | vmx->vcpu.cpu = -1; | |
351 | vmx->launched = 0; | |
6aa8b732 AK |
352 | } |
353 | ||
8b9cf98c | 354 | static void vcpu_clear(struct vcpu_vmx *vmx) |
8d0be2b3 | 355 | { |
eae5ecb5 AK |
356 | if (vmx->vcpu.cpu == -1) |
357 | return; | |
8691e5a8 | 358 | smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1); |
8d0be2b3 AK |
359 | } |
360 | ||
2384d2b3 SY |
361 | static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx) |
362 | { | |
363 | if (vmx->vpid == 0) | |
364 | return; | |
365 | ||
366 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0); | |
367 | } | |
368 | ||
1439442c SY |
369 | static inline void ept_sync_global(void) |
370 | { | |
371 | if (cpu_has_vmx_invept_global()) | |
372 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); | |
373 | } | |
374 | ||
375 | static inline void ept_sync_context(u64 eptp) | |
376 | { | |
377 | if (vm_need_ept()) { | |
378 | if (cpu_has_vmx_invept_context()) | |
379 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
380 | else | |
381 | ept_sync_global(); | |
382 | } | |
383 | } | |
384 | ||
385 | static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa) | |
386 | { | |
387 | if (vm_need_ept()) { | |
388 | if (cpu_has_vmx_invept_individual_addr()) | |
389 | __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR, | |
390 | eptp, gpa); | |
391 | else | |
392 | ept_sync_context(eptp); | |
393 | } | |
394 | } | |
395 | ||
6aa8b732 AK |
396 | static unsigned long vmcs_readl(unsigned long field) |
397 | { | |
398 | unsigned long value; | |
399 | ||
4ecac3fd | 400 | asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX) |
6aa8b732 AK |
401 | : "=a"(value) : "d"(field) : "cc"); |
402 | return value; | |
403 | } | |
404 | ||
405 | static u16 vmcs_read16(unsigned long field) | |
406 | { | |
407 | return vmcs_readl(field); | |
408 | } | |
409 | ||
410 | static u32 vmcs_read32(unsigned long field) | |
411 | { | |
412 | return vmcs_readl(field); | |
413 | } | |
414 | ||
415 | static u64 vmcs_read64(unsigned long field) | |
416 | { | |
05b3e0c2 | 417 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
418 | return vmcs_readl(field); |
419 | #else | |
420 | return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32); | |
421 | #endif | |
422 | } | |
423 | ||
e52de1b8 AK |
424 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
425 | { | |
426 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
427 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
428 | dump_stack(); | |
429 | } | |
430 | ||
6aa8b732 AK |
431 | static void vmcs_writel(unsigned long field, unsigned long value) |
432 | { | |
433 | u8 error; | |
434 | ||
4ecac3fd | 435 | asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
d77c26fc | 436 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
437 | if (unlikely(error)) |
438 | vmwrite_error(field, value); | |
6aa8b732 AK |
439 | } |
440 | ||
441 | static void vmcs_write16(unsigned long field, u16 value) | |
442 | { | |
443 | vmcs_writel(field, value); | |
444 | } | |
445 | ||
446 | static void vmcs_write32(unsigned long field, u32 value) | |
447 | { | |
448 | vmcs_writel(field, value); | |
449 | } | |
450 | ||
451 | static void vmcs_write64(unsigned long field, u64 value) | |
452 | { | |
6aa8b732 | 453 | vmcs_writel(field, value); |
7682f2d0 | 454 | #ifndef CONFIG_X86_64 |
6aa8b732 AK |
455 | asm volatile (""); |
456 | vmcs_writel(field+1, value >> 32); | |
457 | #endif | |
458 | } | |
459 | ||
2ab455cc AL |
460 | static void vmcs_clear_bits(unsigned long field, u32 mask) |
461 | { | |
462 | vmcs_writel(field, vmcs_readl(field) & ~mask); | |
463 | } | |
464 | ||
465 | static void vmcs_set_bits(unsigned long field, u32 mask) | |
466 | { | |
467 | vmcs_writel(field, vmcs_readl(field) | mask); | |
468 | } | |
469 | ||
abd3f2d6 AK |
470 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
471 | { | |
472 | u32 eb; | |
473 | ||
7aa81cc0 | 474 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR); |
abd3f2d6 AK |
475 | if (!vcpu->fpu_active) |
476 | eb |= 1u << NM_VECTOR; | |
477 | if (vcpu->guest_debug.enabled) | |
19bd8afd | 478 | eb |= 1u << DB_VECTOR; |
ad312c7c | 479 | if (vcpu->arch.rmode.active) |
abd3f2d6 | 480 | eb = ~0; |
1439442c SY |
481 | if (vm_need_ept()) |
482 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ | |
abd3f2d6 AK |
483 | vmcs_write32(EXCEPTION_BITMAP, eb); |
484 | } | |
485 | ||
33ed6329 AK |
486 | static void reload_tss(void) |
487 | { | |
33ed6329 AK |
488 | /* |
489 | * VT restores TR but not its size. Useless. | |
490 | */ | |
491 | struct descriptor_table gdt; | |
a5f61300 | 492 | struct desc_struct *descs; |
33ed6329 | 493 | |
d6e88aec | 494 | kvm_get_gdt(&gdt); |
33ed6329 AK |
495 | descs = (void *)gdt.base; |
496 | descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ | |
497 | load_TR_desc(); | |
33ed6329 AK |
498 | } |
499 | ||
8b9cf98c | 500 | static void load_transition_efer(struct vcpu_vmx *vmx) |
2cc51560 | 501 | { |
a2fa3e9f | 502 | int efer_offset = vmx->msr_offset_efer; |
51c6cf66 AK |
503 | u64 host_efer = vmx->host_msrs[efer_offset].data; |
504 | u64 guest_efer = vmx->guest_msrs[efer_offset].data; | |
505 | u64 ignore_bits; | |
506 | ||
507 | if (efer_offset < 0) | |
508 | return; | |
509 | /* | |
510 | * NX is emulated; LMA and LME handled by hardware; SCE meaninless | |
511 | * outside long mode | |
512 | */ | |
513 | ignore_bits = EFER_NX | EFER_SCE; | |
514 | #ifdef CONFIG_X86_64 | |
515 | ignore_bits |= EFER_LMA | EFER_LME; | |
516 | /* SCE is meaningful only in long mode on Intel */ | |
517 | if (guest_efer & EFER_LMA) | |
518 | ignore_bits &= ~(u64)EFER_SCE; | |
519 | #endif | |
520 | if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits)) | |
521 | return; | |
2cc51560 | 522 | |
51c6cf66 AK |
523 | vmx->host_state.guest_efer_loaded = 1; |
524 | guest_efer &= ~ignore_bits; | |
525 | guest_efer |= host_efer & ignore_bits; | |
526 | wrmsrl(MSR_EFER, guest_efer); | |
8b9cf98c | 527 | vmx->vcpu.stat.efer_reload++; |
2cc51560 ED |
528 | } |
529 | ||
51c6cf66 AK |
530 | static void reload_host_efer(struct vcpu_vmx *vmx) |
531 | { | |
532 | if (vmx->host_state.guest_efer_loaded) { | |
533 | vmx->host_state.guest_efer_loaded = 0; | |
534 | load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1); | |
535 | } | |
536 | } | |
537 | ||
04d2cc77 | 538 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 539 | { |
04d2cc77 AK |
540 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
541 | ||
a2fa3e9f | 542 | if (vmx->host_state.loaded) |
33ed6329 AK |
543 | return; |
544 | ||
a2fa3e9f | 545 | vmx->host_state.loaded = 1; |
33ed6329 AK |
546 | /* |
547 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
548 | * allow segment selectors with cpl > 0 or ti == 1. | |
549 | */ | |
d6e88aec | 550 | vmx->host_state.ldt_sel = kvm_read_ldt(); |
152d3f2f | 551 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
d6e88aec | 552 | vmx->host_state.fs_sel = kvm_read_fs(); |
152d3f2f | 553 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 554 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
555 | vmx->host_state.fs_reload_needed = 0; |
556 | } else { | |
33ed6329 | 557 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 558 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 559 | } |
d6e88aec | 560 | vmx->host_state.gs_sel = kvm_read_gs(); |
a2fa3e9f GH |
561 | if (!(vmx->host_state.gs_sel & 7)) |
562 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
563 | else { |
564 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 565 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
566 | } |
567 | ||
568 | #ifdef CONFIG_X86_64 | |
569 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
570 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
571 | #else | |
a2fa3e9f GH |
572 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
573 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 574 | #endif |
707c0874 AK |
575 | |
576 | #ifdef CONFIG_X86_64 | |
d77c26fc | 577 | if (is_long_mode(&vmx->vcpu)) |
a2fa3e9f GH |
578 | save_msrs(vmx->host_msrs + |
579 | vmx->msr_offset_kernel_gs_base, 1); | |
d77c26fc | 580 | |
707c0874 | 581 | #endif |
a2fa3e9f | 582 | load_msrs(vmx->guest_msrs, vmx->save_nmsrs); |
51c6cf66 | 583 | load_transition_efer(vmx); |
33ed6329 AK |
584 | } |
585 | ||
a9b21b62 | 586 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 587 | { |
15ad7146 | 588 | unsigned long flags; |
33ed6329 | 589 | |
a2fa3e9f | 590 | if (!vmx->host_state.loaded) |
33ed6329 AK |
591 | return; |
592 | ||
e1beb1d3 | 593 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 594 | vmx->host_state.loaded = 0; |
152d3f2f | 595 | if (vmx->host_state.fs_reload_needed) |
d6e88aec | 596 | kvm_load_fs(vmx->host_state.fs_sel); |
152d3f2f | 597 | if (vmx->host_state.gs_ldt_reload_needed) { |
d6e88aec | 598 | kvm_load_ldt(vmx->host_state.ldt_sel); |
33ed6329 AK |
599 | /* |
600 | * If we have to reload gs, we must take care to | |
601 | * preserve our gs base. | |
602 | */ | |
15ad7146 | 603 | local_irq_save(flags); |
d6e88aec | 604 | kvm_load_gs(vmx->host_state.gs_sel); |
33ed6329 AK |
605 | #ifdef CONFIG_X86_64 |
606 | wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE)); | |
607 | #endif | |
15ad7146 | 608 | local_irq_restore(flags); |
33ed6329 | 609 | } |
152d3f2f | 610 | reload_tss(); |
a2fa3e9f GH |
611 | save_msrs(vmx->guest_msrs, vmx->save_nmsrs); |
612 | load_msrs(vmx->host_msrs, vmx->save_nmsrs); | |
51c6cf66 | 613 | reload_host_efer(vmx); |
33ed6329 AK |
614 | } |
615 | ||
a9b21b62 AK |
616 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
617 | { | |
618 | preempt_disable(); | |
619 | __vmx_load_host_state(vmx); | |
620 | preempt_enable(); | |
621 | } | |
622 | ||
6aa8b732 AK |
623 | /* |
624 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
625 | * vcpu mutex is already taken. | |
626 | */ | |
15ad7146 | 627 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 628 | { |
a2fa3e9f GH |
629 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
630 | u64 phys_addr = __pa(vmx->vmcs); | |
019960ae | 631 | u64 tsc_this, delta, new_offset; |
6aa8b732 | 632 | |
a3d7f85f | 633 | if (vcpu->cpu != cpu) { |
8b9cf98c | 634 | vcpu_clear(vmx); |
2f599714 | 635 | kvm_migrate_timers(vcpu); |
2384d2b3 | 636 | vpid_sync_vcpu_all(vmx); |
543e4243 AK |
637 | local_irq_disable(); |
638 | list_add(&vmx->local_vcpus_link, | |
639 | &per_cpu(vcpus_on_cpu, cpu)); | |
640 | local_irq_enable(); | |
a3d7f85f | 641 | } |
6aa8b732 | 642 | |
a2fa3e9f | 643 | if (per_cpu(current_vmcs, cpu) != vmx->vmcs) { |
6aa8b732 AK |
644 | u8 error; |
645 | ||
a2fa3e9f | 646 | per_cpu(current_vmcs, cpu) = vmx->vmcs; |
4ecac3fd | 647 | asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" |
6aa8b732 AK |
648 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) |
649 | : "cc"); | |
650 | if (error) | |
651 | printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n", | |
a2fa3e9f | 652 | vmx->vmcs, phys_addr); |
6aa8b732 AK |
653 | } |
654 | ||
655 | if (vcpu->cpu != cpu) { | |
656 | struct descriptor_table dt; | |
657 | unsigned long sysenter_esp; | |
658 | ||
659 | vcpu->cpu = cpu; | |
660 | /* | |
661 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
662 | * processors. | |
663 | */ | |
d6e88aec AK |
664 | vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */ |
665 | kvm_get_gdt(&dt); | |
6aa8b732 AK |
666 | vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */ |
667 | ||
668 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
669 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
7700270e AK |
670 | |
671 | /* | |
672 | * Make sure the time stamp counter is monotonous. | |
673 | */ | |
674 | rdtscll(tsc_this); | |
019960ae AK |
675 | if (tsc_this < vcpu->arch.host_tsc) { |
676 | delta = vcpu->arch.host_tsc - tsc_this; | |
677 | new_offset = vmcs_read64(TSC_OFFSET) + delta; | |
678 | vmcs_write64(TSC_OFFSET, new_offset); | |
679 | } | |
6aa8b732 | 680 | } |
6aa8b732 AK |
681 | } |
682 | ||
683 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
684 | { | |
a9b21b62 | 685 | __vmx_load_host_state(to_vmx(vcpu)); |
6aa8b732 AK |
686 | } |
687 | ||
5fd86fcf AK |
688 | static void vmx_fpu_activate(struct kvm_vcpu *vcpu) |
689 | { | |
690 | if (vcpu->fpu_active) | |
691 | return; | |
692 | vcpu->fpu_active = 1; | |
707d92fa | 693 | vmcs_clear_bits(GUEST_CR0, X86_CR0_TS); |
ad312c7c | 694 | if (vcpu->arch.cr0 & X86_CR0_TS) |
707d92fa | 695 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS); |
5fd86fcf AK |
696 | update_exception_bitmap(vcpu); |
697 | } | |
698 | ||
699 | static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu) | |
700 | { | |
701 | if (!vcpu->fpu_active) | |
702 | return; | |
703 | vcpu->fpu_active = 0; | |
707d92fa | 704 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS); |
5fd86fcf AK |
705 | update_exception_bitmap(vcpu); |
706 | } | |
707 | ||
6aa8b732 AK |
708 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
709 | { | |
710 | return vmcs_readl(GUEST_RFLAGS); | |
711 | } | |
712 | ||
713 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
714 | { | |
ad312c7c | 715 | if (vcpu->arch.rmode.active) |
053de044 | 716 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
717 | vmcs_writel(GUEST_RFLAGS, rflags); |
718 | } | |
719 | ||
720 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
721 | { | |
722 | unsigned long rip; | |
723 | u32 interruptibility; | |
724 | ||
5fdbf976 | 725 | rip = kvm_rip_read(vcpu); |
6aa8b732 | 726 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
5fdbf976 | 727 | kvm_rip_write(vcpu, rip); |
6aa8b732 AK |
728 | |
729 | /* | |
730 | * We emulated an instruction, so temporary interrupt blocking | |
731 | * should be removed, if set. | |
732 | */ | |
733 | interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
734 | if (interruptibility & 3) | |
735 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
736 | interruptibility & ~3); | |
ad312c7c | 737 | vcpu->arch.interrupt_window_open = 1; |
6aa8b732 AK |
738 | } |
739 | ||
298101da AK |
740 | static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
741 | bool has_error_code, u32 error_code) | |
742 | { | |
77ab6db0 JK |
743 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
744 | ||
745 | if (has_error_code) | |
746 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); | |
747 | ||
748 | if (vcpu->arch.rmode.active) { | |
749 | vmx->rmode.irq.pending = true; | |
750 | vmx->rmode.irq.vector = nr; | |
751 | vmx->rmode.irq.rip = kvm_rip_read(vcpu); | |
752 | if (nr == BP_VECTOR) | |
753 | vmx->rmode.irq.rip++; | |
754 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
755 | nr | INTR_TYPE_SOFT_INTR | |
756 | | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0) | |
757 | | INTR_INFO_VALID_MASK); | |
758 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1); | |
759 | kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1); | |
760 | return; | |
761 | } | |
762 | ||
298101da AK |
763 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
764 | nr | INTR_TYPE_EXCEPTION | |
2e11384c | 765 | | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0) |
298101da | 766 | | INTR_INFO_VALID_MASK); |
298101da AK |
767 | } |
768 | ||
769 | static bool vmx_exception_injected(struct kvm_vcpu *vcpu) | |
770 | { | |
35920a35 | 771 | return false; |
298101da AK |
772 | } |
773 | ||
a75beee6 ED |
774 | /* |
775 | * Swap MSR entry in host/guest MSR entry array. | |
776 | */ | |
54e11fa1 | 777 | #ifdef CONFIG_X86_64 |
8b9cf98c | 778 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 779 | { |
a2fa3e9f GH |
780 | struct kvm_msr_entry tmp; |
781 | ||
782 | tmp = vmx->guest_msrs[to]; | |
783 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
784 | vmx->guest_msrs[from] = tmp; | |
785 | tmp = vmx->host_msrs[to]; | |
786 | vmx->host_msrs[to] = vmx->host_msrs[from]; | |
787 | vmx->host_msrs[from] = tmp; | |
a75beee6 | 788 | } |
54e11fa1 | 789 | #endif |
a75beee6 | 790 | |
e38aea3e AK |
791 | /* |
792 | * Set up the vmcs to automatically save and restore system | |
793 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
794 | * mode, as fiddling with msrs is very expensive. | |
795 | */ | |
8b9cf98c | 796 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 797 | { |
2cc51560 | 798 | int save_nmsrs; |
e38aea3e | 799 | |
33f9c505 | 800 | vmx_load_host_state(vmx); |
a75beee6 ED |
801 | save_nmsrs = 0; |
802 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 803 | if (is_long_mode(&vmx->vcpu)) { |
2cc51560 ED |
804 | int index; |
805 | ||
8b9cf98c | 806 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 807 | if (index >= 0) |
8b9cf98c RR |
808 | move_msr_up(vmx, index, save_nmsrs++); |
809 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 810 | if (index >= 0) |
8b9cf98c RR |
811 | move_msr_up(vmx, index, save_nmsrs++); |
812 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 813 | if (index >= 0) |
8b9cf98c RR |
814 | move_msr_up(vmx, index, save_nmsrs++); |
815 | index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE); | |
a75beee6 | 816 | if (index >= 0) |
8b9cf98c | 817 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
818 | /* |
819 | * MSR_K6_STAR is only needed on long mode guests, and only | |
820 | * if efer.sce is enabled. | |
821 | */ | |
8b9cf98c | 822 | index = __find_msr_index(vmx, MSR_K6_STAR); |
ad312c7c | 823 | if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE)) |
8b9cf98c | 824 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
825 | } |
826 | #endif | |
a2fa3e9f | 827 | vmx->save_nmsrs = save_nmsrs; |
e38aea3e | 828 | |
4d56c8a7 | 829 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 830 | vmx->msr_offset_kernel_gs_base = |
8b9cf98c | 831 | __find_msr_index(vmx, MSR_KERNEL_GS_BASE); |
4d56c8a7 | 832 | #endif |
8b9cf98c | 833 | vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER); |
e38aea3e AK |
834 | } |
835 | ||
6aa8b732 AK |
836 | /* |
837 | * reads and returns guest's timestamp counter "register" | |
838 | * guest_tsc = host_tsc + tsc_offset -- 21.3 | |
839 | */ | |
840 | static u64 guest_read_tsc(void) | |
841 | { | |
842 | u64 host_tsc, tsc_offset; | |
843 | ||
844 | rdtscll(host_tsc); | |
845 | tsc_offset = vmcs_read64(TSC_OFFSET); | |
846 | return host_tsc + tsc_offset; | |
847 | } | |
848 | ||
849 | /* | |
850 | * writes 'guest_tsc' into guest's timestamp counter "register" | |
851 | * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc | |
852 | */ | |
853 | static void guest_write_tsc(u64 guest_tsc) | |
854 | { | |
855 | u64 host_tsc; | |
856 | ||
857 | rdtscll(host_tsc); | |
858 | vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc); | |
859 | } | |
860 | ||
6aa8b732 AK |
861 | /* |
862 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
863 | * Returns 0 on success, non-0 otherwise. | |
864 | * Assumes vcpu_load() was already called. | |
865 | */ | |
866 | static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
867 | { | |
868 | u64 data; | |
a2fa3e9f | 869 | struct kvm_msr_entry *msr; |
6aa8b732 AK |
870 | |
871 | if (!pdata) { | |
872 | printk(KERN_ERR "BUG: get_msr called with NULL pdata\n"); | |
873 | return -EINVAL; | |
874 | } | |
875 | ||
876 | switch (msr_index) { | |
05b3e0c2 | 877 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
878 | case MSR_FS_BASE: |
879 | data = vmcs_readl(GUEST_FS_BASE); | |
880 | break; | |
881 | case MSR_GS_BASE: | |
882 | data = vmcs_readl(GUEST_GS_BASE); | |
883 | break; | |
884 | case MSR_EFER: | |
3bab1f5d | 885 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
886 | #endif |
887 | case MSR_IA32_TIME_STAMP_COUNTER: | |
888 | data = guest_read_tsc(); | |
889 | break; | |
890 | case MSR_IA32_SYSENTER_CS: | |
891 | data = vmcs_read32(GUEST_SYSENTER_CS); | |
892 | break; | |
893 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 894 | data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
895 | break; |
896 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 897 | data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 898 | break; |
6aa8b732 | 899 | default: |
8b9cf98c | 900 | msr = find_msr_entry(to_vmx(vcpu), msr_index); |
3bab1f5d AK |
901 | if (msr) { |
902 | data = msr->data; | |
903 | break; | |
6aa8b732 | 904 | } |
3bab1f5d | 905 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
906 | } |
907 | ||
908 | *pdata = data; | |
909 | return 0; | |
910 | } | |
911 | ||
912 | /* | |
913 | * Writes msr value into into the appropriate "register". | |
914 | * Returns 0 on success, non-0 otherwise. | |
915 | * Assumes vcpu_load() was already called. | |
916 | */ | |
917 | static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
918 | { | |
a2fa3e9f GH |
919 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
920 | struct kvm_msr_entry *msr; | |
2cc51560 ED |
921 | int ret = 0; |
922 | ||
6aa8b732 | 923 | switch (msr_index) { |
05b3e0c2 | 924 | #ifdef CONFIG_X86_64 |
3bab1f5d | 925 | case MSR_EFER: |
a9b21b62 | 926 | vmx_load_host_state(vmx); |
2cc51560 | 927 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
2cc51560 | 928 | break; |
6aa8b732 AK |
929 | case MSR_FS_BASE: |
930 | vmcs_writel(GUEST_FS_BASE, data); | |
931 | break; | |
932 | case MSR_GS_BASE: | |
933 | vmcs_writel(GUEST_GS_BASE, data); | |
934 | break; | |
935 | #endif | |
936 | case MSR_IA32_SYSENTER_CS: | |
937 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
938 | break; | |
939 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 940 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
941 | break; |
942 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 943 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 944 | break; |
d27d4aca | 945 | case MSR_IA32_TIME_STAMP_COUNTER: |
6aa8b732 | 946 | guest_write_tsc(data); |
efa67e0d CL |
947 | break; |
948 | case MSR_P6_PERFCTR0: | |
949 | case MSR_P6_PERFCTR1: | |
950 | case MSR_P6_EVNTSEL0: | |
951 | case MSR_P6_EVNTSEL1: | |
952 | /* | |
953 | * Just discard all writes to the performance counters; this | |
954 | * should keep both older linux and windows 64-bit guests | |
955 | * happy | |
956 | */ | |
957 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data); | |
958 | ||
6aa8b732 | 959 | break; |
6aa8b732 | 960 | default: |
a9b21b62 | 961 | vmx_load_host_state(vmx); |
8b9cf98c | 962 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d AK |
963 | if (msr) { |
964 | msr->data = data; | |
965 | break; | |
6aa8b732 | 966 | } |
2cc51560 | 967 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
6aa8b732 AK |
968 | } |
969 | ||
2cc51560 | 970 | return ret; |
6aa8b732 AK |
971 | } |
972 | ||
5fdbf976 | 973 | static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
6aa8b732 | 974 | { |
5fdbf976 MT |
975 | __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); |
976 | switch (reg) { | |
977 | case VCPU_REGS_RSP: | |
978 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
979 | break; | |
980 | case VCPU_REGS_RIP: | |
981 | vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); | |
982 | break; | |
983 | default: | |
984 | break; | |
985 | } | |
6aa8b732 AK |
986 | } |
987 | ||
988 | static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
989 | { | |
990 | unsigned long dr7 = 0x400; | |
6aa8b732 AK |
991 | int old_singlestep; |
992 | ||
6aa8b732 AK |
993 | old_singlestep = vcpu->guest_debug.singlestep; |
994 | ||
995 | vcpu->guest_debug.enabled = dbg->enabled; | |
996 | if (vcpu->guest_debug.enabled) { | |
997 | int i; | |
998 | ||
999 | dr7 |= 0x200; /* exact */ | |
1000 | for (i = 0; i < 4; ++i) { | |
1001 | if (!dbg->breakpoints[i].enabled) | |
1002 | continue; | |
1003 | vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address; | |
1004 | dr7 |= 2 << (i*2); /* global enable */ | |
1005 | dr7 |= 0 << (i*4+16); /* execution breakpoint */ | |
1006 | } | |
1007 | ||
6aa8b732 | 1008 | vcpu->guest_debug.singlestep = dbg->singlestep; |
abd3f2d6 | 1009 | } else |
6aa8b732 | 1010 | vcpu->guest_debug.singlestep = 0; |
6aa8b732 AK |
1011 | |
1012 | if (old_singlestep && !vcpu->guest_debug.singlestep) { | |
1013 | unsigned long flags; | |
1014 | ||
1015 | flags = vmcs_readl(GUEST_RFLAGS); | |
1016 | flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
1017 | vmcs_writel(GUEST_RFLAGS, flags); | |
1018 | } | |
1019 | ||
abd3f2d6 | 1020 | update_exception_bitmap(vcpu); |
6aa8b732 AK |
1021 | vmcs_writel(GUEST_DR7, dr7); |
1022 | ||
1023 | return 0; | |
1024 | } | |
1025 | ||
2a8067f1 ED |
1026 | static int vmx_get_irq(struct kvm_vcpu *vcpu) |
1027 | { | |
f7d9238f AK |
1028 | if (!vcpu->arch.interrupt.pending) |
1029 | return -1; | |
1030 | return vcpu->arch.interrupt.nr; | |
2a8067f1 ED |
1031 | } |
1032 | ||
6aa8b732 AK |
1033 | static __init int cpu_has_kvm_support(void) |
1034 | { | |
1035 | unsigned long ecx = cpuid_ecx(1); | |
1036 | return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */ | |
1037 | } | |
1038 | ||
1039 | static __init int vmx_disabled_by_bios(void) | |
1040 | { | |
1041 | u64 msr; | |
1042 | ||
1043 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
9ea542fa SY |
1044 | return (msr & (FEATURE_CONTROL_LOCKED | |
1045 | FEATURE_CONTROL_VMXON_ENABLED)) | |
1046 | == FEATURE_CONTROL_LOCKED; | |
62b3ffb8 | 1047 | /* locked but not enabled */ |
6aa8b732 AK |
1048 | } |
1049 | ||
774c47f1 | 1050 | static void hardware_enable(void *garbage) |
6aa8b732 AK |
1051 | { |
1052 | int cpu = raw_smp_processor_id(); | |
1053 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
1054 | u64 old; | |
1055 | ||
543e4243 | 1056 | INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu)); |
6aa8b732 | 1057 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
9ea542fa SY |
1058 | if ((old & (FEATURE_CONTROL_LOCKED | |
1059 | FEATURE_CONTROL_VMXON_ENABLED)) | |
1060 | != (FEATURE_CONTROL_LOCKED | | |
1061 | FEATURE_CONTROL_VMXON_ENABLED)) | |
6aa8b732 | 1062 | /* enable and lock */ |
62b3ffb8 | 1063 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | |
9ea542fa SY |
1064 | FEATURE_CONTROL_LOCKED | |
1065 | FEATURE_CONTROL_VMXON_ENABLED); | |
66aee91a | 1066 | write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */ |
4ecac3fd AK |
1067 | asm volatile (ASM_VMX_VMXON_RAX |
1068 | : : "a"(&phys_addr), "m"(phys_addr) | |
6aa8b732 AK |
1069 | : "memory", "cc"); |
1070 | } | |
1071 | ||
543e4243 AK |
1072 | static void vmclear_local_vcpus(void) |
1073 | { | |
1074 | int cpu = raw_smp_processor_id(); | |
1075 | struct vcpu_vmx *vmx, *n; | |
1076 | ||
1077 | list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu), | |
1078 | local_vcpus_link) | |
1079 | __vcpu_clear(vmx); | |
1080 | } | |
1081 | ||
6aa8b732 AK |
1082 | static void hardware_disable(void *garbage) |
1083 | { | |
543e4243 | 1084 | vmclear_local_vcpus(); |
4ecac3fd | 1085 | asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
e693d71b | 1086 | write_cr4(read_cr4() & ~X86_CR4_VMXE); |
6aa8b732 AK |
1087 | } |
1088 | ||
1c3d14fe | 1089 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 1090 | u32 msr, u32 *result) |
1c3d14fe YS |
1091 | { |
1092 | u32 vmx_msr_low, vmx_msr_high; | |
1093 | u32 ctl = ctl_min | ctl_opt; | |
1094 | ||
1095 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
1096 | ||
1097 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
1098 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
1099 | ||
1100 | /* Ensure minimum (required) set of control bits are supported. */ | |
1101 | if (ctl_min & ~ctl) | |
002c7f7c | 1102 | return -EIO; |
1c3d14fe YS |
1103 | |
1104 | *result = ctl; | |
1105 | return 0; | |
1106 | } | |
1107 | ||
002c7f7c | 1108 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
1109 | { |
1110 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 1111 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
1112 | u32 _pin_based_exec_control = 0; |
1113 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 1114 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
1115 | u32 _vmexit_control = 0; |
1116 | u32 _vmentry_control = 0; | |
1117 | ||
1118 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; | |
f08864b4 | 1119 | opt = PIN_BASED_VIRTUAL_NMIS; |
1c3d14fe YS |
1120 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
1121 | &_pin_based_exec_control) < 0) | |
002c7f7c | 1122 | return -EIO; |
1c3d14fe YS |
1123 | |
1124 | min = CPU_BASED_HLT_EXITING | | |
1125 | #ifdef CONFIG_X86_64 | |
1126 | CPU_BASED_CR8_LOAD_EXITING | | |
1127 | CPU_BASED_CR8_STORE_EXITING | | |
1128 | #endif | |
d56f546d SY |
1129 | CPU_BASED_CR3_LOAD_EXITING | |
1130 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
1131 | CPU_BASED_USE_IO_BITMAPS | |
1132 | CPU_BASED_MOV_DR_EXITING | | |
a7052897 MT |
1133 | CPU_BASED_USE_TSC_OFFSETING | |
1134 | CPU_BASED_INVLPG_EXITING; | |
f78e0e2e | 1135 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 1136 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 1137 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
1138 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
1139 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 1140 | return -EIO; |
6e5d865c YS |
1141 | #ifdef CONFIG_X86_64 |
1142 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
1143 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
1144 | ~CPU_BASED_CR8_STORE_EXITING; | |
1145 | #endif | |
f78e0e2e | 1146 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
1147 | min2 = 0; |
1148 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
2384d2b3 | 1149 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d SY |
1150 | SECONDARY_EXEC_ENABLE_VPID | |
1151 | SECONDARY_EXEC_ENABLE_EPT; | |
1152 | if (adjust_vmx_controls(min2, opt2, | |
1153 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
1154 | &_cpu_based_2nd_exec_control) < 0) |
1155 | return -EIO; | |
1156 | } | |
1157 | #ifndef CONFIG_X86_64 | |
1158 | if (!(_cpu_based_2nd_exec_control & | |
1159 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
1160 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
1161 | #endif | |
d56f546d | 1162 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
a7052897 MT |
1163 | /* CR3 accesses and invlpg don't need to cause VM Exits when EPT |
1164 | enabled */ | |
d56f546d | 1165 | min &= ~(CPU_BASED_CR3_LOAD_EXITING | |
a7052897 MT |
1166 | CPU_BASED_CR3_STORE_EXITING | |
1167 | CPU_BASED_INVLPG_EXITING); | |
d56f546d SY |
1168 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
1169 | &_cpu_based_exec_control) < 0) | |
1170 | return -EIO; | |
1171 | rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, | |
1172 | vmx_capability.ept, vmx_capability.vpid); | |
1173 | } | |
1c3d14fe YS |
1174 | |
1175 | min = 0; | |
1176 | #ifdef CONFIG_X86_64 | |
1177 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
1178 | #endif | |
1179 | opt = 0; | |
1180 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, | |
1181 | &_vmexit_control) < 0) | |
002c7f7c | 1182 | return -EIO; |
1c3d14fe YS |
1183 | |
1184 | min = opt = 0; | |
1185 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, | |
1186 | &_vmentry_control) < 0) | |
002c7f7c | 1187 | return -EIO; |
6aa8b732 | 1188 | |
c68876fd | 1189 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
1190 | |
1191 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
1192 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 1193 | return -EIO; |
1c3d14fe YS |
1194 | |
1195 | #ifdef CONFIG_X86_64 | |
1196 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
1197 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 1198 | return -EIO; |
1c3d14fe YS |
1199 | #endif |
1200 | ||
1201 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
1202 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 1203 | return -EIO; |
1c3d14fe | 1204 | |
002c7f7c YS |
1205 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
1206 | vmcs_conf->order = get_order(vmcs_config.size); | |
1207 | vmcs_conf->revision_id = vmx_msr_low; | |
1c3d14fe | 1208 | |
002c7f7c YS |
1209 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
1210 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 1211 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
1212 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
1213 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe YS |
1214 | |
1215 | return 0; | |
c68876fd | 1216 | } |
6aa8b732 AK |
1217 | |
1218 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
1219 | { | |
1220 | int node = cpu_to_node(cpu); | |
1221 | struct page *pages; | |
1222 | struct vmcs *vmcs; | |
1223 | ||
1c3d14fe | 1224 | pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
1225 | if (!pages) |
1226 | return NULL; | |
1227 | vmcs = page_address(pages); | |
1c3d14fe YS |
1228 | memset(vmcs, 0, vmcs_config.size); |
1229 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
1230 | return vmcs; |
1231 | } | |
1232 | ||
1233 | static struct vmcs *alloc_vmcs(void) | |
1234 | { | |
d3b2c338 | 1235 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
1236 | } |
1237 | ||
1238 | static void free_vmcs(struct vmcs *vmcs) | |
1239 | { | |
1c3d14fe | 1240 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
1241 | } |
1242 | ||
39959588 | 1243 | static void free_kvm_area(void) |
6aa8b732 AK |
1244 | { |
1245 | int cpu; | |
1246 | ||
1247 | for_each_online_cpu(cpu) | |
1248 | free_vmcs(per_cpu(vmxarea, cpu)); | |
1249 | } | |
1250 | ||
6aa8b732 AK |
1251 | static __init int alloc_kvm_area(void) |
1252 | { | |
1253 | int cpu; | |
1254 | ||
1255 | for_each_online_cpu(cpu) { | |
1256 | struct vmcs *vmcs; | |
1257 | ||
1258 | vmcs = alloc_vmcs_cpu(cpu); | |
1259 | if (!vmcs) { | |
1260 | free_kvm_area(); | |
1261 | return -ENOMEM; | |
1262 | } | |
1263 | ||
1264 | per_cpu(vmxarea, cpu) = vmcs; | |
1265 | } | |
1266 | return 0; | |
1267 | } | |
1268 | ||
1269 | static __init int hardware_setup(void) | |
1270 | { | |
002c7f7c YS |
1271 | if (setup_vmcs_config(&vmcs_config) < 0) |
1272 | return -EIO; | |
50a37eb4 JR |
1273 | |
1274 | if (boot_cpu_has(X86_FEATURE_NX)) | |
1275 | kvm_enable_efer_bits(EFER_NX); | |
1276 | ||
6aa8b732 AK |
1277 | return alloc_kvm_area(); |
1278 | } | |
1279 | ||
1280 | static __exit void hardware_unsetup(void) | |
1281 | { | |
1282 | free_kvm_area(); | |
1283 | } | |
1284 | ||
6aa8b732 AK |
1285 | static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save) |
1286 | { | |
1287 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1288 | ||
6af11b9e | 1289 | if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) { |
6aa8b732 AK |
1290 | vmcs_write16(sf->selector, save->selector); |
1291 | vmcs_writel(sf->base, save->base); | |
1292 | vmcs_write32(sf->limit, save->limit); | |
1293 | vmcs_write32(sf->ar_bytes, save->ar); | |
1294 | } else { | |
1295 | u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK) | |
1296 | << AR_DPL_SHIFT; | |
1297 | vmcs_write32(sf->ar_bytes, 0x93 | dpl); | |
1298 | } | |
1299 | } | |
1300 | ||
1301 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
1302 | { | |
1303 | unsigned long flags; | |
a89a8fb9 | 1304 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 1305 | |
a89a8fb9 | 1306 | vmx->emulation_required = 1; |
ad312c7c | 1307 | vcpu->arch.rmode.active = 0; |
6aa8b732 | 1308 | |
ad312c7c ZX |
1309 | vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base); |
1310 | vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit); | |
1311 | vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar); | |
6aa8b732 AK |
1312 | |
1313 | flags = vmcs_readl(GUEST_RFLAGS); | |
053de044 | 1314 | flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM); |
ad312c7c | 1315 | flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT); |
6aa8b732 AK |
1316 | vmcs_writel(GUEST_RFLAGS, flags); |
1317 | ||
66aee91a RR |
1318 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
1319 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
1320 | |
1321 | update_exception_bitmap(vcpu); | |
1322 | ||
a89a8fb9 MG |
1323 | if (emulate_invalid_guest_state) |
1324 | return; | |
1325 | ||
ad312c7c ZX |
1326 | fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es); |
1327 | fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds); | |
1328 | fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs); | |
1329 | fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs); | |
6aa8b732 AK |
1330 | |
1331 | vmcs_write16(GUEST_SS_SELECTOR, 0); | |
1332 | vmcs_write32(GUEST_SS_AR_BYTES, 0x93); | |
1333 | ||
1334 | vmcs_write16(GUEST_CS_SELECTOR, | |
1335 | vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK); | |
1336 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
1337 | } | |
1338 | ||
d77c26fc | 1339 | static gva_t rmode_tss_base(struct kvm *kvm) |
6aa8b732 | 1340 | { |
bfc6d222 | 1341 | if (!kvm->arch.tss_addr) { |
cbc94022 IE |
1342 | gfn_t base_gfn = kvm->memslots[0].base_gfn + |
1343 | kvm->memslots[0].npages - 3; | |
1344 | return base_gfn << PAGE_SHIFT; | |
1345 | } | |
bfc6d222 | 1346 | return kvm->arch.tss_addr; |
6aa8b732 AK |
1347 | } |
1348 | ||
1349 | static void fix_rmode_seg(int seg, struct kvm_save_segment *save) | |
1350 | { | |
1351 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1352 | ||
1353 | save->selector = vmcs_read16(sf->selector); | |
1354 | save->base = vmcs_readl(sf->base); | |
1355 | save->limit = vmcs_read32(sf->limit); | |
1356 | save->ar = vmcs_read32(sf->ar_bytes); | |
15b00f32 JK |
1357 | vmcs_write16(sf->selector, save->base >> 4); |
1358 | vmcs_write32(sf->base, save->base & 0xfffff); | |
6aa8b732 AK |
1359 | vmcs_write32(sf->limit, 0xffff); |
1360 | vmcs_write32(sf->ar_bytes, 0xf3); | |
1361 | } | |
1362 | ||
1363 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
1364 | { | |
1365 | unsigned long flags; | |
a89a8fb9 | 1366 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 1367 | |
a89a8fb9 | 1368 | vmx->emulation_required = 1; |
ad312c7c | 1369 | vcpu->arch.rmode.active = 1; |
6aa8b732 | 1370 | |
ad312c7c | 1371 | vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE); |
6aa8b732 AK |
1372 | vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm)); |
1373 | ||
ad312c7c | 1374 | vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT); |
6aa8b732 AK |
1375 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
1376 | ||
ad312c7c | 1377 | vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES); |
6aa8b732 AK |
1378 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
1379 | ||
1380 | flags = vmcs_readl(GUEST_RFLAGS); | |
ad312c7c ZX |
1381 | vcpu->arch.rmode.save_iopl |
1382 | = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
6aa8b732 | 1383 | |
053de044 | 1384 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
1385 | |
1386 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 1387 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
1388 | update_exception_bitmap(vcpu); |
1389 | ||
a89a8fb9 MG |
1390 | if (emulate_invalid_guest_state) |
1391 | goto continue_rmode; | |
1392 | ||
6aa8b732 AK |
1393 | vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4); |
1394 | vmcs_write32(GUEST_SS_LIMIT, 0xffff); | |
1395 | vmcs_write32(GUEST_SS_AR_BYTES, 0xf3); | |
1396 | ||
1397 | vmcs_write32(GUEST_CS_AR_BYTES, 0xf3); | |
abacf8df | 1398 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); |
8cb5b033 AK |
1399 | if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000) |
1400 | vmcs_writel(GUEST_CS_BASE, 0xf0000); | |
6aa8b732 AK |
1401 | vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4); |
1402 | ||
ad312c7c ZX |
1403 | fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es); |
1404 | fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds); | |
1405 | fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs); | |
1406 | fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs); | |
75880a01 | 1407 | |
a89a8fb9 | 1408 | continue_rmode: |
8668a3c4 | 1409 | kvm_mmu_reset_context(vcpu); |
b7ebfb05 | 1410 | init_rmode(vcpu->kvm); |
6aa8b732 AK |
1411 | } |
1412 | ||
05b3e0c2 | 1413 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1414 | |
1415 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
1416 | { | |
1417 | u32 guest_tr_ar; | |
1418 | ||
1419 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); | |
1420 | if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { | |
1421 | printk(KERN_DEBUG "%s: tss fixup for long mode. \n", | |
b8688d51 | 1422 | __func__); |
6aa8b732 AK |
1423 | vmcs_write32(GUEST_TR_AR_BYTES, |
1424 | (guest_tr_ar & ~AR_TYPE_MASK) | |
1425 | | AR_TYPE_BUSY_64_TSS); | |
1426 | } | |
1427 | ||
ad312c7c | 1428 | vcpu->arch.shadow_efer |= EFER_LMA; |
6aa8b732 | 1429 | |
8b9cf98c | 1430 | find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1431 | vmcs_write32(VM_ENTRY_CONTROLS, |
1432 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 1433 | | VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1434 | } |
1435 | ||
1436 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
1437 | { | |
ad312c7c | 1438 | vcpu->arch.shadow_efer &= ~EFER_LMA; |
6aa8b732 AK |
1439 | |
1440 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1441 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 1442 | & ~VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1443 | } |
1444 | ||
1445 | #endif | |
1446 | ||
2384d2b3 SY |
1447 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
1448 | { | |
1449 | vpid_sync_vcpu_all(to_vmx(vcpu)); | |
4e1096d2 SY |
1450 | if (vm_need_ept()) |
1451 | ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa)); | |
2384d2b3 SY |
1452 | } |
1453 | ||
25c4c276 | 1454 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 1455 | { |
ad312c7c ZX |
1456 | vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK; |
1457 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK; | |
399badf3 AK |
1458 | } |
1459 | ||
1439442c SY |
1460 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
1461 | { | |
1462 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { | |
1463 | if (!load_pdptrs(vcpu, vcpu->arch.cr3)) { | |
1464 | printk(KERN_ERR "EPT: Fail to load pdptrs!\n"); | |
1465 | return; | |
1466 | } | |
1467 | vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]); | |
1468 | vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]); | |
1469 | vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]); | |
1470 | vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]); | |
1471 | } | |
1472 | } | |
1473 | ||
1474 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); | |
1475 | ||
1476 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
1477 | unsigned long cr0, | |
1478 | struct kvm_vcpu *vcpu) | |
1479 | { | |
1480 | if (!(cr0 & X86_CR0_PG)) { | |
1481 | /* From paging/starting to nonpaging */ | |
1482 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 1483 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
1439442c SY |
1484 | (CPU_BASED_CR3_LOAD_EXITING | |
1485 | CPU_BASED_CR3_STORE_EXITING)); | |
1486 | vcpu->arch.cr0 = cr0; | |
1487 | vmx_set_cr4(vcpu, vcpu->arch.cr4); | |
1488 | *hw_cr0 |= X86_CR0_PE | X86_CR0_PG; | |
1489 | *hw_cr0 &= ~X86_CR0_WP; | |
1490 | } else if (!is_paging(vcpu)) { | |
1491 | /* From nonpaging to paging */ | |
1492 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 1493 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
1439442c SY |
1494 | ~(CPU_BASED_CR3_LOAD_EXITING | |
1495 | CPU_BASED_CR3_STORE_EXITING)); | |
1496 | vcpu->arch.cr0 = cr0; | |
1497 | vmx_set_cr4(vcpu, vcpu->arch.cr4); | |
1498 | if (!(vcpu->arch.cr0 & X86_CR0_WP)) | |
1499 | *hw_cr0 &= ~X86_CR0_WP; | |
1500 | } | |
1501 | } | |
1502 | ||
1503 | static void ept_update_paging_mode_cr4(unsigned long *hw_cr4, | |
1504 | struct kvm_vcpu *vcpu) | |
1505 | { | |
1506 | if (!is_paging(vcpu)) { | |
1507 | *hw_cr4 &= ~X86_CR4_PAE; | |
1508 | *hw_cr4 |= X86_CR4_PSE; | |
1509 | } else if (!(vcpu->arch.cr4 & X86_CR4_PAE)) | |
1510 | *hw_cr4 &= ~X86_CR4_PAE; | |
1511 | } | |
1512 | ||
6aa8b732 AK |
1513 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1514 | { | |
1439442c SY |
1515 | unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | |
1516 | KVM_VM_CR0_ALWAYS_ON; | |
1517 | ||
5fd86fcf AK |
1518 | vmx_fpu_deactivate(vcpu); |
1519 | ||
ad312c7c | 1520 | if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1521 | enter_pmode(vcpu); |
1522 | ||
ad312c7c | 1523 | if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1524 | enter_rmode(vcpu); |
1525 | ||
05b3e0c2 | 1526 | #ifdef CONFIG_X86_64 |
ad312c7c | 1527 | if (vcpu->arch.shadow_efer & EFER_LME) { |
707d92fa | 1528 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 1529 | enter_lmode(vcpu); |
707d92fa | 1530 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
1531 | exit_lmode(vcpu); |
1532 | } | |
1533 | #endif | |
1534 | ||
1439442c SY |
1535 | if (vm_need_ept()) |
1536 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); | |
1537 | ||
6aa8b732 | 1538 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 1539 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 1540 | vcpu->arch.cr0 = cr0; |
5fd86fcf | 1541 | |
707d92fa | 1542 | if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE)) |
5fd86fcf | 1543 | vmx_fpu_activate(vcpu); |
6aa8b732 AK |
1544 | } |
1545 | ||
1439442c SY |
1546 | static u64 construct_eptp(unsigned long root_hpa) |
1547 | { | |
1548 | u64 eptp; | |
1549 | ||
1550 | /* TODO write the value reading from MSR */ | |
1551 | eptp = VMX_EPT_DEFAULT_MT | | |
1552 | VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT; | |
1553 | eptp |= (root_hpa & PAGE_MASK); | |
1554 | ||
1555 | return eptp; | |
1556 | } | |
1557 | ||
6aa8b732 AK |
1558 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
1559 | { | |
1439442c SY |
1560 | unsigned long guest_cr3; |
1561 | u64 eptp; | |
1562 | ||
1563 | guest_cr3 = cr3; | |
1564 | if (vm_need_ept()) { | |
1565 | eptp = construct_eptp(cr3); | |
1566 | vmcs_write64(EPT_POINTER, eptp); | |
1567 | ept_sync_context(eptp); | |
1568 | ept_load_pdptrs(vcpu); | |
1569 | guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 : | |
1570 | VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
1571 | } | |
1572 | ||
2384d2b3 | 1573 | vmx_flush_tlb(vcpu); |
1439442c | 1574 | vmcs_writel(GUEST_CR3, guest_cr3); |
ad312c7c | 1575 | if (vcpu->arch.cr0 & X86_CR0_PE) |
5fd86fcf | 1576 | vmx_fpu_deactivate(vcpu); |
6aa8b732 AK |
1577 | } |
1578 | ||
1579 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1580 | { | |
1439442c SY |
1581 | unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ? |
1582 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); | |
1583 | ||
ad312c7c | 1584 | vcpu->arch.cr4 = cr4; |
1439442c SY |
1585 | if (vm_need_ept()) |
1586 | ept_update_paging_mode_cr4(&hw_cr4, vcpu); | |
1587 | ||
1588 | vmcs_writel(CR4_READ_SHADOW, cr4); | |
1589 | vmcs_writel(GUEST_CR4, hw_cr4); | |
6aa8b732 AK |
1590 | } |
1591 | ||
6aa8b732 AK |
1592 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
1593 | { | |
8b9cf98c RR |
1594 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1595 | struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); | |
6aa8b732 | 1596 | |
ad312c7c | 1597 | vcpu->arch.shadow_efer = efer; |
9f62e19a JR |
1598 | if (!msr) |
1599 | return; | |
6aa8b732 AK |
1600 | if (efer & EFER_LMA) { |
1601 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1602 | vmcs_read32(VM_ENTRY_CONTROLS) | | |
1e4e6e00 | 1603 | VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1604 | msr->data = efer; |
1605 | ||
1606 | } else { | |
1607 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1608 | vmcs_read32(VM_ENTRY_CONTROLS) & | |
1e4e6e00 | 1609 | ~VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1610 | |
1611 | msr->data = efer & ~EFER_LME; | |
1612 | } | |
8b9cf98c | 1613 | setup_msrs(vmx); |
6aa8b732 AK |
1614 | } |
1615 | ||
6aa8b732 AK |
1616 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
1617 | { | |
1618 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1619 | ||
1620 | return vmcs_readl(sf->base); | |
1621 | } | |
1622 | ||
1623 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
1624 | struct kvm_segment *var, int seg) | |
1625 | { | |
1626 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1627 | u32 ar; | |
1628 | ||
1629 | var->base = vmcs_readl(sf->base); | |
1630 | var->limit = vmcs_read32(sf->limit); | |
1631 | var->selector = vmcs_read16(sf->selector); | |
1632 | ar = vmcs_read32(sf->ar_bytes); | |
1633 | if (ar & AR_UNUSABLE_MASK) | |
1634 | ar = 0; | |
1635 | var->type = ar & 15; | |
1636 | var->s = (ar >> 4) & 1; | |
1637 | var->dpl = (ar >> 5) & 3; | |
1638 | var->present = (ar >> 7) & 1; | |
1639 | var->avl = (ar >> 12) & 1; | |
1640 | var->l = (ar >> 13) & 1; | |
1641 | var->db = (ar >> 14) & 1; | |
1642 | var->g = (ar >> 15) & 1; | |
1643 | var->unusable = (ar >> 16) & 1; | |
1644 | } | |
1645 | ||
2e4d2653 IE |
1646 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
1647 | { | |
1648 | struct kvm_segment kvm_seg; | |
1649 | ||
1650 | if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */ | |
1651 | return 0; | |
1652 | ||
1653 | if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */ | |
1654 | return 3; | |
1655 | ||
1656 | vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS); | |
1657 | return kvm_seg.selector & 3; | |
1658 | } | |
1659 | ||
653e3108 | 1660 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 1661 | { |
6aa8b732 AK |
1662 | u32 ar; |
1663 | ||
653e3108 | 1664 | if (var->unusable) |
6aa8b732 AK |
1665 | ar = 1 << 16; |
1666 | else { | |
1667 | ar = var->type & 15; | |
1668 | ar |= (var->s & 1) << 4; | |
1669 | ar |= (var->dpl & 3) << 5; | |
1670 | ar |= (var->present & 1) << 7; | |
1671 | ar |= (var->avl & 1) << 12; | |
1672 | ar |= (var->l & 1) << 13; | |
1673 | ar |= (var->db & 1) << 14; | |
1674 | ar |= (var->g & 1) << 15; | |
1675 | } | |
f7fbf1fd UL |
1676 | if (ar == 0) /* a 0 value means unusable */ |
1677 | ar = AR_UNUSABLE_MASK; | |
653e3108 AK |
1678 | |
1679 | return ar; | |
1680 | } | |
1681 | ||
1682 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
1683 | struct kvm_segment *var, int seg) | |
1684 | { | |
1685 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1686 | u32 ar; | |
1687 | ||
ad312c7c ZX |
1688 | if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) { |
1689 | vcpu->arch.rmode.tr.selector = var->selector; | |
1690 | vcpu->arch.rmode.tr.base = var->base; | |
1691 | vcpu->arch.rmode.tr.limit = var->limit; | |
1692 | vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var); | |
653e3108 AK |
1693 | return; |
1694 | } | |
1695 | vmcs_writel(sf->base, var->base); | |
1696 | vmcs_write32(sf->limit, var->limit); | |
1697 | vmcs_write16(sf->selector, var->selector); | |
ad312c7c | 1698 | if (vcpu->arch.rmode.active && var->s) { |
653e3108 AK |
1699 | /* |
1700 | * Hack real-mode segments into vm86 compatibility. | |
1701 | */ | |
1702 | if (var->base == 0xffff0000 && var->selector == 0xf000) | |
1703 | vmcs_writel(sf->base, 0xf0000); | |
1704 | ar = 0xf3; | |
1705 | } else | |
1706 | ar = vmx_segment_access_rights(var); | |
6aa8b732 AK |
1707 | vmcs_write32(sf->ar_bytes, ar); |
1708 | } | |
1709 | ||
6aa8b732 AK |
1710 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
1711 | { | |
1712 | u32 ar = vmcs_read32(GUEST_CS_AR_BYTES); | |
1713 | ||
1714 | *db = (ar >> 14) & 1; | |
1715 | *l = (ar >> 13) & 1; | |
1716 | } | |
1717 | ||
1718 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1719 | { | |
1720 | dt->limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
1721 | dt->base = vmcs_readl(GUEST_IDTR_BASE); | |
1722 | } | |
1723 | ||
1724 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1725 | { | |
1726 | vmcs_write32(GUEST_IDTR_LIMIT, dt->limit); | |
1727 | vmcs_writel(GUEST_IDTR_BASE, dt->base); | |
1728 | } | |
1729 | ||
1730 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1731 | { | |
1732 | dt->limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
1733 | dt->base = vmcs_readl(GUEST_GDTR_BASE); | |
1734 | } | |
1735 | ||
1736 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1737 | { | |
1738 | vmcs_write32(GUEST_GDTR_LIMIT, dt->limit); | |
1739 | vmcs_writel(GUEST_GDTR_BASE, dt->base); | |
1740 | } | |
1741 | ||
648dfaa7 MG |
1742 | static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) |
1743 | { | |
1744 | struct kvm_segment var; | |
1745 | u32 ar; | |
1746 | ||
1747 | vmx_get_segment(vcpu, &var, seg); | |
1748 | ar = vmx_segment_access_rights(&var); | |
1749 | ||
1750 | if (var.base != (var.selector << 4)) | |
1751 | return false; | |
1752 | if (var.limit != 0xffff) | |
1753 | return false; | |
1754 | if (ar != 0xf3) | |
1755 | return false; | |
1756 | ||
1757 | return true; | |
1758 | } | |
1759 | ||
1760 | static bool code_segment_valid(struct kvm_vcpu *vcpu) | |
1761 | { | |
1762 | struct kvm_segment cs; | |
1763 | unsigned int cs_rpl; | |
1764 | ||
1765 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
1766 | cs_rpl = cs.selector & SELECTOR_RPL_MASK; | |
1767 | ||
1768 | if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK)) | |
1769 | return false; | |
1770 | if (!cs.s) | |
1771 | return false; | |
1772 | if (!(~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK))) { | |
1773 | if (cs.dpl > cs_rpl) | |
1774 | return false; | |
1775 | } else if (cs.type & AR_TYPE_CODE_MASK) { | |
1776 | if (cs.dpl != cs_rpl) | |
1777 | return false; | |
1778 | } | |
1779 | if (!cs.present) | |
1780 | return false; | |
1781 | ||
1782 | /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ | |
1783 | return true; | |
1784 | } | |
1785 | ||
1786 | static bool stack_segment_valid(struct kvm_vcpu *vcpu) | |
1787 | { | |
1788 | struct kvm_segment ss; | |
1789 | unsigned int ss_rpl; | |
1790 | ||
1791 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
1792 | ss_rpl = ss.selector & SELECTOR_RPL_MASK; | |
1793 | ||
1794 | if ((ss.type != 3) || (ss.type != 7)) | |
1795 | return false; | |
1796 | if (!ss.s) | |
1797 | return false; | |
1798 | if (ss.dpl != ss_rpl) /* DPL != RPL */ | |
1799 | return false; | |
1800 | if (!ss.present) | |
1801 | return false; | |
1802 | ||
1803 | return true; | |
1804 | } | |
1805 | ||
1806 | static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) | |
1807 | { | |
1808 | struct kvm_segment var; | |
1809 | unsigned int rpl; | |
1810 | ||
1811 | vmx_get_segment(vcpu, &var, seg); | |
1812 | rpl = var.selector & SELECTOR_RPL_MASK; | |
1813 | ||
1814 | if (!var.s) | |
1815 | return false; | |
1816 | if (!var.present) | |
1817 | return false; | |
1818 | if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) { | |
1819 | if (var.dpl < rpl) /* DPL < RPL */ | |
1820 | return false; | |
1821 | } | |
1822 | ||
1823 | /* TODO: Add other members to kvm_segment_field to allow checking for other access | |
1824 | * rights flags | |
1825 | */ | |
1826 | return true; | |
1827 | } | |
1828 | ||
1829 | static bool tr_valid(struct kvm_vcpu *vcpu) | |
1830 | { | |
1831 | struct kvm_segment tr; | |
1832 | ||
1833 | vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); | |
1834 | ||
1835 | if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */ | |
1836 | return false; | |
1837 | if ((tr.type != 3) || (tr.type != 11)) /* TODO: Check if guest is in IA32e mode */ | |
1838 | return false; | |
1839 | if (!tr.present) | |
1840 | return false; | |
1841 | ||
1842 | return true; | |
1843 | } | |
1844 | ||
1845 | static bool ldtr_valid(struct kvm_vcpu *vcpu) | |
1846 | { | |
1847 | struct kvm_segment ldtr; | |
1848 | ||
1849 | vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); | |
1850 | ||
1851 | if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */ | |
1852 | return false; | |
1853 | if (ldtr.type != 2) | |
1854 | return false; | |
1855 | if (!ldtr.present) | |
1856 | return false; | |
1857 | ||
1858 | return true; | |
1859 | } | |
1860 | ||
1861 | static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) | |
1862 | { | |
1863 | struct kvm_segment cs, ss; | |
1864 | ||
1865 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
1866 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
1867 | ||
1868 | return ((cs.selector & SELECTOR_RPL_MASK) == | |
1869 | (ss.selector & SELECTOR_RPL_MASK)); | |
1870 | } | |
1871 | ||
1872 | /* | |
1873 | * Check if guest state is valid. Returns true if valid, false if | |
1874 | * not. | |
1875 | * We assume that registers are always usable | |
1876 | */ | |
1877 | static bool guest_state_valid(struct kvm_vcpu *vcpu) | |
1878 | { | |
1879 | /* real mode guest state checks */ | |
1880 | if (!(vcpu->arch.cr0 & X86_CR0_PE)) { | |
1881 | if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) | |
1882 | return false; | |
1883 | if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) | |
1884 | return false; | |
1885 | if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) | |
1886 | return false; | |
1887 | if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) | |
1888 | return false; | |
1889 | if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) | |
1890 | return false; | |
1891 | if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) | |
1892 | return false; | |
1893 | } else { | |
1894 | /* protected mode guest state checks */ | |
1895 | if (!cs_ss_rpl_check(vcpu)) | |
1896 | return false; | |
1897 | if (!code_segment_valid(vcpu)) | |
1898 | return false; | |
1899 | if (!stack_segment_valid(vcpu)) | |
1900 | return false; | |
1901 | if (!data_segment_valid(vcpu, VCPU_SREG_DS)) | |
1902 | return false; | |
1903 | if (!data_segment_valid(vcpu, VCPU_SREG_ES)) | |
1904 | return false; | |
1905 | if (!data_segment_valid(vcpu, VCPU_SREG_FS)) | |
1906 | return false; | |
1907 | if (!data_segment_valid(vcpu, VCPU_SREG_GS)) | |
1908 | return false; | |
1909 | if (!tr_valid(vcpu)) | |
1910 | return false; | |
1911 | if (!ldtr_valid(vcpu)) | |
1912 | return false; | |
1913 | } | |
1914 | /* TODO: | |
1915 | * - Add checks on RIP | |
1916 | * - Add checks on RFLAGS | |
1917 | */ | |
1918 | ||
1919 | return true; | |
1920 | } | |
1921 | ||
d77c26fc | 1922 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 1923 | { |
6aa8b732 | 1924 | gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT; |
195aefde | 1925 | u16 data = 0; |
10589a46 | 1926 | int ret = 0; |
195aefde | 1927 | int r; |
6aa8b732 | 1928 | |
195aefde IE |
1929 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
1930 | if (r < 0) | |
10589a46 | 1931 | goto out; |
195aefde | 1932 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
464d17c8 SY |
1933 | r = kvm_write_guest_page(kvm, fn++, &data, |
1934 | TSS_IOPB_BASE_OFFSET, sizeof(u16)); | |
195aefde | 1935 | if (r < 0) |
10589a46 | 1936 | goto out; |
195aefde IE |
1937 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
1938 | if (r < 0) | |
10589a46 | 1939 | goto out; |
195aefde IE |
1940 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
1941 | if (r < 0) | |
10589a46 | 1942 | goto out; |
195aefde | 1943 | data = ~0; |
10589a46 MT |
1944 | r = kvm_write_guest_page(kvm, fn, &data, |
1945 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
1946 | sizeof(u8)); | |
195aefde | 1947 | if (r < 0) |
10589a46 MT |
1948 | goto out; |
1949 | ||
1950 | ret = 1; | |
1951 | out: | |
10589a46 | 1952 | return ret; |
6aa8b732 AK |
1953 | } |
1954 | ||
b7ebfb05 SY |
1955 | static int init_rmode_identity_map(struct kvm *kvm) |
1956 | { | |
1957 | int i, r, ret; | |
1958 | pfn_t identity_map_pfn; | |
1959 | u32 tmp; | |
1960 | ||
1961 | if (!vm_need_ept()) | |
1962 | return 1; | |
1963 | if (unlikely(!kvm->arch.ept_identity_pagetable)) { | |
1964 | printk(KERN_ERR "EPT: identity-mapping pagetable " | |
1965 | "haven't been allocated!\n"); | |
1966 | return 0; | |
1967 | } | |
1968 | if (likely(kvm->arch.ept_identity_pagetable_done)) | |
1969 | return 1; | |
1970 | ret = 0; | |
1971 | identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT; | |
1972 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); | |
1973 | if (r < 0) | |
1974 | goto out; | |
1975 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
1976 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
1977 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
1978 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
1979 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
1980 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
1981 | if (r < 0) | |
1982 | goto out; | |
1983 | } | |
1984 | kvm->arch.ept_identity_pagetable_done = true; | |
1985 | ret = 1; | |
1986 | out: | |
1987 | return ret; | |
1988 | } | |
1989 | ||
6aa8b732 AK |
1990 | static void seg_setup(int seg) |
1991 | { | |
1992 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1993 | ||
1994 | vmcs_write16(sf->selector, 0); | |
1995 | vmcs_writel(sf->base, 0); | |
1996 | vmcs_write32(sf->limit, 0xffff); | |
a16b20da | 1997 | vmcs_write32(sf->ar_bytes, 0xf3); |
6aa8b732 AK |
1998 | } |
1999 | ||
f78e0e2e SY |
2000 | static int alloc_apic_access_page(struct kvm *kvm) |
2001 | { | |
2002 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
2003 | int r = 0; | |
2004 | ||
72dc67a6 | 2005 | down_write(&kvm->slots_lock); |
bfc6d222 | 2006 | if (kvm->arch.apic_access_page) |
f78e0e2e SY |
2007 | goto out; |
2008 | kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; | |
2009 | kvm_userspace_mem.flags = 0; | |
2010 | kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL; | |
2011 | kvm_userspace_mem.memory_size = PAGE_SIZE; | |
2012 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
2013 | if (r) | |
2014 | goto out; | |
72dc67a6 | 2015 | |
bfc6d222 | 2016 | kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00); |
f78e0e2e | 2017 | out: |
72dc67a6 | 2018 | up_write(&kvm->slots_lock); |
f78e0e2e SY |
2019 | return r; |
2020 | } | |
2021 | ||
b7ebfb05 SY |
2022 | static int alloc_identity_pagetable(struct kvm *kvm) |
2023 | { | |
2024 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
2025 | int r = 0; | |
2026 | ||
2027 | down_write(&kvm->slots_lock); | |
2028 | if (kvm->arch.ept_identity_pagetable) | |
2029 | goto out; | |
2030 | kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; | |
2031 | kvm_userspace_mem.flags = 0; | |
2032 | kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
2033 | kvm_userspace_mem.memory_size = PAGE_SIZE; | |
2034 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
2035 | if (r) | |
2036 | goto out; | |
2037 | ||
b7ebfb05 SY |
2038 | kvm->arch.ept_identity_pagetable = gfn_to_page(kvm, |
2039 | VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT); | |
b7ebfb05 SY |
2040 | out: |
2041 | up_write(&kvm->slots_lock); | |
2042 | return r; | |
2043 | } | |
2044 | ||
2384d2b3 SY |
2045 | static void allocate_vpid(struct vcpu_vmx *vmx) |
2046 | { | |
2047 | int vpid; | |
2048 | ||
2049 | vmx->vpid = 0; | |
2050 | if (!enable_vpid || !cpu_has_vmx_vpid()) | |
2051 | return; | |
2052 | spin_lock(&vmx_vpid_lock); | |
2053 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
2054 | if (vpid < VMX_NR_VPIDS) { | |
2055 | vmx->vpid = vpid; | |
2056 | __set_bit(vpid, vmx_vpid_bitmap); | |
2057 | } | |
2058 | spin_unlock(&vmx_vpid_lock); | |
2059 | } | |
2060 | ||
8b2cf73c | 2061 | static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr) |
25c5f225 SY |
2062 | { |
2063 | void *va; | |
2064 | ||
2065 | if (!cpu_has_vmx_msr_bitmap()) | |
2066 | return; | |
2067 | ||
2068 | /* | |
2069 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
2070 | * have the write-low and read-high bitmap offsets the wrong way round. | |
2071 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
2072 | */ | |
2073 | va = kmap(msr_bitmap); | |
2074 | if (msr <= 0x1fff) { | |
2075 | __clear_bit(msr, va + 0x000); /* read-low */ | |
2076 | __clear_bit(msr, va + 0x800); /* write-low */ | |
2077 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
2078 | msr &= 0x1fff; | |
2079 | __clear_bit(msr, va + 0x400); /* read-high */ | |
2080 | __clear_bit(msr, va + 0xc00); /* write-high */ | |
2081 | } | |
2082 | kunmap(msr_bitmap); | |
2083 | } | |
2084 | ||
6aa8b732 AK |
2085 | /* |
2086 | * Sets up the vmcs for emulated real mode. | |
2087 | */ | |
8b9cf98c | 2088 | static int vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 AK |
2089 | { |
2090 | u32 host_sysenter_cs; | |
2091 | u32 junk; | |
2092 | unsigned long a; | |
2093 | struct descriptor_table dt; | |
2094 | int i; | |
cd2276a7 | 2095 | unsigned long kvm_vmx_return; |
6e5d865c | 2096 | u32 exec_control; |
6aa8b732 | 2097 | |
6aa8b732 | 2098 | /* I/O */ |
fdef3ad1 HQ |
2099 | vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a)); |
2100 | vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b)); | |
6aa8b732 | 2101 | |
25c5f225 SY |
2102 | if (cpu_has_vmx_msr_bitmap()) |
2103 | vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap)); | |
2104 | ||
6aa8b732 AK |
2105 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
2106 | ||
6aa8b732 | 2107 | /* Control */ |
1c3d14fe YS |
2108 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, |
2109 | vmcs_config.pin_based_exec_ctrl); | |
6e5d865c YS |
2110 | |
2111 | exec_control = vmcs_config.cpu_based_exec_ctrl; | |
2112 | if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) { | |
2113 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
2114 | #ifdef CONFIG_X86_64 | |
2115 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
2116 | CPU_BASED_CR8_LOAD_EXITING; | |
2117 | #endif | |
2118 | } | |
d56f546d SY |
2119 | if (!vm_need_ept()) |
2120 | exec_control |= CPU_BASED_CR3_STORE_EXITING | | |
83dbc83a MT |
2121 | CPU_BASED_CR3_LOAD_EXITING | |
2122 | CPU_BASED_INVLPG_EXITING; | |
6e5d865c | 2123 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); |
6aa8b732 | 2124 | |
83ff3b9d SY |
2125 | if (cpu_has_secondary_exec_ctrls()) { |
2126 | exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; | |
2127 | if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
2128 | exec_control &= | |
2129 | ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
2384d2b3 SY |
2130 | if (vmx->vpid == 0) |
2131 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
d56f546d SY |
2132 | if (!vm_need_ept()) |
2133 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; | |
83ff3b9d SY |
2134 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
2135 | } | |
f78e0e2e | 2136 | |
c7addb90 AK |
2137 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf); |
2138 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf); | |
6aa8b732 AK |
2139 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
2140 | ||
2141 | vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */ | |
2142 | vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */ | |
2143 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ | |
2144 | ||
2145 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ | |
2146 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
2147 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
d6e88aec AK |
2148 | vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */ |
2149 | vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */ | |
6aa8b732 | 2150 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
05b3e0c2 | 2151 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
2152 | rdmsrl(MSR_FS_BASE, a); |
2153 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
2154 | rdmsrl(MSR_GS_BASE, a); | |
2155 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
2156 | #else | |
2157 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
2158 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
2159 | #endif | |
2160 | ||
2161 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
2162 | ||
d6e88aec | 2163 | kvm_get_idt(&dt); |
6aa8b732 AK |
2164 | vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */ |
2165 | ||
d77c26fc | 2166 | asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return)); |
cd2276a7 | 2167 | vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */ |
2cc51560 ED |
2168 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
2169 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
2170 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); | |
6aa8b732 AK |
2171 | |
2172 | rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk); | |
2173 | vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs); | |
2174 | rdmsrl(MSR_IA32_SYSENTER_ESP, a); | |
2175 | vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */ | |
2176 | rdmsrl(MSR_IA32_SYSENTER_EIP, a); | |
2177 | vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */ | |
2178 | ||
6aa8b732 AK |
2179 | for (i = 0; i < NR_VMX_MSR; ++i) { |
2180 | u32 index = vmx_msr_index[i]; | |
2181 | u32 data_low, data_high; | |
2182 | u64 data; | |
a2fa3e9f | 2183 | int j = vmx->nmsrs; |
6aa8b732 AK |
2184 | |
2185 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
2186 | continue; | |
432bd6cb AK |
2187 | if (wrmsr_safe(index, data_low, data_high) < 0) |
2188 | continue; | |
6aa8b732 | 2189 | data = data_low | ((u64)data_high << 32); |
a2fa3e9f GH |
2190 | vmx->host_msrs[j].index = index; |
2191 | vmx->host_msrs[j].reserved = 0; | |
2192 | vmx->host_msrs[j].data = data; | |
2193 | vmx->guest_msrs[j] = vmx->host_msrs[j]; | |
2194 | ++vmx->nmsrs; | |
6aa8b732 | 2195 | } |
6aa8b732 | 2196 | |
1c3d14fe | 2197 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
6aa8b732 AK |
2198 | |
2199 | /* 22.2.1, 20.8.1 */ | |
1c3d14fe YS |
2200 | vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl); |
2201 | ||
e00c8cf2 AK |
2202 | vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL); |
2203 | vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK); | |
2204 | ||
f78e0e2e | 2205 | |
e00c8cf2 AK |
2206 | return 0; |
2207 | } | |
2208 | ||
b7ebfb05 SY |
2209 | static int init_rmode(struct kvm *kvm) |
2210 | { | |
2211 | if (!init_rmode_tss(kvm)) | |
2212 | return 0; | |
2213 | if (!init_rmode_identity_map(kvm)) | |
2214 | return 0; | |
2215 | return 1; | |
2216 | } | |
2217 | ||
e00c8cf2 AK |
2218 | static int vmx_vcpu_reset(struct kvm_vcpu *vcpu) |
2219 | { | |
2220 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
2221 | u64 msr; | |
2222 | int ret; | |
2223 | ||
5fdbf976 | 2224 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)); |
3200f405 | 2225 | down_read(&vcpu->kvm->slots_lock); |
b7ebfb05 | 2226 | if (!init_rmode(vmx->vcpu.kvm)) { |
e00c8cf2 AK |
2227 | ret = -ENOMEM; |
2228 | goto out; | |
2229 | } | |
2230 | ||
ad312c7c | 2231 | vmx->vcpu.arch.rmode.active = 0; |
e00c8cf2 | 2232 | |
ad312c7c | 2233 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
2d3ad1f4 | 2234 | kvm_set_cr8(&vmx->vcpu, 0); |
e00c8cf2 AK |
2235 | msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
2236 | if (vmx->vcpu.vcpu_id == 0) | |
2237 | msr |= MSR_IA32_APICBASE_BSP; | |
2238 | kvm_set_apic_base(&vmx->vcpu, msr); | |
2239 | ||
2240 | fx_init(&vmx->vcpu); | |
2241 | ||
5706be0d | 2242 | seg_setup(VCPU_SREG_CS); |
e00c8cf2 AK |
2243 | /* |
2244 | * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode | |
2245 | * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh. | |
2246 | */ | |
2247 | if (vmx->vcpu.vcpu_id == 0) { | |
2248 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); | |
2249 | vmcs_writel(GUEST_CS_BASE, 0x000f0000); | |
2250 | } else { | |
ad312c7c ZX |
2251 | vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8); |
2252 | vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12); | |
e00c8cf2 | 2253 | } |
e00c8cf2 AK |
2254 | |
2255 | seg_setup(VCPU_SREG_DS); | |
2256 | seg_setup(VCPU_SREG_ES); | |
2257 | seg_setup(VCPU_SREG_FS); | |
2258 | seg_setup(VCPU_SREG_GS); | |
2259 | seg_setup(VCPU_SREG_SS); | |
2260 | ||
2261 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
2262 | vmcs_writel(GUEST_TR_BASE, 0); | |
2263 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
2264 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
2265 | ||
2266 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
2267 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
2268 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
2269 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
2270 | ||
2271 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
2272 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
2273 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
2274 | ||
2275 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
2276 | if (vmx->vcpu.vcpu_id == 0) | |
5fdbf976 | 2277 | kvm_rip_write(vcpu, 0xfff0); |
e00c8cf2 | 2278 | else |
5fdbf976 MT |
2279 | kvm_rip_write(vcpu, 0); |
2280 | kvm_register_write(vcpu, VCPU_REGS_RSP, 0); | |
e00c8cf2 AK |
2281 | |
2282 | /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */ | |
2283 | vmcs_writel(GUEST_DR7, 0x400); | |
2284 | ||
2285 | vmcs_writel(GUEST_GDTR_BASE, 0); | |
2286 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
2287 | ||
2288 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
2289 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
2290 | ||
2291 | vmcs_write32(GUEST_ACTIVITY_STATE, 0); | |
2292 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); | |
2293 | vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0); | |
2294 | ||
2295 | guest_write_tsc(0); | |
2296 | ||
2297 | /* Special registers */ | |
2298 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
2299 | ||
2300 | setup_msrs(vmx); | |
2301 | ||
6aa8b732 AK |
2302 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
2303 | ||
f78e0e2e SY |
2304 | if (cpu_has_vmx_tpr_shadow()) { |
2305 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); | |
2306 | if (vm_need_tpr_shadow(vmx->vcpu.kvm)) | |
2307 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, | |
ad312c7c | 2308 | page_to_phys(vmx->vcpu.arch.apic->regs_page)); |
f78e0e2e SY |
2309 | vmcs_write32(TPR_THRESHOLD, 0); |
2310 | } | |
2311 | ||
2312 | if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
2313 | vmcs_write64(APIC_ACCESS_ADDR, | |
bfc6d222 | 2314 | page_to_phys(vmx->vcpu.kvm->arch.apic_access_page)); |
6aa8b732 | 2315 | |
2384d2b3 SY |
2316 | if (vmx->vpid != 0) |
2317 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
2318 | ||
ad312c7c ZX |
2319 | vmx->vcpu.arch.cr0 = 0x60000010; |
2320 | vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */ | |
8b9cf98c | 2321 | vmx_set_cr4(&vmx->vcpu, 0); |
8b9cf98c | 2322 | vmx_set_efer(&vmx->vcpu, 0); |
8b9cf98c RR |
2323 | vmx_fpu_activate(&vmx->vcpu); |
2324 | update_exception_bitmap(&vmx->vcpu); | |
6aa8b732 | 2325 | |
2384d2b3 SY |
2326 | vpid_sync_vcpu_all(vmx); |
2327 | ||
3200f405 | 2328 | ret = 0; |
6aa8b732 | 2329 | |
a89a8fb9 MG |
2330 | /* HACK: Don't enable emulation on guest boot/reset */ |
2331 | vmx->emulation_required = 0; | |
2332 | ||
6aa8b732 | 2333 | out: |
3200f405 | 2334 | up_read(&vcpu->kvm->slots_lock); |
6aa8b732 AK |
2335 | return ret; |
2336 | } | |
2337 | ||
85f455f7 ED |
2338 | static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq) |
2339 | { | |
9c8cba37 AK |
2340 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2341 | ||
2714d1d3 FEL |
2342 | KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler); |
2343 | ||
fa89a817 | 2344 | ++vcpu->stat.irq_injections; |
ad312c7c | 2345 | if (vcpu->arch.rmode.active) { |
9c8cba37 AK |
2346 | vmx->rmode.irq.pending = true; |
2347 | vmx->rmode.irq.vector = irq; | |
5fdbf976 | 2348 | vmx->rmode.irq.rip = kvm_rip_read(vcpu); |
9c5623e3 AK |
2349 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
2350 | irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK); | |
2351 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1); | |
5fdbf976 | 2352 | kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1); |
85f455f7 ED |
2353 | return; |
2354 | } | |
2355 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
2356 | irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
2357 | } | |
2358 | ||
f08864b4 SY |
2359 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
2360 | { | |
2361 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
2362 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
f08864b4 SY |
2363 | } |
2364 | ||
6aa8b732 AK |
2365 | static void kvm_do_inject_irq(struct kvm_vcpu *vcpu) |
2366 | { | |
ad312c7c ZX |
2367 | int word_index = __ffs(vcpu->arch.irq_summary); |
2368 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
6aa8b732 AK |
2369 | int irq = word_index * BITS_PER_LONG + bit_index; |
2370 | ||
ad312c7c ZX |
2371 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
2372 | if (!vcpu->arch.irq_pending[word_index]) | |
2373 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
ecfc79c7 | 2374 | kvm_queue_interrupt(vcpu, irq); |
6aa8b732 AK |
2375 | } |
2376 | ||
c1150d8c DL |
2377 | |
2378 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, | |
2379 | struct kvm_run *kvm_run) | |
6aa8b732 | 2380 | { |
c1150d8c DL |
2381 | u32 cpu_based_vm_exec_control; |
2382 | ||
ad312c7c | 2383 | vcpu->arch.interrupt_window_open = |
c1150d8c DL |
2384 | ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && |
2385 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0); | |
2386 | ||
ad312c7c | 2387 | if (vcpu->arch.interrupt_window_open && |
ecfc79c7 | 2388 | vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending) |
6aa8b732 | 2389 | kvm_do_inject_irq(vcpu); |
c1150d8c | 2390 | |
ecfc79c7 AK |
2391 | if (vcpu->arch.interrupt_window_open && vcpu->arch.interrupt.pending) |
2392 | vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr); | |
2393 | ||
c1150d8c | 2394 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); |
ad312c7c ZX |
2395 | if (!vcpu->arch.interrupt_window_open && |
2396 | (vcpu->arch.irq_summary || kvm_run->request_interrupt_window)) | |
6aa8b732 AK |
2397 | /* |
2398 | * Interrupts blocked. Wait for unblock. | |
2399 | */ | |
c1150d8c DL |
2400 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; |
2401 | else | |
2402 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
2403 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
6aa8b732 AK |
2404 | } |
2405 | ||
cbc94022 IE |
2406 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
2407 | { | |
2408 | int ret; | |
2409 | struct kvm_userspace_memory_region tss_mem = { | |
2410 | .slot = 8, | |
2411 | .guest_phys_addr = addr, | |
2412 | .memory_size = PAGE_SIZE * 3, | |
2413 | .flags = 0, | |
2414 | }; | |
2415 | ||
2416 | ret = kvm_set_memory_region(kvm, &tss_mem, 0); | |
2417 | if (ret) | |
2418 | return ret; | |
bfc6d222 | 2419 | kvm->arch.tss_addr = addr; |
cbc94022 IE |
2420 | return 0; |
2421 | } | |
2422 | ||
6aa8b732 AK |
2423 | static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu) |
2424 | { | |
2425 | struct kvm_guest_debug *dbg = &vcpu->guest_debug; | |
2426 | ||
2427 | set_debugreg(dbg->bp[0], 0); | |
2428 | set_debugreg(dbg->bp[1], 1); | |
2429 | set_debugreg(dbg->bp[2], 2); | |
2430 | set_debugreg(dbg->bp[3], 3); | |
2431 | ||
2432 | if (dbg->singlestep) { | |
2433 | unsigned long flags; | |
2434 | ||
2435 | flags = vmcs_readl(GUEST_RFLAGS); | |
2436 | flags |= X86_EFLAGS_TF | X86_EFLAGS_RF; | |
2437 | vmcs_writel(GUEST_RFLAGS, flags); | |
2438 | } | |
2439 | } | |
2440 | ||
2441 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
2442 | int vec, u32 err_code) | |
2443 | { | |
b3f37707 NK |
2444 | /* |
2445 | * Instruction with address size override prefix opcode 0x67 | |
2446 | * Cause the #SS fault with 0 error code in VM86 mode. | |
2447 | */ | |
2448 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) | |
3427318f | 2449 | if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE) |
6aa8b732 | 2450 | return 1; |
77ab6db0 JK |
2451 | /* |
2452 | * Forward all other exceptions that are valid in real mode. | |
2453 | * FIXME: Breaks guest debugging in real mode, needs to be fixed with | |
2454 | * the required debugging infrastructure rework. | |
2455 | */ | |
2456 | switch (vec) { | |
2457 | case DE_VECTOR: | |
2458 | case DB_VECTOR: | |
2459 | case BP_VECTOR: | |
2460 | case OF_VECTOR: | |
2461 | case BR_VECTOR: | |
2462 | case UD_VECTOR: | |
2463 | case DF_VECTOR: | |
2464 | case SS_VECTOR: | |
2465 | case GP_VECTOR: | |
2466 | case MF_VECTOR: | |
2467 | kvm_queue_exception(vcpu, vec); | |
2468 | return 1; | |
2469 | } | |
6aa8b732 AK |
2470 | return 0; |
2471 | } | |
2472 | ||
2473 | static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2474 | { | |
1155f76a | 2475 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 AK |
2476 | u32 intr_info, error_code; |
2477 | unsigned long cr2, rip; | |
2478 | u32 vect_info; | |
2479 | enum emulation_result er; | |
2480 | ||
1155f76a | 2481 | vect_info = vmx->idt_vectoring_info; |
6aa8b732 AK |
2482 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
2483 | ||
2484 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
d77c26fc | 2485 | !is_page_fault(intr_info)) |
6aa8b732 | 2486 | printk(KERN_ERR "%s: unexpected, vectoring info 0x%x " |
b8688d51 | 2487 | "intr info 0x%x\n", __func__, vect_info, intr_info); |
6aa8b732 | 2488 | |
85f455f7 | 2489 | if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) { |
6aa8b732 | 2490 | int irq = vect_info & VECTORING_INFO_VECTOR_MASK; |
ad312c7c ZX |
2491 | set_bit(irq, vcpu->arch.irq_pending); |
2492 | set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
2493 | } |
2494 | ||
1b6269db AK |
2495 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */ |
2496 | return 1; /* already handled by vmx_vcpu_run() */ | |
2ab455cc AL |
2497 | |
2498 | if (is_no_device(intr_info)) { | |
5fd86fcf | 2499 | vmx_fpu_activate(vcpu); |
2ab455cc AL |
2500 | return 1; |
2501 | } | |
2502 | ||
7aa81cc0 | 2503 | if (is_invalid_opcode(intr_info)) { |
571008da | 2504 | er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 2505 | if (er != EMULATE_DONE) |
7ee5d940 | 2506 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
2507 | return 1; |
2508 | } | |
2509 | ||
6aa8b732 | 2510 | error_code = 0; |
5fdbf976 | 2511 | rip = kvm_rip_read(vcpu); |
2e11384c | 2512 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 AK |
2513 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
2514 | if (is_page_fault(intr_info)) { | |
1439442c SY |
2515 | /* EPT won't cause page fault directly */ |
2516 | if (vm_need_ept()) | |
2517 | BUG(); | |
6aa8b732 | 2518 | cr2 = vmcs_readl(EXIT_QUALIFICATION); |
2714d1d3 FEL |
2519 | KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2, |
2520 | (u32)((u64)cr2 >> 32), handler); | |
f7d9238f | 2521 | if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending) |
577bdc49 | 2522 | kvm_mmu_unprotect_page_virt(vcpu, cr2); |
3067714c | 2523 | return kvm_mmu_page_fault(vcpu, cr2, error_code); |
6aa8b732 AK |
2524 | } |
2525 | ||
ad312c7c | 2526 | if (vcpu->arch.rmode.active && |
6aa8b732 | 2527 | handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK, |
72d6e5a0 | 2528 | error_code)) { |
ad312c7c ZX |
2529 | if (vcpu->arch.halt_request) { |
2530 | vcpu->arch.halt_request = 0; | |
72d6e5a0 AK |
2531 | return kvm_emulate_halt(vcpu); |
2532 | } | |
6aa8b732 | 2533 | return 1; |
72d6e5a0 | 2534 | } |
6aa8b732 | 2535 | |
d77c26fc MD |
2536 | if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == |
2537 | (INTR_TYPE_EXCEPTION | 1)) { | |
6aa8b732 AK |
2538 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
2539 | return 0; | |
2540 | } | |
2541 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; | |
2542 | kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK; | |
2543 | kvm_run->ex.error_code = error_code; | |
2544 | return 0; | |
2545 | } | |
2546 | ||
2547 | static int handle_external_interrupt(struct kvm_vcpu *vcpu, | |
2548 | struct kvm_run *kvm_run) | |
2549 | { | |
1165f5fe | 2550 | ++vcpu->stat.irq_exits; |
2714d1d3 | 2551 | KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler); |
6aa8b732 AK |
2552 | return 1; |
2553 | } | |
2554 | ||
988ad74f AK |
2555 | static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2556 | { | |
2557 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
2558 | return 0; | |
2559 | } | |
6aa8b732 | 2560 | |
6aa8b732 AK |
2561 | static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2562 | { | |
bfdaab09 | 2563 | unsigned long exit_qualification; |
039576c0 AK |
2564 | int size, down, in, string, rep; |
2565 | unsigned port; | |
6aa8b732 | 2566 | |
1165f5fe | 2567 | ++vcpu->stat.io_exits; |
bfdaab09 | 2568 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 2569 | string = (exit_qualification & 16) != 0; |
e70669ab LV |
2570 | |
2571 | if (string) { | |
3427318f LV |
2572 | if (emulate_instruction(vcpu, |
2573 | kvm_run, 0, 0, 0) == EMULATE_DO_MMIO) | |
e70669ab LV |
2574 | return 0; |
2575 | return 1; | |
2576 | } | |
2577 | ||
2578 | size = (exit_qualification & 7) + 1; | |
2579 | in = (exit_qualification & 8) != 0; | |
039576c0 | 2580 | down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0; |
039576c0 AK |
2581 | rep = (exit_qualification & 32) != 0; |
2582 | port = exit_qualification >> 16; | |
e70669ab | 2583 | |
3090dd73 | 2584 | return kvm_emulate_pio(vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
2585 | } |
2586 | ||
102d8325 IM |
2587 | static void |
2588 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
2589 | { | |
2590 | /* | |
2591 | * Patch in the VMCALL instruction: | |
2592 | */ | |
2593 | hypercall[0] = 0x0f; | |
2594 | hypercall[1] = 0x01; | |
2595 | hypercall[2] = 0xc1; | |
102d8325 IM |
2596 | } |
2597 | ||
6aa8b732 AK |
2598 | static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2599 | { | |
bfdaab09 | 2600 | unsigned long exit_qualification; |
6aa8b732 AK |
2601 | int cr; |
2602 | int reg; | |
2603 | ||
bfdaab09 | 2604 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
2605 | cr = exit_qualification & 15; |
2606 | reg = (exit_qualification >> 8) & 15; | |
2607 | switch ((exit_qualification >> 4) & 3) { | |
2608 | case 0: /* mov to cr */ | |
5fdbf976 MT |
2609 | KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, |
2610 | (u32)kvm_register_read(vcpu, reg), | |
2611 | (u32)((u64)kvm_register_read(vcpu, reg) >> 32), | |
2612 | handler); | |
6aa8b732 AK |
2613 | switch (cr) { |
2614 | case 0: | |
5fdbf976 | 2615 | kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg)); |
6aa8b732 AK |
2616 | skip_emulated_instruction(vcpu); |
2617 | return 1; | |
2618 | case 3: | |
5fdbf976 | 2619 | kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg)); |
6aa8b732 AK |
2620 | skip_emulated_instruction(vcpu); |
2621 | return 1; | |
2622 | case 4: | |
5fdbf976 | 2623 | kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg)); |
6aa8b732 AK |
2624 | skip_emulated_instruction(vcpu); |
2625 | return 1; | |
2626 | case 8: | |
5fdbf976 | 2627 | kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg)); |
6aa8b732 | 2628 | skip_emulated_instruction(vcpu); |
e5314067 AK |
2629 | if (irqchip_in_kernel(vcpu->kvm)) |
2630 | return 1; | |
253abdee YS |
2631 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2632 | return 0; | |
6aa8b732 AK |
2633 | }; |
2634 | break; | |
25c4c276 | 2635 | case 2: /* clts */ |
5fd86fcf | 2636 | vmx_fpu_deactivate(vcpu); |
ad312c7c ZX |
2637 | vcpu->arch.cr0 &= ~X86_CR0_TS; |
2638 | vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0); | |
5fd86fcf | 2639 | vmx_fpu_activate(vcpu); |
2714d1d3 | 2640 | KVMTRACE_0D(CLTS, vcpu, handler); |
25c4c276 AL |
2641 | skip_emulated_instruction(vcpu); |
2642 | return 1; | |
6aa8b732 AK |
2643 | case 1: /*mov from cr*/ |
2644 | switch (cr) { | |
2645 | case 3: | |
5fdbf976 | 2646 | kvm_register_write(vcpu, reg, vcpu->arch.cr3); |
2714d1d3 | 2647 | KVMTRACE_3D(CR_READ, vcpu, (u32)cr, |
5fdbf976 MT |
2648 | (u32)kvm_register_read(vcpu, reg), |
2649 | (u32)((u64)kvm_register_read(vcpu, reg) >> 32), | |
2714d1d3 | 2650 | handler); |
6aa8b732 AK |
2651 | skip_emulated_instruction(vcpu); |
2652 | return 1; | |
2653 | case 8: | |
5fdbf976 | 2654 | kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu)); |
2714d1d3 | 2655 | KVMTRACE_2D(CR_READ, vcpu, (u32)cr, |
5fdbf976 | 2656 | (u32)kvm_register_read(vcpu, reg), handler); |
6aa8b732 AK |
2657 | skip_emulated_instruction(vcpu); |
2658 | return 1; | |
2659 | } | |
2660 | break; | |
2661 | case 3: /* lmsw */ | |
2d3ad1f4 | 2662 | kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f); |
6aa8b732 AK |
2663 | |
2664 | skip_emulated_instruction(vcpu); | |
2665 | return 1; | |
2666 | default: | |
2667 | break; | |
2668 | } | |
2669 | kvm_run->exit_reason = 0; | |
f0242478 | 2670 | pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
2671 | (int)(exit_qualification >> 4) & 3, cr); |
2672 | return 0; | |
2673 | } | |
2674 | ||
2675 | static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2676 | { | |
bfdaab09 | 2677 | unsigned long exit_qualification; |
6aa8b732 AK |
2678 | unsigned long val; |
2679 | int dr, reg; | |
2680 | ||
2681 | /* | |
2682 | * FIXME: this code assumes the host is debugging the guest. | |
2683 | * need to deal with guest debugging itself too. | |
2684 | */ | |
bfdaab09 | 2685 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
2686 | dr = exit_qualification & 7; |
2687 | reg = (exit_qualification >> 8) & 15; | |
6aa8b732 AK |
2688 | if (exit_qualification & 16) { |
2689 | /* mov from dr */ | |
2690 | switch (dr) { | |
2691 | case 6: | |
2692 | val = 0xffff0ff0; | |
2693 | break; | |
2694 | case 7: | |
2695 | val = 0x400; | |
2696 | break; | |
2697 | default: | |
2698 | val = 0; | |
2699 | } | |
5fdbf976 | 2700 | kvm_register_write(vcpu, reg, val); |
2714d1d3 | 2701 | KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler); |
6aa8b732 AK |
2702 | } else { |
2703 | /* mov to dr */ | |
2704 | } | |
6aa8b732 AK |
2705 | skip_emulated_instruction(vcpu); |
2706 | return 1; | |
2707 | } | |
2708 | ||
2709 | static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2710 | { | |
06465c5a AK |
2711 | kvm_emulate_cpuid(vcpu); |
2712 | return 1; | |
6aa8b732 AK |
2713 | } |
2714 | ||
2715 | static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2716 | { | |
ad312c7c | 2717 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
2718 | u64 data; |
2719 | ||
2720 | if (vmx_get_msr(vcpu, ecx, &data)) { | |
c1a5d4f9 | 2721 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
2722 | return 1; |
2723 | } | |
2724 | ||
2714d1d3 FEL |
2725 | KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32), |
2726 | handler); | |
2727 | ||
6aa8b732 | 2728 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
ad312c7c ZX |
2729 | vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u; |
2730 | vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u; | |
6aa8b732 AK |
2731 | skip_emulated_instruction(vcpu); |
2732 | return 1; | |
2733 | } | |
2734 | ||
2735 | static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2736 | { | |
ad312c7c ZX |
2737 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
2738 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
2739 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 | 2740 | |
2714d1d3 FEL |
2741 | KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32), |
2742 | handler); | |
2743 | ||
6aa8b732 | 2744 | if (vmx_set_msr(vcpu, ecx, data) != 0) { |
c1a5d4f9 | 2745 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
2746 | return 1; |
2747 | } | |
2748 | ||
2749 | skip_emulated_instruction(vcpu); | |
2750 | return 1; | |
2751 | } | |
2752 | ||
6e5d865c YS |
2753 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu, |
2754 | struct kvm_run *kvm_run) | |
2755 | { | |
2756 | return 1; | |
2757 | } | |
2758 | ||
6aa8b732 AK |
2759 | static int handle_interrupt_window(struct kvm_vcpu *vcpu, |
2760 | struct kvm_run *kvm_run) | |
2761 | { | |
85f455f7 ED |
2762 | u32 cpu_based_vm_exec_control; |
2763 | ||
2764 | /* clear pending irq */ | |
2765 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2766 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
2767 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2714d1d3 FEL |
2768 | |
2769 | KVMTRACE_0D(PEND_INTR, vcpu, handler); | |
2770 | ||
c1150d8c DL |
2771 | /* |
2772 | * If the user space waits to inject interrupts, exit as soon as | |
2773 | * possible | |
2774 | */ | |
2775 | if (kvm_run->request_interrupt_window && | |
ad312c7c | 2776 | !vcpu->arch.irq_summary) { |
c1150d8c | 2777 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1165f5fe | 2778 | ++vcpu->stat.irq_window_exits; |
c1150d8c DL |
2779 | return 0; |
2780 | } | |
6aa8b732 AK |
2781 | return 1; |
2782 | } | |
2783 | ||
2784 | static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2785 | { | |
2786 | skip_emulated_instruction(vcpu); | |
d3bef15f | 2787 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
2788 | } |
2789 | ||
c21415e8 IM |
2790 | static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2791 | { | |
510043da | 2792 | skip_emulated_instruction(vcpu); |
7aa81cc0 AL |
2793 | kvm_emulate_hypercall(vcpu); |
2794 | return 1; | |
c21415e8 IM |
2795 | } |
2796 | ||
a7052897 MT |
2797 | static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2798 | { | |
2799 | u64 exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
2800 | ||
2801 | kvm_mmu_invlpg(vcpu, exit_qualification); | |
2802 | skip_emulated_instruction(vcpu); | |
2803 | return 1; | |
2804 | } | |
2805 | ||
e5edaa01 ED |
2806 | static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2807 | { | |
2808 | skip_emulated_instruction(vcpu); | |
2809 | /* TODO: Add support for VT-d/pass-through device */ | |
2810 | return 1; | |
2811 | } | |
2812 | ||
f78e0e2e SY |
2813 | static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2814 | { | |
2815 | u64 exit_qualification; | |
2816 | enum emulation_result er; | |
2817 | unsigned long offset; | |
2818 | ||
2819 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
2820 | offset = exit_qualification & 0xffful; | |
2821 | ||
2822 | er = emulate_instruction(vcpu, kvm_run, 0, 0, 0); | |
2823 | ||
2824 | if (er != EMULATE_DONE) { | |
2825 | printk(KERN_ERR | |
2826 | "Fail to handle apic access vmexit! Offset is 0x%lx\n", | |
2827 | offset); | |
2828 | return -ENOTSUPP; | |
2829 | } | |
2830 | return 1; | |
2831 | } | |
2832 | ||
37817f29 IE |
2833 | static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2834 | { | |
2835 | unsigned long exit_qualification; | |
2836 | u16 tss_selector; | |
2837 | int reason; | |
2838 | ||
2839 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
2840 | ||
2841 | reason = (u32)exit_qualification >> 30; | |
2842 | tss_selector = exit_qualification; | |
2843 | ||
2844 | return kvm_task_switch(vcpu, tss_selector, reason); | |
2845 | } | |
2846 | ||
1439442c SY |
2847 | static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2848 | { | |
2849 | u64 exit_qualification; | |
2850 | enum emulation_result er; | |
2851 | gpa_t gpa; | |
2852 | unsigned long hva; | |
2853 | int gla_validity; | |
2854 | int r; | |
2855 | ||
2856 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
2857 | ||
2858 | if (exit_qualification & (1 << 6)) { | |
2859 | printk(KERN_ERR "EPT: GPA exceeds GAW!\n"); | |
2860 | return -ENOTSUPP; | |
2861 | } | |
2862 | ||
2863 | gla_validity = (exit_qualification >> 7) & 0x3; | |
2864 | if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) { | |
2865 | printk(KERN_ERR "EPT: Handling EPT violation failed!\n"); | |
2866 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | |
2867 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | |
2868 | (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS)); | |
2869 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", | |
2870 | (long unsigned int)exit_qualification); | |
2871 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
2872 | kvm_run->hw.hardware_exit_reason = 0; | |
2873 | return -ENOTSUPP; | |
2874 | } | |
2875 | ||
2876 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
2877 | hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT); | |
2878 | if (!kvm_is_error_hva(hva)) { | |
2879 | r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0); | |
2880 | if (r < 0) { | |
2881 | printk(KERN_ERR "EPT: Not enough memory!\n"); | |
2882 | return -ENOMEM; | |
2883 | } | |
2884 | return 1; | |
2885 | } else { | |
2886 | /* must be MMIO */ | |
2887 | er = emulate_instruction(vcpu, kvm_run, 0, 0, 0); | |
2888 | ||
2889 | if (er == EMULATE_FAIL) { | |
2890 | printk(KERN_ERR | |
2891 | "EPT: Fail to handle EPT violation vmexit!er is %d\n", | |
2892 | er); | |
2893 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | |
2894 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | |
2895 | (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS)); | |
2896 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", | |
2897 | (long unsigned int)exit_qualification); | |
2898 | return -ENOTSUPP; | |
2899 | } else if (er == EMULATE_DO_MMIO) | |
2900 | return 0; | |
2901 | } | |
2902 | return 1; | |
2903 | } | |
2904 | ||
f08864b4 SY |
2905 | static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2906 | { | |
2907 | u32 cpu_based_vm_exec_control; | |
2908 | ||
2909 | /* clear pending NMI */ | |
2910 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2911 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
2912 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2913 | ++vcpu->stat.nmi_window_exits; | |
2914 | ||
2915 | return 1; | |
2916 | } | |
2917 | ||
ea953ef0 MG |
2918 | static void handle_invalid_guest_state(struct kvm_vcpu *vcpu, |
2919 | struct kvm_run *kvm_run) | |
2920 | { | |
2921 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
2922 | int err; | |
2923 | ||
2924 | preempt_enable(); | |
2925 | local_irq_enable(); | |
2926 | ||
2927 | while (!guest_state_valid(vcpu)) { | |
2928 | err = emulate_instruction(vcpu, kvm_run, 0, 0, 0); | |
2929 | ||
2930 | switch (err) { | |
2931 | case EMULATE_DONE: | |
2932 | break; | |
2933 | case EMULATE_DO_MMIO: | |
2934 | kvm_report_emulation_failure(vcpu, "mmio"); | |
2935 | /* TODO: Handle MMIO */ | |
2936 | return; | |
2937 | default: | |
2938 | kvm_report_emulation_failure(vcpu, "emulation failure"); | |
2939 | return; | |
2940 | } | |
2941 | ||
2942 | if (signal_pending(current)) | |
2943 | break; | |
2944 | if (need_resched()) | |
2945 | schedule(); | |
2946 | } | |
2947 | ||
2948 | local_irq_disable(); | |
2949 | preempt_disable(); | |
2950 | ||
2951 | /* Guest state should be valid now, no more emulation should be needed */ | |
2952 | vmx->emulation_required = 0; | |
2953 | } | |
2954 | ||
6aa8b732 AK |
2955 | /* |
2956 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
2957 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
2958 | * to be done to userspace and return 0. | |
2959 | */ | |
2960 | static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu, | |
2961 | struct kvm_run *kvm_run) = { | |
2962 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, | |
2963 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 2964 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
f08864b4 | 2965 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, |
6aa8b732 | 2966 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
2967 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
2968 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
2969 | [EXIT_REASON_CPUID] = handle_cpuid, | |
2970 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
2971 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
2972 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
2973 | [EXIT_REASON_HLT] = handle_halt, | |
a7052897 | 2974 | [EXIT_REASON_INVLPG] = handle_invlpg, |
c21415e8 | 2975 | [EXIT_REASON_VMCALL] = handle_vmcall, |
f78e0e2e SY |
2976 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
2977 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
e5edaa01 | 2978 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
37817f29 | 2979 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
1439442c | 2980 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
6aa8b732 AK |
2981 | }; |
2982 | ||
2983 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 2984 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 AK |
2985 | |
2986 | /* | |
2987 | * The guest has exited. See if we can fix it or if we need userspace | |
2988 | * assistance. | |
2989 | */ | |
2990 | static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) | |
2991 | { | |
6aa8b732 | 2992 | u32 exit_reason = vmcs_read32(VM_EXIT_REASON); |
29bd8a78 | 2993 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1155f76a | 2994 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 2995 | |
5fdbf976 MT |
2996 | KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu), |
2997 | (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit); | |
2714d1d3 | 2998 | |
1439442c SY |
2999 | /* Access CR3 don't cause VMExit in paging mode, so we need |
3000 | * to sync with guest real CR3. */ | |
3001 | if (vm_need_ept() && is_paging(vcpu)) { | |
3002 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); | |
3003 | ept_load_pdptrs(vcpu); | |
3004 | } | |
3005 | ||
29bd8a78 AK |
3006 | if (unlikely(vmx->fail)) { |
3007 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
3008 | kvm_run->fail_entry.hardware_entry_failure_reason | |
3009 | = vmcs_read32(VM_INSTRUCTION_ERROR); | |
3010 | return 0; | |
3011 | } | |
6aa8b732 | 3012 | |
d77c26fc | 3013 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c SY |
3014 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
3015 | exit_reason != EXIT_REASON_EPT_VIOLATION)) | |
6aa8b732 | 3016 | printk(KERN_WARNING "%s: unexpected, valid vectoring info and " |
b8688d51 | 3017 | "exit reason is 0x%x\n", __func__, exit_reason); |
6aa8b732 AK |
3018 | if (exit_reason < kvm_vmx_max_exit_handlers |
3019 | && kvm_vmx_exit_handlers[exit_reason]) | |
3020 | return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run); | |
3021 | else { | |
3022 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
3023 | kvm_run->hw.hardware_exit_reason = exit_reason; | |
3024 | } | |
3025 | return 0; | |
3026 | } | |
3027 | ||
6e5d865c YS |
3028 | static void update_tpr_threshold(struct kvm_vcpu *vcpu) |
3029 | { | |
3030 | int max_irr, tpr; | |
3031 | ||
3032 | if (!vm_need_tpr_shadow(vcpu->kvm)) | |
3033 | return; | |
3034 | ||
3035 | if (!kvm_lapic_enabled(vcpu) || | |
3036 | ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) { | |
3037 | vmcs_write32(TPR_THRESHOLD, 0); | |
3038 | return; | |
3039 | } | |
3040 | ||
3041 | tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4; | |
3042 | vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4); | |
3043 | } | |
3044 | ||
85f455f7 ED |
3045 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
3046 | { | |
3047 | u32 cpu_based_vm_exec_control; | |
3048 | ||
3049 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
3050 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; | |
3051 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
3052 | } | |
3053 | ||
f08864b4 SY |
3054 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
3055 | { | |
3056 | u32 cpu_based_vm_exec_control; | |
3057 | ||
3058 | if (!cpu_has_virtual_nmis()) | |
3059 | return; | |
3060 | ||
3061 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
3062 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING; | |
3063 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
3064 | } | |
3065 | ||
3066 | static int vmx_nmi_enabled(struct kvm_vcpu *vcpu) | |
3067 | { | |
3068 | u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
3069 | return !(guest_intr & (GUEST_INTR_STATE_NMI | | |
3070 | GUEST_INTR_STATE_MOV_SS | | |
3071 | GUEST_INTR_STATE_STI)); | |
3072 | } | |
3073 | ||
3074 | static int vmx_irq_enabled(struct kvm_vcpu *vcpu) | |
3075 | { | |
3076 | u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
3077 | return (!(guest_intr & (GUEST_INTR_STATE_MOV_SS | | |
3078 | GUEST_INTR_STATE_STI)) && | |
3079 | (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF)); | |
3080 | } | |
3081 | ||
3082 | static void enable_intr_window(struct kvm_vcpu *vcpu) | |
3083 | { | |
3084 | if (vcpu->arch.nmi_pending) | |
3085 | enable_nmi_window(vcpu); | |
3086 | else if (kvm_cpu_has_interrupt(vcpu)) | |
3087 | enable_irq_window(vcpu); | |
3088 | } | |
3089 | ||
cf393f75 AK |
3090 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
3091 | { | |
3092 | u32 exit_intr_info; | |
668f612f | 3093 | u32 idt_vectoring_info; |
cf393f75 AK |
3094 | bool unblock_nmi; |
3095 | u8 vector; | |
668f612f AK |
3096 | int type; |
3097 | bool idtv_info_valid; | |
35920a35 | 3098 | u32 error; |
cf393f75 AK |
3099 | |
3100 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
3101 | if (cpu_has_virtual_nmis()) { | |
3102 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; | |
3103 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
3104 | /* | |
3105 | * SDM 3: 25.7.1.2 | |
3106 | * Re-set bit "block by NMI" before VM entry if vmexit caused by | |
3107 | * a guest IRET fault. | |
3108 | */ | |
3109 | if (unblock_nmi && vector != DF_VECTOR) | |
3110 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
3111 | GUEST_INTR_STATE_NMI); | |
3112 | } | |
668f612f AK |
3113 | |
3114 | idt_vectoring_info = vmx->idt_vectoring_info; | |
3115 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
3116 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; | |
3117 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | |
3118 | if (vmx->vcpu.arch.nmi_injected) { | |
3119 | /* | |
3120 | * SDM 3: 25.7.1.2 | |
3121 | * Clear bit "block by NMI" before VM entry if a NMI delivery | |
3122 | * faulted. | |
3123 | */ | |
3124 | if (idtv_info_valid && type == INTR_TYPE_NMI_INTR) | |
3125 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
3126 | GUEST_INTR_STATE_NMI); | |
3127 | else | |
3128 | vmx->vcpu.arch.nmi_injected = false; | |
3129 | } | |
35920a35 AK |
3130 | kvm_clear_exception_queue(&vmx->vcpu); |
3131 | if (idtv_info_valid && type == INTR_TYPE_EXCEPTION) { | |
3132 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { | |
3133 | error = vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
3134 | kvm_queue_exception_e(&vmx->vcpu, vector, error); | |
3135 | } else | |
3136 | kvm_queue_exception(&vmx->vcpu, vector); | |
3137 | vmx->idt_vectoring_info = 0; | |
3138 | } | |
f7d9238f AK |
3139 | kvm_clear_interrupt_queue(&vmx->vcpu); |
3140 | if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) { | |
3141 | kvm_queue_interrupt(&vmx->vcpu, vector); | |
3142 | vmx->idt_vectoring_info = 0; | |
3143 | } | |
cf393f75 AK |
3144 | } |
3145 | ||
85f455f7 ED |
3146 | static void vmx_intr_assist(struct kvm_vcpu *vcpu) |
3147 | { | |
6e5d865c YS |
3148 | update_tpr_threshold(vcpu); |
3149 | ||
f08864b4 | 3150 | if (cpu_has_virtual_nmis()) { |
668f612f AK |
3151 | if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) { |
3152 | if (vmx_nmi_enabled(vcpu)) { | |
3153 | vcpu->arch.nmi_pending = false; | |
3154 | vcpu->arch.nmi_injected = true; | |
3155 | } else { | |
3156 | enable_intr_window(vcpu); | |
3157 | return; | |
3158 | } | |
3159 | } | |
3160 | if (vcpu->arch.nmi_injected) { | |
3161 | vmx_inject_nmi(vcpu); | |
f08864b4 SY |
3162 | enable_intr_window(vcpu); |
3163 | return; | |
3164 | } | |
f08864b4 | 3165 | } |
f7d9238f AK |
3166 | if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) { |
3167 | if (vmx_irq_enabled(vcpu)) | |
3168 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu)); | |
3169 | else | |
3170 | enable_irq_window(vcpu); | |
3171 | } | |
3172 | if (vcpu->arch.interrupt.pending) { | |
3173 | vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr); | |
3174 | kvm_timer_intr_post(vcpu, vcpu->arch.interrupt.nr); | |
3175 | } | |
85f455f7 ED |
3176 | } |
3177 | ||
9c8cba37 AK |
3178 | /* |
3179 | * Failure to inject an interrupt should give us the information | |
3180 | * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs | |
3181 | * when fetching the interrupt redirection bitmap in the real-mode | |
3182 | * tss, this doesn't happen. So we do it ourselves. | |
3183 | */ | |
3184 | static void fixup_rmode_irq(struct vcpu_vmx *vmx) | |
3185 | { | |
3186 | vmx->rmode.irq.pending = 0; | |
5fdbf976 | 3187 | if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip) |
9c8cba37 | 3188 | return; |
5fdbf976 | 3189 | kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip); |
9c8cba37 AK |
3190 | if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) { |
3191 | vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK; | |
3192 | vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR; | |
3193 | return; | |
3194 | } | |
3195 | vmx->idt_vectoring_info = | |
3196 | VECTORING_INFO_VALID_MASK | |
3197 | | INTR_TYPE_EXT_INTR | |
3198 | | vmx->rmode.irq.vector; | |
3199 | } | |
3200 | ||
c801949d AK |
3201 | #ifdef CONFIG_X86_64 |
3202 | #define R "r" | |
3203 | #define Q "q" | |
3204 | #else | |
3205 | #define R "e" | |
3206 | #define Q "l" | |
3207 | #endif | |
3208 | ||
04d2cc77 | 3209 | static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
6aa8b732 | 3210 | { |
a2fa3e9f | 3211 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1b6269db | 3212 | u32 intr_info; |
e6adf283 | 3213 | |
a89a8fb9 MG |
3214 | /* Handle invalid guest state instead of entering VMX */ |
3215 | if (vmx->emulation_required && emulate_invalid_guest_state) { | |
3216 | handle_invalid_guest_state(vcpu, kvm_run); | |
3217 | return; | |
3218 | } | |
3219 | ||
5fdbf976 MT |
3220 | if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) |
3221 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); | |
3222 | if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
3223 | vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); | |
3224 | ||
e6adf283 AK |
3225 | /* |
3226 | * Loading guest fpu may have cleared host cr0.ts | |
3227 | */ | |
3228 | vmcs_writel(HOST_CR0, read_cr0()); | |
3229 | ||
d77c26fc | 3230 | asm( |
6aa8b732 | 3231 | /* Store host registers */ |
c801949d AK |
3232 | "push %%"R"dx; push %%"R"bp;" |
3233 | "push %%"R"cx \n\t" | |
313dbd49 AK |
3234 | "cmp %%"R"sp, %c[host_rsp](%0) \n\t" |
3235 | "je 1f \n\t" | |
3236 | "mov %%"R"sp, %c[host_rsp](%0) \n\t" | |
4ecac3fd | 3237 | __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t" |
313dbd49 | 3238 | "1: \n\t" |
6aa8b732 | 3239 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 3240 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 3241 | /* Load guest registers. Don't clobber flags. */ |
c801949d AK |
3242 | "mov %c[cr2](%0), %%"R"ax \n\t" |
3243 | "mov %%"R"ax, %%cr2 \n\t" | |
3244 | "mov %c[rax](%0), %%"R"ax \n\t" | |
3245 | "mov %c[rbx](%0), %%"R"bx \n\t" | |
3246 | "mov %c[rdx](%0), %%"R"dx \n\t" | |
3247 | "mov %c[rsi](%0), %%"R"si \n\t" | |
3248 | "mov %c[rdi](%0), %%"R"di \n\t" | |
3249 | "mov %c[rbp](%0), %%"R"bp \n\t" | |
05b3e0c2 | 3250 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
3251 | "mov %c[r8](%0), %%r8 \n\t" |
3252 | "mov %c[r9](%0), %%r9 \n\t" | |
3253 | "mov %c[r10](%0), %%r10 \n\t" | |
3254 | "mov %c[r11](%0), %%r11 \n\t" | |
3255 | "mov %c[r12](%0), %%r12 \n\t" | |
3256 | "mov %c[r13](%0), %%r13 \n\t" | |
3257 | "mov %c[r14](%0), %%r14 \n\t" | |
3258 | "mov %c[r15](%0), %%r15 \n\t" | |
6aa8b732 | 3259 | #endif |
c801949d AK |
3260 | "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */ |
3261 | ||
6aa8b732 | 3262 | /* Enter guest mode */ |
cd2276a7 | 3263 | "jne .Llaunched \n\t" |
4ecac3fd | 3264 | __ex(ASM_VMX_VMLAUNCH) "\n\t" |
cd2276a7 | 3265 | "jmp .Lkvm_vmx_return \n\t" |
4ecac3fd | 3266 | ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t" |
cd2276a7 | 3267 | ".Lkvm_vmx_return: " |
6aa8b732 | 3268 | /* Save guest registers, load host registers, keep flags */ |
c801949d AK |
3269 | "xchg %0, (%%"R"sp) \n\t" |
3270 | "mov %%"R"ax, %c[rax](%0) \n\t" | |
3271 | "mov %%"R"bx, %c[rbx](%0) \n\t" | |
3272 | "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t" | |
3273 | "mov %%"R"dx, %c[rdx](%0) \n\t" | |
3274 | "mov %%"R"si, %c[rsi](%0) \n\t" | |
3275 | "mov %%"R"di, %c[rdi](%0) \n\t" | |
3276 | "mov %%"R"bp, %c[rbp](%0) \n\t" | |
05b3e0c2 | 3277 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
3278 | "mov %%r8, %c[r8](%0) \n\t" |
3279 | "mov %%r9, %c[r9](%0) \n\t" | |
3280 | "mov %%r10, %c[r10](%0) \n\t" | |
3281 | "mov %%r11, %c[r11](%0) \n\t" | |
3282 | "mov %%r12, %c[r12](%0) \n\t" | |
3283 | "mov %%r13, %c[r13](%0) \n\t" | |
3284 | "mov %%r14, %c[r14](%0) \n\t" | |
3285 | "mov %%r15, %c[r15](%0) \n\t" | |
6aa8b732 | 3286 | #endif |
c801949d AK |
3287 | "mov %%cr2, %%"R"ax \n\t" |
3288 | "mov %%"R"ax, %c[cr2](%0) \n\t" | |
3289 | ||
3290 | "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t" | |
e08aa78a AK |
3291 | "setbe %c[fail](%0) \n\t" |
3292 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), | |
3293 | [launched]"i"(offsetof(struct vcpu_vmx, launched)), | |
3294 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), | |
313dbd49 | 3295 | [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)), |
ad312c7c ZX |
3296 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
3297 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
3298 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
3299 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
3300 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
3301 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
3302 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 3303 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
3304 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
3305 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
3306 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
3307 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
3308 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
3309 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
3310 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
3311 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 3312 | #endif |
ad312c7c | 3313 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)) |
c2036300 | 3314 | : "cc", "memory" |
c801949d | 3315 | , R"bx", R"di", R"si" |
c2036300 | 3316 | #ifdef CONFIG_X86_64 |
c2036300 LV |
3317 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
3318 | #endif | |
3319 | ); | |
6aa8b732 | 3320 | |
5fdbf976 MT |
3321 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)); |
3322 | vcpu->arch.regs_dirty = 0; | |
3323 | ||
1155f76a | 3324 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); |
9c8cba37 AK |
3325 | if (vmx->rmode.irq.pending) |
3326 | fixup_rmode_irq(vmx); | |
1155f76a | 3327 | |
ad312c7c | 3328 | vcpu->arch.interrupt_window_open = |
f08864b4 SY |
3329 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
3330 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)) == 0; | |
6aa8b732 | 3331 | |
d77c26fc | 3332 | asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS)); |
15ad7146 | 3333 | vmx->launched = 1; |
1b6269db AK |
3334 | |
3335 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
3336 | ||
3337 | /* We need to handle NMIs before interrupts are enabled */ | |
f08864b4 SY |
3338 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200 && |
3339 | (intr_info & INTR_INFO_VALID_MASK)) { | |
2714d1d3 | 3340 | KVMTRACE_0D(NMI, vcpu, handler); |
1b6269db | 3341 | asm("int $2"); |
2714d1d3 | 3342 | } |
cf393f75 AK |
3343 | |
3344 | vmx_complete_interrupts(vmx); | |
6aa8b732 AK |
3345 | } |
3346 | ||
c801949d AK |
3347 | #undef R |
3348 | #undef Q | |
3349 | ||
6aa8b732 AK |
3350 | static void vmx_free_vmcs(struct kvm_vcpu *vcpu) |
3351 | { | |
a2fa3e9f GH |
3352 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3353 | ||
3354 | if (vmx->vmcs) { | |
543e4243 | 3355 | vcpu_clear(vmx); |
a2fa3e9f GH |
3356 | free_vmcs(vmx->vmcs); |
3357 | vmx->vmcs = NULL; | |
6aa8b732 AK |
3358 | } |
3359 | } | |
3360 | ||
3361 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) | |
3362 | { | |
fb3f0f51 RR |
3363 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3364 | ||
2384d2b3 SY |
3365 | spin_lock(&vmx_vpid_lock); |
3366 | if (vmx->vpid != 0) | |
3367 | __clear_bit(vmx->vpid, vmx_vpid_bitmap); | |
3368 | spin_unlock(&vmx_vpid_lock); | |
6aa8b732 | 3369 | vmx_free_vmcs(vcpu); |
fb3f0f51 RR |
3370 | kfree(vmx->host_msrs); |
3371 | kfree(vmx->guest_msrs); | |
3372 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 3373 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
3374 | } |
3375 | ||
fb3f0f51 | 3376 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 3377 | { |
fb3f0f51 | 3378 | int err; |
c16f862d | 3379 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
15ad7146 | 3380 | int cpu; |
6aa8b732 | 3381 | |
a2fa3e9f | 3382 | if (!vmx) |
fb3f0f51 RR |
3383 | return ERR_PTR(-ENOMEM); |
3384 | ||
2384d2b3 SY |
3385 | allocate_vpid(vmx); |
3386 | ||
fb3f0f51 RR |
3387 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
3388 | if (err) | |
3389 | goto free_vcpu; | |
965b58a5 | 3390 | |
a2fa3e9f | 3391 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
fb3f0f51 RR |
3392 | if (!vmx->guest_msrs) { |
3393 | err = -ENOMEM; | |
3394 | goto uninit_vcpu; | |
3395 | } | |
965b58a5 | 3396 | |
a2fa3e9f GH |
3397 | vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
3398 | if (!vmx->host_msrs) | |
fb3f0f51 | 3399 | goto free_guest_msrs; |
965b58a5 | 3400 | |
a2fa3e9f GH |
3401 | vmx->vmcs = alloc_vmcs(); |
3402 | if (!vmx->vmcs) | |
fb3f0f51 | 3403 | goto free_msrs; |
a2fa3e9f GH |
3404 | |
3405 | vmcs_clear(vmx->vmcs); | |
3406 | ||
15ad7146 AK |
3407 | cpu = get_cpu(); |
3408 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
8b9cf98c | 3409 | err = vmx_vcpu_setup(vmx); |
fb3f0f51 | 3410 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 3411 | put_cpu(); |
fb3f0f51 RR |
3412 | if (err) |
3413 | goto free_vmcs; | |
5e4a0b3c MT |
3414 | if (vm_need_virtualize_apic_accesses(kvm)) |
3415 | if (alloc_apic_access_page(kvm) != 0) | |
3416 | goto free_vmcs; | |
fb3f0f51 | 3417 | |
b7ebfb05 SY |
3418 | if (vm_need_ept()) |
3419 | if (alloc_identity_pagetable(kvm) != 0) | |
3420 | goto free_vmcs; | |
3421 | ||
fb3f0f51 RR |
3422 | return &vmx->vcpu; |
3423 | ||
3424 | free_vmcs: | |
3425 | free_vmcs(vmx->vmcs); | |
3426 | free_msrs: | |
3427 | kfree(vmx->host_msrs); | |
3428 | free_guest_msrs: | |
3429 | kfree(vmx->guest_msrs); | |
3430 | uninit_vcpu: | |
3431 | kvm_vcpu_uninit(&vmx->vcpu); | |
3432 | free_vcpu: | |
a4770347 | 3433 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 3434 | return ERR_PTR(err); |
6aa8b732 AK |
3435 | } |
3436 | ||
002c7f7c YS |
3437 | static void __init vmx_check_processor_compat(void *rtn) |
3438 | { | |
3439 | struct vmcs_config vmcs_conf; | |
3440 | ||
3441 | *(int *)rtn = 0; | |
3442 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
3443 | *(int *)rtn = -EIO; | |
3444 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
3445 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
3446 | smp_processor_id()); | |
3447 | *(int *)rtn = -EIO; | |
3448 | } | |
3449 | } | |
3450 | ||
67253af5 SY |
3451 | static int get_ept_level(void) |
3452 | { | |
3453 | return VMX_EPT_DEFAULT_GAW + 1; | |
3454 | } | |
3455 | ||
cbdd1bea | 3456 | static struct kvm_x86_ops vmx_x86_ops = { |
6aa8b732 AK |
3457 | .cpu_has_kvm_support = cpu_has_kvm_support, |
3458 | .disabled_by_bios = vmx_disabled_by_bios, | |
3459 | .hardware_setup = hardware_setup, | |
3460 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 3461 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
3462 | .hardware_enable = hardware_enable, |
3463 | .hardware_disable = hardware_disable, | |
774ead3a | 3464 | .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses, |
6aa8b732 AK |
3465 | |
3466 | .vcpu_create = vmx_create_vcpu, | |
3467 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 3468 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 3469 | |
04d2cc77 | 3470 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
3471 | .vcpu_load = vmx_vcpu_load, |
3472 | .vcpu_put = vmx_vcpu_put, | |
3473 | ||
3474 | .set_guest_debug = set_guest_debug, | |
04d2cc77 | 3475 | .guest_debug_pre = kvm_guest_debug_pre, |
6aa8b732 AK |
3476 | .get_msr = vmx_get_msr, |
3477 | .set_msr = vmx_set_msr, | |
3478 | .get_segment_base = vmx_get_segment_base, | |
3479 | .get_segment = vmx_get_segment, | |
3480 | .set_segment = vmx_set_segment, | |
2e4d2653 | 3481 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 3482 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
25c4c276 | 3483 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 3484 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
3485 | .set_cr3 = vmx_set_cr3, |
3486 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 3487 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
3488 | .get_idt = vmx_get_idt, |
3489 | .set_idt = vmx_set_idt, | |
3490 | .get_gdt = vmx_get_gdt, | |
3491 | .set_gdt = vmx_set_gdt, | |
5fdbf976 | 3492 | .cache_reg = vmx_cache_reg, |
6aa8b732 AK |
3493 | .get_rflags = vmx_get_rflags, |
3494 | .set_rflags = vmx_set_rflags, | |
3495 | ||
3496 | .tlb_flush = vmx_flush_tlb, | |
6aa8b732 | 3497 | |
6aa8b732 | 3498 | .run = vmx_vcpu_run, |
04d2cc77 | 3499 | .handle_exit = kvm_handle_exit, |
6aa8b732 | 3500 | .skip_emulated_instruction = skip_emulated_instruction, |
102d8325 | 3501 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 ED |
3502 | .get_irq = vmx_get_irq, |
3503 | .set_irq = vmx_inject_irq, | |
298101da AK |
3504 | .queue_exception = vmx_queue_exception, |
3505 | .exception_injected = vmx_exception_injected, | |
04d2cc77 AK |
3506 | .inject_pending_irq = vmx_intr_assist, |
3507 | .inject_pending_vectors = do_interrupt_requests, | |
cbc94022 IE |
3508 | |
3509 | .set_tss_addr = vmx_set_tss_addr, | |
67253af5 | 3510 | .get_tdp_level = get_ept_level, |
6aa8b732 AK |
3511 | }; |
3512 | ||
3513 | static int __init vmx_init(void) | |
3514 | { | |
25c5f225 | 3515 | void *va; |
fdef3ad1 HQ |
3516 | int r; |
3517 | ||
3518 | vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
3519 | if (!vmx_io_bitmap_a) | |
3520 | return -ENOMEM; | |
3521 | ||
3522 | vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
3523 | if (!vmx_io_bitmap_b) { | |
3524 | r = -ENOMEM; | |
3525 | goto out; | |
3526 | } | |
3527 | ||
25c5f225 SY |
3528 | vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); |
3529 | if (!vmx_msr_bitmap) { | |
3530 | r = -ENOMEM; | |
3531 | goto out1; | |
3532 | } | |
3533 | ||
fdef3ad1 HQ |
3534 | /* |
3535 | * Allow direct access to the PC debug port (it is often used for I/O | |
3536 | * delays, but the vmexits simply slow things down). | |
3537 | */ | |
25c5f225 SY |
3538 | va = kmap(vmx_io_bitmap_a); |
3539 | memset(va, 0xff, PAGE_SIZE); | |
3540 | clear_bit(0x80, va); | |
cd0536d7 | 3541 | kunmap(vmx_io_bitmap_a); |
fdef3ad1 | 3542 | |
25c5f225 SY |
3543 | va = kmap(vmx_io_bitmap_b); |
3544 | memset(va, 0xff, PAGE_SIZE); | |
cd0536d7 | 3545 | kunmap(vmx_io_bitmap_b); |
fdef3ad1 | 3546 | |
25c5f225 SY |
3547 | va = kmap(vmx_msr_bitmap); |
3548 | memset(va, 0xff, PAGE_SIZE); | |
3549 | kunmap(vmx_msr_bitmap); | |
3550 | ||
2384d2b3 SY |
3551 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
3552 | ||
cb498ea2 | 3553 | r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE); |
fdef3ad1 | 3554 | if (r) |
25c5f225 SY |
3555 | goto out2; |
3556 | ||
3557 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE); | |
3558 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE); | |
3559 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS); | |
3560 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP); | |
3561 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP); | |
fdef3ad1 | 3562 | |
5fdbcb9d | 3563 | if (vm_need_ept()) { |
1439442c | 3564 | bypass_guest_pf = 0; |
5fdbcb9d SY |
3565 | kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK | |
3566 | VMX_EPT_WRITABLE_MASK | | |
928d4bf7 SY |
3567 | VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT | |
3568 | VMX_EPT_IGMT_BIT); | |
534e38b4 | 3569 | kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull, |
5fdbcb9d SY |
3570 | VMX_EPT_EXECUTABLE_MASK); |
3571 | kvm_enable_tdp(); | |
3572 | } else | |
3573 | kvm_disable_tdp(); | |
1439442c | 3574 | |
c7addb90 AK |
3575 | if (bypass_guest_pf) |
3576 | kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull); | |
3577 | ||
1439442c SY |
3578 | ept_sync_global(); |
3579 | ||
fdef3ad1 HQ |
3580 | return 0; |
3581 | ||
25c5f225 SY |
3582 | out2: |
3583 | __free_page(vmx_msr_bitmap); | |
fdef3ad1 HQ |
3584 | out1: |
3585 | __free_page(vmx_io_bitmap_b); | |
3586 | out: | |
3587 | __free_page(vmx_io_bitmap_a); | |
3588 | return r; | |
6aa8b732 AK |
3589 | } |
3590 | ||
3591 | static void __exit vmx_exit(void) | |
3592 | { | |
25c5f225 | 3593 | __free_page(vmx_msr_bitmap); |
fdef3ad1 HQ |
3594 | __free_page(vmx_io_bitmap_b); |
3595 | __free_page(vmx_io_bitmap_a); | |
3596 | ||
cb498ea2 | 3597 | kvm_exit(); |
6aa8b732 AK |
3598 | } |
3599 | ||
3600 | module_init(vmx_init) | |
3601 | module_exit(vmx_exit) |