[linux-block.git] / arch / x86 / kvm / vmx / vmx.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __KVM_X86_VMX_H
#define __KVM_X86_VMX_H

#include <linux/kvm_host.h>

#include <asm/kvm.h>
#include <asm/intel_pt.h>

#include "capabilities.h"
#include "ops.h"
#include "vmcs.h"

extern const u32 vmx_msr_index[];
extern u64 host_efer;

extern u32 get_umwait_control_msr(void);

#define MSR_TYPE_R	1
#define MSR_TYPE_W	2
#define MSR_TYPE_RW	3

#define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))

#ifdef CONFIG_X86_64
#define NR_SHARED_MSRS	7
#else
#define NR_SHARED_MSRS	4
#endif

#define NR_LOADSTORE_MSRS 8

struct vmx_msrs {
	unsigned int		nr;
	struct vmx_msr_entry	val[NR_LOADSTORE_MSRS];
};

struct shared_msr_entry {
	unsigned index;
	u64 data;
	u64 mask;
};

enum segment_cache_field {
	SEG_FIELD_SEL = 0,
	SEG_FIELD_BASE = 1,
	SEG_FIELD_LIMIT = 2,
	SEG_FIELD_AR = 3,

	SEG_FIELD_NR = 4
};

/* Posted-Interrupt Descriptor */
struct pi_desc {
	u32 pir[8];     /* Posted interrupt requested */
	union {
		struct {
				/* bit 256 - Outstanding Notification */
			u16	on	: 1,
				/* bit 257 - Suppress Notification */
				sn	: 1,
				/* bit 271:258 - Reserved */
				rsvd_1	: 14;
				/* bit 279:272 - Notification Vector */
			u8	nv;
				/* bit 287:280 - Reserved */
			u8	rsvd_2;
				/* bit 319:288 - Notification Destination */
			u32	ndst;
		};
		u64 control;
	};
	u32 rsvd[6];
} __aligned(64);

#define RTIT_ADDR_RANGE		4

struct pt_ctx {
	u64 ctl;
	u64 status;
	u64 output_base;
	u64 output_mask;
	u64 cr3_match;
	u64 addr_a[RTIT_ADDR_RANGE];
	u64 addr_b[RTIT_ADDR_RANGE];
};

struct pt_desc {
	u64 ctl_bitmask;
	u32 addr_range;
	u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
	struct pt_ctx host;
	struct pt_ctx guest;
};

/*
 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 */
struct nested_vmx {
	/* Has the level1 guest done vmxon? */
	bool vmxon;
	gpa_t vmxon_ptr;
	bool pml_full;

	/* The guest-physical address of the current VMCS L1 keeps for L2 */
	gpa_t current_vmptr;
	/*
	 * Cache of the guest's VMCS, existing outside of guest memory.
	 * Loaded from guest memory during VMPTRLD. Flushed to guest
	 * memory during VMCLEAR and VMPTRLD.
	 */
	struct vmcs12 *cached_vmcs12;
	/*
	 * Cache of the guest's shadow VMCS, existing outside of guest
	 * memory. Loaded from guest memory during VM entry. Flushed
	 * to guest memory during VM exit.
	 */
	struct vmcs12 *cached_shadow_vmcs12;

	/*
	 * Indicates if the shadow vmcs or enlightened vmcs must be updated
	 * with the data held by struct vmcs12.
	 */
	bool need_vmcs12_to_shadow_sync;
	bool dirty_vmcs12;

	/*
	 * Indicates lazily loaded guest state has not yet been decached from
	 * vmcs02.
	 */
	bool need_sync_vmcs02_to_vmcs12_rare;

	/*
	 * vmcs02 has been initialized, i.e. state that is constant for
	 * vmcs02 has been written to the backing VMCS.  Initialization
	 * is delayed until L1 actually attempts to run a nested VM.
	 */
	bool vmcs02_initialized;

	bool change_vmcs01_virtual_apic_mode;

	/*
	 * Enlightened VMCS has been enabled. It does not mean that L1 has to
	 * use it. However, VMX features available to L1 will be limited based
	 * on what the enlightened VMCS supports.
	 */
	bool enlightened_vmcs_enabled;

	/* L2 must run next, and mustn't decide to exit to L1. */
	bool nested_run_pending;

	struct loaded_vmcs vmcs02;

	/*
	 * Guest pages referred to in the vmcs02 with host-physical
	 * pointers, so we must keep them pinned while L2 runs.
	 */
	struct page *apic_access_page;
	struct kvm_host_map virtual_apic_map;
	struct kvm_host_map pi_desc_map;

	struct kvm_host_map msr_bitmap_map;

	struct pi_desc *pi_desc;
	bool pi_pending;
	u16 posted_intr_nv;

	struct hrtimer preemption_timer;
	bool preemption_timer_expired;

	/* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
	u64 vmcs01_debugctl;
	u64 vmcs01_guest_bndcfgs;

	/* to migrate it to L1 if L2 writes to L1's CR8 directly */
	int l1_tpr_threshold;

	u16 vpid02;
	u16 last_vpid;

	struct nested_vmx_msrs msrs;

	/* SMM related state */
	struct {
		/* in VMX operation on SMM entry? */
		bool vmxon;
		/* in guest mode on SMM entry? */
		bool guest_mode;
	} smm;

	gpa_t hv_evmcs_vmptr;
	struct kvm_host_map hv_evmcs_map;
	struct hv_enlightened_vmcs *hv_evmcs;
};

struct vcpu_vmx {
	struct kvm_vcpu       vcpu;
	u8                    fail;
	u8		      msr_bitmap_mode;

	/*
	 * If true, host state has been stored in vmx->loaded_vmcs for
	 * the CPU registers that only need to be switched when transitioning
	 * to/from the kernel, and the registers have been loaded with guest
	 * values.  If false, host state is loaded in the CPU registers
	 * and vmx->loaded_vmcs->host_state is invalid.
	 */
	bool		      guest_state_loaded;

	u32                   exit_intr_info;
	u32                   idt_vectoring_info;
	ulong                 rflags;

	struct shared_msr_entry guest_msrs[NR_SHARED_MSRS];
	int                   nmsrs;
	int                   save_nmsrs;
	bool                  guest_msrs_ready;
#ifdef CONFIG_X86_64
	u64		      msr_host_kernel_gs_base;
	u64		      msr_guest_kernel_gs_base;
#endif

	u64		      spec_ctrl;
	u32		      msr_ia32_umwait_control;

	u32 secondary_exec_control;

	/*
	 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
	 * non-nested (L1) guest, it always points to vmcs01. For a nested
	 * guest (L2), it points to a different VMCS.
	 */
	struct loaded_vmcs    vmcs01;
	struct loaded_vmcs   *loaded_vmcs;

	struct msr_autoload {
		struct vmx_msrs guest;
		struct vmx_msrs host;
	} msr_autoload;

	struct msr_autostore {
		struct vmx_msrs guest;
	} msr_autostore;

	struct {
		int vm86_active;
		ulong save_rflags;
		struct kvm_segment segs[8];
	} rmode;
	struct {
		u32 bitmask; /* 4 bits per segment (1 bit per field) */
		struct kvm_save_segment {
			u16 selector;
			unsigned long base;
			u32 limit;
			u32 ar;
		} seg[8];
	} segment_cache;
	int vpid;
	bool emulation_required;

	u32 exit_reason;

	/* Posted interrupt descriptor */
	struct pi_desc pi_desc;

	/* Support for a guest hypervisor (nested VMX) */
	struct nested_vmx nested;

	/* Dynamic PLE window. */
	unsigned int ple_window;
	bool ple_window_dirty;

	bool req_immediate_exit;

	/* Support for PML */
#define PML_ENTITY_NUM		512
	struct page *pml_pg;

	/* apic deadline value in host tsc */
	u64 hv_deadline_tsc;

	u64 current_tsc_ratio;

	u32 host_pkru;

	unsigned long host_debugctlmsr;

	/*
	 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
	 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included
	 * in msr_ia32_feature_control_valid_bits.
	 */
	u64 msr_ia32_feature_control;
	u64 msr_ia32_feature_control_valid_bits;
	u64 ept_pointer;

	struct pt_desc pt_desc;
};

enum ept_pointers_status {
	EPT_POINTERS_CHECK = 0,
	EPT_POINTERS_MATCH = 1,
	EPT_POINTERS_MISMATCH = 2
};

struct kvm_vmx {
	struct kvm kvm;

	unsigned int tss_addr;
	bool ept_identity_pagetable_done;
	gpa_t ept_identity_map_addr;

	enum ept_pointers_status ept_pointers_match;
	spinlock_t ept_pointer_lock;
};

bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu);
void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
int allocate_vpid(void);
void free_vpid(int vpid);
void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
			unsigned long fs_base, unsigned long gs_base);
int vmx_get_cpl(struct kvm_vcpu *vcpu);
unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
void ept_save_pdptrs(struct kvm_vcpu *vcpu);
void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
void update_exception_bitmap(struct kvm_vcpu *vcpu);
void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr);
void pt_update_intercept_for_msr(struct vcpu_vmx *vmx);
void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
int vmx_find_msr_index(struct vmx_msrs *m, u32 msr);

#define POSTED_INTR_ON  0
#define POSTED_INTR_SN  1

static inline bool pi_test_and_set_on(struct pi_desc *pi_desc)
{
	return test_and_set_bit(POSTED_INTR_ON,
			(unsigned long *)&pi_desc->control);
}

static inline bool pi_test_and_clear_on(struct pi_desc *pi_desc)
{
	return test_and_clear_bit(POSTED_INTR_ON,
			(unsigned long *)&pi_desc->control);
}

static inline int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
{
	return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
}

static inline bool pi_is_pir_empty(struct pi_desc *pi_desc)
{
	return bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS);
}

static inline void pi_set_sn(struct pi_desc *pi_desc)
{
	set_bit(POSTED_INTR_SN,
		(unsigned long *)&pi_desc->control);
}

static inline void pi_set_on(struct pi_desc *pi_desc)
{
	set_bit(POSTED_INTR_ON,
		(unsigned long *)&pi_desc->control);
}

static inline void pi_clear_on(struct pi_desc *pi_desc)
{
	clear_bit(POSTED_INTR_ON,
		(unsigned long *)&pi_desc->control);
}

static inline void pi_clear_sn(struct pi_desc *pi_desc)
{
	clear_bit(POSTED_INTR_SN,
		(unsigned long *)&pi_desc->control);
}

static inline int pi_test_on(struct pi_desc *pi_desc)
{
	return test_bit(POSTED_INTR_ON,
			(unsigned long *)&pi_desc->control);
}

static inline int pi_test_sn(struct pi_desc *pi_desc)
{
	return test_bit(POSTED_INTR_SN,
			(unsigned long *)&pi_desc->control);
}

static inline u8 vmx_get_rvi(void)
{
	return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
}

#define BUILD_CONTROLS_SHADOW(lname, uname)				    \
static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val)	    \
{									    \
	if (vmx->loaded_vmcs->controls_shadow.lname != val) {		    \
		vmcs_write32(uname, val);				    \
		vmx->loaded_vmcs->controls_shadow.lname = val;		    \
	}								    \
}									    \
static inline u32 lname##_controls_get(struct vcpu_vmx *vmx)		    \
{									    \
	return vmx->loaded_vmcs->controls_shadow.lname;			    \
}									    \
static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val)   \
{									    \
	lname##_controls_set(vmx, lname##_controls_get(vmx) | val);	    \
}									    \
static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \
{									    \
	lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val);	    \
}
BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL)
BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL)
BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL)

static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
{
	vmx->segment_cache.bitmask = 0;
}

static inline u32 vmx_vmentry_ctrl(void)
{
	u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
	if (pt_mode == PT_MODE_SYSTEM)
		vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP |
				  VM_ENTRY_LOAD_IA32_RTIT_CTL);
	/* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
	return vmentry_ctrl &
		~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
}

static inline u32 vmx_vmexit_ctrl(void)
{
	u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
	if (pt_mode == PT_MODE_SYSTEM)
		vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP |
				 VM_EXIT_CLEAR_IA32_RTIT_CTL);
	/* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
	return vmexit_ctrl &
		~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
}

u32 vmx_exec_control(struct vcpu_vmx *vmx);
u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx);

static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
{
	return container_of(kvm, struct kvm_vmx, kvm);
}

static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
{
	return container_of(vcpu, struct vcpu_vmx, vcpu);
}

static inline struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
{
	return &(to_vmx(vcpu)->pi_desc);
}

struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
void free_vmcs(struct vmcs *vmcs);
int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs);
void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);

static inline struct vmcs *alloc_vmcs(bool shadow)
{
	return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
			      GFP_KERNEL_ACCOUNT);
}

u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);

static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
				bool invalidate_gpa)
{
	if (enable_ept && (invalidate_gpa || !enable_vpid)) {
		if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
			return;
		ept_sync_context(construct_eptp(vcpu,
						vcpu->arch.mmu->root_hpa));
	} else {
		vpid_sync_context(vpid);
	}
}

static inline void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
{
	__vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
}

static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx)
{
	vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
	vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
}

static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx)
{
	return vmx->secondary_exec_control &
		SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
}

void dump_vmcs(void);

#endif /* __KVM_X86_VMX_H */
Commit	Line	Data
8373d25d SC	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	#ifndef __KVM_X86_VMX_H
	3	#define __KVM_X86_VMX_H
	4
	5	#include <linux/kvm_host.h>
	6
	7	#include <asm/kvm.h>
f99e3daf	8	#include <asm/intel_pt.h>
8373d25d SC	9
8373d25d SC	10	#include "capabilities.h"
89b0c9f5	11	#include "ops.h"
8373d25d SC	12	#include "vmcs.h"
8373d25d SC	13
cf3646eb	14	extern const u32 vmx_msr_index[];
cf3646eb SC	15	extern u64 host_efer;
cf3646eb SC	16
6e3ba4ab TX	17	extern u32 get_umwait_control_msr(void);
6e3ba4ab TX	18
8373d25d SC	19	#define MSR_TYPE_R 1
	20	#define MSR_TYPE_W 2
	21	#define MSR_TYPE_RW 3
	22
	23	#define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
	24
7d73710d JM	25	#ifdef CONFIG_X86_64
	26	#define NR_SHARED_MSRS 7
	27	#else
	28	#define NR_SHARED_MSRS 4
	29	#endif
	30
7cfe0526	31	#define NR_LOADSTORE_MSRS 8
8373d25d SC	32
	33	struct vmx_msrs {
	34	unsigned int nr;
7cfe0526	35	struct vmx_msr_entry val[NR_LOADSTORE_MSRS];
8373d25d SC	36	};
	37
	38	struct shared_msr_entry {
	39	unsigned index;
	40	u64 data;
	41	u64 mask;
	42	};
	43
	44	enum segment_cache_field {
	45	SEG_FIELD_SEL = 0,
	46	SEG_FIELD_BASE = 1,
	47	SEG_FIELD_LIMIT = 2,
	48	SEG_FIELD_AR = 3,
	49
	50	SEG_FIELD_NR = 4
	51	};
	52
	53	/* Posted-Interrupt Descriptor */
	54	struct pi_desc {
	55	u32 pir[8]; /* Posted interrupt requested */
	56	union {
	57	struct {
	58	/* bit 256 - Outstanding Notification */
	59	u16 on : 1,
	60	/* bit 257 - Suppress Notification */
	61	sn : 1,
	62	/* bit 271:258 - Reserved */
	63	rsvd_1 : 14;
	64	/* bit 279:272 - Notification Vector */
	65	u8 nv;
	66	/* bit 287:280 - Reserved */
	67	u8 rsvd_2;
	68	/* bit 319:288 - Notification Destination */
	69	u32 ndst;
	70	};
	71	u64 control;
	72	};
	73	u32 rsvd[6];
	74	} __aligned(64);
	75
2ef444f1 CP	76	#define RTIT_ADDR_RANGE 4
	77
	78	struct pt_ctx {
	79	u64 ctl;
	80	u64 status;
	81	u64 output_base;
	82	u64 output_mask;
	83	u64 cr3_match;
	84	u64 addr_a[RTIT_ADDR_RANGE];
	85	u64 addr_b[RTIT_ADDR_RANGE];
	86	};
	87
	88	struct pt_desc {
	89	u64 ctl_bitmask;
	90	u32 addr_range;
	91	u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
	92	struct pt_ctx host;
	93	struct pt_ctx guest;
	94	};
8373d25d SC	95
	96	/*
	97	* The nested_vmx structure is part of vcpu_vmx, and holds information we need
	98	* for correct emulation of VMX (i.e., nested VMX) on this vcpu.
	99	*/
	100	struct nested_vmx {
	101	/* Has the level1 guest done vmxon? */
	102	bool vmxon;
	103	gpa_t vmxon_ptr;
	104	bool pml_full;
	105
	106	/* The guest-physical address of the current VMCS L1 keeps for L2 */
	107	gpa_t current_vmptr;
	108	/*
	109	* Cache of the guest's VMCS, existing outside of guest memory.
	110	* Loaded from guest memory during VMPTRLD. Flushed to guest
	111	* memory during VMCLEAR and VMPTRLD.
	112	*/
	113	struct vmcs12 *cached_vmcs12;
	114	/*
	115	* Cache of the guest's shadow VMCS, existing outside of guest
	116	* memory. Loaded from guest memory during VM entry. Flushed
	117	* to guest memory during VM exit.
	118	*/
	119	struct vmcs12 *cached_shadow_vmcs12;
7952d769	120
8373d25d SC	121	/*
	122	* Indicates if the shadow vmcs or enlightened vmcs must be updated
	123	* with the data held by struct vmcs12.
	124	*/
3731905e	125	bool need_vmcs12_to_shadow_sync;
8373d25d SC	126	bool dirty_vmcs12;
8373d25d SC	127
7952d769 SC	128	/*
	129	* Indicates lazily loaded guest state has not yet been decached from
	130	* vmcs02.
	131	*/
	132	bool need_sync_vmcs02_to_vmcs12_rare;
	133
8373d25d SC	134	/*
	135	* vmcs02 has been initialized, i.e. state that is constant for
	136	* vmcs02 has been written to the backing VMCS. Initialization
	137	* is delayed until L1 actually attempts to run a nested VM.
	138	*/
	139	bool vmcs02_initialized;
	140
	141	bool change_vmcs01_virtual_apic_mode;
	142
	143	/*
	144	* Enlightened VMCS has been enabled. It does not mean that L1 has to
	145	* use it. However, VMX features available to L1 will be limited based
	146	* on what the enlightened VMCS supports.
	147	*/
	148	bool enlightened_vmcs_enabled;
	149
	150	/* L2 must run next, and mustn't decide to exit to L1. */
	151	bool nested_run_pending;
	152
	153	struct loaded_vmcs vmcs02;
	154
	155	/*
	156	* Guest pages referred to in the vmcs02 with host-physical
	157	* pointers, so we must keep them pinned while L2 runs.
	158	*/
	159	struct page *apic_access_page;
96c66e87	160	struct kvm_host_map virtual_apic_map;
3278e049	161	struct kvm_host_map pi_desc_map;
31f0b6c4 KA	162
	163	struct kvm_host_map msr_bitmap_map;
	164
8373d25d SC	165	struct pi_desc *pi_desc;
	166	bool pi_pending;
	167	u16 posted_intr_nv;
	168
	169	struct hrtimer preemption_timer;
	170	bool preemption_timer_expired;
	171
	172	/* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
	173	u64 vmcs01_debugctl;
	174	u64 vmcs01_guest_bndcfgs;
	175
02d496cf LA	176	/* to migrate it to L1 if L2 writes to L1's CR8 directly */
	177	int l1_tpr_threshold;
	178
8373d25d SC	179	u16 vpid02;
	180	u16 last_vpid;
	181
	182	struct nested_vmx_msrs msrs;
	183
	184	/* SMM related state */
	185	struct {
	186	/* in VMX operation on SMM entry? */
	187	bool vmxon;
	188	/* in guest mode on SMM entry? */
	189	bool guest_mode;
	190	} smm;
	191
	192	gpa_t hv_evmcs_vmptr;
dee9c049	193	struct kvm_host_map hv_evmcs_map;
8373d25d SC	194	struct hv_enlightened_vmcs *hv_evmcs;
	195	};
	196
	197	struct vcpu_vmx {
	198	struct kvm_vcpu vcpu;
8373d25d SC	199	u8 fail;
8373d25d SC	200	u8 msr_bitmap_mode;
b464f57e PB	201
	202	/*
	203	* If true, host state has been stored in vmx->loaded_vmcs for
	204	* the CPU registers that only need to be switched when transitioning
	205	* to/from the kernel, and the registers have been loaded with guest
	206	* values. If false, host state is loaded in the CPU registers
	207	* and vmx->loaded_vmcs->host_state is invalid.
	208	*/
	209	bool guest_state_loaded;
	210
8373d25d SC	211	u32 exit_intr_info;
	212	u32 idt_vectoring_info;
	213	ulong rflags;
70f932ec	214
7d73710d	215	struct shared_msr_entry guest_msrs[NR_SHARED_MSRS];
8373d25d SC	216	int nmsrs;
8373d25d SC	217	int save_nmsrs;
b464f57e	218	bool guest_msrs_ready;
8373d25d SC	219	#ifdef CONFIG_X86_64
	220	u64 msr_host_kernel_gs_base;
	221	u64 msr_guest_kernel_gs_base;
	222	#endif
	223
8373d25d	224	u64 spec_ctrl;
6e3ba4ab	225	u32 msr_ia32_umwait_control;
8373d25d	226
8373d25d SC	227	u32 secondary_exec_control;
	228
	229	/*
	230	* loaded_vmcs points to the VMCS currently used in this vcpu. For a
	231	* non-nested (L1) guest, it always points to vmcs01. For a nested
b464f57e	232	* guest (L2), it points to a different VMCS.
8373d25d SC	233	*/
	234	struct loaded_vmcs vmcs01;
	235	struct loaded_vmcs *loaded_vmcs;
c9afc58c	236
8373d25d SC	237	struct msr_autoload {
	238	struct vmx_msrs guest;
	239	struct vmx_msrs host;
	240	} msr_autoload;
	241
662f1d1d AL	242	struct msr_autostore {
	243	struct vmx_msrs guest;
	244	} msr_autostore;
	245
8373d25d SC	246	struct {
	247	int vm86_active;
	248	ulong save_rflags;
	249	struct kvm_segment segs[8];
	250	} rmode;
	251	struct {
	252	u32 bitmask; /* 4 bits per segment (1 bit per field) */
	253	struct kvm_save_segment {
	254	u16 selector;
	255	unsigned long base;
	256	u32 limit;
	257	u32 ar;
	258	} seg[8];
	259	} segment_cache;
	260	int vpid;
	261	bool emulation_required;
	262
	263	u32 exit_reason;
	264
	265	/* Posted interrupt descriptor */
	266	struct pi_desc pi_desc;
	267
	268	/* Support for a guest hypervisor (nested VMX) */
	269	struct nested_vmx nested;
	270
	271	/* Dynamic PLE window. */
c5c5d6fa	272	unsigned int ple_window;
8373d25d SC	273	bool ple_window_dirty;
	274
	275	bool req_immediate_exit;
	276
	277	/* Support for PML */
	278	#define PML_ENTITY_NUM 512
	279	struct page *pml_pg;
	280
	281	/* apic deadline value in host tsc */
	282	u64 hv_deadline_tsc;
	283
	284	u64 current_tsc_ratio;
	285
	286	u32 host_pkru;
	287
	288	unsigned long host_debugctlmsr;
	289
	290	/*
	291	* Only bits masked by msr_ia32_feature_control_valid_bits can be set in
32ad73db	292	* msr_ia32_feature_control. FEAT_CTL_LOCKED is always included
8373d25d SC	293	* in msr_ia32_feature_control_valid_bits.
	294	*/
	295	u64 msr_ia32_feature_control;
	296	u64 msr_ia32_feature_control_valid_bits;
	297	u64 ept_pointer;
2ef444f1 CP	298
2ef444f1 CP	299	struct pt_desc pt_desc;
8373d25d SC	300	};
	301
	302	enum ept_pointers_status {
	303	EPT_POINTERS_CHECK = 0,
	304	EPT_POINTERS_MATCH = 1,
	305	EPT_POINTERS_MISMATCH = 2
	306	};
	307
	308	struct kvm_vmx {
	309	struct kvm kvm;
	310
	311	unsigned int tss_addr;
	312	bool ept_identity_pagetable_done;
	313	gpa_t ept_identity_map_addr;
	314
	315	enum ept_pointers_status ept_pointers_match;
	316	spinlock_t ept_pointer_lock;
	317	};
	318
7c97fcb3	319	bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
8ef863e6	320	void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu);
97b7ead3	321	void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
97b7ead3 SC	322	int allocate_vpid(void);
	323	void free_vpid(int vpid);
	324	void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
	325	void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
13b964a2 SC	326	void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
13b964a2 SC	327	unsigned long fs_base, unsigned long gs_base);
97b7ead3 SC	328	int vmx_get_cpl(struct kvm_vcpu *vcpu);
	329	unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
	330	void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
	331	u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
	332	void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
	333	void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
	334	void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
	335	void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
	336	int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
	337	void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
	338	void ept_save_pdptrs(struct kvm_vcpu *vcpu);
	339	void vmx_get_segment(struct kvm_vcpu vcpu, struct kvm_segment var, int seg);
	340	void vmx_set_segment(struct kvm_vcpu vcpu, struct kvm_segment var, int seg);
	341	u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
	342	void update_exception_bitmap(struct kvm_vcpu *vcpu);
	343	void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
	344	bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
	345	void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
	346	void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
	347	struct shared_msr_entry find_msr_entry(struct vcpu_vmx vmx, u32 msr);
b08c2896	348	void pt_update_intercept_for_msr(struct vcpu_vmx *vmx);
4d259965	349	void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
662f1d1d	350	int vmx_find_msr_index(struct vmx_msrs *m, u32 msr);
97b7ead3	351
8373d25d SC	352	#define POSTED_INTR_ON 0
	353	#define POSTED_INTR_SN 1
	354
	355	static inline bool pi_test_and_set_on(struct pi_desc *pi_desc)
	356	{
	357	return test_and_set_bit(POSTED_INTR_ON,
	358	(unsigned long *)&pi_desc->control);
	359	}
	360
	361	static inline bool pi_test_and_clear_on(struct pi_desc *pi_desc)
	362	{
	363	return test_and_clear_bit(POSTED_INTR_ON,
	364	(unsigned long *)&pi_desc->control);
	365	}
	366
	367	static inline int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
	368	{
	369	return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
	370	}
	371
29881b6e JM	372	static inline bool pi_is_pir_empty(struct pi_desc *pi_desc)
	373	{
	374	return bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS);
	375	}
	376
81b01667	377	static inline void pi_set_sn(struct pi_desc *pi_desc)
8373d25d	378	{
81b01667 LK	379	set_bit(POSTED_INTR_SN,
81b01667 LK	380	(unsigned long *)&pi_desc->control);
8373d25d SC	381	}
8373d25d SC	382
81b01667	383	static inline void pi_set_on(struct pi_desc *pi_desc)
8373d25d	384	{
81b01667 LK	385	set_bit(POSTED_INTR_ON,
81b01667 LK	386	(unsigned long *)&pi_desc->control);
8373d25d SC	387	}
	388
	389	static inline void pi_clear_on(struct pi_desc *pi_desc)
	390	{
	391	clear_bit(POSTED_INTR_ON,
	392	(unsigned long *)&pi_desc->control);
132194ff JM	393	}
	394
	395	static inline void pi_clear_sn(struct pi_desc *pi_desc)
	396	{
	397	clear_bit(POSTED_INTR_SN,
	398	(unsigned long *)&pi_desc->control);
8373d25d SC	399	}
	400
	401	static inline int pi_test_on(struct pi_desc *pi_desc)
	402	{
	403	return test_bit(POSTED_INTR_ON,
	404	(unsigned long *)&pi_desc->control);
	405	}
	406
	407	static inline int pi_test_sn(struct pi_desc *pi_desc)
	408	{
	409	return test_bit(POSTED_INTR_SN,
	410	(unsigned long *)&pi_desc->control);
	411	}
	412
89b0c9f5 SC	413	static inline u8 vmx_get_rvi(void)
	414	{
	415	return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
	416	}
	417
70f932ec	418	#define BUILD_CONTROLS_SHADOW(lname, uname) \
70f932ec SC	419	static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val) \
70f932ec SC	420	{ \
09e226cf SC	421	if (vmx->loaded_vmcs->controls_shadow.lname != val) { \
	422	vmcs_write32(uname, val); \
	423	vmx->loaded_vmcs->controls_shadow.lname = val; \
	424	} \
70f932ec SC	425	} \
	426	static inline u32 lname##_controls_get(struct vcpu_vmx *vmx) \
	427	{ \
09e226cf	428	return vmx->loaded_vmcs->controls_shadow.lname; \
70f932ec SC	429	} \
	430	static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val) \
	431	{ \
	432	lname##_controls_set(vmx, lname##_controls_get(vmx) \| val); \
	433	} \
	434	static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \
	435	{ \
	436	lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \
89b0c9f5	437	}
70f932ec SC	438	BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
70f932ec SC	439	BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
c5f2c766	440	BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL)
2183f564	441	BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL)
fe7f895d	442	BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL)
89b0c9f5	443
8373d25d SC	444	static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
	445	{
	446	vmx->segment_cache.bitmask = 0;
	447	}
	448
	449	static inline u32 vmx_vmentry_ctrl(void)
	450	{
f99e3daf CP	451	u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
f99e3daf CP	452	if (pt_mode == PT_MODE_SYSTEM)
d9293597 YZ	453	vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP \|
d9293597 YZ	454	VM_ENTRY_LOAD_IA32_RTIT_CTL);
8373d25d	455	/* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
f99e3daf	456	return vmentry_ctrl &
8373d25d SC	457	~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL \| VM_ENTRY_LOAD_IA32_EFER);
	458	}
	459
	460	static inline u32 vmx_vmexit_ctrl(void)
	461	{
f99e3daf CP	462	u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
f99e3daf CP	463	if (pt_mode == PT_MODE_SYSTEM)
d9293597 YZ	464	vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP \|
d9293597 YZ	465	VM_EXIT_CLEAR_IA32_RTIT_CTL);
8373d25d	466	/* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
d9293597	467	return vmexit_ctrl &
8373d25d SC	468	~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL \| VM_EXIT_LOAD_IA32_EFER);
	469	}
	470
	471	u32 vmx_exec_control(struct vcpu_vmx *vmx);
c075c3e4	472	u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx);
8373d25d SC	473
	474	static inline struct kvm_vmx to_kvm_vmx(struct kvm kvm)
	475	{
	476	return container_of(kvm, struct kvm_vmx, kvm);
	477	}
	478
	479	static inline struct vcpu_vmx to_vmx(struct kvm_vcpu vcpu)
	480	{
	481	return container_of(vcpu, struct vcpu_vmx, vcpu);
	482	}
	483
	484	static inline struct pi_desc vcpu_to_pi_desc(struct kvm_vcpu vcpu)
	485	{
	486	return &(to_vmx(vcpu)->pi_desc);
	487	}
	488
41836839	489	struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
89b0c9f5 SC	490	void free_vmcs(struct vmcs *vmcs);
	491	int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
	492	void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
	493	void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs);
	494	void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
	495
	496	static inline struct vmcs *alloc_vmcs(bool shadow)
	497	{
41836839 BG	498	return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
41836839 BG	499	GFP_KERNEL_ACCOUNT);
89b0c9f5 SC	500	}
	501
	502	u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
	503
	504	static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
	505	bool invalidate_gpa)
	506	{
	507	if (enable_ept && (invalidate_gpa \|\| !enable_vpid)) {
	508	if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
	509	return;
	510	ept_sync_context(construct_eptp(vcpu,
	511	vcpu->arch.mmu->root_hpa));
	512	} else {
	513	vpid_sync_context(vpid);
	514	}
	515	}
	516
	517	static inline void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
	518	{
	519	__vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
	520	}
	521
	522	static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx)
	523	{
	524	vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
	525	vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
	526	}
	527
6e3ba4ab TX	528	static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx)
	529	{
	530	return vmx->secondary_exec_control &
	531	SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
	532	}
	533
69090810 PB	534	void dump_vmcs(void);
69090810 PB	535
8373d25d	536	#endif /* __KVM_X86_VMX_H */