[linux-block.git] / arch / x86 / kvm / vmx / vmx.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __KVM_X86_VMX_H
#define __KVM_X86_VMX_H

#include <linux/kvm_host.h>

#include <asm/kvm.h>
#include <asm/intel_pt.h>

#include "capabilities.h"
#include "ops.h"
#include "vmcs.h"

extern const u32 vmx_msr_index[];
extern u64 host_efer;

#define MSR_TYPE_R	1
#define MSR_TYPE_W	2
#define MSR_TYPE_RW	3

#define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))

#define NR_AUTOLOAD_MSRS 8

struct vmx_msrs {
	unsigned int		nr;
	struct vmx_msr_entry	val[NR_AUTOLOAD_MSRS];
};

struct shared_msr_entry {
	unsigned index;
	u64 data;
	u64 mask;
};

enum segment_cache_field {
	SEG_FIELD_SEL = 0,
	SEG_FIELD_BASE = 1,
	SEG_FIELD_LIMIT = 2,
	SEG_FIELD_AR = 3,

	SEG_FIELD_NR = 4
};

/* Posted-Interrupt Descriptor */
struct pi_desc {
	u32 pir[8];     /* Posted interrupt requested */
	union {
		struct {
				/* bit 256 - Outstanding Notification */
			u16	on	: 1,
				/* bit 257 - Suppress Notification */
				sn	: 1,
				/* bit 271:258 - Reserved */
				rsvd_1	: 14;
				/* bit 279:272 - Notification Vector */
			u8	nv;
				/* bit 287:280 - Reserved */
			u8	rsvd_2;
				/* bit 319:288 - Notification Destination */
			u32	ndst;
		};
		u64 control;
	};
	u32 rsvd[6];
} __aligned(64);

#define RTIT_ADDR_RANGE		4

struct pt_ctx {
	u64 ctl;
	u64 status;
	u64 output_base;
	u64 output_mask;
	u64 cr3_match;
	u64 addr_a[RTIT_ADDR_RANGE];
	u64 addr_b[RTIT_ADDR_RANGE];
};

struct pt_desc {
	u64 ctl_bitmask;
	u32 addr_range;
	u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
	struct pt_ctx host;
	struct pt_ctx guest;
};

/*
 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 */
struct nested_vmx {
	/* Has the level1 guest done vmxon? */
	bool vmxon;
	gpa_t vmxon_ptr;
	bool pml_full;

	/* The guest-physical address of the current VMCS L1 keeps for L2 */
	gpa_t current_vmptr;
	/*
	 * Cache of the guest's VMCS, existing outside of guest memory.
	 * Loaded from guest memory during VMPTRLD. Flushed to guest
	 * memory during VMCLEAR and VMPTRLD.
	 */
	struct vmcs12 *cached_vmcs12;
	/*
	 * Cache of the guest's shadow VMCS, existing outside of guest
	 * memory. Loaded from guest memory during VM entry. Flushed
	 * to guest memory during VM exit.
	 */
	struct vmcs12 *cached_shadow_vmcs12;

	/*
	 * Indicates if the shadow vmcs or enlightened vmcs must be updated
	 * with the data held by struct vmcs12.
	 */
	bool need_vmcs12_to_shadow_sync;
	bool dirty_vmcs12;

	/*
	 * Indicates lazily loaded guest state has not yet been decached from
	 * vmcs02.
	 */
	bool need_sync_vmcs02_to_vmcs12_rare;

	/*
	 * vmcs02 has been initialized, i.e. state that is constant for
	 * vmcs02 has been written to the backing VMCS.  Initialization
	 * is delayed until L1 actually attempts to run a nested VM.
	 */
	bool vmcs02_initialized;

	bool change_vmcs01_virtual_apic_mode;

	/*
	 * Enlightened VMCS has been enabled. It does not mean that L1 has to
	 * use it. However, VMX features available to L1 will be limited based
	 * on what the enlightened VMCS supports.
	 */
	bool enlightened_vmcs_enabled;

	/* L2 must run next, and mustn't decide to exit to L1. */
	bool nested_run_pending;

	struct loaded_vmcs vmcs02;

	/*
	 * Guest pages referred to in the vmcs02 with host-physical
	 * pointers, so we must keep them pinned while L2 runs.
	 */
	struct page *apic_access_page;
	struct kvm_host_map virtual_apic_map;
	struct kvm_host_map pi_desc_map;

	struct kvm_host_map msr_bitmap_map;

	struct pi_desc *pi_desc;
	bool pi_pending;
	u16 posted_intr_nv;

	struct hrtimer preemption_timer;
	bool preemption_timer_expired;

	/* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
	u64 vmcs01_debugctl;
	u64 vmcs01_guest_bndcfgs;

	u16 vpid02;
	u16 last_vpid;

	struct nested_vmx_msrs msrs;

	/* SMM related state */
	struct {
		/* in VMX operation on SMM entry? */
		bool vmxon;
		/* in guest mode on SMM entry? */
		bool guest_mode;
	} smm;

	gpa_t hv_evmcs_vmptr;
	struct kvm_host_map hv_evmcs_map;
	struct hv_enlightened_vmcs *hv_evmcs;
};

struct vcpu_vmx {
	struct kvm_vcpu       vcpu;
	u8                    fail;
	u8		      msr_bitmap_mode;

	/*
	 * If true, host state has been stored in vmx->loaded_vmcs for
	 * the CPU registers that only need to be switched when transitioning
	 * to/from the kernel, and the registers have been loaded with guest
	 * values.  If false, host state is loaded in the CPU registers
	 * and vmx->loaded_vmcs->host_state is invalid.
	 */
	bool		      guest_state_loaded;

	u32                   exit_intr_info;
	u32                   idt_vectoring_info;
	ulong                 rflags;
	struct shared_msr_entry *guest_msrs;
	int                   nmsrs;
	int                   save_nmsrs;
	bool                  guest_msrs_ready;
#ifdef CONFIG_X86_64
	u64		      msr_host_kernel_gs_base;
	u64		      msr_guest_kernel_gs_base;
#endif

	u64		      spec_ctrl;

	u32 vm_entry_controls_shadow;
	u32 vm_exit_controls_shadow;
	u32 secondary_exec_control;

	/*
	 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
	 * non-nested (L1) guest, it always points to vmcs01. For a nested
	 * guest (L2), it points to a different VMCS.
	 */
	struct loaded_vmcs    vmcs01;
	struct loaded_vmcs   *loaded_vmcs;

	struct msr_autoload {
		struct vmx_msrs guest;
		struct vmx_msrs host;
	} msr_autoload;

	struct {
		int vm86_active;
		ulong save_rflags;
		struct kvm_segment segs[8];
	} rmode;
	struct {
		u32 bitmask; /* 4 bits per segment (1 bit per field) */
		struct kvm_save_segment {
			u16 selector;
			unsigned long base;
			u32 limit;
			u32 ar;
		} seg[8];
	} segment_cache;
	int vpid;
	bool emulation_required;

	u32 exit_reason;

	/* Posted interrupt descriptor */
	struct pi_desc pi_desc;

	/* Support for a guest hypervisor (nested VMX) */
	struct nested_vmx nested;

	/* Dynamic PLE window. */
	int ple_window;
	bool ple_window_dirty;

	bool req_immediate_exit;

	/* Support for PML */
#define PML_ENTITY_NUM		512
	struct page *pml_pg;

	/* apic deadline value in host tsc */
	u64 hv_deadline_tsc;

	u64 current_tsc_ratio;

	u32 host_pkru;

	unsigned long host_debugctlmsr;

	/*
	 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
	 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
	 * in msr_ia32_feature_control_valid_bits.
	 */
	u64 msr_ia32_feature_control;
	u64 msr_ia32_feature_control_valid_bits;
	u64 ept_pointer;

	struct pt_desc pt_desc;
};

enum ept_pointers_status {
	EPT_POINTERS_CHECK = 0,
	EPT_POINTERS_MATCH = 1,
	EPT_POINTERS_MISMATCH = 2
};

struct kvm_vmx {
	struct kvm kvm;

	unsigned int tss_addr;
	bool ept_identity_pagetable_done;
	gpa_t ept_identity_map_addr;

	enum ept_pointers_status ept_pointers_match;
	spinlock_t ept_pointer_lock;
};

bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu);
void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
int allocate_vpid(void);
void free_vpid(int vpid);
void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
			unsigned long fs_base, unsigned long gs_base);
int vmx_get_cpl(struct kvm_vcpu *vcpu);
unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
void ept_save_pdptrs(struct kvm_vcpu *vcpu);
void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
void update_exception_bitmap(struct kvm_vcpu *vcpu);
void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr);
void pt_update_intercept_for_msr(struct vcpu_vmx *vmx);
void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);

#define POSTED_INTR_ON  0
#define POSTED_INTR_SN  1

static inline bool pi_test_and_set_on(struct pi_desc *pi_desc)
{
	return test_and_set_bit(POSTED_INTR_ON,
			(unsigned long *)&pi_desc->control);
}

static inline bool pi_test_and_clear_on(struct pi_desc *pi_desc)
{
	return test_and_clear_bit(POSTED_INTR_ON,
			(unsigned long *)&pi_desc->control);
}

static inline int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
{
	return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
}

static inline void pi_set_sn(struct pi_desc *pi_desc)
{
	set_bit(POSTED_INTR_SN,
		(unsigned long *)&pi_desc->control);
}

static inline void pi_set_on(struct pi_desc *pi_desc)
{
	set_bit(POSTED_INTR_ON,
		(unsigned long *)&pi_desc->control);
}

static inline void pi_clear_on(struct pi_desc *pi_desc)
{
	clear_bit(POSTED_INTR_ON,
		(unsigned long *)&pi_desc->control);
}

static inline int pi_test_on(struct pi_desc *pi_desc)
{
	return test_bit(POSTED_INTR_ON,
			(unsigned long *)&pi_desc->control);
}

static inline int pi_test_sn(struct pi_desc *pi_desc)
{
	return test_bit(POSTED_INTR_SN,
			(unsigned long *)&pi_desc->control);
}

static inline u8 vmx_get_rvi(void)
{
	return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
}

static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
{
	vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
}

static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
{
	vmcs_write32(VM_ENTRY_CONTROLS, val);
	vmx->vm_entry_controls_shadow = val;
}

static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
{
	if (vmx->vm_entry_controls_shadow != val)
		vm_entry_controls_init(vmx, val);
}

static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
{
	return vmx->vm_entry_controls_shadow;
}

static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
{
	vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
}

static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
{
	vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
}

static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
{
	vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
}

static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
{
	vmcs_write32(VM_EXIT_CONTROLS, val);
	vmx->vm_exit_controls_shadow = val;
}

static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
{
	if (vmx->vm_exit_controls_shadow != val)
		vm_exit_controls_init(vmx, val);
}

static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
{
	return vmx->vm_exit_controls_shadow;
}

static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
{
	vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
}

static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
{
	vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
}

static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
{
	vmx->segment_cache.bitmask = 0;
}

static inline u32 vmx_vmentry_ctrl(void)
{
	u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
	if (pt_mode == PT_MODE_SYSTEM)
		vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP |
				  VM_ENTRY_LOAD_IA32_RTIT_CTL);
	/* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
	return vmentry_ctrl &
		~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
}

static inline u32 vmx_vmexit_ctrl(void)
{
	u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
	if (pt_mode == PT_MODE_SYSTEM)
		vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP |
				 VM_EXIT_CLEAR_IA32_RTIT_CTL);
	/* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
	return vmexit_ctrl &
		~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
}

u32 vmx_exec_control(struct vcpu_vmx *vmx);

static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
{
	return container_of(kvm, struct kvm_vmx, kvm);
}

static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
{
	return container_of(vcpu, struct vcpu_vmx, vcpu);
}

static inline struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
{
	return &(to_vmx(vcpu)->pi_desc);
}

struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
void free_vmcs(struct vmcs *vmcs);
int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs);
void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);

static inline struct vmcs *alloc_vmcs(bool shadow)
{
	return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
			      GFP_KERNEL_ACCOUNT);
}

u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);

static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
				bool invalidate_gpa)
{
	if (enable_ept && (invalidate_gpa || !enable_vpid)) {
		if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
			return;
		ept_sync_context(construct_eptp(vcpu,
						vcpu->arch.mmu->root_hpa));
	} else {
		vpid_sync_context(vpid);
	}
}

static inline void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
{
	__vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
}

static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx)
{
	vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
	vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
}

void dump_vmcs(void);

#endif /* __KVM_X86_VMX_H */
Commit	Line	Data
8373d25d SC	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	#ifndef __KVM_X86_VMX_H
	3	#define __KVM_X86_VMX_H
	4
	5	#include <linux/kvm_host.h>
	6
	7	#include <asm/kvm.h>
f99e3daf	8	#include <asm/intel_pt.h>
8373d25d SC	9
8373d25d SC	10	#include "capabilities.h"
89b0c9f5	11	#include "ops.h"
8373d25d SC	12	#include "vmcs.h"
8373d25d SC	13
cf3646eb	14	extern const u32 vmx_msr_index[];
cf3646eb SC	15	extern u64 host_efer;
cf3646eb SC	16
8373d25d SC	17	#define MSR_TYPE_R 1
	18	#define MSR_TYPE_W 2
	19	#define MSR_TYPE_RW 3
	20
	21	#define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
	22
	23	#define NR_AUTOLOAD_MSRS 8
	24
	25	struct vmx_msrs {
	26	unsigned int nr;
	27	struct vmx_msr_entry val[NR_AUTOLOAD_MSRS];
	28	};
	29
	30	struct shared_msr_entry {
	31	unsigned index;
	32	u64 data;
	33	u64 mask;
	34	};
	35
	36	enum segment_cache_field {
	37	SEG_FIELD_SEL = 0,
	38	SEG_FIELD_BASE = 1,
	39	SEG_FIELD_LIMIT = 2,
	40	SEG_FIELD_AR = 3,
	41
	42	SEG_FIELD_NR = 4
	43	};
	44
	45	/* Posted-Interrupt Descriptor */
	46	struct pi_desc {
	47	u32 pir[8]; /* Posted interrupt requested */
	48	union {
	49	struct {
	50	/* bit 256 - Outstanding Notification */
	51	u16 on : 1,
	52	/* bit 257 - Suppress Notification */
	53	sn : 1,
	54	/* bit 271:258 - Reserved */
	55	rsvd_1 : 14;
	56	/* bit 279:272 - Notification Vector */
	57	u8 nv;
	58	/* bit 287:280 - Reserved */
	59	u8 rsvd_2;
	60	/* bit 319:288 - Notification Destination */
	61	u32 ndst;
	62	};
	63	u64 control;
	64	};
	65	u32 rsvd[6];
	66	} __aligned(64);
	67
2ef444f1 CP	68	#define RTIT_ADDR_RANGE 4
	69
	70	struct pt_ctx {
	71	u64 ctl;
	72	u64 status;
	73	u64 output_base;
	74	u64 output_mask;
	75	u64 cr3_match;
	76	u64 addr_a[RTIT_ADDR_RANGE];
	77	u64 addr_b[RTIT_ADDR_RANGE];
	78	};
	79
	80	struct pt_desc {
	81	u64 ctl_bitmask;
	82	u32 addr_range;
	83	u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
	84	struct pt_ctx host;
	85	struct pt_ctx guest;
	86	};
8373d25d SC	87
	88	/*
	89	* The nested_vmx structure is part of vcpu_vmx, and holds information we need
	90	* for correct emulation of VMX (i.e., nested VMX) on this vcpu.
	91	*/
	92	struct nested_vmx {
	93	/* Has the level1 guest done vmxon? */
	94	bool vmxon;
	95	gpa_t vmxon_ptr;
	96	bool pml_full;
	97
	98	/* The guest-physical address of the current VMCS L1 keeps for L2 */
	99	gpa_t current_vmptr;
	100	/*
	101	* Cache of the guest's VMCS, existing outside of guest memory.
	102	* Loaded from guest memory during VMPTRLD. Flushed to guest
	103	* memory during VMCLEAR and VMPTRLD.
	104	*/
	105	struct vmcs12 *cached_vmcs12;
	106	/*
	107	* Cache of the guest's shadow VMCS, existing outside of guest
	108	* memory. Loaded from guest memory during VM entry. Flushed
	109	* to guest memory during VM exit.
	110	*/
	111	struct vmcs12 *cached_shadow_vmcs12;
7952d769	112
8373d25d SC	113	/*
	114	* Indicates if the shadow vmcs or enlightened vmcs must be updated
	115	* with the data held by struct vmcs12.
	116	*/
3731905e	117	bool need_vmcs12_to_shadow_sync;
8373d25d SC	118	bool dirty_vmcs12;
8373d25d SC	119
7952d769 SC	120	/*
	121	* Indicates lazily loaded guest state has not yet been decached from
	122	* vmcs02.
	123	*/
	124	bool need_sync_vmcs02_to_vmcs12_rare;
	125
8373d25d SC	126	/*
	127	* vmcs02 has been initialized, i.e. state that is constant for
	128	* vmcs02 has been written to the backing VMCS. Initialization
	129	* is delayed until L1 actually attempts to run a nested VM.
	130	*/
	131	bool vmcs02_initialized;
	132
	133	bool change_vmcs01_virtual_apic_mode;
	134
	135	/*
	136	* Enlightened VMCS has been enabled. It does not mean that L1 has to
	137	* use it. However, VMX features available to L1 will be limited based
	138	* on what the enlightened VMCS supports.
	139	*/
	140	bool enlightened_vmcs_enabled;
	141
	142	/* L2 must run next, and mustn't decide to exit to L1. */
	143	bool nested_run_pending;
	144
	145	struct loaded_vmcs vmcs02;
	146
	147	/*
	148	* Guest pages referred to in the vmcs02 with host-physical
	149	* pointers, so we must keep them pinned while L2 runs.
	150	*/
	151	struct page *apic_access_page;
96c66e87	152	struct kvm_host_map virtual_apic_map;
3278e049	153	struct kvm_host_map pi_desc_map;
31f0b6c4 KA	154
	155	struct kvm_host_map msr_bitmap_map;
	156
8373d25d SC	157	struct pi_desc *pi_desc;
	158	bool pi_pending;
	159	u16 posted_intr_nv;
	160
	161	struct hrtimer preemption_timer;
	162	bool preemption_timer_expired;
	163
	164	/* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
	165	u64 vmcs01_debugctl;
	166	u64 vmcs01_guest_bndcfgs;
	167
	168	u16 vpid02;
	169	u16 last_vpid;
	170
	171	struct nested_vmx_msrs msrs;
	172
	173	/* SMM related state */
	174	struct {
	175	/* in VMX operation on SMM entry? */
	176	bool vmxon;
	177	/* in guest mode on SMM entry? */
	178	bool guest_mode;
	179	} smm;
	180
	181	gpa_t hv_evmcs_vmptr;
dee9c049	182	struct kvm_host_map hv_evmcs_map;
8373d25d SC	183	struct hv_enlightened_vmcs *hv_evmcs;
	184	};
	185
	186	struct vcpu_vmx {
	187	struct kvm_vcpu vcpu;
8373d25d SC	188	u8 fail;
8373d25d SC	189	u8 msr_bitmap_mode;
b464f57e PB	190
	191	/*
	192	* If true, host state has been stored in vmx->loaded_vmcs for
	193	* the CPU registers that only need to be switched when transitioning
	194	* to/from the kernel, and the registers have been loaded with guest
	195	* values. If false, host state is loaded in the CPU registers
	196	* and vmx->loaded_vmcs->host_state is invalid.
	197	*/
	198	bool guest_state_loaded;
	199
8373d25d SC	200	u32 exit_intr_info;
	201	u32 idt_vectoring_info;
	202	ulong rflags;
	203	struct shared_msr_entry *guest_msrs;
	204	int nmsrs;
	205	int save_nmsrs;
b464f57e	206	bool guest_msrs_ready;
8373d25d SC	207	#ifdef CONFIG_X86_64
	208	u64 msr_host_kernel_gs_base;
	209	u64 msr_guest_kernel_gs_base;
	210	#endif
	211
8373d25d SC	212	u64 spec_ctrl;
	213
	214	u32 vm_entry_controls_shadow;
	215	u32 vm_exit_controls_shadow;
	216	u32 secondary_exec_control;
	217
	218	/*
	219	* loaded_vmcs points to the VMCS currently used in this vcpu. For a
	220	* non-nested (L1) guest, it always points to vmcs01. For a nested
b464f57e	221	* guest (L2), it points to a different VMCS.
8373d25d SC	222	*/
	223	struct loaded_vmcs vmcs01;
	224	struct loaded_vmcs *loaded_vmcs;
c9afc58c	225
8373d25d SC	226	struct msr_autoload {
	227	struct vmx_msrs guest;
	228	struct vmx_msrs host;
	229	} msr_autoload;
	230
	231	struct {
	232	int vm86_active;
	233	ulong save_rflags;
	234	struct kvm_segment segs[8];
	235	} rmode;
	236	struct {
	237	u32 bitmask; /* 4 bits per segment (1 bit per field) */
	238	struct kvm_save_segment {
	239	u16 selector;
	240	unsigned long base;
	241	u32 limit;
	242	u32 ar;
	243	} seg[8];
	244	} segment_cache;
	245	int vpid;
	246	bool emulation_required;
	247
	248	u32 exit_reason;
	249
	250	/* Posted interrupt descriptor */
	251	struct pi_desc pi_desc;
	252
	253	/* Support for a guest hypervisor (nested VMX) */
	254	struct nested_vmx nested;
	255
	256	/* Dynamic PLE window. */
	257	int ple_window;
	258	bool ple_window_dirty;
	259
	260	bool req_immediate_exit;
	261
	262	/* Support for PML */
	263	#define PML_ENTITY_NUM 512
	264	struct page *pml_pg;
	265
	266	/* apic deadline value in host tsc */
	267	u64 hv_deadline_tsc;
	268
	269	u64 current_tsc_ratio;
	270
	271	u32 host_pkru;
	272
	273	unsigned long host_debugctlmsr;
	274
	275	/*
	276	* Only bits masked by msr_ia32_feature_control_valid_bits can be set in
	277	* msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
	278	* in msr_ia32_feature_control_valid_bits.
	279	*/
	280	u64 msr_ia32_feature_control;
	281	u64 msr_ia32_feature_control_valid_bits;
	282	u64 ept_pointer;
2ef444f1 CP	283
2ef444f1 CP	284	struct pt_desc pt_desc;
8373d25d SC	285	};
	286
	287	enum ept_pointers_status {
	288	EPT_POINTERS_CHECK = 0,
	289	EPT_POINTERS_MATCH = 1,
	290	EPT_POINTERS_MISMATCH = 2
	291	};
	292
	293	struct kvm_vmx {
	294	struct kvm kvm;
	295
	296	unsigned int tss_addr;
	297	bool ept_identity_pagetable_done;
	298	gpa_t ept_identity_map_addr;
	299
	300	enum ept_pointers_status ept_pointers_match;
	301	spinlock_t ept_pointer_lock;
	302	};
	303
7c97fcb3	304	bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
8ef863e6	305	void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu);
97b7ead3	306	void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
97b7ead3 SC	307	int allocate_vpid(void);
	308	void free_vpid(int vpid);
	309	void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
	310	void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
13b964a2 SC	311	void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
13b964a2 SC	312	unsigned long fs_base, unsigned long gs_base);
97b7ead3 SC	313	int vmx_get_cpl(struct kvm_vcpu *vcpu);
	314	unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
	315	void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
	316	u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
	317	void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
	318	void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
	319	void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
	320	void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
	321	int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
	322	void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
	323	void ept_save_pdptrs(struct kvm_vcpu *vcpu);
	324	void vmx_get_segment(struct kvm_vcpu vcpu, struct kvm_segment var, int seg);
	325	void vmx_set_segment(struct kvm_vcpu vcpu, struct kvm_segment var, int seg);
	326	u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
	327	void update_exception_bitmap(struct kvm_vcpu *vcpu);
	328	void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
	329	bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
	330	void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
	331	void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
	332	struct shared_msr_entry find_msr_entry(struct vcpu_vmx vmx, u32 msr);
b08c2896	333	void pt_update_intercept_for_msr(struct vcpu_vmx *vmx);
4d259965	334	void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
97b7ead3	335
8373d25d SC	336	#define POSTED_INTR_ON 0
	337	#define POSTED_INTR_SN 1
	338
	339	static inline bool pi_test_and_set_on(struct pi_desc *pi_desc)
	340	{
	341	return test_and_set_bit(POSTED_INTR_ON,
	342	(unsigned long *)&pi_desc->control);
	343	}
	344
	345	static inline bool pi_test_and_clear_on(struct pi_desc *pi_desc)
	346	{
	347	return test_and_clear_bit(POSTED_INTR_ON,
	348	(unsigned long *)&pi_desc->control);
	349	}
	350
	351	static inline int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
	352	{
	353	return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
	354	}
	355
81b01667	356	static inline void pi_set_sn(struct pi_desc *pi_desc)
8373d25d	357	{
81b01667 LK	358	set_bit(POSTED_INTR_SN,
81b01667 LK	359	(unsigned long *)&pi_desc->control);
8373d25d SC	360	}
8373d25d SC	361
81b01667	362	static inline void pi_set_on(struct pi_desc *pi_desc)
8373d25d	363	{
81b01667 LK	364	set_bit(POSTED_INTR_ON,
81b01667 LK	365	(unsigned long *)&pi_desc->control);
8373d25d SC	366	}
	367
	368	static inline void pi_clear_on(struct pi_desc *pi_desc)
	369	{
	370	clear_bit(POSTED_INTR_ON,
	371	(unsigned long *)&pi_desc->control);
	372	}
	373
	374	static inline int pi_test_on(struct pi_desc *pi_desc)
	375	{
	376	return test_bit(POSTED_INTR_ON,
	377	(unsigned long *)&pi_desc->control);
	378	}
	379
	380	static inline int pi_test_sn(struct pi_desc *pi_desc)
	381	{
	382	return test_bit(POSTED_INTR_SN,
	383	(unsigned long *)&pi_desc->control);
	384	}
	385
89b0c9f5 SC	386	static inline u8 vmx_get_rvi(void)
	387	{
	388	return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
	389	}
	390
	391	static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
	392	{
	393	vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
	394	}
	395
	396	static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
	397	{
	398	vmcs_write32(VM_ENTRY_CONTROLS, val);
	399	vmx->vm_entry_controls_shadow = val;
	400	}
	401
	402	static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
	403	{
	404	if (vmx->vm_entry_controls_shadow != val)
	405	vm_entry_controls_init(vmx, val);
	406	}
	407
	408	static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
	409	{
	410	return vmx->vm_entry_controls_shadow;
	411	}
	412
	413	static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
	414	{
	415	vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) \| val);
	416	}
	417
	418	static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
	419	{
	420	vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
	421	}
	422
	423	static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
	424	{
	425	vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
	426	}
	427
	428	static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
	429	{
	430	vmcs_write32(VM_EXIT_CONTROLS, val);
	431	vmx->vm_exit_controls_shadow = val;
	432	}
	433
	434	static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
	435	{
	436	if (vmx->vm_exit_controls_shadow != val)
	437	vm_exit_controls_init(vmx, val);
	438	}
	439
	440	static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
	441	{
	442	return vmx->vm_exit_controls_shadow;
	443	}
	444
	445	static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
	446	{
	447	vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) \| val);
	448	}
	449
450	static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
451	{
452	vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
453	}
454
8373d25d SC	455	static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
	456	{
	457	vmx->segment_cache.bitmask = 0;
	458	}
	459
	460	static inline u32 vmx_vmentry_ctrl(void)
	461	{
f99e3daf CP	462	u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
f99e3daf CP	463	if (pt_mode == PT_MODE_SYSTEM)
d9293597 YZ	464	vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP \|
d9293597 YZ	465	VM_ENTRY_LOAD_IA32_RTIT_CTL);
8373d25d	466	/* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
f99e3daf	467	return vmentry_ctrl &
8373d25d SC	468	~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL \| VM_ENTRY_LOAD_IA32_EFER);
	469	}
	470
	471	static inline u32 vmx_vmexit_ctrl(void)
	472	{
f99e3daf CP	473	u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
f99e3daf CP	474	if (pt_mode == PT_MODE_SYSTEM)
d9293597 YZ	475	vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP \|
d9293597 YZ	476	VM_EXIT_CLEAR_IA32_RTIT_CTL);
8373d25d	477	/* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
d9293597	478	return vmexit_ctrl &
8373d25d SC	479	~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL \| VM_EXIT_LOAD_IA32_EFER);
	480	}
	481
	482	u32 vmx_exec_control(struct vcpu_vmx *vmx);
	483
	484	static inline struct kvm_vmx to_kvm_vmx(struct kvm kvm)
	485	{
	486	return container_of(kvm, struct kvm_vmx, kvm);
	487	}
	488
	489	static inline struct vcpu_vmx to_vmx(struct kvm_vcpu vcpu)
	490	{
	491	return container_of(vcpu, struct vcpu_vmx, vcpu);
	492	}
	493
	494	static inline struct pi_desc vcpu_to_pi_desc(struct kvm_vcpu vcpu)
	495	{
	496	return &(to_vmx(vcpu)->pi_desc);
	497	}
	498
41836839	499	struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
89b0c9f5 SC	500	void free_vmcs(struct vmcs *vmcs);
	501	int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
	502	void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
	503	void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs);
	504	void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
	505
	506	static inline struct vmcs *alloc_vmcs(bool shadow)
	507	{
41836839 BG	508	return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
41836839 BG	509	GFP_KERNEL_ACCOUNT);
89b0c9f5 SC	510	}
	511
	512	u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
	513
	514	static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
	515	bool invalidate_gpa)
	516	{
	517	if (enable_ept && (invalidate_gpa \|\| !enable_vpid)) {
	518	if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
	519	return;
	520	ept_sync_context(construct_eptp(vcpu,
	521	vcpu->arch.mmu->root_hpa));
	522	} else {
	523	vpid_sync_context(vpid);
	524	}
	525	}
	526
	527	static inline void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
	528	{
	529	__vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
	530	}
	531
	532	static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx)
	533	{
	534	vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
	535	vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
	536	}
	537
69090810 PB	538	void dump_vmcs(void);
69090810 PB	539
8373d25d	540	#endif /* __KVM_X86_VMX_H */