[linux-block.git] / arch / x86 / kvm / vmx / vmx.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __KVM_X86_VMX_H
#define __KVM_X86_VMX_H

#include <linux/kvm_host.h>

#include <asm/kvm.h>

#include "capabilities.h"
#include "ops.h"
#include "vmcs.h"

extern const u32 vmx_msr_index[];
extern const ulong vmx_return;
extern u64 host_efer;

#define MSR_TYPE_R	1
#define MSR_TYPE_W	2
#define MSR_TYPE_RW	3

#define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))

#define NR_AUTOLOAD_MSRS 8

struct vmx_msrs {
	unsigned int		nr;
	struct vmx_msr_entry	val[NR_AUTOLOAD_MSRS];
};

struct shared_msr_entry {
	unsigned index;
	u64 data;
	u64 mask;
};

enum segment_cache_field {
	SEG_FIELD_SEL = 0,
	SEG_FIELD_BASE = 1,
	SEG_FIELD_LIMIT = 2,
	SEG_FIELD_AR = 3,

	SEG_FIELD_NR = 4
};

/* Posted-Interrupt Descriptor */
struct pi_desc {
	u32 pir[8];     /* Posted interrupt requested */
	union {
		struct {
				/* bit 256 - Outstanding Notification */
			u16	on	: 1,
				/* bit 257 - Suppress Notification */
				sn	: 1,
				/* bit 271:258 - Reserved */
				rsvd_1	: 14;
				/* bit 279:272 - Notification Vector */
			u8	nv;
				/* bit 287:280 - Reserved */
			u8	rsvd_2;
				/* bit 319:288 - Notification Destination */
			u32	ndst;
		};
		u64 control;
	};
	u32 rsvd[6];
} __aligned(64);


/*
 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 */
struct nested_vmx {
	/* Has the level1 guest done vmxon? */
	bool vmxon;
	gpa_t vmxon_ptr;
	bool pml_full;

	/* The guest-physical address of the current VMCS L1 keeps for L2 */
	gpa_t current_vmptr;
	/*
	 * Cache of the guest's VMCS, existing outside of guest memory.
	 * Loaded from guest memory during VMPTRLD. Flushed to guest
	 * memory during VMCLEAR and VMPTRLD.
	 */
	struct vmcs12 *cached_vmcs12;
	/*
	 * Cache of the guest's shadow VMCS, existing outside of guest
	 * memory. Loaded from guest memory during VM entry. Flushed
	 * to guest memory during VM exit.
	 */
	struct vmcs12 *cached_shadow_vmcs12;
	/*
	 * Indicates if the shadow vmcs or enlightened vmcs must be updated
	 * with the data held by struct vmcs12.
	 */
	bool need_vmcs12_sync;
	bool dirty_vmcs12;

	/*
	 * vmcs02 has been initialized, i.e. state that is constant for
	 * vmcs02 has been written to the backing VMCS.  Initialization
	 * is delayed until L1 actually attempts to run a nested VM.
	 */
	bool vmcs02_initialized;

	bool change_vmcs01_virtual_apic_mode;

	/*
	 * Enlightened VMCS has been enabled. It does not mean that L1 has to
	 * use it. However, VMX features available to L1 will be limited based
	 * on what the enlightened VMCS supports.
	 */
	bool enlightened_vmcs_enabled;

	/* L2 must run next, and mustn't decide to exit to L1. */
	bool nested_run_pending;

	struct loaded_vmcs vmcs02;

	/*
	 * Guest pages referred to in the vmcs02 with host-physical
	 * pointers, so we must keep them pinned while L2 runs.
	 */
	struct page *apic_access_page;
	struct page *virtual_apic_page;
	struct page *pi_desc_page;
	struct pi_desc *pi_desc;
	bool pi_pending;
	u16 posted_intr_nv;

	struct hrtimer preemption_timer;
	bool preemption_timer_expired;

	/* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
	u64 vmcs01_debugctl;
	u64 vmcs01_guest_bndcfgs;

	u16 vpid02;
	u16 last_vpid;

	struct nested_vmx_msrs msrs;

	/* SMM related state */
	struct {
		/* in VMX operation on SMM entry? */
		bool vmxon;
		/* in guest mode on SMM entry? */
		bool guest_mode;
	} smm;

	gpa_t hv_evmcs_vmptr;
	struct page *hv_evmcs_page;
	struct hv_enlightened_vmcs *hv_evmcs;
};

struct vcpu_vmx {
	struct kvm_vcpu       vcpu;
	unsigned long         host_rsp;
	u8                    fail;
	u8		      msr_bitmap_mode;
	u32                   exit_intr_info;
	u32                   idt_vectoring_info;
	ulong                 rflags;
	struct shared_msr_entry *guest_msrs;
	int                   nmsrs;
	int                   save_nmsrs;
	bool                  guest_msrs_dirty;
	unsigned long	      host_idt_base;
#ifdef CONFIG_X86_64
	u64		      msr_host_kernel_gs_base;
	u64		      msr_guest_kernel_gs_base;
#endif

	u64		      arch_capabilities;
	u64		      spec_ctrl;

	u32 vm_entry_controls_shadow;
	u32 vm_exit_controls_shadow;
	u32 secondary_exec_control;

	/*
	 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
	 * non-nested (L1) guest, it always points to vmcs01. For a nested
	 * guest (L2), it points to a different VMCS.  loaded_cpu_state points
	 * to the VMCS whose state is loaded into the CPU registers that only
	 * need to be switched when transitioning to/from the kernel; a NULL
	 * value indicates that host state is loaded.
	 */
	struct loaded_vmcs    vmcs01;
	struct loaded_vmcs   *loaded_vmcs;
	struct loaded_vmcs   *loaded_cpu_state;
	bool                  __launched; /* temporary, used in vmx_vcpu_run */
	struct msr_autoload {
		struct vmx_msrs guest;
		struct vmx_msrs host;
	} msr_autoload;

	struct {
		int vm86_active;
		ulong save_rflags;
		struct kvm_segment segs[8];
	} rmode;
	struct {
		u32 bitmask; /* 4 bits per segment (1 bit per field) */
		struct kvm_save_segment {
			u16 selector;
			unsigned long base;
			u32 limit;
			u32 ar;
		} seg[8];
	} segment_cache;
	int vpid;
	bool emulation_required;

	u32 exit_reason;

	/* Posted interrupt descriptor */
	struct pi_desc pi_desc;

	/* Support for a guest hypervisor (nested VMX) */
	struct nested_vmx nested;

	/* Dynamic PLE window. */
	int ple_window;
	bool ple_window_dirty;

	bool req_immediate_exit;

	/* Support for PML */
#define PML_ENTITY_NUM		512
	struct page *pml_pg;

	/* apic deadline value in host tsc */
	u64 hv_deadline_tsc;

	u64 current_tsc_ratio;

	u32 host_pkru;

	unsigned long host_debugctlmsr;

	/*
	 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
	 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
	 * in msr_ia32_feature_control_valid_bits.
	 */
	u64 msr_ia32_feature_control;
	u64 msr_ia32_feature_control_valid_bits;
	u64 ept_pointer;
};

enum ept_pointers_status {
	EPT_POINTERS_CHECK = 0,
	EPT_POINTERS_MATCH = 1,
	EPT_POINTERS_MISMATCH = 2
};

struct kvm_vmx {
	struct kvm kvm;

	unsigned int tss_addr;
	bool ept_identity_pagetable_done;
	gpa_t ept_identity_map_addr;

	enum ept_pointers_status ept_pointers_match;
	spinlock_t ept_pointer_lock;
};

void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
void vmx_vcpu_put(struct kvm_vcpu *vcpu);
int allocate_vpid(void);
void free_vpid(int vpid);
void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
int vmx_get_cpl(struct kvm_vcpu *vcpu);
unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
void ept_save_pdptrs(struct kvm_vcpu *vcpu);
void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
void update_exception_bitmap(struct kvm_vcpu *vcpu);
void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr);

#define POSTED_INTR_ON  0
#define POSTED_INTR_SN  1

static inline bool pi_test_and_set_on(struct pi_desc *pi_desc)
{
	return test_and_set_bit(POSTED_INTR_ON,
			(unsigned long *)&pi_desc->control);
}

static inline bool pi_test_and_clear_on(struct pi_desc *pi_desc)
{
	return test_and_clear_bit(POSTED_INTR_ON,
			(unsigned long *)&pi_desc->control);
}

static inline int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
{
	return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
}

static inline void pi_clear_sn(struct pi_desc *pi_desc)
{
	return clear_bit(POSTED_INTR_SN,
			(unsigned long *)&pi_desc->control);
}

static inline void pi_set_sn(struct pi_desc *pi_desc)
{
	return set_bit(POSTED_INTR_SN,
			(unsigned long *)&pi_desc->control);
}

static inline void pi_clear_on(struct pi_desc *pi_desc)
{
	clear_bit(POSTED_INTR_ON,
		(unsigned long *)&pi_desc->control);
}

static inline int pi_test_on(struct pi_desc *pi_desc)
{
	return test_bit(POSTED_INTR_ON,
			(unsigned long *)&pi_desc->control);
}

static inline int pi_test_sn(struct pi_desc *pi_desc)
{
	return test_bit(POSTED_INTR_SN,
			(unsigned long *)&pi_desc->control);
}

static inline u8 vmx_get_rvi(void)
{
	return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
}

static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
{
	vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
}

static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
{
	vmcs_write32(VM_ENTRY_CONTROLS, val);
	vmx->vm_entry_controls_shadow = val;
}

static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
{
	if (vmx->vm_entry_controls_shadow != val)
		vm_entry_controls_init(vmx, val);
}

static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
{
	return vmx->vm_entry_controls_shadow;
}

static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
{
	vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
}

static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
{
	vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
}

static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
{
	vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
}

static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
{
	vmcs_write32(VM_EXIT_CONTROLS, val);
	vmx->vm_exit_controls_shadow = val;
}

static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
{
	if (vmx->vm_exit_controls_shadow != val)
		vm_exit_controls_init(vmx, val);
}

static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
{
	return vmx->vm_exit_controls_shadow;
}

static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
{
	vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
}

static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
{
	vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
}

static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
{
	vmx->segment_cache.bitmask = 0;
}

static inline u32 vmx_vmentry_ctrl(void)
{
	/* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
	return vmcs_config.vmentry_ctrl &
		~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
}

static inline u32 vmx_vmexit_ctrl(void)
{
	/* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
	return vmcs_config.vmexit_ctrl &
		~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
}

u32 vmx_exec_control(struct vcpu_vmx *vmx);

static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
{
	return container_of(kvm, struct kvm_vmx, kvm);
}

static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
{
	return container_of(vcpu, struct vcpu_vmx, vcpu);
}

static inline struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
{
	return &(to_vmx(vcpu)->pi_desc);
}

struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu);
void free_vmcs(struct vmcs *vmcs);
int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs);
void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);

static inline struct vmcs *alloc_vmcs(bool shadow)
{
	return alloc_vmcs_cpu(shadow, raw_smp_processor_id());
}

u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);

static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
				bool invalidate_gpa)
{
	if (enable_ept && (invalidate_gpa || !enable_vpid)) {
		if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
			return;
		ept_sync_context(construct_eptp(vcpu,
						vcpu->arch.mmu->root_hpa));
	} else {
		vpid_sync_context(vpid);
	}
}

static inline void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
{
	__vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
}

static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx)
{
	vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
	vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
}

#endif /* __KVM_X86_VMX_H */
Commit	Line	Data
8373d25d SC	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	#ifndef __KVM_X86_VMX_H
	3	#define __KVM_X86_VMX_H
	4
	5	#include <linux/kvm_host.h>
	6
	7	#include <asm/kvm.h>
	8
	9	#include "capabilities.h"
89b0c9f5	10	#include "ops.h"
8373d25d SC	11	#include "vmcs.h"
8373d25d SC	12
cf3646eb SC	13	extern const u32 vmx_msr_index[];
	14	extern const ulong vmx_return;
	15	extern u64 host_efer;
	16
8373d25d SC	17	#define MSR_TYPE_R 1
	18	#define MSR_TYPE_W 2
	19	#define MSR_TYPE_RW 3
	20
	21	#define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
	22
	23	#define NR_AUTOLOAD_MSRS 8
	24
	25	struct vmx_msrs {
	26	unsigned int nr;
	27	struct vmx_msr_entry val[NR_AUTOLOAD_MSRS];
	28	};
	29
	30	struct shared_msr_entry {
	31	unsigned index;
	32	u64 data;
	33	u64 mask;
	34	};
	35
	36	enum segment_cache_field {
	37	SEG_FIELD_SEL = 0,
	38	SEG_FIELD_BASE = 1,
	39	SEG_FIELD_LIMIT = 2,
	40	SEG_FIELD_AR = 3,
	41
	42	SEG_FIELD_NR = 4
	43	};
	44
	45	/* Posted-Interrupt Descriptor */
	46	struct pi_desc {
	47	u32 pir[8]; /* Posted interrupt requested */
	48	union {
	49	struct {
	50	/* bit 256 - Outstanding Notification */
	51	u16 on : 1,
	52	/* bit 257 - Suppress Notification */
	53	sn : 1,
	54	/* bit 271:258 - Reserved */
	55	rsvd_1 : 14;
	56	/* bit 279:272 - Notification Vector */
	57	u8 nv;
	58	/* bit 287:280 - Reserved */
	59	u8 rsvd_2;
	60	/* bit 319:288 - Notification Destination */
	61	u32 ndst;
	62	};
	63	u64 control;
	64	};
	65	u32 rsvd[6];
	66	} __aligned(64);
	67
	68
	69	/*
	70	* The nested_vmx structure is part of vcpu_vmx, and holds information we need
	71	* for correct emulation of VMX (i.e., nested VMX) on this vcpu.
	72	*/
	73	struct nested_vmx {
	74	/* Has the level1 guest done vmxon? */
	75	bool vmxon;
	76	gpa_t vmxon_ptr;
	77	bool pml_full;
	78
	79	/* The guest-physical address of the current VMCS L1 keeps for L2 */
	80	gpa_t current_vmptr;
81	/*
82	* Cache of the guest's VMCS, existing outside of guest memory.
83	* Loaded from guest memory during VMPTRLD. Flushed to guest
84	* memory during VMCLEAR and VMPTRLD.
85	*/
86	struct vmcs12 *cached_vmcs12;
87	/*
88	* Cache of the guest's shadow VMCS, existing outside of guest
89	* memory. Loaded from guest memory during VM entry. Flushed
90	* to guest memory during VM exit.
91	*/
92	struct vmcs12 *cached_shadow_vmcs12;
93	/*
94	* Indicates if the shadow vmcs or enlightened vmcs must be updated
95	* with the data held by struct vmcs12.
96	*/
97	bool need_vmcs12_sync;
98	bool dirty_vmcs12;
99
100	/*
101	* vmcs02 has been initialized, i.e. state that is constant for
102	* vmcs02 has been written to the backing VMCS. Initialization
103	* is delayed until L1 actually attempts to run a nested VM.
104	*/
105	bool vmcs02_initialized;
106
107	bool change_vmcs01_virtual_apic_mode;
108
109	/*
110	* Enlightened VMCS has been enabled. It does not mean that L1 has to
111	* use it. However, VMX features available to L1 will be limited based
112	* on what the enlightened VMCS supports.
113	*/
114	bool enlightened_vmcs_enabled;
115
116	/* L2 must run next, and mustn't decide to exit to L1. */
117	bool nested_run_pending;
118
119	struct loaded_vmcs vmcs02;
120
121	/*
122	* Guest pages referred to in the vmcs02 with host-physical
123	* pointers, so we must keep them pinned while L2 runs.
124	*/
125	struct page *apic_access_page;
126	struct page *virtual_apic_page;
127	struct page *pi_desc_page;
128	struct pi_desc *pi_desc;
129	bool pi_pending;
130	u16 posted_intr_nv;
131
132	struct hrtimer preemption_timer;
133	bool preemption_timer_expired;
134
135	/* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
136	u64 vmcs01_debugctl;
137	u64 vmcs01_guest_bndcfgs;
138
139	u16 vpid02;
140	u16 last_vpid;
141
142	struct nested_vmx_msrs msrs;
143
144	/* SMM related state */
145	struct {
146	/* in VMX operation on SMM entry? */
147	bool vmxon;
148	/* in guest mode on SMM entry? */
149	bool guest_mode;
150	} smm;
151
152	gpa_t hv_evmcs_vmptr;
153	struct page *hv_evmcs_page;
154	struct hv_enlightened_vmcs *hv_evmcs;
155	};
156
157	struct vcpu_vmx {
158	struct kvm_vcpu vcpu;
159	unsigned long host_rsp;
160	u8 fail;
161	u8 msr_bitmap_mode;
162	u32 exit_intr_info;
163	u32 idt_vectoring_info;
164	ulong rflags;
165	struct shared_msr_entry *guest_msrs;
166	int nmsrs;
167	int save_nmsrs;
168	bool guest_msrs_dirty;
169	unsigned long host_idt_base;
170	#ifdef CONFIG_X86_64
171	u64 msr_host_kernel_gs_base;
172	u64 msr_guest_kernel_gs_base;
173	#endif
174
175	u64 arch_capabilities;
176	u64 spec_ctrl;
177
178	u32 vm_entry_controls_shadow;
179	u32 vm_exit_controls_shadow;
180	u32 secondary_exec_control;
181
182	/*
183	* loaded_vmcs points to the VMCS currently used in this vcpu. For a
184	* non-nested (L1) guest, it always points to vmcs01. For a nested
185	* guest (L2), it points to a different VMCS. loaded_cpu_state points
186	* to the VMCS whose state is loaded into the CPU registers that only
187	* need to be switched when transitioning to/from the kernel; a NULL
188	* value indicates that host state is loaded.
189	*/
190	struct loaded_vmcs vmcs01;
191	struct loaded_vmcs *loaded_vmcs;
192	struct loaded_vmcs *loaded_cpu_state;
193	bool __launched; /* temporary, used in vmx_vcpu_run */
194	struct msr_autoload {
195	struct vmx_msrs guest;
196	struct vmx_msrs host;
197	} msr_autoload;
198
199	struct {
200	int vm86_active;
201	ulong save_rflags;
202	struct kvm_segment segs[8];
203	} rmode;
204	struct {
205	u32 bitmask; /* 4 bits per segment (1 bit per field) */
206	struct kvm_save_segment {
207	u16 selector;
208	unsigned long base;
209	u32 limit;
210	u32 ar;
211	} seg[8];
212	} segment_cache;
213	int vpid;
214	bool emulation_required;
215
216	u32 exit_reason;
217
218	/* Posted interrupt descriptor */
219	struct pi_desc pi_desc;
220
221	/* Support for a guest hypervisor (nested VMX) */
222	struct nested_vmx nested;
223
224	/* Dynamic PLE window. */
225	int ple_window;
226	bool ple_window_dirty;
227
228	bool req_immediate_exit;
229
230	/* Support for PML */
231	#define PML_ENTITY_NUM 512
232	struct page *pml_pg;
233
234	/* apic deadline value in host tsc */
235	u64 hv_deadline_tsc;
236
237	u64 current_tsc_ratio;
238
239	u32 host_pkru;
240
241	unsigned long host_debugctlmsr;
242
243	/*
244	* Only bits masked by msr_ia32_feature_control_valid_bits can be set in
245	* msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
246	* in msr_ia32_feature_control_valid_bits.
247	*/
248	u64 msr_ia32_feature_control;
249	u64 msr_ia32_feature_control_valid_bits;
250	u64 ept_pointer;
251	};
252
253	enum ept_pointers_status {
254	EPT_POINTERS_CHECK = 0,
255	EPT_POINTERS_MATCH = 1,
256	EPT_POINTERS_MISMATCH = 2
257	};
258
259	struct kvm_vmx {
260	struct kvm kvm;
261
262	unsigned int tss_addr;
263	bool ept_identity_pagetable_done;
264	gpa_t ept_identity_map_addr;
265
266	enum ept_pointers_status ept_pointers_match;
267	spinlock_t ept_pointer_lock;
268	};
269
97b7ead3 SC	270	void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
	271	void vmx_vcpu_put(struct kvm_vcpu *vcpu);
	272	int allocate_vpid(void);
	273	void free_vpid(int vpid);
	274	void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
	275	void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
	276	int vmx_get_cpl(struct kvm_vcpu *vcpu);
	277	unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
	278	void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
	279	u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
	280	void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
	281	void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
	282	void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
	283	void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
	284	int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
	285	void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
	286	void ept_save_pdptrs(struct kvm_vcpu *vcpu);
	287	void vmx_get_segment(struct kvm_vcpu vcpu, struct kvm_segment var, int seg);
	288	void vmx_set_segment(struct kvm_vcpu vcpu, struct kvm_segment var, int seg);
	289	u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
	290	void update_exception_bitmap(struct kvm_vcpu *vcpu);
	291	void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
	292	bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
	293	void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
	294	void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
	295	struct shared_msr_entry find_msr_entry(struct vcpu_vmx vmx, u32 msr);
	296
8373d25d SC	297	#define POSTED_INTR_ON 0
	298	#define POSTED_INTR_SN 1
	299
	300	static inline bool pi_test_and_set_on(struct pi_desc *pi_desc)
	301	{
	302	return test_and_set_bit(POSTED_INTR_ON,
	303	(unsigned long *)&pi_desc->control);
	304	}
	305
	306	static inline bool pi_test_and_clear_on(struct pi_desc *pi_desc)
	307	{
	308	return test_and_clear_bit(POSTED_INTR_ON,
	309	(unsigned long *)&pi_desc->control);
	310	}
	311
	312	static inline int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
	313	{
	314	return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
	315	}
	316
	317	static inline void pi_clear_sn(struct pi_desc *pi_desc)
	318	{
	319	return clear_bit(POSTED_INTR_SN,
	320	(unsigned long *)&pi_desc->control);
	321	}
	322
	323	static inline void pi_set_sn(struct pi_desc *pi_desc)
	324	{
	325	return set_bit(POSTED_INTR_SN,
	326	(unsigned long *)&pi_desc->control);
	327	}
	328
	329	static inline void pi_clear_on(struct pi_desc *pi_desc)
	330	{
	331	clear_bit(POSTED_INTR_ON,
	332	(unsigned long *)&pi_desc->control);
	333	}
	334
	335	static inline int pi_test_on(struct pi_desc *pi_desc)
	336	{
	337	return test_bit(POSTED_INTR_ON,
	338	(unsigned long *)&pi_desc->control);
	339	}
	340
	341	static inline int pi_test_sn(struct pi_desc *pi_desc)
	342	{
	343	return test_bit(POSTED_INTR_SN,
	344	(unsigned long *)&pi_desc->control);
	345	}
	346
89b0c9f5 SC	347	static inline u8 vmx_get_rvi(void)
	348	{
	349	return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
	350	}
	351
	352	static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
	353	{
	354	vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
	355	}
	356
	357	static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
	358	{
	359	vmcs_write32(VM_ENTRY_CONTROLS, val);
	360	vmx->vm_entry_controls_shadow = val;
	361	}
	362
	363	static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
	364	{
	365	if (vmx->vm_entry_controls_shadow != val)
	366	vm_entry_controls_init(vmx, val);
	367	}
	368
	369	static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
	370	{
	371	return vmx->vm_entry_controls_shadow;
	372	}
	373
	374	static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
	375	{
	376	vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) \| val);
	377	}
	378
	379	static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
	380	{
	381	vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
	382	}
	383
	384	static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
	385	{
	386	vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
	387	}
	388
	389	static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
	390	{
	391	vmcs_write32(VM_EXIT_CONTROLS, val);
	392	vmx->vm_exit_controls_shadow = val;
	393	}
	394
	395	static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
	396	{
	397	if (vmx->vm_exit_controls_shadow != val)
	398	vm_exit_controls_init(vmx, val);
	399	}
	400
	401	static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
	402	{
	403	return vmx->vm_exit_controls_shadow;
	404	}
	405
	406	static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
	407	{
	408	vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) \| val);
	409	}
	410
411	static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
412	{
413	vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
414	}
415
8373d25d SC	416	static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
	417	{
	418	vmx->segment_cache.bitmask = 0;
	419	}
	420
	421	static inline u32 vmx_vmentry_ctrl(void)
	422	{
	423	/* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
	424	return vmcs_config.vmentry_ctrl &
	425	~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL \| VM_ENTRY_LOAD_IA32_EFER);
	426	}
	427
	428	static inline u32 vmx_vmexit_ctrl(void)
	429	{
	430	/* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
	431	return vmcs_config.vmexit_ctrl &
	432	~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL \| VM_EXIT_LOAD_IA32_EFER);
	433	}
	434
	435	u32 vmx_exec_control(struct vcpu_vmx *vmx);
	436
	437	static inline struct kvm_vmx to_kvm_vmx(struct kvm kvm)
	438	{
	439	return container_of(kvm, struct kvm_vmx, kvm);
	440	}
	441
	442	static inline struct vcpu_vmx to_vmx(struct kvm_vcpu vcpu)
	443	{
	444	return container_of(vcpu, struct vcpu_vmx, vcpu);
	445	}
	446
	447	static inline struct pi_desc vcpu_to_pi_desc(struct kvm_vcpu vcpu)
	448	{
	449	return &(to_vmx(vcpu)->pi_desc);
	450	}
	451
89b0c9f5 SC	452	struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu);
	453	void free_vmcs(struct vmcs *vmcs);
	454	int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
	455	void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
	456	void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs);
	457	void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
	458
	459	static inline struct vmcs *alloc_vmcs(bool shadow)
	460	{
	461	return alloc_vmcs_cpu(shadow, raw_smp_processor_id());
	462	}
	463
	464	u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
	465
	466	static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
	467	bool invalidate_gpa)
	468	{
	469	if (enable_ept && (invalidate_gpa \|\| !enable_vpid)) {
	470	if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
	471	return;
	472	ept_sync_context(construct_eptp(vcpu,
	473	vcpu->arch.mmu->root_hpa));
	474	} else {
	475	vpid_sync_context(vpid);
	476	}
	477	}
	478
	479	static inline void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
	480	{
	481	__vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
	482	}
	483
	484	static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx)
	485	{
	486	vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
	487	vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
	488	}
	489
8373d25d	490	#endif /* __KVM_X86_VMX_H */