[linux-block.git] / arch / x86 / kvm / vmx / vmx.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __KVM_X86_VMX_H
#define __KVM_X86_VMX_H

#include <linux/kvm_host.h>

#include <asm/kvm.h>
#include <asm/intel_pt.h>

#include "capabilities.h"
#include "ops.h"
#include "vmcs.h"

extern const u32 vmx_msr_index[];
extern u64 host_efer;

#define MSR_TYPE_R	1
#define MSR_TYPE_W	2
#define MSR_TYPE_RW	3

#define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))

#define NR_AUTOLOAD_MSRS 8

struct vmx_msrs {
	unsigned int		nr;
	struct vmx_msr_entry	val[NR_AUTOLOAD_MSRS];
};

struct shared_msr_entry {
	unsigned index;
	u64 data;
	u64 mask;
};

enum segment_cache_field {
	SEG_FIELD_SEL = 0,
	SEG_FIELD_BASE = 1,
	SEG_FIELD_LIMIT = 2,
	SEG_FIELD_AR = 3,

	SEG_FIELD_NR = 4
};

/* Posted-Interrupt Descriptor */
struct pi_desc {
	u32 pir[8];     /* Posted interrupt requested */
	union {
		struct {
				/* bit 256 - Outstanding Notification */
			u16	on	: 1,
				/* bit 257 - Suppress Notification */
				sn	: 1,
				/* bit 271:258 - Reserved */
				rsvd_1	: 14;
				/* bit 279:272 - Notification Vector */
			u8	nv;
				/* bit 287:280 - Reserved */
			u8	rsvd_2;
				/* bit 319:288 - Notification Destination */
			u32	ndst;
		};
		u64 control;
	};
	u32 rsvd[6];
} __aligned(64);

#define RTIT_ADDR_RANGE		4

struct pt_ctx {
	u64 ctl;
	u64 status;
	u64 output_base;
	u64 output_mask;
	u64 cr3_match;
	u64 addr_a[RTIT_ADDR_RANGE];
	u64 addr_b[RTIT_ADDR_RANGE];
};

struct pt_desc {
	u64 ctl_bitmask;
	u32 addr_range;
	u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
	struct pt_ctx host;
	struct pt_ctx guest;
};

/*
 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 */
struct nested_vmx {
	/* Has the level1 guest done vmxon? */
	bool vmxon;
	gpa_t vmxon_ptr;
	bool pml_full;

	/* The guest-physical address of the current VMCS L1 keeps for L2 */
	gpa_t current_vmptr;
	/*
	 * Cache of the guest's VMCS, existing outside of guest memory.
	 * Loaded from guest memory during VMPTRLD. Flushed to guest
	 * memory during VMCLEAR and VMPTRLD.
	 */
	struct vmcs12 *cached_vmcs12;
	/*
	 * Cache of the guest's shadow VMCS, existing outside of guest
	 * memory. Loaded from guest memory during VM entry. Flushed
	 * to guest memory during VM exit.
	 */
	struct vmcs12 *cached_shadow_vmcs12;
	/*
	 * Indicates if the shadow vmcs or enlightened vmcs must be updated
	 * with the data held by struct vmcs12.
	 */
	bool need_vmcs12_sync;
	bool dirty_vmcs12;

	/*
	 * vmcs02 has been initialized, i.e. state that is constant for
	 * vmcs02 has been written to the backing VMCS.  Initialization
	 * is delayed until L1 actually attempts to run a nested VM.
	 */
	bool vmcs02_initialized;

	bool change_vmcs01_virtual_apic_mode;

	/*
	 * Enlightened VMCS has been enabled. It does not mean that L1 has to
	 * use it. However, VMX features available to L1 will be limited based
	 * on what the enlightened VMCS supports.
	 */
	bool enlightened_vmcs_enabled;

	/* L2 must run next, and mustn't decide to exit to L1. */
	bool nested_run_pending;

	struct loaded_vmcs vmcs02;

	/*
	 * Guest pages referred to in the vmcs02 with host-physical
	 * pointers, so we must keep them pinned while L2 runs.
	 */
	struct page *apic_access_page;
	struct kvm_host_map virtual_apic_map;
	struct kvm_host_map pi_desc_map;

	struct kvm_host_map msr_bitmap_map;

	struct pi_desc *pi_desc;
	bool pi_pending;
	u16 posted_intr_nv;

	struct hrtimer preemption_timer;
	bool preemption_timer_expired;

	/* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
	u64 vmcs01_debugctl;
	u64 vmcs01_guest_bndcfgs;

	u16 vpid02;
	u16 last_vpid;

	struct nested_vmx_msrs msrs;

	/* SMM related state */
	struct {
		/* in VMX operation on SMM entry? */
		bool vmxon;
		/* in guest mode on SMM entry? */
		bool guest_mode;
	} smm;

	gpa_t hv_evmcs_vmptr;
	struct kvm_host_map hv_evmcs_map;
	struct hv_enlightened_vmcs *hv_evmcs;
};

struct vcpu_vmx {
	struct kvm_vcpu       vcpu;
	u8                    fail;
	u8		      msr_bitmap_mode;
	u32                   exit_intr_info;
	u32                   idt_vectoring_info;
	ulong                 rflags;
	struct shared_msr_entry *guest_msrs;
	int                   nmsrs;
	int                   save_nmsrs;
	bool                  guest_msrs_dirty;
	unsigned long	      host_idt_base;
#ifdef CONFIG_X86_64
	u64		      msr_host_kernel_gs_base;
	u64		      msr_guest_kernel_gs_base;
#endif

	u64		      spec_ctrl;

	u32 vm_entry_controls_shadow;
	u32 vm_exit_controls_shadow;
	u32 secondary_exec_control;

	/*
	 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
	 * non-nested (L1) guest, it always points to vmcs01. For a nested
	 * guest (L2), it points to a different VMCS.  loaded_cpu_state points
	 * to the VMCS whose state is loaded into the CPU registers that only
	 * need to be switched when transitioning to/from the kernel; a NULL
	 * value indicates that host state is loaded.
	 */
	struct loaded_vmcs    vmcs01;
	struct loaded_vmcs   *loaded_vmcs;
	struct loaded_vmcs   *loaded_cpu_state;

	struct msr_autoload {
		struct vmx_msrs guest;
		struct vmx_msrs host;
	} msr_autoload;

	struct {
		int vm86_active;
		ulong save_rflags;
		struct kvm_segment segs[8];
	} rmode;
	struct {
		u32 bitmask; /* 4 bits per segment (1 bit per field) */
		struct kvm_save_segment {
			u16 selector;
			unsigned long base;
			u32 limit;
			u32 ar;
		} seg[8];
	} segment_cache;
	int vpid;
	bool emulation_required;

	u32 exit_reason;

	/* Posted interrupt descriptor */
	struct pi_desc pi_desc;

	/* Support for a guest hypervisor (nested VMX) */
	struct nested_vmx nested;

	/* Dynamic PLE window. */
	int ple_window;
	bool ple_window_dirty;

	bool req_immediate_exit;

	/* Support for PML */
#define PML_ENTITY_NUM		512
	struct page *pml_pg;

	/* apic deadline value in host tsc */
	u64 hv_deadline_tsc;

	u64 current_tsc_ratio;

	u32 host_pkru;

	unsigned long host_debugctlmsr;

	u64 msr_ia32_power_ctl;

	/*
	 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
	 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
	 * in msr_ia32_feature_control_valid_bits.
	 */
	u64 msr_ia32_feature_control;
	u64 msr_ia32_feature_control_valid_bits;
	u64 ept_pointer;

	struct pt_desc pt_desc;
};

enum ept_pointers_status {
	EPT_POINTERS_CHECK = 0,
	EPT_POINTERS_MATCH = 1,
	EPT_POINTERS_MISMATCH = 2
};

struct kvm_vmx {
	struct kvm kvm;

	unsigned int tss_addr;
	bool ept_identity_pagetable_done;
	gpa_t ept_identity_map_addr;

	enum ept_pointers_status ept_pointers_match;
	spinlock_t ept_pointer_lock;
};

bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
void vmx_vcpu_put(struct kvm_vcpu *vcpu);
int allocate_vpid(void);
void free_vpid(int vpid);
void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
int vmx_get_cpl(struct kvm_vcpu *vcpu);
unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
void ept_save_pdptrs(struct kvm_vcpu *vcpu);
void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
void update_exception_bitmap(struct kvm_vcpu *vcpu);
void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr);
void pt_update_intercept_for_msr(struct vcpu_vmx *vmx);

#define POSTED_INTR_ON  0
#define POSTED_INTR_SN  1

static inline bool pi_test_and_set_on(struct pi_desc *pi_desc)
{
	return test_and_set_bit(POSTED_INTR_ON,
			(unsigned long *)&pi_desc->control);
}

static inline bool pi_test_and_clear_on(struct pi_desc *pi_desc)
{
	return test_and_clear_bit(POSTED_INTR_ON,
			(unsigned long *)&pi_desc->control);
}

static inline int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
{
	return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
}

static inline void pi_set_sn(struct pi_desc *pi_desc)
{
	set_bit(POSTED_INTR_SN,
		(unsigned long *)&pi_desc->control);
}

static inline void pi_set_on(struct pi_desc *pi_desc)
{
	set_bit(POSTED_INTR_ON,
		(unsigned long *)&pi_desc->control);
}

static inline void pi_clear_on(struct pi_desc *pi_desc)
{
	clear_bit(POSTED_INTR_ON,
		(unsigned long *)&pi_desc->control);
}

static inline int pi_test_on(struct pi_desc *pi_desc)
{
	return test_bit(POSTED_INTR_ON,
			(unsigned long *)&pi_desc->control);
}

static inline int pi_test_sn(struct pi_desc *pi_desc)
{
	return test_bit(POSTED_INTR_SN,
			(unsigned long *)&pi_desc->control);
}

static inline u8 vmx_get_rvi(void)
{
	return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
}

static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
{
	vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
}

static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
{
	vmcs_write32(VM_ENTRY_CONTROLS, val);
	vmx->vm_entry_controls_shadow = val;
}

static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
{
	if (vmx->vm_entry_controls_shadow != val)
		vm_entry_controls_init(vmx, val);
}

static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
{
	return vmx->vm_entry_controls_shadow;
}

static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
{
	vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
}

static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
{
	vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
}

static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
{
	vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
}

static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
{
	vmcs_write32(VM_EXIT_CONTROLS, val);
	vmx->vm_exit_controls_shadow = val;
}

static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
{
	if (vmx->vm_exit_controls_shadow != val)
		vm_exit_controls_init(vmx, val);
}

static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
{
	return vmx->vm_exit_controls_shadow;
}

static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
{
	vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
}

static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
{
	vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
}

static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
{
	vmx->segment_cache.bitmask = 0;
}

static inline u32 vmx_vmentry_ctrl(void)
{
	u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
	if (pt_mode == PT_MODE_SYSTEM)
		vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP |
				  VM_ENTRY_LOAD_IA32_RTIT_CTL);
	/* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
	return vmentry_ctrl &
		~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
}

static inline u32 vmx_vmexit_ctrl(void)
{
	u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
	if (pt_mode == PT_MODE_SYSTEM)
		vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP |
				 VM_EXIT_CLEAR_IA32_RTIT_CTL);
	/* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
	return vmexit_ctrl &
		~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
}

u32 vmx_exec_control(struct vcpu_vmx *vmx);

static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
{
	return container_of(kvm, struct kvm_vmx, kvm);
}

static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
{
	return container_of(vcpu, struct vcpu_vmx, vcpu);
}

static inline struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
{
	return &(to_vmx(vcpu)->pi_desc);
}

struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
void free_vmcs(struct vmcs *vmcs);
int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs);
void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);

static inline struct vmcs *alloc_vmcs(bool shadow)
{
	return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
			      GFP_KERNEL_ACCOUNT);
}

u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);

static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
				bool invalidate_gpa)
{
	if (enable_ept && (invalidate_gpa || !enable_vpid)) {
		if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
			return;
		ept_sync_context(construct_eptp(vcpu,
						vcpu->arch.mmu->root_hpa));
	} else {
		vpid_sync_context(vpid);
	}
}

static inline void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
{
	__vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
}

static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx)
{
	vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
	vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
}

void dump_vmcs(void);

#endif /* __KVM_X86_VMX_H */
Commit	Line	Data
8373d25d SC	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	#ifndef __KVM_X86_VMX_H
	3	#define __KVM_X86_VMX_H
	4
	5	#include <linux/kvm_host.h>
	6
	7	#include <asm/kvm.h>
f99e3daf	8	#include <asm/intel_pt.h>
8373d25d SC	9
8373d25d SC	10	#include "capabilities.h"
89b0c9f5	11	#include "ops.h"
8373d25d SC	12	#include "vmcs.h"
8373d25d SC	13
cf3646eb	14	extern const u32 vmx_msr_index[];
cf3646eb SC	15	extern u64 host_efer;
cf3646eb SC	16
8373d25d SC	17	#define MSR_TYPE_R 1
	18	#define MSR_TYPE_W 2
	19	#define MSR_TYPE_RW 3
	20
	21	#define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
	22
	23	#define NR_AUTOLOAD_MSRS 8
	24
	25	struct vmx_msrs {
	26	unsigned int nr;
	27	struct vmx_msr_entry val[NR_AUTOLOAD_MSRS];
	28	};
	29
	30	struct shared_msr_entry {
	31	unsigned index;
	32	u64 data;
	33	u64 mask;
	34	};
	35
	36	enum segment_cache_field {
	37	SEG_FIELD_SEL = 0,
	38	SEG_FIELD_BASE = 1,
	39	SEG_FIELD_LIMIT = 2,
	40	SEG_FIELD_AR = 3,
	41
	42	SEG_FIELD_NR = 4
	43	};
	44
	45	/* Posted-Interrupt Descriptor */
	46	struct pi_desc {
	47	u32 pir[8]; /* Posted interrupt requested */
	48	union {
	49	struct {
	50	/* bit 256 - Outstanding Notification */
	51	u16 on : 1,
	52	/* bit 257 - Suppress Notification */
	53	sn : 1,
	54	/* bit 271:258 - Reserved */
	55	rsvd_1 : 14;
	56	/* bit 279:272 - Notification Vector */
	57	u8 nv;
	58	/* bit 287:280 - Reserved */
	59	u8 rsvd_2;
	60	/* bit 319:288 - Notification Destination */
	61	u32 ndst;
	62	};
	63	u64 control;
	64	};
	65	u32 rsvd[6];
	66	} __aligned(64);
	67
2ef444f1 CP	68	#define RTIT_ADDR_RANGE 4
	69
	70	struct pt_ctx {
	71	u64 ctl;
	72	u64 status;
	73	u64 output_base;
	74	u64 output_mask;
	75	u64 cr3_match;
	76	u64 addr_a[RTIT_ADDR_RANGE];
	77	u64 addr_b[RTIT_ADDR_RANGE];
	78	};
	79
	80	struct pt_desc {
	81	u64 ctl_bitmask;
	82	u32 addr_range;
	83	u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
	84	struct pt_ctx host;
	85	struct pt_ctx guest;
	86	};
8373d25d SC	87
	88	/*
	89	* The nested_vmx structure is part of vcpu_vmx, and holds information we need
	90	* for correct emulation of VMX (i.e., nested VMX) on this vcpu.
	91	*/
	92	struct nested_vmx {
	93	/* Has the level1 guest done vmxon? */
	94	bool vmxon;
	95	gpa_t vmxon_ptr;
	96	bool pml_full;
	97
	98	/* The guest-physical address of the current VMCS L1 keeps for L2 */
	99	gpa_t current_vmptr;
	100	/*
	101	* Cache of the guest's VMCS, existing outside of guest memory.
	102	* Loaded from guest memory during VMPTRLD. Flushed to guest
	103	* memory during VMCLEAR and VMPTRLD.
	104	*/
	105	struct vmcs12 *cached_vmcs12;
	106	/*
	107	* Cache of the guest's shadow VMCS, existing outside of guest
	108	* memory. Loaded from guest memory during VM entry. Flushed
	109	* to guest memory during VM exit.
	110	*/
	111	struct vmcs12 *cached_shadow_vmcs12;
	112	/*
	113	* Indicates if the shadow vmcs or enlightened vmcs must be updated
	114	* with the data held by struct vmcs12.
	115	*/
	116	bool need_vmcs12_sync;
	117	bool dirty_vmcs12;
	118
	119	/*
	120	* vmcs02 has been initialized, i.e. state that is constant for
	121	* vmcs02 has been written to the backing VMCS. Initialization
	122	* is delayed until L1 actually attempts to run a nested VM.
	123	*/
	124	bool vmcs02_initialized;
	125
	126	bool change_vmcs01_virtual_apic_mode;
	127
	128	/*
	129	* Enlightened VMCS has been enabled. It does not mean that L1 has to
	130	* use it. However, VMX features available to L1 will be limited based
	131	* on what the enlightened VMCS supports.
	132	*/
	133	bool enlightened_vmcs_enabled;
	134
	135	/* L2 must run next, and mustn't decide to exit to L1. */
	136	bool nested_run_pending;
	137
	138	struct loaded_vmcs vmcs02;
	139
	140	/*
	141	* Guest pages referred to in the vmcs02 with host-physical
	142	* pointers, so we must keep them pinned while L2 runs.
	143	*/
	144	struct page *apic_access_page;
96c66e87	145	struct kvm_host_map virtual_apic_map;
3278e049	146	struct kvm_host_map pi_desc_map;
31f0b6c4 KA	147
	148	struct kvm_host_map msr_bitmap_map;
	149
8373d25d SC	150	struct pi_desc *pi_desc;
	151	bool pi_pending;
	152	u16 posted_intr_nv;
	153
	154	struct hrtimer preemption_timer;
	155	bool preemption_timer_expired;
	156
	157	/* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
	158	u64 vmcs01_debugctl;
	159	u64 vmcs01_guest_bndcfgs;
	160
	161	u16 vpid02;
	162	u16 last_vpid;
	163
	164	struct nested_vmx_msrs msrs;
	165
	166	/* SMM related state */
	167	struct {
	168	/* in VMX operation on SMM entry? */
	169	bool vmxon;
	170	/* in guest mode on SMM entry? */
	171	bool guest_mode;
	172	} smm;
	173
	174	gpa_t hv_evmcs_vmptr;
dee9c049	175	struct kvm_host_map hv_evmcs_map;
8373d25d SC	176	struct hv_enlightened_vmcs *hv_evmcs;
	177	};
	178
	179	struct vcpu_vmx {
	180	struct kvm_vcpu vcpu;
8373d25d SC	181	u8 fail;
	182	u8 msr_bitmap_mode;
	183	u32 exit_intr_info;
	184	u32 idt_vectoring_info;
	185	ulong rflags;
	186	struct shared_msr_entry *guest_msrs;
	187	int nmsrs;
	188	int save_nmsrs;
	189	bool guest_msrs_dirty;
	190	unsigned long host_idt_base;
	191	#ifdef CONFIG_X86_64
	192	u64 msr_host_kernel_gs_base;
	193	u64 msr_guest_kernel_gs_base;
	194	#endif
	195
8373d25d SC	196	u64 spec_ctrl;
	197
	198	u32 vm_entry_controls_shadow;
	199	u32 vm_exit_controls_shadow;
	200	u32 secondary_exec_control;
	201
	202	/*
	203	* loaded_vmcs points to the VMCS currently used in this vcpu. For a
	204	* non-nested (L1) guest, it always points to vmcs01. For a nested
	205	* guest (L2), it points to a different VMCS. loaded_cpu_state points
	206	* to the VMCS whose state is loaded into the CPU registers that only
	207	* need to be switched when transitioning to/from the kernel; a NULL
	208	* value indicates that host state is loaded.
	209	*/
	210	struct loaded_vmcs vmcs01;
	211	struct loaded_vmcs *loaded_vmcs;
	212	struct loaded_vmcs *loaded_cpu_state;
c9afc58c	213
8373d25d SC	214	struct msr_autoload {
	215	struct vmx_msrs guest;
	216	struct vmx_msrs host;
	217	} msr_autoload;
	218
	219	struct {
	220	int vm86_active;
	221	ulong save_rflags;
	222	struct kvm_segment segs[8];
	223	} rmode;
	224	struct {
	225	u32 bitmask; /* 4 bits per segment (1 bit per field) */
	226	struct kvm_save_segment {
	227	u16 selector;
	228	unsigned long base;
	229	u32 limit;
	230	u32 ar;
	231	} seg[8];
	232	} segment_cache;
	233	int vpid;
	234	bool emulation_required;
	235
	236	u32 exit_reason;
	237
	238	/* Posted interrupt descriptor */
	239	struct pi_desc pi_desc;
	240
	241	/* Support for a guest hypervisor (nested VMX) */
	242	struct nested_vmx nested;
	243
	244	/* Dynamic PLE window. */
	245	int ple_window;
	246	bool ple_window_dirty;
	247
	248	bool req_immediate_exit;
	249
	250	/* Support for PML */
	251	#define PML_ENTITY_NUM 512
	252	struct page *pml_pg;
	253
	254	/* apic deadline value in host tsc */
	255	u64 hv_deadline_tsc;
	256
	257	u64 current_tsc_ratio;
	258
	259	u32 host_pkru;
	260
	261	unsigned long host_debugctlmsr;
	262
6c6a2ab9 LA	263	u64 msr_ia32_power_ctl;
6c6a2ab9 LA	264
8373d25d SC	265	/*
	266	* Only bits masked by msr_ia32_feature_control_valid_bits can be set in
	267	* msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
	268	* in msr_ia32_feature_control_valid_bits.
	269	*/
	270	u64 msr_ia32_feature_control;
	271	u64 msr_ia32_feature_control_valid_bits;
	272	u64 ept_pointer;
2ef444f1 CP	273
2ef444f1 CP	274	struct pt_desc pt_desc;
8373d25d SC	275	};
	276
	277	enum ept_pointers_status {
	278	EPT_POINTERS_CHECK = 0,
	279	EPT_POINTERS_MATCH = 1,
	280	EPT_POINTERS_MISMATCH = 2
	281	};
	282
	283	struct kvm_vmx {
	284	struct kvm kvm;
	285
	286	unsigned int tss_addr;
	287	bool ept_identity_pagetable_done;
	288	gpa_t ept_identity_map_addr;
	289
	290	enum ept_pointers_status ept_pointers_match;
	291	spinlock_t ept_pointer_lock;
	292	};
	293
7c97fcb3	294	bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
97b7ead3 SC	295	void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
	296	void vmx_vcpu_put(struct kvm_vcpu *vcpu);
	297	int allocate_vpid(void);
	298	void free_vpid(int vpid);
	299	void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
	300	void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
	301	int vmx_get_cpl(struct kvm_vcpu *vcpu);
	302	unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
	303	void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
	304	u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
	305	void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
	306	void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
	307	void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
	308	void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
	309	int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
	310	void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
	311	void ept_save_pdptrs(struct kvm_vcpu *vcpu);
	312	void vmx_get_segment(struct kvm_vcpu vcpu, struct kvm_segment var, int seg);
	313	void vmx_set_segment(struct kvm_vcpu vcpu, struct kvm_segment var, int seg);
	314	u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
	315	void update_exception_bitmap(struct kvm_vcpu *vcpu);
	316	void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
	317	bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
	318	void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
	319	void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
	320	struct shared_msr_entry find_msr_entry(struct vcpu_vmx vmx, u32 msr);
b08c2896	321	void pt_update_intercept_for_msr(struct vcpu_vmx *vmx);
97b7ead3	322
8373d25d SC	323	#define POSTED_INTR_ON 0
	324	#define POSTED_INTR_SN 1
	325
	326	static inline bool pi_test_and_set_on(struct pi_desc *pi_desc)
	327	{
	328	return test_and_set_bit(POSTED_INTR_ON,
	329	(unsigned long *)&pi_desc->control);
	330	}
	331
	332	static inline bool pi_test_and_clear_on(struct pi_desc *pi_desc)
	333	{
	334	return test_and_clear_bit(POSTED_INTR_ON,
	335	(unsigned long *)&pi_desc->control);
	336	}
	337
	338	static inline int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
	339	{
	340	return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
	341	}
	342
81b01667	343	static inline void pi_set_sn(struct pi_desc *pi_desc)
8373d25d	344	{
81b01667 LK	345	set_bit(POSTED_INTR_SN,
81b01667 LK	346	(unsigned long *)&pi_desc->control);
8373d25d SC	347	}
8373d25d SC	348
81b01667	349	static inline void pi_set_on(struct pi_desc *pi_desc)
8373d25d	350	{
81b01667 LK	351	set_bit(POSTED_INTR_ON,
81b01667 LK	352	(unsigned long *)&pi_desc->control);
8373d25d SC	353	}
	354
	355	static inline void pi_clear_on(struct pi_desc *pi_desc)
	356	{
	357	clear_bit(POSTED_INTR_ON,
	358	(unsigned long *)&pi_desc->control);
	359	}
	360
	361	static inline int pi_test_on(struct pi_desc *pi_desc)
	362	{
	363	return test_bit(POSTED_INTR_ON,
	364	(unsigned long *)&pi_desc->control);
	365	}
	366
	367	static inline int pi_test_sn(struct pi_desc *pi_desc)
	368	{
	369	return test_bit(POSTED_INTR_SN,
	370	(unsigned long *)&pi_desc->control);
	371	}
	372
89b0c9f5 SC	373	static inline u8 vmx_get_rvi(void)
	374	{
	375	return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
	376	}
	377
	378	static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
	379	{
	380	vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
	381	}
	382
	383	static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
	384	{
	385	vmcs_write32(VM_ENTRY_CONTROLS, val);
	386	vmx->vm_entry_controls_shadow = val;
	387	}
	388
	389	static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
	390	{
	391	if (vmx->vm_entry_controls_shadow != val)
	392	vm_entry_controls_init(vmx, val);
	393	}
	394
	395	static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
	396	{
	397	return vmx->vm_entry_controls_shadow;
	398	}
	399
	400	static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
	401	{
	402	vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) \| val);
	403	}
	404
	405	static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
	406	{
	407	vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
	408	}
	409
	410	static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
	411	{
	412	vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
	413	}
	414
	415	static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
	416	{
	417	vmcs_write32(VM_EXIT_CONTROLS, val);
	418	vmx->vm_exit_controls_shadow = val;
	419	}
	420
	421	static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
	422	{
	423	if (vmx->vm_exit_controls_shadow != val)
	424	vm_exit_controls_init(vmx, val);
	425	}
	426
	427	static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
	428	{
	429	return vmx->vm_exit_controls_shadow;
	430	}
	431
	432	static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
	433	{
	434	vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) \| val);
	435	}
	436
437	static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
438	{
439	vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
440	}
441
8373d25d SC	442	static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
	443	{
	444	vmx->segment_cache.bitmask = 0;
	445	}
	446
	447	static inline u32 vmx_vmentry_ctrl(void)
	448	{
f99e3daf CP	449	u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
f99e3daf CP	450	if (pt_mode == PT_MODE_SYSTEM)
d9293597 YZ	451	vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP \|
d9293597 YZ	452	VM_ENTRY_LOAD_IA32_RTIT_CTL);
8373d25d	453	/* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
f99e3daf	454	return vmentry_ctrl &
8373d25d SC	455	~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL \| VM_ENTRY_LOAD_IA32_EFER);
	456	}
	457
	458	static inline u32 vmx_vmexit_ctrl(void)
	459	{
f99e3daf CP	460	u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
f99e3daf CP	461	if (pt_mode == PT_MODE_SYSTEM)
d9293597 YZ	462	vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP \|
d9293597 YZ	463	VM_EXIT_CLEAR_IA32_RTIT_CTL);
8373d25d	464	/* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
d9293597	465	return vmexit_ctrl &
8373d25d SC	466	~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL \| VM_EXIT_LOAD_IA32_EFER);
	467	}
	468
	469	u32 vmx_exec_control(struct vcpu_vmx *vmx);
	470
	471	static inline struct kvm_vmx to_kvm_vmx(struct kvm kvm)
	472	{
	473	return container_of(kvm, struct kvm_vmx, kvm);
	474	}
	475
	476	static inline struct vcpu_vmx to_vmx(struct kvm_vcpu vcpu)
	477	{
	478	return container_of(vcpu, struct vcpu_vmx, vcpu);
	479	}
	480
	481	static inline struct pi_desc vcpu_to_pi_desc(struct kvm_vcpu vcpu)
	482	{
	483	return &(to_vmx(vcpu)->pi_desc);
	484	}
	485
41836839	486	struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
89b0c9f5 SC	487	void free_vmcs(struct vmcs *vmcs);
	488	int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
	489	void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
	490	void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs);
	491	void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
	492
	493	static inline struct vmcs *alloc_vmcs(bool shadow)
	494	{
41836839 BG	495	return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
41836839 BG	496	GFP_KERNEL_ACCOUNT);
89b0c9f5 SC	497	}
	498
	499	u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
	500
	501	static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
	502	bool invalidate_gpa)
	503	{
	504	if (enable_ept && (invalidate_gpa \|\| !enable_vpid)) {
	505	if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
	506	return;
	507	ept_sync_context(construct_eptp(vcpu,
	508	vcpu->arch.mmu->root_hpa));
	509	} else {
	510	vpid_sync_context(vpid);
	511	}
	512	}
	513
	514	static inline void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
	515	{
	516	__vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
	517	}
	518
	519	static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx)
	520	{
	521	vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
	522	vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
	523	}
	524
69090810 PB	525	void dump_vmcs(void);
69090810 PB	526
8373d25d	527	#endif /* __KVM_X86_VMX_H */