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Merge branch 'core-objtool-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-block.git] / arch / x86 / kvm / vmx / vmx.c
CommitLineData
20c8ccb1 1// SPDX-License-Identifier: GPL-2.0-only
6aa8b732
AK		 2/*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
7 *
8 * Copyright (C) 2006 Qumranet, Inc.
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
6aa8b732
AK		 14 */
15
199b118a
SC		 16#include <linux/frame.h>
17#include <linux/highmem.h>
18#include <linux/hrtimer.h>
19#include <linux/kernel.h>
edf88417 20#include <linux/kvm_host.h>
6aa8b732 21#include <linux/module.h>
c7addb90 22#include <linux/moduleparam.h>
e9bda3b3 23#include <linux/mod_devicetable.h>
199b118a 24#include <linux/mm.h>
199b118a 25#include <linux/sched.h>
b284909a 26#include <linux/sched/smt.h>
5a0e3ad6 27#include <linux/slab.h>
cafd6659 28#include <linux/tboot.h>
199b118a 29#include <linux/trace_events.h>
e495606d 30
199b118a 31#include <asm/apic.h>
fd8ca6da 32#include <asm/asm.h>
28b835d6 33#include <asm/cpu.h>
199b118a 34#include <asm/debugreg.h>
3b3be0d1 35#include <asm/desc.h>
952f07ec 36#include <asm/fpu/internal.h>
199b118a 37#include <asm/io.h>
efc64404 38#include <asm/irq_remapping.h>
199b118a
SC		 39#include <asm/kexec.h>
40#include <asm/perf_event.h>
41#include <asm/mce.h>
d6e41f11 42#include <asm/mmu_context.h>
773e8a04 43#include <asm/mshyperv.h>
199b118a
SC		 44#include <asm/spec-ctrl.h>
45#include <asm/virtext.h>
46#include <asm/vmx.h>
6aa8b732 47
3077c191 48#include "capabilities.h"
199b118a 49#include "cpuid.h"
4cebd747 50#include "evmcs.h"
199b118a
SC		 51#include "irq.h"
52#include "kvm_cache_regs.h"
53#include "lapic.h"
54#include "mmu.h"
55d2375e 55#include "nested.h"
89b0c9f5 56#include "ops.h"
25462f7f 57#include "pmu.h"
199b118a 58#include "trace.h"
cb1d474b 59#include "vmcs.h"
609363cf 60#include "vmcs12.h"
89b0c9f5 61#include "vmx.h"
199b118a 62#include "x86.h"
229456fc 63
6aa8b732
AK		 64MODULE_AUTHOR("Qumranet");
65MODULE_LICENSE("GPL");
66
575b255c 67#ifdef MODULE
e9bda3b3
JT		 68static const struct x86_cpu_id vmx_cpu_id[] = {
69 X86_FEATURE_MATCH(X86_FEATURE_VMX),
70 {}
71};
72MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
575b255c 73#endif
e9bda3b3 74
2c4fd91d 75bool __read_mostly enable_vpid = 1;
736caefe 76module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 77
d02fcf50
PB		 78static bool __read_mostly enable_vnmi = 1;
79module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
80
2c4fd91d 81bool __read_mostly flexpriority_enabled = 1;
736caefe 82module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 83
2c4fd91d 84bool __read_mostly enable_ept = 1;
736caefe 85module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 86
2c4fd91d 87bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 88module_param_named(unrestricted_guest,
89 enable_unrestricted_guest, bool, S_IRUGO);
90
2c4fd91d 91bool __read_mostly enable_ept_ad_bits = 1;
83c3a331
XH		 92module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
93
a27685c3 94static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 95module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 96
476bc001 97static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 98module_param(fasteoi, bool, S_IRUGO);
99
a4443267 100bool __read_mostly enable_apicv = 1;
01e439be 101module_param(enable_apicv, bool, S_IRUGO);
83d4c286 102
801d3424
NHE		 103/*
104 * If nested=1, nested virtualization is supported, i.e., guests may use
105 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
106 * use VMX instructions.
107 */
1e58e5e5 108static bool __read_mostly nested = 1;
801d3424
NHE		 109module_param(nested, bool, S_IRUGO);
110
2c4fd91d 111bool __read_mostly enable_pml = 1;
843e4330
KH		 112module_param_named(pml, enable_pml, bool, S_IRUGO);
113
6f2f8453
PB		 114static bool __read_mostly dump_invalid_vmcs = 0;
115module_param(dump_invalid_vmcs, bool, 0644);
116
904e14fb
PB		 117#define MSR_BITMAP_MODE_X2APIC 1
118#define MSR_BITMAP_MODE_X2APIC_APICV 2
904e14fb 119
64903d61
HZ		 120#define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
121
64672c95
YJ		 122/* Guest_tsc -> host_tsc conversion requires 64-bit division. */
123static int __read_mostly cpu_preemption_timer_multi;
124static bool __read_mostly enable_preemption_timer = 1;
125#ifdef CONFIG_X86_64
126module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
127#endif
128
3de6347b 129#define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
1706bd0c
SC		 130#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
131#define KVM_VM_CR0_ALWAYS_ON \
132 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
133 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 134#define KVM_CR4_GUEST_OWNED_BITS \
135 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
fd8cb433 136 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
4c38609a 137
5dc1f044 138#define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
cdc0e244
AK		 139#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
140#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
141
78ac8b47
AK		 142#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
143
bf8c55d8
CP		 144#define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
145 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
146 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
147 RTIT_STATUS_BYTECNT))
148
149#define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
150 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
151
4b8d54f9
ZE		 152/*
153 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
154 * ple_gap: upper bound on the amount of time between two successive
155 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 156 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 157 * ple_window: upper bound on the amount of time a guest is allowed to execute
158 * in a PAUSE loop. Tests indicate that most spinlocks are held for
159 * less than 2^12 cycles
160 * Time is measured based on a counter that runs at the same rate as the TSC,
161 * refer SDM volume 3b section 21.6.13 & 22.1.3.
162 */
c8e88717 163static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
a87c99e6 164module_param(ple_gap, uint, 0444);
b4a2d31d 165
7fbc85a5
BM		 166static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
167module_param(ple_window, uint, 0444);
4b8d54f9 168
b4a2d31d 169/* Default doubles per-vcpu window every exit. */
c8e88717 170static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
7fbc85a5 171module_param(ple_window_grow, uint, 0444);
b4a2d31d
RK		 172
173/* Default resets per-vcpu window every exit to ple_window. */
c8e88717 174static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
7fbc85a5 175module_param(ple_window_shrink, uint, 0444);
b4a2d31d
RK		 176
177/* Default is to compute the maximum so we can never overflow. */
7fbc85a5
BM		 178static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
179module_param(ple_window_max, uint, 0444);
b4a2d31d 180
f99e3daf
CP		 181/* Default is SYSTEM mode, 1 for host-guest mode */
182int __read_mostly pt_mode = PT_MODE_SYSTEM;
183module_param(pt_mode, int, S_IRUGO);
184
a399477e 185static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
427362a1 186static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
dd4bfa73 187static DEFINE_MUTEX(vmx_l1d_flush_mutex);
a399477e 188
7db92e16
TG		 189/* Storage for pre module init parameter parsing */
190static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
a399477e
KRW		 191
192static const struct {
193 const char *option;
0027ff2a 194 bool for_parse;
a399477e 195} vmentry_l1d_param[] = {
0027ff2a
PB		 196 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
197 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
198 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
199 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
200 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
201 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
a399477e
KRW		 202};
203
7db92e16
TG		 204#define L1D_CACHE_ORDER 4
205static void *vmx_l1d_flush_pages;
206
207static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
a399477e 208{
7db92e16 209 struct page *page;
288d152c 210 unsigned int i;
a399477e 211
19a36d32
WL		 212 if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
213 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
214 return 0;
215 }
216
7db92e16
TG		 217 if (!enable_ept) {
218 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
219 return 0;
a399477e
KRW		 220 }
221
d806afa4
YW		 222 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
223 u64 msr;
224
225 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
226 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
227 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
228 return 0;
229 }
230 }
8e0b2b91 231
d90a7a0e
JK		 232 /* If set to auto use the default l1tf mitigation method */
233 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
234 switch (l1tf_mitigation) {
235 case L1TF_MITIGATION_OFF:
236 l1tf = VMENTER_L1D_FLUSH_NEVER;
237 break;
238 case L1TF_MITIGATION_FLUSH_NOWARN:
239 case L1TF_MITIGATION_FLUSH:
240 case L1TF_MITIGATION_FLUSH_NOSMT:
241 l1tf = VMENTER_L1D_FLUSH_COND;
242 break;
243 case L1TF_MITIGATION_FULL:
244 case L1TF_MITIGATION_FULL_FORCE:
245 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
246 break;
247 }
248 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
249 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
250 }
251
7db92e16
TG		 252 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
253 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
41836839
BG		 254 /*
255 * This allocation for vmx_l1d_flush_pages is not tied to a VM
256 * lifetime and so should not be charged to a memcg.
257 */
7db92e16
TG		 258 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
259 if (!page)
260 return -ENOMEM;
261 vmx_l1d_flush_pages = page_address(page);
288d152c
NS		 262
263 /*
264 * Initialize each page with a different pattern in
265 * order to protect against KSM in the nested
266 * virtualization case.
267 */
268 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
269 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
270 PAGE_SIZE);
271 }
7db92e16
TG		 272 }
273
274 l1tf_vmx_mitigation = l1tf;
275
895ae47f
TG		 276 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
277 static_branch_enable(&vmx_l1d_should_flush);
278 else
279 static_branch_disable(&vmx_l1d_should_flush);
4c6523ec 280
427362a1
NS		 281 if (l1tf == VMENTER_L1D_FLUSH_COND)
282 static_branch_enable(&vmx_l1d_flush_cond);
895ae47f 283 else
427362a1 284 static_branch_disable(&vmx_l1d_flush_cond);
7db92e16
TG		 285 return 0;
286}
287
288static int vmentry_l1d_flush_parse(const char *s)
289{
290 unsigned int i;
291
292 if (s) {
293 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
0027ff2a
PB		 294 if (vmentry_l1d_param[i].for_parse &&
295 sysfs_streq(s, vmentry_l1d_param[i].option))
296 return i;
7db92e16
TG		 297 }
298 }
a399477e
KRW		 299 return -EINVAL;
300}
301
7db92e16
TG		 302static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
303{
dd4bfa73 304 int l1tf, ret;
7db92e16 305
7db92e16
TG		 306 l1tf = vmentry_l1d_flush_parse(s);
307 if (l1tf < 0)
308 return l1tf;
309
0027ff2a
PB		 310 if (!boot_cpu_has(X86_BUG_L1TF))
311 return 0;
312
7db92e16
TG		 313 /*
314 * Has vmx_init() run already? If not then this is the pre init
315 * parameter parsing. In that case just store the value and let
316 * vmx_init() do the proper setup after enable_ept has been
317 * established.
318 */
319 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
320 vmentry_l1d_flush_param = l1tf;
321 return 0;
322 }
323
dd4bfa73
TG		 324 mutex_lock(&vmx_l1d_flush_mutex);
325 ret = vmx_setup_l1d_flush(l1tf);
326 mutex_unlock(&vmx_l1d_flush_mutex);
327 return ret;
7db92e16
TG		 328}
329
a399477e
KRW		 330static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
331{
0027ff2a
PB		 332 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
333 return sprintf(s, "???\n");
334
7db92e16 335 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
a399477e
KRW		 336}
337
338static const struct kernel_param_ops vmentry_l1d_flush_ops = {
339 .set = vmentry_l1d_flush_set,
340 .get = vmentry_l1d_flush_get,
341};
895ae47f 342module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
a399477e 343
d99e4152
GN		 344static bool guest_state_valid(struct kvm_vcpu *vcpu);
345static u32 vmx_segment_access_rights(struct kvm_segment *var);
1e4329ee 346static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
15d45071 347 u32 msr, int type);
75880a01 348
453eafbe
SC		 349void vmx_vmexit(void);
350
52a9fcbc
SC		 351#define vmx_insn_failed(fmt...) \
352do { \
353 WARN_ONCE(1, fmt); \
354 pr_warn_ratelimited(fmt); \
355} while (0)
356
6e202097
SC		 357asmlinkage void vmread_error(unsigned long field, bool fault)
358{
359 if (fault)
360 kvm_spurious_fault();
361 else
362 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
363}
364
52a9fcbc
SC		 365noinline void vmwrite_error(unsigned long field, unsigned long value)
366{
367 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
368 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
369}
370
371noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
372{
373 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
374}
375
376noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
377{
378 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
379}
380
381noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
382{
383 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
384 ext, vpid, gva);
385}
386
387noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
388{
389 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
390 ext, eptp, gpa);
391}
392
6aa8b732 393static DEFINE_PER_CPU(struct vmcs *, vmxarea);
75edce8a 394DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 395/*
396 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
397 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
398 */
399static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
6aa8b732 400
bf9f6ac8
FW		 401/*
402 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
403 * can find which vCPU should be waken up.
404 */
405static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
406static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
407
2384d2b3
SY		 408static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
409static DEFINE_SPINLOCK(vmx_vpid_lock);
410
3077c191
SC		 411struct vmcs_config vmcs_config;
412struct vmx_capability vmx_capability;
d56f546d 413
6aa8b732
AK		 414#define VMX_SEGMENT_FIELD(seg) \
415 [VCPU_SREG_##seg] = { \
416 .selector = GUEST_##seg##_SELECTOR, \
417 .base = GUEST_##seg##_BASE, \
418 .limit = GUEST_##seg##_LIMIT, \
419 .ar_bytes = GUEST_##seg##_AR_BYTES, \
420 }
421
772e0318 422static const struct kvm_vmx_segment_field {
6aa8b732
AK		 423 unsigned selector;
424 unsigned base;
425 unsigned limit;
426 unsigned ar_bytes;
427} kvm_vmx_segment_fields[] = {
428 VMX_SEGMENT_FIELD(CS),
429 VMX_SEGMENT_FIELD(DS),
430 VMX_SEGMENT_FIELD(ES),
431 VMX_SEGMENT_FIELD(FS),
432 VMX_SEGMENT_FIELD(GS),
433 VMX_SEGMENT_FIELD(SS),
434 VMX_SEGMENT_FIELD(TR),
435 VMX_SEGMENT_FIELD(LDTR),
436};
437
cf3646eb 438u64 host_efer;
2342080c 439static unsigned long host_idt_base;
26bb0981 440
4d56c8a7 441/*
898a811f
JM		 442 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
443 * will emulate SYSCALL in legacy mode if the vendor string in guest
444 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
445 * support this emulation, IA32_STAR must always be included in
446 * vmx_msr_index[], even in i386 builds.
4d56c8a7 447 */
cf3646eb 448const u32 vmx_msr_index[] = {
05b3e0c2 449#ifdef CONFIG_X86_64
44ea2b17 450 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 451#endif
8c06585d 452 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
c11f83e0 453 MSR_IA32_TSX_CTRL,
6aa8b732 454};
6aa8b732 455
773e8a04
VK		 456#if IS_ENABLED(CONFIG_HYPERV)
457static bool __read_mostly enlightened_vmcs = true;
458module_param(enlightened_vmcs, bool, 0444);
459
877ad952
TL		 460/* check_ept_pointer() should be under protection of ept_pointer_lock. */
461static void check_ept_pointer_match(struct kvm *kvm)
462{
463 struct kvm_vcpu *vcpu;
464 u64 tmp_eptp = INVALID_PAGE;
465 int i;
466
467 kvm_for_each_vcpu(i, vcpu, kvm) {
468 if (!VALID_PAGE(tmp_eptp)) {
469 tmp_eptp = to_vmx(vcpu)->ept_pointer;
470 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
471 to_kvm_vmx(kvm)->ept_pointers_match
472 = EPT_POINTERS_MISMATCH;
473 return;
474 }
475 }
476
477 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
478}
479
8997f657 480static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
1f3a3e46
LT		 481 void *data)
482{
483 struct kvm_tlb_range *range = data;
484
485 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
486 range->pages);
487}
488
489static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
490 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
491{
492 u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
493
494 /*
495 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
496 * of the base of EPT PML4 table, strip off EPT configuration
497 * information.
498 */
499 if (range)
500 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
501 kvm_fill_hv_flush_list_func, (void *)range);
502 else
503 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
504}
505
506static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
507 struct kvm_tlb_range *range)
877ad952 508{
a5c214da 509 struct kvm_vcpu *vcpu;
b7c1c226 510 int ret = 0, i;
877ad952
TL		 511
512 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
513
514 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
515 check_ept_pointer_match(kvm);
516
517 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
53963a70 518 kvm_for_each_vcpu(i, vcpu, kvm) {
1f3a3e46
LT		 519 /* If ept_pointer is invalid pointer, bypass flush request. */
520 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
521 ret |= __hv_remote_flush_tlb_with_range(
522 kvm, vcpu, range);
53963a70 523 }
a5c214da 524 } else {
1f3a3e46
LT		 525 ret = __hv_remote_flush_tlb_with_range(kvm,
526 kvm_get_vcpu(kvm, 0), range);
877ad952 527 }
877ad952 528
877ad952
TL		 529 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
530 return ret;
531}
1f3a3e46
LT		 532static int hv_remote_flush_tlb(struct kvm *kvm)
533{
534 return hv_remote_flush_tlb_with_range(kvm, NULL);
535}
536
6f6a657c
VK		 537static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
538{
539 struct hv_enlightened_vmcs *evmcs;
540 struct hv_partition_assist_pg **p_hv_pa_pg =
541 &vcpu->kvm->arch.hyperv.hv_pa_pg;
542 /*
543 * Synthetic VM-Exit is not enabled in current code and so All
544 * evmcs in singe VM shares same assist page.
545 */
cab01850 546 if (!*p_hv_pa_pg)
6f6a657c 547 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
cab01850
VK		 548
549 if (!*p_hv_pa_pg)
550 return -ENOMEM;
6f6a657c
VK		 551
552 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
553
554 evmcs->partition_assist_page =
555 __pa(*p_hv_pa_pg);
cab01850 556 evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
6f6a657c
VK		 557 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
558
6f6a657c
VK		 559 return 0;
560}
561
773e8a04
VK		 562#endif /* IS_ENABLED(CONFIG_HYPERV) */
563
64672c95
YJ		 564/*
565 * Comment's format: document - errata name - stepping - processor name.
566 * Refer from
567 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
568 */
569static u32 vmx_preemption_cpu_tfms[] = {
570/* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
5710x000206E6,
572/* 323056.pdf - AAX65 - C2 - Xeon L3406 */
573/* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
574/* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
5750x00020652,
576/* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
5770x00020655,
578/* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
579/* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
580/*
581 * 320767.pdf - AAP86 - B1 -
582 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
583 */
5840x000106E5,
585/* 321333.pdf - AAM126 - C0 - Xeon 3500 */
5860x000106A0,
587/* 321333.pdf - AAM126 - C1 - Xeon 3500 */
5880x000106A1,
589/* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
5900x000106A4,
591 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
592 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
593 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
5940x000106A5,
3d82c565
WH		 595 /* Xeon E3-1220 V2 */
5960x000306A8,
64672c95
YJ		 597};
598
599static inline bool cpu_has_broken_vmx_preemption_timer(void)
600{
601 u32 eax = cpuid_eax(0x00000001), i;
602
603 /* Clear the reserved bits */
604 eax &= ~(0x3U << 14 | 0xfU << 28);
03f6a22a 605 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
64672c95
YJ		 606 if (eax == vmx_preemption_cpu_tfms[i])
607 return true;
608
609 return false;
610}
611
35754c98 612static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 613{
35754c98 614 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY		 615}
616
04547156
SY		 617static inline bool report_flexpriority(void)
618{
619 return flexpriority_enabled;
620}
621
97b7ead3 622static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 623{
624 int i;
625
a2fa3e9f 626 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 627 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 628 return i;
629 return -1;
630}
631
97b7ead3 632struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 633{
634 int i;
635
8b9cf98c 636 i = __find_msr_index(vmx, msr);
a75beee6 637 if (i >= 0)
a2fa3e9f 638 return &vmx->guest_msrs[i];
8b6d44c7 639 return NULL;
7725f0ba
AK		 640}
641
b07a5c53
PB		 642static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data)
643{
644 int ret = 0;
645
646 u64 old_msr_data = msr->data;
647 msr->data = data;
648 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
649 preempt_disable();
650 ret = kvm_set_shared_msr(msr->index, msr->data,
651 msr->mask);
652 preempt_enable();
653 if (ret)
654 msr->data = old_msr_data;
655 }
656 return ret;
657}
658
7c97fcb3
SC		 659void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
660{
661 vmcs_clear(loaded_vmcs->vmcs);
662 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
663 vmcs_clear(loaded_vmcs->shadow_vmcs);
664 loaded_vmcs->cpu = -1;
665 loaded_vmcs->launched = 0;
666}
667
2965faa5 668#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 669/*
670 * This bitmap is used to indicate whether the vmclear
671 * operation is enabled on all cpus. All disabled by
672 * default.
673 */
674static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
675
676static inline void crash_enable_local_vmclear(int cpu)
677{
678 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
679}
680
681static inline void crash_disable_local_vmclear(int cpu)
682{
683 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
684}
685
686static inline int crash_local_vmclear_enabled(int cpu)
687{
688 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
689}
690
691static void crash_vmclear_local_loaded_vmcss(void)
692{
693 int cpu = raw_smp_processor_id();
694 struct loaded_vmcs *v;
695
696 if (!crash_local_vmclear_enabled(cpu))
697 return;
698
699 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
700 loaded_vmcss_on_cpu_link)
701 vmcs_clear(v->vmcs);
702}
703#else
704static inline void crash_enable_local_vmclear(int cpu) { }
705static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 706#endif /* CONFIG_KEXEC_CORE */
8f536b76 707
d462b819 708static void __loaded_vmcs_clear(void *arg)
6aa8b732 709{
d462b819 710 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 711 int cpu = raw_smp_processor_id();
6aa8b732 712
d462b819
NHE		 713 if (loaded_vmcs->cpu != cpu)
714 return; /* vcpu migration can race with cpu offline */
715 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 716 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 717 crash_disable_local_vmclear(cpu);
d462b819 718 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 719
720 /*
721 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
722 * is before setting loaded_vmcs->vcpu to -1 which is done in
723 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
724 * then adds the vmcs into percpu list before it is deleted.
725 */
726 smp_wmb();
727
d462b819 728 loaded_vmcs_init(loaded_vmcs);
8f536b76 729 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 730}
731
89b0c9f5 732void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 733{
e6c7d321
XG		 734 int cpu = loaded_vmcs->cpu;
735
736 if (cpu != -1)
737 smp_call_function_single(cpu,
738 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 739}
740
2fb92db1
AK		 741static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
742 unsigned field)
743{
744 bool ret;
745 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
746
cb3c1e2f
SC		 747 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
748 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
2fb92db1
AK		 749 vmx->segment_cache.bitmask = 0;
750 }
751 ret = vmx->segment_cache.bitmask & mask;
752 vmx->segment_cache.bitmask |= mask;
753 return ret;
754}
755
756static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
757{
758 u16 *p = &vmx->segment_cache.seg[seg].selector;
759
760 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
761 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
762 return *p;
763}
764
765static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
766{
767 ulong *p = &vmx->segment_cache.seg[seg].base;
768
769 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
770 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
771 return *p;
772}
773
774static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
775{
776 u32 *p = &vmx->segment_cache.seg[seg].limit;
777
778 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
779 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
780 return *p;
781}
782
783static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
784{
785 u32 *p = &vmx->segment_cache.seg[seg].ar;
786
787 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
788 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
789 return *p;
790}
791
97b7ead3 792void update_exception_bitmap(struct kvm_vcpu *vcpu)
abd3f2d6
AK		 793{
794 u32 eb;
795
fd7373cc 796 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
bd7e5b08 797 (1u << DB_VECTOR) | (1u << AC_VECTOR);
9e869480
LA		 798 /*
799 * Guest access to VMware backdoor ports could legitimately
800 * trigger #GP because of TSS I/O permission bitmap.
801 * We intercept those #GP and allow access to them anyway
802 * as VMware does.
803 */
804 if (enable_vmware_backdoor)
805 eb |= (1u << GP_VECTOR);
fd7373cc
JK		 806 if ((vcpu->guest_debug &
807 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
808 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
809 eb |= 1u << BP_VECTOR;
7ffd92c5 810 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 811 eb = ~0;
089d034e 812 if (enable_ept)
1439442c 813 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
36cf24e0
NHE		 814
815 /* When we are running a nested L2 guest and L1 specified for it a
816 * certain exception bitmap, we must trap the same exceptions and pass
817 * them to L1. When running L2, we will only handle the exceptions
818 * specified above if L1 did not want them.
819 */
820 if (is_guest_mode(vcpu))
821 eb |= get_vmcs12(vcpu)->exception_bitmap;
822
abd3f2d6
AK		 823 vmcs_write32(EXCEPTION_BITMAP, eb);
824}
825
d28b387f
KA		 826/*
827 * Check if MSR is intercepted for currently loaded MSR bitmap.
828 */
829static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
830{
831 unsigned long *msr_bitmap;
832 int f = sizeof(unsigned long);
833
834 if (!cpu_has_vmx_msr_bitmap())
835 return true;
836
837 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
838
839 if (msr <= 0x1fff) {
840 return !!test_bit(msr, msr_bitmap + 0x800 / f);
841 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
842 msr &= 0x1fff;
843 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
844 }
845
846 return true;
847}
848
2961e876
GN		 849static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
850 unsigned long entry, unsigned long exit)
8bf00a52 851{
2961e876
GN		 852 vm_entry_controls_clearbit(vmx, entry);
853 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 854}
855
662f1d1d 856int vmx_find_msr_index(struct vmx_msrs *m, u32 msr)
ca83b4a7
KRW		 857{
858 unsigned int i;
859
860 for (i = 0; i < m->nr; ++i) {
861 if (m->val[i].index == msr)
862 return i;
863 }
864 return -ENOENT;
865}
866
61d2ef2c
AK		 867static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
868{
ca83b4a7 869 int i;
61d2ef2c
AK		 870 struct msr_autoload *m = &vmx->msr_autoload;
871
8bf00a52
GN		 872 switch (msr) {
873 case MSR_EFER:
c73da3fc 874 if (cpu_has_load_ia32_efer()) {
2961e876
GN		 875 clear_atomic_switch_msr_special(vmx,
876 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 877 VM_EXIT_LOAD_IA32_EFER);
878 return;
879 }
880 break;
881 case MSR_CORE_PERF_GLOBAL_CTRL:
c73da3fc 882 if (cpu_has_load_perf_global_ctrl()) {
2961e876 883 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 884 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
885 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
886 return;
887 }
888 break;
110312c8 889 }
ef0fbcac 890 i = vmx_find_msr_index(&m->guest, msr);
ca83b4a7 891 if (i < 0)
31907093 892 goto skip_guest;
33966dd6 893 --m->guest.nr;
33966dd6 894 m->guest.val[i] = m->guest.val[m->guest.nr];
33966dd6 895 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
110312c8 896
31907093 897skip_guest:
ef0fbcac 898 i = vmx_find_msr_index(&m->host, msr);
31907093 899 if (i < 0)
61d2ef2c 900 return;
31907093
KRW		 901
902 --m->host.nr;
903 m->host.val[i] = m->host.val[m->host.nr];
33966dd6 904 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
61d2ef2c
AK		 905}
906
2961e876
GN		 907static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
908 unsigned long entry, unsigned long exit,
909 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
910 u64 guest_val, u64 host_val)
8bf00a52
GN		 911{
912 vmcs_write64(guest_val_vmcs, guest_val);
5a5e8a15
SC		 913 if (host_val_vmcs != HOST_IA32_EFER)
914 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 915 vm_entry_controls_setbit(vmx, entry);
916 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 917}
918
61d2ef2c 919static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
989e3992 920 u64 guest_val, u64 host_val, bool entry_only)
61d2ef2c 921{
989e3992 922 int i, j = 0;
61d2ef2c
AK		 923 struct msr_autoload *m = &vmx->msr_autoload;
924
8bf00a52
GN		 925 switch (msr) {
926 case MSR_EFER:
c73da3fc 927 if (cpu_has_load_ia32_efer()) {
2961e876
GN		 928 add_atomic_switch_msr_special(vmx,
929 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 930 VM_EXIT_LOAD_IA32_EFER,
931 GUEST_IA32_EFER,
932 HOST_IA32_EFER,
933 guest_val, host_val);
934 return;
935 }
936 break;
937 case MSR_CORE_PERF_GLOBAL_CTRL:
c73da3fc 938 if (cpu_has_load_perf_global_ctrl()) {
2961e876 939 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 940 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
941 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
942 GUEST_IA32_PERF_GLOBAL_CTRL,
943 HOST_IA32_PERF_GLOBAL_CTRL,
944 guest_val, host_val);
945 return;
946 }
947 break;
7099e2e1
RK		 948 case MSR_IA32_PEBS_ENABLE:
949 /* PEBS needs a quiescent period after being disabled (to write
950 * a record). Disabling PEBS through VMX MSR swapping doesn't
951 * provide that period, so a CPU could write host's record into
952 * guest's memory.
953 */
954 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
110312c8
AK		 955 }
956
ef0fbcac 957 i = vmx_find_msr_index(&m->guest, msr);
989e3992 958 if (!entry_only)
ef0fbcac 959 j = vmx_find_msr_index(&m->host, msr);
61d2ef2c 960
7cfe0526
AL		 961 if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) ||
962 (j < 0 && m->host.nr == NR_LOADSTORE_MSRS)) {
60266204 963 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 964 "Can't add msr %x\n", msr);
965 return;
61d2ef2c 966 }
31907093 967 if (i < 0) {
ca83b4a7 968 i = m->guest.nr++;
33966dd6 969 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
31907093 970 }
989e3992
KRW		 971 m->guest.val[i].index = msr;
972 m->guest.val[i].value = guest_val;
973
974 if (entry_only)
975 return;
61d2ef2c 976
31907093
KRW		 977 if (j < 0) {
978 j = m->host.nr++;
33966dd6 979 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
61d2ef2c 980 }
31907093
KRW		 981 m->host.val[j].index = msr;
982 m->host.val[j].value = host_val;
61d2ef2c
AK		 983}
984
92c0d900 985static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 986{
844a5fe2
PB		 987 u64 guest_efer = vmx->vcpu.arch.efer;
988 u64 ignore_bits = 0;
989
9167ab79
PB		 990 /* Shadow paging assumes NX to be available. */
991 if (!enable_ept)
992 guest_efer |= EFER_NX;
3a34a881 993
51c6cf66 994 /*
844a5fe2 995 * LMA and LME handled by hardware; SCE meaningless outside long mode.
51c6cf66 996 */
844a5fe2 997 ignore_bits |= EFER_SCE;
51c6cf66
AK		 998#ifdef CONFIG_X86_64
999 ignore_bits |= EFER_LMA | EFER_LME;
1000 /* SCE is meaningful only in long mode on Intel */
1001 if (guest_efer & EFER_LMA)
1002 ignore_bits &= ~(u64)EFER_SCE;
1003#endif
84ad33ef 1004
f6577a5f
AL		 1005 /*
1006 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1007 * On CPUs that support "load IA32_EFER", always switch EFER
1008 * atomically, since it's faster than switching it manually.
1009 */
c73da3fc 1010 if (cpu_has_load_ia32_efer() ||
f6577a5f 1011 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1012 if (!(guest_efer & EFER_LMA))
1013 guest_efer &= ~EFER_LME;
54b98bff
AL		 1014 if (guest_efer != host_efer)
1015 add_atomic_switch_msr(vmx, MSR_EFER,
989e3992 1016 guest_efer, host_efer, false);
02343cf2
SC		 1017 else
1018 clear_atomic_switch_msr(vmx, MSR_EFER);
84ad33ef 1019 return false;
844a5fe2 1020 } else {
02343cf2
SC		 1021 clear_atomic_switch_msr(vmx, MSR_EFER);
1022
844a5fe2
PB		 1023 guest_efer &= ~ignore_bits;
1024 guest_efer |= host_efer & ignore_bits;
1025
1026 vmx->guest_msrs[efer_offset].data = guest_efer;
1027 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef 1028
844a5fe2
PB		 1029 return true;
1030 }
51c6cf66
AK		 1031}
1032
e28baead
AL		 1033#ifdef CONFIG_X86_32
1034/*
1035 * On 32-bit kernels, VM exits still load the FS and GS bases from the
1036 * VMCS rather than the segment table. KVM uses this helper to figure
1037 * out the current bases to poke them into the VMCS before entry.
1038 */
2d49ec72
GN		 1039static unsigned long segment_base(u16 selector)
1040{
8c2e41f7 1041 struct desc_struct *table;
2d49ec72
GN		 1042 unsigned long v;
1043
8c2e41f7 1044 if (!(selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN		 1045 return 0;
1046
45fc8757 1047 table = get_current_gdt_ro();
2d49ec72 1048
8c2e41f7 1049 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2d49ec72
GN		 1050 u16 ldt_selector = kvm_read_ldt();
1051
8c2e41f7 1052 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN		 1053 return 0;
1054
8c2e41f7 1055 table = (struct desc_struct *)segment_base(ldt_selector);
2d49ec72 1056 }
8c2e41f7 1057 v = get_desc_base(&table[selector >> 3]);
2d49ec72
GN		 1058 return v;
1059}
e28baead 1060#endif
2d49ec72 1061
e348ac7c
SC		 1062static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1063{
1064 return (pt_mode == PT_MODE_HOST_GUEST) &&
1065 !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1066}
1067
2ef444f1
CP		 1068static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1069{
1070 u32 i;
1071
1072 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1073 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1074 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1075 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1076 for (i = 0; i < addr_range; i++) {
1077 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1078 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1079 }
1080}
1081
1082static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1083{
1084 u32 i;
1085
1086 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1087 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1088 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1089 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1090 for (i = 0; i < addr_range; i++) {
1091 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1092 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1093 }
1094}
1095
1096static void pt_guest_enter(struct vcpu_vmx *vmx)
1097{
1098 if (pt_mode == PT_MODE_SYSTEM)
1099 return;
1100
2ef444f1 1101 /*
b08c2896
CP		 1102 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1103 * Save host state before VM entry.
2ef444f1 1104 */
b08c2896 1105 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
2ef444f1
CP		 1106 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1107 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1108 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1109 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1110 }
1111}
1112
1113static void pt_guest_exit(struct vcpu_vmx *vmx)
1114{
1115 if (pt_mode == PT_MODE_SYSTEM)
1116 return;
1117
1118 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1119 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1120 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1121 }
1122
1123 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1124 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1125}
1126
13b964a2
SC		 1127void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1128 unsigned long fs_base, unsigned long gs_base)
1129{
1130 if (unlikely(fs_sel != host->fs_sel)) {
1131 if (!(fs_sel & 7))
1132 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1133 else
1134 vmcs_write16(HOST_FS_SELECTOR, 0);
1135 host->fs_sel = fs_sel;
1136 }
1137 if (unlikely(gs_sel != host->gs_sel)) {
1138 if (!(gs_sel & 7))
1139 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1140 else
1141 vmcs_write16(HOST_GS_SELECTOR, 0);
1142 host->gs_sel = gs_sel;
1143 }
1144 if (unlikely(fs_base != host->fs_base)) {
1145 vmcs_writel(HOST_FS_BASE, fs_base);
1146 host->fs_base = fs_base;
1147 }
1148 if (unlikely(gs_base != host->gs_base)) {
1149 vmcs_writel(HOST_GS_BASE, gs_base);
1150 host->gs_base = gs_base;
1151 }
1152}
1153
97b7ead3 1154void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
33ed6329 1155{
04d2cc77 1156 struct vcpu_vmx *vmx = to_vmx(vcpu);
d7ee039e 1157 struct vmcs_host_state *host_state;
51e8a8cc 1158#ifdef CONFIG_X86_64
35060ed6 1159 int cpu = raw_smp_processor_id();
51e8a8cc 1160#endif
e368b875
SC		 1161 unsigned long fs_base, gs_base;
1162 u16 fs_sel, gs_sel;
26bb0981 1163 int i;
04d2cc77 1164
d264ee0c
SC		 1165 vmx->req_immediate_exit = false;
1166
f48b4711
LA		 1167 /*
1168 * Note that guest MSRs to be saved/restored can also be changed
1169 * when guest state is loaded. This happens when guest transitions
1170 * to/from long-mode by setting MSR_EFER.LMA.
1171 */
b464f57e
PB		 1172 if (!vmx->guest_msrs_ready) {
1173 vmx->guest_msrs_ready = true;
f48b4711
LA		 1174 for (i = 0; i < vmx->save_nmsrs; ++i)
1175 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1176 vmx->guest_msrs[i].data,
1177 vmx->guest_msrs[i].mask);
1178
1179 }
c9dfd3fb 1180
1181 if (vmx->nested.need_vmcs12_to_shadow_sync)
1182 nested_sync_vmcs12_to_shadow(vcpu);
1183
b464f57e 1184 if (vmx->guest_state_loaded)
33ed6329
AK		 1185 return;
1186
b464f57e 1187 host_state = &vmx->loaded_vmcs->host_state;
bd9966de 1188
33ed6329
AK		 1189 /*
1190 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1191 * allow segment selectors with cpl > 0 or ti == 1.
1192 */
d7ee039e 1193 host_state->ldt_sel = kvm_read_ldt();
42b933b5
VK		 1194
1195#ifdef CONFIG_X86_64
d7ee039e
SC		 1196 savesegment(ds, host_state->ds_sel);
1197 savesegment(es, host_state->es_sel);
e368b875
SC		 1198
1199 gs_base = cpu_kernelmode_gs_base(cpu);
b062b794
VK		 1200 if (likely(is_64bit_mm(current->mm))) {
1201 save_fsgs_for_kvm();
e368b875
SC		 1202 fs_sel = current->thread.fsindex;
1203 gs_sel = current->thread.gsindex;
b062b794 1204 fs_base = current->thread.fsbase;
e368b875 1205 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
b062b794 1206 } else {
e368b875
SC		 1207 savesegment(fs, fs_sel);
1208 savesegment(gs, gs_sel);
b062b794 1209 fs_base = read_msr(MSR_FS_BASE);
e368b875 1210 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
33ed6329 1211 }
b2da15ac 1212
4679b61f 1213 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
4fde8d57 1214#else
e368b875
SC		 1215 savesegment(fs, fs_sel);
1216 savesegment(gs, gs_sel);
1217 fs_base = segment_base(fs_sel);
1218 gs_base = segment_base(gs_sel);
707c0874 1219#endif
e368b875 1220
13b964a2 1221 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
b464f57e 1222 vmx->guest_state_loaded = true;
33ed6329
AK		 1223}
1224
6d6095bd 1225static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
33ed6329 1226{
d7ee039e
SC		 1227 struct vmcs_host_state *host_state;
1228
b464f57e 1229 if (!vmx->guest_state_loaded)
33ed6329
AK		 1230 return;
1231
b464f57e 1232 host_state = &vmx->loaded_vmcs->host_state;
bd9966de 1233
e1beb1d3 1234 ++vmx->vcpu.stat.host_state_reload;
bd9966de 1235
c8770e7b 1236#ifdef CONFIG_X86_64
4679b61f 1237 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
c8770e7b 1238#endif
d7ee039e
SC		 1239 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1240 kvm_load_ldt(host_state->ldt_sel);
33ed6329 1241#ifdef CONFIG_X86_64
d7ee039e 1242 load_gs_index(host_state->gs_sel);
9581d442 1243#else
d7ee039e 1244 loadsegment(gs, host_state->gs_sel);
33ed6329 1245#endif
33ed6329 1246 }
d7ee039e
SC		 1247 if (host_state->fs_sel & 7)
1248 loadsegment(fs, host_state->fs_sel);
b2da15ac 1249#ifdef CONFIG_X86_64
d7ee039e
SC		 1250 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1251 loadsegment(ds, host_state->ds_sel);
1252 loadsegment(es, host_state->es_sel);
b2da15ac 1253 }
b2da15ac 1254#endif
b7ffc44d 1255 invalidate_tss_limit();
44ea2b17 1256#ifdef CONFIG_X86_64
c8770e7b 1257 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1258#endif
45fc8757 1259 load_fixmap_gdt(raw_smp_processor_id());
b464f57e
PB		 1260 vmx->guest_state_loaded = false;
1261 vmx->guest_msrs_ready = false;
33ed6329
AK		 1262}
1263
678e315e
SC		 1264#ifdef CONFIG_X86_64
1265static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
a9b21b62 1266{
4679b61f 1267 preempt_disable();
b464f57e 1268 if (vmx->guest_state_loaded)
4679b61f
PB		 1269 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1270 preempt_enable();
678e315e 1271 return vmx->msr_guest_kernel_gs_base;
a9b21b62
AK		 1272}
1273
678e315e
SC		 1274static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1275{
4679b61f 1276 preempt_disable();
b464f57e 1277 if (vmx->guest_state_loaded)
4679b61f
PB		 1278 wrmsrl(MSR_KERNEL_GS_BASE, data);
1279 preempt_enable();
678e315e
SC		 1280 vmx->msr_guest_kernel_gs_base = data;
1281}
1282#endif
1283
28b835d6
FW		 1284static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1285{
1286 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1287 struct pi_desc old, new;
1288 unsigned int dest;
1289
31afb2ea
PB		 1290 /*
1291 * In case of hot-plug or hot-unplug, we may have to undo
1292 * vmx_vcpu_pi_put even if there is no assigned device. And we
1293 * always keep PI.NDST up to date for simplicity: it makes the
1294 * code easier, and CPU migration is not a fast path.
1295 */
1296 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
28b835d6
FW		 1297 return;
1298
132194ff
JM		 1299 /*
1300 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1301 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
1302 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
1303 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
1304 * correctly.
1305 */
1306 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
1307 pi_clear_sn(pi_desc);
1308 goto after_clear_sn;
1309 }
1310
31afb2ea 1311 /* The full case. */
28b835d6
FW		 1312 do {
1313 old.control = new.control = pi_desc->control;
1314
31afb2ea 1315 dest = cpu_physical_id(cpu);
28b835d6 1316
31afb2ea
PB		 1317 if (x2apic_enabled())
1318 new.ndst = dest;
1319 else
1320 new.ndst = (dest << 8) & 0xFF00;
28b835d6 1321
28b835d6 1322 new.sn = 0;
c0a1666b
PB		 1323 } while (cmpxchg64(&pi_desc->control, old.control,
1324 new.control) != old.control);
c112b5f5 1325
132194ff
JM		 1326after_clear_sn:
1327
c112b5f5
LK		 1328 /*
1329 * Clear SN before reading the bitmap. The VT-d firmware
1330 * writes the bitmap and reads SN atomically (5.2.3 in the
1331 * spec), so it doesn't really have a memory barrier that
1332 * pairs with this, but we cannot do that and we need one.
1333 */
1334 smp_mb__after_atomic();
1335
29881b6e 1336 if (!pi_is_pir_empty(pi_desc))
c112b5f5 1337 pi_set_on(pi_desc);
28b835d6 1338}
1be0e61c 1339
8ef863e6 1340void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1341{
a2fa3e9f 1342 struct vcpu_vmx *vmx = to_vmx(vcpu);
b80c76ec 1343 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
6aa8b732 1344
b80c76ec 1345 if (!already_loaded) {
fe0e80be 1346 loaded_vmcs_clear(vmx->loaded_vmcs);
92fe13be 1347 local_irq_disable();
8f536b76 1348 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1349
1350 /*
1351 * Read loaded_vmcs->cpu should be before fetching
1352 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1353 * See the comments in __loaded_vmcs_clear().
1354 */
1355 smp_rmb();
1356
d462b819
NHE		 1357 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1358 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1359 crash_enable_local_vmclear(cpu);
92fe13be 1360 local_irq_enable();
b80c76ec
JM		 1361 }
1362
1363 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1364 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1365 vmcs_load(vmx->loaded_vmcs->vmcs);
15d45071 1366 indirect_branch_prediction_barrier();
b80c76ec
JM		 1367 }
1368
1369 if (!already_loaded) {
59c58ceb 1370 void *gdt = get_current_gdt_ro();
b80c76ec
JM		 1371 unsigned long sysenter_esp;
1372
1373 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1374
6aa8b732
AK		 1375 /*
1376 * Linux uses per-cpu TSS and GDT, so set these when switching
e0c23063 1377 * processors. See 22.2.4.
6aa8b732 1378 */
e0c23063 1379 vmcs_writel(HOST_TR_BASE,
72f5e08d 1380 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
59c58ceb 1381 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
6aa8b732
AK		 1382
1383 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1384 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
ff2c3a18 1385
d462b819 1386 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1387 }
28b835d6 1388
2680d6da
OH		 1389 /* Setup TSC multiplier */
1390 if (kvm_has_tsc_control &&
c95ba92a
PF		 1391 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1392 decache_tsc_multiplier(vmx);
8ef863e6
SC		 1393}
1394
1395/*
1396 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1397 * vcpu mutex is already taken.
1398 */
1399void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1400{
1401 struct vcpu_vmx *vmx = to_vmx(vcpu);
1402
1403 vmx_vcpu_load_vmcs(vcpu, cpu);
2680d6da 1404
28b835d6 1405 vmx_vcpu_pi_load(vcpu, cpu);
8ef863e6 1406
1be0e61c 1407 vmx->host_pkru = read_pkru();
74c55931 1408 vmx->host_debugctlmsr = get_debugctlmsr();
28b835d6
FW		 1409}
1410
1411static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1412{
1413 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1414
1415 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 1416 !irq_remapping_cap(IRQ_POSTING_CAP) ||
1417 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW		 1418 return;
1419
1420 /* Set SN when the vCPU is preempted */
1421 if (vcpu->preempted)
1422 pi_set_sn(pi_desc);
6aa8b732
AK		 1423}
1424
13b964a2 1425static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
6aa8b732 1426{
28b835d6
FW		 1427 vmx_vcpu_pi_put(vcpu);
1428
6d6095bd 1429 vmx_prepare_switch_to_host(to_vmx(vcpu));
6aa8b732
AK		 1430}
1431
f244deed
WL		 1432static bool emulation_required(struct kvm_vcpu *vcpu)
1433{
1434 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1435}
1436
97b7ead3 1437unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
6aa8b732 1438{
e7bddc52 1439 struct vcpu_vmx *vmx = to_vmx(vcpu);
78ac8b47 1440 unsigned long rflags, save_rflags;
345dcaa8 1441
cb3c1e2f
SC		 1442 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1443 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
6de12732 1444 rflags = vmcs_readl(GUEST_RFLAGS);
e7bddc52 1445 if (vmx->rmode.vm86_active) {
6de12732 1446 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
e7bddc52 1447 save_rflags = vmx->rmode.save_rflags;
6de12732
AK		 1448 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1449 }
e7bddc52 1450 vmx->rflags = rflags;
78ac8b47 1451 }
e7bddc52 1452 return vmx->rflags;
6aa8b732
AK		 1453}
1454
97b7ead3 1455void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6aa8b732 1456{
e7bddc52 1457 struct vcpu_vmx *vmx = to_vmx(vcpu);
491c1ad1 1458 unsigned long old_rflags;
f244deed 1459
491c1ad1 1460 if (enable_unrestricted_guest) {
cb3c1e2f 1461 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
491c1ad1
SC		 1462 vmx->rflags = rflags;
1463 vmcs_writel(GUEST_RFLAGS, rflags);
1464 return;
1465 }
1466
1467 old_rflags = vmx_get_rflags(vcpu);
e7bddc52
SC		 1468 vmx->rflags = rflags;
1469 if (vmx->rmode.vm86_active) {
1470 vmx->rmode.save_rflags = rflags;
053de044 1471 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1472 }
6aa8b732 1473 vmcs_writel(GUEST_RFLAGS, rflags);
f244deed 1474
e7bddc52
SC		 1475 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1476 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 1477}
1478
97b7ead3 1479u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1480{
1481 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1482 int ret = 0;
1483
1484 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1485 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1486 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1487 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 1488
37ccdcbe 1489 return ret;
2809f5d2
GC		 1490}
1491
97b7ead3 1492void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2809f5d2
GC		 1493{
1494 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1495 u32 interruptibility = interruptibility_old;
1496
1497 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1498
48005f64 1499 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1500 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1501 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1502 interruptibility |= GUEST_INTR_STATE_STI;
1503
1504 if ((interruptibility != interruptibility_old))
1505 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1506}
1507
bf8c55d8
CP		 1508static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1509{
1510 struct vcpu_vmx *vmx = to_vmx(vcpu);
1511 unsigned long value;
1512
1513 /*
1514 * Any MSR write that attempts to change bits marked reserved will
1515 * case a #GP fault.
1516 */
1517 if (data & vmx->pt_desc.ctl_bitmask)
1518 return 1;
1519
1520 /*
1521 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1522 * result in a #GP unless the same write also clears TraceEn.
1523 */
1524 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1525 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1526 return 1;
1527
1528 /*
1529 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1530 * and FabricEn would cause #GP, if
1531 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1532 */
1533 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1534 !(data & RTIT_CTL_FABRIC_EN) &&
1535 !intel_pt_validate_cap(vmx->pt_desc.caps,
1536 PT_CAP_single_range_output))
1537 return 1;
1538
1539 /*
1540 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1541 * utilize encodings marked reserved will casue a #GP fault.
1542 */
1543 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1544 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1545 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1546 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1547 return 1;
1548 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1549 PT_CAP_cycle_thresholds);
1550 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1551 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1552 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1553 return 1;
1554 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1555 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1556 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1557 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1558 return 1;
1559
1560 /*
1561 * If ADDRx_CFG is reserved or the encodings is >2 will
1562 * cause a #GP fault.
1563 */
1564 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1565 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1566 return 1;
1567 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1568 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1569 return 1;
1570 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1571 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1572 return 1;
1573 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1574 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1575 return 1;
1576
1577 return 0;
1578}
1579
1957aa63 1580static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
6aa8b732
AK		 1581{
1582 unsigned long rip;
6aa8b732 1583
1957aa63
SC		 1584 /*
1585 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1586 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1587 * set when EPT misconfig occurs. In practice, real hardware updates
1588 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1589 * (namely Hyper-V) don't set it due to it being undefined behavior,
1590 * i.e. we end up advancing IP with some random value.
1591 */
1592 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1593 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1594 rip = kvm_rip_read(vcpu);
1595 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1596 kvm_rip_write(vcpu, rip);
1597 } else {
1598 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1599 return 0;
1600 }
6aa8b732 1601
2809f5d2
GC		 1602 /* skipping an emulated instruction also counts */
1603 vmx_set_interrupt_shadow(vcpu, 0);
f8ea7c60 1604
60fc3d02 1605 return 1;
f8ea7c60
VK		 1606}
1607
5ef8acbd
OU		 1608
1609/*
1610 * Recognizes a pending MTF VM-exit and records the nested state for later
1611 * delivery.
1612 */
1613static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1614{
1615 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1616 struct vcpu_vmx *vmx = to_vmx(vcpu);
1617
1618 if (!is_guest_mode(vcpu))
1619 return;
1620
1621 /*
1622 * Per the SDM, MTF takes priority over debug-trap exceptions besides
1623 * T-bit traps. As instruction emulation is completed (i.e. at the
1624 * instruction boundary), any #DB exception pending delivery must be a
1625 * debug-trap. Record the pending MTF state to be delivered in
1626 * vmx_check_nested_events().
1627 */
1628 if (nested_cpu_has_mtf(vmcs12) &&
1629 (!vcpu->arch.exception.pending ||
1630 vcpu->arch.exception.nr == DB_VECTOR))
1631 vmx->nested.mtf_pending = true;
1632 else
1633 vmx->nested.mtf_pending = false;
1634}
1635
1636static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1637{
1638 vmx_update_emulated_instruction(vcpu);
1639 return skip_emulated_instruction(vcpu);
1640}
1641
caa057a2
WL		 1642static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1643{
1644 /*
1645 * Ensure that we clear the HLT state in the VMCS. We don't need to
1646 * explicitly skip the instruction because if the HLT state is set,
1647 * then the instruction is already executing and RIP has already been
1648 * advanced.
1649 */
1650 if (kvm_hlt_in_guest(vcpu->kvm) &&
1651 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1652 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1653}
1654
cfcd20e5 1655static void vmx_queue_exception(struct kvm_vcpu *vcpu)
298101da 1656{
77ab6db0 1657 struct vcpu_vmx *vmx = to_vmx(vcpu);
cfcd20e5
WL		 1658 unsigned nr = vcpu->arch.exception.nr;
1659 bool has_error_code = vcpu->arch.exception.has_error_code;
cfcd20e5 1660 u32 error_code = vcpu->arch.exception.error_code;
8ab2d2e2 1661 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1662
da998b46
JM		 1663 kvm_deliver_exception_payload(vcpu);
1664
8ab2d2e2 1665 if (has_error_code) {
77ab6db0 1666 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1667 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1668 }
77ab6db0 1669
7ffd92c5 1670 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1671 int inc_eip = 0;
1672 if (kvm_exception_is_soft(nr))
1673 inc_eip = vcpu->arch.event_exit_inst_len;
9497e1f2 1674 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
77ab6db0
JK		 1675 return;
1676 }
1677
add5ff7a
SC		 1678 WARN_ON_ONCE(vmx->emulation_required);
1679
66fd3f7f
GN		 1680 if (kvm_exception_is_soft(nr)) {
1681 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1682 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1683 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1684 } else
1685 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1686
1687 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
caa057a2
WL		 1688
1689 vmx_clear_hlt(vcpu);
298101da
AK		 1690}
1691
4e47c7a6
SY		 1692static bool vmx_rdtscp_supported(void)
1693{
1694 return cpu_has_vmx_rdtscp();
1695}
1696
ad756a16
MJ		 1697static bool vmx_invpcid_supported(void)
1698{
eb4b248e 1699 return cpu_has_vmx_invpcid();
ad756a16
MJ		 1700}
1701
a75beee6
ED		 1702/*
1703 * Swap MSR entry in host/guest MSR entry array.
1704 */
8b9cf98c 1705static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1706{
26bb0981 1707 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1708
1709 tmp = vmx->guest_msrs[to];
1710 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1711 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1712}
1713
e38aea3e
AK		 1714/*
1715 * Set up the vmcs to automatically save and restore system
1716 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1717 * mode, as fiddling with msrs is very expensive.
1718 */
8b9cf98c 1719static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1720{
26bb0981 1721 int save_nmsrs, index;
e38aea3e 1722
a75beee6
ED		 1723 save_nmsrs = 0;
1724#ifdef CONFIG_X86_64
84c8c5b8
JM		 1725 /*
1726 * The SYSCALL MSRs are only needed on long mode guests, and only
1727 * when EFER.SCE is set.
1728 */
1729 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1730 index = __find_msr_index(vmx, MSR_STAR);
a75beee6 1731 if (index >= 0)
8b9cf98c
RR		 1732 move_msr_up(vmx, index, save_nmsrs++);
1733 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1734 if (index >= 0)
8b9cf98c 1735 move_msr_up(vmx, index, save_nmsrs++);
84c8c5b8
JM		 1736 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1737 if (index >= 0)
8b9cf98c 1738 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1739 }
1740#endif
92c0d900
AK		 1741 index = __find_msr_index(vmx, MSR_EFER);
1742 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1743 move_msr_up(vmx, index, save_nmsrs++);
0023ef39
JM		 1744 index = __find_msr_index(vmx, MSR_TSC_AUX);
1745 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1746 move_msr_up(vmx, index, save_nmsrs++);
c11f83e0
PB		 1747 index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL);
1748 if (index >= 0)
1749 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1750
26bb0981 1751 vmx->save_nmsrs = save_nmsrs;
b464f57e 1752 vmx->guest_msrs_ready = false;
5897297b 1753
8d14695f 1754 if (cpu_has_vmx_msr_bitmap())
904e14fb 1755 vmx_update_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 1756}
1757
e79f245d 1758static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
6aa8b732 1759{
e79f245d 1760 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6aa8b732 1761
e79f245d 1762 if (is_guest_mode(vcpu) &&
5e3d394f 1763 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
e79f245d
KA		 1764 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1765
1766 return vcpu->arch.tsc_offset;
6aa8b732
AK		 1767}
1768
326e7425 1769static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1770{
45c3af97
PB		 1771 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1772 u64 g_tsc_offset = 0;
1773
1774 /*
1775 * We're here if L1 chose not to trap WRMSR to TSC. According
1776 * to the spec, this should set L1's TSC; The offset that L1
1777 * set for L2 remains unchanged, and still needs to be added
1778 * to the newly set TSC to get L2's TSC.
1779 */
1780 if (is_guest_mode(vcpu) &&
5e3d394f 1781 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
45c3af97 1782 g_tsc_offset = vmcs12->tsc_offset;
326e7425 1783
45c3af97
PB		 1784 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1785 vcpu->arch.tsc_offset - g_tsc_offset,
1786 offset);
1787 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1788 return offset + g_tsc_offset;
6aa8b732
AK		 1789}
1790
801d3424
NHE		 1791/*
1792 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1793 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1794 * all guests if the "nested" module option is off, and can also be disabled
1795 * for a single guest by disabling its VMX cpuid bit.
1796 */
7c97fcb3 1797bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
801d3424 1798{
d6321d49 1799 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
801d3424
NHE		 1800}
1801
55d2375e
SC		 1802static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1803 uint64_t val)
62cc6b9d 1804{
55d2375e 1805 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
62cc6b9d 1806
55d2375e 1807 return !(val & ~valid_bits);
62cc6b9d
DM		 1808}
1809
55d2375e 1810static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
62cc6b9d 1811{
55d2375e
SC		 1812 switch (msr->index) {
1813 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1814 if (!nested)
1815 return 1;
1816 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1817 default:
1818 return 1;
1819 }
62cc6b9d
DM		 1820}
1821
55d2375e
SC		 1822/*
1823 * Reads an msr value (of 'msr_index') into 'pdata'.
1824 * Returns 0 on success, non-0 otherwise.
1825 * Assumes vcpu_load() was already called.
1826 */
1827static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
62cc6b9d 1828{
55d2375e
SC		 1829 struct vcpu_vmx *vmx = to_vmx(vcpu);
1830 struct shared_msr_entry *msr;
bf8c55d8 1831 u32 index;
62cc6b9d 1832
55d2375e
SC		 1833 switch (msr_info->index) {
1834#ifdef CONFIG_X86_64
1835 case MSR_FS_BASE:
1836 msr_info->data = vmcs_readl(GUEST_FS_BASE);
62cc6b9d 1837 break;
55d2375e
SC		 1838 case MSR_GS_BASE:
1839 msr_info->data = vmcs_readl(GUEST_GS_BASE);
62cc6b9d 1840 break;
55d2375e
SC		 1841 case MSR_KERNEL_GS_BASE:
1842 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
62cc6b9d 1843 break;
55d2375e
SC		 1844#endif
1845 case MSR_EFER:
1846 return kvm_get_msr_common(vcpu, msr_info);
c11f83e0
PB		 1847 case MSR_IA32_TSX_CTRL:
1848 if (!msr_info->host_initiated &&
1849 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1850 return 1;
1851 goto find_shared_msr;
6e3ba4ab
TX		 1852 case MSR_IA32_UMWAIT_CONTROL:
1853 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1854 return 1;
1855
1856 msr_info->data = vmx->msr_ia32_umwait_control;
1857 break;
55d2375e
SC		 1858 case MSR_IA32_SPEC_CTRL:
1859 if (!msr_info->host_initiated &&
1860 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1861 return 1;
1862
1863 msr_info->data = to_vmx(vcpu)->spec_ctrl;
62cc6b9d 1864 break;
6aa8b732 1865 case MSR_IA32_SYSENTER_CS:
609e36d3 1866 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK		 1867 break;
1868 case MSR_IA32_SYSENTER_EIP:
609e36d3 1869 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1870 break;
1871 case MSR_IA32_SYSENTER_ESP:
609e36d3 1872 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1873 break;
0dd376e7 1874 case MSR_IA32_BNDCFGS:
691bd434 1875 if (!kvm_mpx_supported() ||
d6321d49
RK		 1876 (!msr_info->host_initiated &&
1877 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
93c4adc7 1878 return 1;
609e36d3 1879 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 1880 break;
c45dcc71
AR		 1881 case MSR_IA32_MCG_EXT_CTL:
1882 if (!msr_info->host_initiated &&
a6cb099a 1883 !(vmx->msr_ia32_feature_control &
32ad73db 1884 FEAT_CTL_LMCE_ENABLED))
cae50139 1885 return 1;
c45dcc71
AR		 1886 msr_info->data = vcpu->arch.mcg_ext_ctl;
1887 break;
32ad73db 1888 case MSR_IA32_FEAT_CTL:
a6cb099a 1889 msr_info->data = vmx->msr_ia32_feature_control;
cae50139
JK		 1890 break;
1891 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1892 if (!nested_vmx_allowed(vcpu))
1893 return 1;
31de3d25
VK		 1894 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1895 &msr_info->data))
1896 return 1;
1897 /*
1898 * Enlightened VMCS v1 doesn't have certain fields, but buggy
1899 * Hyper-V versions are still trying to use corresponding
1900 * features when they are exposed. Filter out the essential
1901 * minimum.
1902 */
1903 if (!msr_info->host_initiated &&
1904 vmx->nested.enlightened_vmcs_enabled)
1905 nested_evmcs_filter_control_msr(msr_info->index,
1906 &msr_info->data);
1907 break;
bf8c55d8
CP		 1908 case MSR_IA32_RTIT_CTL:
1909 if (pt_mode != PT_MODE_HOST_GUEST)
1910 return 1;
1911 msr_info->data = vmx->pt_desc.guest.ctl;
1912 break;
1913 case MSR_IA32_RTIT_STATUS:
1914 if (pt_mode != PT_MODE_HOST_GUEST)
1915 return 1;
1916 msr_info->data = vmx->pt_desc.guest.status;
1917 break;
1918 case MSR_IA32_RTIT_CR3_MATCH:
1919 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1920 !intel_pt_validate_cap(vmx->pt_desc.caps,
1921 PT_CAP_cr3_filtering))
1922 return 1;
1923 msr_info->data = vmx->pt_desc.guest.cr3_match;
1924 break;
1925 case MSR_IA32_RTIT_OUTPUT_BASE:
1926 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1927 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1928 PT_CAP_topa_output) &&
1929 !intel_pt_validate_cap(vmx->pt_desc.caps,
1930 PT_CAP_single_range_output)))
1931 return 1;
1932 msr_info->data = vmx->pt_desc.guest.output_base;
1933 break;
1934 case MSR_IA32_RTIT_OUTPUT_MASK:
1935 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1936 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1937 PT_CAP_topa_output) &&
1938 !intel_pt_validate_cap(vmx->pt_desc.caps,
1939 PT_CAP_single_range_output)))
1940 return 1;
1941 msr_info->data = vmx->pt_desc.guest.output_mask;
1942 break;
1943 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1944 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1945 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1946 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1947 PT_CAP_num_address_ranges)))
1948 return 1;
1949 if (index % 2)
1950 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1951 else
1952 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1953 break;
4e47c7a6 1954 case MSR_TSC_AUX:
d6321d49
RK		 1955 if (!msr_info->host_initiated &&
1956 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4e47c7a6 1957 return 1;
c11f83e0 1958 goto find_shared_msr;
6aa8b732 1959 default:
c11f83e0 1960 find_shared_msr:
a6cb099a 1961 msr = find_msr_entry(vmx, msr_info->index);
3bab1f5d 1962 if (msr) {
609e36d3 1963 msr_info->data = msr->data;
3bab1f5d 1964 break;
6aa8b732 1965 }
609e36d3 1966 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 1967 }
1968
6aa8b732
AK		 1969 return 0;
1970}
1971
1972/*
311497e0 1973 * Writes msr value into the appropriate "register".
6aa8b732
AK		 1974 * Returns 0 on success, non-0 otherwise.
1975 * Assumes vcpu_load() was already called.
1976 */
8fe8ab46 1977static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 1978{
a2fa3e9f 1979 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1980 struct shared_msr_entry *msr;
2cc51560 1981 int ret = 0;
8fe8ab46
WA		 1982 u32 msr_index = msr_info->index;
1983 u64 data = msr_info->data;
bf8c55d8 1984 u32 index;
2cc51560 1985
6aa8b732 1986 switch (msr_index) {
3bab1f5d 1987 case MSR_EFER:
8fe8ab46 1988 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 1989 break;
16175a79 1990#ifdef CONFIG_X86_64
6aa8b732 1991 case MSR_FS_BASE:
2fb92db1 1992 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1993 vmcs_writel(GUEST_FS_BASE, data);
1994 break;
1995 case MSR_GS_BASE:
2fb92db1 1996 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1997 vmcs_writel(GUEST_GS_BASE, data);
1998 break;
44ea2b17 1999 case MSR_KERNEL_GS_BASE:
678e315e 2000 vmx_write_guest_kernel_gs_base(vmx, data);
44ea2b17 2001 break;
6aa8b732
AK		 2002#endif
2003 case MSR_IA32_SYSENTER_CS:
de70d279
SC		 2004 if (is_guest_mode(vcpu))
2005 get_vmcs12(vcpu)->guest_sysenter_cs = data;
6aa8b732
AK		 2006 vmcs_write32(GUEST_SYSENTER_CS, data);
2007 break;
2008 case MSR_IA32_SYSENTER_EIP:
de70d279
SC		 2009 if (is_guest_mode(vcpu))
2010 get_vmcs12(vcpu)->guest_sysenter_eip = data;
f5b42c33 2011 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2012 break;
2013 case MSR_IA32_SYSENTER_ESP:
de70d279
SC		 2014 if (is_guest_mode(vcpu))
2015 get_vmcs12(vcpu)->guest_sysenter_esp = data;
f5b42c33 2016 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2017 break;
699a1ac2
SC		 2018 case MSR_IA32_DEBUGCTLMSR:
2019 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
2020 VM_EXIT_SAVE_DEBUG_CONTROLS)
2021 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
2022
2023 ret = kvm_set_msr_common(vcpu, msr_info);
2024 break;
2025
0dd376e7 2026 case MSR_IA32_BNDCFGS:
691bd434 2027 if (!kvm_mpx_supported() ||
d6321d49
RK		 2028 (!msr_info->host_initiated &&
2029 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
93c4adc7 2030 return 1;
fd8cb433 2031 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
4531662d 2032 (data & MSR_IA32_BNDCFGS_RSVD))
93c4adc7 2033 return 1;
0dd376e7
LJ		 2034 vmcs_write64(GUEST_BNDCFGS, data);
2035 break;
6e3ba4ab
TX		 2036 case MSR_IA32_UMWAIT_CONTROL:
2037 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2038 return 1;
2039
2040 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2041 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2042 return 1;
2043
2044 vmx->msr_ia32_umwait_control = data;
2045 break;
d28b387f
KA		 2046 case MSR_IA32_SPEC_CTRL:
2047 if (!msr_info->host_initiated &&
d28b387f
KA		 2048 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2049 return 1;
2050
6441fa61 2051 if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
d28b387f
KA		 2052 return 1;
2053
2054 vmx->spec_ctrl = data;
d28b387f
KA		 2055 if (!data)
2056 break;
2057
2058 /*
2059 * For non-nested:
2060 * When it's written (to non-zero) for the first time, pass
2061 * it through.
2062 *
2063 * For nested:
2064 * The handling of the MSR bitmap for L2 guests is done in
4d516fe7 2065 * nested_vmx_prepare_msr_bitmap. We should not touch the
d28b387f
KA		 2066 * vmcs02.msr_bitmap here since it gets completely overwritten
2067 * in the merging. We update the vmcs01 here for L1 as well
2068 * since it will end up touching the MSR anyway now.
2069 */
2070 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2071 MSR_IA32_SPEC_CTRL,
2072 MSR_TYPE_RW);
2073 break;
c11f83e0
PB		 2074 case MSR_IA32_TSX_CTRL:
2075 if (!msr_info->host_initiated &&
2076 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2077 return 1;
2078 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2079 return 1;
2080 goto find_shared_msr;
15d45071
AR		 2081 case MSR_IA32_PRED_CMD:
2082 if (!msr_info->host_initiated &&
15d45071
AR		 2083 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2084 return 1;
2085
2086 if (data & ~PRED_CMD_IBPB)
2087 return 1;
6441fa61
PB		 2088 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL))
2089 return 1;
15d45071
AR		 2090 if (!data)
2091 break;
2092
2093 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2094
2095 /*
2096 * For non-nested:
2097 * When it's written (to non-zero) for the first time, pass
2098 * it through.
2099 *
2100 * For nested:
2101 * The handling of the MSR bitmap for L2 guests is done in
4d516fe7 2102 * nested_vmx_prepare_msr_bitmap. We should not touch the
15d45071
AR		 2103 * vmcs02.msr_bitmap here since it gets completely overwritten
2104 * in the merging.
2105 */
2106 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2107 MSR_TYPE_W);
2108 break;
468d472f 2109 case MSR_IA32_CR_PAT:
d28f4290
SC		 2110 if (!kvm_pat_valid(data))
2111 return 1;
2112
142e4be7
SC		 2113 if (is_guest_mode(vcpu) &&
2114 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2115 get_vmcs12(vcpu)->guest_ia32_pat = data;
2116
468d472f
SY		 2117 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2118 vmcs_write64(GUEST_IA32_PAT, data);
2119 vcpu->arch.pat = data;
2120 break;
2121 }
8fe8ab46 2122 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2123 break;
ba904635
WA		 2124 case MSR_IA32_TSC_ADJUST:
2125 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2126 break;
c45dcc71
AR		 2127 case MSR_IA32_MCG_EXT_CTL:
2128 if ((!msr_info->host_initiated &&
2129 !(to_vmx(vcpu)->msr_ia32_feature_control &
32ad73db 2130 FEAT_CTL_LMCE_ENABLED)) ||
c45dcc71
AR		 2131 (data & ~MCG_EXT_CTL_LMCE_EN))
2132 return 1;
2133 vcpu->arch.mcg_ext_ctl = data;
2134 break;
32ad73db 2135 case MSR_IA32_FEAT_CTL:
37e4c997 2136 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3b84080b 2137 (to_vmx(vcpu)->msr_ia32_feature_control &
32ad73db 2138 FEAT_CTL_LOCKED && !msr_info->host_initiated))
cae50139 2139 return 1;
3b84080b 2140 vmx->msr_ia32_feature_control = data;
cae50139
JK		 2141 if (msr_info->host_initiated && data == 0)
2142 vmx_leave_nested(vcpu);
2143 break;
2144 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
62cc6b9d
DM		 2145 if (!msr_info->host_initiated)
2146 return 1; /* they are read-only */
2147 if (!nested_vmx_allowed(vcpu))
2148 return 1;
2149 return vmx_set_vmx_msr(vcpu, msr_index, data);
bf8c55d8
CP		 2150 case MSR_IA32_RTIT_CTL:
2151 if ((pt_mode != PT_MODE_HOST_GUEST) ||
ee85dec2
LK		 2152 vmx_rtit_ctl_check(vcpu, data) ||
2153 vmx->nested.vmxon)
bf8c55d8
CP		 2154 return 1;
2155 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2156 vmx->pt_desc.guest.ctl = data;
b08c2896 2157 pt_update_intercept_for_msr(vmx);
bf8c55d8
CP		 2158 break;
2159 case MSR_IA32_RTIT_STATUS:
e348ac7c
SC		 2160 if (!pt_can_write_msr(vmx))
2161 return 1;
2162 if (data & MSR_IA32_RTIT_STATUS_MASK)
bf8c55d8
CP		 2163 return 1;
2164 vmx->pt_desc.guest.status = data;
2165 break;
2166 case MSR_IA32_RTIT_CR3_MATCH:
e348ac7c
SC		 2167 if (!pt_can_write_msr(vmx))
2168 return 1;
2169 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2170 PT_CAP_cr3_filtering))
bf8c55d8
CP		 2171 return 1;
2172 vmx->pt_desc.guest.cr3_match = data;
2173 break;
2174 case MSR_IA32_RTIT_OUTPUT_BASE:
e348ac7c
SC		 2175 if (!pt_can_write_msr(vmx))
2176 return 1;
2177 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2178 PT_CAP_topa_output) &&
2179 !intel_pt_validate_cap(vmx->pt_desc.caps,
2180 PT_CAP_single_range_output))
2181 return 1;
2182 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK)
bf8c55d8
CP		 2183 return 1;
2184 vmx->pt_desc.guest.output_base = data;
2185 break;
2186 case MSR_IA32_RTIT_OUTPUT_MASK:
e348ac7c
SC		 2187 if (!pt_can_write_msr(vmx))
2188 return 1;
2189 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2190 PT_CAP_topa_output) &&
2191 !intel_pt_validate_cap(vmx->pt_desc.caps,
2192 PT_CAP_single_range_output))
bf8c55d8
CP		 2193 return 1;
2194 vmx->pt_desc.guest.output_mask = data;
2195 break;
2196 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
e348ac7c
SC		 2197 if (!pt_can_write_msr(vmx))
2198 return 1;
bf8c55d8 2199 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
e348ac7c
SC		 2200 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2201 PT_CAP_num_address_ranges))
bf8c55d8 2202 return 1;
fe6ed369 2203 if (is_noncanonical_address(data, vcpu))
bf8c55d8
CP		 2204 return 1;
2205 if (index % 2)
2206 vmx->pt_desc.guest.addr_b[index / 2] = data;
2207 else
2208 vmx->pt_desc.guest.addr_a[index / 2] = data;
2209 break;
4e47c7a6 2210 case MSR_TSC_AUX:
d6321d49
RK		 2211 if (!msr_info->host_initiated &&
2212 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4e47c7a6
SY		 2213 return 1;
2214 /* Check reserved bit, higher 32 bits should be zero */
2215 if ((data >> 32) != 0)
2216 return 1;
c11f83e0
PB		 2217 goto find_shared_msr;
2218
6aa8b732 2219 default:
c11f83e0 2220 find_shared_msr:
8b9cf98c 2221 msr = find_msr_entry(vmx, msr_index);
b07a5c53
PB		 2222 if (msr)
2223 ret = vmx_set_guest_msr(vmx, msr, data);
2224 else
2225 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2226 }
2227
2cc51560 2228 return ret;
6aa8b732
AK		 2229}
2230
5fdbf976 2231static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2232{
cb3c1e2f
SC		 2233 kvm_register_mark_available(vcpu, reg);
2234
5fdbf976
MT		 2235 switch (reg) {
2236 case VCPU_REGS_RSP:
2237 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2238 break;
2239 case VCPU_REGS_RIP:
2240 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2241 break;
6de4f3ad
AK		 2242 case VCPU_EXREG_PDPTR:
2243 if (enable_ept)
2244 ept_save_pdptrs(vcpu);
2245 break;
34059c25
SC		 2246 case VCPU_EXREG_CR3:
2247 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2248 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2249 break;
5fdbf976 2250 default:
34059c25 2251 WARN_ON_ONCE(1);
5fdbf976
MT		 2252 break;
2253 }
6aa8b732
AK		 2254}
2255
6aa8b732
AK		 2256static __init int cpu_has_kvm_support(void)
2257{
6210e37b 2258 return cpu_has_vmx();
6aa8b732
AK		 2259}
2260
2261static __init int vmx_disabled_by_bios(void)
2262{
a4d0b2fd
SC		 2263 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2264 !boot_cpu_has(X86_FEATURE_VMX);
6aa8b732
AK		 2265}
2266
7725b894
DX		 2267static void kvm_cpu_vmxon(u64 addr)
2268{
fe0e80be 2269 cr4_set_bits(X86_CR4_VMXE);
1c5ac21a
AS		 2270 intel_pt_handle_vmx(1);
2271
4b1e5478 2272 asm volatile ("vmxon %0" : : "m"(addr));
7725b894
DX		 2273}
2274
13a34e06 2275static int hardware_enable(void)
6aa8b732
AK		 2276{
2277 int cpu = raw_smp_processor_id();
2278 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 2279
1e02ce4c 2280 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 2281 return -EBUSY;
2282
773e8a04
VK		 2283 /*
2284 * This can happen if we hot-added a CPU but failed to allocate
2285 * VP assist page for it.
2286 */
2287 if (static_branch_unlikely(&enable_evmcs) &&
2288 !hv_get_vp_assist_page(cpu))
2289 return -EFAULT;
2290
d462b819 2291 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
bf9f6ac8
FW		 2292 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2293 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8f536b76
ZY		 2294
2295 /*
2296 * Now we can enable the vmclear operation in kdump
2297 * since the loaded_vmcss_on_cpu list on this cpu
2298 * has been initialized.
2299 *
2300 * Though the cpu is not in VMX operation now, there
2301 * is no problem to enable the vmclear operation
2302 * for the loaded_vmcss_on_cpu list is empty!
2303 */
2304 crash_enable_local_vmclear(cpu);
2305
fe0e80be 2306 kvm_cpu_vmxon(phys_addr);
fdf288bf
DH		 2307 if (enable_ept)
2308 ept_sync_global();
10474ae8
AG		 2309
2310 return 0;
6aa8b732
AK		 2311}
2312
d462b819 2313static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2314{
2315 int cpu = raw_smp_processor_id();
d462b819 2316 struct loaded_vmcs *v, *n;
543e4243 2317
d462b819
NHE		 2318 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2319 loaded_vmcss_on_cpu_link)
2320 __loaded_vmcs_clear(v);
543e4243
AK		 2321}
2322
710ff4a8
EH		 2323
2324/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2325 * tricks.
2326 */
2327static void kvm_cpu_vmxoff(void)
6aa8b732 2328{
4b1e5478 2329 asm volatile (__ex("vmxoff"));
1c5ac21a
AS		 2330
2331 intel_pt_handle_vmx(0);
fe0e80be 2332 cr4_clear_bits(X86_CR4_VMXE);
6aa8b732
AK		 2333}
2334
13a34e06 2335static void hardware_disable(void)
710ff4a8 2336{
fe0e80be
DH		 2337 vmclear_local_loaded_vmcss();
2338 kvm_cpu_vmxoff();
710ff4a8
EH		 2339}
2340
7a57c09b
SC		 2341/*
2342 * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
2343 * directly instead of going through cpu_has(), to ensure KVM is trapping
2344 * ENCLS whenever it's supported in hardware. It does not matter whether
2345 * the host OS supports or has enabled SGX.
2346 */
2347static bool cpu_has_sgx(void)
2348{
2349 return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
2350}
2351
1c3d14fe 2352static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2353 u32 msr, u32 *result)
1c3d14fe
YS		 2354{
2355 u32 vmx_msr_low, vmx_msr_high;
2356 u32 ctl = ctl_min | ctl_opt;
2357
2358 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2359
2360 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2361 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2362
2363 /* Ensure minimum (required) set of control bits are supported. */
2364 if (ctl_min & ~ctl)
002c7f7c 2365 return -EIO;
1c3d14fe
YS		 2366
2367 *result = ctl;
2368 return 0;
2369}
2370
7caaa711
SC		 2371static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2372 struct vmx_capability *vmx_cap)
6aa8b732
AK		 2373{
2374 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2375 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2376 u32 _pin_based_exec_control = 0;
2377 u32 _cpu_based_exec_control = 0;
f78e0e2e 2378 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2379 u32 _vmexit_control = 0;
2380 u32 _vmentry_control = 0;
2381
1389309c 2382 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
10166744 2383 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2384#ifdef CONFIG_X86_64
2385 CPU_BASED_CR8_LOAD_EXITING |
2386 CPU_BASED_CR8_STORE_EXITING |
2387#endif
d56f546d
SY		 2388 CPU_BASED_CR3_LOAD_EXITING |
2389 CPU_BASED_CR3_STORE_EXITING |
8eb73e2d 2390 CPU_BASED_UNCOND_IO_EXITING |
1c3d14fe 2391 CPU_BASED_MOV_DR_EXITING |
5e3d394f 2392 CPU_BASED_USE_TSC_OFFSETTING |
4d5422ce
WL		 2393 CPU_BASED_MWAIT_EXITING |
2394 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2395 CPU_BASED_INVLPG_EXITING |
2396 CPU_BASED_RDPMC_EXITING;
443381a8 2397
f78e0e2e 2398 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2399 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2400 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2401 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2402 &_cpu_based_exec_control) < 0)
002c7f7c 2403 return -EIO;
6e5d865c
YS		 2404#ifdef CONFIG_X86_64
2405 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2406 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2407 ~CPU_BASED_CR8_STORE_EXITING;
2408#endif
f78e0e2e 2409 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2410 min2 = 0;
2411 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2412 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2413 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2414 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2415 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2416 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2417 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
0367f205 2418 SECONDARY_EXEC_DESC |
ad756a16 2419 SECONDARY_EXEC_RDTSCP |
83d4c286 2420 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2421 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 2422 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 2423 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 2424 SECONDARY_EXEC_XSAVES |
736fdf72
DH		 2425 SECONDARY_EXEC_RDSEED_EXITING |
2426 SECONDARY_EXEC_RDRAND_EXITING |
8b3e34e4 2427 SECONDARY_EXEC_ENABLE_PML |
2a499e49 2428 SECONDARY_EXEC_TSC_SCALING |
e69e72fa 2429 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
f99e3daf
CP		 2430 SECONDARY_EXEC_PT_USE_GPA |
2431 SECONDARY_EXEC_PT_CONCEAL_VMX |
7a57c09b
SC		 2432 SECONDARY_EXEC_ENABLE_VMFUNC;
2433 if (cpu_has_sgx())
2434 opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
d56f546d
SY		 2435 if (adjust_vmx_controls(min2, opt2,
2436 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2437 &_cpu_based_2nd_exec_control) < 0)
2438 return -EIO;
2439 }
2440#ifndef CONFIG_X86_64
2441 if (!(_cpu_based_2nd_exec_control &
2442 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2443 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2444#endif
83d4c286
YZ		 2445
2446 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2447 _cpu_based_2nd_exec_control &= ~(
8d14695f 2448 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2449 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2450 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2451
61f1dd90 2452 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
7caaa711 2453 &vmx_cap->ept, &vmx_cap->vpid);
61f1dd90 2454
d56f546d 2455 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2456 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2457 enabled */
5fff7d27
GN		 2458 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2459 CPU_BASED_CR3_STORE_EXITING |
2460 CPU_BASED_INVLPG_EXITING);
7caaa711
SC		 2461 } else if (vmx_cap->ept) {
2462 vmx_cap->ept = 0;
61f1dd90
WL		 2463 pr_warn_once("EPT CAP should not exist if not support "
2464 "1-setting enable EPT VM-execution control\n");
2465 }
2466 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
7caaa711
SC		 2467 vmx_cap->vpid) {
2468 vmx_cap->vpid = 0;
61f1dd90
WL		 2469 pr_warn_once("VPID CAP should not exist if not support "
2470 "1-setting enable VPID VM-execution control\n");
d56f546d 2471 }
1c3d14fe 2472
91fa0f8e 2473 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2474#ifdef CONFIG_X86_64
2475 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2476#endif
c73da3fc 2477 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
c73da3fc
SC		 2478 VM_EXIT_LOAD_IA32_PAT |
2479 VM_EXIT_LOAD_IA32_EFER |
f99e3daf
CP		 2480 VM_EXIT_CLEAR_BNDCFGS |
2481 VM_EXIT_PT_CONCEAL_PIP |
2482 VM_EXIT_CLEAR_IA32_RTIT_CTL;
1c3d14fe
YS		 2483 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2484 &_vmexit_control) < 0)
002c7f7c 2485 return -EIO;
1c3d14fe 2486
8a1b4392
PB		 2487 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2488 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2489 PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ		 2490 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2491 &_pin_based_exec_control) < 0)
2492 return -EIO;
2493
1c17c3e6
PB		 2494 if (cpu_has_broken_vmx_preemption_timer())
2495 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be 2496 if (!(_cpu_based_2nd_exec_control &
91fa0f8e 2497 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
01e439be
YZ		 2498 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2499
c845f9c6 2500 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
c73da3fc
SC		 2501 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2502 VM_ENTRY_LOAD_IA32_PAT |
2503 VM_ENTRY_LOAD_IA32_EFER |
f99e3daf
CP		 2504 VM_ENTRY_LOAD_BNDCFGS |
2505 VM_ENTRY_PT_CONCEAL_PIP |
2506 VM_ENTRY_LOAD_IA32_RTIT_CTL;
1c3d14fe
YS		 2507 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2508 &_vmentry_control) < 0)
002c7f7c 2509 return -EIO;
6aa8b732 2510
c73da3fc
SC		 2511 /*
2512 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2513 * can't be used due to an errata where VM Exit may incorrectly clear
2514 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2515 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2516 */
2517 if (boot_cpu_data.x86 == 0x6) {
2518 switch (boot_cpu_data.x86_model) {
2519 case 26: /* AAK155 */
2520 case 30: /* AAP115 */
2521 case 37: /* AAT100 */
2522 case 44: /* BC86,AAY89,BD102 */
2523 case 46: /* BA97 */
85ba2b16 2524 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
c73da3fc
SC		 2525 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2526 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2527 "does not work properly. Using workaround\n");
2528 break;
2529 default:
2530 break;
2531 }
2532 }
2533
2534
c68876fd 2535 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2536
2537 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2538 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2539 return -EIO;
1c3d14fe
YS		 2540
2541#ifdef CONFIG_X86_64
2542 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2543 if (vmx_msr_high & (1u<<16))
002c7f7c 2544 return -EIO;
1c3d14fe
YS		 2545#endif
2546
2547 /* Require Write-Back (WB) memory type for VMCS accesses. */
2548 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2549 return -EIO;
1c3d14fe 2550
002c7f7c 2551 vmcs_conf->size = vmx_msr_high & 0x1fff;
16cb0255 2552 vmcs_conf->order = get_order(vmcs_conf->size);
9ac7e3e8 2553 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
773e8a04 2554
2307af1c 2555 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2556
002c7f7c
YS		 2557 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2558 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2559 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2560 vmcs_conf->vmexit_ctrl = _vmexit_control;
2561 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2562
773e8a04
VK		 2563 if (static_branch_unlikely(&enable_evmcs))
2564 evmcs_sanitize_exec_ctrls(vmcs_conf);
2565
1c3d14fe 2566 return 0;
c68876fd 2567}
6aa8b732 2568
41836839 2569struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
6aa8b732
AK		 2570{
2571 int node = cpu_to_node(cpu);
2572 struct page *pages;
2573 struct vmcs *vmcs;
2574
41836839 2575 pages = __alloc_pages_node(node, flags, vmcs_config.order);
6aa8b732
AK		 2576 if (!pages)
2577 return NULL;
2578 vmcs = page_address(pages);
1c3d14fe 2579 memset(vmcs, 0, vmcs_config.size);
2307af1c
LA		 2580
2581 /* KVM supports Enlightened VMCS v1 only */
2582 if (static_branch_unlikely(&enable_evmcs))
392b2f25 2583 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2307af1c 2584 else
392b2f25 2585 vmcs->hdr.revision_id = vmcs_config.revision_id;
2307af1c 2586
491a6038
LA		 2587 if (shadow)
2588 vmcs->hdr.shadow_vmcs = 1;
6aa8b732
AK		 2589 return vmcs;
2590}
2591
89b0c9f5 2592void free_vmcs(struct vmcs *vmcs)
6aa8b732 2593{
1c3d14fe 2594 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2595}
2596
d462b819
NHE		 2597/*
2598 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2599 */
89b0c9f5 2600void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
d462b819
NHE		 2601{
2602 if (!loaded_vmcs->vmcs)
2603 return;
2604 loaded_vmcs_clear(loaded_vmcs);
2605 free_vmcs(loaded_vmcs->vmcs);
2606 loaded_vmcs->vmcs = NULL;
904e14fb
PB		 2607 if (loaded_vmcs->msr_bitmap)
2608 free_page((unsigned long)loaded_vmcs->msr_bitmap);
355f4fb1 2609 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
d462b819
NHE		 2610}
2611
89b0c9f5 2612int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
f21f165e 2613{
491a6038 2614 loaded_vmcs->vmcs = alloc_vmcs(false);
f21f165e
PB		 2615 if (!loaded_vmcs->vmcs)
2616 return -ENOMEM;
2617
2618 loaded_vmcs->shadow_vmcs = NULL;
804939ea 2619 loaded_vmcs->hv_timer_soft_disabled = false;
f21f165e 2620 loaded_vmcs_init(loaded_vmcs);
904e14fb
PB		 2621
2622 if (cpu_has_vmx_msr_bitmap()) {
41836839
BG		 2623 loaded_vmcs->msr_bitmap = (unsigned long *)
2624 __get_free_page(GFP_KERNEL_ACCOUNT);
904e14fb
PB		 2625 if (!loaded_vmcs->msr_bitmap)
2626 goto out_vmcs;
2627 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
ceef7d10 2628
1f008e11
AB		 2629 if (IS_ENABLED(CONFIG_HYPERV) &&
2630 static_branch_unlikely(&enable_evmcs) &&
ceef7d10
VK		 2631 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2632 struct hv_enlightened_vmcs *evmcs =
2633 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2634
2635 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2636 }
904e14fb 2637 }
d7ee039e
SC		 2638
2639 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
3af80fec
SC		 2640 memset(&loaded_vmcs->controls_shadow, 0,
2641 sizeof(struct vmcs_controls_shadow));
d7ee039e 2642
f21f165e 2643 return 0;
904e14fb
PB		 2644
2645out_vmcs:
2646 free_loaded_vmcs(loaded_vmcs);
2647 return -ENOMEM;
f21f165e
PB		 2648}
2649
39959588 2650static void free_kvm_area(void)
6aa8b732
AK		 2651{
2652 int cpu;
2653
3230bb47 2654 for_each_possible_cpu(cpu) {
6aa8b732 2655 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2656 per_cpu(vmxarea, cpu) = NULL;
2657 }
6aa8b732
AK		 2658}
2659
6aa8b732
AK		 2660static __init int alloc_kvm_area(void)
2661{
2662 int cpu;
2663
3230bb47 2664 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2665 struct vmcs *vmcs;
2666
41836839 2667 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
6aa8b732
AK		 2668 if (!vmcs) {
2669 free_kvm_area();
2670 return -ENOMEM;
2671 }
2672
2307af1c
LA		 2673 /*
2674 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2675 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2676 * revision_id reported by MSR_IA32_VMX_BASIC.
2677 *
312a4661 2678 * However, even though not explicitly documented by
2307af1c
LA		 2679 * TLFS, VMXArea passed as VMXON argument should
2680 * still be marked with revision_id reported by
2681 * physical CPU.
2682 */
2683 if (static_branch_unlikely(&enable_evmcs))
392b2f25 2684 vmcs->hdr.revision_id = vmcs_config.revision_id;
2307af1c 2685
6aa8b732
AK		 2686 per_cpu(vmxarea, cpu) = vmcs;
2687 }
2688 return 0;
2689}
2690
91b0aa2c 2691static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 2692 struct kvm_segment *save)
6aa8b732 2693{
d99e4152
GN		 2694 if (!emulate_invalid_guest_state) {
2695 /*
2696 * CS and SS RPL should be equal during guest entry according
2697 * to VMX spec, but in reality it is not always so. Since vcpu
2698 * is in the middle of the transition from real mode to
2699 * protected mode it is safe to assume that RPL 0 is a good
2700 * default value.
2701 */
2702 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA		 2703 save->selector &= ~SEGMENT_RPL_MASK;
2704 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 2705 save->s = 1;
6aa8b732 2706 }
d99e4152 2707 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 2708}
2709
2710static void enter_pmode(struct kvm_vcpu *vcpu)
2711{
2712 unsigned long flags;
a89a8fb9 2713 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2714
d99e4152
GN		 2715 /*
2716 * Update real mode segment cache. It may be not up-to-date if sement
2717 * register was written while vcpu was in a guest mode.
2718 */
2719 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2720 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2721 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2722 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2723 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2724 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2725
7ffd92c5 2726 vmx->rmode.vm86_active = 0;
6aa8b732 2727
f5f7b2fe 2728 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2729
2730 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2731 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2732 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2733 vmcs_writel(GUEST_RFLAGS, flags);
2734
66aee91a
RR		 2735 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2736 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2737
2738 update_exception_bitmap(vcpu);
2739
91b0aa2c
GN		 2740 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2741 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2742 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2743 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2744 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2745 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 2746}
2747
f5f7b2fe 2748static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2749{
772e0318 2750 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 2751 struct kvm_segment var = *save;
2752
2753 var.dpl = 0x3;
2754 if (seg == VCPU_SREG_CS)
2755 var.type = 0x3;
2756
2757 if (!emulate_invalid_guest_state) {
2758 var.selector = var.base >> 4;
2759 var.base = var.base & 0xffff0;
2760 var.limit = 0xffff;
2761 var.g = 0;
2762 var.db = 0;
2763 var.present = 1;
2764 var.s = 1;
2765 var.l = 0;
2766 var.unusable = 0;
2767 var.type = 0x3;
2768 var.avl = 0;
2769 if (save->base & 0xf)
2770 printk_once(KERN_WARNING "kvm: segment base is not "
2771 "paragraph aligned when entering "
2772 "protected mode (seg=%d)", seg);
2773 }
6aa8b732 2774
d99e4152 2775 vmcs_write16(sf->selector, var.selector);
96794e4e 2776 vmcs_writel(sf->base, var.base);
d99e4152
GN		 2777 vmcs_write32(sf->limit, var.limit);
2778 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 2779}
2780
2781static void enter_rmode(struct kvm_vcpu *vcpu)
2782{
2783 unsigned long flags;
a89a8fb9 2784 struct vcpu_vmx *vmx = to_vmx(vcpu);
40bbb9d0 2785 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
6aa8b732 2786
f5f7b2fe
AK		 2787 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2788 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2789 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2790 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2791 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 2792 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2793 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 2794
7ffd92c5 2795 vmx->rmode.vm86_active = 1;
6aa8b732 2796
776e58ea
GN		 2797 /*
2798 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 2799 * vcpu. Warn the user that an update is overdue.
776e58ea 2800 */
40bbb9d0 2801 if (!kvm_vmx->tss_addr)
776e58ea
GN		 2802 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2803 "called before entering vcpu\n");
776e58ea 2804
2fb92db1
AK		 2805 vmx_segment_cache_clear(vmx);
2806
40bbb9d0 2807 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
6aa8b732 2808 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2809 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2810
2811 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2812 vmx->rmode.save_rflags = flags;
6aa8b732 2813
053de044 2814 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2815
2816 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2817 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2818 update_exception_bitmap(vcpu);
2819
d99e4152
GN		 2820 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2821 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2822 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2823 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2824 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2825 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 2826
8668a3c4 2827 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2828}
2829
97b7ead3 2830void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
401d10de
AS		 2831{
2832 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2833 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2834
2835 if (!msr)
2836 return;
401d10de 2837
f6801dff 2838 vcpu->arch.efer = efer;
401d10de 2839 if (efer & EFER_LMA) {
2961e876 2840 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 2841 msr->data = efer;
2842 } else {
2961e876 2843 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 2844
2845 msr->data = efer & ~EFER_LME;
2846 }
2847 setup_msrs(vmx);
2848}
2849
05b3e0c2 2850#ifdef CONFIG_X86_64
6aa8b732
AK		 2851
2852static void enter_lmode(struct kvm_vcpu *vcpu)
2853{
2854 u32 guest_tr_ar;
2855
2fb92db1
AK		 2856 vmx_segment_cache_clear(to_vmx(vcpu));
2857
6aa8b732 2858 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 2859 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2860 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2861 __func__);
6aa8b732 2862 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL		 2863 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2864 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 2865 }
da38f438 2866 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2867}
2868
2869static void exit_lmode(struct kvm_vcpu *vcpu)
2870{
2961e876 2871 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 2872 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2873}
2874
2875#endif
2876
faff8758
JS		 2877static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2878{
2879 int vpid = to_vmx(vcpu)->vpid;
2880
2881 if (!vpid_sync_vcpu_addr(vpid, addr))
2882 vpid_sync_context(vpid);
2883
2884 /*
2885 * If VPIDs are not supported or enabled, then the above is a no-op.
2886 * But we don't really need a TLB flush in that case anyway, because
2887 * each VM entry/exit includes an implicit flush when VPID is 0.
2888 */
2889}
2890
e8467fda
AK		 2891static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2892{
2893 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2894
2895 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2896 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2897}
2898
25c4c276 2899static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2900{
fc78f519
AK		 2901 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2902
2903 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2904 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2905}
2906
1439442c
SY		 2907static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2908{
d0d538b9
GN		 2909 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2910
cb3c1e2f 2911 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
6de4f3ad
AK		 2912 return;
2913
bf03d4f9 2914 if (is_pae_paging(vcpu)) {
d0d538b9
GN		 2915 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2916 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2917 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2918 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 2919 }
2920}
2921
97b7ead3 2922void ept_save_pdptrs(struct kvm_vcpu *vcpu)
8f5d549f 2923{
d0d538b9
GN		 2924 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2925
bf03d4f9 2926 if (is_pae_paging(vcpu)) {
d0d538b9
GN		 2927 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2928 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2929 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2930 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2931 }
6de4f3ad 2932
cb3c1e2f 2933 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
8f5d549f
AK		 2934}
2935
1439442c
SY		 2936static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2937 unsigned long cr0,
2938 struct kvm_vcpu *vcpu)
2939{
2183f564
SC		 2940 struct vcpu_vmx *vmx = to_vmx(vcpu);
2941
cb3c1e2f 2942 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
34059c25 2943 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
1439442c
SY		 2944 if (!(cr0 & X86_CR0_PG)) {
2945 /* From paging/starting to nonpaging */
2183f564
SC		 2946 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2947 CPU_BASED_CR3_STORE_EXITING);
1439442c 2948 vcpu->arch.cr0 = cr0;
fc78f519 2949 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2950 } else if (!is_paging(vcpu)) {
2951 /* From nonpaging to paging */
2183f564
SC		 2952 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2953 CPU_BASED_CR3_STORE_EXITING);
1439442c 2954 vcpu->arch.cr0 = cr0;
fc78f519 2955 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2956 }
95eb84a7
SY		 2957
2958 if (!(cr0 & X86_CR0_WP))
2959 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2960}
2961
97b7ead3 2962void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
6aa8b732 2963{
7ffd92c5 2964 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 2965 unsigned long hw_cr0;
2966
3de6347b 2967 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3a624e29 2968 if (enable_unrestricted_guest)
5037878e 2969 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 2970 else {
5037878e 2971 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 2972
218e763f
GN		 2973 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2974 enter_pmode(vcpu);
6aa8b732 2975
218e763f
GN		 2976 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2977 enter_rmode(vcpu);
2978 }
6aa8b732 2979
05b3e0c2 2980#ifdef CONFIG_X86_64
f6801dff 2981 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2982 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2983 enter_lmode(vcpu);
707d92fa 2984 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2985 exit_lmode(vcpu);
2986 }
2987#endif
2988
b4d18517 2989 if (enable_ept && !enable_unrestricted_guest)
1439442c
SY		 2990 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2991
6aa8b732 2992 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2993 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2994 vcpu->arch.cr0 = cr0;
14168786
GN		 2995
2996 /* depends on vcpu->arch.cr0 to be set to a new value */
2997 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 2998}
2999
855feb67
YZ		 3000static int get_ept_level(struct kvm_vcpu *vcpu)
3001{
148d735e
SC		 3002 /* Nested EPT currently only supports 4-level walks. */
3003 if (is_guest_mode(vcpu) && nested_cpu_has_ept(get_vmcs12(vcpu)))
3004 return 4;
855feb67
YZ		 3005 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
3006 return 5;
3007 return 4;
3008}
3009
89b0c9f5 3010u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
1439442c 3011{
855feb67
YZ		 3012 u64 eptp = VMX_EPTP_MT_WB;
3013
3014 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
1439442c 3015
995f00a6
PF		 3016 if (enable_ept_ad_bits &&
3017 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
bb97a016 3018 eptp |= VMX_EPTP_AD_ENABLE_BIT;
1439442c
SY		 3019 eptp |= (root_hpa & PAGE_MASK);
3020
3021 return eptp;
3022}
3023
97b7ead3 3024void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
6aa8b732 3025{
877ad952 3026 struct kvm *kvm = vcpu->kvm;
04f11ef4 3027 bool update_guest_cr3 = true;
1439442c
SY		 3028 unsigned long guest_cr3;
3029 u64 eptp;
3030
3031 guest_cr3 = cr3;
089d034e 3032 if (enable_ept) {
995f00a6 3033 eptp = construct_eptp(vcpu, cr3);
1439442c 3034 vmcs_write64(EPT_POINTER, eptp);
877ad952
TL		 3035
3036 if (kvm_x86_ops->tlb_remote_flush) {
3037 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3038 to_vmx(vcpu)->ept_pointer = eptp;
3039 to_kvm_vmx(kvm)->ept_pointers_match
3040 = EPT_POINTERS_CHECK;
3041 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3042 }
3043
04f11ef4
SC		 3044 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */
3045 if (is_guest_mode(vcpu))
3046 update_guest_cr3 = false;
b17b7436 3047 else if (!enable_unrestricted_guest && !is_paging(vcpu))
877ad952 3048 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
b17b7436
SC		 3049 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3050 guest_cr3 = vcpu->arch.cr3;
3051 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3052 update_guest_cr3 = false;
7c93be44 3053 ept_load_pdptrs(vcpu);
1439442c
SY		 3054 }
3055
04f11ef4
SC		 3056 if (update_guest_cr3)
3057 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3058}
3059
97b7ead3 3060int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3061{
fe7f895d 3062 struct vcpu_vmx *vmx = to_vmx(vcpu);
085e68ee
BS		 3063 /*
3064 * Pass through host's Machine Check Enable value to hw_cr4, which
3065 * is in force while we are in guest mode. Do not let guests control
3066 * this bit, even if host CR4.MCE == 0.
3067 */
5dc1f044
SC		 3068 unsigned long hw_cr4;
3069
3070 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3071 if (enable_unrestricted_guest)
3072 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
fe7f895d 3073 else if (vmx->rmode.vm86_active)
5dc1f044
SC		 3074 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3075 else
3076 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
1439442c 3077
64f7a115
SC		 3078 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3079 if (cr4 & X86_CR4_UMIP) {
fe7f895d 3080 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
64f7a115
SC		 3081 hw_cr4 &= ~X86_CR4_UMIP;
3082 } else if (!is_guest_mode(vcpu) ||
fe7f895d
SC		 3083 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3084 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3085 }
64f7a115 3086 }
0367f205 3087
5e1746d6
NHE		 3088 if (cr4 & X86_CR4_VMXE) {
3089 /*
3090 * To use VMXON (and later other VMX instructions), a guest
3091 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3092 * So basically the check on whether to allow nested VMX
5bea5123
PB		 3093 * is here. We operate under the default treatment of SMM,
3094 * so VMX cannot be enabled under SMM.
5e1746d6 3095 */
5bea5123 3096 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
5e1746d6 3097 return 1;
1a0d74e6 3098 }
3899152c 3099
fe7f895d 3100 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5e1746d6
NHE		 3101 return 1;
3102
ad312c7c 3103 vcpu->arch.cr4 = cr4;
5dc1f044
SC		 3104
3105 if (!enable_unrestricted_guest) {
3106 if (enable_ept) {
3107 if (!is_paging(vcpu)) {
3108 hw_cr4 &= ~X86_CR4_PAE;
3109 hw_cr4 |= X86_CR4_PSE;
3110 } else if (!(cr4 & X86_CR4_PAE)) {
3111 hw_cr4 &= ~X86_CR4_PAE;
3112 }
bc23008b 3113 }
1439442c 3114
656ec4a4 3115 /*
ddba2628
HH		 3116 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3117 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3118 * to be manually disabled when guest switches to non-paging
3119 * mode.
3120 *
3121 * If !enable_unrestricted_guest, the CPU is always running
3122 * with CR0.PG=1 and CR4 needs to be modified.
3123 * If enable_unrestricted_guest, the CPU automatically
3124 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
656ec4a4 3125 */
5dc1f044
SC		 3126 if (!is_paging(vcpu))
3127 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3128 }
656ec4a4 3129
1439442c
SY		 3130 vmcs_writel(CR4_READ_SHADOW, cr4);
3131 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3132 return 0;
6aa8b732
AK		 3133}
3134
97b7ead3 3135void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
6aa8b732 3136{
a9179499 3137 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3138 u32 ar;
3139
c6ad1153 3140 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3141 *var = vmx->rmode.segs[seg];
a9179499 3142 if (seg == VCPU_SREG_TR
2fb92db1 3143 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3144 return;
1390a28b
AK		 3145 var->base = vmx_read_guest_seg_base(vmx, seg);
3146 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3147 return;
a9179499 3148 }
2fb92db1
AK		 3149 var->base = vmx_read_guest_seg_base(vmx, seg);
3150 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3151 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3152 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3153 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3154 var->type = ar & 15;
3155 var->s = (ar >> 4) & 1;
3156 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3157 /*
3158 * Some userspaces do not preserve unusable property. Since usable
3159 * segment has to be present according to VMX spec we can use present
3160 * property to amend userspace bug by making unusable segment always
3161 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3162 * segment as unusable.
3163 */
3164 var->present = !var->unusable;
6aa8b732
AK		 3165 var->avl = (ar >> 12) & 1;
3166 var->l = (ar >> 13) & 1;
3167 var->db = (ar >> 14) & 1;
3168 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3169}
3170
a9179499
AK		 3171static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3172{
a9179499
AK		 3173 struct kvm_segment s;
3174
3175 if (to_vmx(vcpu)->rmode.vm86_active) {
3176 vmx_get_segment(vcpu, &s, seg);
3177 return s.base;
3178 }
2fb92db1 3179 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3180}
3181
97b7ead3 3182int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3183{
b09408d0
MT		 3184 struct vcpu_vmx *vmx = to_vmx(vcpu);
3185
ae9fedc7 3186 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3187 return 0;
ae9fedc7
PB		 3188 else {
3189 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 3190 return VMX_AR_DPL(ar);
69c73028 3191 }
69c73028
AK		 3192}
3193
653e3108 3194static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3195{
6aa8b732
AK		 3196 u32 ar;
3197
f0495f9b 3198 if (var->unusable || !var->present)
6aa8b732
AK		 3199 ar = 1 << 16;
3200 else {
3201 ar = var->type & 15;
3202 ar |= (var->s & 1) << 4;
3203 ar |= (var->dpl & 3) << 5;
3204 ar |= (var->present & 1) << 7;
3205 ar |= (var->avl & 1) << 12;
3206 ar |= (var->l & 1) << 13;
3207 ar |= (var->db & 1) << 14;
3208 ar |= (var->g & 1) << 15;
3209 }
653e3108
AK		 3210
3211 return ar;
3212}
3213
97b7ead3 3214void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
653e3108 3215{
7ffd92c5 3216 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3217 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3218
2fb92db1
AK		 3219 vmx_segment_cache_clear(vmx);
3220
1ecd50a9
GN		 3221 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3222 vmx->rmode.segs[seg] = *var;
3223 if (seg == VCPU_SREG_TR)
3224 vmcs_write16(sf->selector, var->selector);
3225 else if (var->s)
3226 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3227 goto out;
653e3108 3228 }
1ecd50a9 3229
653e3108
AK		 3230 vmcs_writel(sf->base, var->base);
3231 vmcs_write32(sf->limit, var->limit);
3232 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3233
3234 /*
3235 * Fix the "Accessed" bit in AR field of segment registers for older
3236 * qemu binaries.
3237 * IA32 arch specifies that at the time of processor reset the
3238 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3239 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3240 * state vmexit when "unrestricted guest" mode is turned on.
3241 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3242 * tree. Newer qemu binaries with that qemu fix would not need this
3243 * kvm hack.
3244 */
3245 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3246 var->type |= 0x1; /* Accessed */
3a624e29 3247
f924d66d 3248 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3249
3250out:
98eb2f8b 3251 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3252}
3253
6aa8b732
AK		 3254static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3255{
2fb92db1 3256 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3257
3258 *db = (ar >> 14) & 1;
3259 *l = (ar >> 13) & 1;
3260}
3261
89a27f4d 3262static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3263{
89a27f4d
GN		 3264 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3265 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3266}
3267
89a27f4d 3268static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3269{
89a27f4d
GN		 3270 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3271 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3272}
3273
89a27f4d 3274static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3275{
89a27f4d
GN		 3276 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3277 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3278}
3279
89a27f4d 3280static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3281{
89a27f4d
GN		 3282 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3283 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3284}
3285
648dfaa7
MG		 3286static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3287{
3288 struct kvm_segment var;
3289 u32 ar;
3290
3291 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3292 var.dpl = 0x3;
0647f4aa
GN		 3293 if (seg == VCPU_SREG_CS)
3294 var.type = 0x3;
648dfaa7
MG		 3295 ar = vmx_segment_access_rights(&var);
3296
3297 if (var.base != (var.selector << 4))
3298 return false;
89efbed0 3299 if (var.limit != 0xffff)
648dfaa7 3300 return false;
07f42f5f 3301 if (ar != 0xf3)
648dfaa7
MG		 3302 return false;
3303
3304 return true;
3305}
3306
3307static bool code_segment_valid(struct kvm_vcpu *vcpu)
3308{
3309 struct kvm_segment cs;
3310 unsigned int cs_rpl;
3311
3312 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 3313 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 3314
1872a3f4
AK		 3315 if (cs.unusable)
3316 return false;
4d283ec9 3317 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG		 3318 return false;
3319 if (!cs.s)
3320 return false;
4d283ec9 3321 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3322 if (cs.dpl > cs_rpl)
3323 return false;
1872a3f4 3324 } else {
648dfaa7
MG		 3325 if (cs.dpl != cs_rpl)
3326 return false;
3327 }
3328 if (!cs.present)
3329 return false;
3330
3331 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3332 return true;
3333}
3334
3335static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3336{
3337 struct kvm_segment ss;
3338 unsigned int ss_rpl;
3339
3340 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 3341 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 3342
1872a3f4
AK		 3343 if (ss.unusable)
3344 return true;
3345 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3346 return false;
3347 if (!ss.s)
3348 return false;
3349 if (ss.dpl != ss_rpl) /* DPL != RPL */
3350 return false;
3351 if (!ss.present)
3352 return false;
3353
3354 return true;
3355}
3356
3357static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3358{
3359 struct kvm_segment var;
3360 unsigned int rpl;
3361
3362 vmx_get_segment(vcpu, &var, seg);
b32a9918 3363 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 3364
1872a3f4
AK		 3365 if (var.unusable)
3366 return true;
648dfaa7
MG		 3367 if (!var.s)
3368 return false;
3369 if (!var.present)
3370 return false;
4d283ec9 3371 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG		 3372 if (var.dpl < rpl) /* DPL < RPL */
3373 return false;
3374 }
3375
3376 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3377 * rights flags
3378 */
3379 return true;
3380}
3381
3382static bool tr_valid(struct kvm_vcpu *vcpu)
3383{
3384 struct kvm_segment tr;
3385
3386 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3387
1872a3f4
AK		 3388 if (tr.unusable)
3389 return false;
b32a9918 3390 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 3391 return false;
1872a3f4 3392 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3393 return false;
3394 if (!tr.present)
3395 return false;
3396
3397 return true;
3398}
3399
3400static bool ldtr_valid(struct kvm_vcpu *vcpu)
3401{
3402 struct kvm_segment ldtr;
3403
3404 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3405
1872a3f4
AK		 3406 if (ldtr.unusable)
3407 return true;
b32a9918 3408 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG		 3409 return false;
3410 if (ldtr.type != 2)
3411 return false;
3412 if (!ldtr.present)
3413 return false;
3414
3415 return true;
3416}
3417
3418static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3419{
3420 struct kvm_segment cs, ss;
3421
3422 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3423 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3424
b32a9918
NA		 3425 return ((cs.selector & SEGMENT_RPL_MASK) ==
3426 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG		 3427}
3428
3429/*
3430 * Check if guest state is valid. Returns true if valid, false if
3431 * not.
3432 * We assume that registers are always usable
3433 */
3434static bool guest_state_valid(struct kvm_vcpu *vcpu)
3435{
c5e97c80
GN		 3436 if (enable_unrestricted_guest)
3437 return true;
3438
648dfaa7 3439 /* real mode guest state checks */
f13882d8 3440 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3441 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3442 return false;
3443 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3444 return false;
3445 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3446 return false;
3447 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3448 return false;
3449 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3450 return false;
3451 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3452 return false;
3453 } else {
3454 /* protected mode guest state checks */
3455 if (!cs_ss_rpl_check(vcpu))
3456 return false;
3457 if (!code_segment_valid(vcpu))
3458 return false;
3459 if (!stack_segment_valid(vcpu))
3460 return false;
3461 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3462 return false;
3463 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3464 return false;
3465 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3466 return false;
3467 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3468 return false;
3469 if (!tr_valid(vcpu))
3470 return false;
3471 if (!ldtr_valid(vcpu))
3472 return false;
3473 }
3474 /* TODO:
3475 * - Add checks on RIP
3476 * - Add checks on RFLAGS
3477 */
3478
3479 return true;
3480}
3481
d77c26fc 3482static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3483{
40dcaa9f 3484 gfn_t fn;
195aefde 3485 u16 data = 0;
1f755a82 3486 int idx, r;
6aa8b732 3487
40dcaa9f 3488 idx = srcu_read_lock(&kvm->srcu);
40bbb9d0 3489 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
195aefde
IE		 3490 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3491 if (r < 0)
10589a46 3492 goto out;
195aefde 3493 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3494 r = kvm_write_guest_page(kvm, fn++, &data,
3495 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3496 if (r < 0)
10589a46 3497 goto out;
195aefde
IE		 3498 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3499 if (r < 0)
10589a46 3500 goto out;
195aefde
IE		 3501 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3502 if (r < 0)
10589a46 3503 goto out;
195aefde 3504 data = ~0;
10589a46
MT		 3505 r = kvm_write_guest_page(kvm, fn, &data,
3506 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3507 sizeof(u8));
10589a46 3508out:
40dcaa9f 3509 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 3510 return r;
6aa8b732
AK		 3511}
3512
b7ebfb05
SY		 3513static int init_rmode_identity_map(struct kvm *kvm)
3514{
40bbb9d0 3515 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
2a5755bb 3516 int i, r = 0;
ba049e93 3517 kvm_pfn_t identity_map_pfn;
b7ebfb05
SY		 3518 u32 tmp;
3519
40bbb9d0 3520 /* Protect kvm_vmx->ept_identity_pagetable_done. */
a255d479
TC		 3521 mutex_lock(&kvm->slots_lock);
3522
40bbb9d0 3523 if (likely(kvm_vmx->ept_identity_pagetable_done))
2a5755bb 3524 goto out;
a255d479 3525
40bbb9d0
SC		 3526 if (!kvm_vmx->ept_identity_map_addr)
3527 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3528 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
a255d479 3529
d8a6e365 3530 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
40bbb9d0 3531 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
f51770ed 3532 if (r < 0)
2a5755bb 3533 goto out;
a255d479 3534
b7ebfb05
SY		 3535 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3536 if (r < 0)
3537 goto out;
3538 /* Set up identity-mapping pagetable for EPT in real mode */
3539 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3540 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3541 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3542 r = kvm_write_guest_page(kvm, identity_map_pfn,
3543 &tmp, i * sizeof(tmp), sizeof(tmp));
3544 if (r < 0)
3545 goto out;
3546 }
40bbb9d0 3547 kvm_vmx->ept_identity_pagetable_done = true;
f51770ed 3548
b7ebfb05 3549out:
a255d479 3550 mutex_unlock(&kvm->slots_lock);
f51770ed 3551 return r;
b7ebfb05
SY		 3552}
3553
6aa8b732
AK		 3554static void seg_setup(int seg)
3555{
772e0318 3556 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3557 unsigned int ar;
6aa8b732
AK		 3558
3559 vmcs_write16(sf->selector, 0);
3560 vmcs_writel(sf->base, 0);
3561 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3562 ar = 0x93;
3563 if (seg == VCPU_SREG_CS)
3564 ar |= 0x08; /* code segment */
3a624e29
NK		 3565
3566 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3567}
3568
f78e0e2e
SY		 3569static int alloc_apic_access_page(struct kvm *kvm)
3570{
4484141a 3571 struct page *page;
f78e0e2e
SY		 3572 int r = 0;
3573
79fac95e 3574 mutex_lock(&kvm->slots_lock);
c24ae0dc 3575 if (kvm->arch.apic_access_page_done)
f78e0e2e 3576 goto out;
1d8007bd
PB		 3577 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3578 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
f78e0e2e
SY		 3579 if (r)
3580 goto out;
72dc67a6 3581
73a6d941 3582 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 3583 if (is_error_page(page)) {
3584 r = -EFAULT;
3585 goto out;
3586 }
3587
c24ae0dc
TC		 3588 /*
3589 * Do not pin the page in memory, so that memory hot-unplug
3590 * is able to migrate it.
3591 */
3592 put_page(page);
3593 kvm->arch.apic_access_page_done = true;
f78e0e2e 3594out:
79fac95e 3595 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3596 return r;
3597}
3598
97b7ead3 3599int allocate_vpid(void)
2384d2b3
SY		 3600{
3601 int vpid;
3602
919818ab 3603 if (!enable_vpid)
991e7a0e 3604 return 0;
2384d2b3
SY		 3605 spin_lock(&vmx_vpid_lock);
3606 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
991e7a0e 3607 if (vpid < VMX_NR_VPIDS)
2384d2b3 3608 __set_bit(vpid, vmx_vpid_bitmap);
991e7a0e
WL		 3609 else
3610 vpid = 0;
2384d2b3 3611 spin_unlock(&vmx_vpid_lock);
991e7a0e 3612 return vpid;
2384d2b3
SY		 3613}
3614
97b7ead3 3615void free_vpid(int vpid)
cdbecfc3 3616{
991e7a0e 3617 if (!enable_vpid || vpid == 0)
cdbecfc3
LJ		 3618 return;
3619 spin_lock(&vmx_vpid_lock);
991e7a0e 3620 __clear_bit(vpid, vmx_vpid_bitmap);
cdbecfc3
LJ		 3621 spin_unlock(&vmx_vpid_lock);
3622}
3623
1e4329ee 3624static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb 3625 u32 msr, int type)
25c5f225 3626{
3e7c73e9 3627 int f = sizeof(unsigned long);
25c5f225
SY		 3628
3629 if (!cpu_has_vmx_msr_bitmap())
3630 return;
3631
ceef7d10
VK		 3632 if (static_branch_unlikely(&enable_evmcs))
3633 evmcs_touch_msr_bitmap();
3634
25c5f225
SY		 3635 /*
3636 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3637 * have the write-low and read-high bitmap offsets the wrong way round.
3638 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3639 */
25c5f225 3640 if (msr <= 0x1fff) {
8d14695f
YZ		 3641 if (type & MSR_TYPE_R)
3642 /* read-low */
3643 __clear_bit(msr, msr_bitmap + 0x000 / f);
3644
3645 if (type & MSR_TYPE_W)
3646 /* write-low */
3647 __clear_bit(msr, msr_bitmap + 0x800 / f);
3648
25c5f225
SY		 3649 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3650 msr &= 0x1fff;
8d14695f
YZ		 3651 if (type & MSR_TYPE_R)
3652 /* read-high */
3653 __clear_bit(msr, msr_bitmap + 0x400 / f);
3654
3655 if (type & MSR_TYPE_W)
3656 /* write-high */
3657 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3658
3659 }
3660}
3661
1e4329ee 3662static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb
PB		 3663 u32 msr, int type)
3664{
3665 int f = sizeof(unsigned long);
3666
3667 if (!cpu_has_vmx_msr_bitmap())
3668 return;
3669
ceef7d10
VK		 3670 if (static_branch_unlikely(&enable_evmcs))
3671 evmcs_touch_msr_bitmap();
3672
904e14fb
PB		 3673 /*
3674 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3675 * have the write-low and read-high bitmap offsets the wrong way round.
3676 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3677 */
3678 if (msr <= 0x1fff) {
3679 if (type & MSR_TYPE_R)
3680 /* read-low */
3681 __set_bit(msr, msr_bitmap + 0x000 / f);
3682
3683 if (type & MSR_TYPE_W)
3684 /* write-low */
3685 __set_bit(msr, msr_bitmap + 0x800 / f);
3686
3687 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3688 msr &= 0x1fff;
3689 if (type & MSR_TYPE_R)
3690 /* read-high */
3691 __set_bit(msr, msr_bitmap + 0x400 / f);
3692
3693 if (type & MSR_TYPE_W)
3694 /* write-high */
3695 __set_bit(msr, msr_bitmap + 0xc00 / f);
3696
3697 }
3698}
3699
1e4329ee 3700static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb
PB		 3701 u32 msr, int type, bool value)
3702{
3703 if (value)
3704 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3705 else
3706 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3707}
3708
904e14fb 3709static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5897297b 3710{
904e14fb
PB		 3711 u8 mode = 0;
3712
3713 if (cpu_has_secondary_exec_ctrls() &&
fe7f895d 3714 (secondary_exec_controls_get(to_vmx(vcpu)) &
904e14fb
PB		 3715 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3716 mode |= MSR_BITMAP_MODE_X2APIC;
3717 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3718 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3719 }
3720
904e14fb 3721 return mode;
8d14695f
YZ		 3722}
3723
904e14fb
PB		 3724static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3725 u8 mode)
8d14695f 3726{
904e14fb
PB		 3727 int msr;
3728
3729 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3730 unsigned word = msr / BITS_PER_LONG;
3731 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3732 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3733 }
3734
3735 if (mode & MSR_BITMAP_MODE_X2APIC) {
3736 /*
3737 * TPR reads and writes can be virtualized even if virtual interrupt
3738 * delivery is not in use.
3739 */
3740 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3741 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3742 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3743 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3744 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3745 }
f6e90f9e 3746 }
5897297b
AK		 3747}
3748
97b7ead3 3749void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
904e14fb
PB		 3750{
3751 struct vcpu_vmx *vmx = to_vmx(vcpu);
3752 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3753 u8 mode = vmx_msr_bitmap_mode(vcpu);
3754 u8 changed = mode ^ vmx->msr_bitmap_mode;
3755
3756 if (!changed)
3757 return;
3758
904e14fb
PB		 3759 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3760 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3761
3762 vmx->msr_bitmap_mode = mode;
3763}
3764
b08c2896
CP		 3765void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3766{
3767 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3768 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3769 u32 i;
3770
3771 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3772 MSR_TYPE_RW, flag);
3773 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3774 MSR_TYPE_RW, flag);
3775 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3776 MSR_TYPE_RW, flag);
3777 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3778 MSR_TYPE_RW, flag);
3779 for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3780 vmx_set_intercept_for_msr(msr_bitmap,
3781 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3782 vmx_set_intercept_for_msr(msr_bitmap,
3783 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3784 }
3785}
3786
e6c67d8c
LA		 3787static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3788{
3789 struct vcpu_vmx *vmx = to_vmx(vcpu);
3790 void *vapic_page;
3791 u32 vppr;
3792 int rvi;
3793
3794 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3795 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
96c66e87 3796 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
e6c67d8c
LA		 3797 return false;
3798
7e712684 3799 rvi = vmx_get_rvi();
e6c67d8c 3800
96c66e87 3801 vapic_page = vmx->nested.virtual_apic_map.hva;
e6c67d8c 3802 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
e6c67d8c
LA		 3803
3804 return ((rvi & 0xf0) > (vppr & 0xf0));
3805}
3806
06a5524f
WV		 3807static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3808 bool nested)
21bc8dc5
RK		 3809{
3810#ifdef CONFIG_SMP
06a5524f
WV		 3811 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3812
21bc8dc5 3813 if (vcpu->mode == IN_GUEST_MODE) {
28b835d6 3814 /*
5753743f
HZ		 3815 * The vector of interrupt to be delivered to vcpu had
3816 * been set in PIR before this function.
3817 *
3818 * Following cases will be reached in this block, and
3819 * we always send a notification event in all cases as
3820 * explained below.
3821 *
3822 * Case 1: vcpu keeps in non-root mode. Sending a
3823 * notification event posts the interrupt to vcpu.
3824 *
3825 * Case 2: vcpu exits to root mode and is still
3826 * runnable. PIR will be synced to vIRR before the
3827 * next vcpu entry. Sending a notification event in
3828 * this case has no effect, as vcpu is not in root
3829 * mode.
28b835d6 3830 *
5753743f
HZ		 3831 * Case 3: vcpu exits to root mode and is blocked.
3832 * vcpu_block() has already synced PIR to vIRR and
3833 * never blocks vcpu if vIRR is not cleared. Therefore,
3834 * a blocked vcpu here does not wait for any requested
3835 * interrupts in PIR, and sending a notification event
3836 * which has no effect is safe here.
28b835d6 3837 */
28b835d6 3838
06a5524f 3839 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
21bc8dc5
RK		 3840 return true;
3841 }
3842#endif
3843 return false;
3844}
3845
705699a1
WV		 3846static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3847 int vector)
3848{
3849 struct vcpu_vmx *vmx = to_vmx(vcpu);
3850
3851 if (is_guest_mode(vcpu) &&
3852 vector == vmx->nested.posted_intr_nv) {
705699a1
WV		 3853 /*
3854 * If a posted intr is not recognized by hardware,
3855 * we will accomplish it in the next vmentry.
3856 */
3857 vmx->nested.pi_pending = true;
3858 kvm_make_request(KVM_REQ_EVENT, vcpu);
6b697711
LA		 3859 /* the PIR and ON have been set by L1. */
3860 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3861 kvm_vcpu_kick(vcpu);
705699a1
WV		 3862 return 0;
3863 }
3864 return -1;
3865}
a20ed54d
YZ		 3866/*
3867 * Send interrupt to vcpu via posted interrupt way.
3868 * 1. If target vcpu is running(non-root mode), send posted interrupt
3869 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3870 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3871 * interrupt from PIR in next vmentry.
3872 */
91a5f413 3873static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
a20ed54d
YZ		 3874{
3875 struct vcpu_vmx *vmx = to_vmx(vcpu);
3876 int r;
3877
705699a1
WV		 3878 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3879 if (!r)
91a5f413
VK		 3880 return 0;
3881
3882 if (!vcpu->arch.apicv_active)
3883 return -1;
705699a1 3884
a20ed54d 3885 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
91a5f413 3886 return 0;
a20ed54d 3887
b95234c8
PB		 3888 /* If a previous notification has sent the IPI, nothing to do. */
3889 if (pi_test_and_set_on(&vmx->pi_desc))
91a5f413 3890 return 0;
b95234c8 3891
06a5524f 3892 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
a20ed54d 3893 kvm_vcpu_kick(vcpu);
91a5f413
VK		 3894
3895 return 0;
a20ed54d
YZ		 3896}
3897
a3a8ff8e
NHE		 3898/*
3899 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3900 * will not change in the lifetime of the guest.
3901 * Note that host-state that does change is set elsewhere. E.g., host-state
3902 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3903 */
97b7ead3 3904void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 3905{
3906 u32 low32, high32;
3907 unsigned long tmpl;
d6e41f11 3908 unsigned long cr0, cr3, cr4;
a3a8ff8e 3909
04ac88ab
AL		 3910 cr0 = read_cr0();
3911 WARN_ON(cr0 & X86_CR0_TS);
3912 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
d6e41f11
AL		 3913
3914 /*
3915 * Save the most likely value for this task's CR3 in the VMCS.
3916 * We can't use __get_current_cr3_fast() because we're not atomic.
3917 */
6c690ee1 3918 cr3 = __read_cr3();
d6e41f11 3919 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
d7ee039e 3920 vmx->loaded_vmcs->host_state.cr3 = cr3;
a3a8ff8e 3921
d974baa3 3922 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 3923 cr4 = cr4_read_shadow();
d974baa3 3924 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
d7ee039e 3925 vmx->loaded_vmcs->host_state.cr4 = cr4;
d974baa3 3926
a3a8ff8e 3927 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3928#ifdef CONFIG_X86_64
3929 /*
3930 * Load null selectors, so we can avoid reloading them in
6d6095bd
SC		 3931 * vmx_prepare_switch_to_host(), in case userspace uses
3932 * the null selectors too (the expected case).
b2da15ac
AK		 3933 */
3934 vmcs_write16(HOST_DS_SELECTOR, 0);
3935 vmcs_write16(HOST_ES_SELECTOR, 0);
3936#else
a3a8ff8e
NHE		 3937 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3938 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3939#endif
a3a8ff8e
NHE		 3940 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3941 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3942
2342080c 3943 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
a3a8ff8e 3944
453eafbe 3945 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
a3a8ff8e
NHE		 3946
3947 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3948 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3949 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3950 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3951
3952 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3953 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3954 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3955 }
5a5e8a15 3956
c73da3fc 3957 if (cpu_has_load_ia32_efer())
5a5e8a15 3958 vmcs_write64(HOST_IA32_EFER, host_efer);
a3a8ff8e
NHE		 3959}
3960
97b7ead3 3961void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
bf8179a0
NHE		 3962{
3963 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3964 if (enable_ept)
3965 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3966 if (is_guest_mode(&vmx->vcpu))
3967 vmx->vcpu.arch.cr4_guest_owned_bits &=
3968 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3969 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3970}
3971
c075c3e4 3972u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
01e439be
YZ		 3973{
3974 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3975
d62caabb 3976 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
01e439be 3977 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
d02fcf50
PB		 3978
3979 if (!enable_vnmi)
3980 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3981
804939ea
SC		 3982 if (!enable_preemption_timer)
3983 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3984
01e439be
YZ		 3985 return pin_based_exec_ctrl;
3986}
3987
d62caabb
AS		 3988static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3989{
3990 struct vcpu_vmx *vmx = to_vmx(vcpu);
3991
c5f2c766 3992 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3ce424e4
RK		 3993 if (cpu_has_secondary_exec_ctrls()) {
3994 if (kvm_vcpu_apicv_active(vcpu))
fe7f895d 3995 secondary_exec_controls_setbit(vmx,
3ce424e4
RK		 3996 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3997 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3998 else
fe7f895d 3999 secondary_exec_controls_clearbit(vmx,
3ce424e4
RK		 4000 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4001 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4002 }
4003
4004 if (cpu_has_vmx_msr_bitmap())
904e14fb 4005 vmx_update_msr_bitmap(vcpu);
d62caabb
AS		 4006}
4007
89b0c9f5
SC		 4008u32 vmx_exec_control(struct vcpu_vmx *vmx)
4009{
4010 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4011
4012 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4013 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4014
4015 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4016 exec_control &= ~CPU_BASED_TPR_SHADOW;
4017#ifdef CONFIG_X86_64
4018 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4019 CPU_BASED_CR8_LOAD_EXITING;
4020#endif
4021 }
4022 if (!enable_ept)
4023 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4024 CPU_BASED_CR3_LOAD_EXITING |
4025 CPU_BASED_INVLPG_EXITING;
4026 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4027 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4028 CPU_BASED_MONITOR_EXITING);
4029 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4030 exec_control &= ~CPU_BASED_HLT_EXITING;
4031 return exec_control;
4032}
4033
4034
80154d77 4035static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
bf8179a0 4036{
80154d77
PB		 4037 struct kvm_vcpu *vcpu = &vmx->vcpu;
4038
bf8179a0 4039 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
0367f205 4040
f99e3daf
CP		 4041 if (pt_mode == PT_MODE_SYSTEM)
4042 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
80154d77 4043 if (!cpu_need_virtualize_apic_accesses(vcpu))
bf8179a0
NHE		 4044 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4045 if (vmx->vpid == 0)
4046 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4047 if (!enable_ept) {
4048 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4049 enable_unrestricted_guest = 0;
4050 }
4051 if (!enable_unrestricted_guest)
4052 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
b31c114b 4053 if (kvm_pause_in_guest(vmx->vcpu.kvm))
bf8179a0 4054 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
80154d77 4055 if (!kvm_vcpu_apicv_active(vcpu))
c7c9c56c
YZ		 4056 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4057 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4058 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
0367f205
PB		 4059
4060 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4061 * in vmx_set_cr4. */
4062 exec_control &= ~SECONDARY_EXEC_DESC;
4063
abc4fc58
AG		 4064 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4065 (handle_vmptrld).
4066 We can NOT enable shadow_vmcs here because we don't have yet
4067 a current VMCS12
4068 */
4069 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
a3eaa864
KH		 4070
4071 if (!enable_pml)
4072 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
843e4330 4073
3db13480
PB		 4074 if (vmx_xsaves_supported()) {
4075 /* Exposing XSAVES only when XSAVE is exposed */
4076 bool xsaves_enabled =
96be4e06 4077 boot_cpu_has(X86_FEATURE_XSAVE) &&
3db13480
PB		 4078 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4079 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4080
7204160e
AL		 4081 vcpu->arch.xsaves_enabled = xsaves_enabled;
4082
3db13480
PB		 4083 if (!xsaves_enabled)
4084 exec_control &= ~SECONDARY_EXEC_XSAVES;
4085
4086 if (nested) {
4087 if (xsaves_enabled)
6677f3da 4088 vmx->nested.msrs.secondary_ctls_high |=
3db13480
PB		 4089 SECONDARY_EXEC_XSAVES;
4090 else
6677f3da 4091 vmx->nested.msrs.secondary_ctls_high &=
3db13480
PB		 4092 ~SECONDARY_EXEC_XSAVES;
4093 }
4094 }
4095
80154d77
PB		 4096 if (vmx_rdtscp_supported()) {
4097 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4098 if (!rdtscp_enabled)
4099 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4100
4101 if (nested) {
4102 if (rdtscp_enabled)
6677f3da 4103 vmx->nested.msrs.secondary_ctls_high |=
80154d77
PB		 4104 SECONDARY_EXEC_RDTSCP;
4105 else
6677f3da 4106 vmx->nested.msrs.secondary_ctls_high &=
80154d77
PB		 4107 ~SECONDARY_EXEC_RDTSCP;
4108 }
4109 }
4110
4111 if (vmx_invpcid_supported()) {
4112 /* Exposing INVPCID only when PCID is exposed */
4113 bool invpcid_enabled =
4114 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4115 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4116
4117 if (!invpcid_enabled) {
4118 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4119 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4120 }
4121
4122 if (nested) {
4123 if (invpcid_enabled)
6677f3da 4124 vmx->nested.msrs.secondary_ctls_high |=
80154d77
PB		 4125 SECONDARY_EXEC_ENABLE_INVPCID;
4126 else
6677f3da 4127 vmx->nested.msrs.secondary_ctls_high &=
80154d77
PB		 4128 ~SECONDARY_EXEC_ENABLE_INVPCID;
4129 }
4130 }
4131
45ec368c
JM		 4132 if (vmx_rdrand_supported()) {
4133 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4134 if (rdrand_enabled)
736fdf72 4135 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
45ec368c
JM		 4136
4137 if (nested) {
4138 if (rdrand_enabled)
6677f3da 4139 vmx->nested.msrs.secondary_ctls_high |=
736fdf72 4140 SECONDARY_EXEC_RDRAND_EXITING;
45ec368c 4141 else
6677f3da 4142 vmx->nested.msrs.secondary_ctls_high &=
736fdf72 4143 ~SECONDARY_EXEC_RDRAND_EXITING;
45ec368c
JM		 4144 }
4145 }
4146
75f4fc8d
JM		 4147 if (vmx_rdseed_supported()) {
4148 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4149 if (rdseed_enabled)
736fdf72 4150 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d
JM		 4151
4152 if (nested) {
4153 if (rdseed_enabled)
6677f3da 4154 vmx->nested.msrs.secondary_ctls_high |=
736fdf72 4155 SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d 4156 else
6677f3da 4157 vmx->nested.msrs.secondary_ctls_high &=
736fdf72 4158 ~SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d
JM		 4159 }
4160 }
4161
e69e72fa
TX		 4162 if (vmx_waitpkg_supported()) {
4163 bool waitpkg_enabled =
4164 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4165
4166 if (!waitpkg_enabled)
4167 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4168
4169 if (nested) {
4170 if (waitpkg_enabled)
4171 vmx->nested.msrs.secondary_ctls_high |=
4172 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4173 else
4174 vmx->nested.msrs.secondary_ctls_high &=
4175 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4176 }
4177 }
4178
80154d77 4179 vmx->secondary_exec_control = exec_control;
bf8179a0
NHE		 4180}
4181
ce88decf
XG		 4182static void ept_set_mmio_spte_mask(void)
4183{
4184 /*
4185 * EPT Misconfigurations can be generated if the value of bits 2:0
4186 * of an EPT paging-structure entry is 110b (write/execute).
ce88decf 4187 */
dcdca5fe 4188 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4af77151 4189 VMX_EPT_MISCONFIG_WX_VALUE, 0);
ce88decf
XG		 4190}
4191
f53cd63c 4192#define VMX_XSS_EXIT_BITMAP 0
6aa8b732 4193
944c3464 4194/*
1b84292b
XL		 4195 * Noting that the initialization of Guest-state Area of VMCS is in
4196 * vmx_vcpu_reset().
944c3464 4197 */
1b84292b 4198static void init_vmcs(struct vcpu_vmx *vmx)
944c3464 4199{
944c3464 4200 if (nested)
1b84292b 4201 nested_vmx_set_vmcs_shadowing_bitmap();
944c3464 4202
25c5f225 4203 if (cpu_has_vmx_msr_bitmap())
904e14fb 4204 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
25c5f225 4205
6aa8b732
AK		 4206 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4207
6aa8b732 4208 /* Control */
3af80fec 4209 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4210
3af80fec 4211 exec_controls_set(vmx, vmx_exec_control(vmx));
6aa8b732 4212
dfa169bb 4213 if (cpu_has_secondary_exec_ctrls()) {
80154d77 4214 vmx_compute_secondary_exec_control(vmx);
3af80fec 4215 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
dfa169bb 4216 }
f78e0e2e 4217
d62caabb 4218 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
c7c9c56c
YZ		 4219 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4220 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4221 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4222 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4223
4224 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be 4225
0bcf261c 4226 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
01e439be 4227 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4228 }
4229
b31c114b 4230 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4b8d54f9 4231 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4232 vmx->ple_window = ple_window;
4233 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4234 }
4235
c3707958
XG		 4236 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4237 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4238 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4239
9581d442
AK		 4240 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4241 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4242 vmx_set_constant_host_state(vmx);
6aa8b732
AK		 4243 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4244 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
6aa8b732 4245
2a499e49
BD		 4246 if (cpu_has_vmx_vmfunc())
4247 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4248
2cc51560
ED		 4249 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4250 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
33966dd6 4251 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
2cc51560 4252 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
33966dd6 4253 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
6aa8b732 4254
74545705
RK		 4255 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4256 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 4257
3af80fec 4258 vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
6aa8b732
AK		 4259
4260 /* 22.2.1, 20.8.1 */
3af80fec 4261 vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
1c3d14fe 4262
bd7e5b08
PB		 4263 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4264 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4265
bf8179a0 4266 set_cr4_guest_host_mask(vmx);
e00c8cf2 4267
35fbe0d4
XL		 4268 if (vmx->vpid != 0)
4269 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4270
f53cd63c
WL		 4271 if (vmx_xsaves_supported())
4272 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4273
4e59516a 4274 if (enable_pml) {
4e59516a
PF		 4275 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4276 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4277 }
0b665d30
SC		 4278
4279 if (cpu_has_vmx_encls_vmexit())
4280 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
2ef444f1
CP		 4281
4282 if (pt_mode == PT_MODE_HOST_GUEST) {
4283 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4284 /* Bit[6~0] are forced to 1, writes are ignored. */
4285 vmx->pt_desc.guest.output_mask = 0x7F;
4286 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4287 }
e00c8cf2
AK		 4288}
4289
d28bc9dd 4290static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK		 4291{
4292 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4293 struct msr_data apic_base_msr;
d28bc9dd 4294 u64 cr0;
e00c8cf2 4295
7ffd92c5 4296 vmx->rmode.vm86_active = 0;
d28b387f 4297 vmx->spec_ctrl = 0;
e00c8cf2 4298
6e3ba4ab
TX		 4299 vmx->msr_ia32_umwait_control = 0;
4300
ad312c7c 4301 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
95c06540 4302 vmx->hv_deadline_tsc = -1;
d28bc9dd
NA		 4303 kvm_set_cr8(vcpu, 0);
4304
4305 if (!init_event) {
4306 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4307 MSR_IA32_APICBASE_ENABLE;
4308 if (kvm_vcpu_is_reset_bsp(vcpu))
4309 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4310 apic_base_msr.host_initiated = true;
4311 kvm_set_apic_base(vcpu, &apic_base_msr);
4312 }
e00c8cf2 4313
2fb92db1
AK		 4314 vmx_segment_cache_clear(vmx);
4315
5706be0d 4316 seg_setup(VCPU_SREG_CS);
66450a21 4317 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
f3531054 4318 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
e00c8cf2
AK		 4319
4320 seg_setup(VCPU_SREG_DS);
4321 seg_setup(VCPU_SREG_ES);
4322 seg_setup(VCPU_SREG_FS);
4323 seg_setup(VCPU_SREG_GS);
4324 seg_setup(VCPU_SREG_SS);
4325
4326 vmcs_write16(GUEST_TR_SELECTOR, 0);
4327 vmcs_writel(GUEST_TR_BASE, 0);
4328 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4329 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4330
4331 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4332 vmcs_writel(GUEST_LDTR_BASE, 0);
4333 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4334 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4335
d28bc9dd
NA		 4336 if (!init_event) {
4337 vmcs_write32(GUEST_SYSENTER_CS, 0);
4338 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4339 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4340 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4341 }
e00c8cf2 4342
c37c2873 4343 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
66450a21 4344 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4345
e00c8cf2
AK		 4346 vmcs_writel(GUEST_GDTR_BASE, 0);
4347 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4348
4349 vmcs_writel(GUEST_IDTR_BASE, 0);
4350 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4351
443381a8 4352 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2 4353 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
f3531054 4354 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
a554d207
WL		 4355 if (kvm_mpx_supported())
4356 vmcs_write64(GUEST_BNDCFGS, 0);
e00c8cf2 4357
e00c8cf2
AK		 4358 setup_msrs(vmx);
4359
6aa8b732
AK		 4360 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4361
d28bc9dd 4362 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 4363 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 4364 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 4365 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 4366 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY		 4367 vmcs_write32(TPR_THRESHOLD, 0);
4368 }
4369
a73896cb 4370 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4371
d28bc9dd 4372 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
d28bc9dd 4373 vmx->vcpu.arch.cr0 = cr0;
f2463247 4374 vmx_set_cr0(vcpu, cr0); /* enter rmode */
d28bc9dd 4375 vmx_set_cr4(vcpu, 0);
5690891b 4376 vmx_set_efer(vcpu, 0);
bd7e5b08 4377
d28bc9dd 4378 update_exception_bitmap(vcpu);
6aa8b732 4379
dd5f5341 4380 vpid_sync_context(vmx->vpid);
caa057a2
WL		 4381 if (init_event)
4382 vmx_clear_hlt(vcpu);
6aa8b732
AK		 4383}
4384
55d2375e 4385static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99 4386{
9dadc2f9 4387 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
3b86cd99
JK		 4388}
4389
c9a7953f 4390static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99 4391{
d02fcf50 4392 if (!enable_vnmi ||
8a1b4392 4393 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
c9a7953f
JK		 4394 enable_irq_window(vcpu);
4395 return;
4396 }
3b86cd99 4397
4e2a0bc5 4398 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
3b86cd99
JK		 4399}
4400
66fd3f7f 4401static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4402{
9c8cba37 4403 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4404 uint32_t intr;
4405 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4406
229456fc 4407 trace_kvm_inj_virq(irq);
2714d1d3 4408
fa89a817 4409 ++vcpu->stat.irq_injections;
7ffd92c5 4410 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4411 int inc_eip = 0;
4412 if (vcpu->arch.interrupt.soft)
4413 inc_eip = vcpu->arch.event_exit_inst_len;
9497e1f2 4414 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
85f455f7
ED		 4415 return;
4416 }
66fd3f7f
GN		 4417 intr = irq | INTR_INFO_VALID_MASK;
4418 if (vcpu->arch.interrupt.soft) {
4419 intr |= INTR_TYPE_SOFT_INTR;
4420 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4421 vmx->vcpu.arch.event_exit_inst_len);
4422 } else
4423 intr |= INTR_TYPE_EXT_INTR;
4424 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
caa057a2
WL		 4425
4426 vmx_clear_hlt(vcpu);
85f455f7
ED		 4427}
4428
f08864b4
SY		 4429static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4430{
66a5a347
JK		 4431 struct vcpu_vmx *vmx = to_vmx(vcpu);
4432
d02fcf50 4433 if (!enable_vnmi) {
8a1b4392
PB		 4434 /*
4435 * Tracking the NMI-blocked state in software is built upon
4436 * finding the next open IRQ window. This, in turn, depends on
4437 * well-behaving guests: They have to keep IRQs disabled at
4438 * least as long as the NMI handler runs. Otherwise we may
4439 * cause NMI nesting, maybe breaking the guest. But as this is
4440 * highly unlikely, we can live with the residual risk.
4441 */
4442 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4443 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4444 }
4445
4c4a6f79
PB		 4446 ++vcpu->stat.nmi_injections;
4447 vmx->loaded_vmcs->nmi_known_unmasked = false;
3b86cd99 4448
7ffd92c5 4449 if (vmx->rmode.vm86_active) {
9497e1f2 4450 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
66a5a347
JK		 4451 return;
4452 }
c5a6d5f7 4453
f08864b4
SY		 4454 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4455 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
caa057a2
WL		 4456
4457 vmx_clear_hlt(vcpu);
f08864b4
SY		 4458}
4459
97b7ead3 4460bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3cfc3092 4461{
4c4a6f79
PB		 4462 struct vcpu_vmx *vmx = to_vmx(vcpu);
4463 bool masked;
4464
d02fcf50 4465 if (!enable_vnmi)
8a1b4392 4466 return vmx->loaded_vmcs->soft_vnmi_blocked;
4c4a6f79 4467 if (vmx->loaded_vmcs->nmi_known_unmasked)
9d58b931 4468 return false;
4c4a6f79
PB		 4469 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4470 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4471 return masked;
3cfc3092
JK		 4472}
4473
97b7ead3 4474void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3cfc3092
JK		 4475{
4476 struct vcpu_vmx *vmx = to_vmx(vcpu);
4477
d02fcf50 4478 if (!enable_vnmi) {
8a1b4392
PB		 4479 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4480 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4481 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4482 }
4483 } else {
4484 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4485 if (masked)
4486 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4487 GUEST_INTR_STATE_NMI);
4488 else
4489 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4490 GUEST_INTR_STATE_NMI);
4491 }
3cfc3092
JK		 4492}
4493
2505dc9f
JK		 4494static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4495{
b6b8a145
JK		 4496 if (to_vmx(vcpu)->nested.nested_run_pending)
4497 return 0;
ea8ceb83 4498
d02fcf50 4499 if (!enable_vnmi &&
8a1b4392
PB		 4500 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4501 return 0;
4502
2505dc9f
JK		 4503 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4504 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4505 | GUEST_INTR_STATE_NMI));
4506}
4507
78646121
GN		 4508static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4509{
b6b8a145
JK		 4510 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4511 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4512 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4513 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4514}
4515
cbc94022
IE		 4516static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4517{
4518 int ret;
cbc94022 4519
f7eaeb0a
SC		 4520 if (enable_unrestricted_guest)
4521 return 0;
4522
6a3c623b
PX		 4523 mutex_lock(&kvm->slots_lock);
4524 ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4525 PAGE_SIZE * 3);
4526 mutex_unlock(&kvm->slots_lock);
4527
cbc94022
IE		 4528 if (ret)
4529 return ret;
40bbb9d0 4530 to_kvm_vmx(kvm)->tss_addr = addr;
1f755a82 4531 return init_rmode_tss(kvm);
cbc94022
IE		 4532}
4533
2ac52ab8
SC		 4534static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4535{
40bbb9d0 4536 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
2ac52ab8
SC		 4537 return 0;
4538}
4539
0ca1b4f4 4540static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4541{
77ab6db0 4542 switch (vec) {
77ab6db0 4543 case BP_VECTOR:
c573cd22
JK		 4544 /*
4545 * Update instruction length as we may reinject the exception
4546 * from user space while in guest debugging mode.
4547 */
4548 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4549 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4550 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4551 return false;
4552 /* fall through */
4553 case DB_VECTOR:
4554 if (vcpu->guest_debug &
4555 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4556 return false;
d0bfb940
JK		 4557 /* fall through */
4558 case DE_VECTOR:
77ab6db0
JK		 4559 case OF_VECTOR:
4560 case BR_VECTOR:
4561 case UD_VECTOR:
4562 case DF_VECTOR:
4563 case SS_VECTOR:
4564 case GP_VECTOR:
4565 case MF_VECTOR:
0ca1b4f4
GN		 4566 return true;
4567 break;
77ab6db0 4568 }
0ca1b4f4
GN		 4569 return false;
4570}
4571
4572static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4573 int vec, u32 err_code)
4574{
4575 /*
4576 * Instruction with address size override prefix opcode 0x67
4577 * Cause the #SS fault with 0 error code in VM86 mode.
4578 */
4579 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
60fc3d02 4580 if (kvm_emulate_instruction(vcpu, 0)) {
0ca1b4f4
GN		 4581 if (vcpu->arch.halt_request) {
4582 vcpu->arch.halt_request = 0;
5cb56059 4583 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN		 4584 }
4585 return 1;
4586 }
4587 return 0;
4588 }
4589
4590 /*
4591 * Forward all other exceptions that are valid in real mode.
4592 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4593 * the required debugging infrastructure rework.
4594 */
4595 kvm_queue_exception(vcpu, vec);
4596 return 1;
6aa8b732
AK		 4597}
4598
a0861c02
AK		 4599/*
4600 * Trigger machine check on the host. We assume all the MSRs are already set up
4601 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4602 * We pass a fake environment to the machine check handler because we want
4603 * the guest to be always treated like user space, no matter what context
4604 * it used internally.
4605 */
4606static void kvm_machine_check(void)
4607{
4608#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4609 struct pt_regs regs = {
4610 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4611 .flags = X86_EFLAGS_IF,
4612 };
4613
4614 do_machine_check(&regs, 0);
4615#endif
4616}
4617
851ba692 4618static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02 4619{
95b5a48c 4620 /* handled by vmx_vcpu_run() */
a0861c02
AK		 4621 return 1;
4622}
4623
95b5a48c 4624static int handle_exception_nmi(struct kvm_vcpu *vcpu)
6aa8b732 4625{
1155f76a 4626 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4627 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4628 u32 intr_info, ex_no, error_code;
42dbaa5a 4629 unsigned long cr2, rip, dr6;
6aa8b732 4630 u32 vect_info;
6aa8b732 4631
1155f76a 4632 vect_info = vmx->idt_vectoring_info;
88786475 4633 intr_info = vmx->exit_intr_info;
6aa8b732 4634
2ea72039 4635 if (is_machine_check(intr_info) || is_nmi(intr_info))
95b5a48c 4636 return 1; /* handled by handle_exception_nmi_irqoff() */
2ab455cc 4637
082d06ed
WL		 4638 if (is_invalid_opcode(intr_info))
4639 return handle_ud(vcpu);
7aa81cc0 4640
6aa8b732 4641 error_code = 0;
2e11384c 4642 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4643 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e 4644
9e869480
LA		 4645 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4646 WARN_ON_ONCE(!enable_vmware_backdoor);
a6c6ed1e
SC		 4647
4648 /*
4649 * VMware backdoor emulation on #GP interception only handles
4650 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4651 * error code on #GP.
4652 */
4653 if (error_code) {
4654 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4655 return 1;
4656 }
60fc3d02 4657 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
9e869480
LA		 4658 }
4659
bf4ca23e
XG		 4660 /*
4661 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4662 * MMIO, it is better to report an internal error.
4663 * See the comments in vmx_handle_exit.
4664 */
4665 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4666 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4667 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4668 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 4669 vcpu->run->internal.ndata = 3;
bf4ca23e
XG		 4670 vcpu->run->internal.data[0] = vect_info;
4671 vcpu->run->internal.data[1] = intr_info;
80f0e95d 4672 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG		 4673 return 0;
4674 }
4675
6aa8b732
AK		 4676 if (is_page_fault(intr_info)) {
4677 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1261bfa3
WL		 4678 /* EPT won't cause page fault directly */
4679 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
d0006530 4680 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
6aa8b732
AK		 4681 }
4682
d0bfb940 4683 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4684
4685 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4686 return handle_rmode_exception(vcpu, ex_no, error_code);
4687
42dbaa5a 4688 switch (ex_no) {
54a20552
EN		 4689 case AC_VECTOR:
4690 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4691 return 1;
42dbaa5a
JK		 4692 case DB_VECTOR:
4693 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4694 if (!(vcpu->guest_debug &
4695 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
1fc5d194 4696 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 4697 vcpu->arch.dr6 |= dr6 | DR6_RTM;
32d43cd3 4698 if (is_icebp(intr_info))
1957aa63 4699 WARN_ON(!skip_emulated_instruction(vcpu));
fd2a445a 4700
42dbaa5a
JK		 4701 kvm_queue_exception(vcpu, DB_VECTOR);
4702 return 1;
4703 }
4704 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4705 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4706 /* fall through */
4707 case BP_VECTOR:
c573cd22
JK		 4708 /*
4709 * Update instruction length as we may reinject #BP from
4710 * user space while in guest debugging mode. Reading it for
4711 * #DB as well causes no harm, it is not used in that case.
4712 */
4713 vmx->vcpu.arch.event_exit_inst_len =
4714 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4715 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4716 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4717 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4718 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4719 break;
4720 default:
d0bfb940
JK		 4721 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4722 kvm_run->ex.exception = ex_no;
4723 kvm_run->ex.error_code = error_code;
42dbaa5a 4724 break;
6aa8b732 4725 }
6aa8b732
AK		 4726 return 0;
4727}
4728
f399e60c 4729static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4730{
1165f5fe 4731 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4732 return 1;
4733}
4734
851ba692 4735static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4736{
851ba692 4737 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 4738 vcpu->mmio_needed = 0;
988ad74f
AK		 4739 return 0;
4740}
6aa8b732 4741
851ba692 4742static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4743{
bfdaab09 4744 unsigned long exit_qualification;
dca7f128 4745 int size, in, string;
039576c0 4746 unsigned port;
6aa8b732 4747
bfdaab09 4748 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4749 string = (exit_qualification & 16) != 0;
e70669ab 4750
cf8f70bf 4751 ++vcpu->stat.io_exits;
e70669ab 4752
432baf60 4753 if (string)
60fc3d02 4754 return kvm_emulate_instruction(vcpu, 0);
e70669ab 4755
cf8f70bf
GN		 4756 port = exit_qualification >> 16;
4757 size = (exit_qualification & 7) + 1;
432baf60 4758 in = (exit_qualification & 8) != 0;
cf8f70bf 4759
dca7f128 4760 return kvm_fast_pio(vcpu, size, port, in);
6aa8b732
AK		 4761}
4762
102d8325
IM		 4763static void
4764vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4765{
4766 /*
4767 * Patch in the VMCALL instruction:
4768 */
4769 hypercall[0] = 0x0f;
4770 hypercall[1] = 0x01;
4771 hypercall[2] = 0xc1;
102d8325
IM		 4772}
4773
0fa06071 4774/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4775static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4776{
eeadf9e7 4777 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4778 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4779 unsigned long orig_val = val;
4780
eeadf9e7
NHE		 4781 /*
4782 * We get here when L2 changed cr0 in a way that did not change
4783 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4784 * but did change L0 shadowed bits. So we first calculate the
4785 * effective cr0 value that L1 would like to write into the
4786 * hardware. It consists of the L2-owned bits from the new
4787 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4788 */
1a0d74e6
JK		 4789 val = (val & ~vmcs12->cr0_guest_host_mask) |
4790 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4791
3899152c 4792 if (!nested_guest_cr0_valid(vcpu, val))
eeadf9e7 4793 return 1;
1a0d74e6
JK		 4794
4795 if (kvm_set_cr0(vcpu, val))
4796 return 1;
4797 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4798 return 0;
1a0d74e6
JK		 4799 } else {
4800 if (to_vmx(vcpu)->nested.vmxon &&
3899152c 4801 !nested_host_cr0_valid(vcpu, val))
1a0d74e6 4802 return 1;
3899152c 4803
eeadf9e7 4804 return kvm_set_cr0(vcpu, val);
1a0d74e6 4805 }
eeadf9e7
NHE		 4806}
4807
4808static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4809{
4810 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4811 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4812 unsigned long orig_val = val;
4813
4814 /* analogously to handle_set_cr0 */
4815 val = (val & ~vmcs12->cr4_guest_host_mask) |
4816 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4817 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4818 return 1;
1a0d74e6 4819 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4820 return 0;
4821 } else
4822 return kvm_set_cr4(vcpu, val);
4823}
4824
0367f205
PB		 4825static int handle_desc(struct kvm_vcpu *vcpu)
4826{
4827 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
60fc3d02 4828 return kvm_emulate_instruction(vcpu, 0);
0367f205
PB		 4829}
4830
851ba692 4831static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4832{
229456fc 4833 unsigned long exit_qualification, val;
6aa8b732
AK		 4834 int cr;
4835 int reg;
49a9b07e 4836 int err;
6affcbed 4837 int ret;
6aa8b732 4838
bfdaab09 4839 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4840 cr = exit_qualification & 15;
4841 reg = (exit_qualification >> 8) & 15;
4842 switch ((exit_qualification >> 4) & 3) {
4843 case 0: /* mov to cr */
1e32c079 4844 val = kvm_register_readl(vcpu, reg);
229456fc 4845 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4846 switch (cr) {
4847 case 0:
eeadf9e7 4848 err = handle_set_cr0(vcpu, val);
6affcbed 4849 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 4850 case 3:
e1de91cc 4851 WARN_ON_ONCE(enable_unrestricted_guest);
2390218b 4852 err = kvm_set_cr3(vcpu, val);
6affcbed 4853 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 4854 case 4:
eeadf9e7 4855 err = handle_set_cr4(vcpu, val);
6affcbed 4856 return kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4857 case 8: {
4858 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 4859 u8 cr8 = (u8)val;
eea1cff9 4860 err = kvm_set_cr8(vcpu, cr8);
6affcbed 4861 ret = kvm_complete_insn_gp(vcpu, err);
35754c98 4862 if (lapic_in_kernel(vcpu))
6affcbed 4863 return ret;
0a5fff19 4864 if (cr8_prev <= cr8)
6affcbed
KH		 4865 return ret;
4866 /*
4867 * TODO: we might be squashing a
4868 * KVM_GUESTDBG_SINGLESTEP-triggered
4869 * KVM_EXIT_DEBUG here.
4870 */
851ba692 4871 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4872 return 0;
4873 }
4b8073e4 4874 }
6aa8b732 4875 break;
25c4c276 4876 case 2: /* clts */
bd7e5b08
PB		 4877 WARN_ONCE(1, "Guest should always own CR0.TS");
4878 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 4879 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6affcbed 4880 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4881 case 1: /*mov from cr*/
4882 switch (cr) {
4883 case 3:
e1de91cc 4884 WARN_ON_ONCE(enable_unrestricted_guest);
9f8fe504
AK		 4885 val = kvm_read_cr3(vcpu);
4886 kvm_register_write(vcpu, reg, val);
4887 trace_kvm_cr_read(cr, val);
6affcbed 4888 return kvm_skip_emulated_instruction(vcpu);
6aa8b732 4889 case 8:
229456fc
MT		 4890 val = kvm_get_cr8(vcpu);
4891 kvm_register_write(vcpu, reg, val);
4892 trace_kvm_cr_read(cr, val);
6affcbed 4893 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4894 }
4895 break;
4896 case 3: /* lmsw */
a1f83a74 4897 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4898 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4899 kvm_lmsw(vcpu, val);
6aa8b732 4900
6affcbed 4901 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4902 default:
4903 break;
4904 }
851ba692 4905 vcpu->run->exit_reason = 0;
a737f256 4906 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4907 (int)(exit_qualification >> 4) & 3, cr);
4908 return 0;
4909}
4910
851ba692 4911static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4912{
bfdaab09 4913 unsigned long exit_qualification;
16f8a6f9
NA		 4914 int dr, dr7, reg;
4915
4916 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4917 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4918
4919 /* First, if DR does not exist, trigger UD */
4920 if (!kvm_require_dr(vcpu, dr))
4921 return 1;
6aa8b732 4922
f2483415 4923 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4924 if (!kvm_require_cpl(vcpu, 0))
4925 return 1;
16f8a6f9
NA		 4926 dr7 = vmcs_readl(GUEST_DR7);
4927 if (dr7 & DR7_GD) {
42dbaa5a
JK		 4928 /*
4929 * As the vm-exit takes precedence over the debug trap, we
4930 * need to emulate the latter, either for the host or the
4931 * guest debugging itself.
4932 */
4933 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 4934 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 4935 vcpu->run->debug.arch.dr7 = dr7;
82b32774 4936 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 4937 vcpu->run->debug.arch.exception = DB_VECTOR;
4938 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4939 return 0;
4940 } else {
1fc5d194 4941 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 4942 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 4943 kvm_queue_exception(vcpu, DB_VECTOR);
4944 return 1;
4945 }
4946 }
4947
81908bf4 4948 if (vcpu->guest_debug == 0) {
2183f564 4949 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
81908bf4
PB		 4950
4951 /*
4952 * No more DR vmexits; force a reload of the debug registers
4953 * and reenter on this instruction. The next vmexit will
4954 * retrieve the full state of the debug registers.
4955 */
4956 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4957 return 1;
4958 }
4959
42dbaa5a
JK		 4960 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4961 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 4962 unsigned long val;
4c4d563b
JK		 4963
4964 if (kvm_get_dr(vcpu, dr, &val))
4965 return 1;
4966 kvm_register_write(vcpu, reg, val);
020df079 4967 } else
5777392e 4968 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 4969 return 1;
4970
6affcbed 4971 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4972}
4973
73aaf249
JK		 4974static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4975{
4976 return vcpu->arch.dr6;
4977}
4978
4979static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4980{
4981}
4982
81908bf4
PB		 4983static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4984{
81908bf4
PB		 4985 get_debugreg(vcpu->arch.db[0], 0);
4986 get_debugreg(vcpu->arch.db[1], 1);
4987 get_debugreg(vcpu->arch.db[2], 2);
4988 get_debugreg(vcpu->arch.db[3], 3);
4989 get_debugreg(vcpu->arch.dr6, 6);
4990 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4991
4992 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2183f564 4993 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
81908bf4
PB		 4994}
4995
020df079
GN		 4996static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4997{
4998 vmcs_writel(GUEST_DR7, val);
4999}
5000
851ba692 5001static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5002{
eb90f341 5003 kvm_apic_update_ppr(vcpu);
6e5d865c
YS		 5004 return 1;
5005}
5006
851ba692 5007static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5008{
9dadc2f9 5009 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
2714d1d3 5010
3842d135
AK		 5011 kvm_make_request(KVM_REQ_EVENT, vcpu);
5012
a26bf12a 5013 ++vcpu->stat.irq_window_exits;
6aa8b732
AK		 5014 return 1;
5015}
5016
851ba692 5017static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5018{
0d9c055e 5019 return kvm_emulate_hypercall(vcpu);
c21415e8
IM		 5020}
5021
ec25d5e6
GN		 5022static int handle_invd(struct kvm_vcpu *vcpu)
5023{
60fc3d02 5024 return kvm_emulate_instruction(vcpu, 0);
ec25d5e6
GN		 5025}
5026
851ba692 5027static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5028{
f9c617f6 5029 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5030
5031 kvm_mmu_invlpg(vcpu, exit_qualification);
6affcbed 5032 return kvm_skip_emulated_instruction(vcpu);
a7052897
MT		 5033}
5034
fee84b07
AK		 5035static int handle_rdpmc(struct kvm_vcpu *vcpu)
5036{
5037 int err;
5038
5039 err = kvm_rdpmc(vcpu);
6affcbed 5040 return kvm_complete_insn_gp(vcpu, err);
fee84b07
AK		 5041}
5042
851ba692 5043static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 5044{
6affcbed 5045 return kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5046}
5047
2acf923e
DC		 5048static int handle_xsetbv(struct kvm_vcpu *vcpu)
5049{
5050 u64 new_bv = kvm_read_edx_eax(vcpu);
de3cd117 5051 u32 index = kvm_rcx_read(vcpu);
2acf923e
DC		 5052
5053 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6affcbed 5054 return kvm_skip_emulated_instruction(vcpu);
2acf923e
DC		 5055 return 1;
5056}
5057
851ba692 5058static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5059{
58fbbf26
KT		 5060 if (likely(fasteoi)) {
5061 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5062 int access_type, offset;
5063
5064 access_type = exit_qualification & APIC_ACCESS_TYPE;
5065 offset = exit_qualification & APIC_ACCESS_OFFSET;
5066 /*
5067 * Sane guest uses MOV to write EOI, with written value
5068 * not cared. So make a short-circuit here by avoiding
5069 * heavy instruction emulation.
5070 */
5071 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5072 (offset == APIC_EOI)) {
5073 kvm_lapic_set_eoi(vcpu);
6affcbed 5074 return kvm_skip_emulated_instruction(vcpu);
58fbbf26
KT		 5075 }
5076 }
60fc3d02 5077 return kvm_emulate_instruction(vcpu, 0);
f78e0e2e
SY		 5078}
5079
c7c9c56c
YZ		 5080static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5081{
5082 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5083 int vector = exit_qualification & 0xff;
5084
5085 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5086 kvm_apic_set_eoi_accelerated(vcpu, vector);
5087 return 1;
5088}
5089
83d4c286
YZ		 5090static int handle_apic_write(struct kvm_vcpu *vcpu)
5091{
5092 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5093 u32 offset = exit_qualification & 0xfff;
5094
5095 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5096 kvm_apic_write_nodecode(vcpu, offset);
5097 return 1;
5098}
5099
851ba692 5100static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5101{
60637aac 5102 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5103 unsigned long exit_qualification;
e269fb21
JK		 5104 bool has_error_code = false;
5105 u32 error_code = 0;
37817f29 5106 u16 tss_selector;
7f3d35fd 5107 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5108
5109 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5110 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5111 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5112
5113 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5114
5115 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5116 if (reason == TASK_SWITCH_GATE && idt_v) {
5117 switch (type) {
5118 case INTR_TYPE_NMI_INTR:
5119 vcpu->arch.nmi_injected = false;
654f06fc 5120 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5121 break;
5122 case INTR_TYPE_EXT_INTR:
66fd3f7f 5123 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5124 kvm_clear_interrupt_queue(vcpu);
5125 break;
5126 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5127 if (vmx->idt_vectoring_info &
5128 VECTORING_INFO_DELIVER_CODE_MASK) {
5129 has_error_code = true;
5130 error_code =
5131 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5132 }
5133 /* fall through */
64a7ec06
GN		 5134 case INTR_TYPE_SOFT_EXCEPTION:
5135 kvm_clear_exception_queue(vcpu);
5136 break;
5137 default:
5138 break;
5139 }
60637aac 5140 }
37817f29
IE		 5141 tss_selector = exit_qualification;
5142
64a7ec06
GN		 5143 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5144 type != INTR_TYPE_EXT_INTR &&
5145 type != INTR_TYPE_NMI_INTR))
1957aa63 5146 WARN_ON(!skip_emulated_instruction(vcpu));
64a7ec06 5147
42dbaa5a
JK		 5148 /*
5149 * TODO: What about debug traps on tss switch?
5150 * Are we supposed to inject them and update dr6?
5151 */
1051778f
SC		 5152 return kvm_task_switch(vcpu, tss_selector,
5153 type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
60fc3d02 5154 reason, has_error_code, error_code);
37817f29
IE		 5155}
5156
851ba692 5157static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5158{
f9c617f6 5159 unsigned long exit_qualification;
1439442c 5160 gpa_t gpa;
eebed243 5161 u64 error_code;
1439442c 5162
f9c617f6 5163 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5164
0be9c7a8
GN		 5165 /*
5166 * EPT violation happened while executing iret from NMI,
5167 * "blocked by NMI" bit has to be set before next VM entry.
5168 * There are errata that may cause this bit to not be set:
5169 * AAK134, BY25.
5170 */
bcd1c294 5171 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
d02fcf50 5172 enable_vnmi &&
bcd1c294 5173 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5174 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5175
1439442c 5176 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5177 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5 5178
27959a44 5179 /* Is it a read fault? */
ab22a473 5180 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
27959a44
JS		 5181 ? PFERR_USER_MASK : 0;
5182 /* Is it a write fault? */
ab22a473 5183 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
27959a44
JS		 5184 ? PFERR_WRITE_MASK : 0;
5185 /* Is it a fetch fault? */
ab22a473 5186 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
27959a44
JS		 5187 ? PFERR_FETCH_MASK : 0;
5188 /* ept page table entry is present? */
5189 error_code |= (exit_qualification &
5190 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5191 EPT_VIOLATION_EXECUTABLE))
5192 ? PFERR_PRESENT_MASK : 0;
4f5982a5 5193
eebed243
PB		 5194 error_code |= (exit_qualification & 0x100) != 0 ?
5195 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
25d92081 5196
25d92081 5197 vcpu->arch.exit_qualification = exit_qualification;
4f5982a5 5198 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5199}
5200
851ba692 5201static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 5202{
68f89400
MT		 5203 gpa_t gpa;
5204
9034e6e8
PB		 5205 /*
5206 * A nested guest cannot optimize MMIO vmexits, because we have an
5207 * nGPA here instead of the required GPA.
5208 */
68f89400 5209 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
9034e6e8
PB		 5210 if (!is_guest_mode(vcpu) &&
5211 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
931c33b1 5212 trace_kvm_fast_mmio(gpa);
1957aa63 5213 return kvm_skip_emulated_instruction(vcpu);
68c3b4d1 5214 }
68f89400 5215
c75d0edc 5216 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
68f89400
MT		 5217}
5218
851ba692 5219static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4 5220{
d02fcf50 5221 WARN_ON_ONCE(!enable_vnmi);
4e2a0bc5 5222 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
f08864b4 5223 ++vcpu->stat.nmi_window_exits;
3842d135 5224 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5225
5226 return 1;
5227}
5228
80ced186 5229static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5230{
8b3079a5 5231 struct vcpu_vmx *vmx = to_vmx(vcpu);
49e9d557 5232 bool intr_window_requested;
b8405c18 5233 unsigned count = 130;
49e9d557 5234
2bb8cafe
SC		 5235 /*
5236 * We should never reach the point where we are emulating L2
5237 * due to invalid guest state as that means we incorrectly
5238 * allowed a nested VMEntry with an invalid vmcs12.
5239 */
5240 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5241
2183f564 5242 intr_window_requested = exec_controls_get(vmx) &
9dadc2f9 5243 CPU_BASED_INTR_WINDOW_EXITING;
ea953ef0 5244
98eb2f8b 5245 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5246 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5247 return handle_interrupt_window(&vmx->vcpu);
5248
72875d8a 5249 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
de87dcdd
AK		 5250 return 1;
5251
60fc3d02 5252 if (!kvm_emulate_instruction(vcpu, 0))
8fff2710 5253 return 0;
1d5a4d9b 5254
add5ff7a 5255 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
8fff2710
SC		 5256 vcpu->arch.exception.pending) {
5257 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5258 vcpu->run->internal.suberror =
5259 KVM_INTERNAL_ERROR_EMULATION;
5260 vcpu->run->internal.ndata = 0;
5261 return 0;
5262 }
ea953ef0 5263
8d76c49e
GN		 5264 if (vcpu->arch.halt_request) {
5265 vcpu->arch.halt_request = 0;
8fff2710 5266 return kvm_vcpu_halt(vcpu);
8d76c49e
GN		 5267 }
5268
8fff2710
SC		 5269 /*
5270 * Note, return 1 and not 0, vcpu_run() is responsible for
5271 * morphing the pending signal into the proper return code.
5272 */
ea953ef0 5273 if (signal_pending(current))
8fff2710
SC		 5274 return 1;
5275
ea953ef0
MG		 5276 if (need_resched())
5277 schedule();
5278 }
5279
8fff2710 5280 return 1;
b4a2d31d
RK		 5281}
5282
5283static void grow_ple_window(struct kvm_vcpu *vcpu)
5284{
5285 struct vcpu_vmx *vmx = to_vmx(vcpu);
c5c5d6fa 5286 unsigned int old = vmx->ple_window;
b4a2d31d 5287
c8e88717
BM		 5288 vmx->ple_window = __grow_ple_window(old, ple_window,
5289 ple_window_grow,
5290 ple_window_max);
b4a2d31d 5291
4f75bcc3 5292 if (vmx->ple_window != old) {
b4a2d31d 5293 vmx->ple_window_dirty = true;
4f75bcc3
PX		 5294 trace_kvm_ple_window_update(vcpu->vcpu_id,
5295 vmx->ple_window, old);
5296 }
b4a2d31d
RK		 5297}
5298
5299static void shrink_ple_window(struct kvm_vcpu *vcpu)
5300{
5301 struct vcpu_vmx *vmx = to_vmx(vcpu);
c5c5d6fa 5302 unsigned int old = vmx->ple_window;
b4a2d31d 5303
c8e88717
BM		 5304 vmx->ple_window = __shrink_ple_window(old, ple_window,
5305 ple_window_shrink,
5306 ple_window);
b4a2d31d 5307
4f75bcc3 5308 if (vmx->ple_window != old) {
b4a2d31d 5309 vmx->ple_window_dirty = true;
4f75bcc3
PX		 5310 trace_kvm_ple_window_update(vcpu->vcpu_id,
5311 vmx->ple_window, old);
5312 }
b4a2d31d
RK		 5313}
5314
bf9f6ac8
FW		 5315/*
5316 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5317 */
5318static void wakeup_handler(void)
5319{
5320 struct kvm_vcpu *vcpu;
5321 int cpu = smp_processor_id();
5322
5323 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5324 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5325 blocked_vcpu_list) {
5326 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5327
5328 if (pi_test_on(pi_desc) == 1)
5329 kvm_vcpu_kick(vcpu);
5330 }
5331 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5332}
5333
e01bca2f 5334static void vmx_enable_tdp(void)
f160c7b7
JS		 5335{
5336 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5337 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5338 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5339 0ull, VMX_EPT_EXECUTABLE_MASK,
5340 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
d0ec49d4 5341 VMX_EPT_RWX_MASK, 0ull);
f160c7b7
JS		 5342
5343 ept_set_mmio_spte_mask();
5344 kvm_enable_tdp();
5345}
5346
4b8d54f9
ZE		 5347/*
5348 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5349 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5350 */
9fb41ba8 5351static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 5352{
b31c114b 5353 if (!kvm_pause_in_guest(vcpu->kvm))
b4a2d31d
RK		 5354 grow_ple_window(vcpu);
5355
de63ad4c
LM		 5356 /*
5357 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5358 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5359 * never set PAUSE_EXITING and just set PLE if supported,
5360 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5361 */
5362 kvm_vcpu_on_spin(vcpu, true);
6affcbed 5363 return kvm_skip_emulated_instruction(vcpu);
4b8d54f9
ZE		 5364}
5365
87c00572 5366static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5367{
6affcbed 5368 return kvm_skip_emulated_instruction(vcpu);
59708670
SY		 5369}
5370
87c00572
GS		 5371static int handle_mwait(struct kvm_vcpu *vcpu)
5372{
5373 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5374 return handle_nop(vcpu);
5375}
5376
45ec368c
JM		 5377static int handle_invalid_op(struct kvm_vcpu *vcpu)
5378{
5379 kvm_queue_exception(vcpu, UD_VECTOR);
5380 return 1;
5381}
5382
5f3d45e7
MD		 5383static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5384{
5385 return 1;
5386}
5387
87c00572
GS		 5388static int handle_monitor(struct kvm_vcpu *vcpu)
5389{
5390 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5391 return handle_nop(vcpu);
5392}
5393
55d2375e 5394static int handle_invpcid(struct kvm_vcpu *vcpu)
19677e32 5395{
55d2375e
SC		 5396 u32 vmx_instruction_info;
5397 unsigned long type;
5398 bool pcid_enabled;
5399 gva_t gva;
5400 struct x86_exception e;
5401 unsigned i;
5402 unsigned long roots_to_free = 0;
5403 struct {
5404 u64 pcid;
5405 u64 gla;
5406 } operand;
f9eb4af6 5407
55d2375e 5408 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
19677e32
BD		 5409 kvm_queue_exception(vcpu, UD_VECTOR);
5410 return 1;
5411 }
5412
55d2375e
SC		 5413 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5414 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5415
5416 if (type > 3) {
5417 kvm_inject_gp(vcpu, 0);
f9eb4af6
EK		 5418 return 1;
5419 }
5420
55d2375e
SC		 5421 /* According to the Intel instruction reference, the memory operand
5422 * is read even if it isn't needed (e.g., for type==all)
5423 */
3573e22c 5424 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
fdb28619
EK		 5425 vmx_instruction_info, false,
5426 sizeof(operand), &gva))
3573e22c
BD		 5427 return 1;
5428
55d2375e 5429 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
3573e22c
BD		 5430 kvm_inject_page_fault(vcpu, &e);
5431 return 1;
5432 }
5433
55d2375e
SC		 5434 if (operand.pcid >> 12 != 0) {
5435 kvm_inject_gp(vcpu, 0);
5436 return 1;
abfc52c6 5437 }
e29acc55 5438
55d2375e 5439 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
e29acc55 5440
55d2375e
SC		 5441 switch (type) {
5442 case INVPCID_TYPE_INDIV_ADDR:
5443 if ((!pcid_enabled && (operand.pcid != 0)) ||
5444 is_noncanonical_address(operand.gla, vcpu)) {
5445 kvm_inject_gp(vcpu, 0);
5446 return 1;
5447 }
5448 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5449 return kvm_skip_emulated_instruction(vcpu);
61ada748 5450
55d2375e
SC		 5451 case INVPCID_TYPE_SINGLE_CTXT:
5452 if (!pcid_enabled && (operand.pcid != 0)) {
5453 kvm_inject_gp(vcpu, 0);
5454 return 1;
5455 }
e29acc55 5456
55d2375e
SC		 5457 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5458 kvm_mmu_sync_roots(vcpu);
5459 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5460 }
e29acc55 5461
55d2375e
SC		 5462 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5463 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5464 == operand.pcid)
5465 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
63aff655 5466
55d2375e
SC		 5467 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5468 /*
5469 * If neither the current cr3 nor any of the prev_roots use the
5470 * given PCID, then nothing needs to be done here because a
5471 * resync will happen anyway before switching to any other CR3.
5472 */
e29acc55 5473
55d2375e 5474 return kvm_skip_emulated_instruction(vcpu);
61ada748 5475
55d2375e
SC		 5476 case INVPCID_TYPE_ALL_NON_GLOBAL:
5477 /*
5478 * Currently, KVM doesn't mark global entries in the shadow
5479 * page tables, so a non-global flush just degenerates to a
5480 * global flush. If needed, we could optimize this later by
5481 * keeping track of global entries in shadow page tables.
5482 */
e29acc55 5483
55d2375e
SC		 5484 /* fall-through */
5485 case INVPCID_TYPE_ALL_INCL_GLOBAL:
5486 kvm_mmu_unload(vcpu);
5487 return kvm_skip_emulated_instruction(vcpu);
e29acc55 5488
55d2375e
SC		 5489 default:
5490 BUG(); /* We have already checked above that type <= 3 */
5491 }
e29acc55
JM		 5492}
5493
55d2375e 5494static int handle_pml_full(struct kvm_vcpu *vcpu)
ec378aee 5495{
55d2375e 5496 unsigned long exit_qualification;
b3897a49 5497
55d2375e 5498 trace_kvm_pml_full(vcpu->vcpu_id);
b3897a49 5499
55d2375e 5500 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
cbf71279
RK		 5501
5502 /*
55d2375e
SC		 5503 * PML buffer FULL happened while executing iret from NMI,
5504 * "blocked by NMI" bit has to be set before next VM entry.
cbf71279 5505 */
55d2375e
SC		 5506 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5507 enable_vnmi &&
5508 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5509 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5510 GUEST_INTR_STATE_NMI);
e49fcb8b 5511
55d2375e
SC		 5512 /*
5513 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5514 * here.., and there's no userspace involvement needed for PML.
5515 */
ec378aee
NHE		 5516 return 1;
5517}
5518
55d2375e 5519static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8ca44e88 5520{
804939ea
SC		 5521 struct vcpu_vmx *vmx = to_vmx(vcpu);
5522
5523 if (!vmx->req_immediate_exit &&
5524 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
55d2375e 5525 kvm_lapic_expired_hv_timer(vcpu);
804939ea 5526
55d2375e 5527 return 1;
8ca44e88
DM		 5528}
5529
55d2375e
SC		 5530/*
5531 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5532 * are overwritten by nested_vmx_setup() when nested=1.
5533 */
5534static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
b8bbab92 5535{
55d2375e
SC		 5536 kvm_queue_exception(vcpu, UD_VECTOR);
5537 return 1;
b8bbab92
VK		 5538}
5539
55d2375e 5540static int handle_encls(struct kvm_vcpu *vcpu)
e7953d7f 5541{
55d2375e
SC		 5542 /*
5543 * SGX virtualization is not yet supported. There is no software
5544 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5545 * to prevent the guest from executing ENCLS.
5546 */
5547 kvm_queue_exception(vcpu, UD_VECTOR);
5548 return 1;
e7953d7f
AG		 5549}
5550
ec378aee 5551/*
55d2375e
SC		 5552 * The exit handlers return 1 if the exit was handled fully and guest execution
5553 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5554 * to be done to userspace and return 0.
ec378aee 5555 */
55d2375e 5556static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
95b5a48c 5557 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
55d2375e
SC		 5558 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5559 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5560 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5561 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5562 [EXIT_REASON_CR_ACCESS] = handle_cr,
5563 [EXIT_REASON_DR_ACCESS] = handle_dr,
f399e60c
AA		 5564 [EXIT_REASON_CPUID] = kvm_emulate_cpuid,
5565 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr,
5566 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr,
9dadc2f9 5567 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window,
f399e60c 5568 [EXIT_REASON_HLT] = kvm_emulate_halt,
55d2375e
SC		 5569 [EXIT_REASON_INVD] = handle_invd,
5570 [EXIT_REASON_INVLPG] = handle_invlpg,
5571 [EXIT_REASON_RDPMC] = handle_rdpmc,
5572 [EXIT_REASON_VMCALL] = handle_vmcall,
5573 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5574 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5575 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5576 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5577 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5578 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5579 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5580 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5581 [EXIT_REASON_VMON] = handle_vmx_instruction,
5582 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5583 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5584 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5585 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5586 [EXIT_REASON_WBINVD] = handle_wbinvd,
5587 [EXIT_REASON_XSETBV] = handle_xsetbv,
5588 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5589 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5590 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5591 [EXIT_REASON_LDTR_TR] = handle_desc,
5592 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5593 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5594 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5595 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5596 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5597 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
5598 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5599 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5600 [EXIT_REASON_RDRAND] = handle_invalid_op,
5601 [EXIT_REASON_RDSEED] = handle_invalid_op,
55d2375e
SC		 5602 [EXIT_REASON_PML_FULL] = handle_pml_full,
5603 [EXIT_REASON_INVPCID] = handle_invpcid,
5604 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5605 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5606 [EXIT_REASON_ENCLS] = handle_encls,
5607};
b8bbab92 5608
55d2375e
SC		 5609static const int kvm_vmx_max_exit_handlers =
5610 ARRAY_SIZE(kvm_vmx_exit_handlers);
ec378aee 5611
55d2375e 5612static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
ec378aee 5613{
55d2375e
SC		 5614 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5615 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
ec378aee
NHE		 5616}
5617
55d2375e 5618static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
27d6c865 5619{
55d2375e
SC		 5620 if (vmx->pml_pg) {
5621 __free_page(vmx->pml_pg);
5622 vmx->pml_pg = NULL;
b8bbab92 5623 }
27d6c865
NHE		 5624}
5625
55d2375e 5626static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
cd232ad0 5627{
55d2375e
SC		 5628 struct vcpu_vmx *vmx = to_vmx(vcpu);
5629 u64 *pml_buf;
5630 u16 pml_idx;
cd232ad0 5631
55d2375e 5632 pml_idx = vmcs_read16(GUEST_PML_INDEX);
cd232ad0 5633
55d2375e
SC		 5634 /* Do nothing if PML buffer is empty */
5635 if (pml_idx == (PML_ENTITY_NUM - 1))
5636 return;
cd232ad0 5637
55d2375e
SC		 5638 /* PML index always points to next available PML buffer entity */
5639 if (pml_idx >= PML_ENTITY_NUM)
5640 pml_idx = 0;
5641 else
5642 pml_idx++;
945679e3 5643
55d2375e
SC		 5644 pml_buf = page_address(vmx->pml_pg);
5645 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5646 u64 gpa;
945679e3 5647
55d2375e
SC		 5648 gpa = pml_buf[pml_idx];
5649 WARN_ON(gpa & (PAGE_SIZE - 1));
5650 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
945679e3
VK		 5651 }
5652
55d2375e
SC		 5653 /* reset PML index */
5654 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
945679e3
VK		 5655}
5656
f4160e45 5657/*
55d2375e
SC		 5658 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5659 * Called before reporting dirty_bitmap to userspace.
f4160e45 5660 */
55d2375e 5661static void kvm_flush_pml_buffers(struct kvm *kvm)
49f705c5 5662{
55d2375e
SC		 5663 int i;
5664 struct kvm_vcpu *vcpu;
49f705c5 5665 /*
55d2375e
SC		 5666 * We only need to kick vcpu out of guest mode here, as PML buffer
5667 * is flushed at beginning of all VMEXITs, and it's obvious that only
5668 * vcpus running in guest are possible to have unflushed GPAs in PML
5669 * buffer.
49f705c5 5670 */
55d2375e
SC		 5671 kvm_for_each_vcpu(i, vcpu, kvm)
5672 kvm_vcpu_kick(vcpu);
49f705c5
NHE		 5673}
5674
55d2375e 5675static void vmx_dump_sel(char *name, uint32_t sel)
49f705c5 5676{
55d2375e
SC		 5677 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5678 name, vmcs_read16(sel),
5679 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5680 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5681 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
49f705c5
NHE		 5682}
5683
55d2375e 5684static void vmx_dump_dtsel(char *name, uint32_t limit)
a8bc284e 5685{
55d2375e
SC		 5686 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5687 name, vmcs_read32(limit),
5688 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
a8bc284e
JM		 5689}
5690
69090810 5691void dump_vmcs(void)
63846663 5692{
6f2f8453
PB		 5693 u32 vmentry_ctl, vmexit_ctl;
5694 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5695 unsigned long cr4;
5696 u64 efer;
55d2375e 5697 int i, n;
63846663 5698
6f2f8453
PB		 5699 if (!dump_invalid_vmcs) {
5700 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5701 return;
5702 }
5703
5704 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5705 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5706 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5707 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5708 cr4 = vmcs_readl(GUEST_CR4);
5709 efer = vmcs_read64(GUEST_IA32_EFER);
5710 secondary_exec_control = 0;
55d2375e
SC		 5711 if (cpu_has_secondary_exec_ctrls())
5712 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
14c07ad8 5713
55d2375e
SC		 5714 pr_err("*** Guest State ***\n");
5715 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5716 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5717 vmcs_readl(CR0_GUEST_HOST_MASK));
5718 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5719 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5720 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5721 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5722 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5723 {
5724 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5725 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5726 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5727 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
e9ac033e 5728 }
55d2375e
SC		 5729 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5730 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5731 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5732 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5733 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5734 vmcs_readl(GUEST_SYSENTER_ESP),
5735 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5736 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5737 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5738 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5739 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5740 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5741 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5742 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5743 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5744 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5745 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5746 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5747 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5748 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5749 efer, vmcs_read64(GUEST_IA32_PAT));
5750 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5751 vmcs_read64(GUEST_IA32_DEBUGCTL),
5752 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5753 if (cpu_has_load_perf_global_ctrl() &&
5754 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5755 pr_err("PerfGlobCtl = 0x%016llx\n",
5756 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5757 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5758 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5759 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5760 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5761 vmcs_read32(GUEST_ACTIVITY_STATE));
5762 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5763 pr_err("InterruptStatus = %04x\n",
5764 vmcs_read16(GUEST_INTR_STATUS));
ff651cb6 5765
55d2375e
SC		 5766 pr_err("*** Host State ***\n");
5767 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5768 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5769 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5770 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5771 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5772 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5773 vmcs_read16(HOST_TR_SELECTOR));
5774 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5775 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5776 vmcs_readl(HOST_TR_BASE));
5777 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5778 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5779 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5780 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5781 vmcs_readl(HOST_CR4));
5782 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5783 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5784 vmcs_read32(HOST_IA32_SYSENTER_CS),
5785 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5786 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5787 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5788 vmcs_read64(HOST_IA32_EFER),
5789 vmcs_read64(HOST_IA32_PAT));
5790 if (cpu_has_load_perf_global_ctrl() &&
5791 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5792 pr_err("PerfGlobCtl = 0x%016llx\n",
5793 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
ff651cb6 5794
55d2375e
SC		 5795 pr_err("*** Control State ***\n");
5796 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5797 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5798 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5799 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5800 vmcs_read32(EXCEPTION_BITMAP),
5801 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5802 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5803 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5804 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5805 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5806 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5807 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5808 vmcs_read32(VM_EXIT_INTR_INFO),
5809 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5810 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5811 pr_err(" reason=%08x qualification=%016lx\n",
5812 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5813 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5814 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5815 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5816 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5817 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5818 pr_err("TSC Multiplier = 0x%016llx\n",
5819 vmcs_read64(TSC_MULTIPLIER));
9d609649
PB		 5820 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5821 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5822 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5823 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5824 }
d6a85c32 5825 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
9d609649
PB		 5826 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5827 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
d6a85c32 5828 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
9d609649 5829 }
55d2375e
SC		 5830 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5831 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5832 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5833 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5834 n = vmcs_read32(CR3_TARGET_COUNT);
5835 for (i = 0; i + 1 < n; i += 4)
5836 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5837 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5838 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5839 if (i < n)
5840 pr_err("CR3 target%u=%016lx\n",
5841 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5842 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5843 pr_err("PLE Gap=%08x Window=%08x\n",
5844 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5845 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5846 pr_err("Virtual processor ID = 0x%04x\n",
5847 vmcs_read16(VIRTUAL_PROCESSOR_ID));
ff651cb6
WV		 5848}
5849
55d2375e
SC		 5850/*
5851 * The guest has exited. See if we can fix it or if we need userspace
5852 * assistance.
5853 */
1e9e2622
WL		 5854static int vmx_handle_exit(struct kvm_vcpu *vcpu,
5855 enum exit_fastpath_completion exit_fastpath)
ff651cb6 5856{
55d2375e
SC		 5857 struct vcpu_vmx *vmx = to_vmx(vcpu);
5858 u32 exit_reason = vmx->exit_reason;
5859 u32 vectoring_info = vmx->idt_vectoring_info;
ff651cb6 5860
55d2375e 5861 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
ff651cb6 5862
55d2375e
SC		 5863 /*
5864 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5865 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5866 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5867 * mode as if vcpus is in root mode, the PML buffer must has been
5868 * flushed already.
5869 */
5870 if (enable_pml)
5871 vmx_flush_pml_buffer(vcpu);
1dc35dac 5872
55d2375e
SC		 5873 /* If guest state is invalid, start emulating */
5874 if (vmx->emulation_required)
5875 return handle_invalid_guest_state(vcpu);
1dc35dac 5876
55d2375e
SC		 5877 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5878 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
9ed38ffa 5879
55d2375e
SC		 5880 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5881 dump_vmcs();
5882 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5883 vcpu->run->fail_entry.hardware_entry_failure_reason
5884 = exit_reason;
5885 return 0;
9ed38ffa
LP		 5886 }
5887
55d2375e 5888 if (unlikely(vmx->fail)) {
3b20e03a 5889 dump_vmcs();
55d2375e
SC		 5890 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5891 vcpu->run->fail_entry.hardware_entry_failure_reason
5892 = vmcs_read32(VM_INSTRUCTION_ERROR);
5893 return 0;
5894 }
50c28f21 5895
55d2375e
SC		 5896 /*
5897 * Note:
5898 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5899 * delivery event since it indicates guest is accessing MMIO.
5900 * The vm-exit can be triggered again after return to guest that
5901 * will cause infinite loop.
5902 */
5903 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5904 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5905 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5906 exit_reason != EXIT_REASON_PML_FULL &&
5907 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5908 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5909 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5910 vcpu->run->internal.ndata = 3;
5911 vcpu->run->internal.data[0] = vectoring_info;
5912 vcpu->run->internal.data[1] = exit_reason;
5913 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5914 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5915 vcpu->run->internal.ndata++;
5916 vcpu->run->internal.data[3] =
5917 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5918 }
5919 return 0;
5920 }
50c28f21 5921
55d2375e
SC		 5922 if (unlikely(!enable_vnmi &&
5923 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5924 if (vmx_interrupt_allowed(vcpu)) {
5925 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5926 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5927 vcpu->arch.nmi_pending) {
5928 /*
5929 * This CPU don't support us in finding the end of an
5930 * NMI-blocked window if the guest runs with IRQs
5931 * disabled. So we pull the trigger after 1 s of
5932 * futile waiting, but inform the user about this.
5933 */
5934 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5935 "state on VCPU %d after 1 s timeout\n",
5936 __func__, vcpu->vcpu_id);
5937 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5938 }
5939 }
50c28f21 5940
1e9e2622
WL		 5941 if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) {
5942 kvm_skip_emulated_instruction(vcpu);
5943 return 1;
c926f2f7
MP		 5944 }
5945
5946 if (exit_reason >= kvm_vmx_max_exit_handlers)
5947 goto unexpected_vmexit;
4289d272 5948#ifdef CONFIG_RETPOLINE
c926f2f7
MP		 5949 if (exit_reason == EXIT_REASON_MSR_WRITE)
5950 return kvm_emulate_wrmsr(vcpu);
5951 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER)
5952 return handle_preemption_timer(vcpu);
5953 else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW)
5954 return handle_interrupt_window(vcpu);
5955 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
5956 return handle_external_interrupt(vcpu);
5957 else if (exit_reason == EXIT_REASON_HLT)
5958 return kvm_emulate_halt(vcpu);
5959 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG)
5960 return handle_ept_misconfig(vcpu);
4289d272 5961#endif
c926f2f7
MP		 5962
5963 exit_reason = array_index_nospec(exit_reason,
5964 kvm_vmx_max_exit_handlers);
5965 if (!kvm_vmx_exit_handlers[exit_reason])
5966 goto unexpected_vmexit;
5967
5968 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5969
5970unexpected_vmexit:
5971 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason);
5972 dump_vmcs();
5973 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5974 vcpu->run->internal.suberror =
7396d337 5975 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
c926f2f7
MP		 5976 vcpu->run->internal.ndata = 1;
5977 vcpu->run->internal.data[0] = exit_reason;
5978 return 0;
9ed38ffa
LP		 5979}
5980
efebf0aa 5981/*
55d2375e
SC		 5982 * Software based L1D cache flush which is used when microcode providing
5983 * the cache control MSR is not loaded.
efebf0aa 5984 *
55d2375e
SC		 5985 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5986 * flush it is required to read in 64 KiB because the replacement algorithm
5987 * is not exactly LRU. This could be sized at runtime via topology
5988 * information but as all relevant affected CPUs have 32KiB L1D cache size
5989 * there is no point in doing so.
efebf0aa 5990 */
55d2375e 5991static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
fe3ef05c 5992{
55d2375e 5993 int size = PAGE_SIZE << L1D_CACHE_ORDER;
25a2e4fe
PB		 5994
5995 /*
55d2375e
SC		 5996 * This code is only executed when the the flush mode is 'cond' or
5997 * 'always'
25a2e4fe 5998 */
55d2375e
SC		 5999 if (static_branch_likely(&vmx_l1d_flush_cond)) {
6000 bool flush_l1d;
25a2e4fe 6001
55d2375e
SC		 6002 /*
6003 * Clear the per-vcpu flush bit, it gets set again
6004 * either from vcpu_run() or from one of the unsafe
6005 * VMEXIT handlers.
6006 */
6007 flush_l1d = vcpu->arch.l1tf_flush_l1d;
6008 vcpu->arch.l1tf_flush_l1d = false;
25a2e4fe 6009
55d2375e
SC		 6010 /*
6011 * Clear the per-cpu flush bit, it gets set again from
6012 * the interrupt handlers.
6013 */
6014 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6015 kvm_clear_cpu_l1tf_flush_l1d();
25a2e4fe 6016
55d2375e
SC		 6017 if (!flush_l1d)
6018 return;
6019 }
09abe320 6020
55d2375e 6021 vcpu->stat.l1d_flush++;
25a2e4fe 6022
55d2375e
SC		 6023 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6024 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6025 return;
6026 }
25a2e4fe 6027
55d2375e
SC		 6028 asm volatile(
6029 /* First ensure the pages are in the TLB */
6030 "xorl %%eax, %%eax\n"
6031 ".Lpopulate_tlb:\n\t"
6032 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6033 "addl $4096, %%eax\n\t"
6034 "cmpl %%eax, %[size]\n\t"
6035 "jne .Lpopulate_tlb\n\t"
6036 "xorl %%eax, %%eax\n\t"
6037 "cpuid\n\t"
6038 /* Now fill the cache */
6039 "xorl %%eax, %%eax\n"
6040 ".Lfill_cache:\n"
6041 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6042 "addl $64, %%eax\n\t"
6043 "cmpl %%eax, %[size]\n\t"
6044 "jne .Lfill_cache\n\t"
6045 "lfence\n"
6046 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6047 [size] "r" (size)
6048 : "eax", "ebx", "ecx", "edx");
09abe320 6049}
25a2e4fe 6050
55d2375e 6051static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
09abe320 6052{
55d2375e 6053 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
132f4f7e 6054 int tpr_threshold;
09abe320 6055
55d2375e
SC		 6056 if (is_guest_mode(vcpu) &&
6057 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6058 return;
25a2e4fe 6059
132f4f7e 6060 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
02d496cf
LA		 6061 if (is_guest_mode(vcpu))
6062 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6063 else
6064 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
8665c3f9
PB		 6065}
6066
55d2375e 6067void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
8665c3f9 6068{
fe7f895d 6069 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e 6070 u32 sec_exec_control;
8665c3f9 6071
55d2375e
SC		 6072 if (!lapic_in_kernel(vcpu))
6073 return;
9314006d 6074
55d2375e
SC		 6075 if (!flexpriority_enabled &&
6076 !cpu_has_vmx_virtualize_x2apic_mode())
6077 return;
705699a1 6078
55d2375e
SC		 6079 /* Postpone execution until vmcs01 is the current VMCS. */
6080 if (is_guest_mode(vcpu)) {
fe7f895d 6081 vmx->nested.change_vmcs01_virtual_apic_mode = true;
55d2375e 6082 return;
6beb7bd5 6083 }
fe3ef05c 6084
fe7f895d 6085 sec_exec_control = secondary_exec_controls_get(vmx);
55d2375e
SC		 6086 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6087 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
09abe320 6088
55d2375e
SC		 6089 switch (kvm_get_apic_mode(vcpu)) {
6090 case LAPIC_MODE_INVALID:
6091 WARN_ONCE(true, "Invalid local APIC state");
6092 case LAPIC_MODE_DISABLED:
6093 break;
6094 case LAPIC_MODE_XAPIC:
6095 if (flexpriority_enabled) {
6096 sec_exec_control |=
6097 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6098 vmx_flush_tlb(vcpu, true);
6099 }
6100 break;
6101 case LAPIC_MODE_X2APIC:
6102 if (cpu_has_vmx_virtualize_x2apic_mode())
6103 sec_exec_control |=
6104 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6105 break;
09abe320 6106 }
fe7f895d 6107 secondary_exec_controls_set(vmx, sec_exec_control);
09abe320 6108
55d2375e
SC		 6109 vmx_update_msr_bitmap(vcpu);
6110}
0238ea91 6111
55d2375e
SC		 6112static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6113{
6114 if (!is_guest_mode(vcpu)) {
6115 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6116 vmx_flush_tlb(vcpu, true);
6117 }
6118}
fe3ef05c 6119
55d2375e
SC		 6120static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6121{
6122 u16 status;
6123 u8 old;
32c7acf0 6124
55d2375e
SC		 6125 if (max_isr == -1)
6126 max_isr = 0;
608406e2 6127
55d2375e
SC		 6128 status = vmcs_read16(GUEST_INTR_STATUS);
6129 old = status >> 8;
6130 if (max_isr != old) {
6131 status &= 0xff;
6132 status |= max_isr << 8;
6133 vmcs_write16(GUEST_INTR_STATUS, status);
6134 }
6135}
6beb7bd5 6136
55d2375e
SC		 6137static void vmx_set_rvi(int vector)
6138{
6139 u16 status;
6140 u8 old;
0b665d30 6141
55d2375e
SC		 6142 if (vector == -1)
6143 vector = 0;
fe3ef05c 6144
55d2375e
SC		 6145 status = vmcs_read16(GUEST_INTR_STATUS);
6146 old = (u8)status & 0xff;
6147 if ((u8)vector != old) {
6148 status &= ~0xff;
6149 status |= (u8)vector;
6150 vmcs_write16(GUEST_INTR_STATUS, status);
09abe320 6151 }
55d2375e 6152}
09abe320 6153
55d2375e
SC		 6154static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6155{
09abe320 6156 /*
55d2375e
SC		 6157 * When running L2, updating RVI is only relevant when
6158 * vmcs12 virtual-interrupt-delivery enabled.
6159 * However, it can be enabled only when L1 also
6160 * intercepts external-interrupts and in that case
6161 * we should not update vmcs02 RVI but instead intercept
6162 * interrupt. Therefore, do nothing when running L2.
fe3ef05c 6163 */
55d2375e
SC		 6164 if (!is_guest_mode(vcpu))
6165 vmx_set_rvi(max_irr);
6166}
fe3ef05c 6167
55d2375e
SC		 6168static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6169{
6170 struct vcpu_vmx *vmx = to_vmx(vcpu);
6171 int max_irr;
6172 bool max_irr_updated;
a7c0b07d 6173
55d2375e
SC		 6174 WARN_ON(!vcpu->arch.apicv_active);
6175 if (pi_test_on(&vmx->pi_desc)) {
6176 pi_clear_on(&vmx->pi_desc);
6177 /*
d9ff2744 6178 * IOMMU can write to PID.ON, so the barrier matters even on UP.
55d2375e
SC		 6179 * But on x86 this is just a compiler barrier anyway.
6180 */
6181 smp_mb__after_atomic();
6182 max_irr_updated =
6183 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
c4ebd629
VK		 6184
6185 /*
55d2375e
SC		 6186 * If we are running L2 and L1 has a new pending interrupt
6187 * which can be injected, we should re-evaluate
6188 * what should be done with this new L1 interrupt.
6189 * If L1 intercepts external-interrupts, we should
6190 * exit from L2 to L1. Otherwise, interrupt should be
6191 * delivered directly to L2.
c4ebd629 6192 */
55d2375e
SC		 6193 if (is_guest_mode(vcpu) && max_irr_updated) {
6194 if (nested_exit_on_intr(vcpu))
6195 kvm_vcpu_exiting_guest_mode(vcpu);
6196 else
6197 kvm_make_request(KVM_REQ_EVENT, vcpu);
c4ebd629 6198 }
55d2375e
SC		 6199 } else {
6200 max_irr = kvm_lapic_find_highest_irr(vcpu);
a7c0b07d 6201 }
55d2375e
SC		 6202 vmx_hwapic_irr_update(vcpu, max_irr);
6203 return max_irr;
6204}
a7c0b07d 6205
17e433b5
WL		 6206static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6207{
9482ae45
JM		 6208 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6209
6210 return pi_test_on(pi_desc) ||
29881b6e 6211 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
17e433b5
WL		 6212}
6213
55d2375e
SC		 6214static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6215{
6216 if (!kvm_vcpu_apicv_active(vcpu))
6217 return;
25a2e4fe 6218
55d2375e
SC		 6219 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6220 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6221 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6222 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8665c3f9
PB		 6223}
6224
55d2375e 6225static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8665c3f9
PB		 6226{
6227 struct vcpu_vmx *vmx = to_vmx(vcpu);
9d1887ef 6228
55d2375e
SC		 6229 pi_clear_on(&vmx->pi_desc);
6230 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6231}
8665c3f9 6232
95b5a48c 6233static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
55d2375e 6234{
beb8d93b 6235 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
fe3ef05c 6236
55d2375e 6237 /* if exit due to PF check for async PF */
beb8d93b 6238 if (is_page_fault(vmx->exit_intr_info))
55d2375e 6239 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
e79f245d 6240
55d2375e 6241 /* Handle machine checks before interrupts are enabled */
beb8d93b 6242 if (is_machine_check(vmx->exit_intr_info))
55d2375e 6243 kvm_machine_check();
fe3ef05c 6244
55d2375e 6245 /* We need to handle NMIs before interrupts are enabled */
beb8d93b 6246 if (is_nmi(vmx->exit_intr_info)) {
55d2375e
SC		 6247 kvm_before_interrupt(&vmx->vcpu);
6248 asm("int $2");
6249 kvm_after_interrupt(&vmx->vcpu);
fe3ef05c 6250 }
55d2375e 6251}
fe3ef05c 6252
95b5a48c 6253static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
55d2375e 6254{
49def500
SC		 6255 unsigned int vector;
6256 unsigned long entry;
55d2375e 6257#ifdef CONFIG_X86_64
49def500 6258 unsigned long tmp;
55d2375e 6259#endif
49def500
SC		 6260 gate_desc *desc;
6261 u32 intr_info;
fe3ef05c 6262
49def500
SC		 6263 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6264 if (WARN_ONCE(!is_external_intr(intr_info),
6265 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6266 return;
6267
6268 vector = intr_info & INTR_INFO_VECTOR_MASK;
2342080c 6269 desc = (gate_desc *)host_idt_base + vector;
49def500
SC		 6270 entry = gate_offset(desc);
6271
165072b0
SC		 6272 kvm_before_interrupt(vcpu);
6273
49def500 6274 asm volatile(
55d2375e 6275#ifdef CONFIG_X86_64
49def500
SC		 6276 "mov %%" _ASM_SP ", %[sp]\n\t"
6277 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6278 "push $%c[ss]\n\t"
6279 "push %[sp]\n\t"
55d2375e 6280#endif
49def500
SC		 6281 "pushf\n\t"
6282 __ASM_SIZE(push) " $%c[cs]\n\t"
6283 CALL_NOSPEC
6284 :
55d2375e 6285#ifdef CONFIG_X86_64
49def500 6286 [sp]"=&r"(tmp),
55d2375e 6287#endif
49def500
SC		 6288 ASM_CALL_CONSTRAINT
6289 :
428b8f1d 6290 [thunk_target]"r"(entry),
49def500
SC		 6291 [ss]"i"(__KERNEL_DS),
6292 [cs]"i"(__KERNEL_CS)
6293 );
165072b0
SC		 6294
6295 kvm_after_interrupt(vcpu);
55d2375e 6296}
95b5a48c
SC		 6297STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6298
1e9e2622
WL		 6299static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu,
6300 enum exit_fastpath_completion *exit_fastpath)
95b5a48c
SC		 6301{
6302 struct vcpu_vmx *vmx = to_vmx(vcpu);
6303
6304 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6305 handle_external_interrupt_irqoff(vcpu);
6306 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6307 handle_exception_nmi_irqoff(vmx);
1e9e2622
WL		 6308 else if (!is_guest_mode(vcpu) &&
6309 vmx->exit_reason == EXIT_REASON_MSR_WRITE)
6310 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu);
95b5a48c 6311}
5a6a9748 6312
55d2375e
SC		 6313static bool vmx_has_emulated_msr(int index)
6314{
6315 switch (index) {
6316 case MSR_IA32_SMBASE:
6317 /*
6318 * We cannot do SMM unless we can run the guest in big
6319 * real mode.
6320 */
6321 return enable_unrestricted_guest || emulate_invalid_guest_state;
95c5c7c7
PB		 6322 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6323 return nested;
55d2375e
SC		 6324 case MSR_AMD64_VIRT_SPEC_CTRL:
6325 /* This is AMD only. */
6326 return false;
6327 default:
6328 return true;
3184a995 6329 }
55d2375e 6330}
2bb8cafe 6331
86f5201d
CP		 6332static bool vmx_pt_supported(void)
6333{
6334 return pt_mode == PT_MODE_HOST_GUEST;
6335}
6336
55d2375e
SC		 6337static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6338{
6339 u32 exit_intr_info;
6340 bool unblock_nmi;
6341 u8 vector;
6342 bool idtv_info_valid;
7ca29de2 6343
55d2375e 6344 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
feaf0c7d 6345
55d2375e
SC		 6346 if (enable_vnmi) {
6347 if (vmx->loaded_vmcs->nmi_known_unmasked)
6348 return;
6349 /*
6350 * Can't use vmx->exit_intr_info since we're not sure what
6351 * the exit reason is.
6352 */
6353 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6354 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6355 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6356 /*
6357 * SDM 3: 27.7.1.2 (September 2008)
6358 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6359 * a guest IRET fault.
6360 * SDM 3: 23.2.2 (September 2008)
6361 * Bit 12 is undefined in any of the following cases:
6362 * If the VM exit sets the valid bit in the IDT-vectoring
6363 * information field.
6364 * If the VM exit is due to a double fault.
6365 */
6366 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6367 vector != DF_VECTOR && !idtv_info_valid)
6368 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6369 GUEST_INTR_STATE_NMI);
6370 else
6371 vmx->loaded_vmcs->nmi_known_unmasked =
6372 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6373 & GUEST_INTR_STATE_NMI);
6374 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6375 vmx->loaded_vmcs->vnmi_blocked_time +=
6376 ktime_to_ns(ktime_sub(ktime_get(),
6377 vmx->loaded_vmcs->entry_time));
fe3ef05c
NHE		 6378}
6379
55d2375e
SC		 6380static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6381 u32 idt_vectoring_info,
6382 int instr_len_field,
6383 int error_code_field)
0c7f650e 6384{
55d2375e
SC		 6385 u8 vector;
6386 int type;
6387 bool idtv_info_valid;
0c7f650e 6388
55d2375e 6389 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
0c7f650e 6390
55d2375e
SC		 6391 vcpu->arch.nmi_injected = false;
6392 kvm_clear_exception_queue(vcpu);
6393 kvm_clear_interrupt_queue(vcpu);
27c42a1b 6394
55d2375e
SC		 6395 if (!idtv_info_valid)
6396 return;
c7c2c709 6397
55d2375e 6398 kvm_make_request(KVM_REQ_EVENT, vcpu);
ca0bde28 6399
55d2375e
SC		 6400 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6401 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
64a919f7 6402
55d2375e
SC		 6403 switch (type) {
6404 case INTR_TYPE_NMI_INTR:
6405 vcpu->arch.nmi_injected = true;
6406 /*
6407 * SDM 3: 27.7.1.2 (September 2008)
6408 * Clear bit "block by NMI" before VM entry if a NMI
6409 * delivery faulted.
6410 */
6411 vmx_set_nmi_mask(vcpu, false);
6412 break;
6413 case INTR_TYPE_SOFT_EXCEPTION:
6414 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6415 /* fall through */
6416 case INTR_TYPE_HARD_EXCEPTION:
6417 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6418 u32 err = vmcs_read32(error_code_field);
6419 kvm_requeue_exception_e(vcpu, vector, err);
6420 } else
6421 kvm_requeue_exception(vcpu, vector);
6422 break;
6423 case INTR_TYPE_SOFT_INTR:
6424 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6425 /* fall through */
6426 case INTR_TYPE_EXT_INTR:
6427 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6428 break;
6429 default:
6430 break;
0447378a 6431 }
ca0bde28
JM		 6432}
6433
55d2375e 6434static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
f145d90d 6435{
55d2375e
SC		 6436 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6437 VM_EXIT_INSTRUCTION_LEN,
6438 IDT_VECTORING_ERROR_CODE);
f145d90d
LA		 6439}
6440
55d2375e 6441static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
ca0bde28 6442{
55d2375e
SC		 6443 __vmx_complete_interrupts(vcpu,
6444 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6445 VM_ENTRY_INSTRUCTION_LEN,
6446 VM_ENTRY_EXCEPTION_ERROR_CODE);
f1b026a3 6447
55d2375e 6448 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
ca0bde28
JM		 6449}
6450
55d2375e 6451static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
52017608 6452{
55d2375e
SC		 6453 int i, nr_msrs;
6454 struct perf_guest_switch_msr *msrs;
7c177938 6455
55d2375e 6456 msrs = perf_guest_get_msrs(&nr_msrs);
384bb783 6457
55d2375e
SC		 6458 if (!msrs)
6459 return;
f1b026a3 6460
55d2375e
SC		 6461 for (i = 0; i < nr_msrs; i++)
6462 if (msrs[i].host == msrs[i].guest)
6463 clear_atomic_switch_msr(vmx, msrs[i].msr);
6464 else
6465 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6466 msrs[i].host, false);
ca0bde28 6467}
52017608 6468
6e3ba4ab
TX		 6469static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
6470{
6471 u32 host_umwait_control;
6472
6473 if (!vmx_has_waitpkg(vmx))
6474 return;
6475
6476 host_umwait_control = get_umwait_control_msr();
6477
6478 if (vmx->msr_ia32_umwait_control != host_umwait_control)
6479 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
6480 vmx->msr_ia32_umwait_control,
6481 host_umwait_control, false);
6482 else
6483 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
6484}
6485
55d2375e 6486static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
858e25c0
JM		 6487{
6488 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e
SC		 6489 u64 tscl;
6490 u32 delta_tsc;
52017608 6491
55d2375e 6492 if (vmx->req_immediate_exit) {
804939ea
SC		 6493 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6494 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6495 } else if (vmx->hv_deadline_tsc != -1) {
55d2375e
SC		 6496 tscl = rdtsc();
6497 if (vmx->hv_deadline_tsc > tscl)
6498 /* set_hv_timer ensures the delta fits in 32-bits */
6499 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6500 cpu_preemption_timer_multi);
6501 else
6502 delta_tsc = 0;
858e25c0 6503
804939ea
SC		 6504 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6505 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6506 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6507 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6508 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
7f7f1ba3 6509 }
858e25c0
JM		 6510}
6511
c09b03eb 6512void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
ca0bde28 6513{
c09b03eb
SC		 6514 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6515 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6516 vmcs_writel(HOST_RSP, host_rsp);
6517 }
5ad6ece8 6518}
5f3d5799 6519
fc2ba5a2 6520bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
5ad6ece8
SC		 6521
6522static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6523{
6524 struct vcpu_vmx *vmx = to_vmx(vcpu);
6525 unsigned long cr3, cr4;
6526
6527 /* Record the guest's net vcpu time for enforced NMI injections. */
6528 if (unlikely(!enable_vnmi &&
6529 vmx->loaded_vmcs->soft_vnmi_blocked))
6530 vmx->loaded_vmcs->entry_time = ktime_get();
6531
6532 /* Don't enter VMX if guest state is invalid, let the exit handler
6533 start emulation until we arrive back to a valid state */
6534 if (vmx->emulation_required)
6535 return;
6536
6537 if (vmx->ple_window_dirty) {
6538 vmx->ple_window_dirty = false;
6539 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6540 }
6541
c9dfd3fb 6542 /*
6543 * We did this in prepare_switch_to_guest, because it needs to
6544 * be within srcu_read_lock.
6545 */
6546 WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
5ad6ece8 6547
cb3c1e2f 6548 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
5ad6ece8 6549 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
cb3c1e2f 6550 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
5ad6ece8
SC		 6551 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6552
6553 cr3 = __get_current_cr3_fast();
6554 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6555 vmcs_writel(HOST_CR3, cr3);
6556 vmx->loaded_vmcs->host_state.cr3 = cr3;
6557 }
6558
6559 cr4 = cr4_read_shadow();
6560 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6561 vmcs_writel(HOST_CR4, cr4);
6562 vmx->loaded_vmcs->host_state.cr4 = cr4;
6563 }
6564
6565 /* When single-stepping over STI and MOV SS, we must clear the
6566 * corresponding interruptibility bits in the guest state. Otherwise
6567 * vmentry fails as it then expects bit 14 (BS) in pending debug
6568 * exceptions being set, but that's not correct for the guest debugging
6569 * case. */
6570 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6571 vmx_set_interrupt_shadow(vcpu, 0);
6572
139a12cf 6573 kvm_load_guest_xsave_state(vcpu);
1811d979 6574
5ad6ece8
SC		 6575 if (static_cpu_has(X86_FEATURE_PKU) &&
6576 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6577 vcpu->arch.pkru != vmx->host_pkru)
6578 __write_pkru(vcpu->arch.pkru);
6579
6580 pt_guest_enter(vmx);
6581
6582 atomic_switch_perf_msrs(vmx);
6e3ba4ab 6583 atomic_switch_umwait_control_msr(vmx);
5ad6ece8 6584
804939ea
SC		 6585 if (enable_preemption_timer)
6586 vmx_update_hv_timer(vcpu);
5ad6ece8 6587
b6c4bc65
WL		 6588 if (lapic_in_kernel(vcpu) &&
6589 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6590 kvm_wait_lapic_expire(vcpu);
6591
5ad6ece8
SC		 6592 /*
6593 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6594 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6595 * is no need to worry about the conditional branch over the wrmsr
6596 * being speculatively taken.
6597 */
6598 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6599
fa4bff16 6600 /* L1D Flush includes CPU buffer clear to mitigate MDS */
c823dd5c
SC		 6601 if (static_branch_unlikely(&vmx_l1d_should_flush))
6602 vmx_l1d_flush(vcpu);
fa4bff16
LT		 6603 else if (static_branch_unlikely(&mds_user_clear))
6604 mds_clear_cpu_buffers();
c823dd5c
SC		 6605
6606 if (vcpu->arch.cr2 != read_cr2())
6607 write_cr2(vcpu->arch.cr2);
6608
fc2ba5a2
SC		 6609 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6610 vmx->loaded_vmcs->launched);
c823dd5c
SC		 6611
6612 vcpu->arch.cr2 = read_cr2();
b6b8a145 6613
55d2375e
SC		 6614 /*
6615 * We do not use IBRS in the kernel. If this vCPU has used the
6616 * SPEC_CTRL MSR it may have left it on; save the value and
6617 * turn it off. This is much more efficient than blindly adding
6618 * it to the atomic save/restore list. Especially as the former
6619 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6620 *
6621 * For non-nested case:
6622 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6623 * save it.
6624 *
6625 * For nested case:
6626 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6627 * save it.
6628 */
6629 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6630 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
b6b8a145 6631
55d2375e 6632 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
d264ee0c 6633
55d2375e
SC		 6634 /* All fields are clean at this point */
6635 if (static_branch_unlikely(&enable_evmcs))
6636 current_evmcs->hv_clean_fields |=
6637 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
f4124500 6638
6f6a657c
VK		 6639 if (static_branch_unlikely(&enable_evmcs))
6640 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6641
55d2375e
SC		 6642 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6643 if (vmx->host_debugctlmsr)
6644 update_debugctlmsr(vmx->host_debugctlmsr);
f4124500 6645
55d2375e
SC		 6646#ifndef CONFIG_X86_64
6647 /*
6648 * The sysexit path does not restore ds/es, so we must set them to
6649 * a reasonable value ourselves.
6650 *
6651 * We can't defer this to vmx_prepare_switch_to_host() since that
6652 * function may be executed in interrupt context, which saves and
6653 * restore segments around it, nullifying its effect.
6654 */
6655 loadsegment(ds, __USER_DS);
6656 loadsegment(es, __USER_DS);
6657#endif
4704d0be 6658
55d2375e
SC		 6659 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6660 | (1 << VCPU_EXREG_RFLAGS)
6661 | (1 << VCPU_EXREG_PDPTR)
6662 | (1 << VCPU_EXREG_SEGMENTS)
6663 | (1 << VCPU_EXREG_CR3));
6664 vcpu->arch.regs_dirty = 0;
7854cbca 6665
2ef444f1
CP		 6666 pt_guest_exit(vmx);
6667
3633cfc3 6668 /*
55d2375e
SC		 6669 * eager fpu is enabled if PKEY is supported and CR4 is switched
6670 * back on host, so it is safe to read guest PKRU from current
6671 * XSAVE.
3633cfc3 6672 */
55d2375e
SC		 6673 if (static_cpu_has(X86_FEATURE_PKU) &&
6674 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
c806e887 6675 vcpu->arch.pkru = rdpkru();
55d2375e
SC		 6676 if (vcpu->arch.pkru != vmx->host_pkru)
6677 __write_pkru(vmx->host_pkru);
3633cfc3
NHE		 6678 }
6679
139a12cf 6680 kvm_load_host_xsave_state(vcpu);
1811d979 6681
55d2375e
SC		 6682 vmx->nested.nested_run_pending = 0;
6683 vmx->idt_vectoring_info = 0;
119a9c01 6684
55d2375e 6685 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
beb8d93b
SC		 6686 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6687 kvm_machine_check();
6688
55d2375e
SC		 6689 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6690 return;
608406e2 6691
55d2375e
SC		 6692 vmx->loaded_vmcs->launched = 1;
6693 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
c18911a2 6694
55d2375e
SC		 6695 vmx_recover_nmi_blocking(vmx);
6696 vmx_complete_interrupts(vmx);
6697}
2996fca0 6698
55d2375e
SC		 6699static struct kvm *vmx_vm_alloc(void)
6700{
41836839
BG		 6701 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
6702 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
6703 PAGE_KERNEL);
55d2375e 6704 return &kvm_vmx->kvm;
cf8b84f4
JM		 6705}
6706
55d2375e
SC		 6707static void vmx_vm_free(struct kvm *kvm)
6708{
6f6a657c 6709 kfree(kvm->arch.hyperv.hv_pa_pg);
55d2375e
SC		 6710 vfree(to_kvm_vmx(kvm));
6711}
6712
6713static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
cf8b84f4 6714{
55d2375e 6715 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 6716
55d2375e
SC		 6717 if (enable_pml)
6718 vmx_destroy_pml_buffer(vmx);
6719 free_vpid(vmx->vpid);
55d2375e
SC		 6720 nested_vmx_free_vcpu(vcpu);
6721 free_loaded_vmcs(vmx->loaded_vmcs);
55d2375e 6722}
4704d0be 6723
987b2594 6724static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
55d2375e 6725{
41836839 6726 struct vcpu_vmx *vmx;
55d2375e 6727 unsigned long *msr_bitmap;
34109c04 6728 int i, cpu, err;
4704d0be 6729
a9dd6f09
SC		 6730 BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6731 vmx = to_vmx(vcpu);
d9a710e5 6732
55d2375e 6733 err = -ENOMEM;
b666a4b6 6734
55d2375e 6735 vmx->vpid = allocate_vpid();
7cdc2d62 6736
5f3d5799 6737 /*
55d2375e
SC		 6738 * If PML is turned on, failure on enabling PML just results in failure
6739 * of creating the vcpu, therefore we can simplify PML logic (by
6740 * avoiding dealing with cases, such as enabling PML partially on vcpus
67b0ae43 6741 * for the guest), etc.
5f3d5799 6742 */
55d2375e 6743 if (enable_pml) {
41836839 6744 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
55d2375e 6745 if (!vmx->pml_pg)
987b2594 6746 goto free_vpid;
55d2375e 6747 }
4704d0be 6748
7d73710d 6749 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS);
4704d0be 6750
4be53410
XL		 6751 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6752 u32 index = vmx_msr_index[i];
6753 u32 data_low, data_high;
6754 int j = vmx->nmsrs;
6755
6756 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6757 continue;
6758 if (wrmsr_safe(index, data_low, data_high) < 0)
6759 continue;
46f4f0aa 6760
4be53410
XL		 6761 vmx->guest_msrs[j].index = i;
6762 vmx->guest_msrs[j].data = 0;
46f4f0aa
PB		 6763 switch (index) {
6764 case MSR_IA32_TSX_CTRL:
6765 /*
6766 * No need to pass TSX_CTRL_CPUID_CLEAR through, so
6767 * let's avoid changing CPUID bits under the host
6768 * kernel's feet.
6769 */
6770 vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6771 break;
6772 default:
6773 vmx->guest_msrs[j].mask = -1ull;
6774 break;
6775 }
4be53410
XL		 6776 ++vmx->nmsrs;
6777 }
6778
55d2375e
SC		 6779 err = alloc_loaded_vmcs(&vmx->vmcs01);
6780 if (err < 0)
7d73710d 6781 goto free_pml;
cb61de2f 6782
55d2375e 6783 msr_bitmap = vmx->vmcs01.msr_bitmap;
788fc1e9 6784 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
55d2375e
SC		 6785 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6786 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6787 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6788 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6789 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6790 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
987b2594 6791 if (kvm_cstate_in_guest(vcpu->kvm)) {
b5170063
WL		 6792 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6793 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6794 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6795 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6796 }
55d2375e 6797 vmx->msr_bitmap_mode = 0;
4704d0be 6798
55d2375e
SC		 6799 vmx->loaded_vmcs = &vmx->vmcs01;
6800 cpu = get_cpu();
34109c04
SC		 6801 vmx_vcpu_load(vcpu, cpu);
6802 vcpu->cpu = cpu;
1b84292b 6803 init_vmcs(vmx);
34109c04 6804 vmx_vcpu_put(vcpu);
55d2375e 6805 put_cpu();
34109c04 6806 if (cpu_need_virtualize_apic_accesses(vcpu)) {
987b2594 6807 err = alloc_apic_access_page(vcpu->kvm);
55d2375e
SC		 6808 if (err)
6809 goto free_vmcs;
6810 }
6811
6812 if (enable_ept && !enable_unrestricted_guest) {
987b2594 6813 err = init_rmode_identity_map(vcpu->kvm);
55d2375e
SC		 6814 if (err)
6815 goto free_vmcs;
6816 }
4704d0be 6817
55d2375e
SC		 6818 if (nested)
6819 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
a4443267 6820 vmx_capability.ept);
55d2375e
SC		 6821 else
6822 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
bd18bffc 6823
55d2375e
SC		 6824 vmx->nested.posted_intr_nv = -1;
6825 vmx->nested.current_vmptr = -1ull;
bd18bffc 6826
bab0c318 6827 vcpu->arch.microcode_version = 0x100000000ULL;
32ad73db 6828 vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
feaf0c7d 6829
6f1e03bc 6830 /*
55d2375e
SC		 6831 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6832 * or POSTED_INTR_WAKEUP_VECTOR.
6f1e03bc 6833 */
55d2375e
SC		 6834 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6835 vmx->pi_desc.sn = 1;
4704d0be 6836
53963a70
LT		 6837 vmx->ept_pointer = INVALID_PAGE;
6838
a9dd6f09 6839 return 0;
4704d0be 6840
55d2375e
SC		 6841free_vmcs:
6842 free_loaded_vmcs(vmx->loaded_vmcs);
55d2375e
SC		 6843free_pml:
6844 vmx_destroy_pml_buffer(vmx);
987b2594 6845free_vpid:
55d2375e 6846 free_vpid(vmx->vpid);
a9dd6f09 6847 return err;
55d2375e 6848}
36be0b9d 6849
65fd4cb6
TG		 6850#define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6851#define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
21feb4eb 6852
55d2375e
SC		 6853static int vmx_vm_init(struct kvm *kvm)
6854{
6855 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
ff651cb6 6856
55d2375e
SC		 6857 if (!ple_gap)
6858 kvm->arch.pause_in_guest = true;
3af18d9c 6859
55d2375e
SC		 6860 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6861 switch (l1tf_mitigation) {
6862 case L1TF_MITIGATION_OFF:
6863 case L1TF_MITIGATION_FLUSH_NOWARN:
6864 /* 'I explicitly don't care' is set */
6865 break;
6866 case L1TF_MITIGATION_FLUSH:
6867 case L1TF_MITIGATION_FLUSH_NOSMT:
6868 case L1TF_MITIGATION_FULL:
6869 /*
6870 * Warn upon starting the first VM in a potentially
6871 * insecure environment.
6872 */
b284909a 6873 if (sched_smt_active())
55d2375e
SC		 6874 pr_warn_once(L1TF_MSG_SMT);
6875 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6876 pr_warn_once(L1TF_MSG_L1D);
6877 break;
6878 case L1TF_MITIGATION_FULL_FORCE:
6879 /* Flush is enforced */
6880 break;
6881 }
6882 }
4e19c36f 6883 kvm_apicv_init(kvm, enable_apicv);
55d2375e 6884 return 0;
4704d0be
NHE		 6885}
6886
f257d6dc 6887static int __init vmx_check_processor_compat(void)
bd18bffc 6888{
55d2375e
SC		 6889 struct vmcs_config vmcs_conf;
6890 struct vmx_capability vmx_cap;
bd18bffc 6891
ff10e22e
SC		 6892 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6893 !this_cpu_has(X86_FEATURE_VMX)) {
6894 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6895 return -EIO;
6896 }
6897
55d2375e 6898 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
f257d6dc 6899 return -EIO;
55d2375e 6900 if (nested)
a4443267 6901 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
55d2375e
SC		 6902 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6903 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6904 smp_processor_id());
f257d6dc 6905 return -EIO;
bd18bffc 6906 }
f257d6dc 6907 return 0;
bd18bffc
SC		 6908}
6909
55d2375e 6910static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
bd18bffc 6911{
55d2375e
SC		 6912 u8 cache;
6913 u64 ipat = 0;
bd18bffc 6914
55d2375e
SC		 6915 /* For VT-d and EPT combination
6916 * 1. MMIO: always map as UC
6917 * 2. EPT with VT-d:
6918 * a. VT-d without snooping control feature: can't guarantee the
6919 * result, try to trust guest.
6920 * b. VT-d with snooping control feature: snooping control feature of
6921 * VT-d engine can guarantee the cache correctness. Just set it
6922 * to WB to keep consistent with host. So the same as item 3.
6923 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6924 * consistent with host MTRR
bd18bffc 6925 */
55d2375e
SC		 6926 if (is_mmio) {
6927 cache = MTRR_TYPE_UNCACHABLE;
6928 goto exit;
6929 }
bd18bffc 6930
55d2375e
SC		 6931 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6932 ipat = VMX_EPT_IPAT_BIT;
6933 cache = MTRR_TYPE_WRBACK;
6934 goto exit;
6935 }
bd18bffc 6936
55d2375e
SC		 6937 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6938 ipat = VMX_EPT_IPAT_BIT;
6939 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6940 cache = MTRR_TYPE_WRBACK;
6941 else
6942 cache = MTRR_TYPE_UNCACHABLE;
6943 goto exit;
6944 }
bd18bffc 6945
55d2375e 6946 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
bd18bffc 6947
55d2375e
SC		 6948exit:
6949 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6950}
bd18bffc 6951
55d2375e
SC		 6952static int vmx_get_lpage_level(void)
6953{
6954 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6955 return PT_DIRECTORY_LEVEL;
6956 else
6957 /* For shadow and EPT supported 1GB page */
6958 return PT_PDPE_LEVEL;
6959}
bd18bffc 6960
fe7f895d 6961static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
55d2375e 6962{
bd18bffc 6963 /*
55d2375e
SC		 6964 * These bits in the secondary execution controls field
6965 * are dynamic, the others are mostly based on the hypervisor
6966 * architecture and the guest's CPUID. Do not touch the
6967 * dynamic bits.
bd18bffc 6968 */
55d2375e
SC		 6969 u32 mask =
6970 SECONDARY_EXEC_SHADOW_VMCS |
6971 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6972 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6973 SECONDARY_EXEC_DESC;
bd18bffc 6974
fe7f895d
SC		 6975 u32 new_ctl = vmx->secondary_exec_control;
6976 u32 cur_ctl = secondary_exec_controls_get(vmx);
bd18bffc 6977
fe7f895d 6978 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
bd18bffc
SC		 6979}
6980
4704d0be 6981/*
55d2375e
SC		 6982 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6983 * (indicating "allowed-1") if they are supported in the guest's CPUID.
4704d0be 6984 */
55d2375e 6985static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
4704d0be
NHE		 6986{
6987 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e 6988 struct kvm_cpuid_entry2 *entry;
4704d0be 6989
55d2375e
SC		 6990 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6991 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
e79f245d 6992
55d2375e
SC		 6993#define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
6994 if (entry && (entry->_reg & (_cpuid_mask))) \
6995 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
6996} while (0)
ff651cb6 6997
55d2375e 6998 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
87382003
SC		 6999 cr4_fixed1_update(X86_CR4_VME, edx, feature_bit(VME));
7000 cr4_fixed1_update(X86_CR4_PVI, edx, feature_bit(VME));
7001 cr4_fixed1_update(X86_CR4_TSD, edx, feature_bit(TSC));
7002 cr4_fixed1_update(X86_CR4_DE, edx, feature_bit(DE));
7003 cr4_fixed1_update(X86_CR4_PSE, edx, feature_bit(PSE));
7004 cr4_fixed1_update(X86_CR4_PAE, edx, feature_bit(PAE));
7005 cr4_fixed1_update(X86_CR4_MCE, edx, feature_bit(MCE));
7006 cr4_fixed1_update(X86_CR4_PGE, edx, feature_bit(PGE));
7007 cr4_fixed1_update(X86_CR4_OSFXSR, edx, feature_bit(FXSR));
7008 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
7009 cr4_fixed1_update(X86_CR4_VMXE, ecx, feature_bit(VMX));
7010 cr4_fixed1_update(X86_CR4_SMXE, ecx, feature_bit(SMX));
7011 cr4_fixed1_update(X86_CR4_PCIDE, ecx, feature_bit(PCID));
7012 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, feature_bit(XSAVE));
61ada748 7013
55d2375e 7014 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
87382003
SC		 7015 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, feature_bit(FSGSBASE));
7016 cr4_fixed1_update(X86_CR4_SMEP, ebx, feature_bit(SMEP));
7017 cr4_fixed1_update(X86_CR4_SMAP, ebx, feature_bit(SMAP));
7018 cr4_fixed1_update(X86_CR4_PKE, ecx, feature_bit(PKU));
7019 cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP));
7020 cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57));
cf3215d9 7021
55d2375e
SC		 7022#undef cr4_fixed1_update
7023}
36c3cc42 7024
55d2375e
SC		 7025static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7026{
7027 struct vcpu_vmx *vmx = to_vmx(vcpu);
f459a707 7028
55d2375e
SC		 7029 if (kvm_mpx_supported()) {
7030 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
4704d0be 7031
55d2375e
SC		 7032 if (mpx_enabled) {
7033 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7034 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7035 } else {
7036 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7037 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7038 }
dccbfcf5 7039 }
55d2375e 7040}
4704d0be 7041
6c0f0bba
LK		 7042static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7043{
7044 struct vcpu_vmx *vmx = to_vmx(vcpu);
7045 struct kvm_cpuid_entry2 *best = NULL;
7046 int i;
7047
7048 for (i = 0; i < PT_CPUID_LEAVES; i++) {
7049 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7050 if (!best)
7051 return;
7052 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7053 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7054 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7055 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7056 }
7057
7058 /* Get the number of configurable Address Ranges for filtering */
7059 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7060 PT_CAP_num_address_ranges);
7061
7062 /* Initialize and clear the no dependency bits */
7063 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7064 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7065
7066 /*
7067 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7068 * will inject an #GP
7069 */
7070 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7071 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7072
7073 /*
7074 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7075 * PSBFreq can be set
7076 */
7077 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7078 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7079 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7080
7081 /*
7082 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7083 * MTCFreq can be set
7084 */
7085 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7086 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7087 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7088
7089 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7090 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7091 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7092 RTIT_CTL_PTW_EN);
7093
7094 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7095 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7096 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7097
7098 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7099 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7100 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7101
7102 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7103 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7104 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7105
7106 /* unmask address range configure area */
7107 for (i = 0; i < vmx->pt_desc.addr_range; i++)
d14eff1b 7108 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
6c0f0bba
LK		 7109}
7110
55d2375e
SC		 7111static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7112{
7113 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 7114
7204160e
AL		 7115 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7116 vcpu->arch.xsaves_enabled = false;
7117
55d2375e
SC		 7118 if (cpu_has_secondary_exec_ctrls()) {
7119 vmx_compute_secondary_exec_control(vmx);
fe7f895d 7120 vmcs_set_secondary_exec_control(vmx);
705699a1 7121 }
4704d0be 7122
55d2375e
SC		 7123 if (nested_vmx_allowed(vcpu))
7124 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
32ad73db
SC		 7125 FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7126 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
55d2375e
SC		 7127 else
7128 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
32ad73db
SC		 7129 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7130 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
4f350c6d 7131
55d2375e
SC		 7132 if (nested_vmx_allowed(vcpu)) {
7133 nested_vmx_cr_fixed1_bits_update(vcpu);
7134 nested_vmx_entry_exit_ctls_update(vcpu);
4f350c6d 7135 }
6c0f0bba
LK		 7136
7137 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7138 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7139 update_intel_pt_cfg(vcpu);
b07a5c53
PB		 7140
7141 if (boot_cpu_has(X86_FEATURE_RTM)) {
7142 struct shared_msr_entry *msr;
7143 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL);
7144 if (msr) {
7145 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7146 vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7147 }
7148 }
55d2375e 7149}
09abb5e3 7150
55d2375e
SC		 7151static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7152{
7153 if (func == 1 && nested)
87382003 7154 entry->ecx |= feature_bit(VMX);
4704d0be
NHE		 7155}
7156
55d2375e 7157static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
42124925 7158{
55d2375e 7159 to_vmx(vcpu)->req_immediate_exit = true;
7c177938
NHE		 7160}
7161
35a57134
OU		 7162static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7163 struct x86_instruction_info *info)
7164{
7165 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7166 unsigned short port;
7167 bool intercept;
7168 int size;
7169
7170 if (info->intercept == x86_intercept_in ||
7171 info->intercept == x86_intercept_ins) {
7172 port = info->src_val;
7173 size = info->dst_bytes;
7174 } else {
7175 port = info->dst_val;
7176 size = info->src_bytes;
7177 }
7178
7179 /*
7180 * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7181 * VM-exits depend on the 'unconditional IO exiting' VM-execution
7182 * control.
7183 *
7184 * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7185 */
7186 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7187 intercept = nested_cpu_has(vmcs12,
7188 CPU_BASED_UNCOND_IO_EXITING);
7189 else
7190 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7191
86f7e90c 7192 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */
35a57134
OU		 7193 return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7194}
7195
8a76d7f2
JR		 7196static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7197 struct x86_instruction_info *info,
7198 enum x86_intercept_stage stage)
7199{
fb6d4d34
PB		 7200 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7201 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7202
35a57134 7203 switch (info->intercept) {
fb6d4d34
PB		 7204 /*
7205 * RDPID causes #UD if disabled through secondary execution controls.
7206 * Because it is marked as EmulateOnUD, we need to intercept it here.
7207 */
35a57134
OU		 7208 case x86_intercept_rdtscp:
7209 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7210 ctxt->exception.vector = UD_VECTOR;
7211 ctxt->exception.error_code_valid = false;
7212 return X86EMUL_PROPAGATE_FAULT;
7213 }
7214 break;
7215
7216 case x86_intercept_in:
7217 case x86_intercept_ins:
7218 case x86_intercept_out:
7219 case x86_intercept_outs:
7220 return vmx_check_intercept_io(vcpu, info);
fb6d4d34 7221
86f7e90c
OU		 7222 case x86_intercept_lgdt:
7223 case x86_intercept_lidt:
7224 case x86_intercept_lldt:
7225 case x86_intercept_ltr:
7226 case x86_intercept_sgdt:
7227 case x86_intercept_sidt:
7228 case x86_intercept_sldt:
7229 case x86_intercept_str:
7230 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
7231 return X86EMUL_CONTINUE;
7232
7233 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */
7234 break;
7235
fb6d4d34 7236 /* TODO: check more intercepts... */
35a57134
OU		 7237 default:
7238 break;
7239 }
7240
07721fee 7241 return X86EMUL_UNHANDLEABLE;
8a76d7f2
JR		 7242}
7243
64672c95
YJ		 7244#ifdef CONFIG_X86_64
7245/* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7246static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7247 u64 divisor, u64 *result)
7248{
7249 u64 low = a << shift, high = a >> (64 - shift);
7250
7251 /* To avoid the overflow on divq */
7252 if (high >= divisor)
7253 return 1;
7254
7255 /* Low hold the result, high hold rem which is discarded */
7256 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7257 "rm" (divisor), "0" (low), "1" (high));
7258 *result = low;
7259
7260 return 0;
7261}
7262
f9927982
SC		 7263static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7264 bool *expired)
64672c95 7265{
386c6ddb 7266 struct vcpu_vmx *vmx;
c5ce8235 7267 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
39497d76 7268 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
386c6ddb 7269
0c5f81da
WL		 7270 if (kvm_mwait_in_guest(vcpu->kvm) ||
7271 kvm_can_post_timer_interrupt(vcpu))
386c6ddb
KA		 7272 return -EOPNOTSUPP;
7273
7274 vmx = to_vmx(vcpu);
7275 tscl = rdtsc();
7276 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7277 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
39497d76
SC		 7278 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7279 ktimer->timer_advance_ns);
c5ce8235
WL		 7280
7281 if (delta_tsc > lapic_timer_advance_cycles)
7282 delta_tsc -= lapic_timer_advance_cycles;
7283 else
7284 delta_tsc = 0;
64672c95
YJ		 7285
7286 /* Convert to host delta tsc if tsc scaling is enabled */
7287 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
0967fa1c 7288 delta_tsc && u64_shl_div_u64(delta_tsc,
64672c95 7289 kvm_tsc_scaling_ratio_frac_bits,
0967fa1c 7290 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
64672c95
YJ		 7291 return -ERANGE;
7292
7293 /*
7294 * If the delta tsc can't fit in the 32 bit after the multi shift,
7295 * we can't use the preemption timer.
7296 * It's possible that it fits on later vmentries, but checking
7297 * on every vmentry is costly so we just use an hrtimer.
7298 */
7299 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7300 return -ERANGE;
7301
7302 vmx->hv_deadline_tsc = tscl + delta_tsc;
f9927982
SC		 7303 *expired = !delta_tsc;
7304 return 0;
64672c95
YJ		 7305}
7306
7307static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7308{
f459a707 7309 to_vmx(vcpu)->hv_deadline_tsc = -1;
64672c95
YJ		 7310}
7311#endif
7312
48d89b92 7313static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 7314{
b31c114b 7315 if (!kvm_pause_in_guest(vcpu->kvm))
b4a2d31d 7316 shrink_ple_window(vcpu);
ae97a3b8
RK		 7317}
7318
843e4330
KH		 7319static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7320 struct kvm_memory_slot *slot)
7321{
7322 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7323 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7324}
7325
7326static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7327 struct kvm_memory_slot *slot)
7328{
7329 kvm_mmu_slot_set_dirty(kvm, slot);
7330}
7331
7332static void vmx_flush_log_dirty(struct kvm *kvm)
7333{
7334 kvm_flush_pml_buffers(kvm);
7335}
7336
c5f983f6
BD		 7337static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7338{
7339 struct vmcs12 *vmcs12;
7340 struct vcpu_vmx *vmx = to_vmx(vcpu);
3d5f6beb 7341 gpa_t gpa, dst;
c5f983f6
BD		 7342
7343 if (is_guest_mode(vcpu)) {
7344 WARN_ON_ONCE(vmx->nested.pml_full);
7345
7346 /*
7347 * Check if PML is enabled for the nested guest.
7348 * Whether eptp bit 6 is set is already checked
7349 * as part of A/D emulation.
7350 */
7351 vmcs12 = get_vmcs12(vcpu);
7352 if (!nested_cpu_has_pml(vmcs12))
7353 return 0;
7354
4769886b 7355 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
c5f983f6
BD		 7356 vmx->nested.pml_full = true;
7357 return 1;
7358 }
7359
7360 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
3d5f6beb 7361 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
c5f983f6 7362
3d5f6beb
KA		 7363 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7364 offset_in_page(dst), sizeof(gpa)))
c5f983f6
BD		 7365 return 0;
7366
3d5f6beb 7367 vmcs12->guest_pml_index--;
c5f983f6
BD		 7368 }
7369
7370 return 0;
7371}
7372
843e4330
KH		 7373static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7374 struct kvm_memory_slot *memslot,
7375 gfn_t offset, unsigned long mask)
7376{
7377 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7378}
7379
cd39e117
PB		 7380static void __pi_post_block(struct kvm_vcpu *vcpu)
7381{
7382 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7383 struct pi_desc old, new;
7384 unsigned int dest;
cd39e117
PB		 7385
7386 do {
7387 old.control = new.control = pi_desc->control;
8b306e2f
PB		 7388 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7389 "Wakeup handler not enabled while the VCPU is blocked\n");
cd39e117
PB		 7390
7391 dest = cpu_physical_id(vcpu->cpu);
7392
7393 if (x2apic_enabled())
7394 new.ndst = dest;
7395 else
7396 new.ndst = (dest << 8) & 0xFF00;
7397
cd39e117
PB		 7398 /* set 'NV' to 'notification vector' */
7399 new.nv = POSTED_INTR_VECTOR;
c0a1666b
PB		 7400 } while (cmpxchg64(&pi_desc->control, old.control,
7401 new.control) != old.control);
cd39e117 7402
8b306e2f
PB		 7403 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7404 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
cd39e117 7405 list_del(&vcpu->blocked_vcpu_list);
8b306e2f 7406 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
cd39e117
PB		 7407 vcpu->pre_pcpu = -1;
7408 }
7409}
7410
bf9f6ac8
FW		 7411/*
7412 * This routine does the following things for vCPU which is going
7413 * to be blocked if VT-d PI is enabled.
7414 * - Store the vCPU to the wakeup list, so when interrupts happen
7415 * we can find the right vCPU to wake up.
7416 * - Change the Posted-interrupt descriptor as below:
7417 * 'NDST' <-- vcpu->pre_pcpu
7418 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7419 * - If 'ON' is set during this process, which means at least one
7420 * interrupt is posted for this vCPU, we cannot block it, in
7421 * this case, return 1, otherwise, return 0.
7422 *
7423 */
bc22512b 7424static int pi_pre_block(struct kvm_vcpu *vcpu)
bf9f6ac8 7425{
bf9f6ac8
FW		 7426 unsigned int dest;
7427 struct pi_desc old, new;
7428 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7429
7430 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 7431 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7432 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW		 7433 return 0;
7434
8b306e2f
PB		 7435 WARN_ON(irqs_disabled());
7436 local_irq_disable();
7437 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7438 vcpu->pre_pcpu = vcpu->cpu;
7439 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7440 list_add_tail(&vcpu->blocked_vcpu_list,
7441 &per_cpu(blocked_vcpu_on_cpu,
7442 vcpu->pre_pcpu));
7443 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7444 }
bf9f6ac8
FW		 7445
7446 do {
7447 old.control = new.control = pi_desc->control;
7448
bf9f6ac8
FW		 7449 WARN((pi_desc->sn == 1),
7450 "Warning: SN field of posted-interrupts "
7451 "is set before blocking\n");
7452
7453 /*
7454 * Since vCPU can be preempted during this process,
7455 * vcpu->cpu could be different with pre_pcpu, we
7456 * need to set pre_pcpu as the destination of wakeup
7457 * notification event, then we can find the right vCPU
7458 * to wakeup in wakeup handler if interrupts happen
7459 * when the vCPU is in blocked state.
7460 */
7461 dest = cpu_physical_id(vcpu->pre_pcpu);
7462
7463 if (x2apic_enabled())
7464 new.ndst = dest;
7465 else
7466 new.ndst = (dest << 8) & 0xFF00;
7467
7468 /* set 'NV' to 'wakeup vector' */
7469 new.nv = POSTED_INTR_WAKEUP_VECTOR;
c0a1666b
PB		 7470 } while (cmpxchg64(&pi_desc->control, old.control,
7471 new.control) != old.control);
bf9f6ac8 7472
8b306e2f
PB		 7473 /* We should not block the vCPU if an interrupt is posted for it. */
7474 if (pi_test_on(pi_desc) == 1)
7475 __pi_post_block(vcpu);
7476
7477 local_irq_enable();
7478 return (vcpu->pre_pcpu == -1);
bf9f6ac8
FW		 7479}
7480
bc22512b
YJ		 7481static int vmx_pre_block(struct kvm_vcpu *vcpu)
7482{
7483 if (pi_pre_block(vcpu))
7484 return 1;
7485
64672c95
YJ		 7486 if (kvm_lapic_hv_timer_in_use(vcpu))
7487 kvm_lapic_switch_to_sw_timer(vcpu);
7488
bc22512b
YJ		 7489 return 0;
7490}
7491
7492static void pi_post_block(struct kvm_vcpu *vcpu)
bf9f6ac8 7493{
8b306e2f 7494 if (vcpu->pre_pcpu == -1)
bf9f6ac8
FW		 7495 return;
7496
8b306e2f
PB		 7497 WARN_ON(irqs_disabled());
7498 local_irq_disable();
cd39e117 7499 __pi_post_block(vcpu);
8b306e2f 7500 local_irq_enable();
bf9f6ac8
FW		 7501}
7502
bc22512b
YJ		 7503static void vmx_post_block(struct kvm_vcpu *vcpu)
7504{
64672c95
YJ		 7505 if (kvm_x86_ops->set_hv_timer)
7506 kvm_lapic_switch_to_hv_timer(vcpu);
7507
bc22512b
YJ		 7508 pi_post_block(vcpu);
7509}
7510
efc64404
FW		 7511/*
7512 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7513 *
7514 * @kvm: kvm
7515 * @host_irq: host irq of the interrupt
7516 * @guest_irq: gsi of the interrupt
7517 * @set: set or unset PI
7518 * returns 0 on success, < 0 on failure
7519 */
7520static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7521 uint32_t guest_irq, bool set)
7522{
7523 struct kvm_kernel_irq_routing_entry *e;
7524 struct kvm_irq_routing_table *irq_rt;
7525 struct kvm_lapic_irq irq;
7526 struct kvm_vcpu *vcpu;
7527 struct vcpu_data vcpu_info;
3a8b0677 7528 int idx, ret = 0;
efc64404
FW		 7529
7530 if (!kvm_arch_has_assigned_device(kvm) ||
a0052191
YZ		 7531 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7532 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
efc64404
FW		 7533 return 0;
7534
7535 idx = srcu_read_lock(&kvm->irq_srcu);
7536 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
3a8b0677
JS		 7537 if (guest_irq >= irq_rt->nr_rt_entries ||
7538 hlist_empty(&irq_rt->map[guest_irq])) {
7539 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7540 guest_irq, irq_rt->nr_rt_entries);
7541 goto out;
7542 }
efc64404
FW		 7543
7544 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7545 if (e->type != KVM_IRQ_ROUTING_MSI)
7546 continue;
7547 /*
7548 * VT-d PI cannot support posting multicast/broadcast
7549 * interrupts to a vCPU, we still use interrupt remapping
7550 * for these kind of interrupts.
7551 *
7552 * For lowest-priority interrupts, we only support
7553 * those with single CPU as the destination, e.g. user
7554 * configures the interrupts via /proc/irq or uses
7555 * irqbalance to make the interrupts single-CPU.
7556 *
7557 * We will support full lowest-priority interrupt later.
fdcf7562
AG		 7558 *
7559 * In addition, we can only inject generic interrupts using
7560 * the PI mechanism, refuse to route others through it.
efc64404
FW		 7561 */
7562
37131313 7563 kvm_set_msi_irq(kvm, e, &irq);
fdcf7562
AG		 7564 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7565 !kvm_irq_is_postable(&irq)) {
23a1c257
FW		 7566 /*
7567 * Make sure the IRTE is in remapped mode if
7568 * we don't handle it in posted mode.
7569 */
7570 ret = irq_set_vcpu_affinity(host_irq, NULL);
7571 if (ret < 0) {
7572 printk(KERN_INFO
7573 "failed to back to remapped mode, irq: %u\n",
7574 host_irq);
7575 goto out;
7576 }
7577
efc64404 7578 continue;
23a1c257 7579 }
efc64404
FW		 7580
7581 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7582 vcpu_info.vector = irq.vector;
7583
2698d82e 7584 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
efc64404
FW		 7585 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7586
7587 if (set)
7588 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
dc91f2eb 7589 else
efc64404 7590 ret = irq_set_vcpu_affinity(host_irq, NULL);
efc64404
FW		 7591
7592 if (ret < 0) {
7593 printk(KERN_INFO "%s: failed to update PI IRTE\n",
7594 __func__);
7595 goto out;
7596 }
7597 }
7598
7599 ret = 0;
7600out:
7601 srcu_read_unlock(&kvm->irq_srcu, idx);
7602 return ret;
7603}
7604
c45dcc71
AR		 7605static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7606{
7607 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7608 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
32ad73db 7609 FEAT_CTL_LMCE_ENABLED;
c45dcc71
AR		 7610 else
7611 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
32ad73db 7612 ~FEAT_CTL_LMCE_ENABLED;
c45dcc71
AR		 7613}
7614
72d7b374
LP		 7615static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7616{
72e9cbdb
LP		 7617 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7618 if (to_vmx(vcpu)->nested.nested_run_pending)
7619 return 0;
72d7b374
LP		 7620 return 1;
7621}
7622
0234bf88
LP		 7623static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7624{
72e9cbdb
LP		 7625 struct vcpu_vmx *vmx = to_vmx(vcpu);
7626
7627 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7628 if (vmx->nested.smm.guest_mode)
7629 nested_vmx_vmexit(vcpu, -1, 0, 0);
7630
7631 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7632 vmx->nested.vmxon = false;
caa057a2 7633 vmx_clear_hlt(vcpu);
0234bf88
LP		 7634 return 0;
7635}
7636
ed19321f 7637static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
0234bf88 7638{
72e9cbdb
LP		 7639 struct vcpu_vmx *vmx = to_vmx(vcpu);
7640 int ret;
7641
7642 if (vmx->nested.smm.vmxon) {
7643 vmx->nested.vmxon = true;
7644 vmx->nested.smm.vmxon = false;
7645 }
7646
7647 if (vmx->nested.smm.guest_mode) {
a633e41e 7648 ret = nested_vmx_enter_non_root_mode(vcpu, false);
72e9cbdb
LP		 7649 if (ret)
7650 return ret;
7651
7652 vmx->nested.smm.guest_mode = false;
7653 }
0234bf88
LP		 7654 return 0;
7655}
7656
cc3d967f
LP		 7657static int enable_smi_window(struct kvm_vcpu *vcpu)
7658{
7659 return 0;
7660}
7661
05d5a486
SB		 7662static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7663{
9481b7f1 7664 return false;
05d5a486
SB		 7665}
7666
4b9852f4
LA		 7667static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7668{
7669 return to_vmx(vcpu)->nested.vmxon;
7670}
7671
a3203381
SC		 7672static __init int hardware_setup(void)
7673{
7674 unsigned long host_bndcfgs;
2342080c 7675 struct desc_ptr dt;
a3203381
SC		 7676 int r, i;
7677
7678 rdmsrl_safe(MSR_EFER, &host_efer);
7679
2342080c
SC		 7680 store_idt(&dt);
7681 host_idt_base = dt.address;
7682
a3203381
SC		 7683 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7684 kvm_define_shared_msr(i, vmx_msr_index[i]);
7685
7686 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7687 return -EIO;
7688
7689 if (boot_cpu_has(X86_FEATURE_NX))
7690 kvm_enable_efer_bits(EFER_NX);
7691
7692 if (boot_cpu_has(X86_FEATURE_MPX)) {
7693 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7694 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7695 }
7696
a3203381
SC		 7697 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7698 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7699 enable_vpid = 0;
7700
7701 if (!cpu_has_vmx_ept() ||
7702 !cpu_has_vmx_ept_4levels() ||
7703 !cpu_has_vmx_ept_mt_wb() ||
7704 !cpu_has_vmx_invept_global())
7705 enable_ept = 0;
7706
7707 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7708 enable_ept_ad_bits = 0;
7709
7710 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7711 enable_unrestricted_guest = 0;
7712
7713 if (!cpu_has_vmx_flexpriority())
7714 flexpriority_enabled = 0;
7715
7716 if (!cpu_has_virtual_nmis())
7717 enable_vnmi = 0;
7718
7719 /*
7720 * set_apic_access_page_addr() is used to reload apic access
7721 * page upon invalidation. No need to do anything if not
7722 * using the APIC_ACCESS_ADDR VMCS field.
7723 */
7724 if (!flexpriority_enabled)
7725 kvm_x86_ops->set_apic_access_page_addr = NULL;
7726
7727 if (!cpu_has_vmx_tpr_shadow())
7728 kvm_x86_ops->update_cr8_intercept = NULL;
7729
7730 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7731 kvm_disable_largepages();
7732
7733#if IS_ENABLED(CONFIG_HYPERV)
7734 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
1f3a3e46
LT		 7735 && enable_ept) {
7736 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7737 kvm_x86_ops->tlb_remote_flush_with_range =
7738 hv_remote_flush_tlb_with_range;
7739 }
a3203381
SC		 7740#endif
7741
7742 if (!cpu_has_vmx_ple()) {
7743 ple_gap = 0;
7744 ple_window = 0;
7745 ple_window_grow = 0;
7746 ple_window_max = 0;
7747 ple_window_shrink = 0;
7748 }
7749
7750 if (!cpu_has_vmx_apicv()) {
7751 enable_apicv = 0;
7752 kvm_x86_ops->sync_pir_to_irr = NULL;
7753 }
7754
7755 if (cpu_has_vmx_tsc_scaling()) {
7756 kvm_has_tsc_control = true;
7757 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7758 kvm_tsc_scaling_ratio_frac_bits = 48;
7759 }
7760
7761 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7762
7763 if (enable_ept)
7764 vmx_enable_tdp();
7765 else
7766 kvm_disable_tdp();
7767
a3203381
SC		 7768 /*
7769 * Only enable PML when hardware supports PML feature, and both EPT
7770 * and EPT A/D bit features are enabled -- PML depends on them to work.
7771 */
7772 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7773 enable_pml = 0;
7774
7775 if (!enable_pml) {
7776 kvm_x86_ops->slot_enable_log_dirty = NULL;
7777 kvm_x86_ops->slot_disable_log_dirty = NULL;
7778 kvm_x86_ops->flush_log_dirty = NULL;
7779 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7780 }
7781
7782 if (!cpu_has_vmx_preemption_timer())
804939ea 7783 enable_preemption_timer = false;
a3203381 7784
804939ea
SC		 7785 if (enable_preemption_timer) {
7786 u64 use_timer_freq = 5000ULL * 1000 * 1000;
a3203381
SC		 7787 u64 vmx_msr;
7788
7789 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7790 cpu_preemption_timer_multi =
7791 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
804939ea
SC		 7792
7793 if (tsc_khz)
7794 use_timer_freq = (u64)tsc_khz * 1000;
7795 use_timer_freq >>= cpu_preemption_timer_multi;
7796
7797 /*
7798 * KVM "disables" the preemption timer by setting it to its max
7799 * value. Don't use the timer if it might cause spurious exits
7800 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7801 */
7802 if (use_timer_freq > 0xffffffffu / 10)
7803 enable_preemption_timer = false;
7804 }
7805
7806 if (!enable_preemption_timer) {
a3203381
SC		 7807 kvm_x86_ops->set_hv_timer = NULL;
7808 kvm_x86_ops->cancel_hv_timer = NULL;
804939ea 7809 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
a3203381
SC		 7810 }
7811
a3203381 7812 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
a3203381
SC		 7813
7814 kvm_mce_cap_supported |= MCG_LMCE_P;
7815
f99e3daf
CP		 7816 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7817 return -EINVAL;
7818 if (!enable_ept || !cpu_has_vmx_intel_pt())
7819 pt_mode = PT_MODE_SYSTEM;
7820
a3203381 7821 if (nested) {
3e8eaccc 7822 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
a4443267 7823 vmx_capability.ept);
3e8eaccc 7824
e4027cfa 7825 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
a3203381
SC		 7826 if (r)
7827 return r;
7828 }
7829
7830 r = alloc_kvm_area();
7831 if (r)
7832 nested_vmx_hardware_unsetup();
7833 return r;
7834}
7835
7836static __exit void hardware_unsetup(void)
7837{
7838 if (nested)
7839 nested_vmx_hardware_unsetup();
7840
7841 free_kvm_area();
7842}
7843
ef8efd7a
SS		 7844static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7845{
f4fdc0a2
SS		 7846 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7847 BIT(APICV_INHIBIT_REASON_HYPERV);
ef8efd7a
SS		 7848
7849 return supported & BIT(bit);
7850}
7851
404f6aac 7852static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
6aa8b732
AK		 7853 .cpu_has_kvm_support = cpu_has_kvm_support,
7854 .disabled_by_bios = vmx_disabled_by_bios,
7855 .hardware_setup = hardware_setup,
7856 .hardware_unsetup = hardware_unsetup,
002c7f7c 7857 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7858 .hardware_enable = hardware_enable,
7859 .hardware_disable = hardware_disable,
04547156 7860 .cpu_has_accelerated_tpr = report_flexpriority,
bc226f07 7861 .has_emulated_msr = vmx_has_emulated_msr,
6aa8b732 7862
b31c114b 7863 .vm_init = vmx_vm_init,
434a1e94
SC		 7864 .vm_alloc = vmx_vm_alloc,
7865 .vm_free = vmx_vm_free,
b31c114b 7866
6aa8b732
AK		 7867 .vcpu_create = vmx_create_vcpu,
7868 .vcpu_free = vmx_free_vcpu,
04d2cc77 7869 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7870
6d6095bd 7871 .prepare_guest_switch = vmx_prepare_switch_to_guest,
6aa8b732
AK		 7872 .vcpu_load = vmx_vcpu_load,
7873 .vcpu_put = vmx_vcpu_put,
7874
a96036b8 7875 .update_bp_intercept = update_exception_bitmap,
801e459a 7876 .get_msr_feature = vmx_get_msr_feature,
6aa8b732
AK		 7877 .get_msr = vmx_get_msr,
7878 .set_msr = vmx_set_msr,
7879 .get_segment_base = vmx_get_segment_base,
7880 .get_segment = vmx_get_segment,
7881 .set_segment = vmx_set_segment,
2e4d2653 7882 .get_cpl = vmx_get_cpl,
6aa8b732 7883 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7884 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 7885 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7886 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7887 .set_cr3 = vmx_set_cr3,
7888 .set_cr4 = vmx_set_cr4,
6aa8b732 7889 .set_efer = vmx_set_efer,
6aa8b732
AK		 7890 .get_idt = vmx_get_idt,
7891 .set_idt = vmx_set_idt,
7892 .get_gdt = vmx_get_gdt,
7893 .set_gdt = vmx_set_gdt,
73aaf249
JK		 7894 .get_dr6 = vmx_get_dr6,
7895 .set_dr6 = vmx_set_dr6,
020df079 7896 .set_dr7 = vmx_set_dr7,
81908bf4 7897 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 7898 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7899 .get_rflags = vmx_get_rflags,
7900 .set_rflags = vmx_set_rflags,
be94f6b7 7901
6aa8b732 7902 .tlb_flush = vmx_flush_tlb,
faff8758 7903 .tlb_flush_gva = vmx_flush_tlb_gva,
6aa8b732 7904
6aa8b732 7905 .run = vmx_vcpu_run,
6062d012 7906 .handle_exit = vmx_handle_exit,
5ef8acbd
OU		 7907 .skip_emulated_instruction = vmx_skip_emulated_instruction,
7908 .update_emulated_instruction = vmx_update_emulated_instruction,
2809f5d2
GC		 7909 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7910 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7911 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7912 .set_irq = vmx_inject_irq,
95ba8273 7913 .set_nmi = vmx_inject_nmi,
298101da 7914 .queue_exception = vmx_queue_exception,
b463a6f7 7915 .cancel_injection = vmx_cancel_injection,
78646121 7916 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7917 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7918 .get_nmi_mask = vmx_get_nmi_mask,
7919 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7920 .enable_nmi_window = enable_nmi_window,
7921 .enable_irq_window = enable_irq_window,
7922 .update_cr8_intercept = update_cr8_intercept,
8d860bbe 7923 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
38b99173 7924 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d62caabb 7925 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
c7c9c56c 7926 .load_eoi_exitmap = vmx_load_eoi_exitmap,
967235d3 7927 .apicv_post_state_restore = vmx_apicv_post_state_restore,
ef8efd7a 7928 .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
c7c9c56c
YZ		 7929 .hwapic_irr_update = vmx_hwapic_irr_update,
7930 .hwapic_isr_update = vmx_hwapic_isr_update,
e6c67d8c 7931 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
a20ed54d
YZ		 7932 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7933 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
17e433b5 7934 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
95ba8273 7935
cbc94022 7936 .set_tss_addr = vmx_set_tss_addr,
2ac52ab8 7937 .set_identity_map_addr = vmx_set_identity_map_addr,
67253af5 7938 .get_tdp_level = get_ept_level,
4b12f0de 7939 .get_mt_mask = vmx_get_mt_mask,
229456fc 7940
586f9607 7941 .get_exit_info = vmx_get_exit_info,
586f9607 7942
17cc3935 7943 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7944
7945 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7946
7947 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7948 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7949
7950 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7951
7952 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7953
e79f245d 7954 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
326e7425 7955 .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
1c97f0a0
JR		 7956
7957 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7958
7959 .check_intercept = vmx_check_intercept,
95b5a48c 7960 .handle_exit_irqoff = vmx_handle_exit_irqoff,
da8999d3 7961 .mpx_supported = vmx_mpx_supported,
55412b2e 7962 .xsaves_supported = vmx_xsaves_supported,
66336cab 7963 .umip_emulated = vmx_umip_emulated,
86f5201d 7964 .pt_supported = vmx_pt_supported,
a47970ed 7965 .pku_supported = vmx_pku_supported,
b6b8a145 7966
d264ee0c 7967 .request_immediate_exit = vmx_request_immediate_exit,
ae97a3b8
RK		 7968
7969 .sched_in = vmx_sched_in,
843e4330
KH		 7970
7971 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7972 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7973 .flush_log_dirty = vmx_flush_log_dirty,
7974 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
c5f983f6 7975 .write_log_dirty = vmx_write_pml_buffer,
25462f7f 7976
bf9f6ac8
FW		 7977 .pre_block = vmx_pre_block,
7978 .post_block = vmx_post_block,
7979
25462f7f 7980 .pmu_ops = &intel_pmu_ops,
efc64404
FW		 7981
7982 .update_pi_irte = vmx_update_pi_irte,
64672c95
YJ		 7983
7984#ifdef CONFIG_X86_64
7985 .set_hv_timer = vmx_set_hv_timer,
7986 .cancel_hv_timer = vmx_cancel_hv_timer,
7987#endif
c45dcc71
AR		 7988
7989 .setup_mce = vmx_setup_mce,
0234bf88 7990
72d7b374 7991 .smi_allowed = vmx_smi_allowed,
0234bf88
LP		 7992 .pre_enter_smm = vmx_pre_enter_smm,
7993 .pre_leave_smm = vmx_pre_leave_smm,
cc3d967f 7994 .enable_smi_window = enable_smi_window,
57b119da 7995
e4027cfa
SC		 7996 .check_nested_events = NULL,
7997 .get_nested_state = NULL,
7998 .set_nested_state = NULL,
7999 .get_vmcs12_pages = NULL,
8000 .nested_enable_evmcs = NULL,
ea152987 8001 .nested_get_evmcs_version = NULL,
05d5a486 8002 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
4b9852f4 8003 .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
6aa8b732
AK		 8004};
8005
72c6d2db 8006static void vmx_cleanup_l1d_flush(void)
a47dd5f0
PB		 8007{
8008 if (vmx_l1d_flush_pages) {
8009 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
8010 vmx_l1d_flush_pages = NULL;
8011 }
72c6d2db
TG		 8012 /* Restore state so sysfs ignores VMX */
8013 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
a399477e
KRW		 8014}
8015
a7b9020b
TG		 8016static void vmx_exit(void)
8017{
8018#ifdef CONFIG_KEXEC_CORE
8019 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8020 synchronize_rcu();
8021#endif
8022
8023 kvm_exit();
8024
8025#if IS_ENABLED(CONFIG_HYPERV)
8026 if (static_branch_unlikely(&enable_evmcs)) {
8027 int cpu;
8028 struct hv_vp_assist_page *vp_ap;
8029 /*
8030 * Reset everything to support using non-enlightened VMCS
8031 * access later (e.g. when we reload the module with
8032 * enlightened_vmcs=0)
8033 */
8034 for_each_online_cpu(cpu) {
8035 vp_ap = hv_get_vp_assist_page(cpu);
8036
8037 if (!vp_ap)
8038 continue;
8039
6f6a657c 8040 vp_ap->nested_control.features.directhypercall = 0;
a7b9020b
TG		 8041 vp_ap->current_nested_vmcs = 0;
8042 vp_ap->enlighten_vmentry = 0;
8043 }
8044
8045 static_branch_disable(&enable_evmcs);
8046 }
8047#endif
8048 vmx_cleanup_l1d_flush();
8049}
8050module_exit(vmx_exit);
8051
6aa8b732
AK		 8052static int __init vmx_init(void)
8053{
773e8a04
VK		 8054 int r;
8055
8056#if IS_ENABLED(CONFIG_HYPERV)
8057 /*
8058 * Enlightened VMCS usage should be recommended and the host needs
8059 * to support eVMCS v1 or above. We can also disable eVMCS support
8060 * with module parameter.
8061 */
8062 if (enlightened_vmcs &&
8063 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
8064 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
8065 KVM_EVMCS_VERSION) {
8066 int cpu;
8067
8068 /* Check that we have assist pages on all online CPUs */
8069 for_each_online_cpu(cpu) {
8070 if (!hv_get_vp_assist_page(cpu)) {
8071 enlightened_vmcs = false;
8072 break;
8073 }
8074 }
8075
8076 if (enlightened_vmcs) {
8077 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
8078 static_branch_enable(&enable_evmcs);
8079 }
6f6a657c
VK		 8080
8081 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
8082 vmx_x86_ops.enable_direct_tlbflush
8083 = hv_enable_direct_tlbflush;
8084
773e8a04
VK		 8085 } else {
8086 enlightened_vmcs = false;
8087 }
8088#endif
8089
8090 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
a7b9020b 8091 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8092 if (r)
34a1cd60 8093 return r;
25c5f225 8094
a7b9020b 8095 /*
7db92e16
TG		 8096 * Must be called after kvm_init() so enable_ept is properly set
8097 * up. Hand the parameter mitigation value in which was stored in
8098 * the pre module init parser. If no parameter was given, it will
8099 * contain 'auto' which will be turned into the default 'cond'
8100 * mitigation mode.
8101 */
19a36d32
WL		 8102 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8103 if (r) {
8104 vmx_exit();
8105 return r;
a47dd5f0 8106 }
25c5f225 8107
2965faa5 8108#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 8109 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8110 crash_vmclear_local_loaded_vmcss);
8111#endif
21ebf53b 8112 vmx_check_vmcs12_offsets();
8f536b76 8113
fdef3ad1 8114 return 0;
6aa8b732 8115}
a7b9020b 8116module_init(vmx_init);
Linux 6.x block layer and io_uring tree(s)