Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 7 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
8 | * |
9 | * Authors: | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
44a95dae SS |
17 | |
18 | #define pr_fmt(fmt) "SVM: " fmt | |
19 | ||
edf88417 AK |
20 | #include <linux/kvm_host.h> |
21 | ||
85f455f7 | 22 | #include "irq.h" |
1d737c8a | 23 | #include "mmu.h" |
5fdbf976 | 24 | #include "kvm_cache_regs.h" |
fe4c7b19 | 25 | #include "x86.h" |
66f7b72e | 26 | #include "cpuid.h" |
25462f7f | 27 | #include "pmu.h" |
e495606d | 28 | |
6aa8b732 | 29 | #include <linux/module.h> |
ae759544 | 30 | #include <linux/mod_devicetable.h> |
9d8f549d | 31 | #include <linux/kernel.h> |
6aa8b732 AK |
32 | #include <linux/vmalloc.h> |
33 | #include <linux/highmem.h> | |
e8edc6e0 | 34 | #include <linux/sched.h> |
af658dca | 35 | #include <linux/trace_events.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
5881f737 SS |
37 | #include <linux/amd-iommu.h> |
38 | #include <linux/hashtable.h> | |
c207aee4 | 39 | #include <linux/frame.h> |
e9df0942 | 40 | #include <linux/psp-sev.h> |
6aa8b732 | 41 | |
8221c137 | 42 | #include <asm/apic.h> |
1018faa6 | 43 | #include <asm/perf_event.h> |
67ec6607 | 44 | #include <asm/tlbflush.h> |
e495606d | 45 | #include <asm/desc.h> |
facb0139 | 46 | #include <asm/debugreg.h> |
631bc487 | 47 | #include <asm/kvm_para.h> |
411b44ba | 48 | #include <asm/irq_remapping.h> |
6aa8b732 | 49 | |
63d1142f | 50 | #include <asm/virtext.h> |
229456fc | 51 | #include "trace.h" |
63d1142f | 52 | |
4ecac3fd AK |
53 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
54 | ||
6aa8b732 AK |
55 | MODULE_AUTHOR("Qumranet"); |
56 | MODULE_LICENSE("GPL"); | |
57 | ||
ae759544 JT |
58 | static const struct x86_cpu_id svm_cpu_id[] = { |
59 | X86_FEATURE_MATCH(X86_FEATURE_SVM), | |
60 | {} | |
61 | }; | |
62 | MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id); | |
63 | ||
6aa8b732 AK |
64 | #define IOPM_ALLOC_ORDER 2 |
65 | #define MSRPM_ALLOC_ORDER 1 | |
66 | ||
6aa8b732 AK |
67 | #define SEG_TYPE_LDT 2 |
68 | #define SEG_TYPE_BUSY_TSS16 3 | |
69 | ||
6bc31bdc AP |
70 | #define SVM_FEATURE_NPT (1 << 0) |
71 | #define SVM_FEATURE_LBRV (1 << 1) | |
72 | #define SVM_FEATURE_SVML (1 << 2) | |
73 | #define SVM_FEATURE_NRIP (1 << 3) | |
ddce97aa AP |
74 | #define SVM_FEATURE_TSC_RATE (1 << 4) |
75 | #define SVM_FEATURE_VMCB_CLEAN (1 << 5) | |
76 | #define SVM_FEATURE_FLUSH_ASID (1 << 6) | |
77 | #define SVM_FEATURE_DECODE_ASSIST (1 << 7) | |
6bc31bdc | 78 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) |
80b7706e | 79 | |
340d3bc3 SS |
80 | #define SVM_AVIC_DOORBELL 0xc001011b |
81 | ||
410e4d57 JR |
82 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
83 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
84 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
85 | ||
24e09cbf JR |
86 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
87 | ||
fbc0db76 | 88 | #define TSC_RATIO_RSVD 0xffffff0000000000ULL |
92a1f12d JR |
89 | #define TSC_RATIO_MIN 0x0000000000000001ULL |
90 | #define TSC_RATIO_MAX 0x000000ffffffffffULL | |
fbc0db76 | 91 | |
5446a979 | 92 | #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF) |
44a95dae SS |
93 | |
94 | /* | |
95 | * 0xff is broadcast, so the max index allowed for physical APIC ID | |
96 | * table is 0xfe. APIC IDs above 0xff are reserved. | |
97 | */ | |
98 | #define AVIC_MAX_PHYSICAL_ID_COUNT 255 | |
99 | ||
18f40c53 SS |
100 | #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1 |
101 | #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0 | |
102 | #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF | |
103 | ||
5ea11f2b SS |
104 | /* AVIC GATAG is encoded using VM and VCPU IDs */ |
105 | #define AVIC_VCPU_ID_BITS 8 | |
106 | #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1) | |
107 | ||
108 | #define AVIC_VM_ID_BITS 24 | |
109 | #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS) | |
110 | #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1) | |
111 | ||
112 | #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \ | |
113 | (y & AVIC_VCPU_ID_MASK)) | |
114 | #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK) | |
115 | #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK) | |
116 | ||
67ec6607 JR |
117 | static bool erratum_383_found __read_mostly; |
118 | ||
6c8166a7 AK |
119 | static const u32 host_save_user_msrs[] = { |
120 | #ifdef CONFIG_X86_64 | |
121 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
122 | MSR_FS_BASE, | |
123 | #endif | |
124 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
46896c73 | 125 | MSR_TSC_AUX, |
6c8166a7 AK |
126 | }; |
127 | ||
128 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
129 | ||
130 | struct kvm_vcpu; | |
131 | ||
e6aa9abd JR |
132 | struct nested_state { |
133 | struct vmcb *hsave; | |
134 | u64 hsave_msr; | |
4a810181 | 135 | u64 vm_cr_msr; |
e6aa9abd JR |
136 | u64 vmcb; |
137 | ||
138 | /* These are the merged vectors */ | |
139 | u32 *msrpm; | |
140 | ||
141 | /* gpa pointers to the real vectors */ | |
142 | u64 vmcb_msrpm; | |
ce2ac085 | 143 | u64 vmcb_iopm; |
aad42c64 | 144 | |
cd3ff653 JR |
145 | /* A VMEXIT is required but not yet emulated */ |
146 | bool exit_required; | |
147 | ||
aad42c64 | 148 | /* cache for intercepts of the guest */ |
4ee546b4 | 149 | u32 intercept_cr; |
3aed041a | 150 | u32 intercept_dr; |
aad42c64 JR |
151 | u32 intercept_exceptions; |
152 | u64 intercept; | |
153 | ||
5bd2edc3 JR |
154 | /* Nested Paging related state */ |
155 | u64 nested_cr3; | |
e6aa9abd JR |
156 | }; |
157 | ||
323c3d80 JR |
158 | #define MSRPM_OFFSETS 16 |
159 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
160 | ||
2b036c6b BO |
161 | /* |
162 | * Set osvw_len to higher value when updated Revision Guides | |
163 | * are published and we know what the new status bits are | |
164 | */ | |
165 | static uint64_t osvw_len = 4, osvw_status; | |
166 | ||
6c8166a7 AK |
167 | struct vcpu_svm { |
168 | struct kvm_vcpu vcpu; | |
169 | struct vmcb *vmcb; | |
170 | unsigned long vmcb_pa; | |
171 | struct svm_cpu_data *svm_data; | |
172 | uint64_t asid_generation; | |
173 | uint64_t sysenter_esp; | |
174 | uint64_t sysenter_eip; | |
46896c73 | 175 | uint64_t tsc_aux; |
6c8166a7 AK |
176 | |
177 | u64 next_rip; | |
178 | ||
179 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
afe9e66f | 180 | struct { |
dacccfdd AK |
181 | u16 fs; |
182 | u16 gs; | |
183 | u16 ldt; | |
afe9e66f AK |
184 | u64 gs_base; |
185 | } host; | |
6c8166a7 AK |
186 | |
187 | u32 *msrpm; | |
6c8166a7 | 188 | |
bd3d1ec3 AK |
189 | ulong nmi_iret_rip; |
190 | ||
e6aa9abd | 191 | struct nested_state nested; |
6be7d306 JK |
192 | |
193 | bool nmi_singlestep; | |
ab2f4d73 | 194 | u64 nmi_singlestep_guest_rflags; |
66b7138f JK |
195 | |
196 | unsigned int3_injected; | |
197 | unsigned long int3_rip; | |
fbc0db76 | 198 | |
6092d3d3 JR |
199 | /* cached guest cpuid flags for faster access */ |
200 | bool nrips_enabled : 1; | |
44a95dae | 201 | |
18f40c53 | 202 | u32 ldr_reg; |
44a95dae SS |
203 | struct page *avic_backing_page; |
204 | u64 *avic_physical_id_cache; | |
8221c137 | 205 | bool avic_is_running; |
411b44ba SS |
206 | |
207 | /* | |
208 | * Per-vcpu list of struct amd_svm_iommu_ir: | |
209 | * This is used mainly to store interrupt remapping information used | |
210 | * when update the vcpu affinity. This avoids the need to scan for | |
211 | * IRTE and try to match ga_tag in the IOMMU driver. | |
212 | */ | |
213 | struct list_head ir_list; | |
214 | spinlock_t ir_list_lock; | |
215 | }; | |
216 | ||
217 | /* | |
218 | * This is a wrapper of struct amd_iommu_ir_data. | |
219 | */ | |
220 | struct amd_svm_iommu_ir { | |
221 | struct list_head node; /* Used by SVM for per-vcpu ir_list */ | |
222 | void *data; /* Storing pointer to struct amd_ir_data */ | |
6c8166a7 AK |
223 | }; |
224 | ||
44a95dae SS |
225 | #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF) |
226 | #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) | |
227 | ||
228 | #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL) | |
229 | #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12) | |
230 | #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) | |
231 | #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63) | |
232 | ||
fbc0db76 JR |
233 | static DEFINE_PER_CPU(u64, current_tsc_ratio); |
234 | #define TSC_RATIO_DEFAULT 0x0100000000ULL | |
235 | ||
455716fa JR |
236 | #define MSR_INVALID 0xffffffffU |
237 | ||
09941fbb | 238 | static const struct svm_direct_access_msrs { |
ac72a9b7 JR |
239 | u32 index; /* Index of the MSR */ |
240 | bool always; /* True if intercept is always on */ | |
241 | } direct_access_msrs[] = { | |
8c06585d | 242 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
243 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
244 | #ifdef CONFIG_X86_64 | |
245 | { .index = MSR_GS_BASE, .always = true }, | |
246 | { .index = MSR_FS_BASE, .always = true }, | |
247 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
248 | { .index = MSR_LSTAR, .always = true }, | |
249 | { .index = MSR_CSTAR, .always = true }, | |
250 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
251 | #endif | |
252 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, | |
253 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
254 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
255 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
256 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
257 | }; |
258 | ||
709ddebf JR |
259 | /* enable NPT for AMD64 and X86 with PAE */ |
260 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
261 | static bool npt_enabled = true; | |
262 | #else | |
e0231715 | 263 | static bool npt_enabled; |
709ddebf | 264 | #endif |
6c7dac72 | 265 | |
e2358851 DB |
266 | /* allow nested paging (virtualized MMU) for all guests */ |
267 | static int npt = true; | |
6c7dac72 | 268 | module_param(npt, int, S_IRUGO); |
e3da3acd | 269 | |
e2358851 DB |
270 | /* allow nested virtualization in KVM/SVM */ |
271 | static int nested = true; | |
236de055 AG |
272 | module_param(nested, int, S_IRUGO); |
273 | ||
44a95dae SS |
274 | /* enable / disable AVIC */ |
275 | static int avic; | |
5b8abf1f | 276 | #ifdef CONFIG_X86_LOCAL_APIC |
44a95dae | 277 | module_param(avic, int, S_IRUGO); |
5b8abf1f | 278 | #endif |
44a95dae | 279 | |
89c8a498 JN |
280 | /* enable/disable Virtual VMLOAD VMSAVE */ |
281 | static int vls = true; | |
282 | module_param(vls, int, 0444); | |
283 | ||
640bd6e5 JN |
284 | /* enable/disable Virtual GIF */ |
285 | static int vgif = true; | |
286 | module_param(vgif, int, 0444); | |
5ea11f2b | 287 | |
e9df0942 BS |
288 | /* enable/disable SEV support */ |
289 | static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT); | |
290 | module_param(sev, int, 0444); | |
291 | ||
79a8059d | 292 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
44874f84 | 293 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 294 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 295 | |
410e4d57 | 296 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 297 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 298 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
299 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
300 | bool has_error_code, u32 error_code); | |
301 | ||
8d28fec4 | 302 | enum { |
116a0a23 JR |
303 | VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, |
304 | pause filter count */ | |
f56838e4 | 305 | VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ |
d48086d1 | 306 | VMCB_ASID, /* ASID */ |
decdbf6a | 307 | VMCB_INTR, /* int_ctl, int_vector */ |
b2747166 | 308 | VMCB_NPT, /* npt_en, nCR3, gPAT */ |
dcca1a65 | 309 | VMCB_CR, /* CR0, CR3, CR4, EFER */ |
72214b96 | 310 | VMCB_DR, /* DR6, DR7 */ |
17a703cb | 311 | VMCB_DT, /* GDT, IDT */ |
060d0c9a | 312 | VMCB_SEG, /* CS, DS, SS, ES, CPL */ |
0574dec0 | 313 | VMCB_CR2, /* CR2 only */ |
b53ba3f9 | 314 | VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ |
44a95dae SS |
315 | VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, |
316 | * AVIC PHYSICAL_TABLE pointer, | |
317 | * AVIC LOGICAL_TABLE pointer | |
318 | */ | |
8d28fec4 RJ |
319 | VMCB_DIRTY_MAX, |
320 | }; | |
321 | ||
0574dec0 JR |
322 | /* TPR and CR2 are always written before VMRUN */ |
323 | #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) | |
8d28fec4 | 324 | |
44a95dae SS |
325 | #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL |
326 | ||
ed3cd233 BS |
327 | static unsigned int max_sev_asid; |
328 | ||
8d28fec4 RJ |
329 | static inline void mark_all_dirty(struct vmcb *vmcb) |
330 | { | |
331 | vmcb->control.clean = 0; | |
332 | } | |
333 | ||
334 | static inline void mark_all_clean(struct vmcb *vmcb) | |
335 | { | |
336 | vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) | |
337 | & ~VMCB_ALWAYS_DIRTY_MASK; | |
338 | } | |
339 | ||
340 | static inline void mark_dirty(struct vmcb *vmcb, int bit) | |
341 | { | |
342 | vmcb->control.clean &= ~(1 << bit); | |
343 | } | |
344 | ||
a2fa3e9f GH |
345 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
346 | { | |
fb3f0f51 | 347 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
348 | } |
349 | ||
44a95dae SS |
350 | static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data) |
351 | { | |
352 | svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK; | |
353 | mark_dirty(svm->vmcb, VMCB_AVIC); | |
354 | } | |
355 | ||
340d3bc3 SS |
356 | static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu) |
357 | { | |
358 | struct vcpu_svm *svm = to_svm(vcpu); | |
359 | u64 *entry = svm->avic_physical_id_cache; | |
360 | ||
361 | if (!entry) | |
362 | return false; | |
363 | ||
364 | return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); | |
365 | } | |
366 | ||
384c6368 JR |
367 | static void recalc_intercepts(struct vcpu_svm *svm) |
368 | { | |
369 | struct vmcb_control_area *c, *h; | |
370 | struct nested_state *g; | |
371 | ||
116a0a23 JR |
372 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
373 | ||
384c6368 JR |
374 | if (!is_guest_mode(&svm->vcpu)) |
375 | return; | |
376 | ||
377 | c = &svm->vmcb->control; | |
378 | h = &svm->nested.hsave->control; | |
379 | g = &svm->nested; | |
380 | ||
4ee546b4 | 381 | c->intercept_cr = h->intercept_cr | g->intercept_cr; |
3aed041a | 382 | c->intercept_dr = h->intercept_dr | g->intercept_dr; |
384c6368 JR |
383 | c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions; |
384 | c->intercept = h->intercept | g->intercept; | |
385 | } | |
386 | ||
4ee546b4 RJ |
387 | static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) |
388 | { | |
389 | if (is_guest_mode(&svm->vcpu)) | |
390 | return svm->nested.hsave; | |
391 | else | |
392 | return svm->vmcb; | |
393 | } | |
394 | ||
395 | static inline void set_cr_intercept(struct vcpu_svm *svm, int bit) | |
396 | { | |
397 | struct vmcb *vmcb = get_host_vmcb(svm); | |
398 | ||
399 | vmcb->control.intercept_cr |= (1U << bit); | |
400 | ||
401 | recalc_intercepts(svm); | |
402 | } | |
403 | ||
404 | static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit) | |
405 | { | |
406 | struct vmcb *vmcb = get_host_vmcb(svm); | |
407 | ||
408 | vmcb->control.intercept_cr &= ~(1U << bit); | |
409 | ||
410 | recalc_intercepts(svm); | |
411 | } | |
412 | ||
413 | static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit) | |
414 | { | |
415 | struct vmcb *vmcb = get_host_vmcb(svm); | |
416 | ||
417 | return vmcb->control.intercept_cr & (1U << bit); | |
418 | } | |
419 | ||
5315c716 | 420 | static inline void set_dr_intercepts(struct vcpu_svm *svm) |
3aed041a JR |
421 | { |
422 | struct vmcb *vmcb = get_host_vmcb(svm); | |
423 | ||
5315c716 PB |
424 | vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ) |
425 | | (1 << INTERCEPT_DR1_READ) | |
426 | | (1 << INTERCEPT_DR2_READ) | |
427 | | (1 << INTERCEPT_DR3_READ) | |
428 | | (1 << INTERCEPT_DR4_READ) | |
429 | | (1 << INTERCEPT_DR5_READ) | |
430 | | (1 << INTERCEPT_DR6_READ) | |
431 | | (1 << INTERCEPT_DR7_READ) | |
432 | | (1 << INTERCEPT_DR0_WRITE) | |
433 | | (1 << INTERCEPT_DR1_WRITE) | |
434 | | (1 << INTERCEPT_DR2_WRITE) | |
435 | | (1 << INTERCEPT_DR3_WRITE) | |
436 | | (1 << INTERCEPT_DR4_WRITE) | |
437 | | (1 << INTERCEPT_DR5_WRITE) | |
438 | | (1 << INTERCEPT_DR6_WRITE) | |
439 | | (1 << INTERCEPT_DR7_WRITE); | |
3aed041a JR |
440 | |
441 | recalc_intercepts(svm); | |
442 | } | |
443 | ||
5315c716 | 444 | static inline void clr_dr_intercepts(struct vcpu_svm *svm) |
3aed041a JR |
445 | { |
446 | struct vmcb *vmcb = get_host_vmcb(svm); | |
447 | ||
5315c716 | 448 | vmcb->control.intercept_dr = 0; |
3aed041a JR |
449 | |
450 | recalc_intercepts(svm); | |
451 | } | |
452 | ||
18c918c5 JR |
453 | static inline void set_exception_intercept(struct vcpu_svm *svm, int bit) |
454 | { | |
455 | struct vmcb *vmcb = get_host_vmcb(svm); | |
456 | ||
457 | vmcb->control.intercept_exceptions |= (1U << bit); | |
458 | ||
459 | recalc_intercepts(svm); | |
460 | } | |
461 | ||
462 | static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit) | |
463 | { | |
464 | struct vmcb *vmcb = get_host_vmcb(svm); | |
465 | ||
466 | vmcb->control.intercept_exceptions &= ~(1U << bit); | |
467 | ||
468 | recalc_intercepts(svm); | |
469 | } | |
470 | ||
8a05a1b8 JR |
471 | static inline void set_intercept(struct vcpu_svm *svm, int bit) |
472 | { | |
473 | struct vmcb *vmcb = get_host_vmcb(svm); | |
474 | ||
475 | vmcb->control.intercept |= (1ULL << bit); | |
476 | ||
477 | recalc_intercepts(svm); | |
478 | } | |
479 | ||
480 | static inline void clr_intercept(struct vcpu_svm *svm, int bit) | |
481 | { | |
482 | struct vmcb *vmcb = get_host_vmcb(svm); | |
483 | ||
484 | vmcb->control.intercept &= ~(1ULL << bit); | |
485 | ||
486 | recalc_intercepts(svm); | |
487 | } | |
488 | ||
640bd6e5 JN |
489 | static inline bool vgif_enabled(struct vcpu_svm *svm) |
490 | { | |
491 | return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK); | |
492 | } | |
493 | ||
2af9194d JR |
494 | static inline void enable_gif(struct vcpu_svm *svm) |
495 | { | |
640bd6e5 JN |
496 | if (vgif_enabled(svm)) |
497 | svm->vmcb->control.int_ctl |= V_GIF_MASK; | |
498 | else | |
499 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
2af9194d JR |
500 | } |
501 | ||
502 | static inline void disable_gif(struct vcpu_svm *svm) | |
503 | { | |
640bd6e5 JN |
504 | if (vgif_enabled(svm)) |
505 | svm->vmcb->control.int_ctl &= ~V_GIF_MASK; | |
506 | else | |
507 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
2af9194d JR |
508 | } |
509 | ||
510 | static inline bool gif_set(struct vcpu_svm *svm) | |
511 | { | |
640bd6e5 JN |
512 | if (vgif_enabled(svm)) |
513 | return !!(svm->vmcb->control.int_ctl & V_GIF_MASK); | |
514 | else | |
515 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
2af9194d JR |
516 | } |
517 | ||
4866d5e3 | 518 | static unsigned long iopm_base; |
6aa8b732 AK |
519 | |
520 | struct kvm_ldttss_desc { | |
521 | u16 limit0; | |
522 | u16 base0; | |
e0231715 JR |
523 | unsigned base1:8, type:5, dpl:2, p:1; |
524 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
525 | u32 base3; |
526 | u32 zero1; | |
527 | } __attribute__((packed)); | |
528 | ||
529 | struct svm_cpu_data { | |
530 | int cpu; | |
531 | ||
5008fdf5 AK |
532 | u64 asid_generation; |
533 | u32 max_asid; | |
534 | u32 next_asid; | |
4faefff3 | 535 | u32 min_asid; |
6aa8b732 AK |
536 | struct kvm_ldttss_desc *tss_desc; |
537 | ||
538 | struct page *save_area; | |
539 | }; | |
540 | ||
541 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
542 | ||
543 | struct svm_init_data { | |
544 | int cpu; | |
545 | int r; | |
546 | }; | |
547 | ||
09941fbb | 548 | static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; |
6aa8b732 | 549 | |
9d8f549d | 550 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
551 | #define MSRS_RANGE_SIZE 2048 |
552 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
553 | ||
455716fa JR |
554 | static u32 svm_msrpm_offset(u32 msr) |
555 | { | |
556 | u32 offset; | |
557 | int i; | |
558 | ||
559 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
560 | if (msr < msrpm_ranges[i] || | |
561 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
562 | continue; | |
563 | ||
564 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
565 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
566 | ||
567 | /* Now we have the u8 offset - but need the u32 offset */ | |
568 | return offset / 4; | |
569 | } | |
570 | ||
571 | /* MSR not in any range */ | |
572 | return MSR_INVALID; | |
573 | } | |
574 | ||
6aa8b732 AK |
575 | #define MAX_INST_SIZE 15 |
576 | ||
6aa8b732 AK |
577 | static inline void clgi(void) |
578 | { | |
4ecac3fd | 579 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
580 | } |
581 | ||
582 | static inline void stgi(void) | |
583 | { | |
4ecac3fd | 584 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
585 | } |
586 | ||
587 | static inline void invlpga(unsigned long addr, u32 asid) | |
588 | { | |
e0231715 | 589 | asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); |
6aa8b732 AK |
590 | } |
591 | ||
855feb67 | 592 | static int get_npt_level(struct kvm_vcpu *vcpu) |
4b16184c JR |
593 | { |
594 | #ifdef CONFIG_X86_64 | |
2a7266a8 | 595 | return PT64_ROOT_4LEVEL; |
4b16184c JR |
596 | #else |
597 | return PT32E_ROOT_LEVEL; | |
598 | #endif | |
599 | } | |
600 | ||
6aa8b732 AK |
601 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
602 | { | |
6dc696d4 | 603 | vcpu->arch.efer = efer; |
709ddebf | 604 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 605 | efer &= ~EFER_LME; |
6aa8b732 | 606 | |
9962d032 | 607 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
dcca1a65 | 608 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
609 | } |
610 | ||
6aa8b732 AK |
611 | static int is_external_interrupt(u32 info) |
612 | { | |
613 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
614 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
615 | } | |
616 | ||
37ccdcbe | 617 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
618 | { |
619 | struct vcpu_svm *svm = to_svm(vcpu); | |
620 | u32 ret = 0; | |
621 | ||
622 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
37ccdcbe PB |
623 | ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
624 | return ret; | |
2809f5d2 GC |
625 | } |
626 | ||
627 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
628 | { | |
629 | struct vcpu_svm *svm = to_svm(vcpu); | |
630 | ||
631 | if (mask == 0) | |
632 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
633 | else | |
634 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
635 | ||
636 | } | |
637 | ||
6aa8b732 AK |
638 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
639 | { | |
a2fa3e9f GH |
640 | struct vcpu_svm *svm = to_svm(vcpu); |
641 | ||
f104765b | 642 | if (svm->vmcb->control.next_rip != 0) { |
d2922422 | 643 | WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS)); |
6bc31bdc | 644 | svm->next_rip = svm->vmcb->control.next_rip; |
f104765b | 645 | } |
6bc31bdc | 646 | |
a2fa3e9f | 647 | if (!svm->next_rip) { |
51d8b661 | 648 | if (emulate_instruction(vcpu, EMULTYPE_SKIP) != |
f629cf84 GN |
649 | EMULATE_DONE) |
650 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
651 | return; |
652 | } | |
5fdbf976 MT |
653 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
654 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
655 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 656 | |
5fdbf976 | 657 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 658 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
659 | } |
660 | ||
cfcd20e5 | 661 | static void svm_queue_exception(struct kvm_vcpu *vcpu) |
116a4752 JK |
662 | { |
663 | struct vcpu_svm *svm = to_svm(vcpu); | |
cfcd20e5 WL |
664 | unsigned nr = vcpu->arch.exception.nr; |
665 | bool has_error_code = vcpu->arch.exception.has_error_code; | |
664f8e26 | 666 | bool reinject = vcpu->arch.exception.injected; |
cfcd20e5 | 667 | u32 error_code = vcpu->arch.exception.error_code; |
116a4752 | 668 | |
e0231715 JR |
669 | /* |
670 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
671 | * handle the exception | |
672 | */ | |
ce7ddec4 JR |
673 | if (!reinject && |
674 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
675 | return; |
676 | ||
2a6b20b8 | 677 | if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) { |
66b7138f JK |
678 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); |
679 | ||
680 | /* | |
681 | * For guest debugging where we have to reinject #BP if some | |
682 | * INT3 is guest-owned: | |
683 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
684 | * raises a fault that is not intercepted. Still better than | |
685 | * failing in all cases. | |
686 | */ | |
687 | skip_emulated_instruction(&svm->vcpu); | |
688 | rip = kvm_rip_read(&svm->vcpu); | |
689 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
690 | svm->int3_injected = rip - old_rip; | |
691 | } | |
692 | ||
116a4752 JK |
693 | svm->vmcb->control.event_inj = nr |
694 | | SVM_EVTINJ_VALID | |
695 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
696 | | SVM_EVTINJ_TYPE_EXEPT; | |
697 | svm->vmcb->control.event_inj_err = error_code; | |
698 | } | |
699 | ||
67ec6607 JR |
700 | static void svm_init_erratum_383(void) |
701 | { | |
702 | u32 low, high; | |
703 | int err; | |
704 | u64 val; | |
705 | ||
e6ee94d5 | 706 | if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH)) |
67ec6607 JR |
707 | return; |
708 | ||
709 | /* Use _safe variants to not break nested virtualization */ | |
710 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
711 | if (err) | |
712 | return; | |
713 | ||
714 | val |= (1ULL << 47); | |
715 | ||
716 | low = lower_32_bits(val); | |
717 | high = upper_32_bits(val); | |
718 | ||
719 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
720 | ||
721 | erratum_383_found = true; | |
722 | } | |
723 | ||
2b036c6b BO |
724 | static void svm_init_osvw(struct kvm_vcpu *vcpu) |
725 | { | |
726 | /* | |
727 | * Guests should see errata 400 and 415 as fixed (assuming that | |
728 | * HLT and IO instructions are intercepted). | |
729 | */ | |
730 | vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3; | |
731 | vcpu->arch.osvw.status = osvw_status & ~(6ULL); | |
732 | ||
733 | /* | |
734 | * By increasing VCPU's osvw.length to 3 we are telling the guest that | |
735 | * all osvw.status bits inside that length, including bit 0 (which is | |
736 | * reserved for erratum 298), are valid. However, if host processor's | |
737 | * osvw_len is 0 then osvw_status[0] carries no information. We need to | |
738 | * be conservative here and therefore we tell the guest that erratum 298 | |
739 | * is present (because we really don't know). | |
740 | */ | |
741 | if (osvw_len == 0 && boot_cpu_data.x86 == 0x10) | |
742 | vcpu->arch.osvw.status |= 1; | |
743 | } | |
744 | ||
6aa8b732 AK |
745 | static int has_svm(void) |
746 | { | |
63d1142f | 747 | const char *msg; |
6aa8b732 | 748 | |
63d1142f | 749 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 750 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
751 | return 0; |
752 | } | |
753 | ||
6aa8b732 AK |
754 | return 1; |
755 | } | |
756 | ||
13a34e06 | 757 | static void svm_hardware_disable(void) |
6aa8b732 | 758 | { |
fbc0db76 JR |
759 | /* Make sure we clean up behind us */ |
760 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) | |
761 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
762 | ||
2c8dceeb | 763 | cpu_svm_disable(); |
1018faa6 JR |
764 | |
765 | amd_pmu_disable_virt(); | |
6aa8b732 AK |
766 | } |
767 | ||
13a34e06 | 768 | static int svm_hardware_enable(void) |
6aa8b732 AK |
769 | { |
770 | ||
0fe1e009 | 771 | struct svm_cpu_data *sd; |
6aa8b732 | 772 | uint64_t efer; |
6aa8b732 AK |
773 | struct desc_struct *gdt; |
774 | int me = raw_smp_processor_id(); | |
775 | ||
10474ae8 AG |
776 | rdmsrl(MSR_EFER, efer); |
777 | if (efer & EFER_SVME) | |
778 | return -EBUSY; | |
779 | ||
6aa8b732 | 780 | if (!has_svm()) { |
1f5b77f5 | 781 | pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me); |
10474ae8 | 782 | return -EINVAL; |
6aa8b732 | 783 | } |
0fe1e009 | 784 | sd = per_cpu(svm_data, me); |
0fe1e009 | 785 | if (!sd) { |
1f5b77f5 | 786 | pr_err("%s: svm_data is NULL on %d\n", __func__, me); |
10474ae8 | 787 | return -EINVAL; |
6aa8b732 AK |
788 | } |
789 | ||
0fe1e009 TH |
790 | sd->asid_generation = 1; |
791 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
792 | sd->next_asid = sd->max_asid + 1; | |
ed3cd233 | 793 | sd->min_asid = max_sev_asid + 1; |
6aa8b732 | 794 | |
45fc8757 | 795 | gdt = get_current_gdt_rw(); |
0fe1e009 | 796 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 797 | |
9962d032 | 798 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 799 | |
d0316554 | 800 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 801 | |
fbc0db76 JR |
802 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
803 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
89cbc767 | 804 | __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT); |
fbc0db76 JR |
805 | } |
806 | ||
2b036c6b BO |
807 | |
808 | /* | |
809 | * Get OSVW bits. | |
810 | * | |
811 | * Note that it is possible to have a system with mixed processor | |
812 | * revisions and therefore different OSVW bits. If bits are not the same | |
813 | * on different processors then choose the worst case (i.e. if erratum | |
814 | * is present on one processor and not on another then assume that the | |
815 | * erratum is present everywhere). | |
816 | */ | |
817 | if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) { | |
818 | uint64_t len, status = 0; | |
819 | int err; | |
820 | ||
821 | len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err); | |
822 | if (!err) | |
823 | status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS, | |
824 | &err); | |
825 | ||
826 | if (err) | |
827 | osvw_status = osvw_len = 0; | |
828 | else { | |
829 | if (len < osvw_len) | |
830 | osvw_len = len; | |
831 | osvw_status |= status; | |
832 | osvw_status &= (1ULL << osvw_len) - 1; | |
833 | } | |
834 | } else | |
835 | osvw_status = osvw_len = 0; | |
836 | ||
67ec6607 JR |
837 | svm_init_erratum_383(); |
838 | ||
1018faa6 JR |
839 | amd_pmu_enable_virt(); |
840 | ||
10474ae8 | 841 | return 0; |
6aa8b732 AK |
842 | } |
843 | ||
0da1db75 JR |
844 | static void svm_cpu_uninit(int cpu) |
845 | { | |
0fe1e009 | 846 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 847 | |
0fe1e009 | 848 | if (!sd) |
0da1db75 JR |
849 | return; |
850 | ||
851 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
0fe1e009 TH |
852 | __free_page(sd->save_area); |
853 | kfree(sd); | |
0da1db75 JR |
854 | } |
855 | ||
6aa8b732 AK |
856 | static int svm_cpu_init(int cpu) |
857 | { | |
0fe1e009 | 858 | struct svm_cpu_data *sd; |
6aa8b732 AK |
859 | int r; |
860 | ||
0fe1e009 TH |
861 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
862 | if (!sd) | |
6aa8b732 | 863 | return -ENOMEM; |
0fe1e009 TH |
864 | sd->cpu = cpu; |
865 | sd->save_area = alloc_page(GFP_KERNEL); | |
6aa8b732 | 866 | r = -ENOMEM; |
0fe1e009 | 867 | if (!sd->save_area) |
6aa8b732 AK |
868 | goto err_1; |
869 | ||
0fe1e009 | 870 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
871 | |
872 | return 0; | |
873 | ||
874 | err_1: | |
0fe1e009 | 875 | kfree(sd); |
6aa8b732 AK |
876 | return r; |
877 | ||
878 | } | |
879 | ||
ac72a9b7 JR |
880 | static bool valid_msr_intercept(u32 index) |
881 | { | |
882 | int i; | |
883 | ||
884 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
885 | if (direct_access_msrs[i].index == index) | |
886 | return true; | |
887 | ||
888 | return false; | |
889 | } | |
890 | ||
bfc733a7 RR |
891 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
892 | int read, int write) | |
6aa8b732 | 893 | { |
455716fa JR |
894 | u8 bit_read, bit_write; |
895 | unsigned long tmp; | |
896 | u32 offset; | |
6aa8b732 | 897 | |
ac72a9b7 JR |
898 | /* |
899 | * If this warning triggers extend the direct_access_msrs list at the | |
900 | * beginning of the file | |
901 | */ | |
902 | WARN_ON(!valid_msr_intercept(msr)); | |
903 | ||
455716fa JR |
904 | offset = svm_msrpm_offset(msr); |
905 | bit_read = 2 * (msr & 0x0f); | |
906 | bit_write = 2 * (msr & 0x0f) + 1; | |
907 | tmp = msrpm[offset]; | |
908 | ||
909 | BUG_ON(offset == MSR_INVALID); | |
910 | ||
911 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
912 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
913 | ||
914 | msrpm[offset] = tmp; | |
6aa8b732 AK |
915 | } |
916 | ||
f65c229c | 917 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
918 | { |
919 | int i; | |
920 | ||
f65c229c JR |
921 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
922 | ||
ac72a9b7 JR |
923 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
924 | if (!direct_access_msrs[i].always) | |
925 | continue; | |
926 | ||
927 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
928 | } | |
f65c229c JR |
929 | } |
930 | ||
323c3d80 JR |
931 | static void add_msr_offset(u32 offset) |
932 | { | |
933 | int i; | |
934 | ||
935 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
936 | ||
937 | /* Offset already in list? */ | |
938 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 939 | return; |
323c3d80 JR |
940 | |
941 | /* Slot used by another offset? */ | |
942 | if (msrpm_offsets[i] != MSR_INVALID) | |
943 | continue; | |
944 | ||
945 | /* Add offset to list */ | |
946 | msrpm_offsets[i] = offset; | |
947 | ||
948 | return; | |
6aa8b732 | 949 | } |
323c3d80 JR |
950 | |
951 | /* | |
952 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
953 | * increase MSRPM_OFFSETS in this case. | |
954 | */ | |
bfc733a7 | 955 | BUG(); |
6aa8b732 AK |
956 | } |
957 | ||
323c3d80 | 958 | static void init_msrpm_offsets(void) |
f65c229c | 959 | { |
323c3d80 | 960 | int i; |
f65c229c | 961 | |
323c3d80 JR |
962 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
963 | ||
964 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
965 | u32 offset; | |
966 | ||
967 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
968 | BUG_ON(offset == MSR_INVALID); | |
969 | ||
970 | add_msr_offset(offset); | |
971 | } | |
f65c229c JR |
972 | } |
973 | ||
24e09cbf JR |
974 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
975 | { | |
976 | u32 *msrpm = svm->msrpm; | |
977 | ||
0dc92119 | 978 | svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK; |
24e09cbf JR |
979 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); |
980 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
981 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
982 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
983 | } | |
984 | ||
985 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
986 | { | |
987 | u32 *msrpm = svm->msrpm; | |
988 | ||
0dc92119 | 989 | svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK; |
24e09cbf JR |
990 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); |
991 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
992 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
993 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
994 | } | |
995 | ||
4aebd0e9 LP |
996 | static void disable_nmi_singlestep(struct vcpu_svm *svm) |
997 | { | |
998 | svm->nmi_singlestep = false; | |
640bd6e5 | 999 | |
ab2f4d73 LP |
1000 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) { |
1001 | /* Clear our flags if they were not set by the guest */ | |
1002 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF)) | |
1003 | svm->vmcb->save.rflags &= ~X86_EFLAGS_TF; | |
1004 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF)) | |
1005 | svm->vmcb->save.rflags &= ~X86_EFLAGS_RF; | |
1006 | } | |
4aebd0e9 LP |
1007 | } |
1008 | ||
5881f737 SS |
1009 | /* Note: |
1010 | * This hash table is used to map VM_ID to a struct kvm_arch, | |
1011 | * when handling AMD IOMMU GALOG notification to schedule in | |
1012 | * a particular vCPU. | |
1013 | */ | |
1014 | #define SVM_VM_DATA_HASH_BITS 8 | |
681bcea8 | 1015 | static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS); |
3f0d4db7 DV |
1016 | static u32 next_vm_id = 0; |
1017 | static bool next_vm_id_wrapped = 0; | |
681bcea8 | 1018 | static DEFINE_SPINLOCK(svm_vm_data_hash_lock); |
5881f737 SS |
1019 | |
1020 | /* Note: | |
1021 | * This function is called from IOMMU driver to notify | |
1022 | * SVM to schedule in a particular vCPU of a particular VM. | |
1023 | */ | |
1024 | static int avic_ga_log_notifier(u32 ga_tag) | |
1025 | { | |
1026 | unsigned long flags; | |
1027 | struct kvm_arch *ka = NULL; | |
1028 | struct kvm_vcpu *vcpu = NULL; | |
1029 | u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag); | |
1030 | u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag); | |
1031 | ||
1032 | pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id); | |
1033 | ||
1034 | spin_lock_irqsave(&svm_vm_data_hash_lock, flags); | |
1035 | hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) { | |
1036 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
1037 | struct kvm_arch *vm_data = &kvm->arch; | |
1038 | ||
1039 | if (vm_data->avic_vm_id != vm_id) | |
1040 | continue; | |
1041 | vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id); | |
1042 | break; | |
1043 | } | |
1044 | spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); | |
1045 | ||
5881f737 SS |
1046 | /* Note: |
1047 | * At this point, the IOMMU should have already set the pending | |
1048 | * bit in the vAPIC backing page. So, we just need to schedule | |
1049 | * in the vcpu. | |
1050 | */ | |
1cf53587 | 1051 | if (vcpu) |
5881f737 SS |
1052 | kvm_vcpu_wake_up(vcpu); |
1053 | ||
1054 | return 0; | |
1055 | } | |
1056 | ||
e9df0942 BS |
1057 | static __init int sev_hardware_setup(void) |
1058 | { | |
1059 | struct sev_user_data_status *status; | |
1060 | int rc; | |
1061 | ||
1062 | /* Maximum number of encrypted guests supported simultaneously */ | |
1063 | max_sev_asid = cpuid_ecx(0x8000001F); | |
1064 | ||
1065 | if (!max_sev_asid) | |
1066 | return 1; | |
1067 | ||
1068 | status = kmalloc(sizeof(*status), GFP_KERNEL); | |
1069 | if (!status) | |
1070 | return 1; | |
1071 | ||
1072 | /* | |
1073 | * Check SEV platform status. | |
1074 | * | |
1075 | * PLATFORM_STATUS can be called in any state, if we failed to query | |
1076 | * the PLATFORM status then either PSP firmware does not support SEV | |
1077 | * feature or SEV firmware is dead. | |
1078 | */ | |
1079 | rc = sev_platform_status(status, NULL); | |
1080 | if (rc) | |
1081 | goto err; | |
1082 | ||
1083 | pr_info("SEV supported\n"); | |
1084 | ||
1085 | err: | |
1086 | kfree(status); | |
1087 | return rc; | |
1088 | } | |
1089 | ||
6aa8b732 AK |
1090 | static __init int svm_hardware_setup(void) |
1091 | { | |
1092 | int cpu; | |
1093 | struct page *iopm_pages; | |
f65c229c | 1094 | void *iopm_va; |
6aa8b732 AK |
1095 | int r; |
1096 | ||
6aa8b732 AK |
1097 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
1098 | ||
1099 | if (!iopm_pages) | |
1100 | return -ENOMEM; | |
c8681339 AL |
1101 | |
1102 | iopm_va = page_address(iopm_pages); | |
1103 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
1104 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
1105 | ||
323c3d80 JR |
1106 | init_msrpm_offsets(); |
1107 | ||
50a37eb4 JR |
1108 | if (boot_cpu_has(X86_FEATURE_NX)) |
1109 | kvm_enable_efer_bits(EFER_NX); | |
1110 | ||
1b2fd70c AG |
1111 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
1112 | kvm_enable_efer_bits(EFER_FFXSR); | |
1113 | ||
92a1f12d | 1114 | if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
92a1f12d | 1115 | kvm_has_tsc_control = true; |
bc9b961b HZ |
1116 | kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX; |
1117 | kvm_tsc_scaling_ratio_frac_bits = 32; | |
92a1f12d JR |
1118 | } |
1119 | ||
236de055 AG |
1120 | if (nested) { |
1121 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 1122 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
1123 | } |
1124 | ||
e9df0942 BS |
1125 | if (sev) { |
1126 | if (boot_cpu_has(X86_FEATURE_SEV) && | |
1127 | IS_ENABLED(CONFIG_KVM_AMD_SEV)) { | |
1128 | r = sev_hardware_setup(); | |
1129 | if (r) | |
1130 | sev = false; | |
1131 | } else { | |
1132 | sev = false; | |
1133 | } | |
1134 | } | |
1135 | ||
3230bb47 | 1136 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
1137 | r = svm_cpu_init(cpu); |
1138 | if (r) | |
f65c229c | 1139 | goto err; |
6aa8b732 | 1140 | } |
33bd6a0b | 1141 | |
2a6b20b8 | 1142 | if (!boot_cpu_has(X86_FEATURE_NPT)) |
e3da3acd JR |
1143 | npt_enabled = false; |
1144 | ||
6c7dac72 JR |
1145 | if (npt_enabled && !npt) { |
1146 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
1147 | npt_enabled = false; | |
1148 | } | |
1149 | ||
18552672 | 1150 | if (npt_enabled) { |
e3da3acd | 1151 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 1152 | kvm_enable_tdp(); |
5f4cb662 JR |
1153 | } else |
1154 | kvm_disable_tdp(); | |
e3da3acd | 1155 | |
5b8abf1f SS |
1156 | if (avic) { |
1157 | if (!npt_enabled || | |
1158 | !boot_cpu_has(X86_FEATURE_AVIC) || | |
5881f737 | 1159 | !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) { |
5b8abf1f | 1160 | avic = false; |
5881f737 | 1161 | } else { |
5b8abf1f | 1162 | pr_info("AVIC enabled\n"); |
5881f737 | 1163 | |
5881f737 SS |
1164 | amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier); |
1165 | } | |
5b8abf1f | 1166 | } |
44a95dae | 1167 | |
89c8a498 JN |
1168 | if (vls) { |
1169 | if (!npt_enabled || | |
5442c269 | 1170 | !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) || |
89c8a498 JN |
1171 | !IS_ENABLED(CONFIG_X86_64)) { |
1172 | vls = false; | |
1173 | } else { | |
1174 | pr_info("Virtual VMLOAD VMSAVE supported\n"); | |
1175 | } | |
1176 | } | |
1177 | ||
640bd6e5 JN |
1178 | if (vgif) { |
1179 | if (!boot_cpu_has(X86_FEATURE_VGIF)) | |
1180 | vgif = false; | |
1181 | else | |
1182 | pr_info("Virtual GIF supported\n"); | |
1183 | } | |
1184 | ||
6aa8b732 AK |
1185 | return 0; |
1186 | ||
f65c229c | 1187 | err: |
6aa8b732 AK |
1188 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
1189 | iopm_base = 0; | |
1190 | return r; | |
1191 | } | |
1192 | ||
1193 | static __exit void svm_hardware_unsetup(void) | |
1194 | { | |
0da1db75 JR |
1195 | int cpu; |
1196 | ||
3230bb47 | 1197 | for_each_possible_cpu(cpu) |
0da1db75 JR |
1198 | svm_cpu_uninit(cpu); |
1199 | ||
6aa8b732 | 1200 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 1201 | iopm_base = 0; |
6aa8b732 AK |
1202 | } |
1203 | ||
1204 | static void init_seg(struct vmcb_seg *seg) | |
1205 | { | |
1206 | seg->selector = 0; | |
1207 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 1208 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
1209 | seg->limit = 0xffff; |
1210 | seg->base = 0; | |
1211 | } | |
1212 | ||
1213 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
1214 | { | |
1215 | seg->selector = 0; | |
1216 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
1217 | seg->limit = 0xffff; | |
1218 | seg->base = 0; | |
1219 | } | |
1220 | ||
f4e1b3c8 ZA |
1221 | static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
1222 | { | |
1223 | struct vcpu_svm *svm = to_svm(vcpu); | |
1224 | u64 g_tsc_offset = 0; | |
1225 | ||
2030753d | 1226 | if (is_guest_mode(vcpu)) { |
f4e1b3c8 ZA |
1227 | g_tsc_offset = svm->vmcb->control.tsc_offset - |
1228 | svm->nested.hsave->control.tsc_offset; | |
1229 | svm->nested.hsave->control.tsc_offset = offset; | |
489223ed YY |
1230 | } else |
1231 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, | |
1232 | svm->vmcb->control.tsc_offset, | |
1233 | offset); | |
f4e1b3c8 ZA |
1234 | |
1235 | svm->vmcb->control.tsc_offset = offset + g_tsc_offset; | |
116a0a23 JR |
1236 | |
1237 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); | |
f4e1b3c8 ZA |
1238 | } |
1239 | ||
44a95dae SS |
1240 | static void avic_init_vmcb(struct vcpu_svm *svm) |
1241 | { | |
1242 | struct vmcb *vmcb = svm->vmcb; | |
1243 | struct kvm_arch *vm_data = &svm->vcpu.kvm->arch; | |
d0ec49d4 TL |
1244 | phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page)); |
1245 | phys_addr_t lpa = __sme_set(page_to_phys(vm_data->avic_logical_id_table_page)); | |
1246 | phys_addr_t ppa = __sme_set(page_to_phys(vm_data->avic_physical_id_table_page)); | |
44a95dae SS |
1247 | |
1248 | vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK; | |
1249 | vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK; | |
1250 | vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK; | |
1251 | vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT; | |
1252 | vmcb->control.int_ctl |= AVIC_ENABLE_MASK; | |
44a95dae SS |
1253 | } |
1254 | ||
5690891b | 1255 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 1256 | { |
e6101a96 JR |
1257 | struct vmcb_control_area *control = &svm->vmcb->control; |
1258 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 1259 | |
4ee546b4 | 1260 | svm->vcpu.arch.hflags = 0; |
bff78274 | 1261 | |
4ee546b4 RJ |
1262 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1263 | set_cr_intercept(svm, INTERCEPT_CR3_READ); | |
1264 | set_cr_intercept(svm, INTERCEPT_CR4_READ); | |
1265 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
1266 | set_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
1267 | set_cr_intercept(svm, INTERCEPT_CR4_WRITE); | |
3bbf3565 SS |
1268 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) |
1269 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
6aa8b732 | 1270 | |
5315c716 | 1271 | set_dr_intercepts(svm); |
6aa8b732 | 1272 | |
18c918c5 JR |
1273 | set_exception_intercept(svm, PF_VECTOR); |
1274 | set_exception_intercept(svm, UD_VECTOR); | |
1275 | set_exception_intercept(svm, MC_VECTOR); | |
54a20552 | 1276 | set_exception_intercept(svm, AC_VECTOR); |
cbdb967a | 1277 | set_exception_intercept(svm, DB_VECTOR); |
6aa8b732 | 1278 | |
8a05a1b8 JR |
1279 | set_intercept(svm, INTERCEPT_INTR); |
1280 | set_intercept(svm, INTERCEPT_NMI); | |
1281 | set_intercept(svm, INTERCEPT_SMI); | |
1282 | set_intercept(svm, INTERCEPT_SELECTIVE_CR0); | |
332b56e4 | 1283 | set_intercept(svm, INTERCEPT_RDPMC); |
8a05a1b8 JR |
1284 | set_intercept(svm, INTERCEPT_CPUID); |
1285 | set_intercept(svm, INTERCEPT_INVD); | |
1286 | set_intercept(svm, INTERCEPT_HLT); | |
1287 | set_intercept(svm, INTERCEPT_INVLPG); | |
1288 | set_intercept(svm, INTERCEPT_INVLPGA); | |
1289 | set_intercept(svm, INTERCEPT_IOIO_PROT); | |
1290 | set_intercept(svm, INTERCEPT_MSR_PROT); | |
1291 | set_intercept(svm, INTERCEPT_TASK_SWITCH); | |
1292 | set_intercept(svm, INTERCEPT_SHUTDOWN); | |
1293 | set_intercept(svm, INTERCEPT_VMRUN); | |
1294 | set_intercept(svm, INTERCEPT_VMMCALL); | |
1295 | set_intercept(svm, INTERCEPT_VMLOAD); | |
1296 | set_intercept(svm, INTERCEPT_VMSAVE); | |
1297 | set_intercept(svm, INTERCEPT_STGI); | |
1298 | set_intercept(svm, INTERCEPT_CLGI); | |
1299 | set_intercept(svm, INTERCEPT_SKINIT); | |
1300 | set_intercept(svm, INTERCEPT_WBINVD); | |
81dd35d4 | 1301 | set_intercept(svm, INTERCEPT_XSETBV); |
6aa8b732 | 1302 | |
668fffa3 MT |
1303 | if (!kvm_mwait_in_guest()) { |
1304 | set_intercept(svm, INTERCEPT_MONITOR); | |
1305 | set_intercept(svm, INTERCEPT_MWAIT); | |
1306 | } | |
1307 | ||
d0ec49d4 TL |
1308 | control->iopm_base_pa = __sme_set(iopm_base); |
1309 | control->msrpm_base_pa = __sme_set(__pa(svm->msrpm)); | |
6aa8b732 AK |
1310 | control->int_ctl = V_INTR_MASKING_MASK; |
1311 | ||
1312 | init_seg(&save->es); | |
1313 | init_seg(&save->ss); | |
1314 | init_seg(&save->ds); | |
1315 | init_seg(&save->fs); | |
1316 | init_seg(&save->gs); | |
1317 | ||
1318 | save->cs.selector = 0xf000; | |
04b66839 | 1319 | save->cs.base = 0xffff0000; |
6aa8b732 AK |
1320 | /* Executable/Readable Code Segment */ |
1321 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
1322 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
1323 | save->cs.limit = 0xffff; | |
6aa8b732 AK |
1324 | |
1325 | save->gdtr.limit = 0xffff; | |
1326 | save->idtr.limit = 0xffff; | |
1327 | ||
1328 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
1329 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
1330 | ||
5690891b | 1331 | svm_set_efer(&svm->vcpu, 0); |
d77c26fc | 1332 | save->dr6 = 0xffff0ff0; |
f6e78475 | 1333 | kvm_set_rflags(&svm->vcpu, 2); |
6aa8b732 | 1334 | save->rip = 0x0000fff0; |
5fdbf976 | 1335 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 1336 | |
e0231715 | 1337 | /* |
18fa000a | 1338 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
d28bc9dd | 1339 | * It also updates the guest-visible cr0 value. |
6aa8b732 | 1340 | */ |
79a8059d | 1341 | svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); |
ebae871a | 1342 | kvm_mmu_reset_context(&svm->vcpu); |
18fa000a | 1343 | |
66aee91a | 1344 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 1345 | /* rdx = ?? */ |
709ddebf JR |
1346 | |
1347 | if (npt_enabled) { | |
1348 | /* Setup VMCB for Nested Paging */ | |
cea3a19b | 1349 | control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE; |
8a05a1b8 | 1350 | clr_intercept(svm, INTERCEPT_INVLPG); |
18c918c5 | 1351 | clr_exception_intercept(svm, PF_VECTOR); |
4ee546b4 RJ |
1352 | clr_cr_intercept(svm, INTERCEPT_CR3_READ); |
1353 | clr_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
74545705 | 1354 | save->g_pat = svm->vcpu.arch.pat; |
709ddebf JR |
1355 | save->cr3 = 0; |
1356 | save->cr4 = 0; | |
1357 | } | |
f40f6a45 | 1358 | svm->asid_generation = 0; |
1371d904 | 1359 | |
e6aa9abd | 1360 | svm->nested.vmcb = 0; |
2af9194d JR |
1361 | svm->vcpu.arch.hflags = 0; |
1362 | ||
2a6b20b8 | 1363 | if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { |
565d0998 | 1364 | control->pause_filter_count = 3000; |
8a05a1b8 | 1365 | set_intercept(svm, INTERCEPT_PAUSE); |
565d0998 ML |
1366 | } |
1367 | ||
67034bb9 | 1368 | if (kvm_vcpu_apicv_active(&svm->vcpu)) |
44a95dae SS |
1369 | avic_init_vmcb(svm); |
1370 | ||
89c8a498 JN |
1371 | /* |
1372 | * If hardware supports Virtual VMLOAD VMSAVE then enable it | |
1373 | * in VMCB and clear intercepts to avoid #VMEXIT. | |
1374 | */ | |
1375 | if (vls) { | |
1376 | clr_intercept(svm, INTERCEPT_VMLOAD); | |
1377 | clr_intercept(svm, INTERCEPT_VMSAVE); | |
1378 | svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK; | |
1379 | } | |
1380 | ||
640bd6e5 JN |
1381 | if (vgif) { |
1382 | clr_intercept(svm, INTERCEPT_STGI); | |
1383 | clr_intercept(svm, INTERCEPT_CLGI); | |
1384 | svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK; | |
1385 | } | |
1386 | ||
8d28fec4 RJ |
1387 | mark_all_dirty(svm->vmcb); |
1388 | ||
2af9194d | 1389 | enable_gif(svm); |
44a95dae SS |
1390 | |
1391 | } | |
1392 | ||
d3e7dec0 DC |
1393 | static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, |
1394 | unsigned int index) | |
44a95dae SS |
1395 | { |
1396 | u64 *avic_physical_id_table; | |
1397 | struct kvm_arch *vm_data = &vcpu->kvm->arch; | |
1398 | ||
1399 | if (index >= AVIC_MAX_PHYSICAL_ID_COUNT) | |
1400 | return NULL; | |
1401 | ||
1402 | avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page); | |
1403 | ||
1404 | return &avic_physical_id_table[index]; | |
1405 | } | |
1406 | ||
1407 | /** | |
1408 | * Note: | |
1409 | * AVIC hardware walks the nested page table to check permissions, | |
1410 | * but does not use the SPA address specified in the leaf page | |
1411 | * table entry since it uses address in the AVIC_BACKING_PAGE pointer | |
1412 | * field of the VMCB. Therefore, we set up the | |
1413 | * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here. | |
1414 | */ | |
1415 | static int avic_init_access_page(struct kvm_vcpu *vcpu) | |
1416 | { | |
1417 | struct kvm *kvm = vcpu->kvm; | |
1418 | int ret; | |
1419 | ||
1420 | if (kvm->arch.apic_access_page_done) | |
1421 | return 0; | |
1422 | ||
1423 | ret = x86_set_memory_region(kvm, | |
1424 | APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
1425 | APIC_DEFAULT_PHYS_BASE, | |
1426 | PAGE_SIZE); | |
1427 | if (ret) | |
1428 | return ret; | |
1429 | ||
1430 | kvm->arch.apic_access_page_done = true; | |
1431 | return 0; | |
1432 | } | |
1433 | ||
1434 | static int avic_init_backing_page(struct kvm_vcpu *vcpu) | |
1435 | { | |
1436 | int ret; | |
1437 | u64 *entry, new_entry; | |
1438 | int id = vcpu->vcpu_id; | |
1439 | struct vcpu_svm *svm = to_svm(vcpu); | |
1440 | ||
1441 | ret = avic_init_access_page(vcpu); | |
1442 | if (ret) | |
1443 | return ret; | |
1444 | ||
1445 | if (id >= AVIC_MAX_PHYSICAL_ID_COUNT) | |
1446 | return -EINVAL; | |
1447 | ||
1448 | if (!svm->vcpu.arch.apic->regs) | |
1449 | return -EINVAL; | |
1450 | ||
1451 | svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs); | |
1452 | ||
1453 | /* Setting AVIC backing page address in the phy APIC ID table */ | |
1454 | entry = avic_get_physical_id_entry(vcpu, id); | |
1455 | if (!entry) | |
1456 | return -EINVAL; | |
1457 | ||
1458 | new_entry = READ_ONCE(*entry); | |
d0ec49d4 TL |
1459 | new_entry = __sme_set((page_to_phys(svm->avic_backing_page) & |
1460 | AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) | | |
1461 | AVIC_PHYSICAL_ID_ENTRY_VALID_MASK); | |
44a95dae SS |
1462 | WRITE_ONCE(*entry, new_entry); |
1463 | ||
1464 | svm->avic_physical_id_cache = entry; | |
1465 | ||
1466 | return 0; | |
1467 | } | |
1468 | ||
1469 | static void avic_vm_destroy(struct kvm *kvm) | |
1470 | { | |
5881f737 | 1471 | unsigned long flags; |
44a95dae SS |
1472 | struct kvm_arch *vm_data = &kvm->arch; |
1473 | ||
3863dff0 DV |
1474 | if (!avic) |
1475 | return; | |
1476 | ||
44a95dae SS |
1477 | if (vm_data->avic_logical_id_table_page) |
1478 | __free_page(vm_data->avic_logical_id_table_page); | |
1479 | if (vm_data->avic_physical_id_table_page) | |
1480 | __free_page(vm_data->avic_physical_id_table_page); | |
5881f737 SS |
1481 | |
1482 | spin_lock_irqsave(&svm_vm_data_hash_lock, flags); | |
1483 | hash_del(&vm_data->hnode); | |
1484 | spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); | |
44a95dae SS |
1485 | } |
1486 | ||
1487 | static int avic_vm_init(struct kvm *kvm) | |
1488 | { | |
5881f737 | 1489 | unsigned long flags; |
3f0d4db7 | 1490 | int err = -ENOMEM; |
44a95dae SS |
1491 | struct kvm_arch *vm_data = &kvm->arch; |
1492 | struct page *p_page; | |
1493 | struct page *l_page; | |
3f0d4db7 DV |
1494 | struct kvm_arch *ka; |
1495 | u32 vm_id; | |
44a95dae SS |
1496 | |
1497 | if (!avic) | |
1498 | return 0; | |
1499 | ||
1500 | /* Allocating physical APIC ID table (4KB) */ | |
1501 | p_page = alloc_page(GFP_KERNEL); | |
1502 | if (!p_page) | |
1503 | goto free_avic; | |
1504 | ||
1505 | vm_data->avic_physical_id_table_page = p_page; | |
1506 | clear_page(page_address(p_page)); | |
1507 | ||
1508 | /* Allocating logical APIC ID table (4KB) */ | |
1509 | l_page = alloc_page(GFP_KERNEL); | |
1510 | if (!l_page) | |
1511 | goto free_avic; | |
1512 | ||
1513 | vm_data->avic_logical_id_table_page = l_page; | |
1514 | clear_page(page_address(l_page)); | |
1515 | ||
5881f737 | 1516 | spin_lock_irqsave(&svm_vm_data_hash_lock, flags); |
3f0d4db7 DV |
1517 | again: |
1518 | vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK; | |
1519 | if (vm_id == 0) { /* id is 1-based, zero is not okay */ | |
1520 | next_vm_id_wrapped = 1; | |
1521 | goto again; | |
1522 | } | |
1523 | /* Is it still in use? Only possible if wrapped at least once */ | |
1524 | if (next_vm_id_wrapped) { | |
1525 | hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) { | |
1526 | struct kvm *k2 = container_of(ka, struct kvm, arch); | |
1527 | struct kvm_arch *vd2 = &k2->arch; | |
1528 | if (vd2->avic_vm_id == vm_id) | |
1529 | goto again; | |
1530 | } | |
1531 | } | |
1532 | vm_data->avic_vm_id = vm_id; | |
5881f737 SS |
1533 | hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id); |
1534 | spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); | |
1535 | ||
44a95dae SS |
1536 | return 0; |
1537 | ||
1538 | free_avic: | |
1539 | avic_vm_destroy(kvm); | |
1540 | return err; | |
6aa8b732 AK |
1541 | } |
1542 | ||
411b44ba SS |
1543 | static inline int |
1544 | avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r) | |
8221c137 | 1545 | { |
411b44ba SS |
1546 | int ret = 0; |
1547 | unsigned long flags; | |
1548 | struct amd_svm_iommu_ir *ir; | |
8221c137 SS |
1549 | struct vcpu_svm *svm = to_svm(vcpu); |
1550 | ||
411b44ba SS |
1551 | if (!kvm_arch_has_assigned_device(vcpu->kvm)) |
1552 | return 0; | |
8221c137 | 1553 | |
411b44ba SS |
1554 | /* |
1555 | * Here, we go through the per-vcpu ir_list to update all existing | |
1556 | * interrupt remapping table entry targeting this vcpu. | |
1557 | */ | |
1558 | spin_lock_irqsave(&svm->ir_list_lock, flags); | |
8221c137 | 1559 | |
411b44ba SS |
1560 | if (list_empty(&svm->ir_list)) |
1561 | goto out; | |
8221c137 | 1562 | |
411b44ba SS |
1563 | list_for_each_entry(ir, &svm->ir_list, node) { |
1564 | ret = amd_iommu_update_ga(cpu, r, ir->data); | |
1565 | if (ret) | |
1566 | break; | |
1567 | } | |
1568 | out: | |
1569 | spin_unlock_irqrestore(&svm->ir_list_lock, flags); | |
1570 | return ret; | |
8221c137 SS |
1571 | } |
1572 | ||
1573 | static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) | |
1574 | { | |
1575 | u64 entry; | |
1576 | /* ID = 0xff (broadcast), ID > 0xff (reserved) */ | |
7d669f50 | 1577 | int h_physical_id = kvm_cpu_get_apicid(cpu); |
8221c137 SS |
1578 | struct vcpu_svm *svm = to_svm(vcpu); |
1579 | ||
1580 | if (!kvm_vcpu_apicv_active(vcpu)) | |
1581 | return; | |
1582 | ||
1583 | if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT)) | |
1584 | return; | |
1585 | ||
1586 | entry = READ_ONCE(*(svm->avic_physical_id_cache)); | |
1587 | WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); | |
1588 | ||
1589 | entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK; | |
1590 | entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK); | |
1591 | ||
1592 | entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; | |
1593 | if (svm->avic_is_running) | |
1594 | entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; | |
1595 | ||
1596 | WRITE_ONCE(*(svm->avic_physical_id_cache), entry); | |
411b44ba SS |
1597 | avic_update_iommu_vcpu_affinity(vcpu, h_physical_id, |
1598 | svm->avic_is_running); | |
8221c137 SS |
1599 | } |
1600 | ||
1601 | static void avic_vcpu_put(struct kvm_vcpu *vcpu) | |
1602 | { | |
1603 | u64 entry; | |
1604 | struct vcpu_svm *svm = to_svm(vcpu); | |
1605 | ||
1606 | if (!kvm_vcpu_apicv_active(vcpu)) | |
1607 | return; | |
1608 | ||
1609 | entry = READ_ONCE(*(svm->avic_physical_id_cache)); | |
411b44ba SS |
1610 | if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) |
1611 | avic_update_iommu_vcpu_affinity(vcpu, -1, 0); | |
1612 | ||
8221c137 SS |
1613 | entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; |
1614 | WRITE_ONCE(*(svm->avic_physical_id_cache), entry); | |
6aa8b732 AK |
1615 | } |
1616 | ||
411b44ba SS |
1617 | /** |
1618 | * This function is called during VCPU halt/unhalt. | |
1619 | */ | |
1620 | static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run) | |
1621 | { | |
1622 | struct vcpu_svm *svm = to_svm(vcpu); | |
1623 | ||
1624 | svm->avic_is_running = is_run; | |
1625 | if (is_run) | |
1626 | avic_vcpu_load(vcpu, vcpu->cpu); | |
1627 | else | |
1628 | avic_vcpu_put(vcpu); | |
1629 | } | |
1630 | ||
d28bc9dd | 1631 | static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
04d2cc77 AK |
1632 | { |
1633 | struct vcpu_svm *svm = to_svm(vcpu); | |
66f7b72e JS |
1634 | u32 dummy; |
1635 | u32 eax = 1; | |
04d2cc77 | 1636 | |
d28bc9dd NA |
1637 | if (!init_event) { |
1638 | svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE | | |
1639 | MSR_IA32_APICBASE_ENABLE; | |
1640 | if (kvm_vcpu_is_reset_bsp(&svm->vcpu)) | |
1641 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; | |
1642 | } | |
5690891b | 1643 | init_vmcb(svm); |
70433389 | 1644 | |
e911eb3b | 1645 | kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true); |
66f7b72e | 1646 | kvm_register_write(vcpu, VCPU_REGS_RDX, eax); |
44a95dae SS |
1647 | |
1648 | if (kvm_vcpu_apicv_active(vcpu) && !init_event) | |
1649 | avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE); | |
04d2cc77 AK |
1650 | } |
1651 | ||
dfa20099 SS |
1652 | static int avic_init_vcpu(struct vcpu_svm *svm) |
1653 | { | |
1654 | int ret; | |
1655 | ||
67034bb9 | 1656 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) |
dfa20099 SS |
1657 | return 0; |
1658 | ||
1659 | ret = avic_init_backing_page(&svm->vcpu); | |
1660 | if (ret) | |
1661 | return ret; | |
1662 | ||
1663 | INIT_LIST_HEAD(&svm->ir_list); | |
1664 | spin_lock_init(&svm->ir_list_lock); | |
1665 | ||
1666 | return ret; | |
1667 | } | |
1668 | ||
fb3f0f51 | 1669 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 1670 | { |
a2fa3e9f | 1671 | struct vcpu_svm *svm; |
6aa8b732 | 1672 | struct page *page; |
f65c229c | 1673 | struct page *msrpm_pages; |
b286d5d8 | 1674 | struct page *hsave_page; |
3d6368ef | 1675 | struct page *nested_msrpm_pages; |
fb3f0f51 | 1676 | int err; |
6aa8b732 | 1677 | |
c16f862d | 1678 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
1679 | if (!svm) { |
1680 | err = -ENOMEM; | |
1681 | goto out; | |
1682 | } | |
1683 | ||
1684 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
1685 | if (err) | |
1686 | goto free_svm; | |
1687 | ||
b7af4043 | 1688 | err = -ENOMEM; |
6aa8b732 | 1689 | page = alloc_page(GFP_KERNEL); |
b7af4043 | 1690 | if (!page) |
fb3f0f51 | 1691 | goto uninit; |
6aa8b732 | 1692 | |
f65c229c JR |
1693 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); |
1694 | if (!msrpm_pages) | |
b7af4043 | 1695 | goto free_page1; |
3d6368ef AG |
1696 | |
1697 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
1698 | if (!nested_msrpm_pages) | |
b7af4043 | 1699 | goto free_page2; |
f65c229c | 1700 | |
b286d5d8 AG |
1701 | hsave_page = alloc_page(GFP_KERNEL); |
1702 | if (!hsave_page) | |
b7af4043 TY |
1703 | goto free_page3; |
1704 | ||
dfa20099 SS |
1705 | err = avic_init_vcpu(svm); |
1706 | if (err) | |
1707 | goto free_page4; | |
44a95dae | 1708 | |
8221c137 SS |
1709 | /* We initialize this flag to true to make sure that the is_running |
1710 | * bit would be set the first time the vcpu is loaded. | |
1711 | */ | |
1712 | svm->avic_is_running = true; | |
1713 | ||
e6aa9abd | 1714 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 1715 | |
b7af4043 TY |
1716 | svm->msrpm = page_address(msrpm_pages); |
1717 | svm_vcpu_init_msrpm(svm->msrpm); | |
1718 | ||
e6aa9abd | 1719 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 1720 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 1721 | |
a2fa3e9f GH |
1722 | svm->vmcb = page_address(page); |
1723 | clear_page(svm->vmcb); | |
d0ec49d4 | 1724 | svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT); |
a2fa3e9f | 1725 | svm->asid_generation = 0; |
5690891b | 1726 | init_vmcb(svm); |
6aa8b732 | 1727 | |
2b036c6b BO |
1728 | svm_init_osvw(&svm->vcpu); |
1729 | ||
fb3f0f51 | 1730 | return &svm->vcpu; |
36241b8c | 1731 | |
44a95dae SS |
1732 | free_page4: |
1733 | __free_page(hsave_page); | |
b7af4043 TY |
1734 | free_page3: |
1735 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
1736 | free_page2: | |
1737 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
1738 | free_page1: | |
1739 | __free_page(page); | |
fb3f0f51 RR |
1740 | uninit: |
1741 | kvm_vcpu_uninit(&svm->vcpu); | |
1742 | free_svm: | |
a4770347 | 1743 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
1744 | out: |
1745 | return ERR_PTR(err); | |
6aa8b732 AK |
1746 | } |
1747 | ||
1748 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
1749 | { | |
a2fa3e9f GH |
1750 | struct vcpu_svm *svm = to_svm(vcpu); |
1751 | ||
d0ec49d4 | 1752 | __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT)); |
f65c229c | 1753 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
1754 | __free_page(virt_to_page(svm->nested.hsave)); |
1755 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 1756 | kvm_vcpu_uninit(vcpu); |
a4770347 | 1757 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
1758 | } |
1759 | ||
15ad7146 | 1760 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 1761 | { |
a2fa3e9f | 1762 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 1763 | int i; |
0cc5064d | 1764 | |
0cc5064d | 1765 | if (unlikely(cpu != vcpu->cpu)) { |
4b656b12 | 1766 | svm->asid_generation = 0; |
8d28fec4 | 1767 | mark_all_dirty(svm->vmcb); |
0cc5064d | 1768 | } |
94dfbdb3 | 1769 | |
82ca2d10 AK |
1770 | #ifdef CONFIG_X86_64 |
1771 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); | |
1772 | #endif | |
dacccfdd AK |
1773 | savesegment(fs, svm->host.fs); |
1774 | savesegment(gs, svm->host.gs); | |
1775 | svm->host.ldt = kvm_read_ldt(); | |
1776 | ||
94dfbdb3 | 1777 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1778 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
fbc0db76 | 1779 | |
ad721883 HZ |
1780 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
1781 | u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio; | |
1782 | if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) { | |
1783 | __this_cpu_write(current_tsc_ratio, tsc_ratio); | |
1784 | wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio); | |
1785 | } | |
fbc0db76 | 1786 | } |
46896c73 PB |
1787 | /* This assumes that the kernel never uses MSR_TSC_AUX */ |
1788 | if (static_cpu_has(X86_FEATURE_RDTSCP)) | |
1789 | wrmsrl(MSR_TSC_AUX, svm->tsc_aux); | |
8221c137 SS |
1790 | |
1791 | avic_vcpu_load(vcpu, cpu); | |
6aa8b732 AK |
1792 | } |
1793 | ||
1794 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
1795 | { | |
a2fa3e9f | 1796 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
1797 | int i; |
1798 | ||
8221c137 SS |
1799 | avic_vcpu_put(vcpu); |
1800 | ||
e1beb1d3 | 1801 | ++vcpu->stat.host_state_reload; |
dacccfdd AK |
1802 | kvm_load_ldt(svm->host.ldt); |
1803 | #ifdef CONFIG_X86_64 | |
1804 | loadsegment(fs, svm->host.fs); | |
296f781a | 1805 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase); |
893a5ab6 | 1806 | load_gs_index(svm->host.gs); |
dacccfdd | 1807 | #else |
831ca609 | 1808 | #ifdef CONFIG_X86_32_LAZY_GS |
dacccfdd | 1809 | loadsegment(gs, svm->host.gs); |
831ca609 | 1810 | #endif |
dacccfdd | 1811 | #endif |
94dfbdb3 | 1812 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1813 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1814 | } |
1815 | ||
8221c137 SS |
1816 | static void svm_vcpu_blocking(struct kvm_vcpu *vcpu) |
1817 | { | |
1818 | avic_set_running(vcpu, false); | |
1819 | } | |
1820 | ||
1821 | static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu) | |
1822 | { | |
1823 | avic_set_running(vcpu, true); | |
1824 | } | |
1825 | ||
6aa8b732 AK |
1826 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
1827 | { | |
9b611747 LP |
1828 | struct vcpu_svm *svm = to_svm(vcpu); |
1829 | unsigned long rflags = svm->vmcb->save.rflags; | |
1830 | ||
1831 | if (svm->nmi_singlestep) { | |
1832 | /* Hide our flags if they were not set by the guest */ | |
1833 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF)) | |
1834 | rflags &= ~X86_EFLAGS_TF; | |
1835 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF)) | |
1836 | rflags &= ~X86_EFLAGS_RF; | |
1837 | } | |
1838 | return rflags; | |
6aa8b732 AK |
1839 | } |
1840 | ||
1841 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
1842 | { | |
9b611747 LP |
1843 | if (to_svm(vcpu)->nmi_singlestep) |
1844 | rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); | |
1845 | ||
ae9fedc7 | 1846 | /* |
bb3541f1 | 1847 | * Any change of EFLAGS.VM is accompanied by a reload of SS |
ae9fedc7 PB |
1848 | * (caused by either a task switch or an inter-privilege IRET), |
1849 | * so we do not need to update the CPL here. | |
1850 | */ | |
a2fa3e9f | 1851 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
1852 | } |
1853 | ||
6de4f3ad AK |
1854 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
1855 | { | |
1856 | switch (reg) { | |
1857 | case VCPU_EXREG_PDPTR: | |
1858 | BUG_ON(!npt_enabled); | |
9f8fe504 | 1859 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
6de4f3ad AK |
1860 | break; |
1861 | default: | |
1862 | BUG(); | |
1863 | } | |
1864 | } | |
1865 | ||
f0b85051 AG |
1866 | static void svm_set_vintr(struct vcpu_svm *svm) |
1867 | { | |
8a05a1b8 | 1868 | set_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1869 | } |
1870 | ||
1871 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
1872 | { | |
8a05a1b8 | 1873 | clr_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1874 | } |
1875 | ||
6aa8b732 AK |
1876 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
1877 | { | |
a2fa3e9f | 1878 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
1879 | |
1880 | switch (seg) { | |
1881 | case VCPU_SREG_CS: return &save->cs; | |
1882 | case VCPU_SREG_DS: return &save->ds; | |
1883 | case VCPU_SREG_ES: return &save->es; | |
1884 | case VCPU_SREG_FS: return &save->fs; | |
1885 | case VCPU_SREG_GS: return &save->gs; | |
1886 | case VCPU_SREG_SS: return &save->ss; | |
1887 | case VCPU_SREG_TR: return &save->tr; | |
1888 | case VCPU_SREG_LDTR: return &save->ldtr; | |
1889 | } | |
1890 | BUG(); | |
8b6d44c7 | 1891 | return NULL; |
6aa8b732 AK |
1892 | } |
1893 | ||
1894 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1895 | { | |
1896 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1897 | ||
1898 | return s->base; | |
1899 | } | |
1900 | ||
1901 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
1902 | struct kvm_segment *var, int seg) | |
1903 | { | |
1904 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1905 | ||
1906 | var->base = s->base; | |
1907 | var->limit = s->limit; | |
1908 | var->selector = s->selector; | |
1909 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
1910 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
1911 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
1912 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
1913 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
1914 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
1915 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
80112c89 JM |
1916 | |
1917 | /* | |
1918 | * AMD CPUs circa 2014 track the G bit for all segments except CS. | |
1919 | * However, the SVM spec states that the G bit is not observed by the | |
1920 | * CPU, and some VMware virtual CPUs drop the G bit for all segments. | |
1921 | * So let's synthesize a legal G bit for all segments, this helps | |
1922 | * running KVM nested. It also helps cross-vendor migration, because | |
1923 | * Intel's vmentry has a check on the 'G' bit. | |
1924 | */ | |
1925 | var->g = s->limit > 0xfffff; | |
25022acc | 1926 | |
e0231715 JR |
1927 | /* |
1928 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
1929 | * for cross vendor migration purposes by "not present" |
1930 | */ | |
8eae9570 | 1931 | var->unusable = !var->present; |
19bca6ab | 1932 | |
1fbdc7a5 | 1933 | switch (seg) { |
1fbdc7a5 AP |
1934 | case VCPU_SREG_TR: |
1935 | /* | |
1936 | * Work around a bug where the busy flag in the tr selector | |
1937 | * isn't exposed | |
1938 | */ | |
c0d09828 | 1939 | var->type |= 0x2; |
1fbdc7a5 AP |
1940 | break; |
1941 | case VCPU_SREG_DS: | |
1942 | case VCPU_SREG_ES: | |
1943 | case VCPU_SREG_FS: | |
1944 | case VCPU_SREG_GS: | |
1945 | /* | |
1946 | * The accessed bit must always be set in the segment | |
1947 | * descriptor cache, although it can be cleared in the | |
1948 | * descriptor, the cached bit always remains at 1. Since | |
1949 | * Intel has a check on this, set it here to support | |
1950 | * cross-vendor migration. | |
1951 | */ | |
1952 | if (!var->unusable) | |
1953 | var->type |= 0x1; | |
1954 | break; | |
b586eb02 | 1955 | case VCPU_SREG_SS: |
e0231715 JR |
1956 | /* |
1957 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
1958 | * descriptor is left as 1, although the whole segment has |
1959 | * been made unusable. Clear it here to pass an Intel VMX | |
1960 | * entry check when cross vendor migrating. | |
1961 | */ | |
1962 | if (var->unusable) | |
1963 | var->db = 0; | |
d9c1b543 | 1964 | /* This is symmetric with svm_set_segment() */ |
33b458d2 | 1965 | var->dpl = to_svm(vcpu)->vmcb->save.cpl; |
b586eb02 | 1966 | break; |
1fbdc7a5 | 1967 | } |
6aa8b732 AK |
1968 | } |
1969 | ||
2e4d2653 IE |
1970 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
1971 | { | |
1972 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
1973 | ||
1974 | return save->cpl; | |
1975 | } | |
1976 | ||
89a27f4d | 1977 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1978 | { |
a2fa3e9f GH |
1979 | struct vcpu_svm *svm = to_svm(vcpu); |
1980 | ||
89a27f4d GN |
1981 | dt->size = svm->vmcb->save.idtr.limit; |
1982 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
1983 | } |
1984 | ||
89a27f4d | 1985 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1986 | { |
a2fa3e9f GH |
1987 | struct vcpu_svm *svm = to_svm(vcpu); |
1988 | ||
89a27f4d GN |
1989 | svm->vmcb->save.idtr.limit = dt->size; |
1990 | svm->vmcb->save.idtr.base = dt->address ; | |
17a703cb | 1991 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1992 | } |
1993 | ||
89a27f4d | 1994 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1995 | { |
a2fa3e9f GH |
1996 | struct vcpu_svm *svm = to_svm(vcpu); |
1997 | ||
89a27f4d GN |
1998 | dt->size = svm->vmcb->save.gdtr.limit; |
1999 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
2000 | } |
2001 | ||
89a27f4d | 2002 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2003 | { |
a2fa3e9f GH |
2004 | struct vcpu_svm *svm = to_svm(vcpu); |
2005 | ||
89a27f4d GN |
2006 | svm->vmcb->save.gdtr.limit = dt->size; |
2007 | svm->vmcb->save.gdtr.base = dt->address ; | |
17a703cb | 2008 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
2009 | } |
2010 | ||
e8467fda AK |
2011 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
2012 | { | |
2013 | } | |
2014 | ||
aff48baa AK |
2015 | static void svm_decache_cr3(struct kvm_vcpu *vcpu) |
2016 | { | |
2017 | } | |
2018 | ||
25c4c276 | 2019 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
2020 | { |
2021 | } | |
2022 | ||
d225157b AK |
2023 | static void update_cr0_intercept(struct vcpu_svm *svm) |
2024 | { | |
2025 | ulong gcr0 = svm->vcpu.arch.cr0; | |
2026 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
2027 | ||
bd7e5b08 PB |
2028 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) |
2029 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
d225157b | 2030 | |
dcca1a65 | 2031 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 2032 | |
bd7e5b08 | 2033 | if (gcr0 == *hcr0) { |
4ee546b4 RJ |
2034 | clr_cr_intercept(svm, INTERCEPT_CR0_READ); |
2035 | clr_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b | 2036 | } else { |
4ee546b4 RJ |
2037 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
2038 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b AK |
2039 | } |
2040 | } | |
2041 | ||
6aa8b732 AK |
2042 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
2043 | { | |
a2fa3e9f GH |
2044 | struct vcpu_svm *svm = to_svm(vcpu); |
2045 | ||
05b3e0c2 | 2046 | #ifdef CONFIG_X86_64 |
f6801dff | 2047 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 2048 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 2049 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 2050 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
2051 | } |
2052 | ||
d77c26fc | 2053 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 2054 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 2055 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
2056 | } |
2057 | } | |
2058 | #endif | |
ad312c7c | 2059 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
2060 | |
2061 | if (!npt_enabled) | |
2062 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 | 2063 | |
bcf166a9 PB |
2064 | /* |
2065 | * re-enable caching here because the QEMU bios | |
2066 | * does not do it - this results in some delay at | |
2067 | * reboot | |
2068 | */ | |
2069 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
2070 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 2071 | svm->vmcb->save.cr0 = cr0; |
dcca1a65 | 2072 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 2073 | update_cr0_intercept(svm); |
6aa8b732 AK |
2074 | } |
2075 | ||
5e1746d6 | 2076 | static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 2077 | { |
1e02ce4c | 2078 | unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE; |
e5eab0ce JR |
2079 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
2080 | ||
5e1746d6 NHE |
2081 | if (cr4 & X86_CR4_VMXE) |
2082 | return 1; | |
2083 | ||
e5eab0ce | 2084 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) |
f40f6a45 | 2085 | svm_flush_tlb(vcpu); |
6394b649 | 2086 | |
ec077263 JR |
2087 | vcpu->arch.cr4 = cr4; |
2088 | if (!npt_enabled) | |
2089 | cr4 |= X86_CR4_PAE; | |
6394b649 | 2090 | cr4 |= host_cr4_mce; |
ec077263 | 2091 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
dcca1a65 | 2092 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
5e1746d6 | 2093 | return 0; |
6aa8b732 AK |
2094 | } |
2095 | ||
2096 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
2097 | struct kvm_segment *var, int seg) | |
2098 | { | |
a2fa3e9f | 2099 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
2100 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
2101 | ||
2102 | s->base = var->base; | |
2103 | s->limit = var->limit; | |
2104 | s->selector = var->selector; | |
d9c1b543 RP |
2105 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); |
2106 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
2107 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
2108 | s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT; | |
2109 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
2110 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
2111 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
2112 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
ae9fedc7 PB |
2113 | |
2114 | /* | |
2115 | * This is always accurate, except if SYSRET returned to a segment | |
2116 | * with SS.DPL != 3. Intel does not have this quirk, and always | |
2117 | * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it | |
2118 | * would entail passing the CPL to userspace and back. | |
2119 | */ | |
2120 | if (seg == VCPU_SREG_SS) | |
d9c1b543 RP |
2121 | /* This is symmetric with svm_get_segment() */ |
2122 | svm->vmcb->save.cpl = (var->dpl & 3); | |
6aa8b732 | 2123 | |
060d0c9a | 2124 | mark_dirty(svm->vmcb, VMCB_SEG); |
6aa8b732 AK |
2125 | } |
2126 | ||
cbdb967a | 2127 | static void update_bp_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 2128 | { |
d0bfb940 JK |
2129 | struct vcpu_svm *svm = to_svm(vcpu); |
2130 | ||
18c918c5 | 2131 | clr_exception_intercept(svm, BP_VECTOR); |
44c11430 | 2132 | |
d0bfb940 | 2133 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
d0bfb940 | 2134 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
18c918c5 | 2135 | set_exception_intercept(svm, BP_VECTOR); |
d0bfb940 JK |
2136 | } else |
2137 | vcpu->guest_debug = 0; | |
44c11430 GN |
2138 | } |
2139 | ||
0fe1e009 | 2140 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 2141 | { |
0fe1e009 TH |
2142 | if (sd->next_asid > sd->max_asid) { |
2143 | ++sd->asid_generation; | |
4faefff3 | 2144 | sd->next_asid = sd->min_asid; |
a2fa3e9f | 2145 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
2146 | } |
2147 | ||
0fe1e009 TH |
2148 | svm->asid_generation = sd->asid_generation; |
2149 | svm->vmcb->control.asid = sd->next_asid++; | |
d48086d1 JR |
2150 | |
2151 | mark_dirty(svm->vmcb, VMCB_ASID); | |
6aa8b732 AK |
2152 | } |
2153 | ||
73aaf249 JK |
2154 | static u64 svm_get_dr6(struct kvm_vcpu *vcpu) |
2155 | { | |
2156 | return to_svm(vcpu)->vmcb->save.dr6; | |
2157 | } | |
2158 | ||
2159 | static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value) | |
2160 | { | |
2161 | struct vcpu_svm *svm = to_svm(vcpu); | |
2162 | ||
2163 | svm->vmcb->save.dr6 = value; | |
2164 | mark_dirty(svm->vmcb, VMCB_DR); | |
2165 | } | |
2166 | ||
facb0139 PB |
2167 | static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
2168 | { | |
2169 | struct vcpu_svm *svm = to_svm(vcpu); | |
2170 | ||
2171 | get_debugreg(vcpu->arch.db[0], 0); | |
2172 | get_debugreg(vcpu->arch.db[1], 1); | |
2173 | get_debugreg(vcpu->arch.db[2], 2); | |
2174 | get_debugreg(vcpu->arch.db[3], 3); | |
2175 | vcpu->arch.dr6 = svm_get_dr6(vcpu); | |
2176 | vcpu->arch.dr7 = svm->vmcb->save.dr7; | |
2177 | ||
2178 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
2179 | set_dr_intercepts(svm); | |
2180 | } | |
2181 | ||
020df079 | 2182 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 2183 | { |
42dbaa5a | 2184 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 2185 | |
020df079 | 2186 | svm->vmcb->save.dr7 = value; |
72214b96 | 2187 | mark_dirty(svm->vmcb, VMCB_DR); |
6aa8b732 AK |
2188 | } |
2189 | ||
851ba692 | 2190 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 2191 | { |
631bc487 | 2192 | u64 fault_address = svm->vmcb->control.exit_info_2; |
1261bfa3 | 2193 | u64 error_code = svm->vmcb->control.exit_info_1; |
6aa8b732 | 2194 | |
1261bfa3 | 2195 | return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address, |
dc25e89e | 2196 | svm->vmcb->control.insn_bytes, |
d0006530 PB |
2197 | svm->vmcb->control.insn_len); |
2198 | } | |
2199 | ||
2200 | static int npf_interception(struct vcpu_svm *svm) | |
2201 | { | |
2202 | u64 fault_address = svm->vmcb->control.exit_info_2; | |
2203 | u64 error_code = svm->vmcb->control.exit_info_1; | |
2204 | ||
2205 | trace_kvm_page_fault(fault_address, error_code); | |
2206 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code, | |
2207 | svm->vmcb->control.insn_bytes, | |
2208 | svm->vmcb->control.insn_len); | |
6aa8b732 AK |
2209 | } |
2210 | ||
851ba692 | 2211 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 2212 | { |
851ba692 AK |
2213 | struct kvm_run *kvm_run = svm->vcpu.run; |
2214 | ||
d0bfb940 | 2215 | if (!(svm->vcpu.guest_debug & |
44c11430 | 2216 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 2217 | !svm->nmi_singlestep) { |
d0bfb940 JK |
2218 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
2219 | return 1; | |
2220 | } | |
44c11430 | 2221 | |
6be7d306 | 2222 | if (svm->nmi_singlestep) { |
4aebd0e9 | 2223 | disable_nmi_singlestep(svm); |
44c11430 GN |
2224 | } |
2225 | ||
2226 | if (svm->vcpu.guest_debug & | |
e0231715 | 2227 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
2228 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
2229 | kvm_run->debug.arch.pc = | |
2230 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
2231 | kvm_run->debug.arch.exception = DB_VECTOR; | |
2232 | return 0; | |
2233 | } | |
2234 | ||
2235 | return 1; | |
d0bfb940 JK |
2236 | } |
2237 | ||
851ba692 | 2238 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 2239 | { |
851ba692 AK |
2240 | struct kvm_run *kvm_run = svm->vcpu.run; |
2241 | ||
d0bfb940 JK |
2242 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
2243 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
2244 | kvm_run->debug.arch.exception = BP_VECTOR; | |
2245 | return 0; | |
2246 | } | |
2247 | ||
851ba692 | 2248 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
2249 | { |
2250 | int er; | |
2251 | ||
51d8b661 | 2252 | er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 2253 | if (er != EMULATE_DONE) |
7ee5d940 | 2254 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
2255 | return 1; |
2256 | } | |
2257 | ||
54a20552 EN |
2258 | static int ac_interception(struct vcpu_svm *svm) |
2259 | { | |
2260 | kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0); | |
2261 | return 1; | |
2262 | } | |
2263 | ||
67ec6607 JR |
2264 | static bool is_erratum_383(void) |
2265 | { | |
2266 | int err, i; | |
2267 | u64 value; | |
2268 | ||
2269 | if (!erratum_383_found) | |
2270 | return false; | |
2271 | ||
2272 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
2273 | if (err) | |
2274 | return false; | |
2275 | ||
2276 | /* Bit 62 may or may not be set for this mce */ | |
2277 | value &= ~(1ULL << 62); | |
2278 | ||
2279 | if (value != 0xb600000000010015ULL) | |
2280 | return false; | |
2281 | ||
2282 | /* Clear MCi_STATUS registers */ | |
2283 | for (i = 0; i < 6; ++i) | |
2284 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
2285 | ||
2286 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
2287 | if (!err) { | |
2288 | u32 low, high; | |
2289 | ||
2290 | value &= ~(1ULL << 2); | |
2291 | low = lower_32_bits(value); | |
2292 | high = upper_32_bits(value); | |
2293 | ||
2294 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
2295 | } | |
2296 | ||
2297 | /* Flush tlb to evict multi-match entries */ | |
2298 | __flush_tlb_all(); | |
2299 | ||
2300 | return true; | |
2301 | } | |
2302 | ||
fe5913e4 | 2303 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 2304 | { |
67ec6607 JR |
2305 | if (is_erratum_383()) { |
2306 | /* | |
2307 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
2308 | * guest. | |
2309 | */ | |
2310 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
2311 | ||
a8eeb04a | 2312 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
2313 | |
2314 | return; | |
2315 | } | |
2316 | ||
53371b50 JR |
2317 | /* |
2318 | * On an #MC intercept the MCE handler is not called automatically in | |
2319 | * the host. So do it by hand here. | |
2320 | */ | |
2321 | asm volatile ( | |
2322 | "int $0x12\n"); | |
2323 | /* not sure if we ever come back to this point */ | |
2324 | ||
fe5913e4 JR |
2325 | return; |
2326 | } | |
2327 | ||
2328 | static int mc_interception(struct vcpu_svm *svm) | |
2329 | { | |
53371b50 JR |
2330 | return 1; |
2331 | } | |
2332 | ||
851ba692 | 2333 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 2334 | { |
851ba692 AK |
2335 | struct kvm_run *kvm_run = svm->vcpu.run; |
2336 | ||
46fe4ddd JR |
2337 | /* |
2338 | * VMCB is undefined after a SHUTDOWN intercept | |
2339 | * so reinitialize it. | |
2340 | */ | |
a2fa3e9f | 2341 | clear_page(svm->vmcb); |
5690891b | 2342 | init_vmcb(svm); |
46fe4ddd JR |
2343 | |
2344 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
2345 | return 0; | |
2346 | } | |
2347 | ||
851ba692 | 2348 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 2349 | { |
cf8f70bf | 2350 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 2351 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
b742c1e6 | 2352 | int size, in, string, ret; |
039576c0 | 2353 | unsigned port; |
6aa8b732 | 2354 | |
e756fc62 | 2355 | ++svm->vcpu.stat.io_exits; |
e70669ab | 2356 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 2357 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
8370c3d0 | 2358 | if (string) |
51d8b661 | 2359 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
cf8f70bf | 2360 | |
039576c0 AK |
2361 | port = io_info >> 16; |
2362 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 2363 | svm->next_rip = svm->vmcb->control.exit_info_2; |
b742c1e6 | 2364 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
cf8f70bf | 2365 | |
b742c1e6 LP |
2366 | /* |
2367 | * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered | |
2368 | * KVM_EXIT_DEBUG here. | |
2369 | */ | |
2370 | if (in) | |
2371 | return kvm_fast_pio_in(vcpu, size, port) && ret; | |
2372 | else | |
2373 | return kvm_fast_pio_out(vcpu, size, port) && ret; | |
6aa8b732 AK |
2374 | } |
2375 | ||
851ba692 | 2376 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
2377 | { |
2378 | return 1; | |
2379 | } | |
2380 | ||
851ba692 | 2381 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
2382 | { |
2383 | ++svm->vcpu.stat.irq_exits; | |
2384 | return 1; | |
2385 | } | |
2386 | ||
851ba692 | 2387 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
2388 | { |
2389 | return 1; | |
2390 | } | |
2391 | ||
851ba692 | 2392 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 2393 | { |
5fdbf976 | 2394 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 | 2395 | return kvm_emulate_halt(&svm->vcpu); |
6aa8b732 AK |
2396 | } |
2397 | ||
851ba692 | 2398 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 2399 | { |
5fdbf976 | 2400 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
0d9c055e | 2401 | return kvm_emulate_hypercall(&svm->vcpu); |
02e235bc AK |
2402 | } |
2403 | ||
5bd2edc3 JR |
2404 | static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) |
2405 | { | |
2406 | struct vcpu_svm *svm = to_svm(vcpu); | |
2407 | ||
2408 | return svm->nested.nested_cr3; | |
2409 | } | |
2410 | ||
e4e517b4 AK |
2411 | static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index) |
2412 | { | |
2413 | struct vcpu_svm *svm = to_svm(vcpu); | |
2414 | u64 cr3 = svm->nested.nested_cr3; | |
2415 | u64 pdpte; | |
2416 | int ret; | |
2417 | ||
d0ec49d4 | 2418 | ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte, |
54bf36aa | 2419 | offset_in_page(cr3) + index * 8, 8); |
e4e517b4 AK |
2420 | if (ret) |
2421 | return 0; | |
2422 | return pdpte; | |
2423 | } | |
2424 | ||
5bd2edc3 JR |
2425 | static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu, |
2426 | unsigned long root) | |
2427 | { | |
2428 | struct vcpu_svm *svm = to_svm(vcpu); | |
2429 | ||
d0ec49d4 | 2430 | svm->vmcb->control.nested_cr3 = __sme_set(root); |
b2747166 | 2431 | mark_dirty(svm->vmcb, VMCB_NPT); |
f40f6a45 | 2432 | svm_flush_tlb(vcpu); |
5bd2edc3 JR |
2433 | } |
2434 | ||
6389ee94 AK |
2435 | static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, |
2436 | struct x86_exception *fault) | |
5bd2edc3 JR |
2437 | { |
2438 | struct vcpu_svm *svm = to_svm(vcpu); | |
2439 | ||
5e352519 PB |
2440 | if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) { |
2441 | /* | |
2442 | * TODO: track the cause of the nested page fault, and | |
2443 | * correctly fill in the high bits of exit_info_1. | |
2444 | */ | |
2445 | svm->vmcb->control.exit_code = SVM_EXIT_NPF; | |
2446 | svm->vmcb->control.exit_code_hi = 0; | |
2447 | svm->vmcb->control.exit_info_1 = (1ULL << 32); | |
2448 | svm->vmcb->control.exit_info_2 = fault->address; | |
2449 | } | |
2450 | ||
2451 | svm->vmcb->control.exit_info_1 &= ~0xffffffffULL; | |
2452 | svm->vmcb->control.exit_info_1 |= fault->error_code; | |
2453 | ||
2454 | /* | |
2455 | * The present bit is always zero for page structure faults on real | |
2456 | * hardware. | |
2457 | */ | |
2458 | if (svm->vmcb->control.exit_info_1 & (2ULL << 32)) | |
2459 | svm->vmcb->control.exit_info_1 &= ~1; | |
5bd2edc3 JR |
2460 | |
2461 | nested_svm_vmexit(svm); | |
2462 | } | |
2463 | ||
8a3c1a33 | 2464 | static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) |
4b16184c | 2465 | { |
ad896af0 PB |
2466 | WARN_ON(mmu_is_nested(vcpu)); |
2467 | kvm_init_shadow_mmu(vcpu); | |
4b16184c JR |
2468 | vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3; |
2469 | vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3; | |
e4e517b4 | 2470 | vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr; |
4b16184c | 2471 | vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit; |
855feb67 | 2472 | vcpu->arch.mmu.shadow_root_level = get_npt_level(vcpu); |
c258b62b | 2473 | reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu); |
4b16184c | 2474 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; |
4b16184c JR |
2475 | } |
2476 | ||
2477 | static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
2478 | { | |
2479 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
2480 | } | |
2481 | ||
c0725420 AG |
2482 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
2483 | { | |
e9196ceb DC |
2484 | if (!(svm->vcpu.arch.efer & EFER_SVME) || |
2485 | !is_paging(&svm->vcpu)) { | |
c0725420 AG |
2486 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
2487 | return 1; | |
2488 | } | |
2489 | ||
2490 | if (svm->vmcb->save.cpl) { | |
2491 | kvm_inject_gp(&svm->vcpu, 0); | |
2492 | return 1; | |
2493 | } | |
2494 | ||
e9196ceb | 2495 | return 0; |
c0725420 AG |
2496 | } |
2497 | ||
cf74a78b AG |
2498 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
2499 | bool has_error_code, u32 error_code) | |
2500 | { | |
b8e88bc8 JR |
2501 | int vmexit; |
2502 | ||
2030753d | 2503 | if (!is_guest_mode(&svm->vcpu)) |
0295ad7d | 2504 | return 0; |
cf74a78b | 2505 | |
adfe20fb WL |
2506 | vmexit = nested_svm_intercept(svm); |
2507 | if (vmexit != NESTED_EXIT_DONE) | |
2508 | return 0; | |
2509 | ||
0295ad7d JR |
2510 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
2511 | svm->vmcb->control.exit_code_hi = 0; | |
2512 | svm->vmcb->control.exit_info_1 = error_code; | |
b96fb439 PB |
2513 | |
2514 | /* | |
2515 | * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception. | |
2516 | * The fix is to add the ancillary datum (CR2 or DR6) to structs | |
2517 | * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be | |
2518 | * written only when inject_pending_event runs (DR6 would written here | |
2519 | * too). This should be conditional on a new capability---if the | |
2520 | * capability is disabled, kvm_multiple_exception would write the | |
2521 | * ancillary information to CR2 or DR6, for backwards ABI-compatibility. | |
2522 | */ | |
adfe20fb WL |
2523 | if (svm->vcpu.arch.exception.nested_apf) |
2524 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token; | |
2525 | else | |
2526 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
b8e88bc8 | 2527 | |
adfe20fb | 2528 | svm->nested.exit_required = true; |
b8e88bc8 | 2529 | return vmexit; |
cf74a78b AG |
2530 | } |
2531 | ||
8fe54654 JR |
2532 | /* This function returns true if it is save to enable the irq window */ |
2533 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 2534 | { |
2030753d | 2535 | if (!is_guest_mode(&svm->vcpu)) |
8fe54654 | 2536 | return true; |
cf74a78b | 2537 | |
26666957 | 2538 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 2539 | return true; |
cf74a78b | 2540 | |
26666957 | 2541 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 2542 | return false; |
cf74a78b | 2543 | |
a0a07cd2 GN |
2544 | /* |
2545 | * if vmexit was already requested (by intercepted exception | |
2546 | * for instance) do not overwrite it with "external interrupt" | |
2547 | * vmexit. | |
2548 | */ | |
2549 | if (svm->nested.exit_required) | |
2550 | return false; | |
2551 | ||
197717d5 JR |
2552 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
2553 | svm->vmcb->control.exit_info_1 = 0; | |
2554 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 2555 | |
cd3ff653 JR |
2556 | if (svm->nested.intercept & 1ULL) { |
2557 | /* | |
2558 | * The #vmexit can't be emulated here directly because this | |
c5ec2e56 | 2559 | * code path runs with irqs and preemption disabled. A |
cd3ff653 JR |
2560 | * #vmexit emulation might sleep. Only signal request for |
2561 | * the #vmexit here. | |
2562 | */ | |
2563 | svm->nested.exit_required = true; | |
236649de | 2564 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 2565 | return false; |
cf74a78b AG |
2566 | } |
2567 | ||
8fe54654 | 2568 | return true; |
cf74a78b AG |
2569 | } |
2570 | ||
887f500c JR |
2571 | /* This function returns true if it is save to enable the nmi window */ |
2572 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
2573 | { | |
2030753d | 2574 | if (!is_guest_mode(&svm->vcpu)) |
887f500c JR |
2575 | return true; |
2576 | ||
2577 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
2578 | return true; | |
2579 | ||
2580 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
2581 | svm->nested.exit_required = true; | |
2582 | ||
2583 | return false; | |
cf74a78b AG |
2584 | } |
2585 | ||
7597f129 | 2586 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) |
34f80cfa JR |
2587 | { |
2588 | struct page *page; | |
2589 | ||
6c3bd3d7 JR |
2590 | might_sleep(); |
2591 | ||
54bf36aa | 2592 | page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT); |
34f80cfa JR |
2593 | if (is_error_page(page)) |
2594 | goto error; | |
2595 | ||
7597f129 JR |
2596 | *_page = page; |
2597 | ||
2598 | return kmap(page); | |
34f80cfa JR |
2599 | |
2600 | error: | |
34f80cfa JR |
2601 | kvm_inject_gp(&svm->vcpu, 0); |
2602 | ||
2603 | return NULL; | |
2604 | } | |
2605 | ||
7597f129 | 2606 | static void nested_svm_unmap(struct page *page) |
34f80cfa | 2607 | { |
7597f129 | 2608 | kunmap(page); |
34f80cfa JR |
2609 | kvm_release_page_dirty(page); |
2610 | } | |
34f80cfa | 2611 | |
ce2ac085 JR |
2612 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
2613 | { | |
9bf41833 JK |
2614 | unsigned port, size, iopm_len; |
2615 | u16 val, mask; | |
2616 | u8 start_bit; | |
ce2ac085 | 2617 | u64 gpa; |
34f80cfa | 2618 | |
ce2ac085 JR |
2619 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
2620 | return NESTED_EXIT_HOST; | |
34f80cfa | 2621 | |
ce2ac085 | 2622 | port = svm->vmcb->control.exit_info_1 >> 16; |
9bf41833 JK |
2623 | size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >> |
2624 | SVM_IOIO_SIZE_SHIFT; | |
ce2ac085 | 2625 | gpa = svm->nested.vmcb_iopm + (port / 8); |
9bf41833 JK |
2626 | start_bit = port % 8; |
2627 | iopm_len = (start_bit + size > 8) ? 2 : 1; | |
2628 | mask = (0xf >> (4 - size)) << start_bit; | |
2629 | val = 0; | |
ce2ac085 | 2630 | |
54bf36aa | 2631 | if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len)) |
9bf41833 | 2632 | return NESTED_EXIT_DONE; |
ce2ac085 | 2633 | |
9bf41833 | 2634 | return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
34f80cfa JR |
2635 | } |
2636 | ||
d2477826 | 2637 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 2638 | { |
0d6b3537 JR |
2639 | u32 offset, msr, value; |
2640 | int write, mask; | |
4c2161ae | 2641 | |
3d62d9aa | 2642 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 2643 | return NESTED_EXIT_HOST; |
3d62d9aa | 2644 | |
0d6b3537 JR |
2645 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
2646 | offset = svm_msrpm_offset(msr); | |
2647 | write = svm->vmcb->control.exit_info_1 & 1; | |
2648 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 2649 | |
0d6b3537 JR |
2650 | if (offset == MSR_INVALID) |
2651 | return NESTED_EXIT_DONE; | |
4c2161ae | 2652 | |
0d6b3537 JR |
2653 | /* Offset is in 32 bit units but need in 8 bit units */ |
2654 | offset *= 4; | |
4c2161ae | 2655 | |
54bf36aa | 2656 | if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4)) |
0d6b3537 | 2657 | return NESTED_EXIT_DONE; |
3d62d9aa | 2658 | |
0d6b3537 | 2659 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
2660 | } |
2661 | ||
ab2f4d73 LP |
2662 | /* DB exceptions for our internal use must not cause vmexit */ |
2663 | static int nested_svm_intercept_db(struct vcpu_svm *svm) | |
2664 | { | |
2665 | unsigned long dr6; | |
2666 | ||
2667 | /* if we're not singlestepping, it's not ours */ | |
2668 | if (!svm->nmi_singlestep) | |
2669 | return NESTED_EXIT_DONE; | |
2670 | ||
2671 | /* if it's not a singlestep exception, it's not ours */ | |
2672 | if (kvm_get_dr(&svm->vcpu, 6, &dr6)) | |
2673 | return NESTED_EXIT_DONE; | |
2674 | if (!(dr6 & DR6_BS)) | |
2675 | return NESTED_EXIT_DONE; | |
2676 | ||
2677 | /* if the guest is singlestepping, it should get the vmexit */ | |
2678 | if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) { | |
2679 | disable_nmi_singlestep(svm); | |
2680 | return NESTED_EXIT_DONE; | |
2681 | } | |
2682 | ||
2683 | /* it's ours, the nested hypervisor must not see this one */ | |
2684 | return NESTED_EXIT_HOST; | |
2685 | } | |
2686 | ||
410e4d57 | 2687 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 2688 | { |
cf74a78b | 2689 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 2690 | |
410e4d57 JR |
2691 | switch (exit_code) { |
2692 | case SVM_EXIT_INTR: | |
2693 | case SVM_EXIT_NMI: | |
ff47a49b | 2694 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 2695 | return NESTED_EXIT_HOST; |
410e4d57 | 2696 | case SVM_EXIT_NPF: |
e0231715 | 2697 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
2698 | if (npt_enabled) |
2699 | return NESTED_EXIT_HOST; | |
2700 | break; | |
410e4d57 | 2701 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
631bc487 | 2702 | /* When we're shadowing, trap PFs, but not async PF */ |
1261bfa3 | 2703 | if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0) |
410e4d57 JR |
2704 | return NESTED_EXIT_HOST; |
2705 | break; | |
2706 | default: | |
2707 | break; | |
cf74a78b AG |
2708 | } |
2709 | ||
410e4d57 JR |
2710 | return NESTED_EXIT_CONTINUE; |
2711 | } | |
2712 | ||
2713 | /* | |
2714 | * If this function returns true, this #vmexit was already handled | |
2715 | */ | |
b8e88bc8 | 2716 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
2717 | { |
2718 | u32 exit_code = svm->vmcb->control.exit_code; | |
2719 | int vmexit = NESTED_EXIT_HOST; | |
2720 | ||
cf74a78b | 2721 | switch (exit_code) { |
9c4e40b9 | 2722 | case SVM_EXIT_MSR: |
3d62d9aa | 2723 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 2724 | break; |
ce2ac085 JR |
2725 | case SVM_EXIT_IOIO: |
2726 | vmexit = nested_svm_intercept_ioio(svm); | |
2727 | break; | |
4ee546b4 RJ |
2728 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: { |
2729 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0); | |
2730 | if (svm->nested.intercept_cr & bit) | |
410e4d57 | 2731 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2732 | break; |
2733 | } | |
3aed041a JR |
2734 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: { |
2735 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0); | |
2736 | if (svm->nested.intercept_dr & bit) | |
410e4d57 | 2737 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2738 | break; |
2739 | } | |
2740 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
2741 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
ab2f4d73 LP |
2742 | if (svm->nested.intercept_exceptions & excp_bits) { |
2743 | if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR) | |
2744 | vmexit = nested_svm_intercept_db(svm); | |
2745 | else | |
2746 | vmexit = NESTED_EXIT_DONE; | |
2747 | } | |
631bc487 GN |
2748 | /* async page fault always cause vmexit */ |
2749 | else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) && | |
adfe20fb | 2750 | svm->vcpu.arch.exception.nested_apf != 0) |
631bc487 | 2751 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2752 | break; |
2753 | } | |
228070b1 JR |
2754 | case SVM_EXIT_ERR: { |
2755 | vmexit = NESTED_EXIT_DONE; | |
2756 | break; | |
2757 | } | |
cf74a78b AG |
2758 | default: { |
2759 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 2760 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 2761 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2762 | } |
2763 | } | |
2764 | ||
b8e88bc8 JR |
2765 | return vmexit; |
2766 | } | |
2767 | ||
2768 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
2769 | { | |
2770 | int vmexit; | |
2771 | ||
2772 | vmexit = nested_svm_intercept(svm); | |
2773 | ||
2774 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 2775 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
2776 | |
2777 | return vmexit; | |
cf74a78b AG |
2778 | } |
2779 | ||
0460a979 JR |
2780 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
2781 | { | |
2782 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
2783 | struct vmcb_control_area *from = &from_vmcb->control; | |
2784 | ||
4ee546b4 | 2785 | dst->intercept_cr = from->intercept_cr; |
3aed041a | 2786 | dst->intercept_dr = from->intercept_dr; |
0460a979 JR |
2787 | dst->intercept_exceptions = from->intercept_exceptions; |
2788 | dst->intercept = from->intercept; | |
2789 | dst->iopm_base_pa = from->iopm_base_pa; | |
2790 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
2791 | dst->tsc_offset = from->tsc_offset; | |
2792 | dst->asid = from->asid; | |
2793 | dst->tlb_ctl = from->tlb_ctl; | |
2794 | dst->int_ctl = from->int_ctl; | |
2795 | dst->int_vector = from->int_vector; | |
2796 | dst->int_state = from->int_state; | |
2797 | dst->exit_code = from->exit_code; | |
2798 | dst->exit_code_hi = from->exit_code_hi; | |
2799 | dst->exit_info_1 = from->exit_info_1; | |
2800 | dst->exit_info_2 = from->exit_info_2; | |
2801 | dst->exit_int_info = from->exit_int_info; | |
2802 | dst->exit_int_info_err = from->exit_int_info_err; | |
2803 | dst->nested_ctl = from->nested_ctl; | |
2804 | dst->event_inj = from->event_inj; | |
2805 | dst->event_inj_err = from->event_inj_err; | |
2806 | dst->nested_cr3 = from->nested_cr3; | |
0dc92119 | 2807 | dst->virt_ext = from->virt_ext; |
0460a979 JR |
2808 | } |
2809 | ||
34f80cfa | 2810 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 2811 | { |
34f80cfa | 2812 | struct vmcb *nested_vmcb; |
e6aa9abd | 2813 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 2814 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2815 | struct page *page; |
cf74a78b | 2816 | |
17897f36 JR |
2817 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
2818 | vmcb->control.exit_info_1, | |
2819 | vmcb->control.exit_info_2, | |
2820 | vmcb->control.exit_int_info, | |
e097e5ff SH |
2821 | vmcb->control.exit_int_info_err, |
2822 | KVM_ISA_SVM); | |
17897f36 | 2823 | |
7597f129 | 2824 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); |
34f80cfa JR |
2825 | if (!nested_vmcb) |
2826 | return 1; | |
2827 | ||
2030753d JR |
2828 | /* Exit Guest-Mode */ |
2829 | leave_guest_mode(&svm->vcpu); | |
06fc7772 JR |
2830 | svm->nested.vmcb = 0; |
2831 | ||
cf74a78b | 2832 | /* Give the current vmcb to the guest */ |
33740e40 JR |
2833 | disable_gif(svm); |
2834 | ||
2835 | nested_vmcb->save.es = vmcb->save.es; | |
2836 | nested_vmcb->save.cs = vmcb->save.cs; | |
2837 | nested_vmcb->save.ss = vmcb->save.ss; | |
2838 | nested_vmcb->save.ds = vmcb->save.ds; | |
2839 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
2840 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
3f6a9d16 | 2841 | nested_vmcb->save.efer = svm->vcpu.arch.efer; |
cdbbdc12 | 2842 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
9f8fe504 | 2843 | nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu); |
33740e40 | 2844 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 2845 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2846 | nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu); |
33740e40 JR |
2847 | nested_vmcb->save.rip = vmcb->save.rip; |
2848 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
2849 | nested_vmcb->save.rax = vmcb->save.rax; | |
2850 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
2851 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
2852 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
2853 | ||
2854 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
2855 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
2856 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
2857 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
2858 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
2859 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
2860 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
2861 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
2862 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
6092d3d3 JR |
2863 | |
2864 | if (svm->nrips_enabled) | |
2865 | nested_vmcb->control.next_rip = vmcb->control.next_rip; | |
8d23c466 AG |
2866 | |
2867 | /* | |
2868 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
2869 | * to make sure that we do not lose injected events. So check event_inj | |
2870 | * here and copy it to exit_int_info if it is valid. | |
2871 | * Exit_int_info and event_inj can't be both valid because the case | |
2872 | * below only happens on a VMRUN instruction intercept which has | |
2873 | * no valid exit_int_info set. | |
2874 | */ | |
2875 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
2876 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
2877 | ||
2878 | nc->exit_int_info = vmcb->control.event_inj; | |
2879 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
2880 | } | |
2881 | ||
33740e40 JR |
2882 | nested_vmcb->control.tlb_ctl = 0; |
2883 | nested_vmcb->control.event_inj = 0; | |
2884 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
2885 | |
2886 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
2887 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
2888 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
2889 | ||
cf74a78b | 2890 | /* Restore the original control entries */ |
0460a979 | 2891 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 2892 | |
219b65dc AG |
2893 | kvm_clear_exception_queue(&svm->vcpu); |
2894 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b | 2895 | |
4b16184c JR |
2896 | svm->nested.nested_cr3 = 0; |
2897 | ||
cf74a78b AG |
2898 | /* Restore selected save entries */ |
2899 | svm->vmcb->save.es = hsave->save.es; | |
2900 | svm->vmcb->save.cs = hsave->save.cs; | |
2901 | svm->vmcb->save.ss = hsave->save.ss; | |
2902 | svm->vmcb->save.ds = hsave->save.ds; | |
2903 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
2904 | svm->vmcb->save.idtr = hsave->save.idtr; | |
f6e78475 | 2905 | kvm_set_rflags(&svm->vcpu, hsave->save.rflags); |
cf74a78b AG |
2906 | svm_set_efer(&svm->vcpu, hsave->save.efer); |
2907 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
2908 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
2909 | if (npt_enabled) { | |
2910 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
2911 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
2912 | } else { | |
2390218b | 2913 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b AG |
2914 | } |
2915 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
2916 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
2917 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
2918 | svm->vmcb->save.dr7 = 0; | |
2919 | svm->vmcb->save.cpl = 0; | |
2920 | svm->vmcb->control.exit_int_info = 0; | |
2921 | ||
8d28fec4 RJ |
2922 | mark_all_dirty(svm->vmcb); |
2923 | ||
7597f129 | 2924 | nested_svm_unmap(page); |
cf74a78b | 2925 | |
4b16184c | 2926 | nested_svm_uninit_mmu_context(&svm->vcpu); |
cf74a78b AG |
2927 | kvm_mmu_reset_context(&svm->vcpu); |
2928 | kvm_mmu_load(&svm->vcpu); | |
2929 | ||
2930 | return 0; | |
2931 | } | |
3d6368ef | 2932 | |
9738b2c9 | 2933 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 2934 | { |
323c3d80 JR |
2935 | /* |
2936 | * This function merges the msr permission bitmaps of kvm and the | |
c5ec2e56 | 2937 | * nested vmcb. It is optimized in that it only merges the parts where |
323c3d80 JR |
2938 | * the kvm msr permission bitmap may contain zero bits |
2939 | */ | |
3d6368ef | 2940 | int i; |
9738b2c9 | 2941 | |
323c3d80 JR |
2942 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
2943 | return true; | |
9738b2c9 | 2944 | |
323c3d80 JR |
2945 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
2946 | u32 value, p; | |
2947 | u64 offset; | |
9738b2c9 | 2948 | |
323c3d80 JR |
2949 | if (msrpm_offsets[i] == 0xffffffff) |
2950 | break; | |
3d6368ef | 2951 | |
0d6b3537 JR |
2952 | p = msrpm_offsets[i]; |
2953 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 | 2954 | |
54bf36aa | 2955 | if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4)) |
323c3d80 JR |
2956 | return false; |
2957 | ||
2958 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
2959 | } | |
3d6368ef | 2960 | |
d0ec49d4 | 2961 | svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm)); |
9738b2c9 JR |
2962 | |
2963 | return true; | |
3d6368ef AG |
2964 | } |
2965 | ||
52c65a30 JR |
2966 | static bool nested_vmcb_checks(struct vmcb *vmcb) |
2967 | { | |
2968 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
2969 | return false; | |
2970 | ||
dbe77584 JR |
2971 | if (vmcb->control.asid == 0) |
2972 | return false; | |
2973 | ||
cea3a19b TL |
2974 | if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) && |
2975 | !npt_enabled) | |
4b16184c JR |
2976 | return false; |
2977 | ||
52c65a30 JR |
2978 | return true; |
2979 | } | |
2980 | ||
c2634065 LP |
2981 | static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa, |
2982 | struct vmcb *nested_vmcb, struct page *page) | |
3d6368ef | 2983 | { |
f6e78475 | 2984 | if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF) |
3d6368ef AG |
2985 | svm->vcpu.arch.hflags |= HF_HIF_MASK; |
2986 | else | |
2987 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
2988 | ||
cea3a19b | 2989 | if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) { |
4b16184c JR |
2990 | kvm_mmu_unload(&svm->vcpu); |
2991 | svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; | |
2992 | nested_svm_init_mmu_context(&svm->vcpu); | |
2993 | } | |
2994 | ||
3d6368ef AG |
2995 | /* Load the nested guest state */ |
2996 | svm->vmcb->save.es = nested_vmcb->save.es; | |
2997 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
2998 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
2999 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
3000 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
3001 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
f6e78475 | 3002 | kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags); |
3d6368ef AG |
3003 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); |
3004 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
3005 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
3006 | if (npt_enabled) { | |
3007 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
3008 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 3009 | } else |
2390218b | 3010 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
3011 | |
3012 | /* Guest paging mode is active - reset mmu */ | |
3013 | kvm_mmu_reset_context(&svm->vcpu); | |
3014 | ||
defbba56 | 3015 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
3016 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
3017 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
3018 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
e0231715 | 3019 | |
3d6368ef AG |
3020 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
3021 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
3022 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
3023 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
3024 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
3025 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
3026 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
3027 | ||
f7138538 | 3028 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 3029 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 3030 | |
aad42c64 | 3031 | /* cache intercepts */ |
4ee546b4 | 3032 | svm->nested.intercept_cr = nested_vmcb->control.intercept_cr; |
3aed041a | 3033 | svm->nested.intercept_dr = nested_vmcb->control.intercept_dr; |
aad42c64 JR |
3034 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; |
3035 | svm->nested.intercept = nested_vmcb->control.intercept; | |
3036 | ||
f40f6a45 | 3037 | svm_flush_tlb(&svm->vcpu); |
3d6368ef | 3038 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
3039 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
3040 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
3041 | else | |
3042 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
3043 | ||
88ab24ad JR |
3044 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
3045 | /* We only want the cr8 intercept bits of the guest */ | |
4ee546b4 RJ |
3046 | clr_cr_intercept(svm, INTERCEPT_CR8_READ); |
3047 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
88ab24ad JR |
3048 | } |
3049 | ||
0d945bd9 | 3050 | /* We don't want to see VMMCALLs from a nested guest */ |
8a05a1b8 | 3051 | clr_intercept(svm, INTERCEPT_VMMCALL); |
0d945bd9 | 3052 | |
0dc92119 | 3053 | svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext; |
3d6368ef AG |
3054 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
3055 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
3056 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
3057 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
3058 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
3059 | ||
7597f129 | 3060 | nested_svm_unmap(page); |
9738b2c9 | 3061 | |
2030753d JR |
3062 | /* Enter Guest-Mode */ |
3063 | enter_guest_mode(&svm->vcpu); | |
3064 | ||
384c6368 JR |
3065 | /* |
3066 | * Merge guest and host intercepts - must be called with vcpu in | |
3067 | * guest-mode to take affect here | |
3068 | */ | |
3069 | recalc_intercepts(svm); | |
3070 | ||
06fc7772 | 3071 | svm->nested.vmcb = vmcb_gpa; |
9738b2c9 | 3072 | |
2af9194d | 3073 | enable_gif(svm); |
3d6368ef | 3074 | |
8d28fec4 | 3075 | mark_all_dirty(svm->vmcb); |
c2634065 LP |
3076 | } |
3077 | ||
3078 | static bool nested_svm_vmrun(struct vcpu_svm *svm) | |
3079 | { | |
3080 | struct vmcb *nested_vmcb; | |
3081 | struct vmcb *hsave = svm->nested.hsave; | |
3082 | struct vmcb *vmcb = svm->vmcb; | |
3083 | struct page *page; | |
3084 | u64 vmcb_gpa; | |
3085 | ||
3086 | vmcb_gpa = svm->vmcb->save.rax; | |
3087 | ||
3088 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); | |
3089 | if (!nested_vmcb) | |
3090 | return false; | |
3091 | ||
3092 | if (!nested_vmcb_checks(nested_vmcb)) { | |
3093 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
3094 | nested_vmcb->control.exit_code_hi = 0; | |
3095 | nested_vmcb->control.exit_info_1 = 0; | |
3096 | nested_vmcb->control.exit_info_2 = 0; | |
3097 | ||
3098 | nested_svm_unmap(page); | |
3099 | ||
3100 | return false; | |
3101 | } | |
3102 | ||
3103 | trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa, | |
3104 | nested_vmcb->save.rip, | |
3105 | nested_vmcb->control.int_ctl, | |
3106 | nested_vmcb->control.event_inj, | |
3107 | nested_vmcb->control.nested_ctl); | |
3108 | ||
3109 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, | |
3110 | nested_vmcb->control.intercept_cr >> 16, | |
3111 | nested_vmcb->control.intercept_exceptions, | |
3112 | nested_vmcb->control.intercept); | |
3113 | ||
3114 | /* Clear internal status */ | |
3115 | kvm_clear_exception_queue(&svm->vcpu); | |
3116 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3117 | ||
3118 | /* | |
3119 | * Save the old vmcb, so we don't need to pick what we save, but can | |
3120 | * restore everything when a VMEXIT occurs | |
3121 | */ | |
3122 | hsave->save.es = vmcb->save.es; | |
3123 | hsave->save.cs = vmcb->save.cs; | |
3124 | hsave->save.ss = vmcb->save.ss; | |
3125 | hsave->save.ds = vmcb->save.ds; | |
3126 | hsave->save.gdtr = vmcb->save.gdtr; | |
3127 | hsave->save.idtr = vmcb->save.idtr; | |
3128 | hsave->save.efer = svm->vcpu.arch.efer; | |
3129 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); | |
3130 | hsave->save.cr4 = svm->vcpu.arch.cr4; | |
3131 | hsave->save.rflags = kvm_get_rflags(&svm->vcpu); | |
3132 | hsave->save.rip = kvm_rip_read(&svm->vcpu); | |
3133 | hsave->save.rsp = vmcb->save.rsp; | |
3134 | hsave->save.rax = vmcb->save.rax; | |
3135 | if (npt_enabled) | |
3136 | hsave->save.cr3 = vmcb->save.cr3; | |
3137 | else | |
3138 | hsave->save.cr3 = kvm_read_cr3(&svm->vcpu); | |
3139 | ||
3140 | copy_vmcb_control_area(hsave, vmcb); | |
3141 | ||
3142 | enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, page); | |
8d28fec4 | 3143 | |
9738b2c9 | 3144 | return true; |
3d6368ef AG |
3145 | } |
3146 | ||
9966bf68 | 3147 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
3148 | { |
3149 | to_vmcb->save.fs = from_vmcb->save.fs; | |
3150 | to_vmcb->save.gs = from_vmcb->save.gs; | |
3151 | to_vmcb->save.tr = from_vmcb->save.tr; | |
3152 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
3153 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
3154 | to_vmcb->save.star = from_vmcb->save.star; | |
3155 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
3156 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
3157 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
3158 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
3159 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
3160 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
3161 | } |
3162 | ||
851ba692 | 3163 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 3164 | { |
9966bf68 | 3165 | struct vmcb *nested_vmcb; |
7597f129 | 3166 | struct page *page; |
b742c1e6 | 3167 | int ret; |
9966bf68 | 3168 | |
5542675b AG |
3169 | if (nested_svm_check_permissions(svm)) |
3170 | return 1; | |
3171 | ||
7597f129 | 3172 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
3173 | if (!nested_vmcb) |
3174 | return 1; | |
3175 | ||
e3e9ed3d | 3176 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
b742c1e6 | 3177 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
e3e9ed3d | 3178 | |
9966bf68 | 3179 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); |
7597f129 | 3180 | nested_svm_unmap(page); |
5542675b | 3181 | |
b742c1e6 | 3182 | return ret; |
5542675b AG |
3183 | } |
3184 | ||
851ba692 | 3185 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 3186 | { |
9966bf68 | 3187 | struct vmcb *nested_vmcb; |
7597f129 | 3188 | struct page *page; |
b742c1e6 | 3189 | int ret; |
9966bf68 | 3190 | |
5542675b AG |
3191 | if (nested_svm_check_permissions(svm)) |
3192 | return 1; | |
3193 | ||
7597f129 | 3194 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
3195 | if (!nested_vmcb) |
3196 | return 1; | |
3197 | ||
e3e9ed3d | 3198 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
b742c1e6 | 3199 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
e3e9ed3d | 3200 | |
9966bf68 | 3201 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); |
7597f129 | 3202 | nested_svm_unmap(page); |
5542675b | 3203 | |
b742c1e6 | 3204 | return ret; |
5542675b AG |
3205 | } |
3206 | ||
851ba692 | 3207 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 3208 | { |
3d6368ef AG |
3209 | if (nested_svm_check_permissions(svm)) |
3210 | return 1; | |
3211 | ||
b75f4eb3 RJ |
3212 | /* Save rip after vmrun instruction */ |
3213 | kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3); | |
3d6368ef | 3214 | |
9738b2c9 | 3215 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
3216 | return 1; |
3217 | ||
9738b2c9 | 3218 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
3219 | goto failed; |
3220 | ||
3221 | return 1; | |
3222 | ||
3223 | failed: | |
3224 | ||
3225 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
3226 | svm->vmcb->control.exit_code_hi = 0; | |
3227 | svm->vmcb->control.exit_info_1 = 0; | |
3228 | svm->vmcb->control.exit_info_2 = 0; | |
3229 | ||
3230 | nested_svm_vmexit(svm); | |
3d6368ef AG |
3231 | |
3232 | return 1; | |
3233 | } | |
3234 | ||
851ba692 | 3235 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 | 3236 | { |
b742c1e6 LP |
3237 | int ret; |
3238 | ||
1371d904 AG |
3239 | if (nested_svm_check_permissions(svm)) |
3240 | return 1; | |
3241 | ||
640bd6e5 JN |
3242 | /* |
3243 | * If VGIF is enabled, the STGI intercept is only added to | |
cc3d967f | 3244 | * detect the opening of the SMI/NMI window; remove it now. |
640bd6e5 JN |
3245 | */ |
3246 | if (vgif_enabled(svm)) | |
3247 | clr_intercept(svm, INTERCEPT_STGI); | |
3248 | ||
1371d904 | 3249 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
b742c1e6 | 3250 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
3842d135 | 3251 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
1371d904 | 3252 | |
2af9194d | 3253 | enable_gif(svm); |
1371d904 | 3254 | |
b742c1e6 | 3255 | return ret; |
1371d904 AG |
3256 | } |
3257 | ||
851ba692 | 3258 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 | 3259 | { |
b742c1e6 LP |
3260 | int ret; |
3261 | ||
1371d904 AG |
3262 | if (nested_svm_check_permissions(svm)) |
3263 | return 1; | |
3264 | ||
3265 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
b742c1e6 | 3266 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
1371d904 | 3267 | |
2af9194d | 3268 | disable_gif(svm); |
1371d904 AG |
3269 | |
3270 | /* After a CLGI no interrupts should come */ | |
340d3bc3 SS |
3271 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) { |
3272 | svm_clear_vintr(svm); | |
3273 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
3274 | mark_dirty(svm->vmcb, VMCB_INTR); | |
3275 | } | |
decdbf6a | 3276 | |
b742c1e6 | 3277 | return ret; |
1371d904 AG |
3278 | } |
3279 | ||
851ba692 | 3280 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
3281 | { |
3282 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 3283 | |
668f198f DK |
3284 | trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX), |
3285 | kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); | |
ec1ff790 | 3286 | |
ff092385 | 3287 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
668f198f | 3288 | kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); |
ff092385 AG |
3289 | |
3290 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
b742c1e6 | 3291 | return kvm_skip_emulated_instruction(&svm->vcpu); |
ff092385 AG |
3292 | } |
3293 | ||
532a46b9 JR |
3294 | static int skinit_interception(struct vcpu_svm *svm) |
3295 | { | |
668f198f | 3296 | trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); |
532a46b9 JR |
3297 | |
3298 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3299 | return 1; | |
3300 | } | |
3301 | ||
dab429a7 DK |
3302 | static int wbinvd_interception(struct vcpu_svm *svm) |
3303 | { | |
6affcbed | 3304 | return kvm_emulate_wbinvd(&svm->vcpu); |
dab429a7 DK |
3305 | } |
3306 | ||
81dd35d4 JR |
3307 | static int xsetbv_interception(struct vcpu_svm *svm) |
3308 | { | |
3309 | u64 new_bv = kvm_read_edx_eax(&svm->vcpu); | |
3310 | u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); | |
3311 | ||
3312 | if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) { | |
3313 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
b742c1e6 | 3314 | return kvm_skip_emulated_instruction(&svm->vcpu); |
81dd35d4 JR |
3315 | } |
3316 | ||
3317 | return 1; | |
3318 | } | |
3319 | ||
851ba692 | 3320 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 3321 | { |
37817f29 | 3322 | u16 tss_selector; |
64a7ec06 GN |
3323 | int reason; |
3324 | int int_type = svm->vmcb->control.exit_int_info & | |
3325 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 3326 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
3327 | uint32_t type = |
3328 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
3329 | uint32_t idt_v = | |
3330 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
3331 | bool has_error_code = false; |
3332 | u32 error_code = 0; | |
37817f29 IE |
3333 | |
3334 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 3335 | |
37817f29 IE |
3336 | if (svm->vmcb->control.exit_info_2 & |
3337 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
3338 | reason = TASK_SWITCH_IRET; |
3339 | else if (svm->vmcb->control.exit_info_2 & | |
3340 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
3341 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 3342 | else if (idt_v) |
64a7ec06 GN |
3343 | reason = TASK_SWITCH_GATE; |
3344 | else | |
3345 | reason = TASK_SWITCH_CALL; | |
3346 | ||
fe8e7f83 GN |
3347 | if (reason == TASK_SWITCH_GATE) { |
3348 | switch (type) { | |
3349 | case SVM_EXITINTINFO_TYPE_NMI: | |
3350 | svm->vcpu.arch.nmi_injected = false; | |
3351 | break; | |
3352 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
3353 | if (svm->vmcb->control.exit_info_2 & |
3354 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
3355 | has_error_code = true; | |
3356 | error_code = | |
3357 | (u32)svm->vmcb->control.exit_info_2; | |
3358 | } | |
fe8e7f83 GN |
3359 | kvm_clear_exception_queue(&svm->vcpu); |
3360 | break; | |
3361 | case SVM_EXITINTINFO_TYPE_INTR: | |
3362 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3363 | break; | |
3364 | default: | |
3365 | break; | |
3366 | } | |
3367 | } | |
64a7ec06 | 3368 | |
8317c298 GN |
3369 | if (reason != TASK_SWITCH_GATE || |
3370 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
3371 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
3372 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
3373 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 | 3374 | |
7f3d35fd KW |
3375 | if (int_type != SVM_EXITINTINFO_TYPE_SOFT) |
3376 | int_vec = -1; | |
3377 | ||
3378 | if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason, | |
acb54517 GN |
3379 | has_error_code, error_code) == EMULATE_FAIL) { |
3380 | svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
3381 | svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
3382 | svm->vcpu.run->internal.ndata = 0; | |
3383 | return 0; | |
3384 | } | |
3385 | return 1; | |
6aa8b732 AK |
3386 | } |
3387 | ||
851ba692 | 3388 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 3389 | { |
5fdbf976 | 3390 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
6a908b62 | 3391 | return kvm_emulate_cpuid(&svm->vcpu); |
6aa8b732 AK |
3392 | } |
3393 | ||
851ba692 | 3394 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
3395 | { |
3396 | ++svm->vcpu.stat.nmi_window_exits; | |
8a05a1b8 | 3397 | clr_intercept(svm, INTERCEPT_IRET); |
44c11430 | 3398 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
bd3d1ec3 | 3399 | svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu); |
f303b4ce | 3400 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
95ba8273 GN |
3401 | return 1; |
3402 | } | |
3403 | ||
851ba692 | 3404 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 3405 | { |
df4f3108 AP |
3406 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) |
3407 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; | |
3408 | ||
3409 | kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1); | |
b742c1e6 | 3410 | return kvm_skip_emulated_instruction(&svm->vcpu); |
a7052897 MT |
3411 | } |
3412 | ||
851ba692 | 3413 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 3414 | { |
51d8b661 | 3415 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; |
6aa8b732 AK |
3416 | } |
3417 | ||
332b56e4 AK |
3418 | static int rdpmc_interception(struct vcpu_svm *svm) |
3419 | { | |
3420 | int err; | |
3421 | ||
3422 | if (!static_cpu_has(X86_FEATURE_NRIPS)) | |
3423 | return emulate_on_interception(svm); | |
3424 | ||
3425 | err = kvm_rdpmc(&svm->vcpu); | |
6affcbed | 3426 | return kvm_complete_insn_gp(&svm->vcpu, err); |
332b56e4 AK |
3427 | } |
3428 | ||
52eb5a6d XL |
3429 | static bool check_selective_cr0_intercepted(struct vcpu_svm *svm, |
3430 | unsigned long val) | |
628afd2a JR |
3431 | { |
3432 | unsigned long cr0 = svm->vcpu.arch.cr0; | |
3433 | bool ret = false; | |
3434 | u64 intercept; | |
3435 | ||
3436 | intercept = svm->nested.intercept; | |
3437 | ||
3438 | if (!is_guest_mode(&svm->vcpu) || | |
3439 | (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))) | |
3440 | return false; | |
3441 | ||
3442 | cr0 &= ~SVM_CR0_SELECTIVE_MASK; | |
3443 | val &= ~SVM_CR0_SELECTIVE_MASK; | |
3444 | ||
3445 | if (cr0 ^ val) { | |
3446 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
3447 | ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE); | |
3448 | } | |
3449 | ||
3450 | return ret; | |
3451 | } | |
3452 | ||
7ff76d58 AP |
3453 | #define CR_VALID (1ULL << 63) |
3454 | ||
3455 | static int cr_interception(struct vcpu_svm *svm) | |
3456 | { | |
3457 | int reg, cr; | |
3458 | unsigned long val; | |
3459 | int err; | |
3460 | ||
3461 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
3462 | return emulate_on_interception(svm); | |
3463 | ||
3464 | if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) | |
3465 | return emulate_on_interception(svm); | |
3466 | ||
3467 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
5e57518d DK |
3468 | if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE) |
3469 | cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0; | |
3470 | else | |
3471 | cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0; | |
7ff76d58 AP |
3472 | |
3473 | err = 0; | |
3474 | if (cr >= 16) { /* mov to cr */ | |
3475 | cr -= 16; | |
3476 | val = kvm_register_read(&svm->vcpu, reg); | |
3477 | switch (cr) { | |
3478 | case 0: | |
628afd2a JR |
3479 | if (!check_selective_cr0_intercepted(svm, val)) |
3480 | err = kvm_set_cr0(&svm->vcpu, val); | |
977b2d03 JR |
3481 | else |
3482 | return 1; | |
3483 | ||
7ff76d58 AP |
3484 | break; |
3485 | case 3: | |
3486 | err = kvm_set_cr3(&svm->vcpu, val); | |
3487 | break; | |
3488 | case 4: | |
3489 | err = kvm_set_cr4(&svm->vcpu, val); | |
3490 | break; | |
3491 | case 8: | |
3492 | err = kvm_set_cr8(&svm->vcpu, val); | |
3493 | break; | |
3494 | default: | |
3495 | WARN(1, "unhandled write to CR%d", cr); | |
3496 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3497 | return 1; | |
3498 | } | |
3499 | } else { /* mov from cr */ | |
3500 | switch (cr) { | |
3501 | case 0: | |
3502 | val = kvm_read_cr0(&svm->vcpu); | |
3503 | break; | |
3504 | case 2: | |
3505 | val = svm->vcpu.arch.cr2; | |
3506 | break; | |
3507 | case 3: | |
9f8fe504 | 3508 | val = kvm_read_cr3(&svm->vcpu); |
7ff76d58 AP |
3509 | break; |
3510 | case 4: | |
3511 | val = kvm_read_cr4(&svm->vcpu); | |
3512 | break; | |
3513 | case 8: | |
3514 | val = kvm_get_cr8(&svm->vcpu); | |
3515 | break; | |
3516 | default: | |
3517 | WARN(1, "unhandled read from CR%d", cr); | |
3518 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3519 | return 1; | |
3520 | } | |
3521 | kvm_register_write(&svm->vcpu, reg, val); | |
3522 | } | |
6affcbed | 3523 | return kvm_complete_insn_gp(&svm->vcpu, err); |
7ff76d58 AP |
3524 | } |
3525 | ||
cae3797a AP |
3526 | static int dr_interception(struct vcpu_svm *svm) |
3527 | { | |
3528 | int reg, dr; | |
3529 | unsigned long val; | |
cae3797a | 3530 | |
facb0139 PB |
3531 | if (svm->vcpu.guest_debug == 0) { |
3532 | /* | |
3533 | * No more DR vmexits; force a reload of the debug registers | |
3534 | * and reenter on this instruction. The next vmexit will | |
3535 | * retrieve the full state of the debug registers. | |
3536 | */ | |
3537 | clr_dr_intercepts(svm); | |
3538 | svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
3539 | return 1; | |
3540 | } | |
3541 | ||
cae3797a AP |
3542 | if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS)) |
3543 | return emulate_on_interception(svm); | |
3544 | ||
3545 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
3546 | dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0; | |
3547 | ||
3548 | if (dr >= 16) { /* mov to DRn */ | |
16f8a6f9 NA |
3549 | if (!kvm_require_dr(&svm->vcpu, dr - 16)) |
3550 | return 1; | |
cae3797a AP |
3551 | val = kvm_register_read(&svm->vcpu, reg); |
3552 | kvm_set_dr(&svm->vcpu, dr - 16, val); | |
3553 | } else { | |
16f8a6f9 NA |
3554 | if (!kvm_require_dr(&svm->vcpu, dr)) |
3555 | return 1; | |
3556 | kvm_get_dr(&svm->vcpu, dr, &val); | |
3557 | kvm_register_write(&svm->vcpu, reg, val); | |
cae3797a AP |
3558 | } |
3559 | ||
b742c1e6 | 3560 | return kvm_skip_emulated_instruction(&svm->vcpu); |
cae3797a AP |
3561 | } |
3562 | ||
851ba692 | 3563 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 3564 | { |
851ba692 | 3565 | struct kvm_run *kvm_run = svm->vcpu.run; |
eea1cff9 | 3566 | int r; |
851ba692 | 3567 | |
0a5fff19 GN |
3568 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
3569 | /* instruction emulation calls kvm_set_cr8() */ | |
7ff76d58 | 3570 | r = cr_interception(svm); |
35754c98 | 3571 | if (lapic_in_kernel(&svm->vcpu)) |
7ff76d58 | 3572 | return r; |
0a5fff19 | 3573 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
7ff76d58 | 3574 | return r; |
1d075434 JR |
3575 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
3576 | return 0; | |
3577 | } | |
3578 | ||
609e36d3 | 3579 | static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3580 | { |
a2fa3e9f GH |
3581 | struct vcpu_svm *svm = to_svm(vcpu); |
3582 | ||
609e36d3 | 3583 | switch (msr_info->index) { |
af24a4e4 | 3584 | case MSR_IA32_TSC: { |
609e36d3 | 3585 | msr_info->data = svm->vmcb->control.tsc_offset + |
35181e86 | 3586 | kvm_scale_tsc(vcpu, rdtsc()); |
fbc0db76 | 3587 | |
6aa8b732 AK |
3588 | break; |
3589 | } | |
8c06585d | 3590 | case MSR_STAR: |
609e36d3 | 3591 | msr_info->data = svm->vmcb->save.star; |
6aa8b732 | 3592 | break; |
0e859cac | 3593 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3594 | case MSR_LSTAR: |
609e36d3 | 3595 | msr_info->data = svm->vmcb->save.lstar; |
6aa8b732 AK |
3596 | break; |
3597 | case MSR_CSTAR: | |
609e36d3 | 3598 | msr_info->data = svm->vmcb->save.cstar; |
6aa8b732 AK |
3599 | break; |
3600 | case MSR_KERNEL_GS_BASE: | |
609e36d3 | 3601 | msr_info->data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
3602 | break; |
3603 | case MSR_SYSCALL_MASK: | |
609e36d3 | 3604 | msr_info->data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
3605 | break; |
3606 | #endif | |
3607 | case MSR_IA32_SYSENTER_CS: | |
609e36d3 | 3608 | msr_info->data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
3609 | break; |
3610 | case MSR_IA32_SYSENTER_EIP: | |
609e36d3 | 3611 | msr_info->data = svm->sysenter_eip; |
6aa8b732 AK |
3612 | break; |
3613 | case MSR_IA32_SYSENTER_ESP: | |
609e36d3 | 3614 | msr_info->data = svm->sysenter_esp; |
6aa8b732 | 3615 | break; |
46896c73 PB |
3616 | case MSR_TSC_AUX: |
3617 | if (!boot_cpu_has(X86_FEATURE_RDTSCP)) | |
3618 | return 1; | |
3619 | msr_info->data = svm->tsc_aux; | |
3620 | break; | |
e0231715 JR |
3621 | /* |
3622 | * Nobody will change the following 5 values in the VMCB so we can | |
3623 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
3624 | * implemented. | |
3625 | */ | |
a2938c80 | 3626 | case MSR_IA32_DEBUGCTLMSR: |
609e36d3 | 3627 | msr_info->data = svm->vmcb->save.dbgctl; |
a2938c80 JR |
3628 | break; |
3629 | case MSR_IA32_LASTBRANCHFROMIP: | |
609e36d3 | 3630 | msr_info->data = svm->vmcb->save.br_from; |
a2938c80 JR |
3631 | break; |
3632 | case MSR_IA32_LASTBRANCHTOIP: | |
609e36d3 | 3633 | msr_info->data = svm->vmcb->save.br_to; |
a2938c80 JR |
3634 | break; |
3635 | case MSR_IA32_LASTINTFROMIP: | |
609e36d3 | 3636 | msr_info->data = svm->vmcb->save.last_excp_from; |
a2938c80 JR |
3637 | break; |
3638 | case MSR_IA32_LASTINTTOIP: | |
609e36d3 | 3639 | msr_info->data = svm->vmcb->save.last_excp_to; |
a2938c80 | 3640 | break; |
b286d5d8 | 3641 | case MSR_VM_HSAVE_PA: |
609e36d3 | 3642 | msr_info->data = svm->nested.hsave_msr; |
b286d5d8 | 3643 | break; |
eb6f302e | 3644 | case MSR_VM_CR: |
609e36d3 | 3645 | msr_info->data = svm->nested.vm_cr_msr; |
eb6f302e | 3646 | break; |
c8a73f18 | 3647 | case MSR_IA32_UCODE_REV: |
609e36d3 | 3648 | msr_info->data = 0x01000065; |
c8a73f18 | 3649 | break; |
ae8b7875 BP |
3650 | case MSR_F15H_IC_CFG: { |
3651 | ||
3652 | int family, model; | |
3653 | ||
3654 | family = guest_cpuid_family(vcpu); | |
3655 | model = guest_cpuid_model(vcpu); | |
3656 | ||
3657 | if (family < 0 || model < 0) | |
3658 | return kvm_get_msr_common(vcpu, msr_info); | |
3659 | ||
3660 | msr_info->data = 0; | |
3661 | ||
3662 | if (family == 0x15 && | |
3663 | (model >= 0x2 && model < 0x20)) | |
3664 | msr_info->data = 0x1E; | |
3665 | } | |
3666 | break; | |
6aa8b732 | 3667 | default: |
609e36d3 | 3668 | return kvm_get_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3669 | } |
3670 | return 0; | |
3671 | } | |
3672 | ||
851ba692 | 3673 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3674 | { |
668f198f | 3675 | u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); |
609e36d3 | 3676 | struct msr_data msr_info; |
6aa8b732 | 3677 | |
609e36d3 PB |
3678 | msr_info.index = ecx; |
3679 | msr_info.host_initiated = false; | |
3680 | if (svm_get_msr(&svm->vcpu, &msr_info)) { | |
59200273 | 3681 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 3682 | kvm_inject_gp(&svm->vcpu, 0); |
b742c1e6 | 3683 | return 1; |
59200273 | 3684 | } else { |
609e36d3 | 3685 | trace_kvm_msr_read(ecx, msr_info.data); |
af9ca2d7 | 3686 | |
609e36d3 PB |
3687 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, |
3688 | msr_info.data & 0xffffffff); | |
3689 | kvm_register_write(&svm->vcpu, VCPU_REGS_RDX, | |
3690 | msr_info.data >> 32); | |
5fdbf976 | 3691 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
b742c1e6 | 3692 | return kvm_skip_emulated_instruction(&svm->vcpu); |
6aa8b732 | 3693 | } |
6aa8b732 AK |
3694 | } |
3695 | ||
4a810181 JR |
3696 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
3697 | { | |
3698 | struct vcpu_svm *svm = to_svm(vcpu); | |
3699 | int svm_dis, chg_mask; | |
3700 | ||
3701 | if (data & ~SVM_VM_CR_VALID_MASK) | |
3702 | return 1; | |
3703 | ||
3704 | chg_mask = SVM_VM_CR_VALID_MASK; | |
3705 | ||
3706 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
3707 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
3708 | ||
3709 | svm->nested.vm_cr_msr &= ~chg_mask; | |
3710 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
3711 | ||
3712 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
3713 | ||
3714 | /* check for svm_disable while efer.svme is set */ | |
3715 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
3716 | return 1; | |
3717 | ||
3718 | return 0; | |
3719 | } | |
3720 | ||
8fe8ab46 | 3721 | static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
6aa8b732 | 3722 | { |
a2fa3e9f GH |
3723 | struct vcpu_svm *svm = to_svm(vcpu); |
3724 | ||
8fe8ab46 WA |
3725 | u32 ecx = msr->index; |
3726 | u64 data = msr->data; | |
6aa8b732 | 3727 | switch (ecx) { |
15038e14 PB |
3728 | case MSR_IA32_CR_PAT: |
3729 | if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data)) | |
3730 | return 1; | |
3731 | vcpu->arch.pat = data; | |
3732 | svm->vmcb->save.g_pat = data; | |
3733 | mark_dirty(svm->vmcb, VMCB_NPT); | |
3734 | break; | |
f4e1b3c8 | 3735 | case MSR_IA32_TSC: |
8fe8ab46 | 3736 | kvm_write_tsc(vcpu, msr); |
6aa8b732 | 3737 | break; |
8c06585d | 3738 | case MSR_STAR: |
a2fa3e9f | 3739 | svm->vmcb->save.star = data; |
6aa8b732 | 3740 | break; |
49b14f24 | 3741 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3742 | case MSR_LSTAR: |
a2fa3e9f | 3743 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
3744 | break; |
3745 | case MSR_CSTAR: | |
a2fa3e9f | 3746 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
3747 | break; |
3748 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 3749 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
3750 | break; |
3751 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 3752 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
3753 | break; |
3754 | #endif | |
3755 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 3756 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
3757 | break; |
3758 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 3759 | svm->sysenter_eip = data; |
a2fa3e9f | 3760 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
3761 | break; |
3762 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 3763 | svm->sysenter_esp = data; |
a2fa3e9f | 3764 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 3765 | break; |
46896c73 PB |
3766 | case MSR_TSC_AUX: |
3767 | if (!boot_cpu_has(X86_FEATURE_RDTSCP)) | |
3768 | return 1; | |
3769 | ||
3770 | /* | |
3771 | * This is rare, so we update the MSR here instead of using | |
3772 | * direct_access_msrs. Doing that would require a rdmsr in | |
3773 | * svm_vcpu_put. | |
3774 | */ | |
3775 | svm->tsc_aux = data; | |
3776 | wrmsrl(MSR_TSC_AUX, svm->tsc_aux); | |
3777 | break; | |
a2938c80 | 3778 | case MSR_IA32_DEBUGCTLMSR: |
2a6b20b8 | 3779 | if (!boot_cpu_has(X86_FEATURE_LBRV)) { |
a737f256 CD |
3780 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", |
3781 | __func__, data); | |
24e09cbf JR |
3782 | break; |
3783 | } | |
3784 | if (data & DEBUGCTL_RESERVED_BITS) | |
3785 | return 1; | |
3786 | ||
3787 | svm->vmcb->save.dbgctl = data; | |
b53ba3f9 | 3788 | mark_dirty(svm->vmcb, VMCB_LBR); |
24e09cbf JR |
3789 | if (data & (1ULL<<0)) |
3790 | svm_enable_lbrv(svm); | |
3791 | else | |
3792 | svm_disable_lbrv(svm); | |
a2938c80 | 3793 | break; |
b286d5d8 | 3794 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 3795 | svm->nested.hsave_msr = data; |
62b9abaa | 3796 | break; |
3c5d0a44 | 3797 | case MSR_VM_CR: |
4a810181 | 3798 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 3799 | case MSR_VM_IGNNE: |
a737f256 | 3800 | vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
3c5d0a44 | 3801 | break; |
44a95dae SS |
3802 | case MSR_IA32_APICBASE: |
3803 | if (kvm_vcpu_apicv_active(vcpu)) | |
3804 | avic_update_vapic_bar(to_svm(vcpu), data); | |
3805 | /* Follow through */ | |
6aa8b732 | 3806 | default: |
8fe8ab46 | 3807 | return kvm_set_msr_common(vcpu, msr); |
6aa8b732 AK |
3808 | } |
3809 | return 0; | |
3810 | } | |
3811 | ||
851ba692 | 3812 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3813 | { |
8fe8ab46 | 3814 | struct msr_data msr; |
668f198f DK |
3815 | u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); |
3816 | u64 data = kvm_read_edx_eax(&svm->vcpu); | |
af9ca2d7 | 3817 | |
8fe8ab46 WA |
3818 | msr.data = data; |
3819 | msr.index = ecx; | |
3820 | msr.host_initiated = false; | |
af9ca2d7 | 3821 | |
5fdbf976 | 3822 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
854e8bb1 | 3823 | if (kvm_set_msr(&svm->vcpu, &msr)) { |
59200273 | 3824 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 3825 | kvm_inject_gp(&svm->vcpu, 0); |
b742c1e6 | 3826 | return 1; |
59200273 AK |
3827 | } else { |
3828 | trace_kvm_msr_write(ecx, data); | |
b742c1e6 | 3829 | return kvm_skip_emulated_instruction(&svm->vcpu); |
59200273 | 3830 | } |
6aa8b732 AK |
3831 | } |
3832 | ||
851ba692 | 3833 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3834 | { |
e756fc62 | 3835 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 3836 | return wrmsr_interception(svm); |
6aa8b732 | 3837 | else |
851ba692 | 3838 | return rdmsr_interception(svm); |
6aa8b732 AK |
3839 | } |
3840 | ||
851ba692 | 3841 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 3842 | { |
3842d135 | 3843 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
f0b85051 | 3844 | svm_clear_vintr(svm); |
85f455f7 | 3845 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
decdbf6a | 3846 | mark_dirty(svm->vmcb, VMCB_INTR); |
675acb75 | 3847 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
3848 | return 1; |
3849 | } | |
3850 | ||
565d0998 ML |
3851 | static int pause_interception(struct vcpu_svm *svm) |
3852 | { | |
de63ad4c LM |
3853 | struct kvm_vcpu *vcpu = &svm->vcpu; |
3854 | bool in_kernel = (svm_get_cpl(vcpu) == 0); | |
3855 | ||
3856 | kvm_vcpu_on_spin(vcpu, in_kernel); | |
565d0998 ML |
3857 | return 1; |
3858 | } | |
3859 | ||
87c00572 GS |
3860 | static int nop_interception(struct vcpu_svm *svm) |
3861 | { | |
b742c1e6 | 3862 | return kvm_skip_emulated_instruction(&(svm->vcpu)); |
87c00572 GS |
3863 | } |
3864 | ||
3865 | static int monitor_interception(struct vcpu_svm *svm) | |
3866 | { | |
3867 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
3868 | return nop_interception(svm); | |
3869 | } | |
3870 | ||
3871 | static int mwait_interception(struct vcpu_svm *svm) | |
3872 | { | |
3873 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
3874 | return nop_interception(svm); | |
3875 | } | |
3876 | ||
18f40c53 SS |
3877 | enum avic_ipi_failure_cause { |
3878 | AVIC_IPI_FAILURE_INVALID_INT_TYPE, | |
3879 | AVIC_IPI_FAILURE_TARGET_NOT_RUNNING, | |
3880 | AVIC_IPI_FAILURE_INVALID_TARGET, | |
3881 | AVIC_IPI_FAILURE_INVALID_BACKING_PAGE, | |
3882 | }; | |
3883 | ||
3884 | static int avic_incomplete_ipi_interception(struct vcpu_svm *svm) | |
3885 | { | |
3886 | u32 icrh = svm->vmcb->control.exit_info_1 >> 32; | |
3887 | u32 icrl = svm->vmcb->control.exit_info_1; | |
3888 | u32 id = svm->vmcb->control.exit_info_2 >> 32; | |
5446a979 | 3889 | u32 index = svm->vmcb->control.exit_info_2 & 0xFF; |
18f40c53 SS |
3890 | struct kvm_lapic *apic = svm->vcpu.arch.apic; |
3891 | ||
3892 | trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index); | |
3893 | ||
3894 | switch (id) { | |
3895 | case AVIC_IPI_FAILURE_INVALID_INT_TYPE: | |
3896 | /* | |
3897 | * AVIC hardware handles the generation of | |
3898 | * IPIs when the specified Message Type is Fixed | |
3899 | * (also known as fixed delivery mode) and | |
3900 | * the Trigger Mode is edge-triggered. The hardware | |
3901 | * also supports self and broadcast delivery modes | |
3902 | * specified via the Destination Shorthand(DSH) | |
3903 | * field of the ICRL. Logical and physical APIC ID | |
3904 | * formats are supported. All other IPI types cause | |
3905 | * a #VMEXIT, which needs to emulated. | |
3906 | */ | |
3907 | kvm_lapic_reg_write(apic, APIC_ICR2, icrh); | |
3908 | kvm_lapic_reg_write(apic, APIC_ICR, icrl); | |
3909 | break; | |
3910 | case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: { | |
3911 | int i; | |
3912 | struct kvm_vcpu *vcpu; | |
3913 | struct kvm *kvm = svm->vcpu.kvm; | |
3914 | struct kvm_lapic *apic = svm->vcpu.arch.apic; | |
3915 | ||
3916 | /* | |
3917 | * At this point, we expect that the AVIC HW has already | |
3918 | * set the appropriate IRR bits on the valid target | |
3919 | * vcpus. So, we just need to kick the appropriate vcpu. | |
3920 | */ | |
3921 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
3922 | bool m = kvm_apic_match_dest(vcpu, apic, | |
3923 | icrl & KVM_APIC_SHORT_MASK, | |
3924 | GET_APIC_DEST_FIELD(icrh), | |
3925 | icrl & KVM_APIC_DEST_MASK); | |
3926 | ||
3927 | if (m && !avic_vcpu_is_running(vcpu)) | |
3928 | kvm_vcpu_wake_up(vcpu); | |
3929 | } | |
3930 | break; | |
3931 | } | |
3932 | case AVIC_IPI_FAILURE_INVALID_TARGET: | |
3933 | break; | |
3934 | case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE: | |
3935 | WARN_ONCE(1, "Invalid backing page\n"); | |
3936 | break; | |
3937 | default: | |
3938 | pr_err("Unknown IPI interception\n"); | |
3939 | } | |
3940 | ||
3941 | return 1; | |
3942 | } | |
3943 | ||
3944 | static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat) | |
3945 | { | |
3946 | struct kvm_arch *vm_data = &vcpu->kvm->arch; | |
3947 | int index; | |
3948 | u32 *logical_apic_id_table; | |
3949 | int dlid = GET_APIC_LOGICAL_ID(ldr); | |
3950 | ||
3951 | if (!dlid) | |
3952 | return NULL; | |
3953 | ||
3954 | if (flat) { /* flat */ | |
3955 | index = ffs(dlid) - 1; | |
3956 | if (index > 7) | |
3957 | return NULL; | |
3958 | } else { /* cluster */ | |
3959 | int cluster = (dlid & 0xf0) >> 4; | |
3960 | int apic = ffs(dlid & 0x0f) - 1; | |
3961 | ||
3962 | if ((apic < 0) || (apic > 7) || | |
3963 | (cluster >= 0xf)) | |
3964 | return NULL; | |
3965 | index = (cluster << 2) + apic; | |
3966 | } | |
3967 | ||
3968 | logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page); | |
3969 | ||
3970 | return &logical_apic_id_table[index]; | |
3971 | } | |
3972 | ||
3973 | static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr, | |
3974 | bool valid) | |
3975 | { | |
3976 | bool flat; | |
3977 | u32 *entry, new_entry; | |
3978 | ||
3979 | flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT; | |
3980 | entry = avic_get_logical_id_entry(vcpu, ldr, flat); | |
3981 | if (!entry) | |
3982 | return -EINVAL; | |
3983 | ||
3984 | new_entry = READ_ONCE(*entry); | |
3985 | new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK; | |
3986 | new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK); | |
3987 | if (valid) | |
3988 | new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK; | |
3989 | else | |
3990 | new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK; | |
3991 | WRITE_ONCE(*entry, new_entry); | |
3992 | ||
3993 | return 0; | |
3994 | } | |
3995 | ||
3996 | static int avic_handle_ldr_update(struct kvm_vcpu *vcpu) | |
3997 | { | |
3998 | int ret; | |
3999 | struct vcpu_svm *svm = to_svm(vcpu); | |
4000 | u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR); | |
4001 | ||
4002 | if (!ldr) | |
4003 | return 1; | |
4004 | ||
4005 | ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true); | |
4006 | if (ret && svm->ldr_reg) { | |
4007 | avic_ldr_write(vcpu, 0, svm->ldr_reg, false); | |
4008 | svm->ldr_reg = 0; | |
4009 | } else { | |
4010 | svm->ldr_reg = ldr; | |
4011 | } | |
4012 | return ret; | |
4013 | } | |
4014 | ||
4015 | static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu) | |
4016 | { | |
4017 | u64 *old, *new; | |
4018 | struct vcpu_svm *svm = to_svm(vcpu); | |
4019 | u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID); | |
4020 | u32 id = (apic_id_reg >> 24) & 0xff; | |
4021 | ||
4022 | if (vcpu->vcpu_id == id) | |
4023 | return 0; | |
4024 | ||
4025 | old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id); | |
4026 | new = avic_get_physical_id_entry(vcpu, id); | |
4027 | if (!new || !old) | |
4028 | return 1; | |
4029 | ||
4030 | /* We need to move physical_id_entry to new offset */ | |
4031 | *new = *old; | |
4032 | *old = 0ULL; | |
4033 | to_svm(vcpu)->avic_physical_id_cache = new; | |
4034 | ||
4035 | /* | |
4036 | * Also update the guest physical APIC ID in the logical | |
4037 | * APIC ID table entry if already setup the LDR. | |
4038 | */ | |
4039 | if (svm->ldr_reg) | |
4040 | avic_handle_ldr_update(vcpu); | |
4041 | ||
4042 | return 0; | |
4043 | } | |
4044 | ||
4045 | static int avic_handle_dfr_update(struct kvm_vcpu *vcpu) | |
4046 | { | |
4047 | struct vcpu_svm *svm = to_svm(vcpu); | |
4048 | struct kvm_arch *vm_data = &vcpu->kvm->arch; | |
4049 | u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR); | |
4050 | u32 mod = (dfr >> 28) & 0xf; | |
4051 | ||
4052 | /* | |
4053 | * We assume that all local APICs are using the same type. | |
4054 | * If this changes, we need to flush the AVIC logical | |
4055 | * APID id table. | |
4056 | */ | |
4057 | if (vm_data->ldr_mode == mod) | |
4058 | return 0; | |
4059 | ||
4060 | clear_page(page_address(vm_data->avic_logical_id_table_page)); | |
4061 | vm_data->ldr_mode = mod; | |
4062 | ||
4063 | if (svm->ldr_reg) | |
4064 | avic_handle_ldr_update(vcpu); | |
4065 | return 0; | |
4066 | } | |
4067 | ||
4068 | static int avic_unaccel_trap_write(struct vcpu_svm *svm) | |
4069 | { | |
4070 | struct kvm_lapic *apic = svm->vcpu.arch.apic; | |
4071 | u32 offset = svm->vmcb->control.exit_info_1 & | |
4072 | AVIC_UNACCEL_ACCESS_OFFSET_MASK; | |
4073 | ||
4074 | switch (offset) { | |
4075 | case APIC_ID: | |
4076 | if (avic_handle_apic_id_update(&svm->vcpu)) | |
4077 | return 0; | |
4078 | break; | |
4079 | case APIC_LDR: | |
4080 | if (avic_handle_ldr_update(&svm->vcpu)) | |
4081 | return 0; | |
4082 | break; | |
4083 | case APIC_DFR: | |
4084 | avic_handle_dfr_update(&svm->vcpu); | |
4085 | break; | |
4086 | default: | |
4087 | break; | |
4088 | } | |
4089 | ||
4090 | kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset)); | |
4091 | ||
4092 | return 1; | |
4093 | } | |
4094 | ||
4095 | static bool is_avic_unaccelerated_access_trap(u32 offset) | |
4096 | { | |
4097 | bool ret = false; | |
4098 | ||
4099 | switch (offset) { | |
4100 | case APIC_ID: | |
4101 | case APIC_EOI: | |
4102 | case APIC_RRR: | |
4103 | case APIC_LDR: | |
4104 | case APIC_DFR: | |
4105 | case APIC_SPIV: | |
4106 | case APIC_ESR: | |
4107 | case APIC_ICR: | |
4108 | case APIC_LVTT: | |
4109 | case APIC_LVTTHMR: | |
4110 | case APIC_LVTPC: | |
4111 | case APIC_LVT0: | |
4112 | case APIC_LVT1: | |
4113 | case APIC_LVTERR: | |
4114 | case APIC_TMICT: | |
4115 | case APIC_TDCR: | |
4116 | ret = true; | |
4117 | break; | |
4118 | default: | |
4119 | break; | |
4120 | } | |
4121 | return ret; | |
4122 | } | |
4123 | ||
4124 | static int avic_unaccelerated_access_interception(struct vcpu_svm *svm) | |
4125 | { | |
4126 | int ret = 0; | |
4127 | u32 offset = svm->vmcb->control.exit_info_1 & | |
4128 | AVIC_UNACCEL_ACCESS_OFFSET_MASK; | |
4129 | u32 vector = svm->vmcb->control.exit_info_2 & | |
4130 | AVIC_UNACCEL_ACCESS_VECTOR_MASK; | |
4131 | bool write = (svm->vmcb->control.exit_info_1 >> 32) & | |
4132 | AVIC_UNACCEL_ACCESS_WRITE_MASK; | |
4133 | bool trap = is_avic_unaccelerated_access_trap(offset); | |
4134 | ||
4135 | trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset, | |
4136 | trap, write, vector); | |
4137 | if (trap) { | |
4138 | /* Handling Trap */ | |
4139 | WARN_ONCE(!write, "svm: Handling trap read.\n"); | |
4140 | ret = avic_unaccel_trap_write(svm); | |
4141 | } else { | |
4142 | /* Handling Fault */ | |
4143 | ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE); | |
4144 | } | |
4145 | ||
4146 | return ret; | |
4147 | } | |
4148 | ||
09941fbb | 4149 | static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = { |
7ff76d58 AP |
4150 | [SVM_EXIT_READ_CR0] = cr_interception, |
4151 | [SVM_EXIT_READ_CR3] = cr_interception, | |
4152 | [SVM_EXIT_READ_CR4] = cr_interception, | |
4153 | [SVM_EXIT_READ_CR8] = cr_interception, | |
5e57518d | 4154 | [SVM_EXIT_CR0_SEL_WRITE] = cr_interception, |
628afd2a | 4155 | [SVM_EXIT_WRITE_CR0] = cr_interception, |
7ff76d58 AP |
4156 | [SVM_EXIT_WRITE_CR3] = cr_interception, |
4157 | [SVM_EXIT_WRITE_CR4] = cr_interception, | |
e0231715 | 4158 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
cae3797a AP |
4159 | [SVM_EXIT_READ_DR0] = dr_interception, |
4160 | [SVM_EXIT_READ_DR1] = dr_interception, | |
4161 | [SVM_EXIT_READ_DR2] = dr_interception, | |
4162 | [SVM_EXIT_READ_DR3] = dr_interception, | |
4163 | [SVM_EXIT_READ_DR4] = dr_interception, | |
4164 | [SVM_EXIT_READ_DR5] = dr_interception, | |
4165 | [SVM_EXIT_READ_DR6] = dr_interception, | |
4166 | [SVM_EXIT_READ_DR7] = dr_interception, | |
4167 | [SVM_EXIT_WRITE_DR0] = dr_interception, | |
4168 | [SVM_EXIT_WRITE_DR1] = dr_interception, | |
4169 | [SVM_EXIT_WRITE_DR2] = dr_interception, | |
4170 | [SVM_EXIT_WRITE_DR3] = dr_interception, | |
4171 | [SVM_EXIT_WRITE_DR4] = dr_interception, | |
4172 | [SVM_EXIT_WRITE_DR5] = dr_interception, | |
4173 | [SVM_EXIT_WRITE_DR6] = dr_interception, | |
4174 | [SVM_EXIT_WRITE_DR7] = dr_interception, | |
d0bfb940 JK |
4175 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
4176 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 4177 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 | 4178 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
e0231715 | 4179 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, |
54a20552 | 4180 | [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception, |
e0231715 | 4181 | [SVM_EXIT_INTR] = intr_interception, |
c47f098d | 4182 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
4183 | [SVM_EXIT_SMI] = nop_on_interception, |
4184 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 4185 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
332b56e4 | 4186 | [SVM_EXIT_RDPMC] = rdpmc_interception, |
6aa8b732 | 4187 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 4188 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 4189 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 4190 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 4191 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 4192 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 4193 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 4194 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
4195 | [SVM_EXIT_MSR] = msr_interception, |
4196 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 4197 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 4198 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 4199 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
4200 | [SVM_EXIT_VMLOAD] = vmload_interception, |
4201 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
4202 | [SVM_EXIT_STGI] = stgi_interception, |
4203 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 4204 | [SVM_EXIT_SKINIT] = skinit_interception, |
dab429a7 | 4205 | [SVM_EXIT_WBINVD] = wbinvd_interception, |
87c00572 GS |
4206 | [SVM_EXIT_MONITOR] = monitor_interception, |
4207 | [SVM_EXIT_MWAIT] = mwait_interception, | |
81dd35d4 | 4208 | [SVM_EXIT_XSETBV] = xsetbv_interception, |
d0006530 | 4209 | [SVM_EXIT_NPF] = npf_interception, |
64d60670 | 4210 | [SVM_EXIT_RSM] = emulate_on_interception, |
18f40c53 SS |
4211 | [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception, |
4212 | [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception, | |
6aa8b732 AK |
4213 | }; |
4214 | ||
ae8cc059 | 4215 | static void dump_vmcb(struct kvm_vcpu *vcpu) |
3f10c846 JR |
4216 | { |
4217 | struct vcpu_svm *svm = to_svm(vcpu); | |
4218 | struct vmcb_control_area *control = &svm->vmcb->control; | |
4219 | struct vmcb_save_area *save = &svm->vmcb->save; | |
4220 | ||
4221 | pr_err("VMCB Control Area:\n"); | |
ae8cc059 JP |
4222 | pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff); |
4223 | pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16); | |
4224 | pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff); | |
4225 | pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16); | |
4226 | pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions); | |
4227 | pr_err("%-20s%016llx\n", "intercepts:", control->intercept); | |
4228 | pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count); | |
4229 | pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa); | |
4230 | pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa); | |
4231 | pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset); | |
4232 | pr_err("%-20s%d\n", "asid:", control->asid); | |
4233 | pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl); | |
4234 | pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl); | |
4235 | pr_err("%-20s%08x\n", "int_vector:", control->int_vector); | |
4236 | pr_err("%-20s%08x\n", "int_state:", control->int_state); | |
4237 | pr_err("%-20s%08x\n", "exit_code:", control->exit_code); | |
4238 | pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1); | |
4239 | pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2); | |
4240 | pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info); | |
4241 | pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err); | |
4242 | pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl); | |
4243 | pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3); | |
44a95dae | 4244 | pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar); |
ae8cc059 JP |
4245 | pr_err("%-20s%08x\n", "event_inj:", control->event_inj); |
4246 | pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err); | |
0dc92119 | 4247 | pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext); |
ae8cc059 | 4248 | pr_err("%-20s%016llx\n", "next_rip:", control->next_rip); |
44a95dae SS |
4249 | pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page); |
4250 | pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id); | |
4251 | pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id); | |
3f10c846 | 4252 | pr_err("VMCB State Save Area:\n"); |
ae8cc059 JP |
4253 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", |
4254 | "es:", | |
4255 | save->es.selector, save->es.attrib, | |
4256 | save->es.limit, save->es.base); | |
4257 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4258 | "cs:", | |
4259 | save->cs.selector, save->cs.attrib, | |
4260 | save->cs.limit, save->cs.base); | |
4261 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4262 | "ss:", | |
4263 | save->ss.selector, save->ss.attrib, | |
4264 | save->ss.limit, save->ss.base); | |
4265 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4266 | "ds:", | |
4267 | save->ds.selector, save->ds.attrib, | |
4268 | save->ds.limit, save->ds.base); | |
4269 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4270 | "fs:", | |
4271 | save->fs.selector, save->fs.attrib, | |
4272 | save->fs.limit, save->fs.base); | |
4273 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4274 | "gs:", | |
4275 | save->gs.selector, save->gs.attrib, | |
4276 | save->gs.limit, save->gs.base); | |
4277 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4278 | "gdtr:", | |
4279 | save->gdtr.selector, save->gdtr.attrib, | |
4280 | save->gdtr.limit, save->gdtr.base); | |
4281 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4282 | "ldtr:", | |
4283 | save->ldtr.selector, save->ldtr.attrib, | |
4284 | save->ldtr.limit, save->ldtr.base); | |
4285 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4286 | "idtr:", | |
4287 | save->idtr.selector, save->idtr.attrib, | |
4288 | save->idtr.limit, save->idtr.base); | |
4289 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4290 | "tr:", | |
4291 | save->tr.selector, save->tr.attrib, | |
4292 | save->tr.limit, save->tr.base); | |
3f10c846 JR |
4293 | pr_err("cpl: %d efer: %016llx\n", |
4294 | save->cpl, save->efer); | |
ae8cc059 JP |
4295 | pr_err("%-15s %016llx %-13s %016llx\n", |
4296 | "cr0:", save->cr0, "cr2:", save->cr2); | |
4297 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4298 | "cr3:", save->cr3, "cr4:", save->cr4); | |
4299 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4300 | "dr6:", save->dr6, "dr7:", save->dr7); | |
4301 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4302 | "rip:", save->rip, "rflags:", save->rflags); | |
4303 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4304 | "rsp:", save->rsp, "rax:", save->rax); | |
4305 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4306 | "star:", save->star, "lstar:", save->lstar); | |
4307 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4308 | "cstar:", save->cstar, "sfmask:", save->sfmask); | |
4309 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4310 | "kernel_gs_base:", save->kernel_gs_base, | |
4311 | "sysenter_cs:", save->sysenter_cs); | |
4312 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4313 | "sysenter_esp:", save->sysenter_esp, | |
4314 | "sysenter_eip:", save->sysenter_eip); | |
4315 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4316 | "gpat:", save->g_pat, "dbgctl:", save->dbgctl); | |
4317 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4318 | "br_from:", save->br_from, "br_to:", save->br_to); | |
4319 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4320 | "excp_from:", save->last_excp_from, | |
4321 | "excp_to:", save->last_excp_to); | |
3f10c846 JR |
4322 | } |
4323 | ||
586f9607 AK |
4324 | static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
4325 | { | |
4326 | struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; | |
4327 | ||
4328 | *info1 = control->exit_info_1; | |
4329 | *info2 = control->exit_info_2; | |
4330 | } | |
4331 | ||
851ba692 | 4332 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 4333 | { |
04d2cc77 | 4334 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 4335 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 4336 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 4337 | |
8b89fe1f PB |
4338 | trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM); |
4339 | ||
4ee546b4 | 4340 | if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE)) |
2be4fc7a JR |
4341 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
4342 | if (npt_enabled) | |
4343 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 4344 | |
cd3ff653 JR |
4345 | if (unlikely(svm->nested.exit_required)) { |
4346 | nested_svm_vmexit(svm); | |
4347 | svm->nested.exit_required = false; | |
4348 | ||
4349 | return 1; | |
4350 | } | |
4351 | ||
2030753d | 4352 | if (is_guest_mode(vcpu)) { |
410e4d57 JR |
4353 | int vmexit; |
4354 | ||
d8cabddf JR |
4355 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
4356 | svm->vmcb->control.exit_info_1, | |
4357 | svm->vmcb->control.exit_info_2, | |
4358 | svm->vmcb->control.exit_int_info, | |
e097e5ff SH |
4359 | svm->vmcb->control.exit_int_info_err, |
4360 | KVM_ISA_SVM); | |
d8cabddf | 4361 | |
410e4d57 JR |
4362 | vmexit = nested_svm_exit_special(svm); |
4363 | ||
4364 | if (vmexit == NESTED_EXIT_CONTINUE) | |
4365 | vmexit = nested_svm_exit_handled(svm); | |
4366 | ||
4367 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 4368 | return 1; |
cf74a78b AG |
4369 | } |
4370 | ||
a5c3832d JR |
4371 | svm_complete_interrupts(svm); |
4372 | ||
04d2cc77 AK |
4373 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
4374 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
4375 | kvm_run->fail_entry.hardware_entry_failure_reason | |
4376 | = svm->vmcb->control.exit_code; | |
3f10c846 JR |
4377 | pr_err("KVM: FAILED VMRUN WITH VMCB:\n"); |
4378 | dump_vmcb(vcpu); | |
04d2cc77 AK |
4379 | return 0; |
4380 | } | |
4381 | ||
a2fa3e9f | 4382 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 4383 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
55c5e464 JR |
4384 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH && |
4385 | exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI) | |
6614c7d0 | 4386 | printk(KERN_ERR "%s: unexpected exit_int_info 0x%x " |
6aa8b732 | 4387 | "exit_code 0x%x\n", |
b8688d51 | 4388 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
4389 | exit_code); |
4390 | ||
9d8f549d | 4391 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 4392 | || !svm_exit_handlers[exit_code]) { |
faac2458 | 4393 | WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code); |
2bc19dc3 MT |
4394 | kvm_queue_exception(vcpu, UD_VECTOR); |
4395 | return 1; | |
6aa8b732 AK |
4396 | } |
4397 | ||
851ba692 | 4398 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
4399 | } |
4400 | ||
4401 | static void reload_tss(struct kvm_vcpu *vcpu) | |
4402 | { | |
4403 | int cpu = raw_smp_processor_id(); | |
4404 | ||
0fe1e009 TH |
4405 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
4406 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
4407 | load_TR_desc(); |
4408 | } | |
4409 | ||
e756fc62 | 4410 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
4411 | { |
4412 | int cpu = raw_smp_processor_id(); | |
4413 | ||
0fe1e009 | 4414 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 4415 | |
4b656b12 | 4416 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
4417 | if (svm->asid_generation != sd->asid_generation) |
4418 | new_asid(svm, sd); | |
6aa8b732 AK |
4419 | } |
4420 | ||
95ba8273 GN |
4421 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
4422 | { | |
4423 | struct vcpu_svm *svm = to_svm(vcpu); | |
4424 | ||
4425 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
4426 | vcpu->arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 4427 | set_intercept(svm, INTERCEPT_IRET); |
95ba8273 GN |
4428 | ++vcpu->stat.nmi_injections; |
4429 | } | |
6aa8b732 | 4430 | |
85f455f7 | 4431 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
4432 | { |
4433 | struct vmcb_control_area *control; | |
4434 | ||
340d3bc3 | 4435 | /* The following fields are ignored when AVIC is enabled */ |
e756fc62 | 4436 | control = &svm->vmcb->control; |
85f455f7 | 4437 | control->int_vector = irq; |
6aa8b732 AK |
4438 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
4439 | control->int_ctl |= V_IRQ_MASK | | |
4440 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
decdbf6a | 4441 | mark_dirty(svm->vmcb, VMCB_INTR); |
6aa8b732 AK |
4442 | } |
4443 | ||
66fd3f7f | 4444 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
4445 | { |
4446 | struct vcpu_svm *svm = to_svm(vcpu); | |
4447 | ||
2af9194d | 4448 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 4449 | |
9fb2d2b4 GN |
4450 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
4451 | ++vcpu->stat.irq_injections; | |
4452 | ||
219b65dc AG |
4453 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
4454 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
4455 | } |
4456 | ||
3bbf3565 SS |
4457 | static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu) |
4458 | { | |
4459 | return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK); | |
4460 | } | |
4461 | ||
95ba8273 | 4462 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
4463 | { |
4464 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 4465 | |
3bbf3565 SS |
4466 | if (svm_nested_virtualize_tpr(vcpu) || |
4467 | kvm_vcpu_apicv_active(vcpu)) | |
88ab24ad JR |
4468 | return; |
4469 | ||
596f3142 RK |
4470 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
4471 | ||
95ba8273 | 4472 | if (irr == -1) |
aaacfc9a JR |
4473 | return; |
4474 | ||
95ba8273 | 4475 | if (tpr >= irr) |
4ee546b4 | 4476 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
95ba8273 | 4477 | } |
aaacfc9a | 4478 | |
8d14695f YZ |
4479 | static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) |
4480 | { | |
4481 | return; | |
4482 | } | |
4483 | ||
b2a05fef | 4484 | static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu) |
d62caabb | 4485 | { |
67034bb9 | 4486 | return avic && irqchip_split(vcpu->kvm); |
44a95dae SS |
4487 | } |
4488 | ||
4489 | static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) | |
4490 | { | |
d62caabb AS |
4491 | } |
4492 | ||
67c9dddc | 4493 | static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) |
44a95dae | 4494 | { |
d62caabb AS |
4495 | } |
4496 | ||
44a95dae | 4497 | /* Note: Currently only used by Hyper-V. */ |
d62caabb | 4498 | static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) |
c7c9c56c | 4499 | { |
44a95dae SS |
4500 | struct vcpu_svm *svm = to_svm(vcpu); |
4501 | struct vmcb *vmcb = svm->vmcb; | |
4502 | ||
67034bb9 | 4503 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) |
44a95dae SS |
4504 | return; |
4505 | ||
4506 | vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK; | |
4507 | mark_dirty(vmcb, VMCB_INTR); | |
c7c9c56c YZ |
4508 | } |
4509 | ||
6308630b | 4510 | static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
c7c9c56c YZ |
4511 | { |
4512 | return; | |
4513 | } | |
4514 | ||
340d3bc3 SS |
4515 | static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec) |
4516 | { | |
4517 | kvm_lapic_set_irr(vec, vcpu->arch.apic); | |
4518 | smp_mb__after_atomic(); | |
4519 | ||
4520 | if (avic_vcpu_is_running(vcpu)) | |
4521 | wrmsrl(SVM_AVIC_DOORBELL, | |
7d669f50 | 4522 | kvm_cpu_get_apicid(vcpu->cpu)); |
340d3bc3 SS |
4523 | else |
4524 | kvm_vcpu_wake_up(vcpu); | |
4525 | } | |
4526 | ||
411b44ba SS |
4527 | static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi) |
4528 | { | |
4529 | unsigned long flags; | |
4530 | struct amd_svm_iommu_ir *cur; | |
4531 | ||
4532 | spin_lock_irqsave(&svm->ir_list_lock, flags); | |
4533 | list_for_each_entry(cur, &svm->ir_list, node) { | |
4534 | if (cur->data != pi->ir_data) | |
4535 | continue; | |
4536 | list_del(&cur->node); | |
4537 | kfree(cur); | |
4538 | break; | |
4539 | } | |
4540 | spin_unlock_irqrestore(&svm->ir_list_lock, flags); | |
4541 | } | |
4542 | ||
4543 | static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi) | |
4544 | { | |
4545 | int ret = 0; | |
4546 | unsigned long flags; | |
4547 | struct amd_svm_iommu_ir *ir; | |
4548 | ||
4549 | /** | |
4550 | * In some cases, the existing irte is updaed and re-set, | |
4551 | * so we need to check here if it's already been * added | |
4552 | * to the ir_list. | |
4553 | */ | |
4554 | if (pi->ir_data && (pi->prev_ga_tag != 0)) { | |
4555 | struct kvm *kvm = svm->vcpu.kvm; | |
4556 | u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag); | |
4557 | struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id); | |
4558 | struct vcpu_svm *prev_svm; | |
4559 | ||
4560 | if (!prev_vcpu) { | |
4561 | ret = -EINVAL; | |
4562 | goto out; | |
4563 | } | |
4564 | ||
4565 | prev_svm = to_svm(prev_vcpu); | |
4566 | svm_ir_list_del(prev_svm, pi); | |
4567 | } | |
4568 | ||
4569 | /** | |
4570 | * Allocating new amd_iommu_pi_data, which will get | |
4571 | * add to the per-vcpu ir_list. | |
4572 | */ | |
4573 | ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL); | |
4574 | if (!ir) { | |
4575 | ret = -ENOMEM; | |
4576 | goto out; | |
4577 | } | |
4578 | ir->data = pi->ir_data; | |
4579 | ||
4580 | spin_lock_irqsave(&svm->ir_list_lock, flags); | |
4581 | list_add(&ir->node, &svm->ir_list); | |
4582 | spin_unlock_irqrestore(&svm->ir_list_lock, flags); | |
4583 | out: | |
4584 | return ret; | |
4585 | } | |
4586 | ||
4587 | /** | |
4588 | * Note: | |
4589 | * The HW cannot support posting multicast/broadcast | |
4590 | * interrupts to a vCPU. So, we still use legacy interrupt | |
4591 | * remapping for these kind of interrupts. | |
4592 | * | |
4593 | * For lowest-priority interrupts, we only support | |
4594 | * those with single CPU as the destination, e.g. user | |
4595 | * configures the interrupts via /proc/irq or uses | |
4596 | * irqbalance to make the interrupts single-CPU. | |
4597 | */ | |
4598 | static int | |
4599 | get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, | |
4600 | struct vcpu_data *vcpu_info, struct vcpu_svm **svm) | |
4601 | { | |
4602 | struct kvm_lapic_irq irq; | |
4603 | struct kvm_vcpu *vcpu = NULL; | |
4604 | ||
4605 | kvm_set_msi_irq(kvm, e, &irq); | |
4606 | ||
4607 | if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) { | |
4608 | pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n", | |
4609 | __func__, irq.vector); | |
4610 | return -1; | |
4611 | } | |
4612 | ||
4613 | pr_debug("SVM: %s: use GA mode for irq %u\n", __func__, | |
4614 | irq.vector); | |
4615 | *svm = to_svm(vcpu); | |
d0ec49d4 | 4616 | vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page)); |
411b44ba SS |
4617 | vcpu_info->vector = irq.vector; |
4618 | ||
4619 | return 0; | |
4620 | } | |
4621 | ||
4622 | /* | |
4623 | * svm_update_pi_irte - set IRTE for Posted-Interrupts | |
4624 | * | |
4625 | * @kvm: kvm | |
4626 | * @host_irq: host irq of the interrupt | |
4627 | * @guest_irq: gsi of the interrupt | |
4628 | * @set: set or unset PI | |
4629 | * returns 0 on success, < 0 on failure | |
4630 | */ | |
4631 | static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq, | |
4632 | uint32_t guest_irq, bool set) | |
4633 | { | |
4634 | struct kvm_kernel_irq_routing_entry *e; | |
4635 | struct kvm_irq_routing_table *irq_rt; | |
4636 | int idx, ret = -EINVAL; | |
4637 | ||
4638 | if (!kvm_arch_has_assigned_device(kvm) || | |
4639 | !irq_remapping_cap(IRQ_POSTING_CAP)) | |
4640 | return 0; | |
4641 | ||
4642 | pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n", | |
4643 | __func__, host_irq, guest_irq, set); | |
4644 | ||
4645 | idx = srcu_read_lock(&kvm->irq_srcu); | |
4646 | irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); | |
4647 | WARN_ON(guest_irq >= irq_rt->nr_rt_entries); | |
4648 | ||
4649 | hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { | |
4650 | struct vcpu_data vcpu_info; | |
4651 | struct vcpu_svm *svm = NULL; | |
4652 | ||
4653 | if (e->type != KVM_IRQ_ROUTING_MSI) | |
4654 | continue; | |
4655 | ||
4656 | /** | |
4657 | * Here, we setup with legacy mode in the following cases: | |
4658 | * 1. When cannot target interrupt to a specific vcpu. | |
4659 | * 2. Unsetting posted interrupt. | |
4660 | * 3. APIC virtialization is disabled for the vcpu. | |
4661 | */ | |
4662 | if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set && | |
4663 | kvm_vcpu_apicv_active(&svm->vcpu)) { | |
4664 | struct amd_iommu_pi_data pi; | |
4665 | ||
4666 | /* Try to enable guest_mode in IRTE */ | |
d0ec49d4 TL |
4667 | pi.base = __sme_set(page_to_phys(svm->avic_backing_page) & |
4668 | AVIC_HPA_MASK); | |
411b44ba SS |
4669 | pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id, |
4670 | svm->vcpu.vcpu_id); | |
4671 | pi.is_guest_mode = true; | |
4672 | pi.vcpu_data = &vcpu_info; | |
4673 | ret = irq_set_vcpu_affinity(host_irq, &pi); | |
4674 | ||
4675 | /** | |
4676 | * Here, we successfully setting up vcpu affinity in | |
4677 | * IOMMU guest mode. Now, we need to store the posted | |
4678 | * interrupt information in a per-vcpu ir_list so that | |
4679 | * we can reference to them directly when we update vcpu | |
4680 | * scheduling information in IOMMU irte. | |
4681 | */ | |
4682 | if (!ret && pi.is_guest_mode) | |
4683 | svm_ir_list_add(svm, &pi); | |
4684 | } else { | |
4685 | /* Use legacy mode in IRTE */ | |
4686 | struct amd_iommu_pi_data pi; | |
4687 | ||
4688 | /** | |
4689 | * Here, pi is used to: | |
4690 | * - Tell IOMMU to use legacy mode for this interrupt. | |
4691 | * - Retrieve ga_tag of prior interrupt remapping data. | |
4692 | */ | |
4693 | pi.is_guest_mode = false; | |
4694 | ret = irq_set_vcpu_affinity(host_irq, &pi); | |
4695 | ||
4696 | /** | |
4697 | * Check if the posted interrupt was previously | |
4698 | * setup with the guest_mode by checking if the ga_tag | |
4699 | * was cached. If so, we need to clean up the per-vcpu | |
4700 | * ir_list. | |
4701 | */ | |
4702 | if (!ret && pi.prev_ga_tag) { | |
4703 | int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag); | |
4704 | struct kvm_vcpu *vcpu; | |
4705 | ||
4706 | vcpu = kvm_get_vcpu_by_id(kvm, id); | |
4707 | if (vcpu) | |
4708 | svm_ir_list_del(to_svm(vcpu), &pi); | |
4709 | } | |
4710 | } | |
4711 | ||
4712 | if (!ret && svm) { | |
4713 | trace_kvm_pi_irte_update(svm->vcpu.vcpu_id, | |
4714 | host_irq, e->gsi, | |
4715 | vcpu_info.vector, | |
4716 | vcpu_info.pi_desc_addr, set); | |
4717 | } | |
4718 | ||
4719 | if (ret < 0) { | |
4720 | pr_err("%s: failed to update PI IRTE\n", __func__); | |
4721 | goto out; | |
4722 | } | |
4723 | } | |
4724 | ||
4725 | ret = 0; | |
4726 | out: | |
4727 | srcu_read_unlock(&kvm->irq_srcu, idx); | |
4728 | return ret; | |
4729 | } | |
4730 | ||
95ba8273 GN |
4731 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
4732 | { | |
4733 | struct vcpu_svm *svm = to_svm(vcpu); | |
4734 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
4735 | int ret; |
4736 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
4737 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
4738 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
4739 | ||
4740 | return ret; | |
aaacfc9a JR |
4741 | } |
4742 | ||
3cfc3092 JK |
4743 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
4744 | { | |
4745 | struct vcpu_svm *svm = to_svm(vcpu); | |
4746 | ||
4747 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
4748 | } | |
4749 | ||
4750 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
4751 | { | |
4752 | struct vcpu_svm *svm = to_svm(vcpu); | |
4753 | ||
4754 | if (masked) { | |
4755 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 4756 | set_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
4757 | } else { |
4758 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
8a05a1b8 | 4759 | clr_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
4760 | } |
4761 | } | |
4762 | ||
78646121 GN |
4763 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
4764 | { | |
4765 | struct vcpu_svm *svm = to_svm(vcpu); | |
4766 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
4767 | int ret; |
4768 | ||
4769 | if (!gif_set(svm) || | |
4770 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
4771 | return 0; | |
4772 | ||
f6e78475 | 4773 | ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF); |
7fcdb510 | 4774 | |
2030753d | 4775 | if (is_guest_mode(vcpu)) |
7fcdb510 JR |
4776 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); |
4777 | ||
4778 | return ret; | |
78646121 GN |
4779 | } |
4780 | ||
c9a7953f | 4781 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 4782 | { |
219b65dc | 4783 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 4784 | |
340d3bc3 SS |
4785 | if (kvm_vcpu_apicv_active(vcpu)) |
4786 | return; | |
4787 | ||
e0231715 JR |
4788 | /* |
4789 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
4790 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
4791 | * get that intercept, this function will be called again though and | |
640bd6e5 JN |
4792 | * we'll get the vintr intercept. However, if the vGIF feature is |
4793 | * enabled, the STGI interception will not occur. Enable the irq | |
4794 | * window under the assumption that the hardware will set the GIF. | |
e0231715 | 4795 | */ |
640bd6e5 | 4796 | if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) { |
219b65dc AG |
4797 | svm_set_vintr(svm); |
4798 | svm_inject_irq(svm, 0x0); | |
4799 | } | |
85f455f7 ED |
4800 | } |
4801 | ||
c9a7953f | 4802 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 4803 | { |
04d2cc77 | 4804 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 4805 | |
44c11430 GN |
4806 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
4807 | == HF_NMI_MASK) | |
c9a7953f | 4808 | return; /* IRET will cause a vm exit */ |
44c11430 | 4809 | |
640bd6e5 JN |
4810 | if (!gif_set(svm)) { |
4811 | if (vgif_enabled(svm)) | |
4812 | set_intercept(svm, INTERCEPT_STGI); | |
1a5e1852 | 4813 | return; /* STGI will cause a vm exit */ |
640bd6e5 | 4814 | } |
1a5e1852 LP |
4815 | |
4816 | if (svm->nested.exit_required) | |
4817 | return; /* we're not going to run the guest yet */ | |
4818 | ||
e0231715 JR |
4819 | /* |
4820 | * Something prevents NMI from been injected. Single step over possible | |
4821 | * problem (IRET or exception injection or interrupt shadow) | |
4822 | */ | |
ab2f4d73 | 4823 | svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu); |
6be7d306 | 4824 | svm->nmi_singlestep = true; |
44c11430 | 4825 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
c1150d8c DL |
4826 | } |
4827 | ||
cbc94022 IE |
4828 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
4829 | { | |
4830 | return 0; | |
4831 | } | |
4832 | ||
d9e368d6 AK |
4833 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
4834 | { | |
38e5e92f JR |
4835 | struct vcpu_svm *svm = to_svm(vcpu); |
4836 | ||
4837 | if (static_cpu_has(X86_FEATURE_FLUSHBYASID)) | |
4838 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; | |
4839 | else | |
4840 | svm->asid_generation--; | |
d9e368d6 AK |
4841 | } |
4842 | ||
04d2cc77 AK |
4843 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
4844 | { | |
4845 | } | |
4846 | ||
d7bf8221 JR |
4847 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
4848 | { | |
4849 | struct vcpu_svm *svm = to_svm(vcpu); | |
4850 | ||
3bbf3565 | 4851 | if (svm_nested_virtualize_tpr(vcpu)) |
88ab24ad JR |
4852 | return; |
4853 | ||
4ee546b4 | 4854 | if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) { |
d7bf8221 | 4855 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; |
615d5193 | 4856 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
4857 | } |
4858 | } | |
4859 | ||
649d6864 JR |
4860 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
4861 | { | |
4862 | struct vcpu_svm *svm = to_svm(vcpu); | |
4863 | u64 cr8; | |
4864 | ||
3bbf3565 SS |
4865 | if (svm_nested_virtualize_tpr(vcpu) || |
4866 | kvm_vcpu_apicv_active(vcpu)) | |
88ab24ad JR |
4867 | return; |
4868 | ||
649d6864 JR |
4869 | cr8 = kvm_get_cr8(vcpu); |
4870 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
4871 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
4872 | } | |
4873 | ||
9222be18 GN |
4874 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
4875 | { | |
4876 | u8 vector; | |
4877 | int type; | |
4878 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
4879 | unsigned int3_injected = svm->int3_injected; |
4880 | ||
4881 | svm->int3_injected = 0; | |
9222be18 | 4882 | |
bd3d1ec3 AK |
4883 | /* |
4884 | * If we've made progress since setting HF_IRET_MASK, we've | |
4885 | * executed an IRET and can allow NMI injection. | |
4886 | */ | |
4887 | if ((svm->vcpu.arch.hflags & HF_IRET_MASK) | |
4888 | && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) { | |
44c11430 | 4889 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); |
3842d135 AK |
4890 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
4891 | } | |
44c11430 | 4892 | |
9222be18 GN |
4893 | svm->vcpu.arch.nmi_injected = false; |
4894 | kvm_clear_exception_queue(&svm->vcpu); | |
4895 | kvm_clear_interrupt_queue(&svm->vcpu); | |
4896 | ||
4897 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
4898 | return; | |
4899 | ||
3842d135 AK |
4900 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
4901 | ||
9222be18 GN |
4902 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; |
4903 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
4904 | ||
4905 | switch (type) { | |
4906 | case SVM_EXITINTINFO_TYPE_NMI: | |
4907 | svm->vcpu.arch.nmi_injected = true; | |
4908 | break; | |
4909 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
4910 | /* |
4911 | * In case of software exceptions, do not reinject the vector, | |
4912 | * but re-execute the instruction instead. Rewind RIP first | |
4913 | * if we emulated INT3 before. | |
4914 | */ | |
4915 | if (kvm_exception_is_soft(vector)) { | |
4916 | if (vector == BP_VECTOR && int3_injected && | |
4917 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
4918 | kvm_rip_write(&svm->vcpu, | |
4919 | kvm_rip_read(&svm->vcpu) - | |
4920 | int3_injected); | |
9222be18 | 4921 | break; |
66b7138f | 4922 | } |
9222be18 GN |
4923 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
4924 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 4925 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
4926 | |
4927 | } else | |
ce7ddec4 | 4928 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
4929 | break; |
4930 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 4931 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
4932 | break; |
4933 | default: | |
4934 | break; | |
4935 | } | |
4936 | } | |
4937 | ||
b463a6f7 AK |
4938 | static void svm_cancel_injection(struct kvm_vcpu *vcpu) |
4939 | { | |
4940 | struct vcpu_svm *svm = to_svm(vcpu); | |
4941 | struct vmcb_control_area *control = &svm->vmcb->control; | |
4942 | ||
4943 | control->exit_int_info = control->event_inj; | |
4944 | control->exit_int_info_err = control->event_inj_err; | |
4945 | control->event_inj = 0; | |
4946 | svm_complete_interrupts(svm); | |
4947 | } | |
4948 | ||
851ba692 | 4949 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 4950 | { |
a2fa3e9f | 4951 | struct vcpu_svm *svm = to_svm(vcpu); |
d9e368d6 | 4952 | |
2041a06a JR |
4953 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
4954 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
4955 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
4956 | ||
cd3ff653 JR |
4957 | /* |
4958 | * A vmexit emulation is required before the vcpu can be executed | |
4959 | * again. | |
4960 | */ | |
4961 | if (unlikely(svm->nested.exit_required)) | |
4962 | return; | |
4963 | ||
a12713c2 LP |
4964 | /* |
4965 | * Disable singlestep if we're injecting an interrupt/exception. | |
4966 | * We don't want our modified rflags to be pushed on the stack where | |
4967 | * we might not be able to easily reset them if we disabled NMI | |
4968 | * singlestep later. | |
4969 | */ | |
4970 | if (svm->nmi_singlestep && svm->vmcb->control.event_inj) { | |
4971 | /* | |
4972 | * Event injection happens before external interrupts cause a | |
4973 | * vmexit and interrupts are disabled here, so smp_send_reschedule | |
4974 | * is enough to force an immediate vmexit. | |
4975 | */ | |
4976 | disable_nmi_singlestep(svm); | |
4977 | smp_send_reschedule(vcpu->cpu); | |
4978 | } | |
4979 | ||
e756fc62 | 4980 | pre_svm_run(svm); |
6aa8b732 | 4981 | |
649d6864 JR |
4982 | sync_lapic_to_cr8(vcpu); |
4983 | ||
cda0ffdd | 4984 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 4985 | |
04d2cc77 AK |
4986 | clgi(); |
4987 | ||
4988 | local_irq_enable(); | |
36241b8c | 4989 | |
6aa8b732 | 4990 | asm volatile ( |
7454766f AK |
4991 | "push %%" _ASM_BP "; \n\t" |
4992 | "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t" | |
4993 | "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t" | |
4994 | "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t" | |
4995 | "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t" | |
4996 | "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t" | |
4997 | "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 4998 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
4999 | "mov %c[r8](%[svm]), %%r8 \n\t" |
5000 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
5001 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
5002 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
5003 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
5004 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
5005 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
5006 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
5007 | #endif |
5008 | ||
6aa8b732 | 5009 | /* Enter guest mode */ |
7454766f AK |
5010 | "push %%" _ASM_AX " \n\t" |
5011 | "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t" | |
4ecac3fd AK |
5012 | __ex(SVM_VMLOAD) "\n\t" |
5013 | __ex(SVM_VMRUN) "\n\t" | |
5014 | __ex(SVM_VMSAVE) "\n\t" | |
7454766f | 5015 | "pop %%" _ASM_AX " \n\t" |
6aa8b732 AK |
5016 | |
5017 | /* Save guest registers, load host registers */ | |
7454766f AK |
5018 | "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t" |
5019 | "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t" | |
5020 | "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t" | |
5021 | "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t" | |
5022 | "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t" | |
5023 | "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 5024 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
5025 | "mov %%r8, %c[r8](%[svm]) \n\t" |
5026 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
5027 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
5028 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
5029 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
5030 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
5031 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
5032 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 5033 | #endif |
7454766f | 5034 | "pop %%" _ASM_BP |
6aa8b732 | 5035 | : |
fb3f0f51 | 5036 | : [svm]"a"(svm), |
6aa8b732 | 5037 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
5038 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
5039 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
5040 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
5041 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
5042 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
5043 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 5044 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
5045 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
5046 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
5047 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
5048 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
5049 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
5050 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
5051 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
5052 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 5053 | #endif |
54a08c04 LV |
5054 | : "cc", "memory" |
5055 | #ifdef CONFIG_X86_64 | |
7454766f | 5056 | , "rbx", "rcx", "rdx", "rsi", "rdi" |
54a08c04 | 5057 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
7454766f AK |
5058 | #else |
5059 | , "ebx", "ecx", "edx", "esi", "edi" | |
54a08c04 LV |
5060 | #endif |
5061 | ); | |
6aa8b732 | 5062 | |
82ca2d10 AK |
5063 | #ifdef CONFIG_X86_64 |
5064 | wrmsrl(MSR_GS_BASE, svm->host.gs_base); | |
5065 | #else | |
dacccfdd | 5066 | loadsegment(fs, svm->host.fs); |
831ca609 AK |
5067 | #ifndef CONFIG_X86_32_LAZY_GS |
5068 | loadsegment(gs, svm->host.gs); | |
5069 | #endif | |
9581d442 | 5070 | #endif |
6aa8b732 AK |
5071 | |
5072 | reload_tss(vcpu); | |
5073 | ||
56ba47dd AK |
5074 | local_irq_disable(); |
5075 | ||
13c34e07 AK |
5076 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
5077 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
5078 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
5079 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
5080 | ||
3781c01c JR |
5081 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) |
5082 | kvm_before_handle_nmi(&svm->vcpu); | |
5083 | ||
5084 | stgi(); | |
5085 | ||
5086 | /* Any pending NMI will happen here */ | |
5087 | ||
5088 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) | |
5089 | kvm_after_handle_nmi(&svm->vcpu); | |
5090 | ||
d7bf8221 JR |
5091 | sync_cr8_to_lapic(vcpu); |
5092 | ||
a2fa3e9f | 5093 | svm->next_rip = 0; |
9222be18 | 5094 | |
38e5e92f JR |
5095 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
5096 | ||
631bc487 GN |
5097 | /* if exit due to PF check for async PF */ |
5098 | if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
1261bfa3 | 5099 | svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); |
631bc487 | 5100 | |
6de4f3ad AK |
5101 | if (npt_enabled) { |
5102 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
5103 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
5104 | } | |
fe5913e4 JR |
5105 | |
5106 | /* | |
5107 | * We need to handle MC intercepts here before the vcpu has a chance to | |
5108 | * change the physical cpu | |
5109 | */ | |
5110 | if (unlikely(svm->vmcb->control.exit_code == | |
5111 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
5112 | svm_handle_mce(svm); | |
8d28fec4 RJ |
5113 | |
5114 | mark_all_clean(svm->vmcb); | |
6aa8b732 | 5115 | } |
c207aee4 | 5116 | STACK_FRAME_NON_STANDARD(svm_vcpu_run); |
6aa8b732 | 5117 | |
6aa8b732 AK |
5118 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
5119 | { | |
a2fa3e9f GH |
5120 | struct vcpu_svm *svm = to_svm(vcpu); |
5121 | ||
d0ec49d4 | 5122 | svm->vmcb->save.cr3 = __sme_set(root); |
dcca1a65 | 5123 | mark_dirty(svm->vmcb, VMCB_CR); |
f40f6a45 | 5124 | svm_flush_tlb(vcpu); |
6aa8b732 AK |
5125 | } |
5126 | ||
1c97f0a0 JR |
5127 | static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
5128 | { | |
5129 | struct vcpu_svm *svm = to_svm(vcpu); | |
5130 | ||
d0ec49d4 | 5131 | svm->vmcb->control.nested_cr3 = __sme_set(root); |
b2747166 | 5132 | mark_dirty(svm->vmcb, VMCB_NPT); |
1c97f0a0 JR |
5133 | |
5134 | /* Also sync guest cr3 here in case we live migrate */ | |
9f8fe504 | 5135 | svm->vmcb->save.cr3 = kvm_read_cr3(vcpu); |
dcca1a65 | 5136 | mark_dirty(svm->vmcb, VMCB_CR); |
1c97f0a0 | 5137 | |
f40f6a45 | 5138 | svm_flush_tlb(vcpu); |
1c97f0a0 JR |
5139 | } |
5140 | ||
6aa8b732 AK |
5141 | static int is_disabled(void) |
5142 | { | |
6031a61c JR |
5143 | u64 vm_cr; |
5144 | ||
5145 | rdmsrl(MSR_VM_CR, vm_cr); | |
5146 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
5147 | return 1; | |
5148 | ||
6aa8b732 AK |
5149 | return 0; |
5150 | } | |
5151 | ||
102d8325 IM |
5152 | static void |
5153 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
5154 | { | |
5155 | /* | |
5156 | * Patch in the VMMCALL instruction: | |
5157 | */ | |
5158 | hypercall[0] = 0x0f; | |
5159 | hypercall[1] = 0x01; | |
5160 | hypercall[2] = 0xd9; | |
102d8325 IM |
5161 | } |
5162 | ||
002c7f7c YS |
5163 | static void svm_check_processor_compat(void *rtn) |
5164 | { | |
5165 | *(int *)rtn = 0; | |
5166 | } | |
5167 | ||
774ead3a AK |
5168 | static bool svm_cpu_has_accelerated_tpr(void) |
5169 | { | |
5170 | return false; | |
5171 | } | |
5172 | ||
6d396b55 PB |
5173 | static bool svm_has_high_real_mode_segbase(void) |
5174 | { | |
5175 | return true; | |
5176 | } | |
5177 | ||
fc07e76a PB |
5178 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
5179 | { | |
5180 | return 0; | |
5181 | } | |
5182 | ||
0e851880 SY |
5183 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
5184 | { | |
6092d3d3 JR |
5185 | struct vcpu_svm *svm = to_svm(vcpu); |
5186 | ||
5187 | /* Update nrips enabled cache */ | |
d6321d49 | 5188 | svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS); |
46781eae SS |
5189 | |
5190 | if (!kvm_vcpu_apicv_active(vcpu)) | |
5191 | return; | |
5192 | ||
1b4d56b8 | 5193 | guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC); |
0e851880 SY |
5194 | } |
5195 | ||
d4330ef2 JR |
5196 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
5197 | { | |
c2c63a49 | 5198 | switch (func) { |
46781eae SS |
5199 | case 0x1: |
5200 | if (avic) | |
5201 | entry->ecx &= ~bit(X86_FEATURE_X2APIC); | |
5202 | break; | |
4c62a2dc JR |
5203 | case 0x80000001: |
5204 | if (nested) | |
5205 | entry->ecx |= (1 << 2); /* Set SVM bit */ | |
5206 | break; | |
c2c63a49 JR |
5207 | case 0x8000000A: |
5208 | entry->eax = 1; /* SVM revision 1 */ | |
5209 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
5210 | ASID emulation to nested SVM */ | |
5211 | entry->ecx = 0; /* Reserved */ | |
7a190667 JR |
5212 | entry->edx = 0; /* Per default do not support any |
5213 | additional features */ | |
5214 | ||
5215 | /* Support next_rip if host supports it */ | |
2a6b20b8 | 5216 | if (boot_cpu_has(X86_FEATURE_NRIPS)) |
7a190667 | 5217 | entry->edx |= SVM_FEATURE_NRIP; |
c2c63a49 | 5218 | |
3d4aeaad JR |
5219 | /* Support NPT for the guest if enabled */ |
5220 | if (npt_enabled) | |
5221 | entry->edx |= SVM_FEATURE_NPT; | |
5222 | ||
c2c63a49 | 5223 | break; |
8765d753 BS |
5224 | case 0x8000001F: |
5225 | /* Support memory encryption cpuid if host supports it */ | |
5226 | if (boot_cpu_has(X86_FEATURE_SEV)) | |
5227 | cpuid(0x8000001f, &entry->eax, &entry->ebx, | |
5228 | &entry->ecx, &entry->edx); | |
5229 | ||
c2c63a49 | 5230 | } |
d4330ef2 JR |
5231 | } |
5232 | ||
17cc3935 | 5233 | static int svm_get_lpage_level(void) |
344f414f | 5234 | { |
17cc3935 | 5235 | return PT_PDPE_LEVEL; |
344f414f JR |
5236 | } |
5237 | ||
4e47c7a6 SY |
5238 | static bool svm_rdtscp_supported(void) |
5239 | { | |
46896c73 | 5240 | return boot_cpu_has(X86_FEATURE_RDTSCP); |
4e47c7a6 SY |
5241 | } |
5242 | ||
ad756a16 MJ |
5243 | static bool svm_invpcid_supported(void) |
5244 | { | |
5245 | return false; | |
5246 | } | |
5247 | ||
93c4adc7 PB |
5248 | static bool svm_mpx_supported(void) |
5249 | { | |
5250 | return false; | |
5251 | } | |
5252 | ||
55412b2e WL |
5253 | static bool svm_xsaves_supported(void) |
5254 | { | |
5255 | return false; | |
5256 | } | |
5257 | ||
f5f48ee1 SY |
5258 | static bool svm_has_wbinvd_exit(void) |
5259 | { | |
5260 | return true; | |
5261 | } | |
5262 | ||
8061252e | 5263 | #define PRE_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 5264 | .stage = X86_ICPT_PRE_EXCEPT, } |
cfec82cb | 5265 | #define POST_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 5266 | .stage = X86_ICPT_POST_EXCEPT, } |
d7eb8203 | 5267 | #define POST_MEM(exit) { .exit_code = (exit), \ |
40e19b51 | 5268 | .stage = X86_ICPT_POST_MEMACCESS, } |
cfec82cb | 5269 | |
09941fbb | 5270 | static const struct __x86_intercept { |
cfec82cb JR |
5271 | u32 exit_code; |
5272 | enum x86_intercept_stage stage; | |
cfec82cb JR |
5273 | } x86_intercept_map[] = { |
5274 | [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0), | |
5275 | [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0), | |
5276 | [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0), | |
5277 | [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0), | |
5278 | [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0), | |
3b88e41a JR |
5279 | [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0), |
5280 | [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0), | |
dee6bb70 JR |
5281 | [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ), |
5282 | [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ), | |
5283 | [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE), | |
5284 | [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE), | |
5285 | [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ), | |
5286 | [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ), | |
5287 | [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE), | |
5288 | [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE), | |
01de8b09 JR |
5289 | [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN), |
5290 | [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL), | |
5291 | [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD), | |
5292 | [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE), | |
5293 | [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI), | |
5294 | [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI), | |
5295 | [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT), | |
5296 | [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA), | |
d7eb8203 JR |
5297 | [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP), |
5298 | [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR), | |
5299 | [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT), | |
8061252e JR |
5300 | [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG), |
5301 | [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD), | |
5302 | [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD), | |
5303 | [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR), | |
5304 | [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC), | |
5305 | [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR), | |
5306 | [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC), | |
5307 | [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID), | |
5308 | [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM), | |
bf608f88 JR |
5309 | [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE), |
5310 | [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF), | |
5311 | [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF), | |
5312 | [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT), | |
5313 | [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET), | |
5314 | [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP), | |
5315 | [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT), | |
f6511935 JR |
5316 | [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO), |
5317 | [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO), | |
5318 | [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO), | |
5319 | [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO), | |
cfec82cb JR |
5320 | }; |
5321 | ||
8061252e | 5322 | #undef PRE_EX |
cfec82cb | 5323 | #undef POST_EX |
d7eb8203 | 5324 | #undef POST_MEM |
cfec82cb | 5325 | |
8a76d7f2 JR |
5326 | static int svm_check_intercept(struct kvm_vcpu *vcpu, |
5327 | struct x86_instruction_info *info, | |
5328 | enum x86_intercept_stage stage) | |
5329 | { | |
cfec82cb JR |
5330 | struct vcpu_svm *svm = to_svm(vcpu); |
5331 | int vmexit, ret = X86EMUL_CONTINUE; | |
5332 | struct __x86_intercept icpt_info; | |
5333 | struct vmcb *vmcb = svm->vmcb; | |
5334 | ||
5335 | if (info->intercept >= ARRAY_SIZE(x86_intercept_map)) | |
5336 | goto out; | |
5337 | ||
5338 | icpt_info = x86_intercept_map[info->intercept]; | |
5339 | ||
40e19b51 | 5340 | if (stage != icpt_info.stage) |
cfec82cb JR |
5341 | goto out; |
5342 | ||
5343 | switch (icpt_info.exit_code) { | |
5344 | case SVM_EXIT_READ_CR0: | |
5345 | if (info->intercept == x86_intercept_cr_read) | |
5346 | icpt_info.exit_code += info->modrm_reg; | |
5347 | break; | |
5348 | case SVM_EXIT_WRITE_CR0: { | |
5349 | unsigned long cr0, val; | |
5350 | u64 intercept; | |
5351 | ||
5352 | if (info->intercept == x86_intercept_cr_write) | |
5353 | icpt_info.exit_code += info->modrm_reg; | |
5354 | ||
62baf44c JK |
5355 | if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 || |
5356 | info->intercept == x86_intercept_clts) | |
cfec82cb JR |
5357 | break; |
5358 | ||
5359 | intercept = svm->nested.intercept; | |
5360 | ||
5361 | if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))) | |
5362 | break; | |
5363 | ||
5364 | cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK; | |
5365 | val = info->src_val & ~SVM_CR0_SELECTIVE_MASK; | |
5366 | ||
5367 | if (info->intercept == x86_intercept_lmsw) { | |
5368 | cr0 &= 0xfUL; | |
5369 | val &= 0xfUL; | |
5370 | /* lmsw can't clear PE - catch this here */ | |
5371 | if (cr0 & X86_CR0_PE) | |
5372 | val |= X86_CR0_PE; | |
5373 | } | |
5374 | ||
5375 | if (cr0 ^ val) | |
5376 | icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
5377 | ||
5378 | break; | |
5379 | } | |
3b88e41a JR |
5380 | case SVM_EXIT_READ_DR0: |
5381 | case SVM_EXIT_WRITE_DR0: | |
5382 | icpt_info.exit_code += info->modrm_reg; | |
5383 | break; | |
8061252e JR |
5384 | case SVM_EXIT_MSR: |
5385 | if (info->intercept == x86_intercept_wrmsr) | |
5386 | vmcb->control.exit_info_1 = 1; | |
5387 | else | |
5388 | vmcb->control.exit_info_1 = 0; | |
5389 | break; | |
bf608f88 JR |
5390 | case SVM_EXIT_PAUSE: |
5391 | /* | |
5392 | * We get this for NOP only, but pause | |
5393 | * is rep not, check this here | |
5394 | */ | |
5395 | if (info->rep_prefix != REPE_PREFIX) | |
5396 | goto out; | |
49a8afca | 5397 | break; |
f6511935 JR |
5398 | case SVM_EXIT_IOIO: { |
5399 | u64 exit_info; | |
5400 | u32 bytes; | |
5401 | ||
f6511935 JR |
5402 | if (info->intercept == x86_intercept_in || |
5403 | info->intercept == x86_intercept_ins) { | |
6cbc5f5a JK |
5404 | exit_info = ((info->src_val & 0xffff) << 16) | |
5405 | SVM_IOIO_TYPE_MASK; | |
f6511935 | 5406 | bytes = info->dst_bytes; |
6493f157 | 5407 | } else { |
6cbc5f5a | 5408 | exit_info = (info->dst_val & 0xffff) << 16; |
6493f157 | 5409 | bytes = info->src_bytes; |
f6511935 JR |
5410 | } |
5411 | ||
5412 | if (info->intercept == x86_intercept_outs || | |
5413 | info->intercept == x86_intercept_ins) | |
5414 | exit_info |= SVM_IOIO_STR_MASK; | |
5415 | ||
5416 | if (info->rep_prefix) | |
5417 | exit_info |= SVM_IOIO_REP_MASK; | |
5418 | ||
5419 | bytes = min(bytes, 4u); | |
5420 | ||
5421 | exit_info |= bytes << SVM_IOIO_SIZE_SHIFT; | |
5422 | ||
5423 | exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1); | |
5424 | ||
5425 | vmcb->control.exit_info_1 = exit_info; | |
5426 | vmcb->control.exit_info_2 = info->next_rip; | |
5427 | ||
5428 | break; | |
5429 | } | |
cfec82cb JR |
5430 | default: |
5431 | break; | |
5432 | } | |
5433 | ||
f104765b BD |
5434 | /* TODO: Advertise NRIPS to guest hypervisor unconditionally */ |
5435 | if (static_cpu_has(X86_FEATURE_NRIPS)) | |
5436 | vmcb->control.next_rip = info->next_rip; | |
cfec82cb JR |
5437 | vmcb->control.exit_code = icpt_info.exit_code; |
5438 | vmexit = nested_svm_exit_handled(svm); | |
5439 | ||
5440 | ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED | |
5441 | : X86EMUL_CONTINUE; | |
5442 | ||
5443 | out: | |
5444 | return ret; | |
8a76d7f2 JR |
5445 | } |
5446 | ||
a547c6db YZ |
5447 | static void svm_handle_external_intr(struct kvm_vcpu *vcpu) |
5448 | { | |
5449 | local_irq_enable(); | |
f2485b3e PB |
5450 | /* |
5451 | * We must have an instruction with interrupts enabled, so | |
5452 | * the timer interrupt isn't delayed by the interrupt shadow. | |
5453 | */ | |
5454 | asm("nop"); | |
5455 | local_irq_disable(); | |
a547c6db YZ |
5456 | } |
5457 | ||
ae97a3b8 RK |
5458 | static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu) |
5459 | { | |
5460 | } | |
5461 | ||
be8ca170 SS |
5462 | static inline void avic_post_state_restore(struct kvm_vcpu *vcpu) |
5463 | { | |
5464 | if (avic_handle_apic_id_update(vcpu) != 0) | |
5465 | return; | |
5466 | if (avic_handle_dfr_update(vcpu) != 0) | |
5467 | return; | |
5468 | avic_handle_ldr_update(vcpu); | |
5469 | } | |
5470 | ||
74f16909 BP |
5471 | static void svm_setup_mce(struct kvm_vcpu *vcpu) |
5472 | { | |
5473 | /* [63:9] are reserved. */ | |
5474 | vcpu->arch.mcg_cap &= 0x1ff; | |
5475 | } | |
5476 | ||
72d7b374 LP |
5477 | static int svm_smi_allowed(struct kvm_vcpu *vcpu) |
5478 | { | |
05cade71 LP |
5479 | struct vcpu_svm *svm = to_svm(vcpu); |
5480 | ||
5481 | /* Per APM Vol.2 15.22.2 "Response to SMI" */ | |
5482 | if (!gif_set(svm)) | |
5483 | return 0; | |
5484 | ||
5485 | if (is_guest_mode(&svm->vcpu) && | |
5486 | svm->nested.intercept & (1ULL << INTERCEPT_SMI)) { | |
5487 | /* TODO: Might need to set exit_info_1 and exit_info_2 here */ | |
5488 | svm->vmcb->control.exit_code = SVM_EXIT_SMI; | |
5489 | svm->nested.exit_required = true; | |
5490 | return 0; | |
5491 | } | |
5492 | ||
72d7b374 LP |
5493 | return 1; |
5494 | } | |
5495 | ||
0234bf88 LP |
5496 | static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) |
5497 | { | |
05cade71 LP |
5498 | struct vcpu_svm *svm = to_svm(vcpu); |
5499 | int ret; | |
5500 | ||
5501 | if (is_guest_mode(vcpu)) { | |
5502 | /* FED8h - SVM Guest */ | |
5503 | put_smstate(u64, smstate, 0x7ed8, 1); | |
5504 | /* FEE0h - SVM Guest VMCB Physical Address */ | |
5505 | put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb); | |
5506 | ||
5507 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; | |
5508 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
5509 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
5510 | ||
5511 | ret = nested_svm_vmexit(svm); | |
5512 | if (ret) | |
5513 | return ret; | |
5514 | } | |
0234bf88 LP |
5515 | return 0; |
5516 | } | |
5517 | ||
5518 | static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase) | |
5519 | { | |
05cade71 LP |
5520 | struct vcpu_svm *svm = to_svm(vcpu); |
5521 | struct vmcb *nested_vmcb; | |
5522 | struct page *page; | |
5523 | struct { | |
5524 | u64 guest; | |
5525 | u64 vmcb; | |
5526 | } svm_state_save; | |
5527 | int ret; | |
5528 | ||
5529 | ret = kvm_vcpu_read_guest(vcpu, smbase + 0xfed8, &svm_state_save, | |
5530 | sizeof(svm_state_save)); | |
5531 | if (ret) | |
5532 | return ret; | |
5533 | ||
5534 | if (svm_state_save.guest) { | |
5535 | vcpu->arch.hflags &= ~HF_SMM_MASK; | |
5536 | nested_vmcb = nested_svm_map(svm, svm_state_save.vmcb, &page); | |
5537 | if (nested_vmcb) | |
5538 | enter_svm_guest_mode(svm, svm_state_save.vmcb, nested_vmcb, page); | |
5539 | else | |
5540 | ret = 1; | |
5541 | vcpu->arch.hflags |= HF_SMM_MASK; | |
5542 | } | |
5543 | return ret; | |
0234bf88 LP |
5544 | } |
5545 | ||
cc3d967f LP |
5546 | static int enable_smi_window(struct kvm_vcpu *vcpu) |
5547 | { | |
5548 | struct vcpu_svm *svm = to_svm(vcpu); | |
5549 | ||
5550 | if (!gif_set(svm)) { | |
5551 | if (vgif_enabled(svm)) | |
5552 | set_intercept(svm, INTERCEPT_STGI); | |
5553 | /* STGI will cause a vm exit */ | |
5554 | return 1; | |
5555 | } | |
5556 | return 0; | |
5557 | } | |
5558 | ||
404f6aac | 5559 | static struct kvm_x86_ops svm_x86_ops __ro_after_init = { |
6aa8b732 AK |
5560 | .cpu_has_kvm_support = has_svm, |
5561 | .disabled_by_bios = is_disabled, | |
5562 | .hardware_setup = svm_hardware_setup, | |
5563 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 5564 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
5565 | .hardware_enable = svm_hardware_enable, |
5566 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 5567 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6d396b55 | 5568 | .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase, |
6aa8b732 AK |
5569 | |
5570 | .vcpu_create = svm_create_vcpu, | |
5571 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 5572 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 5573 | |
44a95dae SS |
5574 | .vm_init = avic_vm_init, |
5575 | .vm_destroy = avic_vm_destroy, | |
5576 | ||
04d2cc77 | 5577 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
5578 | .vcpu_load = svm_vcpu_load, |
5579 | .vcpu_put = svm_vcpu_put, | |
8221c137 SS |
5580 | .vcpu_blocking = svm_vcpu_blocking, |
5581 | .vcpu_unblocking = svm_vcpu_unblocking, | |
6aa8b732 | 5582 | |
a96036b8 | 5583 | .update_bp_intercept = update_bp_intercept, |
6aa8b732 AK |
5584 | .get_msr = svm_get_msr, |
5585 | .set_msr = svm_set_msr, | |
5586 | .get_segment_base = svm_get_segment_base, | |
5587 | .get_segment = svm_get_segment, | |
5588 | .set_segment = svm_set_segment, | |
2e4d2653 | 5589 | .get_cpl = svm_get_cpl, |
1747fb71 | 5590 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 5591 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
aff48baa | 5592 | .decache_cr3 = svm_decache_cr3, |
25c4c276 | 5593 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 5594 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
5595 | .set_cr3 = svm_set_cr3, |
5596 | .set_cr4 = svm_set_cr4, | |
5597 | .set_efer = svm_set_efer, | |
5598 | .get_idt = svm_get_idt, | |
5599 | .set_idt = svm_set_idt, | |
5600 | .get_gdt = svm_get_gdt, | |
5601 | .set_gdt = svm_set_gdt, | |
73aaf249 JK |
5602 | .get_dr6 = svm_get_dr6, |
5603 | .set_dr6 = svm_set_dr6, | |
020df079 | 5604 | .set_dr7 = svm_set_dr7, |
facb0139 | 5605 | .sync_dirty_debug_regs = svm_sync_dirty_debug_regs, |
6de4f3ad | 5606 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
5607 | .get_rflags = svm_get_rflags, |
5608 | .set_rflags = svm_set_rflags, | |
be94f6b7 | 5609 | |
6aa8b732 | 5610 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 5611 | |
6aa8b732 | 5612 | .run = svm_vcpu_run, |
04d2cc77 | 5613 | .handle_exit = handle_exit, |
6aa8b732 | 5614 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
5615 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
5616 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 5617 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 5618 | .set_irq = svm_set_irq, |
95ba8273 | 5619 | .set_nmi = svm_inject_nmi, |
298101da | 5620 | .queue_exception = svm_queue_exception, |
b463a6f7 | 5621 | .cancel_injection = svm_cancel_injection, |
78646121 | 5622 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 5623 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
5624 | .get_nmi_mask = svm_get_nmi_mask, |
5625 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
5626 | .enable_nmi_window = enable_nmi_window, |
5627 | .enable_irq_window = enable_irq_window, | |
5628 | .update_cr8_intercept = update_cr8_intercept, | |
8d14695f | 5629 | .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode, |
d62caabb AS |
5630 | .get_enable_apicv = svm_get_enable_apicv, |
5631 | .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl, | |
c7c9c56c | 5632 | .load_eoi_exitmap = svm_load_eoi_exitmap, |
44a95dae SS |
5633 | .hwapic_irr_update = svm_hwapic_irr_update, |
5634 | .hwapic_isr_update = svm_hwapic_isr_update, | |
be8ca170 | 5635 | .apicv_post_state_restore = avic_post_state_restore, |
cbc94022 IE |
5636 | |
5637 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 5638 | .get_tdp_level = get_npt_level, |
4b12f0de | 5639 | .get_mt_mask = svm_get_mt_mask, |
229456fc | 5640 | |
586f9607 | 5641 | .get_exit_info = svm_get_exit_info, |
586f9607 | 5642 | |
17cc3935 | 5643 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
5644 | |
5645 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
5646 | |
5647 | .rdtscp_supported = svm_rdtscp_supported, | |
ad756a16 | 5648 | .invpcid_supported = svm_invpcid_supported, |
93c4adc7 | 5649 | .mpx_supported = svm_mpx_supported, |
55412b2e | 5650 | .xsaves_supported = svm_xsaves_supported, |
d4330ef2 JR |
5651 | |
5652 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
5653 | |
5654 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
99e3e30a ZA |
5655 | |
5656 | .write_tsc_offset = svm_write_tsc_offset, | |
1c97f0a0 JR |
5657 | |
5658 | .set_tdp_cr3 = set_tdp_cr3, | |
8a76d7f2 JR |
5659 | |
5660 | .check_intercept = svm_check_intercept, | |
a547c6db | 5661 | .handle_external_intr = svm_handle_external_intr, |
ae97a3b8 RK |
5662 | |
5663 | .sched_in = svm_sched_in, | |
25462f7f WH |
5664 | |
5665 | .pmu_ops = &amd_pmu_ops, | |
340d3bc3 | 5666 | .deliver_posted_interrupt = svm_deliver_avic_intr, |
411b44ba | 5667 | .update_pi_irte = svm_update_pi_irte, |
74f16909 | 5668 | .setup_mce = svm_setup_mce, |
0234bf88 | 5669 | |
72d7b374 | 5670 | .smi_allowed = svm_smi_allowed, |
0234bf88 LP |
5671 | .pre_enter_smm = svm_pre_enter_smm, |
5672 | .pre_leave_smm = svm_pre_leave_smm, | |
cc3d967f | 5673 | .enable_smi_window = enable_smi_window, |
6aa8b732 AK |
5674 | }; |
5675 | ||
5676 | static int __init svm_init(void) | |
5677 | { | |
cb498ea2 | 5678 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 5679 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
5680 | } |
5681 | ||
5682 | static void __exit svm_exit(void) | |
5683 | { | |
cb498ea2 | 5684 | kvm_exit(); |
6aa8b732 AK |
5685 | } |
5686 | ||
5687 | module_init(svm_init) | |
5688 | module_exit(svm_exit) |