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KVM: SVM: Move fs/gs/ldt save/restore to heavyweight exit path
[linux-block.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
9611c187 7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
edf88417
AK		 17#include <linux/kvm_host.h>
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
5fdbf976 21#include "kvm_cache_regs.h"
fe4c7b19 22#include "x86.h"
e495606d 23
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/vmalloc.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
6aa8b732 31
67ec6607 32#include <asm/tlbflush.h>
e495606d 33#include <asm/desc.h>
631bc487 34#include <asm/kvm_para.h>
6aa8b732 35
63d1142f 36#include <asm/virtext.h>
229456fc 37#include "trace.h"
63d1142f 38
4ecac3fd
AK		 39#define __ex(x) __kvm_handle_fault_on_reboot(x)
40
6aa8b732
AK		 41MODULE_AUTHOR("Qumranet");
42MODULE_LICENSE("GPL");
43
44#define IOPM_ALLOC_ORDER 2
45#define MSRPM_ALLOC_ORDER 1
46
6aa8b732
AK		 47#define SEG_TYPE_LDT 2
48#define SEG_TYPE_BUSY_TSS16 3
49
6bc31bdc
AP		 50#define SVM_FEATURE_NPT (1 << 0)
51#define SVM_FEATURE_LBRV (1 << 1)
52#define SVM_FEATURE_SVML (1 << 2)
53#define SVM_FEATURE_NRIP (1 << 3)
54#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 55
410e4d57
JR		 56#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
59
24e09cbf
JR		 60#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
61
67ec6607
JR		 62static bool erratum_383_found __read_mostly;
63
6c8166a7
AK		 64static const u32 host_save_user_msrs[] = {
65#ifdef CONFIG_X86_64
66 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
67 MSR_FS_BASE,
68#endif
69 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
70};
71
72#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
73
74struct kvm_vcpu;
75
e6aa9abd
JR		 76struct nested_state {
77 struct vmcb *hsave;
78 u64 hsave_msr;
4a810181 79 u64 vm_cr_msr;
e6aa9abd
JR		 80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
ce2ac085 87 u64 vmcb_iopm;
aad42c64 88
cd3ff653
JR		 89 /* A VMEXIT is required but not yet emulated */
90 bool exit_required;
91
cda00082
JR		 92 /*
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
95 */
96 unsigned long vmexit_rip;
97 unsigned long vmexit_rsp;
98 unsigned long vmexit_rax;
99
aad42c64
JR		 100 /* cache for intercepts of the guest */
101 u16 intercept_cr_read;
102 u16 intercept_cr_write;
103 u16 intercept_dr_read;
104 u16 intercept_dr_write;
105 u32 intercept_exceptions;
106 u64 intercept;
107
5bd2edc3
JR		 108 /* Nested Paging related state */
109 u64 nested_cr3;
e6aa9abd
JR		 110};
111
323c3d80
JR		 112#define MSRPM_OFFSETS 16
113static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
114
6c8166a7
AK		 115struct vcpu_svm {
116 struct kvm_vcpu vcpu;
117 struct vmcb *vmcb;
118 unsigned long vmcb_pa;
119 struct svm_cpu_data *svm_data;
120 uint64_t asid_generation;
121 uint64_t sysenter_esp;
122 uint64_t sysenter_eip;
123
124 u64 next_rip;
125
126 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
afe9e66f 127 struct {
dacccfdd
AK		 128 u16 fs;
129 u16 gs;
130 u16 ldt;
afe9e66f
AK		 131 u64 gs_base;
132 } host;
6c8166a7
AK		 133
134 u32 *msrpm;
6c8166a7 135
e6aa9abd 136 struct nested_state nested;
6be7d306
JK		 137
138 bool nmi_singlestep;
66b7138f
JK		 139
140 unsigned int3_injected;
141 unsigned long int3_rip;
631bc487 142 u32 apf_reason;
6c8166a7
AK		 143};
144
455716fa
JR		 145#define MSR_INVALID 0xffffffffU
146
ac72a9b7
JR		 147static struct svm_direct_access_msrs {
148 u32 index; /* Index of the MSR */
149 bool always; /* True if intercept is always on */
150} direct_access_msrs[] = {
8c06585d 151 { .index = MSR_STAR, .always = true },
ac72a9b7
JR		 152 { .index = MSR_IA32_SYSENTER_CS, .always = true },
153#ifdef CONFIG_X86_64
154 { .index = MSR_GS_BASE, .always = true },
155 { .index = MSR_FS_BASE, .always = true },
156 { .index = MSR_KERNEL_GS_BASE, .always = true },
157 { .index = MSR_LSTAR, .always = true },
158 { .index = MSR_CSTAR, .always = true },
159 { .index = MSR_SYSCALL_MASK, .always = true },
160#endif
161 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
162 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
163 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
164 { .index = MSR_IA32_LASTINTTOIP, .always = false },
165 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 166};
167
709ddebf
JR		 168/* enable NPT for AMD64 and X86 with PAE */
169#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
170static bool npt_enabled = true;
171#else
e0231715 172static bool npt_enabled;
709ddebf 173#endif
6c7dac72
JR		 174static int npt = 1;
175
176module_param(npt, int, S_IRUGO);
e3da3acd 177
4b6e4dca 178static int nested = 1;
236de055
AG		 179module_param(nested, int, S_IRUGO);
180
44874f84 181static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 182static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 183
410e4d57 184static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 185static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 186static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 187static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
188 bool has_error_code, u32 error_code);
189
dacccfdd
AK		 190static void save_host_msrs(struct kvm_vcpu *vcpu);
191static void load_host_msrs(struct kvm_vcpu *vcpu);
192
a2fa3e9f
GH		 193static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
194{
fb3f0f51 195 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 196}
197
3d6368ef
AG		 198static inline bool is_nested(struct vcpu_svm *svm)
199{
e6aa9abd 200 return svm->nested.vmcb;
3d6368ef
AG		 201}
202
2af9194d
JR		 203static inline void enable_gif(struct vcpu_svm *svm)
204{
205 svm->vcpu.arch.hflags |= HF_GIF_MASK;
206}
207
208static inline void disable_gif(struct vcpu_svm *svm)
209{
210 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
211}
212
213static inline bool gif_set(struct vcpu_svm *svm)
214{
215 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
216}
217
4866d5e3 218static unsigned long iopm_base;
6aa8b732
AK		 219
220struct kvm_ldttss_desc {
221 u16 limit0;
222 u16 base0;
e0231715
JR		 223 unsigned base1:8, type:5, dpl:2, p:1;
224 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 225 u32 base3;
226 u32 zero1;
227} __attribute__((packed));
228
229struct svm_cpu_data {
230 int cpu;
231
5008fdf5
AK		 232 u64 asid_generation;
233 u32 max_asid;
234 u32 next_asid;
6aa8b732
AK		 235 struct kvm_ldttss_desc *tss_desc;
236
237 struct page *save_area;
238};
239
240static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 241static uint32_t svm_features;
6aa8b732
AK		 242
243struct svm_init_data {
244 int cpu;
245 int r;
246};
247
248static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
249
9d8f549d 250#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 251#define MSRS_RANGE_SIZE 2048
252#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
253
455716fa
JR		 254static u32 svm_msrpm_offset(u32 msr)
255{
256 u32 offset;
257 int i;
258
259 for (i = 0; i < NUM_MSR_MAPS; i++) {
260 if (msr < msrpm_ranges[i] ||
261 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
262 continue;
263
264 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
265 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
266
267 /* Now we have the u8 offset - but need the u32 offset */
268 return offset / 4;
269 }
270
271 /* MSR not in any range */
272 return MSR_INVALID;
273}
274
6aa8b732
AK		 275#define MAX_INST_SIZE 15
276
80b7706e
JR		 277static inline u32 svm_has(u32 feat)
278{
279 return svm_features & feat;
280}
281
6aa8b732
AK		 282static inline void clgi(void)
283{
4ecac3fd 284 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 285}
286
287static inline void stgi(void)
288{
4ecac3fd 289 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 290}
291
292static inline void invlpga(unsigned long addr, u32 asid)
293{
e0231715 294 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 295}
296
6aa8b732
AK		 297static inline void force_new_asid(struct kvm_vcpu *vcpu)
298{
a2fa3e9f 299 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 300}
301
302static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
303{
304 force_new_asid(vcpu);
305}
306
4b16184c
JR		 307static int get_npt_level(void)
308{
309#ifdef CONFIG_X86_64
310 return PT64_ROOT_LEVEL;
311#else
312 return PT32E_ROOT_LEVEL;
313#endif
314}
315
6aa8b732
AK		 316static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
317{
6dc696d4 318 vcpu->arch.efer = efer;
709ddebf 319 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 320 efer &= ~EFER_LME;
6aa8b732 321
9962d032 322 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
6aa8b732
AK		 323}
324
6aa8b732
AK		 325static int is_external_interrupt(u32 info)
326{
327 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
328 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
329}
330
2809f5d2
GC		 331static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
332{
333 struct vcpu_svm *svm = to_svm(vcpu);
334 u32 ret = 0;
335
336 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 337 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 338 return ret & mask;
339}
340
341static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
342{
343 struct vcpu_svm *svm = to_svm(vcpu);
344
345 if (mask == 0)
346 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
347 else
348 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
349
350}
351
6aa8b732
AK		 352static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
353{
a2fa3e9f
GH		 354 struct vcpu_svm *svm = to_svm(vcpu);
355
6bc31bdc
AP		 356 if (svm->vmcb->control.next_rip != 0)
357 svm->next_rip = svm->vmcb->control.next_rip;
358
a2fa3e9f 359 if (!svm->next_rip) {
851ba692 360 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 361 EMULATE_DONE)
362 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 363 return;
364 }
5fdbf976
MT		 365 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
366 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
367 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 368
5fdbf976 369 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 370 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 371}
372
116a4752 373static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 374 bool has_error_code, u32 error_code,
375 bool reinject)
116a4752
JK		 376{
377 struct vcpu_svm *svm = to_svm(vcpu);
378
e0231715
JR		 379 /*
380 * If we are within a nested VM we'd better #VMEXIT and let the guest
381 * handle the exception
382 */
ce7ddec4
JR		 383 if (!reinject &&
384 nested_svm_check_exception(svm, nr, has_error_code, error_code))
116a4752
JK		 385 return;
386
66b7138f
JK		 387 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
388 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
389
390 /*
391 * For guest debugging where we have to reinject #BP if some
392 * INT3 is guest-owned:
393 * Emulate nRIP by moving RIP forward. Will fail if injection
394 * raises a fault that is not intercepted. Still better than
395 * failing in all cases.
396 */
397 skip_emulated_instruction(&svm->vcpu);
398 rip = kvm_rip_read(&svm->vcpu);
399 svm->int3_rip = rip + svm->vmcb->save.cs.base;
400 svm->int3_injected = rip - old_rip;
401 }
402
116a4752
JK		 403 svm->vmcb->control.event_inj = nr
404 | SVM_EVTINJ_VALID
405 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
406 | SVM_EVTINJ_TYPE_EXEPT;
407 svm->vmcb->control.event_inj_err = error_code;
408}
409
67ec6607
JR		 410static void svm_init_erratum_383(void)
411{
412 u32 low, high;
413 int err;
414 u64 val;
415
1be85a6d 416 if (!cpu_has_amd_erratum(amd_erratum_383))
67ec6607
JR		 417 return;
418
419 /* Use _safe variants to not break nested virtualization */
420 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
421 if (err)
422 return;
423
424 val |= (1ULL << 47);
425
426 low = lower_32_bits(val);
427 high = upper_32_bits(val);
428
429 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
430
431 erratum_383_found = true;
432}
433
6aa8b732
AK		 434static int has_svm(void)
435{
63d1142f 436 const char *msg;
6aa8b732 437
63d1142f 438 if (!cpu_has_svm(&msg)) {
ff81ff10 439 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 440 return 0;
441 }
442
6aa8b732
AK		 443 return 1;
444}
445
446static void svm_hardware_disable(void *garbage)
447{
2c8dceeb 448 cpu_svm_disable();
6aa8b732
AK		 449}
450
10474ae8 451static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 452{
453
0fe1e009 454 struct svm_cpu_data *sd;
6aa8b732 455 uint64_t efer;
89a27f4d 456 struct desc_ptr gdt_descr;
6aa8b732
AK		 457 struct desc_struct *gdt;
458 int me = raw_smp_processor_id();
459
10474ae8
AG		 460 rdmsrl(MSR_EFER, efer);
461 if (efer & EFER_SVME)
462 return -EBUSY;
463
6aa8b732 464 if (!has_svm()) {
e6732a5a
ZA		 465 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
466 me);
10474ae8 467 return -EINVAL;
6aa8b732 468 }
0fe1e009 469 sd = per_cpu(svm_data, me);
6aa8b732 470
0fe1e009 471 if (!sd) {
e6732a5a 472 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 473 me);
10474ae8 474 return -EINVAL;
6aa8b732
AK		 475 }
476
0fe1e009
TH		 477 sd->asid_generation = 1;
478 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
479 sd->next_asid = sd->max_asid + 1;
6aa8b732 480
d6ab1ed4 481 native_store_gdt(&gdt_descr);
89a27f4d 482 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 483 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 484
9962d032 485 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 486
d0316554 487 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8 488
67ec6607
JR		 489 svm_init_erratum_383();
490
10474ae8 491 return 0;
6aa8b732
AK		 492}
493
0da1db75
JR		 494static void svm_cpu_uninit(int cpu)
495{
0fe1e009 496 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 497
0fe1e009 498 if (!sd)
0da1db75
JR		 499 return;
500
501 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 502 __free_page(sd->save_area);
503 kfree(sd);
0da1db75
JR		 504}
505
6aa8b732
AK		 506static int svm_cpu_init(int cpu)
507{
0fe1e009 508 struct svm_cpu_data *sd;
6aa8b732
AK		 509 int r;
510
0fe1e009
TH		 511 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
512 if (!sd)
6aa8b732 513 return -ENOMEM;
0fe1e009
TH		 514 sd->cpu = cpu;
515 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 516 r = -ENOMEM;
0fe1e009 517 if (!sd->save_area)
6aa8b732
AK		 518 goto err_1;
519
0fe1e009 520 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 521
522 return 0;
523
524err_1:
0fe1e009 525 kfree(sd);
6aa8b732
AK		 526 return r;
527
528}
529
ac72a9b7
JR		 530static bool valid_msr_intercept(u32 index)
531{
532 int i;
533
534 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
535 if (direct_access_msrs[i].index == index)
536 return true;
537
538 return false;
539}
540
bfc733a7
RR		 541static void set_msr_interception(u32 *msrpm, unsigned msr,
542 int read, int write)
6aa8b732 543{
455716fa
JR		 544 u8 bit_read, bit_write;
545 unsigned long tmp;
546 u32 offset;
6aa8b732 547
ac72a9b7
JR		 548 /*
549 * If this warning triggers extend the direct_access_msrs list at the
550 * beginning of the file
551 */
552 WARN_ON(!valid_msr_intercept(msr));
553
455716fa
JR		 554 offset = svm_msrpm_offset(msr);
555 bit_read = 2 * (msr & 0x0f);
556 bit_write = 2 * (msr & 0x0f) + 1;
557 tmp = msrpm[offset];
558
559 BUG_ON(offset == MSR_INVALID);
560
561 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
562 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
563
564 msrpm[offset] = tmp;
6aa8b732
AK		 565}
566
f65c229c 567static void svm_vcpu_init_msrpm(u32 *msrpm)
6aa8b732
AK		 568{
569 int i;
570
f65c229c
JR		 571 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
572
ac72a9b7
JR		 573 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
574 if (!direct_access_msrs[i].always)
575 continue;
576
577 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
578 }
f65c229c
JR		 579}
580
323c3d80
JR		 581static void add_msr_offset(u32 offset)
582{
583 int i;
584
585 for (i = 0; i < MSRPM_OFFSETS; ++i) {
586
587 /* Offset already in list? */
588 if (msrpm_offsets[i] == offset)
bfc733a7 589 return;
323c3d80
JR		 590
591 /* Slot used by another offset? */
592 if (msrpm_offsets[i] != MSR_INVALID)
593 continue;
594
595 /* Add offset to list */
596 msrpm_offsets[i] = offset;
597
598 return;
6aa8b732 599 }
323c3d80
JR		 600
601 /*
602 * If this BUG triggers the msrpm_offsets table has an overflow. Just
603 * increase MSRPM_OFFSETS in this case.
604 */
bfc733a7 605 BUG();
6aa8b732
AK		 606}
607
323c3d80 608static void init_msrpm_offsets(void)
f65c229c 609{
323c3d80 610 int i;
f65c229c 611
323c3d80
JR		 612 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
613
614 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
615 u32 offset;
616
617 offset = svm_msrpm_offset(direct_access_msrs[i].index);
618 BUG_ON(offset == MSR_INVALID);
619
620 add_msr_offset(offset);
621 }
f65c229c
JR		 622}
623
24e09cbf
JR		 624static void svm_enable_lbrv(struct vcpu_svm *svm)
625{
626 u32 *msrpm = svm->msrpm;
627
628 svm->vmcb->control.lbr_ctl = 1;
629 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
630 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
631 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
632 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
633}
634
635static void svm_disable_lbrv(struct vcpu_svm *svm)
636{
637 u32 *msrpm = svm->msrpm;
638
639 svm->vmcb->control.lbr_ctl = 0;
640 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
641 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
642 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
643 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
644}
645
6aa8b732
AK		 646static __init int svm_hardware_setup(void)
647{
648 int cpu;
649 struct page *iopm_pages;
f65c229c 650 void *iopm_va;
6aa8b732
AK		 651 int r;
652
6aa8b732
AK		 653 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
654
655 if (!iopm_pages)
656 return -ENOMEM;
c8681339
AL		 657
658 iopm_va = page_address(iopm_pages);
659 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 660 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
661
323c3d80
JR		 662 init_msrpm_offsets();
663
50a37eb4
JR		 664 if (boot_cpu_has(X86_FEATURE_NX))
665 kvm_enable_efer_bits(EFER_NX);
666
1b2fd70c
AG		 667 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
668 kvm_enable_efer_bits(EFER_FFXSR);
669
236de055
AG		 670 if (nested) {
671 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
eec4b140 672 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
236de055
AG		 673 }
674
3230bb47 675 for_each_possible_cpu(cpu) {
6aa8b732
AK		 676 r = svm_cpu_init(cpu);
677 if (r)
f65c229c 678 goto err;
6aa8b732 679 }
33bd6a0b
JR		 680
681 svm_features = cpuid_edx(SVM_CPUID_FUNC);
682
e3da3acd
JR		 683 if (!svm_has(SVM_FEATURE_NPT))
684 npt_enabled = false;
685
6c7dac72
JR		 686 if (npt_enabled && !npt) {
687 printk(KERN_INFO "kvm: Nested Paging disabled\n");
688 npt_enabled = false;
689 }
690
18552672 691 if (npt_enabled) {
e3da3acd 692 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 693 kvm_enable_tdp();
5f4cb662
JR		 694 } else
695 kvm_disable_tdp();
e3da3acd 696
6aa8b732
AK		 697 return 0;
698
f65c229c 699err:
6aa8b732
AK		 700 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
701 iopm_base = 0;
702 return r;
703}
704
705static __exit void svm_hardware_unsetup(void)
706{
0da1db75
JR		 707 int cpu;
708
3230bb47 709 for_each_possible_cpu(cpu)
0da1db75
JR		 710 svm_cpu_uninit(cpu);
711
6aa8b732 712 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 713 iopm_base = 0;
6aa8b732
AK		 714}
715
716static void init_seg(struct vmcb_seg *seg)
717{
718 seg->selector = 0;
719 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 720 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 721 seg->limit = 0xffff;
722 seg->base = 0;
723}
724
725static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
726{
727 seg->selector = 0;
728 seg->attrib = SVM_SELECTOR_P_MASK | type;
729 seg->limit = 0xffff;
730 seg->base = 0;
731}
732
f4e1b3c8
ZA		 733static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
734{
735 struct vcpu_svm *svm = to_svm(vcpu);
736 u64 g_tsc_offset = 0;
737
738 if (is_nested(svm)) {
739 g_tsc_offset = svm->vmcb->control.tsc_offset -
740 svm->nested.hsave->control.tsc_offset;
741 svm->nested.hsave->control.tsc_offset = offset;
742 }
743
744 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
745}
746
e48672fa
ZA		 747static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
748{
749 struct vcpu_svm *svm = to_svm(vcpu);
750
751 svm->vmcb->control.tsc_offset += adjustment;
752 if (is_nested(svm))
753 svm->nested.hsave->control.tsc_offset += adjustment;
754}
755
e6101a96 756static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 757{
e6101a96
JR		 758 struct vmcb_control_area *control = &svm->vmcb->control;
759 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 760
bff78274
AK		 761 svm->vcpu.fpu_active = 1;
762
e0231715 763 control->intercept_cr_read = INTERCEPT_CR0_MASK |
6aa8b732 764 INTERCEPT_CR3_MASK |
649d6864 765 INTERCEPT_CR4_MASK;
6aa8b732 766
e0231715 767 control->intercept_cr_write = INTERCEPT_CR0_MASK |
6aa8b732 768 INTERCEPT_CR3_MASK |
80a8119c
AK		 769 INTERCEPT_CR4_MASK |
770 INTERCEPT_CR8_MASK;
6aa8b732 771
e0231715 772 control->intercept_dr_read = INTERCEPT_DR0_MASK |
6aa8b732
AK		 773 INTERCEPT_DR1_MASK |
774 INTERCEPT_DR2_MASK |
727f5a23
JK		 775 INTERCEPT_DR3_MASK |
776 INTERCEPT_DR4_MASK |
777 INTERCEPT_DR5_MASK |
778 INTERCEPT_DR6_MASK |
779 INTERCEPT_DR7_MASK;
6aa8b732 780
e0231715 781 control->intercept_dr_write = INTERCEPT_DR0_MASK |
6aa8b732
AK		 782 INTERCEPT_DR1_MASK |
783 INTERCEPT_DR2_MASK |
784 INTERCEPT_DR3_MASK |
727f5a23 785 INTERCEPT_DR4_MASK |
6aa8b732 786 INTERCEPT_DR5_MASK |
727f5a23 787 INTERCEPT_DR6_MASK |
6aa8b732
AK		 788 INTERCEPT_DR7_MASK;
789
7aa81cc0 790 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 791 (1 << UD_VECTOR) |
792 (1 << MC_VECTOR);
6aa8b732
AK		 793
794
e0231715 795 control->intercept = (1ULL << INTERCEPT_INTR) |
6aa8b732 796 (1ULL << INTERCEPT_NMI) |
0152527b 797 (1ULL << INTERCEPT_SMI) |
d225157b 798 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 799 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 800 (1ULL << INTERCEPT_INVD) |
6aa8b732 801 (1ULL << INTERCEPT_HLT) |
a7052897 802 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 803 (1ULL << INTERCEPT_INVLPGA) |
804 (1ULL << INTERCEPT_IOIO_PROT) |
805 (1ULL << INTERCEPT_MSR_PROT) |
806 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 807 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 808 (1ULL << INTERCEPT_VMRUN) |
809 (1ULL << INTERCEPT_VMMCALL) |
810 (1ULL << INTERCEPT_VMLOAD) |
811 (1ULL << INTERCEPT_VMSAVE) |
812 (1ULL << INTERCEPT_STGI) |
813 (1ULL << INTERCEPT_CLGI) |
916ce236 814 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 815 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 816 (1ULL << INTERCEPT_MONITOR) |
817 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 818
819 control->iopm_base_pa = iopm_base;
f65c229c 820 control->msrpm_base_pa = __pa(svm->msrpm);
6aa8b732
AK		 821 control->int_ctl = V_INTR_MASKING_MASK;
822
823 init_seg(&save->es);
824 init_seg(&save->ss);
825 init_seg(&save->ds);
826 init_seg(&save->fs);
827 init_seg(&save->gs);
828
829 save->cs.selector = 0xf000;
830 /* Executable/Readable Code Segment */
831 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
832 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
833 save->cs.limit = 0xffff;
d92899a0
AK		 834 /*
835 * cs.base should really be 0xffff0000, but vmx can't handle that, so
836 * be consistent with it.
837 *
838 * Replace when we have real mode working for vmx.
839 */
840 save->cs.base = 0xf0000;
6aa8b732
AK		 841
842 save->gdtr.limit = 0xffff;
843 save->idtr.limit = 0xffff;
844
845 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
846 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
847
eaa48512 848 svm_set_efer(&svm->vcpu, 0);
d77c26fc 849 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 850 save->dr7 = 0x400;
851 save->rflags = 2;
852 save->rip = 0x0000fff0;
5fdbf976 853 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 854
e0231715
JR		 855 /*
856 * This is the guest-visible cr0 value.
18fa000a 857 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 858 */
678041ad
MT		 859 svm->vcpu.arch.cr0 = 0;
860 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
18fa000a 861
66aee91a 862 save->cr4 = X86_CR4_PAE;
6aa8b732 863 /* rdx = ?? */
709ddebf
JR		 864
865 if (npt_enabled) {
866 /* Setup VMCB for Nested Paging */
867 control->nested_ctl = 1;
a7052897
MT		 868 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
869 (1ULL << INTERCEPT_INVLPG));
709ddebf 870 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 871 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
872 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 873 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 874 save->cr3 = 0;
875 save->cr4 = 0;
876 }
a79d2f18 877 force_new_asid(&svm->vcpu);
1371d904 878
e6aa9abd 879 svm->nested.vmcb = 0;
2af9194d
JR		 880 svm->vcpu.arch.hflags = 0;
881
565d0998
ML		 882 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
883 control->pause_filter_count = 3000;
884 control->intercept |= (1ULL << INTERCEPT_PAUSE);
885 }
886
2af9194d 887 enable_gif(svm);
6aa8b732
AK		 888}
889
e00c8cf2 890static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 891{
892 struct vcpu_svm *svm = to_svm(vcpu);
893
e6101a96 894 init_vmcb(svm);
70433389 895
c5af89b6 896 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 897 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 898 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
899 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 900 }
5fdbf976
MT		 901 vcpu->arch.regs_avail = ~0;
902 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 903
904 return 0;
04d2cc77
AK		 905}
906
fb3f0f51 907static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 908{
a2fa3e9f 909 struct vcpu_svm *svm;
6aa8b732 910 struct page *page;
f65c229c 911 struct page *msrpm_pages;
b286d5d8 912 struct page *hsave_page;
3d6368ef 913 struct page *nested_msrpm_pages;
fb3f0f51 914 int err;
6aa8b732 915
c16f862d 916 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 917 if (!svm) {
918 err = -ENOMEM;
919 goto out;
920 }
921
922 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
923 if (err)
924 goto free_svm;
925
b7af4043 926 err = -ENOMEM;
6aa8b732 927 page = alloc_page(GFP_KERNEL);
b7af4043 928 if (!page)
fb3f0f51 929 goto uninit;
6aa8b732 930
f65c229c
JR		 931 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
932 if (!msrpm_pages)
b7af4043 933 goto free_page1;
3d6368ef
AG		 934
935 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
936 if (!nested_msrpm_pages)
b7af4043 937 goto free_page2;
f65c229c 938
b286d5d8
AG		 939 hsave_page = alloc_page(GFP_KERNEL);
940 if (!hsave_page)
b7af4043
TY		 941 goto free_page3;
942
e6aa9abd 943 svm->nested.hsave = page_address(hsave_page);
b286d5d8 944
b7af4043
TY		 945 svm->msrpm = page_address(msrpm_pages);
946 svm_vcpu_init_msrpm(svm->msrpm);
947
e6aa9abd 948 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 949 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 950
a2fa3e9f
GH		 951 svm->vmcb = page_address(page);
952 clear_page(svm->vmcb);
953 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
954 svm->asid_generation = 0;
e6101a96 955 init_vmcb(svm);
99e3e30a 956 kvm_write_tsc(&svm->vcpu, 0);
a2fa3e9f 957
10ab25cd
JK		 958 err = fx_init(&svm->vcpu);
959 if (err)
960 goto free_page4;
961
ad312c7c 962 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 963 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 964 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 965
fb3f0f51 966 return &svm->vcpu;
36241b8c 967
10ab25cd
JK		 968free_page4:
969 __free_page(hsave_page);
b7af4043
TY		 970free_page3:
971 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
972free_page2:
973 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
974free_page1:
975 __free_page(page);
fb3f0f51
RR		 976uninit:
977 kvm_vcpu_uninit(&svm->vcpu);
978free_svm:
a4770347 979 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 980out:
981 return ERR_PTR(err);
6aa8b732
AK		 982}
983
984static void svm_free_vcpu(struct kvm_vcpu *vcpu)
985{
a2fa3e9f
GH		 986 struct vcpu_svm *svm = to_svm(vcpu);
987
fb3f0f51 988 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 989 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 990 __free_page(virt_to_page(svm->nested.hsave));
991 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 992 kvm_vcpu_uninit(vcpu);
a4770347 993 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 994}
995
15ad7146 996static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 997{
a2fa3e9f 998 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 999 int i;
0cc5064d 1000
0cc5064d 1001 if (unlikely(cpu != vcpu->cpu)) {
4b656b12 1002 svm->asid_generation = 0;
0cc5064d 1003 }
94dfbdb3 1004
dacccfdd
AK		 1005 save_host_msrs(vcpu);
1006 savesegment(fs, svm->host.fs);
1007 savesegment(gs, svm->host.gs);
1008 svm->host.ldt = kvm_read_ldt();
1009
94dfbdb3 1010 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1011 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 1012}
1013
1014static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1015{
a2fa3e9f 1016 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 1017 int i;
1018
e1beb1d3 1019 ++vcpu->stat.host_state_reload;
dacccfdd
AK		 1020 kvm_load_ldt(svm->host.ldt);
1021#ifdef CONFIG_X86_64
1022 loadsegment(fs, svm->host.fs);
1023 load_gs_index(svm->host.gs);
1024 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1025#else
1026 loadsegment(gs, svm->host.gs);
1027#endif
94dfbdb3 1028 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1029 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 1030}
1031
6aa8b732
AK		 1032static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1033{
a2fa3e9f 1034 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 1035}
1036
1037static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1038{
a2fa3e9f 1039 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 1040}
1041
6de4f3ad
AK		 1042static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1043{
1044 switch (reg) {
1045 case VCPU_EXREG_PDPTR:
1046 BUG_ON(!npt_enabled);
ff03a073 1047 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
6de4f3ad
AK		 1048 break;
1049 default:
1050 BUG();
1051 }
1052}
1053
f0b85051
AG		 1054static void svm_set_vintr(struct vcpu_svm *svm)
1055{
1056 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1057}
1058
1059static void svm_clear_vintr(struct vcpu_svm *svm)
1060{
1061 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1062}
1063
6aa8b732
AK		 1064static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1065{
a2fa3e9f 1066 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 1067
1068 switch (seg) {
1069 case VCPU_SREG_CS: return &save->cs;
1070 case VCPU_SREG_DS: return &save->ds;
1071 case VCPU_SREG_ES: return &save->es;
1072 case VCPU_SREG_FS: return &save->fs;
1073 case VCPU_SREG_GS: return &save->gs;
1074 case VCPU_SREG_SS: return &save->ss;
1075 case VCPU_SREG_TR: return &save->tr;
1076 case VCPU_SREG_LDTR: return &save->ldtr;
1077 }
1078 BUG();
8b6d44c7 1079 return NULL;
6aa8b732
AK		 1080}
1081
1082static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1083{
1084 struct vmcb_seg *s = svm_seg(vcpu, seg);
1085
1086 return s->base;
1087}
1088
1089static void svm_get_segment(struct kvm_vcpu *vcpu,
1090 struct kvm_segment *var, int seg)
1091{
1092 struct vmcb_seg *s = svm_seg(vcpu, seg);
1093
1094 var->base = s->base;
1095 var->limit = s->limit;
1096 var->selector = s->selector;
1097 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1098 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1099 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1100 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1101 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1102 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1103 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1104 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 1105
e0231715
JR		 1106 /*
1107 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1108 * for cross vendor migration purposes by "not present"
1109 */
1110 var->unusable = !var->present || (var->type == 0);
1111
1fbdc7a5
AP		 1112 switch (seg) {
1113 case VCPU_SREG_CS:
1114 /*
1115 * SVM always stores 0 for the 'G' bit in the CS selector in
1116 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1117 * Intel's VMENTRY has a check on the 'G' bit.
1118 */
25022acc 1119 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 1120 break;
1121 case VCPU_SREG_TR:
1122 /*
1123 * Work around a bug where the busy flag in the tr selector
1124 * isn't exposed
1125 */
c0d09828 1126 var->type |= 0x2;
1fbdc7a5
AP		 1127 break;
1128 case VCPU_SREG_DS:
1129 case VCPU_SREG_ES:
1130 case VCPU_SREG_FS:
1131 case VCPU_SREG_GS:
1132 /*
1133 * The accessed bit must always be set in the segment
1134 * descriptor cache, although it can be cleared in the
1135 * descriptor, the cached bit always remains at 1. Since
1136 * Intel has a check on this, set it here to support
1137 * cross-vendor migration.
1138 */
1139 if (!var->unusable)
1140 var->type |= 0x1;
1141 break;
b586eb02 1142 case VCPU_SREG_SS:
e0231715
JR		 1143 /*
1144 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1145 * descriptor is left as 1, although the whole segment has
1146 * been made unusable. Clear it here to pass an Intel VMX
1147 * entry check when cross vendor migrating.
1148 */
1149 if (var->unusable)
1150 var->db = 0;
1151 break;
1fbdc7a5 1152 }
6aa8b732
AK		 1153}
1154
2e4d2653
IE		 1155static int svm_get_cpl(struct kvm_vcpu *vcpu)
1156{
1157 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1158
1159 return save->cpl;
1160}
1161
89a27f4d 1162static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1163{
a2fa3e9f
GH		 1164 struct vcpu_svm *svm = to_svm(vcpu);
1165
89a27f4d
GN		 1166 dt->size = svm->vmcb->save.idtr.limit;
1167 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1168}
1169
89a27f4d 1170static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1171{
a2fa3e9f
GH		 1172 struct vcpu_svm *svm = to_svm(vcpu);
1173
89a27f4d
GN		 1174 svm->vmcb->save.idtr.limit = dt->size;
1175 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 1176}
1177
89a27f4d 1178static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1179{
a2fa3e9f
GH		 1180 struct vcpu_svm *svm = to_svm(vcpu);
1181
89a27f4d
GN		 1182 dt->size = svm->vmcb->save.gdtr.limit;
1183 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1184}
1185
89a27f4d 1186static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1187{
a2fa3e9f
GH		 1188 struct vcpu_svm *svm = to_svm(vcpu);
1189
89a27f4d
GN		 1190 svm->vmcb->save.gdtr.limit = dt->size;
1191 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 1192}
1193
e8467fda
AK		 1194static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1195{
1196}
1197
25c4c276 1198static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1199{
1200}
1201
d225157b
AK		 1202static void update_cr0_intercept(struct vcpu_svm *svm)
1203{
66a562f7 1204 struct vmcb *vmcb = svm->vmcb;
d225157b
AK		 1205 ulong gcr0 = svm->vcpu.arch.cr0;
1206 u64 *hcr0 = &svm->vmcb->save.cr0;
1207
1208 if (!svm->vcpu.fpu_active)
1209 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1210 else
1211 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1212 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1213
1214
1215 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
66a562f7
JR		 1216 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1217 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1218 if (is_nested(svm)) {
1219 struct vmcb *hsave = svm->nested.hsave;
1220
1221 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1222 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1223 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1224 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1225 }
d225157b
AK		 1226 } else {
1227 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1228 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
66a562f7
JR		 1229 if (is_nested(svm)) {
1230 struct vmcb *hsave = svm->nested.hsave;
1231
1232 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1233 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1234 }
d225157b
AK		 1235 }
1236}
1237
6aa8b732
AK		 1238static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1239{
a2fa3e9f
GH		 1240 struct vcpu_svm *svm = to_svm(vcpu);
1241
7f5d8b56
JR		 1242 if (is_nested(svm)) {
1243 /*
1244 * We are here because we run in nested mode, the host kvm
1245 * intercepts cr0 writes but the l1 hypervisor does not.
1246 * But the L1 hypervisor may intercept selective cr0 writes.
1247 * This needs to be checked here.
1248 */
1249 unsigned long old, new;
1250
1251 /* Remove bits that would trigger a real cr0 write intercept */
1252 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1253 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1254
1255 if (old == new) {
1256 /* cr0 write with ts and mp unchanged */
1257 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
cda00082
JR		 1258 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1259 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1260 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1261 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7f5d8b56 1262 return;
cda00082 1263 }
7f5d8b56
JR		 1264 }
1265 }
1266
05b3e0c2 1267#ifdef CONFIG_X86_64
f6801dff 1268 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1269 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1270 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1271 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1272 }
1273
d77c26fc 1274 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1275 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1276 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1277 }
1278 }
1279#endif
ad312c7c 1280 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1281
1282 if (!npt_enabled)
1283 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1284
1285 if (!vcpu->fpu_active)
334df50a 1286 cr0 |= X86_CR0_TS;
709ddebf
JR		 1287 /*
1288 * re-enable caching here because the QEMU bios
1289 * does not do it - this results in some delay at
1290 * reboot
1291 */
1292 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1293 svm->vmcb->save.cr0 = cr0;
d225157b 1294 update_cr0_intercept(svm);
6aa8b732
AK		 1295}
1296
1297static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1298{
6394b649 1299 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1300 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1301
1302 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1303 force_new_asid(vcpu);
6394b649 1304
ec077263
JR		 1305 vcpu->arch.cr4 = cr4;
1306 if (!npt_enabled)
1307 cr4 |= X86_CR4_PAE;
6394b649 1308 cr4 |= host_cr4_mce;
ec077263 1309 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1310}
1311
1312static void svm_set_segment(struct kvm_vcpu *vcpu,
1313 struct kvm_segment *var, int seg)
1314{
a2fa3e9f 1315 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1316 struct vmcb_seg *s = svm_seg(vcpu, seg);
1317
1318 s->base = var->base;
1319 s->limit = var->limit;
1320 s->selector = var->selector;
1321 if (var->unusable)
1322 s->attrib = 0;
1323 else {
1324 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1325 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1326 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1327 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1328 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1329 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1330 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1331 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1332 }
1333 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1334 svm->vmcb->save.cpl
1335 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1336 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1337
1338}
1339
44c11430 1340static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1341{
d0bfb940
JK		 1342 struct vcpu_svm *svm = to_svm(vcpu);
1343
d0bfb940
JK		 1344 svm->vmcb->control.intercept_exceptions &=
1345 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1346
6be7d306 1347 if (svm->nmi_singlestep)
44c11430
GN		 1348 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1349
d0bfb940
JK		 1350 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1351 if (vcpu->guest_debug &
1352 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1353 svm->vmcb->control.intercept_exceptions |=
1354 1 << DB_VECTOR;
1355 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1356 svm->vmcb->control.intercept_exceptions |=
1357 1 << BP_VECTOR;
1358 } else
1359 vcpu->guest_debug = 0;
44c11430
GN		 1360}
1361
355be0b9 1362static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1363{
44c11430
GN		 1364 struct vcpu_svm *svm = to_svm(vcpu);
1365
ae675ef0
JK		 1366 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1367 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1368 else
1369 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1370
355be0b9 1371 update_db_intercept(vcpu);
6aa8b732
AK		 1372}
1373
1374static void load_host_msrs(struct kvm_vcpu *vcpu)
1375{
94dfbdb3 1376#ifdef CONFIG_X86_64
afe9e66f 1377 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
94dfbdb3 1378#endif
6aa8b732
AK		 1379}
1380
1381static void save_host_msrs(struct kvm_vcpu *vcpu)
1382{
94dfbdb3 1383#ifdef CONFIG_X86_64
afe9e66f 1384 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
94dfbdb3 1385#endif
6aa8b732
AK		 1386}
1387
0fe1e009 1388static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1389{
0fe1e009
TH		 1390 if (sd->next_asid > sd->max_asid) {
1391 ++sd->asid_generation;
1392 sd->next_asid = 1;
a2fa3e9f 1393 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1394 }
1395
0fe1e009
TH		 1396 svm->asid_generation = sd->asid_generation;
1397 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1398}
1399
020df079 1400static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1401{
42dbaa5a 1402 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1403
020df079 1404 svm->vmcb->save.dr7 = value;
6aa8b732
AK		 1405}
1406
851ba692 1407static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1408{
631bc487 1409 u64 fault_address = svm->vmcb->control.exit_info_2;
6aa8b732 1410 u32 error_code;
631bc487 1411 int r = 1;
6aa8b732 1412
631bc487
GN		 1413 switch (svm->apf_reason) {
1414 default:
1415 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1416
631bc487
GN		 1417 trace_kvm_page_fault(fault_address, error_code);
1418 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1419 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1420 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1421 break;
1422 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1423 svm->apf_reason = 0;
1424 local_irq_disable();
1425 kvm_async_pf_task_wait(fault_address);
1426 local_irq_enable();
1427 break;
1428 case KVM_PV_REASON_PAGE_READY:
1429 svm->apf_reason = 0;
1430 local_irq_disable();
1431 kvm_async_pf_task_wake(fault_address);
1432 local_irq_enable();
1433 break;
1434 }
1435 return r;
6aa8b732
AK		 1436}
1437
851ba692 1438static int db_interception(struct vcpu_svm *svm)
d0bfb940 1439{
851ba692
AK		 1440 struct kvm_run *kvm_run = svm->vcpu.run;
1441
d0bfb940 1442 if (!(svm->vcpu.guest_debug &
44c11430 1443 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1444 !svm->nmi_singlestep) {
d0bfb940
JK		 1445 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1446 return 1;
1447 }
44c11430 1448
6be7d306
JK		 1449 if (svm->nmi_singlestep) {
1450 svm->nmi_singlestep = false;
44c11430
GN		 1451 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1452 svm->vmcb->save.rflags &=
1453 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1454 update_db_intercept(&svm->vcpu);
1455 }
1456
1457 if (svm->vcpu.guest_debug &
e0231715 1458 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1459 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1460 kvm_run->debug.arch.pc =
1461 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1462 kvm_run->debug.arch.exception = DB_VECTOR;
1463 return 0;
1464 }
1465
1466 return 1;
d0bfb940
JK		 1467}
1468
851ba692 1469static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1470{
851ba692
AK		 1471 struct kvm_run *kvm_run = svm->vcpu.run;
1472
d0bfb940
JK		 1473 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1474 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1475 kvm_run->debug.arch.exception = BP_VECTOR;
1476 return 0;
1477}
1478
851ba692 1479static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1480{
1481 int er;
1482
851ba692 1483 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1484 if (er != EMULATE_DONE)
7ee5d940 1485 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1486 return 1;
1487}
1488
6b52d186 1489static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1490{
6b52d186 1491 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7
JR		 1492 u32 excp;
1493
1494 if (is_nested(svm)) {
1495 u32 h_excp, n_excp;
1496
1497 h_excp = svm->nested.hsave->control.intercept_exceptions;
1498 n_excp = svm->nested.intercept_exceptions;
1499 h_excp &= ~(1 << NM_VECTOR);
1500 excp = h_excp | n_excp;
1501 } else {
1502 excp = svm->vmcb->control.intercept_exceptions;
e0231715 1503 excp &= ~(1 << NM_VECTOR);
66a562f7
JR		 1504 }
1505
1506 svm->vmcb->control.intercept_exceptions = excp;
1507
e756fc62 1508 svm->vcpu.fpu_active = 1;
d225157b 1509 update_cr0_intercept(svm);
6b52d186 1510}
a2fa3e9f 1511
6b52d186
AK		 1512static int nm_interception(struct vcpu_svm *svm)
1513{
1514 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1515 return 1;
7807fa6c
AL		 1516}
1517
67ec6607
JR		 1518static bool is_erratum_383(void)
1519{
1520 int err, i;
1521 u64 value;
1522
1523 if (!erratum_383_found)
1524 return false;
1525
1526 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1527 if (err)
1528 return false;
1529
1530 /* Bit 62 may or may not be set for this mce */
1531 value &= ~(1ULL << 62);
1532
1533 if (value != 0xb600000000010015ULL)
1534 return false;
1535
1536 /* Clear MCi_STATUS registers */
1537 for (i = 0; i < 6; ++i)
1538 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1539
1540 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1541 if (!err) {
1542 u32 low, high;
1543
1544 value &= ~(1ULL << 2);
1545 low = lower_32_bits(value);
1546 high = upper_32_bits(value);
1547
1548 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1549 }
1550
1551 /* Flush tlb to evict multi-match entries */
1552 __flush_tlb_all();
1553
1554 return true;
1555}
1556
fe5913e4 1557static void svm_handle_mce(struct vcpu_svm *svm)
53371b50 1558{
67ec6607
JR		 1559 if (is_erratum_383()) {
1560 /*
1561 * Erratum 383 triggered. Guest state is corrupt so kill the
1562 * guest.
1563 */
1564 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1565
a8eeb04a 1566 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
67ec6607
JR		 1567
1568 return;
1569 }
1570
53371b50
JR		 1571 /*
1572 * On an #MC intercept the MCE handler is not called automatically in
1573 * the host. So do it by hand here.
1574 */
1575 asm volatile (
1576 "int $0x12\n");
1577 /* not sure if we ever come back to this point */
1578
fe5913e4
JR		 1579 return;
1580}
1581
1582static int mc_interception(struct vcpu_svm *svm)
1583{
53371b50
JR		 1584 return 1;
1585}
1586
851ba692 1587static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1588{
851ba692
AK		 1589 struct kvm_run *kvm_run = svm->vcpu.run;
1590
46fe4ddd
JR		 1591 /*
1592 * VMCB is undefined after a SHUTDOWN intercept
1593 * so reinitialize it.
1594 */
a2fa3e9f 1595 clear_page(svm->vmcb);
e6101a96 1596 init_vmcb(svm);
46fe4ddd
JR		 1597
1598 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1599 return 0;
1600}
1601
851ba692 1602static int io_interception(struct vcpu_svm *svm)
6aa8b732 1603{
cf8f70bf 1604 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1605 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1606 int size, in, string;
039576c0 1607 unsigned port;
6aa8b732 1608
e756fc62 1609 ++svm->vcpu.stat.io_exits;
e70669ab 1610 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1611 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
cf8f70bf 1612 if (string || in)
6d77dbfc 1613 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
cf8f70bf 1614
039576c0
AK		 1615 port = io_info >> 16;
1616 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1617 svm->next_rip = svm->vmcb->control.exit_info_2;
e93f36bc 1618 skip_emulated_instruction(&svm->vcpu);
cf8f70bf
GN		 1619
1620 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 1621}
1622
851ba692 1623static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1624{
1625 return 1;
1626}
1627
851ba692 1628static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1629{
1630 ++svm->vcpu.stat.irq_exits;
1631 return 1;
1632}
1633
851ba692 1634static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1635{
1636 return 1;
1637}
1638
851ba692 1639static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1640{
5fdbf976 1641 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1642 skip_emulated_instruction(&svm->vcpu);
1643 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1644}
1645
851ba692 1646static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1647{
5fdbf976 1648 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1649 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1650 kvm_emulate_hypercall(&svm->vcpu);
1651 return 1;
02e235bc
AK		 1652}
1653
5bd2edc3
JR		 1654static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1655{
1656 struct vcpu_svm *svm = to_svm(vcpu);
1657
1658 return svm->nested.nested_cr3;
1659}
1660
1661static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1662 unsigned long root)
1663{
1664 struct vcpu_svm *svm = to_svm(vcpu);
1665
1666 svm->vmcb->control.nested_cr3 = root;
1667 force_new_asid(vcpu);
1668}
1669
1670static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu)
1671{
1672 struct vcpu_svm *svm = to_svm(vcpu);
1673
1674 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1675 svm->vmcb->control.exit_code_hi = 0;
1676 svm->vmcb->control.exit_info_1 = vcpu->arch.fault.error_code;
1677 svm->vmcb->control.exit_info_2 = vcpu->arch.fault.address;
1678
1679 nested_svm_vmexit(svm);
1680}
1681
4b16184c
JR		 1682static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1683{
1684 int r;
1685
1686 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1687
1688 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1689 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1690 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1691 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1692 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1693
1694 return r;
1695}
1696
1697static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1698{
1699 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1700}
1701
c0725420
AG		 1702static int nested_svm_check_permissions(struct vcpu_svm *svm)
1703{
f6801dff 1704 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1705 || !is_paging(&svm->vcpu)) {
1706 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1707 return 1;
1708 }
1709
1710 if (svm->vmcb->save.cpl) {
1711 kvm_inject_gp(&svm->vcpu, 0);
1712 return 1;
1713 }
1714
1715 return 0;
1716}
1717
cf74a78b
AG		 1718static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1719 bool has_error_code, u32 error_code)
1720{
b8e88bc8
JR		 1721 int vmexit;
1722
0295ad7d
JR		 1723 if (!is_nested(svm))
1724 return 0;
cf74a78b 1725
0295ad7d
JR		 1726 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1727 svm->vmcb->control.exit_code_hi = 0;
1728 svm->vmcb->control.exit_info_1 = error_code;
1729 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1730
b8e88bc8
JR		 1731 vmexit = nested_svm_intercept(svm);
1732 if (vmexit == NESTED_EXIT_DONE)
1733 svm->nested.exit_required = true;
1734
1735 return vmexit;
cf74a78b
AG		 1736}
1737
8fe54654
JR		 1738/* This function returns true if it is save to enable the irq window */
1739static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1740{
26666957 1741 if (!is_nested(svm))
8fe54654 1742 return true;
cf74a78b 1743
26666957 1744 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1745 return true;
cf74a78b 1746
26666957 1747 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1748 return false;
cf74a78b 1749
a0a07cd2
GN		 1750 /*
1751 * if vmexit was already requested (by intercepted exception
1752 * for instance) do not overwrite it with "external interrupt"
1753 * vmexit.
1754 */
1755 if (svm->nested.exit_required)
1756 return false;
1757
197717d5
JR		 1758 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1759 svm->vmcb->control.exit_info_1 = 0;
1760 svm->vmcb->control.exit_info_2 = 0;
26666957 1761
cd3ff653
JR		 1762 if (svm->nested.intercept & 1ULL) {
1763 /*
1764 * The #vmexit can't be emulated here directly because this
1765 * code path runs with irqs and preemtion disabled. A
1766 * #vmexit emulation might sleep. Only signal request for
1767 * the #vmexit here.
1768 */
1769 svm->nested.exit_required = true;
236649de 1770 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1771 return false;
cf74a78b
AG		 1772 }
1773
8fe54654 1774 return true;
cf74a78b
AG		 1775}
1776
887f500c
JR		 1777/* This function returns true if it is save to enable the nmi window */
1778static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1779{
1780 if (!is_nested(svm))
1781 return true;
1782
1783 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1784 return true;
1785
1786 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1787 svm->nested.exit_required = true;
1788
1789 return false;
cf74a78b
AG		 1790}
1791
7597f129 1792static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1793{
1794 struct page *page;
1795
6c3bd3d7
JR		 1796 might_sleep();
1797
34f80cfa 1798 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1799 if (is_error_page(page))
1800 goto error;
1801
7597f129
JR		 1802 *_page = page;
1803
1804 return kmap(page);
34f80cfa
JR		 1805
1806error:
1807 kvm_release_page_clean(page);
1808 kvm_inject_gp(&svm->vcpu, 0);
1809
1810 return NULL;
1811}
1812
7597f129 1813static void nested_svm_unmap(struct page *page)
34f80cfa 1814{
7597f129 1815 kunmap(page);
34f80cfa
JR		 1816 kvm_release_page_dirty(page);
1817}
34f80cfa 1818
ce2ac085
JR		 1819static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1820{
1821 unsigned port;
1822 u8 val, bit;
1823 u64 gpa;
34f80cfa 1824
ce2ac085
JR		 1825 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1826 return NESTED_EXIT_HOST;
34f80cfa 1827
ce2ac085
JR		 1828 port = svm->vmcb->control.exit_info_1 >> 16;
1829 gpa = svm->nested.vmcb_iopm + (port / 8);
1830 bit = port % 8;
1831 val = 0;
1832
1833 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1834 val &= (1 << bit);
1835
1836 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
34f80cfa
JR		 1837}
1838
d2477826 1839static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1840{
0d6b3537
JR		 1841 u32 offset, msr, value;
1842 int write, mask;
4c2161ae 1843
3d62d9aa 1844 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 1845 return NESTED_EXIT_HOST;
3d62d9aa 1846
0d6b3537
JR		 1847 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1848 offset = svm_msrpm_offset(msr);
1849 write = svm->vmcb->control.exit_info_1 & 1;
1850 mask = 1 << ((2 * (msr & 0xf)) + write);
3d62d9aa 1851
0d6b3537
JR		 1852 if (offset == MSR_INVALID)
1853 return NESTED_EXIT_DONE;
4c2161ae 1854
0d6b3537
JR		 1855 /* Offset is in 32 bit units but need in 8 bit units */
1856 offset *= 4;
4c2161ae 1857
0d6b3537
JR		 1858 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1859 return NESTED_EXIT_DONE;
3d62d9aa 1860
0d6b3537 1861 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
4c2161ae
JR		 1862}
1863
410e4d57 1864static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1865{
cf74a78b 1866 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1867
410e4d57
JR		 1868 switch (exit_code) {
1869 case SVM_EXIT_INTR:
1870 case SVM_EXIT_NMI:
ff47a49b 1871 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
410e4d57 1872 return NESTED_EXIT_HOST;
410e4d57 1873 case SVM_EXIT_NPF:
e0231715 1874 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1875 if (npt_enabled)
1876 return NESTED_EXIT_HOST;
1877 break;
410e4d57 1878 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
631bc487
GN		 1879 /* When we're shadowing, trap PFs, but not async PF */
1880 if (!npt_enabled && svm->apf_reason == 0)
410e4d57
JR		 1881 return NESTED_EXIT_HOST;
1882 break;
66a562f7
JR		 1883 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1884 nm_interception(svm);
1885 break;
410e4d57
JR		 1886 default:
1887 break;
cf74a78b
AG		 1888 }
1889
410e4d57
JR		 1890 return NESTED_EXIT_CONTINUE;
1891}
1892
1893/*
1894 * If this function returns true, this #vmexit was already handled
1895 */
b8e88bc8 1896static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1897{
1898 u32 exit_code = svm->vmcb->control.exit_code;
1899 int vmexit = NESTED_EXIT_HOST;
1900
cf74a78b 1901 switch (exit_code) {
9c4e40b9 1902 case SVM_EXIT_MSR:
3d62d9aa 1903 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1904 break;
ce2ac085
JR		 1905 case SVM_EXIT_IOIO:
1906 vmexit = nested_svm_intercept_ioio(svm);
1907 break;
cf74a78b
AG		 1908 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1909 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1910 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1911 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1912 break;
1913 }
1914 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1915 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1916 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1917 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1918 break;
1919 }
1920 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1921 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1922 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1923 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1924 break;
1925 }
1926 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1927 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1928 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1929 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1930 break;
1931 }
1932 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1933 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1934 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1935 vmexit = NESTED_EXIT_DONE;
631bc487
GN		 1936 /* async page fault always cause vmexit */
1937 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
1938 svm->apf_reason != 0)
1939 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1940 break;
1941 }
228070b1
JR		 1942 case SVM_EXIT_ERR: {
1943 vmexit = NESTED_EXIT_DONE;
1944 break;
1945 }
cf74a78b
AG		 1946 default: {
1947 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1948 if (svm->nested.intercept & exit_bits)
410e4d57 1949 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1950 }
1951 }
1952
b8e88bc8
JR		 1953 return vmexit;
1954}
1955
1956static int nested_svm_exit_handled(struct vcpu_svm *svm)
1957{
1958 int vmexit;
1959
1960 vmexit = nested_svm_intercept(svm);
1961
1962 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1963 nested_svm_vmexit(svm);
9c4e40b9
JR		 1964
1965 return vmexit;
cf74a78b
AG		 1966}
1967
0460a979
JR		 1968static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1969{
1970 struct vmcb_control_area *dst = &dst_vmcb->control;
1971 struct vmcb_control_area *from = &from_vmcb->control;
1972
1973 dst->intercept_cr_read = from->intercept_cr_read;
1974 dst->intercept_cr_write = from->intercept_cr_write;
1975 dst->intercept_dr_read = from->intercept_dr_read;
1976 dst->intercept_dr_write = from->intercept_dr_write;
1977 dst->intercept_exceptions = from->intercept_exceptions;
1978 dst->intercept = from->intercept;
1979 dst->iopm_base_pa = from->iopm_base_pa;
1980 dst->msrpm_base_pa = from->msrpm_base_pa;
1981 dst->tsc_offset = from->tsc_offset;
1982 dst->asid = from->asid;
1983 dst->tlb_ctl = from->tlb_ctl;
1984 dst->int_ctl = from->int_ctl;
1985 dst->int_vector = from->int_vector;
1986 dst->int_state = from->int_state;
1987 dst->exit_code = from->exit_code;
1988 dst->exit_code_hi = from->exit_code_hi;
1989 dst->exit_info_1 = from->exit_info_1;
1990 dst->exit_info_2 = from->exit_info_2;
1991 dst->exit_int_info = from->exit_int_info;
1992 dst->exit_int_info_err = from->exit_int_info_err;
1993 dst->nested_ctl = from->nested_ctl;
1994 dst->event_inj = from->event_inj;
1995 dst->event_inj_err = from->event_inj_err;
1996 dst->nested_cr3 = from->nested_cr3;
1997 dst->lbr_ctl = from->lbr_ctl;
1998}
1999
34f80cfa 2000static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 2001{
34f80cfa 2002 struct vmcb *nested_vmcb;
e6aa9abd 2003 struct vmcb *hsave = svm->nested.hsave;
33740e40 2004 struct vmcb *vmcb = svm->vmcb;
7597f129 2005 struct page *page;
cf74a78b 2006
17897f36
JR		 2007 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2008 vmcb->control.exit_info_1,
2009 vmcb->control.exit_info_2,
2010 vmcb->control.exit_int_info,
2011 vmcb->control.exit_int_info_err);
2012
7597f129 2013 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 2014 if (!nested_vmcb)
2015 return 1;
2016
06fc7772
JR		 2017 /* Exit nested SVM mode */
2018 svm->nested.vmcb = 0;
2019
cf74a78b 2020 /* Give the current vmcb to the guest */
33740e40
JR		 2021 disable_gif(svm);
2022
2023 nested_vmcb->save.es = vmcb->save.es;
2024 nested_vmcb->save.cs = vmcb->save.cs;
2025 nested_vmcb->save.ss = vmcb->save.ss;
2026 nested_vmcb->save.ds = vmcb->save.ds;
2027 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2028 nested_vmcb->save.idtr = vmcb->save.idtr;
3f6a9d16 2029 nested_vmcb->save.efer = svm->vcpu.arch.efer;
cdbbdc12 2030 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2be4fc7a 2031 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 2032 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 2033 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 2034 nested_vmcb->save.rflags = vmcb->save.rflags;
2035 nested_vmcb->save.rip = vmcb->save.rip;
2036 nested_vmcb->save.rsp = vmcb->save.rsp;
2037 nested_vmcb->save.rax = vmcb->save.rax;
2038 nested_vmcb->save.dr7 = vmcb->save.dr7;
2039 nested_vmcb->save.dr6 = vmcb->save.dr6;
2040 nested_vmcb->save.cpl = vmcb->save.cpl;
2041
2042 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2043 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2044 nested_vmcb->control.int_state = vmcb->control.int_state;
2045 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2046 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2047 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2048 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2049 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2050 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
7a190667 2051 nested_vmcb->control.next_rip = vmcb->control.next_rip;
8d23c466
AG		 2052
2053 /*
2054 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2055 * to make sure that we do not lose injected events. So check event_inj
2056 * here and copy it to exit_int_info if it is valid.
2057 * Exit_int_info and event_inj can't be both valid because the case
2058 * below only happens on a VMRUN instruction intercept which has
2059 * no valid exit_int_info set.
2060 */
2061 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2062 struct vmcb_control_area *nc = &nested_vmcb->control;
2063
2064 nc->exit_int_info = vmcb->control.event_inj;
2065 nc->exit_int_info_err = vmcb->control.event_inj_err;
2066 }
2067
33740e40
JR		 2068 nested_vmcb->control.tlb_ctl = 0;
2069 nested_vmcb->control.event_inj = 0;
2070 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 2071
2072 /* We always set V_INTR_MASKING and remember the old value in hflags */
2073 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2074 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2075
cf74a78b 2076 /* Restore the original control entries */
0460a979 2077 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 2078
219b65dc
AG		 2079 kvm_clear_exception_queue(&svm->vcpu);
2080 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b 2081
4b16184c
JR		 2082 svm->nested.nested_cr3 = 0;
2083
cf74a78b
AG		 2084 /* Restore selected save entries */
2085 svm->vmcb->save.es = hsave->save.es;
2086 svm->vmcb->save.cs = hsave->save.cs;
2087 svm->vmcb->save.ss = hsave->save.ss;
2088 svm->vmcb->save.ds = hsave->save.ds;
2089 svm->vmcb->save.gdtr = hsave->save.gdtr;
2090 svm->vmcb->save.idtr = hsave->save.idtr;
2091 svm->vmcb->save.rflags = hsave->save.rflags;
2092 svm_set_efer(&svm->vcpu, hsave->save.efer);
2093 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2094 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2095 if (npt_enabled) {
2096 svm->vmcb->save.cr3 = hsave->save.cr3;
2097 svm->vcpu.arch.cr3 = hsave->save.cr3;
2098 } else {
2390218b 2099 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
cf74a78b
AG		 2100 }
2101 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2102 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2103 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2104 svm->vmcb->save.dr7 = 0;
2105 svm->vmcb->save.cpl = 0;
2106 svm->vmcb->control.exit_int_info = 0;
2107
7597f129 2108 nested_svm_unmap(page);
cf74a78b 2109
4b16184c 2110 nested_svm_uninit_mmu_context(&svm->vcpu);
cf74a78b
AG		 2111 kvm_mmu_reset_context(&svm->vcpu);
2112 kvm_mmu_load(&svm->vcpu);
2113
2114 return 0;
2115}
3d6368ef 2116
9738b2c9 2117static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 2118{
323c3d80
JR		 2119 /*
2120 * This function merges the msr permission bitmaps of kvm and the
2121 * nested vmcb. It is omptimized in that it only merges the parts where
2122 * the kvm msr permission bitmap may contain zero bits
2123 */
3d6368ef 2124 int i;
9738b2c9 2125
323c3d80
JR		 2126 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2127 return true;
9738b2c9 2128
323c3d80
JR		 2129 for (i = 0; i < MSRPM_OFFSETS; i++) {
2130 u32 value, p;
2131 u64 offset;
9738b2c9 2132
323c3d80
JR		 2133 if (msrpm_offsets[i] == 0xffffffff)
2134 break;
3d6368ef 2135
0d6b3537
JR		 2136 p = msrpm_offsets[i];
2137 offset = svm->nested.vmcb_msrpm + (p * 4);
323c3d80
JR		 2138
2139 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2140 return false;
2141
2142 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2143 }
3d6368ef 2144
323c3d80 2145 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
9738b2c9
JR		 2146
2147 return true;
3d6368ef
AG		 2148}
2149
52c65a30
JR		 2150static bool nested_vmcb_checks(struct vmcb *vmcb)
2151{
2152 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2153 return false;
2154
dbe77584
JR		 2155 if (vmcb->control.asid == 0)
2156 return false;
2157
4b16184c
JR		 2158 if (vmcb->control.nested_ctl && !npt_enabled)
2159 return false;
2160
52c65a30
JR		 2161 return true;
2162}
2163
9738b2c9 2164static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 2165{
9738b2c9 2166 struct vmcb *nested_vmcb;
e6aa9abd 2167 struct vmcb *hsave = svm->nested.hsave;
defbba56 2168 struct vmcb *vmcb = svm->vmcb;
7597f129 2169 struct page *page;
06fc7772 2170 u64 vmcb_gpa;
3d6368ef 2171
06fc7772 2172 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 2173
7597f129 2174 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 2175 if (!nested_vmcb)
2176 return false;
2177
52c65a30
JR		 2178 if (!nested_vmcb_checks(nested_vmcb)) {
2179 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2180 nested_vmcb->control.exit_code_hi = 0;
2181 nested_vmcb->control.exit_info_1 = 0;
2182 nested_vmcb->control.exit_info_2 = 0;
2183
2184 nested_svm_unmap(page);
2185
2186 return false;
2187 }
2188
b75f4eb3 2189 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
0ac406de
JR		 2190 nested_vmcb->save.rip,
2191 nested_vmcb->control.int_ctl,
2192 nested_vmcb->control.event_inj,
2193 nested_vmcb->control.nested_ctl);
2194
2e554e8d
JR		 2195 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2196 nested_vmcb->control.intercept_cr_write,
2197 nested_vmcb->control.intercept_exceptions,
2198 nested_vmcb->control.intercept);
2199
3d6368ef 2200 /* Clear internal status */
219b65dc
AG		 2201 kvm_clear_exception_queue(&svm->vcpu);
2202 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 2203
e0231715
JR		 2204 /*
2205 * Save the old vmcb, so we don't need to pick what we save, but can
2206 * restore everything when a VMEXIT occurs
2207 */
defbba56
JR		 2208 hsave->save.es = vmcb->save.es;
2209 hsave->save.cs = vmcb->save.cs;
2210 hsave->save.ss = vmcb->save.ss;
2211 hsave->save.ds = vmcb->save.ds;
2212 hsave->save.gdtr = vmcb->save.gdtr;
2213 hsave->save.idtr = vmcb->save.idtr;
f6801dff 2214 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 2215 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 2216 hsave->save.cr4 = svm->vcpu.arch.cr4;
2217 hsave->save.rflags = vmcb->save.rflags;
b75f4eb3 2218 hsave->save.rip = kvm_rip_read(&svm->vcpu);
defbba56
JR		 2219 hsave->save.rsp = vmcb->save.rsp;
2220 hsave->save.rax = vmcb->save.rax;
2221 if (npt_enabled)
2222 hsave->save.cr3 = vmcb->save.cr3;
2223 else
2224 hsave->save.cr3 = svm->vcpu.arch.cr3;
2225
0460a979 2226 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 2227
2228 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2229 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2230 else
2231 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2232
4b16184c
JR		 2233 if (nested_vmcb->control.nested_ctl) {
2234 kvm_mmu_unload(&svm->vcpu);
2235 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2236 nested_svm_init_mmu_context(&svm->vcpu);
2237 }
2238
3d6368ef
AG		 2239 /* Load the nested guest state */
2240 svm->vmcb->save.es = nested_vmcb->save.es;
2241 svm->vmcb->save.cs = nested_vmcb->save.cs;
2242 svm->vmcb->save.ss = nested_vmcb->save.ss;
2243 svm->vmcb->save.ds = nested_vmcb->save.ds;
2244 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2245 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2246 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2247 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2248 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2249 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2250 if (npt_enabled) {
2251 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2252 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 2253 } else
2390218b 2254 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 2255
2256 /* Guest paging mode is active - reset mmu */
2257 kvm_mmu_reset_context(&svm->vcpu);
2258
defbba56 2259 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 2260 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2261 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2262 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 2263
3d6368ef
AG		 2264 /* In case we don't even reach vcpu_run, the fields are not updated */
2265 svm->vmcb->save.rax = nested_vmcb->save.rax;
2266 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2267 svm->vmcb->save.rip = nested_vmcb->save.rip;
2268 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2269 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2270 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2271
f7138538 2272 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
ce2ac085 2273 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3d6368ef 2274
aad42c64
JR		 2275 /* cache intercepts */
2276 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2277 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2278 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2279 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2280 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2281 svm->nested.intercept = nested_vmcb->control.intercept;
2282
3d6368ef 2283 force_new_asid(&svm->vcpu);
3d6368ef 2284 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 2285 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2286 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2287 else
2288 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2289
88ab24ad
JR		 2290 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2291 /* We only want the cr8 intercept bits of the guest */
2292 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2293 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2294 }
2295
0d945bd9
JR		 2296 /* We don't want to see VMMCALLs from a nested guest */
2297 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2298
e0231715
JR		 2299 /*
2300 * We don't want a nested guest to be more powerful than the guest, so
2301 * all intercepts are ORed
2302 */
88ab24ad
JR		 2303 svm->vmcb->control.intercept_cr_read |=
2304 nested_vmcb->control.intercept_cr_read;
2305 svm->vmcb->control.intercept_cr_write |=
2306 nested_vmcb->control.intercept_cr_write;
2307 svm->vmcb->control.intercept_dr_read |=
2308 nested_vmcb->control.intercept_dr_read;
2309 svm->vmcb->control.intercept_dr_write |=
2310 nested_vmcb->control.intercept_dr_write;
2311 svm->vmcb->control.intercept_exceptions |=
2312 nested_vmcb->control.intercept_exceptions;
2313
2314 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2315
2316 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2317 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2318 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2319 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2320 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2321 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2322
7597f129 2323 nested_svm_unmap(page);
9738b2c9 2324
06fc7772
JR		 2325 /* nested_vmcb is our indicator if nested SVM is activated */
2326 svm->nested.vmcb = vmcb_gpa;
9738b2c9 2327
2af9194d 2328 enable_gif(svm);
3d6368ef 2329
9738b2c9 2330 return true;
3d6368ef
AG		 2331}
2332
9966bf68 2333static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2334{
2335 to_vmcb->save.fs = from_vmcb->save.fs;
2336 to_vmcb->save.gs = from_vmcb->save.gs;
2337 to_vmcb->save.tr = from_vmcb->save.tr;
2338 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2339 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2340 to_vmcb->save.star = from_vmcb->save.star;
2341 to_vmcb->save.lstar = from_vmcb->save.lstar;
2342 to_vmcb->save.cstar = from_vmcb->save.cstar;
2343 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2344 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2345 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2346 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2347}
2348
851ba692 2349static int vmload_interception(struct vcpu_svm *svm)
5542675b 2350{
9966bf68 2351 struct vmcb *nested_vmcb;
7597f129 2352 struct page *page;
9966bf68 2353
5542675b
AG		 2354 if (nested_svm_check_permissions(svm))
2355 return 1;
2356
2357 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2358 skip_emulated_instruction(&svm->vcpu);
2359
7597f129 2360 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2361 if (!nested_vmcb)
2362 return 1;
2363
2364 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2365 nested_svm_unmap(page);
5542675b
AG		 2366
2367 return 1;
2368}
2369
851ba692 2370static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2371{
9966bf68 2372 struct vmcb *nested_vmcb;
7597f129 2373 struct page *page;
9966bf68 2374
5542675b
AG		 2375 if (nested_svm_check_permissions(svm))
2376 return 1;
2377
2378 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2379 skip_emulated_instruction(&svm->vcpu);
2380
7597f129 2381 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2382 if (!nested_vmcb)
2383 return 1;
2384
2385 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2386 nested_svm_unmap(page);
5542675b
AG		 2387
2388 return 1;
2389}
2390
851ba692 2391static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2392{
3d6368ef
AG		 2393 if (nested_svm_check_permissions(svm))
2394 return 1;
2395
b75f4eb3
RJ		 2396 /* Save rip after vmrun instruction */
2397 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3d6368ef 2398
9738b2c9 2399 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2400 return 1;
2401
9738b2c9 2402 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2403 goto failed;
2404
2405 return 1;
2406
2407failed:
2408
2409 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2410 svm->vmcb->control.exit_code_hi = 0;
2411 svm->vmcb->control.exit_info_1 = 0;
2412 svm->vmcb->control.exit_info_2 = 0;
2413
2414 nested_svm_vmexit(svm);
3d6368ef
AG		 2415
2416 return 1;
2417}
2418
851ba692 2419static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2420{
2421 if (nested_svm_check_permissions(svm))
2422 return 1;
2423
2424 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2425 skip_emulated_instruction(&svm->vcpu);
3842d135 2426 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
1371d904 2427
2af9194d 2428 enable_gif(svm);
1371d904
AG		 2429
2430 return 1;
2431}
2432
851ba692 2433static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2434{
2435 if (nested_svm_check_permissions(svm))
2436 return 1;
2437
2438 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2439 skip_emulated_instruction(&svm->vcpu);
2440
2af9194d 2441 disable_gif(svm);
1371d904
AG		 2442
2443 /* After a CLGI no interrupts should come */
2444 svm_clear_vintr(svm);
2445 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2446
2447 return 1;
2448}
2449
851ba692 2450static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2451{
2452 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2453
ec1ff790
JR		 2454 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2455 vcpu->arch.regs[VCPU_REGS_RAX]);
2456
ff092385
AG		 2457 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2458 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2459
2460 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2461 skip_emulated_instruction(&svm->vcpu);
2462 return 1;
2463}
2464
532a46b9
JR		 2465static int skinit_interception(struct vcpu_svm *svm)
2466{
2467 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2468
2469 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2470 return 1;
2471}
2472
851ba692 2473static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2474{
7ee5d940 2475 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2476 return 1;
2477}
2478
851ba692 2479static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2480{
37817f29 2481 u16 tss_selector;
64a7ec06
GN		 2482 int reason;
2483 int int_type = svm->vmcb->control.exit_int_info &
2484 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2485 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2486 uint32_t type =
2487 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2488 uint32_t idt_v =
2489 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2490 bool has_error_code = false;
2491 u32 error_code = 0;
37817f29
IE		 2492
2493 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2494
37817f29
IE		 2495 if (svm->vmcb->control.exit_info_2 &
2496 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2497 reason = TASK_SWITCH_IRET;
2498 else if (svm->vmcb->control.exit_info_2 &
2499 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2500 reason = TASK_SWITCH_JMP;
fe8e7f83 2501 else if (idt_v)
64a7ec06
GN		 2502 reason = TASK_SWITCH_GATE;
2503 else
2504 reason = TASK_SWITCH_CALL;
2505
fe8e7f83
GN		 2506 if (reason == TASK_SWITCH_GATE) {
2507 switch (type) {
2508 case SVM_EXITINTINFO_TYPE_NMI:
2509 svm->vcpu.arch.nmi_injected = false;
2510 break;
2511 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2512 if (svm->vmcb->control.exit_info_2 &
2513 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2514 has_error_code = true;
2515 error_code =
2516 (u32)svm->vmcb->control.exit_info_2;
2517 }
fe8e7f83
GN		 2518 kvm_clear_exception_queue(&svm->vcpu);
2519 break;
2520 case SVM_EXITINTINFO_TYPE_INTR:
2521 kvm_clear_interrupt_queue(&svm->vcpu);
2522 break;
2523 default:
2524 break;
2525 }
2526 }
64a7ec06 2527
8317c298
GN		 2528 if (reason != TASK_SWITCH_GATE ||
2529 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2530 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2531 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2532 skip_emulated_instruction(&svm->vcpu);
64a7ec06 2533
acb54517
GN		 2534 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2535 has_error_code, error_code) == EMULATE_FAIL) {
2536 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2537 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2538 svm->vcpu.run->internal.ndata = 0;
2539 return 0;
2540 }
2541 return 1;
6aa8b732
AK		 2542}
2543
851ba692 2544static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2545{
5fdbf976 2546 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2547 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2548 return 1;
6aa8b732
AK		 2549}
2550
851ba692 2551static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2552{
2553 ++svm->vcpu.stat.nmi_window_exits;
061e2fd1 2554 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
44c11430 2555 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2556 return 1;
2557}
2558
851ba692 2559static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2560{
6d77dbfc 2561 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
a7052897
MT		 2562}
2563
851ba692 2564static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2565{
6d77dbfc 2566 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
6aa8b732
AK		 2567}
2568
cda00082
JR		 2569static int cr0_write_interception(struct vcpu_svm *svm)
2570{
2571 struct kvm_vcpu *vcpu = &svm->vcpu;
2572 int r;
2573
2574 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2575
2576 if (svm->nested.vmexit_rip) {
2577 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2578 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2579 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2580 svm->nested.vmexit_rip = 0;
2581 }
2582
2583 return r == EMULATE_DONE;
2584}
2585
851ba692 2586static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2587{
851ba692
AK		 2588 struct kvm_run *kvm_run = svm->vcpu.run;
2589
0a5fff19
GN		 2590 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2591 /* instruction emulation calls kvm_set_cr8() */
851ba692 2592 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2593 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2594 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2595 return 1;
95ba8273 2596 }
0a5fff19
GN		 2597 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2598 return 1;
1d075434
JR		 2599 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2600 return 0;
2601}
2602
6aa8b732
AK		 2603static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2604{
a2fa3e9f
GH		 2605 struct vcpu_svm *svm = to_svm(vcpu);
2606
6aa8b732 2607 switch (ecx) {
af24a4e4 2608 case MSR_IA32_TSC: {
20824f30 2609 u64 tsc_offset;
6aa8b732 2610
20824f30
JR		 2611 if (is_nested(svm))
2612 tsc_offset = svm->nested.hsave->control.tsc_offset;
2613 else
2614 tsc_offset = svm->vmcb->control.tsc_offset;
2615
2616 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2617 break;
2618 }
8c06585d 2619 case MSR_STAR:
a2fa3e9f 2620 *data = svm->vmcb->save.star;
6aa8b732 2621 break;
0e859cac 2622#ifdef CONFIG_X86_64
6aa8b732 2623 case MSR_LSTAR:
a2fa3e9f 2624 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2625 break;
2626 case MSR_CSTAR:
a2fa3e9f 2627 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2628 break;
2629 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2630 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2631 break;
2632 case MSR_SYSCALL_MASK:
a2fa3e9f 2633 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2634 break;
2635#endif
2636 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2637 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2638 break;
2639 case MSR_IA32_SYSENTER_EIP:
017cb99e 2640 *data = svm->sysenter_eip;
6aa8b732
AK		 2641 break;
2642 case MSR_IA32_SYSENTER_ESP:
017cb99e 2643 *data = svm->sysenter_esp;
6aa8b732 2644 break;
e0231715
JR		 2645 /*
2646 * Nobody will change the following 5 values in the VMCB so we can
2647 * safely return them on rdmsr. They will always be 0 until LBRV is
2648 * implemented.
2649 */
a2938c80
JR		 2650 case MSR_IA32_DEBUGCTLMSR:
2651 *data = svm->vmcb->save.dbgctl;
2652 break;
2653 case MSR_IA32_LASTBRANCHFROMIP:
2654 *data = svm->vmcb->save.br_from;
2655 break;
2656 case MSR_IA32_LASTBRANCHTOIP:
2657 *data = svm->vmcb->save.br_to;
2658 break;
2659 case MSR_IA32_LASTINTFROMIP:
2660 *data = svm->vmcb->save.last_excp_from;
2661 break;
2662 case MSR_IA32_LASTINTTOIP:
2663 *data = svm->vmcb->save.last_excp_to;
2664 break;
b286d5d8 2665 case MSR_VM_HSAVE_PA:
e6aa9abd 2666 *data = svm->nested.hsave_msr;
b286d5d8 2667 break;
eb6f302e 2668 case MSR_VM_CR:
4a810181 2669 *data = svm->nested.vm_cr_msr;
eb6f302e 2670 break;
c8a73f18
AG		 2671 case MSR_IA32_UCODE_REV:
2672 *data = 0x01000065;
2673 break;
6aa8b732 2674 default:
3bab1f5d 2675 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2676 }
2677 return 0;
2678}
2679
851ba692 2680static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2681{
ad312c7c 2682 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2683 u64 data;
2684
59200273
AK		 2685 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2686 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2687 kvm_inject_gp(&svm->vcpu, 0);
59200273 2688 } else {
229456fc 2689 trace_kvm_msr_read(ecx, data);
af9ca2d7 2690
5fdbf976 2691 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2692 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2693 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2694 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2695 }
2696 return 1;
2697}
2698
4a810181
JR		 2699static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2700{
2701 struct vcpu_svm *svm = to_svm(vcpu);
2702 int svm_dis, chg_mask;
2703
2704 if (data & ~SVM_VM_CR_VALID_MASK)
2705 return 1;
2706
2707 chg_mask = SVM_VM_CR_VALID_MASK;
2708
2709 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2710 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2711
2712 svm->nested.vm_cr_msr &= ~chg_mask;
2713 svm->nested.vm_cr_msr |= (data & chg_mask);
2714
2715 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2716
2717 /* check for svm_disable while efer.svme is set */
2718 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2719 return 1;
2720
2721 return 0;
2722}
2723
6aa8b732
AK		 2724static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2725{
a2fa3e9f
GH		 2726 struct vcpu_svm *svm = to_svm(vcpu);
2727
6aa8b732 2728 switch (ecx) {
f4e1b3c8 2729 case MSR_IA32_TSC:
99e3e30a 2730 kvm_write_tsc(vcpu, data);
6aa8b732 2731 break;
8c06585d 2732 case MSR_STAR:
a2fa3e9f 2733 svm->vmcb->save.star = data;
6aa8b732 2734 break;
49b14f24 2735#ifdef CONFIG_X86_64
6aa8b732 2736 case MSR_LSTAR:
a2fa3e9f 2737 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2738 break;
2739 case MSR_CSTAR:
a2fa3e9f 2740 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2741 break;
2742 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2743 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2744 break;
2745 case MSR_SYSCALL_MASK:
a2fa3e9f 2746 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2747 break;
2748#endif
2749 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2750 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2751 break;
2752 case MSR_IA32_SYSENTER_EIP:
017cb99e 2753 svm->sysenter_eip = data;
a2fa3e9f 2754 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2755 break;
2756 case MSR_IA32_SYSENTER_ESP:
017cb99e 2757 svm->sysenter_esp = data;
a2fa3e9f 2758 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2759 break;
a2938c80 2760 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2761 if (!svm_has(SVM_FEATURE_LBRV)) {
2762 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2763 __func__, data);
24e09cbf
JR		 2764 break;
2765 }
2766 if (data & DEBUGCTL_RESERVED_BITS)
2767 return 1;
2768
2769 svm->vmcb->save.dbgctl = data;
2770 if (data & (1ULL<<0))
2771 svm_enable_lbrv(svm);
2772 else
2773 svm_disable_lbrv(svm);
a2938c80 2774 break;
b286d5d8 2775 case MSR_VM_HSAVE_PA:
e6aa9abd 2776 svm->nested.hsave_msr = data;
62b9abaa 2777 break;
3c5d0a44 2778 case MSR_VM_CR:
4a810181 2779 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2780 case MSR_VM_IGNNE:
3c5d0a44
AG		 2781 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2782 break;
6aa8b732 2783 default:
3bab1f5d 2784 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2785 }
2786 return 0;
2787}
2788
851ba692 2789static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2790{
ad312c7c 2791 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2792 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2793 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2794
af9ca2d7 2795
5fdbf976 2796 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2797 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2798 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2799 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2800 } else {
2801 trace_kvm_msr_write(ecx, data);
e756fc62 2802 skip_emulated_instruction(&svm->vcpu);
59200273 2803 }
6aa8b732
AK		 2804 return 1;
2805}
2806
851ba692 2807static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2808{
e756fc62 2809 if (svm->vmcb->control.exit_info_1)
851ba692 2810 return wrmsr_interception(svm);
6aa8b732 2811 else
851ba692 2812 return rdmsr_interception(svm);
6aa8b732
AK		 2813}
2814
851ba692 2815static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2816{
851ba692
AK		 2817 struct kvm_run *kvm_run = svm->vcpu.run;
2818
3842d135 2819 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
f0b85051 2820 svm_clear_vintr(svm);
85f455f7 2821 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2822 /*
2823 * If the user space waits to inject interrupts, exit as soon as
2824 * possible
2825 */
8061823a
GN		 2826 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2827 kvm_run->request_interrupt_window &&
2828 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2829 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2830 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2831 return 0;
2832 }
2833
2834 return 1;
2835}
2836
565d0998
ML		 2837static int pause_interception(struct vcpu_svm *svm)
2838{
2839 kvm_vcpu_on_spin(&(svm->vcpu));
2840 return 1;
2841}
2842
851ba692 2843static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2844 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2845 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2846 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2847 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2848 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
cda00082 2849 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
e0231715
JR		 2850 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2851 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2852 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2853 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2854 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2855 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2856 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2857 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2858 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2859 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2860 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2861 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2862 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2863 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2864 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2865 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2866 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2867 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2868 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2869 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2870 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2871 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2872 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2873 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2874 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2875 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2876 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2877 [SVM_EXIT_SMI] = nop_on_interception,
2878 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2879 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2880 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2881 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2882 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2883 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2884 [SVM_EXIT_HLT] = halt_interception,
a7052897 2885 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2886 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2887 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2888 [SVM_EXIT_MSR] = msr_interception,
2889 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2890 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2891 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2892 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2893 [SVM_EXIT_VMLOAD] = vmload_interception,
2894 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2895 [SVM_EXIT_STGI] = stgi_interception,
2896 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2897 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2898 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2899 [SVM_EXIT_MONITOR] = invalid_op_interception,
2900 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2901 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2902};
2903
3f10c846
JR		 2904void dump_vmcb(struct kvm_vcpu *vcpu)
2905{
2906 struct vcpu_svm *svm = to_svm(vcpu);
2907 struct vmcb_control_area *control = &svm->vmcb->control;
2908 struct vmcb_save_area *save = &svm->vmcb->save;
2909
2910 pr_err("VMCB Control Area:\n");
2911 pr_err("cr_read: %04x\n", control->intercept_cr_read);
2912 pr_err("cr_write: %04x\n", control->intercept_cr_write);
2913 pr_err("dr_read: %04x\n", control->intercept_dr_read);
2914 pr_err("dr_write: %04x\n", control->intercept_dr_write);
2915 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2916 pr_err("intercepts: %016llx\n", control->intercept);
2917 pr_err("pause filter count: %d\n", control->pause_filter_count);
2918 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2919 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2920 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2921 pr_err("asid: %d\n", control->asid);
2922 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2923 pr_err("int_ctl: %08x\n", control->int_ctl);
2924 pr_err("int_vector: %08x\n", control->int_vector);
2925 pr_err("int_state: %08x\n", control->int_state);
2926 pr_err("exit_code: %08x\n", control->exit_code);
2927 pr_err("exit_info1: %016llx\n", control->exit_info_1);
2928 pr_err("exit_info2: %016llx\n", control->exit_info_2);
2929 pr_err("exit_int_info: %08x\n", control->exit_int_info);
2930 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
2931 pr_err("nested_ctl: %lld\n", control->nested_ctl);
2932 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
2933 pr_err("event_inj: %08x\n", control->event_inj);
2934 pr_err("event_inj_err: %08x\n", control->event_inj_err);
2935 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
2936 pr_err("next_rip: %016llx\n", control->next_rip);
2937 pr_err("VMCB State Save Area:\n");
2938 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2939 save->es.selector, save->es.attrib,
2940 save->es.limit, save->es.base);
2941 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2942 save->cs.selector, save->cs.attrib,
2943 save->cs.limit, save->cs.base);
2944 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
2945 save->ss.selector, save->ss.attrib,
2946 save->ss.limit, save->ss.base);
2947 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
2948 save->ds.selector, save->ds.attrib,
2949 save->ds.limit, save->ds.base);
2950 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
2951 save->fs.selector, save->fs.attrib,
2952 save->fs.limit, save->fs.base);
2953 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
2954 save->gs.selector, save->gs.attrib,
2955 save->gs.limit, save->gs.base);
2956 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2957 save->gdtr.selector, save->gdtr.attrib,
2958 save->gdtr.limit, save->gdtr.base);
2959 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2960 save->ldtr.selector, save->ldtr.attrib,
2961 save->ldtr.limit, save->ldtr.base);
2962 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2963 save->idtr.selector, save->idtr.attrib,
2964 save->idtr.limit, save->idtr.base);
2965 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
2966 save->tr.selector, save->tr.attrib,
2967 save->tr.limit, save->tr.base);
2968 pr_err("cpl: %d efer: %016llx\n",
2969 save->cpl, save->efer);
2970 pr_err("cr0: %016llx cr2: %016llx\n",
2971 save->cr0, save->cr2);
2972 pr_err("cr3: %016llx cr4: %016llx\n",
2973 save->cr3, save->cr4);
2974 pr_err("dr6: %016llx dr7: %016llx\n",
2975 save->dr6, save->dr7);
2976 pr_err("rip: %016llx rflags: %016llx\n",
2977 save->rip, save->rflags);
2978 pr_err("rsp: %016llx rax: %016llx\n",
2979 save->rsp, save->rax);
2980 pr_err("star: %016llx lstar: %016llx\n",
2981 save->star, save->lstar);
2982 pr_err("cstar: %016llx sfmask: %016llx\n",
2983 save->cstar, save->sfmask);
2984 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
2985 save->kernel_gs_base, save->sysenter_cs);
2986 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
2987 save->sysenter_esp, save->sysenter_eip);
2988 pr_err("gpat: %016llx dbgctl: %016llx\n",
2989 save->g_pat, save->dbgctl);
2990 pr_err("br_from: %016llx br_to: %016llx\n",
2991 save->br_from, save->br_to);
2992 pr_err("excp_from: %016llx excp_to: %016llx\n",
2993 save->last_excp_from, save->last_excp_to);
2994
2995}
2996
851ba692 2997static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2998{
04d2cc77 2999 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 3000 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 3001 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 3002
5bfd8b54 3003 trace_kvm_exit(exit_code, vcpu);
af9ca2d7 3004
2be4fc7a
JR		 3005 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
3006 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3007 if (npt_enabled)
3008 vcpu->arch.cr3 = svm->vmcb->save.cr3;
af9ca2d7 3009
cd3ff653
JR		 3010 if (unlikely(svm->nested.exit_required)) {
3011 nested_svm_vmexit(svm);
3012 svm->nested.exit_required = false;
3013
3014 return 1;
3015 }
3016
cf74a78b 3017 if (is_nested(svm)) {
410e4d57
JR		 3018 int vmexit;
3019
d8cabddf
JR		 3020 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3021 svm->vmcb->control.exit_info_1,
3022 svm->vmcb->control.exit_info_2,
3023 svm->vmcb->control.exit_int_info,
3024 svm->vmcb->control.exit_int_info_err);
3025
410e4d57
JR		 3026 vmexit = nested_svm_exit_special(svm);
3027
3028 if (vmexit == NESTED_EXIT_CONTINUE)
3029 vmexit = nested_svm_exit_handled(svm);
3030
3031 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 3032 return 1;
cf74a78b
AG		 3033 }
3034
a5c3832d
JR		 3035 svm_complete_interrupts(svm);
3036
04d2cc77
AK		 3037 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3038 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3039 kvm_run->fail_entry.hardware_entry_failure_reason
3040 = svm->vmcb->control.exit_code;
3f10c846
JR		 3041 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3042 dump_vmcb(vcpu);
04d2cc77
AK		 3043 return 0;
3044 }
3045
a2fa3e9f 3046 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 3047 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
55c5e464
JR		 3048 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3049 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
6aa8b732
AK		 3050 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3051 "exit_code 0x%x\n",
b8688d51 3052 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 3053 exit_code);
3054
9d8f549d 3055 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 3056 || !svm_exit_handlers[exit_code]) {
6aa8b732 3057 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 3058 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 3059 return 0;
3060 }
3061
851ba692 3062 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 3063}
3064
3065static void reload_tss(struct kvm_vcpu *vcpu)
3066{
3067 int cpu = raw_smp_processor_id();
3068
0fe1e009
TH		 3069 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3070 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 3071 load_TR_desc();
3072}
3073
e756fc62 3074static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 3075{
3076 int cpu = raw_smp_processor_id();
3077
0fe1e009 3078 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 3079
a2fa3e9f 3080 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 3081 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 3082 if (svm->asid_generation != sd->asid_generation)
3083 new_asid(svm, sd);
6aa8b732
AK		 3084}
3085
95ba8273
GN		 3086static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3087{
3088 struct vcpu_svm *svm = to_svm(vcpu);
3089
3090 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3091 vcpu->arch.hflags |= HF_NMI_MASK;
061e2fd1 3092 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
95ba8273
GN		 3093 ++vcpu->stat.nmi_injections;
3094}
6aa8b732 3095
85f455f7 3096static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 3097{
3098 struct vmcb_control_area *control;
3099
e756fc62 3100 control = &svm->vmcb->control;
85f455f7 3101 control->int_vector = irq;
6aa8b732
AK		 3102 control->int_ctl &= ~V_INTR_PRIO_MASK;
3103 control->int_ctl |= V_IRQ_MASK |
3104 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3105}
3106
66fd3f7f 3107static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 3108{
3109 struct vcpu_svm *svm = to_svm(vcpu);
3110
2af9194d 3111 BUG_ON(!(gif_set(svm)));
cf74a78b 3112
9fb2d2b4
GN		 3113 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3114 ++vcpu->stat.irq_injections;
3115
219b65dc
AG		 3116 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3117 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 3118}
3119
95ba8273 3120static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 3121{
3122 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 3123
88ab24ad
JR		 3124 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3125 return;
3126
95ba8273 3127 if (irr == -1)
aaacfc9a
JR		 3128 return;
3129
95ba8273
GN		 3130 if (tpr >= irr)
3131 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
3132}
aaacfc9a 3133
95ba8273
GN		 3134static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3135{
3136 struct vcpu_svm *svm = to_svm(vcpu);
3137 struct vmcb *vmcb = svm->vmcb;
924584cc
JR		 3138 int ret;
3139 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3140 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3141 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3142
3143 return ret;
aaacfc9a
JR		 3144}
3145
3cfc3092
JK		 3146static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3147{
3148 struct vcpu_svm *svm = to_svm(vcpu);
3149
3150 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3151}
3152
3153static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3154{
3155 struct vcpu_svm *svm = to_svm(vcpu);
3156
3157 if (masked) {
3158 svm->vcpu.arch.hflags |= HF_NMI_MASK;
061e2fd1 3159 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3cfc3092
JK		 3160 } else {
3161 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
061e2fd1 3162 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3cfc3092
JK		 3163 }
3164}
3165
78646121
GN		 3166static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3167{
3168 struct vcpu_svm *svm = to_svm(vcpu);
3169 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 3170 int ret;
3171
3172 if (!gif_set(svm) ||
3173 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3174 return 0;
3175
3176 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3177
3178 if (is_nested(svm))
3179 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3180
3181 return ret;
78646121
GN		 3182}
3183
9222be18 3184static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 3185{
219b65dc 3186 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 3187
e0231715
JR		 3188 /*
3189 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3190 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3191 * get that intercept, this function will be called again though and
3192 * we'll get the vintr intercept.
3193 */
8fe54654 3194 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 3195 svm_set_vintr(svm);
3196 svm_inject_irq(svm, 0x0);
3197 }
85f455f7
ED		 3198}
3199
95ba8273 3200static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 3201{
04d2cc77 3202 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 3203
44c11430
GN		 3204 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3205 == HF_NMI_MASK)
3206 return; /* IRET will cause a vm exit */
3207
e0231715
JR		 3208 /*
3209 * Something prevents NMI from been injected. Single step over possible
3210 * problem (IRET or exception injection or interrupt shadow)
3211 */
6be7d306 3212 svm->nmi_singlestep = true;
44c11430
GN		 3213 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3214 update_db_intercept(vcpu);
c1150d8c
DL		 3215}
3216
cbc94022
IE		 3217static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3218{
3219 return 0;
3220}
3221
d9e368d6
AK		 3222static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3223{
3224 force_new_asid(vcpu);
3225}
3226
04d2cc77
AK		 3227static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3228{
3229}
3230
d7bf8221
JR		 3231static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3232{
3233 struct vcpu_svm *svm = to_svm(vcpu);
3234
88ab24ad
JR		 3235 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3236 return;
3237
d7bf8221
JR		 3238 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
3239 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 3240 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 3241 }
3242}
3243
649d6864
JR		 3244static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3245{
3246 struct vcpu_svm *svm = to_svm(vcpu);
3247 u64 cr8;
3248
88ab24ad
JR		 3249 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3250 return;
3251
649d6864
JR		 3252 cr8 = kvm_get_cr8(vcpu);
3253 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3254 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3255}
3256
9222be18
GN		 3257static void svm_complete_interrupts(struct vcpu_svm *svm)
3258{
3259 u8 vector;
3260 int type;
3261 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 3262 unsigned int3_injected = svm->int3_injected;
3263
3264 svm->int3_injected = 0;
9222be18 3265
3842d135 3266 if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
44c11430 3267 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3842d135
AK		 3268 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3269 }
44c11430 3270
9222be18
GN		 3271 svm->vcpu.arch.nmi_injected = false;
3272 kvm_clear_exception_queue(&svm->vcpu);
3273 kvm_clear_interrupt_queue(&svm->vcpu);
3274
3275 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3276 return;
3277
3842d135
AK		 3278 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3279
9222be18
GN		 3280 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3281 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3282
3283 switch (type) {
3284 case SVM_EXITINTINFO_TYPE_NMI:
3285 svm->vcpu.arch.nmi_injected = true;
3286 break;
3287 case SVM_EXITINTINFO_TYPE_EXEPT:
66b7138f
JK		 3288 /*
3289 * In case of software exceptions, do not reinject the vector,
3290 * but re-execute the instruction instead. Rewind RIP first
3291 * if we emulated INT3 before.
3292 */
3293 if (kvm_exception_is_soft(vector)) {
3294 if (vector == BP_VECTOR && int3_injected &&
3295 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3296 kvm_rip_write(&svm->vcpu,
3297 kvm_rip_read(&svm->vcpu) -
3298 int3_injected);
9222be18 3299 break;
66b7138f 3300 }
9222be18
GN		 3301 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3302 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 3303 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 3304
3305 } else
ce7ddec4 3306 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 3307 break;
3308 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 3309 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 3310 break;
3311 default:
3312 break;
3313 }
3314}
3315
b463a6f7
AK		 3316static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3317{
3318 struct vcpu_svm *svm = to_svm(vcpu);
3319 struct vmcb_control_area *control = &svm->vmcb->control;
3320
3321 control->exit_int_info = control->event_inj;
3322 control->exit_int_info_err = control->event_inj_err;
3323 control->event_inj = 0;
3324 svm_complete_interrupts(svm);
3325}
3326
80e31d4f
AK		 3327#ifdef CONFIG_X86_64
3328#define R "r"
3329#else
3330#define R "e"
3331#endif
3332
851ba692 3333static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3334{
a2fa3e9f 3335 struct vcpu_svm *svm = to_svm(vcpu);
d9e368d6 3336
2041a06a
JR		 3337 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3338 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3339 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3340
cd3ff653
JR		 3341 /*
3342 * A vmexit emulation is required before the vcpu can be executed
3343 * again.
3344 */
3345 if (unlikely(svm->nested.exit_required))
3346 return;
3347
e756fc62 3348 pre_svm_run(svm);
6aa8b732 3349
649d6864
JR		 3350 sync_lapic_to_cr8(vcpu);
3351
cda0ffdd 3352 svm->vmcb->save.cr2 = vcpu->arch.cr2;
6aa8b732 3353
04d2cc77
AK		 3354 clgi();
3355
3356 local_irq_enable();
36241b8c 3357
6aa8b732 3358 asm volatile (
80e31d4f
AK		 3359 "push %%"R"bp; \n\t"
3360 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3361 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3362 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3363 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3364 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3365 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 3366#ifdef CONFIG_X86_64
fb3f0f51
RR		 3367 "mov %c[r8](%[svm]), %%r8 \n\t"
3368 "mov %c[r9](%[svm]), %%r9 \n\t"
3369 "mov %c[r10](%[svm]), %%r10 \n\t"
3370 "mov %c[r11](%[svm]), %%r11 \n\t"
3371 "mov %c[r12](%[svm]), %%r12 \n\t"
3372 "mov %c[r13](%[svm]), %%r13 \n\t"
3373 "mov %c[r14](%[svm]), %%r14 \n\t"
3374 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 3375#endif
3376
6aa8b732 3377 /* Enter guest mode */
80e31d4f
AK		 3378 "push %%"R"ax \n\t"
3379 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 3380 __ex(SVM_VMLOAD) "\n\t"
3381 __ex(SVM_VMRUN) "\n\t"
3382 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 3383 "pop %%"R"ax \n\t"
6aa8b732
AK		 3384
3385 /* Save guest registers, load host registers */
80e31d4f
AK		 3386 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3387 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3388 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3389 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3390 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3391 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 3392#ifdef CONFIG_X86_64
fb3f0f51
RR		 3393 "mov %%r8, %c[r8](%[svm]) \n\t"
3394 "mov %%r9, %c[r9](%[svm]) \n\t"
3395 "mov %%r10, %c[r10](%[svm]) \n\t"
3396 "mov %%r11, %c[r11](%[svm]) \n\t"
3397 "mov %%r12, %c[r12](%[svm]) \n\t"
3398 "mov %%r13, %c[r13](%[svm]) \n\t"
3399 "mov %%r14, %c[r14](%[svm]) \n\t"
3400 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 3401#endif
80e31d4f 3402 "pop %%"R"bp"
6aa8b732 3403 :
fb3f0f51 3404 : [svm]"a"(svm),
6aa8b732 3405 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 3406 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3407 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3408 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3409 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3410 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3411 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 3412#ifdef CONFIG_X86_64
ad312c7c
ZX		 3413 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3414 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3415 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3416 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3417 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3418 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3419 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3420 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 3421#endif
54a08c04 3422 : "cc", "memory"
80e31d4f 3423 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 3424#ifdef CONFIG_X86_64
54a08c04
LV		 3425 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3426#endif
3427 );
6aa8b732 3428
6aa8b732 3429 load_host_msrs(vcpu);
dacccfdd
AK		 3430#ifndef CONFIG_X86_64
3431 loadsegment(fs, svm->host.fs);
9581d442 3432#endif
6aa8b732
AK		 3433
3434 reload_tss(vcpu);
3435
56ba47dd
AK		 3436 local_irq_disable();
3437
3438 stgi();
3439
13c34e07
AK		 3440 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3441 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3442 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3443 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3444
d7bf8221
JR		 3445 sync_cr8_to_lapic(vcpu);
3446
a2fa3e9f 3447 svm->next_rip = 0;
9222be18 3448
631bc487
GN		 3449 /* if exit due to PF check for async PF */
3450 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3451 svm->apf_reason = kvm_read_and_reset_pf_reason();
3452
6de4f3ad
AK		 3453 if (npt_enabled) {
3454 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3455 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3456 }
fe5913e4
JR		 3457
3458 /*
3459 * We need to handle MC intercepts here before the vcpu has a chance to
3460 * change the physical cpu
3461 */
3462 if (unlikely(svm->vmcb->control.exit_code ==
3463 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3464 svm_handle_mce(svm);
6aa8b732
AK		 3465}
3466
80e31d4f
AK		 3467#undef R
3468
6aa8b732
AK		 3469static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3470{
a2fa3e9f
GH		 3471 struct vcpu_svm *svm = to_svm(vcpu);
3472
3473 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 3474 force_new_asid(vcpu);
3475}
3476
1c97f0a0
JR		 3477static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3478{
3479 struct vcpu_svm *svm = to_svm(vcpu);
3480
3481 svm->vmcb->control.nested_cr3 = root;
3482
3483 /* Also sync guest cr3 here in case we live migrate */
3484 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3485
3486 force_new_asid(vcpu);
3487}
3488
6aa8b732
AK		 3489static int is_disabled(void)
3490{
6031a61c
JR		 3491 u64 vm_cr;
3492
3493 rdmsrl(MSR_VM_CR, vm_cr);
3494 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3495 return 1;
3496
6aa8b732
AK		 3497 return 0;
3498}
3499
102d8325
IM		 3500static void
3501svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3502{
3503 /*
3504 * Patch in the VMMCALL instruction:
3505 */
3506 hypercall[0] = 0x0f;
3507 hypercall[1] = 0x01;
3508 hypercall[2] = 0xd9;
102d8325
IM		 3509}
3510
002c7f7c
YS		 3511static void svm_check_processor_compat(void *rtn)
3512{
3513 *(int *)rtn = 0;
3514}
3515
774ead3a
AK		 3516static bool svm_cpu_has_accelerated_tpr(void)
3517{
3518 return false;
3519}
3520
4b12f0de 3521static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3522{
3523 return 0;
3524}
3525
0e851880
SY		 3526static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3527{
3528}
3529
d4330ef2
JR		 3530static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3531{
c2c63a49 3532 switch (func) {
24d1b15f
JR		 3533 case 0x00000001:
3534 /* Mask out xsave bit as long as it is not supported by SVM */
3535 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3536 break;
4c62a2dc
JR		 3537 case 0x80000001:
3538 if (nested)
3539 entry->ecx |= (1 << 2); /* Set SVM bit */
3540 break;
c2c63a49
JR		 3541 case 0x8000000A:
3542 entry->eax = 1; /* SVM revision 1 */
3543 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3544 ASID emulation to nested SVM */
3545 entry->ecx = 0; /* Reserved */
7a190667
JR		 3546 entry->edx = 0; /* Per default do not support any
3547 additional features */
3548
3549 /* Support next_rip if host supports it */
3550 if (svm_has(SVM_FEATURE_NRIP))
3551 entry->edx |= SVM_FEATURE_NRIP;
c2c63a49 3552
3d4aeaad
JR		 3553 /* Support NPT for the guest if enabled */
3554 if (npt_enabled)
3555 entry->edx |= SVM_FEATURE_NPT;
3556
c2c63a49
JR		 3557 break;
3558 }
d4330ef2
JR		 3559}
3560
229456fc 3561static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 3562 { SVM_EXIT_READ_CR0, "read_cr0" },
3563 { SVM_EXIT_READ_CR3, "read_cr3" },
3564 { SVM_EXIT_READ_CR4, "read_cr4" },
3565 { SVM_EXIT_READ_CR8, "read_cr8" },
3566 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3567 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3568 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3569 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3570 { SVM_EXIT_READ_DR0, "read_dr0" },
3571 { SVM_EXIT_READ_DR1, "read_dr1" },
3572 { SVM_EXIT_READ_DR2, "read_dr2" },
3573 { SVM_EXIT_READ_DR3, "read_dr3" },
3574 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3575 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3576 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3577 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3578 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3579 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3580 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3581 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3582 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3583 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3584 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3585 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3586 { SVM_EXIT_INTR, "interrupt" },
3587 { SVM_EXIT_NMI, "nmi" },
3588 { SVM_EXIT_SMI, "smi" },
3589 { SVM_EXIT_INIT, "init" },
3590 { SVM_EXIT_VINTR, "vintr" },
3591 { SVM_EXIT_CPUID, "cpuid" },
3592 { SVM_EXIT_INVD, "invd" },
3593 { SVM_EXIT_HLT, "hlt" },
3594 { SVM_EXIT_INVLPG, "invlpg" },
3595 { SVM_EXIT_INVLPGA, "invlpga" },
3596 { SVM_EXIT_IOIO, "io" },
3597 { SVM_EXIT_MSR, "msr" },
3598 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3599 { SVM_EXIT_SHUTDOWN, "shutdown" },
3600 { SVM_EXIT_VMRUN, "vmrun" },
3601 { SVM_EXIT_VMMCALL, "hypercall" },
3602 { SVM_EXIT_VMLOAD, "vmload" },
3603 { SVM_EXIT_VMSAVE, "vmsave" },
3604 { SVM_EXIT_STGI, "stgi" },
3605 { SVM_EXIT_CLGI, "clgi" },
3606 { SVM_EXIT_SKINIT, "skinit" },
3607 { SVM_EXIT_WBINVD, "wbinvd" },
3608 { SVM_EXIT_MONITOR, "monitor" },
3609 { SVM_EXIT_MWAIT, "mwait" },
3610 { SVM_EXIT_NPF, "npf" },
3611 { -1, NULL }
3612};
3613
17cc3935 3614static int svm_get_lpage_level(void)
344f414f 3615{
17cc3935 3616 return PT_PDPE_LEVEL;
344f414f
JR		 3617}
3618
4e47c7a6
SY		 3619static bool svm_rdtscp_supported(void)
3620{
3621 return false;
3622}
3623
f5f48ee1
SY		 3624static bool svm_has_wbinvd_exit(void)
3625{
3626 return true;
3627}
3628
02daab21
AK		 3629static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3630{
3631 struct vcpu_svm *svm = to_svm(vcpu);
3632
02daab21 3633 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
66a562f7
JR		 3634 if (is_nested(svm))
3635 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3636 update_cr0_intercept(svm);
02daab21
AK		 3637}
3638
cbdd1bea 3639static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3640 .cpu_has_kvm_support = has_svm,
3641 .disabled_by_bios = is_disabled,
3642 .hardware_setup = svm_hardware_setup,
3643 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3644 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3645 .hardware_enable = svm_hardware_enable,
3646 .hardware_disable = svm_hardware_disable,
774ead3a 3647 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3648
3649 .vcpu_create = svm_create_vcpu,
3650 .vcpu_free = svm_free_vcpu,
04d2cc77 3651 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3652
04d2cc77 3653 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3654 .vcpu_load = svm_vcpu_load,
3655 .vcpu_put = svm_vcpu_put,
3656
3657 .set_guest_debug = svm_guest_debug,
3658 .get_msr = svm_get_msr,
3659 .set_msr = svm_set_msr,
3660 .get_segment_base = svm_get_segment_base,
3661 .get_segment = svm_get_segment,
3662 .set_segment = svm_set_segment,
2e4d2653 3663 .get_cpl = svm_get_cpl,
1747fb71 3664 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3665 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3666 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3667 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3668 .set_cr3 = svm_set_cr3,
3669 .set_cr4 = svm_set_cr4,
3670 .set_efer = svm_set_efer,
3671 .get_idt = svm_get_idt,
3672 .set_idt = svm_set_idt,
3673 .get_gdt = svm_get_gdt,
3674 .set_gdt = svm_set_gdt,
020df079 3675 .set_dr7 = svm_set_dr7,
6de4f3ad 3676 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3677 .get_rflags = svm_get_rflags,
3678 .set_rflags = svm_set_rflags,
6b52d186 3679 .fpu_activate = svm_fpu_activate,
02daab21 3680 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3681
6aa8b732 3682 .tlb_flush = svm_flush_tlb,
6aa8b732 3683
6aa8b732 3684 .run = svm_vcpu_run,
04d2cc77 3685 .handle_exit = handle_exit,
6aa8b732 3686 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3687 .set_interrupt_shadow = svm_set_interrupt_shadow,
3688 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3689 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3690 .set_irq = svm_set_irq,
95ba8273 3691 .set_nmi = svm_inject_nmi,
298101da 3692 .queue_exception = svm_queue_exception,
b463a6f7 3693 .cancel_injection = svm_cancel_injection,
78646121 3694 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3695 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3696 .get_nmi_mask = svm_get_nmi_mask,
3697 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3698 .enable_nmi_window = enable_nmi_window,
3699 .enable_irq_window = enable_irq_window,
3700 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3701
3702 .set_tss_addr = svm_set_tss_addr,
67253af5 3703 .get_tdp_level = get_npt_level,
4b12f0de 3704 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3705
3706 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3707 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3708
3709 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3710
3711 .rdtscp_supported = svm_rdtscp_supported,
d4330ef2
JR		 3712
3713 .set_supported_cpuid = svm_set_supported_cpuid,
f5f48ee1
SY		 3714
3715 .has_wbinvd_exit = svm_has_wbinvd_exit,
99e3e30a
ZA		 3716
3717 .write_tsc_offset = svm_write_tsc_offset,
e48672fa 3718 .adjust_tsc_offset = svm_adjust_tsc_offset,
1c97f0a0
JR		 3719
3720 .set_tdp_cr3 = set_tdp_cr3,
6aa8b732
AK		 3721};
3722
3723static int __init svm_init(void)
3724{
cb498ea2 3725 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
0ee75bea 3726 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 3727}
3728
3729static void __exit svm_exit(void)
3730{
cb498ea2 3731 kvm_exit();
6aa8b732
AK		 3732}
3733
3734module_init(svm_init)
3735module_exit(svm_exit)
Linux 6.x block layer and io_uring tree(s)