Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 7 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
8 | * |
9 | * Authors: | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
44a95dae SS |
17 | |
18 | #define pr_fmt(fmt) "SVM: " fmt | |
19 | ||
edf88417 AK |
20 | #include <linux/kvm_host.h> |
21 | ||
85f455f7 | 22 | #include "irq.h" |
1d737c8a | 23 | #include "mmu.h" |
5fdbf976 | 24 | #include "kvm_cache_regs.h" |
fe4c7b19 | 25 | #include "x86.h" |
66f7b72e | 26 | #include "cpuid.h" |
25462f7f | 27 | #include "pmu.h" |
e495606d | 28 | |
6aa8b732 | 29 | #include <linux/module.h> |
ae759544 | 30 | #include <linux/mod_devicetable.h> |
9d8f549d | 31 | #include <linux/kernel.h> |
6aa8b732 AK |
32 | #include <linux/vmalloc.h> |
33 | #include <linux/highmem.h> | |
e8edc6e0 | 34 | #include <linux/sched.h> |
af658dca | 35 | #include <linux/trace_events.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
5881f737 SS |
37 | #include <linux/amd-iommu.h> |
38 | #include <linux/hashtable.h> | |
c207aee4 | 39 | #include <linux/frame.h> |
6aa8b732 | 40 | |
8221c137 | 41 | #include <asm/apic.h> |
1018faa6 | 42 | #include <asm/perf_event.h> |
67ec6607 | 43 | #include <asm/tlbflush.h> |
e495606d | 44 | #include <asm/desc.h> |
facb0139 | 45 | #include <asm/debugreg.h> |
631bc487 | 46 | #include <asm/kvm_para.h> |
411b44ba | 47 | #include <asm/irq_remapping.h> |
117cc7a9 | 48 | #include <asm/nospec-branch.h> |
6aa8b732 | 49 | |
63d1142f | 50 | #include <asm/virtext.h> |
229456fc | 51 | #include "trace.h" |
63d1142f | 52 | |
4ecac3fd AK |
53 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
54 | ||
6aa8b732 AK |
55 | MODULE_AUTHOR("Qumranet"); |
56 | MODULE_LICENSE("GPL"); | |
57 | ||
ae759544 JT |
58 | static const struct x86_cpu_id svm_cpu_id[] = { |
59 | X86_FEATURE_MATCH(X86_FEATURE_SVM), | |
60 | {} | |
61 | }; | |
62 | MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id); | |
63 | ||
6aa8b732 AK |
64 | #define IOPM_ALLOC_ORDER 2 |
65 | #define MSRPM_ALLOC_ORDER 1 | |
66 | ||
6aa8b732 AK |
67 | #define SEG_TYPE_LDT 2 |
68 | #define SEG_TYPE_BUSY_TSS16 3 | |
69 | ||
6bc31bdc AP |
70 | #define SVM_FEATURE_NPT (1 << 0) |
71 | #define SVM_FEATURE_LBRV (1 << 1) | |
72 | #define SVM_FEATURE_SVML (1 << 2) | |
73 | #define SVM_FEATURE_NRIP (1 << 3) | |
ddce97aa AP |
74 | #define SVM_FEATURE_TSC_RATE (1 << 4) |
75 | #define SVM_FEATURE_VMCB_CLEAN (1 << 5) | |
76 | #define SVM_FEATURE_FLUSH_ASID (1 << 6) | |
77 | #define SVM_FEATURE_DECODE_ASSIST (1 << 7) | |
6bc31bdc | 78 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) |
80b7706e | 79 | |
340d3bc3 SS |
80 | #define SVM_AVIC_DOORBELL 0xc001011b |
81 | ||
410e4d57 JR |
82 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
83 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
84 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
85 | ||
24e09cbf JR |
86 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
87 | ||
fbc0db76 | 88 | #define TSC_RATIO_RSVD 0xffffff0000000000ULL |
92a1f12d JR |
89 | #define TSC_RATIO_MIN 0x0000000000000001ULL |
90 | #define TSC_RATIO_MAX 0x000000ffffffffffULL | |
fbc0db76 | 91 | |
5446a979 | 92 | #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF) |
44a95dae SS |
93 | |
94 | /* | |
95 | * 0xff is broadcast, so the max index allowed for physical APIC ID | |
96 | * table is 0xfe. APIC IDs above 0xff are reserved. | |
97 | */ | |
98 | #define AVIC_MAX_PHYSICAL_ID_COUNT 255 | |
99 | ||
18f40c53 SS |
100 | #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1 |
101 | #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0 | |
102 | #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF | |
103 | ||
5ea11f2b SS |
104 | /* AVIC GATAG is encoded using VM and VCPU IDs */ |
105 | #define AVIC_VCPU_ID_BITS 8 | |
106 | #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1) | |
107 | ||
108 | #define AVIC_VM_ID_BITS 24 | |
109 | #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS) | |
110 | #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1) | |
111 | ||
112 | #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \ | |
113 | (y & AVIC_VCPU_ID_MASK)) | |
114 | #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK) | |
115 | #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK) | |
116 | ||
67ec6607 JR |
117 | static bool erratum_383_found __read_mostly; |
118 | ||
6c8166a7 AK |
119 | static const u32 host_save_user_msrs[] = { |
120 | #ifdef CONFIG_X86_64 | |
121 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
122 | MSR_FS_BASE, | |
123 | #endif | |
124 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
46896c73 | 125 | MSR_TSC_AUX, |
6c8166a7 AK |
126 | }; |
127 | ||
128 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
129 | ||
130 | struct kvm_vcpu; | |
131 | ||
e6aa9abd JR |
132 | struct nested_state { |
133 | struct vmcb *hsave; | |
134 | u64 hsave_msr; | |
4a810181 | 135 | u64 vm_cr_msr; |
e6aa9abd JR |
136 | u64 vmcb; |
137 | ||
138 | /* These are the merged vectors */ | |
139 | u32 *msrpm; | |
140 | ||
141 | /* gpa pointers to the real vectors */ | |
142 | u64 vmcb_msrpm; | |
ce2ac085 | 143 | u64 vmcb_iopm; |
aad42c64 | 144 | |
cd3ff653 JR |
145 | /* A VMEXIT is required but not yet emulated */ |
146 | bool exit_required; | |
147 | ||
aad42c64 | 148 | /* cache for intercepts of the guest */ |
4ee546b4 | 149 | u32 intercept_cr; |
3aed041a | 150 | u32 intercept_dr; |
aad42c64 JR |
151 | u32 intercept_exceptions; |
152 | u64 intercept; | |
153 | ||
5bd2edc3 JR |
154 | /* Nested Paging related state */ |
155 | u64 nested_cr3; | |
e6aa9abd JR |
156 | }; |
157 | ||
323c3d80 JR |
158 | #define MSRPM_OFFSETS 16 |
159 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
160 | ||
2b036c6b BO |
161 | /* |
162 | * Set osvw_len to higher value when updated Revision Guides | |
163 | * are published and we know what the new status bits are | |
164 | */ | |
165 | static uint64_t osvw_len = 4, osvw_status; | |
166 | ||
6c8166a7 AK |
167 | struct vcpu_svm { |
168 | struct kvm_vcpu vcpu; | |
169 | struct vmcb *vmcb; | |
170 | unsigned long vmcb_pa; | |
171 | struct svm_cpu_data *svm_data; | |
172 | uint64_t asid_generation; | |
173 | uint64_t sysenter_esp; | |
174 | uint64_t sysenter_eip; | |
46896c73 | 175 | uint64_t tsc_aux; |
6c8166a7 AK |
176 | |
177 | u64 next_rip; | |
178 | ||
179 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
afe9e66f | 180 | struct { |
dacccfdd AK |
181 | u16 fs; |
182 | u16 gs; | |
183 | u16 ldt; | |
afe9e66f AK |
184 | u64 gs_base; |
185 | } host; | |
6c8166a7 AK |
186 | |
187 | u32 *msrpm; | |
6c8166a7 | 188 | |
bd3d1ec3 AK |
189 | ulong nmi_iret_rip; |
190 | ||
e6aa9abd | 191 | struct nested_state nested; |
6be7d306 JK |
192 | |
193 | bool nmi_singlestep; | |
ab2f4d73 | 194 | u64 nmi_singlestep_guest_rflags; |
66b7138f JK |
195 | |
196 | unsigned int3_injected; | |
197 | unsigned long int3_rip; | |
fbc0db76 | 198 | |
6092d3d3 JR |
199 | /* cached guest cpuid flags for faster access */ |
200 | bool nrips_enabled : 1; | |
44a95dae | 201 | |
18f40c53 | 202 | u32 ldr_reg; |
44a95dae SS |
203 | struct page *avic_backing_page; |
204 | u64 *avic_physical_id_cache; | |
8221c137 | 205 | bool avic_is_running; |
411b44ba SS |
206 | |
207 | /* | |
208 | * Per-vcpu list of struct amd_svm_iommu_ir: | |
209 | * This is used mainly to store interrupt remapping information used | |
210 | * when update the vcpu affinity. This avoids the need to scan for | |
211 | * IRTE and try to match ga_tag in the IOMMU driver. | |
212 | */ | |
213 | struct list_head ir_list; | |
214 | spinlock_t ir_list_lock; | |
215 | }; | |
216 | ||
217 | /* | |
218 | * This is a wrapper of struct amd_iommu_ir_data. | |
219 | */ | |
220 | struct amd_svm_iommu_ir { | |
221 | struct list_head node; /* Used by SVM for per-vcpu ir_list */ | |
222 | void *data; /* Storing pointer to struct amd_ir_data */ | |
6c8166a7 AK |
223 | }; |
224 | ||
44a95dae SS |
225 | #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF) |
226 | #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) | |
227 | ||
228 | #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL) | |
229 | #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12) | |
230 | #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) | |
231 | #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63) | |
232 | ||
fbc0db76 JR |
233 | static DEFINE_PER_CPU(u64, current_tsc_ratio); |
234 | #define TSC_RATIO_DEFAULT 0x0100000000ULL | |
235 | ||
455716fa JR |
236 | #define MSR_INVALID 0xffffffffU |
237 | ||
09941fbb | 238 | static const struct svm_direct_access_msrs { |
ac72a9b7 JR |
239 | u32 index; /* Index of the MSR */ |
240 | bool always; /* True if intercept is always on */ | |
241 | } direct_access_msrs[] = { | |
8c06585d | 242 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
243 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
244 | #ifdef CONFIG_X86_64 | |
245 | { .index = MSR_GS_BASE, .always = true }, | |
246 | { .index = MSR_FS_BASE, .always = true }, | |
247 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
248 | { .index = MSR_LSTAR, .always = true }, | |
249 | { .index = MSR_CSTAR, .always = true }, | |
250 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
251 | #endif | |
15d45071 | 252 | { .index = MSR_IA32_PRED_CMD, .always = false }, |
ac72a9b7 JR |
253 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, |
254 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
255 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
256 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
257 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
258 | }; |
259 | ||
709ddebf JR |
260 | /* enable NPT for AMD64 and X86 with PAE */ |
261 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
262 | static bool npt_enabled = true; | |
263 | #else | |
e0231715 | 264 | static bool npt_enabled; |
709ddebf | 265 | #endif |
6c7dac72 | 266 | |
e2358851 DB |
267 | /* allow nested paging (virtualized MMU) for all guests */ |
268 | static int npt = true; | |
6c7dac72 | 269 | module_param(npt, int, S_IRUGO); |
e3da3acd | 270 | |
e2358851 DB |
271 | /* allow nested virtualization in KVM/SVM */ |
272 | static int nested = true; | |
236de055 AG |
273 | module_param(nested, int, S_IRUGO); |
274 | ||
44a95dae SS |
275 | /* enable / disable AVIC */ |
276 | static int avic; | |
5b8abf1f | 277 | #ifdef CONFIG_X86_LOCAL_APIC |
44a95dae | 278 | module_param(avic, int, S_IRUGO); |
5b8abf1f | 279 | #endif |
44a95dae | 280 | |
89c8a498 JN |
281 | /* enable/disable Virtual VMLOAD VMSAVE */ |
282 | static int vls = true; | |
283 | module_param(vls, int, 0444); | |
284 | ||
640bd6e5 JN |
285 | /* enable/disable Virtual GIF */ |
286 | static int vgif = true; | |
287 | module_param(vgif, int, 0444); | |
5ea11f2b | 288 | |
79a8059d | 289 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
44874f84 | 290 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 291 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 292 | |
410e4d57 | 293 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 294 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 295 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
296 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
297 | bool has_error_code, u32 error_code); | |
298 | ||
8d28fec4 | 299 | enum { |
116a0a23 JR |
300 | VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, |
301 | pause filter count */ | |
f56838e4 | 302 | VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ |
d48086d1 | 303 | VMCB_ASID, /* ASID */ |
decdbf6a | 304 | VMCB_INTR, /* int_ctl, int_vector */ |
b2747166 | 305 | VMCB_NPT, /* npt_en, nCR3, gPAT */ |
dcca1a65 | 306 | VMCB_CR, /* CR0, CR3, CR4, EFER */ |
72214b96 | 307 | VMCB_DR, /* DR6, DR7 */ |
17a703cb | 308 | VMCB_DT, /* GDT, IDT */ |
060d0c9a | 309 | VMCB_SEG, /* CS, DS, SS, ES, CPL */ |
0574dec0 | 310 | VMCB_CR2, /* CR2 only */ |
b53ba3f9 | 311 | VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ |
44a95dae SS |
312 | VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, |
313 | * AVIC PHYSICAL_TABLE pointer, | |
314 | * AVIC LOGICAL_TABLE pointer | |
315 | */ | |
8d28fec4 RJ |
316 | VMCB_DIRTY_MAX, |
317 | }; | |
318 | ||
0574dec0 JR |
319 | /* TPR and CR2 are always written before VMRUN */ |
320 | #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) | |
8d28fec4 | 321 | |
44a95dae SS |
322 | #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL |
323 | ||
8d28fec4 RJ |
324 | static inline void mark_all_dirty(struct vmcb *vmcb) |
325 | { | |
326 | vmcb->control.clean = 0; | |
327 | } | |
328 | ||
329 | static inline void mark_all_clean(struct vmcb *vmcb) | |
330 | { | |
331 | vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) | |
332 | & ~VMCB_ALWAYS_DIRTY_MASK; | |
333 | } | |
334 | ||
335 | static inline void mark_dirty(struct vmcb *vmcb, int bit) | |
336 | { | |
337 | vmcb->control.clean &= ~(1 << bit); | |
338 | } | |
339 | ||
a2fa3e9f GH |
340 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
341 | { | |
fb3f0f51 | 342 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
343 | } |
344 | ||
44a95dae SS |
345 | static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data) |
346 | { | |
347 | svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK; | |
348 | mark_dirty(svm->vmcb, VMCB_AVIC); | |
349 | } | |
350 | ||
340d3bc3 SS |
351 | static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu) |
352 | { | |
353 | struct vcpu_svm *svm = to_svm(vcpu); | |
354 | u64 *entry = svm->avic_physical_id_cache; | |
355 | ||
356 | if (!entry) | |
357 | return false; | |
358 | ||
359 | return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); | |
360 | } | |
361 | ||
384c6368 JR |
362 | static void recalc_intercepts(struct vcpu_svm *svm) |
363 | { | |
364 | struct vmcb_control_area *c, *h; | |
365 | struct nested_state *g; | |
366 | ||
116a0a23 JR |
367 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
368 | ||
384c6368 JR |
369 | if (!is_guest_mode(&svm->vcpu)) |
370 | return; | |
371 | ||
372 | c = &svm->vmcb->control; | |
373 | h = &svm->nested.hsave->control; | |
374 | g = &svm->nested; | |
375 | ||
4ee546b4 | 376 | c->intercept_cr = h->intercept_cr | g->intercept_cr; |
3aed041a | 377 | c->intercept_dr = h->intercept_dr | g->intercept_dr; |
bd89525a | 378 | c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions; |
384c6368 JR |
379 | c->intercept = h->intercept | g->intercept; |
380 | } | |
381 | ||
4ee546b4 RJ |
382 | static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) |
383 | { | |
384 | if (is_guest_mode(&svm->vcpu)) | |
385 | return svm->nested.hsave; | |
386 | else | |
387 | return svm->vmcb; | |
388 | } | |
389 | ||
390 | static inline void set_cr_intercept(struct vcpu_svm *svm, int bit) | |
391 | { | |
392 | struct vmcb *vmcb = get_host_vmcb(svm); | |
393 | ||
394 | vmcb->control.intercept_cr |= (1U << bit); | |
395 | ||
396 | recalc_intercepts(svm); | |
397 | } | |
398 | ||
399 | static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit) | |
400 | { | |
401 | struct vmcb *vmcb = get_host_vmcb(svm); | |
402 | ||
403 | vmcb->control.intercept_cr &= ~(1U << bit); | |
404 | ||
405 | recalc_intercepts(svm); | |
406 | } | |
407 | ||
408 | static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit) | |
409 | { | |
410 | struct vmcb *vmcb = get_host_vmcb(svm); | |
411 | ||
412 | return vmcb->control.intercept_cr & (1U << bit); | |
413 | } | |
414 | ||
5315c716 | 415 | static inline void set_dr_intercepts(struct vcpu_svm *svm) |
3aed041a JR |
416 | { |
417 | struct vmcb *vmcb = get_host_vmcb(svm); | |
418 | ||
5315c716 PB |
419 | vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ) |
420 | | (1 << INTERCEPT_DR1_READ) | |
421 | | (1 << INTERCEPT_DR2_READ) | |
422 | | (1 << INTERCEPT_DR3_READ) | |
423 | | (1 << INTERCEPT_DR4_READ) | |
424 | | (1 << INTERCEPT_DR5_READ) | |
425 | | (1 << INTERCEPT_DR6_READ) | |
426 | | (1 << INTERCEPT_DR7_READ) | |
427 | | (1 << INTERCEPT_DR0_WRITE) | |
428 | | (1 << INTERCEPT_DR1_WRITE) | |
429 | | (1 << INTERCEPT_DR2_WRITE) | |
430 | | (1 << INTERCEPT_DR3_WRITE) | |
431 | | (1 << INTERCEPT_DR4_WRITE) | |
432 | | (1 << INTERCEPT_DR5_WRITE) | |
433 | | (1 << INTERCEPT_DR6_WRITE) | |
434 | | (1 << INTERCEPT_DR7_WRITE); | |
3aed041a JR |
435 | |
436 | recalc_intercepts(svm); | |
437 | } | |
438 | ||
5315c716 | 439 | static inline void clr_dr_intercepts(struct vcpu_svm *svm) |
3aed041a JR |
440 | { |
441 | struct vmcb *vmcb = get_host_vmcb(svm); | |
442 | ||
5315c716 | 443 | vmcb->control.intercept_dr = 0; |
3aed041a JR |
444 | |
445 | recalc_intercepts(svm); | |
446 | } | |
447 | ||
18c918c5 JR |
448 | static inline void set_exception_intercept(struct vcpu_svm *svm, int bit) |
449 | { | |
450 | struct vmcb *vmcb = get_host_vmcb(svm); | |
451 | ||
452 | vmcb->control.intercept_exceptions |= (1U << bit); | |
453 | ||
454 | recalc_intercepts(svm); | |
455 | } | |
456 | ||
457 | static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit) | |
458 | { | |
459 | struct vmcb *vmcb = get_host_vmcb(svm); | |
460 | ||
461 | vmcb->control.intercept_exceptions &= ~(1U << bit); | |
462 | ||
463 | recalc_intercepts(svm); | |
464 | } | |
465 | ||
8a05a1b8 JR |
466 | static inline void set_intercept(struct vcpu_svm *svm, int bit) |
467 | { | |
468 | struct vmcb *vmcb = get_host_vmcb(svm); | |
469 | ||
470 | vmcb->control.intercept |= (1ULL << bit); | |
471 | ||
472 | recalc_intercepts(svm); | |
473 | } | |
474 | ||
475 | static inline void clr_intercept(struct vcpu_svm *svm, int bit) | |
476 | { | |
477 | struct vmcb *vmcb = get_host_vmcb(svm); | |
478 | ||
479 | vmcb->control.intercept &= ~(1ULL << bit); | |
480 | ||
481 | recalc_intercepts(svm); | |
482 | } | |
483 | ||
640bd6e5 JN |
484 | static inline bool vgif_enabled(struct vcpu_svm *svm) |
485 | { | |
486 | return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK); | |
487 | } | |
488 | ||
2af9194d JR |
489 | static inline void enable_gif(struct vcpu_svm *svm) |
490 | { | |
640bd6e5 JN |
491 | if (vgif_enabled(svm)) |
492 | svm->vmcb->control.int_ctl |= V_GIF_MASK; | |
493 | else | |
494 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
2af9194d JR |
495 | } |
496 | ||
497 | static inline void disable_gif(struct vcpu_svm *svm) | |
498 | { | |
640bd6e5 JN |
499 | if (vgif_enabled(svm)) |
500 | svm->vmcb->control.int_ctl &= ~V_GIF_MASK; | |
501 | else | |
502 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
2af9194d JR |
503 | } |
504 | ||
505 | static inline bool gif_set(struct vcpu_svm *svm) | |
506 | { | |
640bd6e5 JN |
507 | if (vgif_enabled(svm)) |
508 | return !!(svm->vmcb->control.int_ctl & V_GIF_MASK); | |
509 | else | |
510 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
2af9194d JR |
511 | } |
512 | ||
4866d5e3 | 513 | static unsigned long iopm_base; |
6aa8b732 AK |
514 | |
515 | struct kvm_ldttss_desc { | |
516 | u16 limit0; | |
517 | u16 base0; | |
e0231715 JR |
518 | unsigned base1:8, type:5, dpl:2, p:1; |
519 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
520 | u32 base3; |
521 | u32 zero1; | |
522 | } __attribute__((packed)); | |
523 | ||
524 | struct svm_cpu_data { | |
525 | int cpu; | |
526 | ||
5008fdf5 AK |
527 | u64 asid_generation; |
528 | u32 max_asid; | |
529 | u32 next_asid; | |
6aa8b732 AK |
530 | struct kvm_ldttss_desc *tss_desc; |
531 | ||
532 | struct page *save_area; | |
15d45071 | 533 | struct vmcb *current_vmcb; |
6aa8b732 AK |
534 | }; |
535 | ||
536 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
537 | ||
538 | struct svm_init_data { | |
539 | int cpu; | |
540 | int r; | |
541 | }; | |
542 | ||
09941fbb | 543 | static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; |
6aa8b732 | 544 | |
9d8f549d | 545 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
546 | #define MSRS_RANGE_SIZE 2048 |
547 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
548 | ||
455716fa JR |
549 | static u32 svm_msrpm_offset(u32 msr) |
550 | { | |
551 | u32 offset; | |
552 | int i; | |
553 | ||
554 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
555 | if (msr < msrpm_ranges[i] || | |
556 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
557 | continue; | |
558 | ||
559 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
560 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
561 | ||
562 | /* Now we have the u8 offset - but need the u32 offset */ | |
563 | return offset / 4; | |
564 | } | |
565 | ||
566 | /* MSR not in any range */ | |
567 | return MSR_INVALID; | |
568 | } | |
569 | ||
6aa8b732 AK |
570 | #define MAX_INST_SIZE 15 |
571 | ||
6aa8b732 AK |
572 | static inline void clgi(void) |
573 | { | |
4ecac3fd | 574 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
575 | } |
576 | ||
577 | static inline void stgi(void) | |
578 | { | |
4ecac3fd | 579 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
580 | } |
581 | ||
582 | static inline void invlpga(unsigned long addr, u32 asid) | |
583 | { | |
e0231715 | 584 | asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); |
6aa8b732 AK |
585 | } |
586 | ||
855feb67 | 587 | static int get_npt_level(struct kvm_vcpu *vcpu) |
4b16184c JR |
588 | { |
589 | #ifdef CONFIG_X86_64 | |
2a7266a8 | 590 | return PT64_ROOT_4LEVEL; |
4b16184c JR |
591 | #else |
592 | return PT32E_ROOT_LEVEL; | |
593 | #endif | |
594 | } | |
595 | ||
6aa8b732 AK |
596 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
597 | { | |
6dc696d4 | 598 | vcpu->arch.efer = efer; |
709ddebf | 599 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 600 | efer &= ~EFER_LME; |
6aa8b732 | 601 | |
9962d032 | 602 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
dcca1a65 | 603 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
604 | } |
605 | ||
6aa8b732 AK |
606 | static int is_external_interrupt(u32 info) |
607 | { | |
608 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
609 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
610 | } | |
611 | ||
37ccdcbe | 612 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
613 | { |
614 | struct vcpu_svm *svm = to_svm(vcpu); | |
615 | u32 ret = 0; | |
616 | ||
617 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
37ccdcbe PB |
618 | ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
619 | return ret; | |
2809f5d2 GC |
620 | } |
621 | ||
622 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
623 | { | |
624 | struct vcpu_svm *svm = to_svm(vcpu); | |
625 | ||
626 | if (mask == 0) | |
627 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
628 | else | |
629 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
630 | ||
631 | } | |
632 | ||
6aa8b732 AK |
633 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
634 | { | |
a2fa3e9f GH |
635 | struct vcpu_svm *svm = to_svm(vcpu); |
636 | ||
f104765b | 637 | if (svm->vmcb->control.next_rip != 0) { |
d2922422 | 638 | WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS)); |
6bc31bdc | 639 | svm->next_rip = svm->vmcb->control.next_rip; |
f104765b | 640 | } |
6bc31bdc | 641 | |
a2fa3e9f | 642 | if (!svm->next_rip) { |
51d8b661 | 643 | if (emulate_instruction(vcpu, EMULTYPE_SKIP) != |
f629cf84 GN |
644 | EMULATE_DONE) |
645 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
646 | return; |
647 | } | |
5fdbf976 MT |
648 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
649 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
650 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 651 | |
5fdbf976 | 652 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 653 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
654 | } |
655 | ||
cfcd20e5 | 656 | static void svm_queue_exception(struct kvm_vcpu *vcpu) |
116a4752 JK |
657 | { |
658 | struct vcpu_svm *svm = to_svm(vcpu); | |
cfcd20e5 WL |
659 | unsigned nr = vcpu->arch.exception.nr; |
660 | bool has_error_code = vcpu->arch.exception.has_error_code; | |
664f8e26 | 661 | bool reinject = vcpu->arch.exception.injected; |
cfcd20e5 | 662 | u32 error_code = vcpu->arch.exception.error_code; |
116a4752 | 663 | |
e0231715 JR |
664 | /* |
665 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
666 | * handle the exception | |
667 | */ | |
ce7ddec4 JR |
668 | if (!reinject && |
669 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
670 | return; |
671 | ||
2a6b20b8 | 672 | if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) { |
66b7138f JK |
673 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); |
674 | ||
675 | /* | |
676 | * For guest debugging where we have to reinject #BP if some | |
677 | * INT3 is guest-owned: | |
678 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
679 | * raises a fault that is not intercepted. Still better than | |
680 | * failing in all cases. | |
681 | */ | |
682 | skip_emulated_instruction(&svm->vcpu); | |
683 | rip = kvm_rip_read(&svm->vcpu); | |
684 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
685 | svm->int3_injected = rip - old_rip; | |
686 | } | |
687 | ||
116a4752 JK |
688 | svm->vmcb->control.event_inj = nr |
689 | | SVM_EVTINJ_VALID | |
690 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
691 | | SVM_EVTINJ_TYPE_EXEPT; | |
692 | svm->vmcb->control.event_inj_err = error_code; | |
693 | } | |
694 | ||
67ec6607 JR |
695 | static void svm_init_erratum_383(void) |
696 | { | |
697 | u32 low, high; | |
698 | int err; | |
699 | u64 val; | |
700 | ||
e6ee94d5 | 701 | if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH)) |
67ec6607 JR |
702 | return; |
703 | ||
704 | /* Use _safe variants to not break nested virtualization */ | |
705 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
706 | if (err) | |
707 | return; | |
708 | ||
709 | val |= (1ULL << 47); | |
710 | ||
711 | low = lower_32_bits(val); | |
712 | high = upper_32_bits(val); | |
713 | ||
714 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
715 | ||
716 | erratum_383_found = true; | |
717 | } | |
718 | ||
2b036c6b BO |
719 | static void svm_init_osvw(struct kvm_vcpu *vcpu) |
720 | { | |
721 | /* | |
722 | * Guests should see errata 400 and 415 as fixed (assuming that | |
723 | * HLT and IO instructions are intercepted). | |
724 | */ | |
725 | vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3; | |
726 | vcpu->arch.osvw.status = osvw_status & ~(6ULL); | |
727 | ||
728 | /* | |
729 | * By increasing VCPU's osvw.length to 3 we are telling the guest that | |
730 | * all osvw.status bits inside that length, including bit 0 (which is | |
731 | * reserved for erratum 298), are valid. However, if host processor's | |
732 | * osvw_len is 0 then osvw_status[0] carries no information. We need to | |
733 | * be conservative here and therefore we tell the guest that erratum 298 | |
734 | * is present (because we really don't know). | |
735 | */ | |
736 | if (osvw_len == 0 && boot_cpu_data.x86 == 0x10) | |
737 | vcpu->arch.osvw.status |= 1; | |
738 | } | |
739 | ||
6aa8b732 AK |
740 | static int has_svm(void) |
741 | { | |
63d1142f | 742 | const char *msg; |
6aa8b732 | 743 | |
63d1142f | 744 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 745 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
746 | return 0; |
747 | } | |
748 | ||
6aa8b732 AK |
749 | return 1; |
750 | } | |
751 | ||
13a34e06 | 752 | static void svm_hardware_disable(void) |
6aa8b732 | 753 | { |
fbc0db76 JR |
754 | /* Make sure we clean up behind us */ |
755 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) | |
756 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
757 | ||
2c8dceeb | 758 | cpu_svm_disable(); |
1018faa6 JR |
759 | |
760 | amd_pmu_disable_virt(); | |
6aa8b732 AK |
761 | } |
762 | ||
13a34e06 | 763 | static int svm_hardware_enable(void) |
6aa8b732 AK |
764 | { |
765 | ||
0fe1e009 | 766 | struct svm_cpu_data *sd; |
6aa8b732 | 767 | uint64_t efer; |
6aa8b732 AK |
768 | struct desc_struct *gdt; |
769 | int me = raw_smp_processor_id(); | |
770 | ||
10474ae8 AG |
771 | rdmsrl(MSR_EFER, efer); |
772 | if (efer & EFER_SVME) | |
773 | return -EBUSY; | |
774 | ||
6aa8b732 | 775 | if (!has_svm()) { |
1f5b77f5 | 776 | pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me); |
10474ae8 | 777 | return -EINVAL; |
6aa8b732 | 778 | } |
0fe1e009 | 779 | sd = per_cpu(svm_data, me); |
0fe1e009 | 780 | if (!sd) { |
1f5b77f5 | 781 | pr_err("%s: svm_data is NULL on %d\n", __func__, me); |
10474ae8 | 782 | return -EINVAL; |
6aa8b732 AK |
783 | } |
784 | ||
0fe1e009 TH |
785 | sd->asid_generation = 1; |
786 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
787 | sd->next_asid = sd->max_asid + 1; | |
6aa8b732 | 788 | |
45fc8757 | 789 | gdt = get_current_gdt_rw(); |
0fe1e009 | 790 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 791 | |
9962d032 | 792 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 793 | |
d0316554 | 794 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 795 | |
fbc0db76 JR |
796 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
797 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
89cbc767 | 798 | __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT); |
fbc0db76 JR |
799 | } |
800 | ||
2b036c6b BO |
801 | |
802 | /* | |
803 | * Get OSVW bits. | |
804 | * | |
805 | * Note that it is possible to have a system with mixed processor | |
806 | * revisions and therefore different OSVW bits. If bits are not the same | |
807 | * on different processors then choose the worst case (i.e. if erratum | |
808 | * is present on one processor and not on another then assume that the | |
809 | * erratum is present everywhere). | |
810 | */ | |
811 | if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) { | |
812 | uint64_t len, status = 0; | |
813 | int err; | |
814 | ||
815 | len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err); | |
816 | if (!err) | |
817 | status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS, | |
818 | &err); | |
819 | ||
820 | if (err) | |
821 | osvw_status = osvw_len = 0; | |
822 | else { | |
823 | if (len < osvw_len) | |
824 | osvw_len = len; | |
825 | osvw_status |= status; | |
826 | osvw_status &= (1ULL << osvw_len) - 1; | |
827 | } | |
828 | } else | |
829 | osvw_status = osvw_len = 0; | |
830 | ||
67ec6607 JR |
831 | svm_init_erratum_383(); |
832 | ||
1018faa6 JR |
833 | amd_pmu_enable_virt(); |
834 | ||
10474ae8 | 835 | return 0; |
6aa8b732 AK |
836 | } |
837 | ||
0da1db75 JR |
838 | static void svm_cpu_uninit(int cpu) |
839 | { | |
0fe1e009 | 840 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 841 | |
0fe1e009 | 842 | if (!sd) |
0da1db75 JR |
843 | return; |
844 | ||
845 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
0fe1e009 TH |
846 | __free_page(sd->save_area); |
847 | kfree(sd); | |
0da1db75 JR |
848 | } |
849 | ||
6aa8b732 AK |
850 | static int svm_cpu_init(int cpu) |
851 | { | |
0fe1e009 | 852 | struct svm_cpu_data *sd; |
6aa8b732 AK |
853 | int r; |
854 | ||
0fe1e009 TH |
855 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
856 | if (!sd) | |
6aa8b732 | 857 | return -ENOMEM; |
0fe1e009 TH |
858 | sd->cpu = cpu; |
859 | sd->save_area = alloc_page(GFP_KERNEL); | |
6aa8b732 | 860 | r = -ENOMEM; |
0fe1e009 | 861 | if (!sd->save_area) |
6aa8b732 AK |
862 | goto err_1; |
863 | ||
0fe1e009 | 864 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
865 | |
866 | return 0; | |
867 | ||
868 | err_1: | |
0fe1e009 | 869 | kfree(sd); |
6aa8b732 AK |
870 | return r; |
871 | ||
872 | } | |
873 | ||
ac72a9b7 JR |
874 | static bool valid_msr_intercept(u32 index) |
875 | { | |
876 | int i; | |
877 | ||
878 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
879 | if (direct_access_msrs[i].index == index) | |
880 | return true; | |
881 | ||
882 | return false; | |
883 | } | |
884 | ||
bfc733a7 RR |
885 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
886 | int read, int write) | |
6aa8b732 | 887 | { |
455716fa JR |
888 | u8 bit_read, bit_write; |
889 | unsigned long tmp; | |
890 | u32 offset; | |
6aa8b732 | 891 | |
ac72a9b7 JR |
892 | /* |
893 | * If this warning triggers extend the direct_access_msrs list at the | |
894 | * beginning of the file | |
895 | */ | |
896 | WARN_ON(!valid_msr_intercept(msr)); | |
897 | ||
455716fa JR |
898 | offset = svm_msrpm_offset(msr); |
899 | bit_read = 2 * (msr & 0x0f); | |
900 | bit_write = 2 * (msr & 0x0f) + 1; | |
901 | tmp = msrpm[offset]; | |
902 | ||
903 | BUG_ON(offset == MSR_INVALID); | |
904 | ||
905 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
906 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
907 | ||
908 | msrpm[offset] = tmp; | |
6aa8b732 AK |
909 | } |
910 | ||
f65c229c | 911 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
912 | { |
913 | int i; | |
914 | ||
f65c229c JR |
915 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
916 | ||
ac72a9b7 JR |
917 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
918 | if (!direct_access_msrs[i].always) | |
919 | continue; | |
920 | ||
921 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
922 | } | |
f65c229c JR |
923 | } |
924 | ||
323c3d80 JR |
925 | static void add_msr_offset(u32 offset) |
926 | { | |
927 | int i; | |
928 | ||
929 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
930 | ||
931 | /* Offset already in list? */ | |
932 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 933 | return; |
323c3d80 JR |
934 | |
935 | /* Slot used by another offset? */ | |
936 | if (msrpm_offsets[i] != MSR_INVALID) | |
937 | continue; | |
938 | ||
939 | /* Add offset to list */ | |
940 | msrpm_offsets[i] = offset; | |
941 | ||
942 | return; | |
6aa8b732 | 943 | } |
323c3d80 JR |
944 | |
945 | /* | |
946 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
947 | * increase MSRPM_OFFSETS in this case. | |
948 | */ | |
bfc733a7 | 949 | BUG(); |
6aa8b732 AK |
950 | } |
951 | ||
323c3d80 | 952 | static void init_msrpm_offsets(void) |
f65c229c | 953 | { |
323c3d80 | 954 | int i; |
f65c229c | 955 | |
323c3d80 JR |
956 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
957 | ||
958 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
959 | u32 offset; | |
960 | ||
961 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
962 | BUG_ON(offset == MSR_INVALID); | |
963 | ||
964 | add_msr_offset(offset); | |
965 | } | |
f65c229c JR |
966 | } |
967 | ||
24e09cbf JR |
968 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
969 | { | |
970 | u32 *msrpm = svm->msrpm; | |
971 | ||
0dc92119 | 972 | svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK; |
24e09cbf JR |
973 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); |
974 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
975 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
976 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
977 | } | |
978 | ||
979 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
980 | { | |
981 | u32 *msrpm = svm->msrpm; | |
982 | ||
0dc92119 | 983 | svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK; |
24e09cbf JR |
984 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); |
985 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
986 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
987 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
988 | } | |
989 | ||
4aebd0e9 LP |
990 | static void disable_nmi_singlestep(struct vcpu_svm *svm) |
991 | { | |
992 | svm->nmi_singlestep = false; | |
640bd6e5 | 993 | |
ab2f4d73 LP |
994 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) { |
995 | /* Clear our flags if they were not set by the guest */ | |
996 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF)) | |
997 | svm->vmcb->save.rflags &= ~X86_EFLAGS_TF; | |
998 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF)) | |
999 | svm->vmcb->save.rflags &= ~X86_EFLAGS_RF; | |
1000 | } | |
4aebd0e9 LP |
1001 | } |
1002 | ||
5881f737 SS |
1003 | /* Note: |
1004 | * This hash table is used to map VM_ID to a struct kvm_arch, | |
1005 | * when handling AMD IOMMU GALOG notification to schedule in | |
1006 | * a particular vCPU. | |
1007 | */ | |
1008 | #define SVM_VM_DATA_HASH_BITS 8 | |
681bcea8 | 1009 | static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS); |
3f0d4db7 DV |
1010 | static u32 next_vm_id = 0; |
1011 | static bool next_vm_id_wrapped = 0; | |
681bcea8 | 1012 | static DEFINE_SPINLOCK(svm_vm_data_hash_lock); |
5881f737 SS |
1013 | |
1014 | /* Note: | |
1015 | * This function is called from IOMMU driver to notify | |
1016 | * SVM to schedule in a particular vCPU of a particular VM. | |
1017 | */ | |
1018 | static int avic_ga_log_notifier(u32 ga_tag) | |
1019 | { | |
1020 | unsigned long flags; | |
1021 | struct kvm_arch *ka = NULL; | |
1022 | struct kvm_vcpu *vcpu = NULL; | |
1023 | u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag); | |
1024 | u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag); | |
1025 | ||
1026 | pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id); | |
1027 | ||
1028 | spin_lock_irqsave(&svm_vm_data_hash_lock, flags); | |
1029 | hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) { | |
1030 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
1031 | struct kvm_arch *vm_data = &kvm->arch; | |
1032 | ||
1033 | if (vm_data->avic_vm_id != vm_id) | |
1034 | continue; | |
1035 | vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id); | |
1036 | break; | |
1037 | } | |
1038 | spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); | |
1039 | ||
5881f737 SS |
1040 | /* Note: |
1041 | * At this point, the IOMMU should have already set the pending | |
1042 | * bit in the vAPIC backing page. So, we just need to schedule | |
1043 | * in the vcpu. | |
1044 | */ | |
1cf53587 | 1045 | if (vcpu) |
5881f737 SS |
1046 | kvm_vcpu_wake_up(vcpu); |
1047 | ||
1048 | return 0; | |
1049 | } | |
1050 | ||
6aa8b732 AK |
1051 | static __init int svm_hardware_setup(void) |
1052 | { | |
1053 | int cpu; | |
1054 | struct page *iopm_pages; | |
f65c229c | 1055 | void *iopm_va; |
6aa8b732 AK |
1056 | int r; |
1057 | ||
6aa8b732 AK |
1058 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
1059 | ||
1060 | if (!iopm_pages) | |
1061 | return -ENOMEM; | |
c8681339 AL |
1062 | |
1063 | iopm_va = page_address(iopm_pages); | |
1064 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
1065 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
1066 | ||
323c3d80 JR |
1067 | init_msrpm_offsets(); |
1068 | ||
50a37eb4 JR |
1069 | if (boot_cpu_has(X86_FEATURE_NX)) |
1070 | kvm_enable_efer_bits(EFER_NX); | |
1071 | ||
1b2fd70c AG |
1072 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
1073 | kvm_enable_efer_bits(EFER_FFXSR); | |
1074 | ||
92a1f12d | 1075 | if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
92a1f12d | 1076 | kvm_has_tsc_control = true; |
bc9b961b HZ |
1077 | kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX; |
1078 | kvm_tsc_scaling_ratio_frac_bits = 32; | |
92a1f12d JR |
1079 | } |
1080 | ||
236de055 AG |
1081 | if (nested) { |
1082 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 1083 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
1084 | } |
1085 | ||
3230bb47 | 1086 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
1087 | r = svm_cpu_init(cpu); |
1088 | if (r) | |
f65c229c | 1089 | goto err; |
6aa8b732 | 1090 | } |
33bd6a0b | 1091 | |
2a6b20b8 | 1092 | if (!boot_cpu_has(X86_FEATURE_NPT)) |
e3da3acd JR |
1093 | npt_enabled = false; |
1094 | ||
6c7dac72 JR |
1095 | if (npt_enabled && !npt) { |
1096 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
1097 | npt_enabled = false; | |
1098 | } | |
1099 | ||
18552672 | 1100 | if (npt_enabled) { |
e3da3acd | 1101 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 1102 | kvm_enable_tdp(); |
5f4cb662 JR |
1103 | } else |
1104 | kvm_disable_tdp(); | |
e3da3acd | 1105 | |
5b8abf1f SS |
1106 | if (avic) { |
1107 | if (!npt_enabled || | |
1108 | !boot_cpu_has(X86_FEATURE_AVIC) || | |
5881f737 | 1109 | !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) { |
5b8abf1f | 1110 | avic = false; |
5881f737 | 1111 | } else { |
5b8abf1f | 1112 | pr_info("AVIC enabled\n"); |
5881f737 | 1113 | |
5881f737 SS |
1114 | amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier); |
1115 | } | |
5b8abf1f | 1116 | } |
44a95dae | 1117 | |
89c8a498 JN |
1118 | if (vls) { |
1119 | if (!npt_enabled || | |
5442c269 | 1120 | !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) || |
89c8a498 JN |
1121 | !IS_ENABLED(CONFIG_X86_64)) { |
1122 | vls = false; | |
1123 | } else { | |
1124 | pr_info("Virtual VMLOAD VMSAVE supported\n"); | |
1125 | } | |
1126 | } | |
1127 | ||
640bd6e5 JN |
1128 | if (vgif) { |
1129 | if (!boot_cpu_has(X86_FEATURE_VGIF)) | |
1130 | vgif = false; | |
1131 | else | |
1132 | pr_info("Virtual GIF supported\n"); | |
1133 | } | |
1134 | ||
6aa8b732 AK |
1135 | return 0; |
1136 | ||
f65c229c | 1137 | err: |
6aa8b732 AK |
1138 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
1139 | iopm_base = 0; | |
1140 | return r; | |
1141 | } | |
1142 | ||
1143 | static __exit void svm_hardware_unsetup(void) | |
1144 | { | |
0da1db75 JR |
1145 | int cpu; |
1146 | ||
3230bb47 | 1147 | for_each_possible_cpu(cpu) |
0da1db75 JR |
1148 | svm_cpu_uninit(cpu); |
1149 | ||
6aa8b732 | 1150 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 1151 | iopm_base = 0; |
6aa8b732 AK |
1152 | } |
1153 | ||
1154 | static void init_seg(struct vmcb_seg *seg) | |
1155 | { | |
1156 | seg->selector = 0; | |
1157 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 1158 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
1159 | seg->limit = 0xffff; |
1160 | seg->base = 0; | |
1161 | } | |
1162 | ||
1163 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
1164 | { | |
1165 | seg->selector = 0; | |
1166 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
1167 | seg->limit = 0xffff; | |
1168 | seg->base = 0; | |
1169 | } | |
1170 | ||
f4e1b3c8 ZA |
1171 | static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
1172 | { | |
1173 | struct vcpu_svm *svm = to_svm(vcpu); | |
1174 | u64 g_tsc_offset = 0; | |
1175 | ||
2030753d | 1176 | if (is_guest_mode(vcpu)) { |
f4e1b3c8 ZA |
1177 | g_tsc_offset = svm->vmcb->control.tsc_offset - |
1178 | svm->nested.hsave->control.tsc_offset; | |
1179 | svm->nested.hsave->control.tsc_offset = offset; | |
489223ed YY |
1180 | } else |
1181 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, | |
1182 | svm->vmcb->control.tsc_offset, | |
1183 | offset); | |
f4e1b3c8 ZA |
1184 | |
1185 | svm->vmcb->control.tsc_offset = offset + g_tsc_offset; | |
116a0a23 JR |
1186 | |
1187 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); | |
f4e1b3c8 ZA |
1188 | } |
1189 | ||
44a95dae SS |
1190 | static void avic_init_vmcb(struct vcpu_svm *svm) |
1191 | { | |
1192 | struct vmcb *vmcb = svm->vmcb; | |
1193 | struct kvm_arch *vm_data = &svm->vcpu.kvm->arch; | |
d0ec49d4 TL |
1194 | phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page)); |
1195 | phys_addr_t lpa = __sme_set(page_to_phys(vm_data->avic_logical_id_table_page)); | |
1196 | phys_addr_t ppa = __sme_set(page_to_phys(vm_data->avic_physical_id_table_page)); | |
44a95dae SS |
1197 | |
1198 | vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK; | |
1199 | vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK; | |
1200 | vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK; | |
1201 | vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT; | |
1202 | vmcb->control.int_ctl |= AVIC_ENABLE_MASK; | |
44a95dae SS |
1203 | } |
1204 | ||
5690891b | 1205 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 1206 | { |
e6101a96 JR |
1207 | struct vmcb_control_area *control = &svm->vmcb->control; |
1208 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 1209 | |
4ee546b4 | 1210 | svm->vcpu.arch.hflags = 0; |
bff78274 | 1211 | |
4ee546b4 RJ |
1212 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1213 | set_cr_intercept(svm, INTERCEPT_CR3_READ); | |
1214 | set_cr_intercept(svm, INTERCEPT_CR4_READ); | |
1215 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
1216 | set_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
1217 | set_cr_intercept(svm, INTERCEPT_CR4_WRITE); | |
3bbf3565 SS |
1218 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) |
1219 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
6aa8b732 | 1220 | |
5315c716 | 1221 | set_dr_intercepts(svm); |
6aa8b732 | 1222 | |
18c918c5 JR |
1223 | set_exception_intercept(svm, PF_VECTOR); |
1224 | set_exception_intercept(svm, UD_VECTOR); | |
1225 | set_exception_intercept(svm, MC_VECTOR); | |
54a20552 | 1226 | set_exception_intercept(svm, AC_VECTOR); |
cbdb967a | 1227 | set_exception_intercept(svm, DB_VECTOR); |
6aa8b732 | 1228 | |
8a05a1b8 JR |
1229 | set_intercept(svm, INTERCEPT_INTR); |
1230 | set_intercept(svm, INTERCEPT_NMI); | |
1231 | set_intercept(svm, INTERCEPT_SMI); | |
1232 | set_intercept(svm, INTERCEPT_SELECTIVE_CR0); | |
332b56e4 | 1233 | set_intercept(svm, INTERCEPT_RDPMC); |
8a05a1b8 JR |
1234 | set_intercept(svm, INTERCEPT_CPUID); |
1235 | set_intercept(svm, INTERCEPT_INVD); | |
1236 | set_intercept(svm, INTERCEPT_HLT); | |
1237 | set_intercept(svm, INTERCEPT_INVLPG); | |
1238 | set_intercept(svm, INTERCEPT_INVLPGA); | |
1239 | set_intercept(svm, INTERCEPT_IOIO_PROT); | |
1240 | set_intercept(svm, INTERCEPT_MSR_PROT); | |
1241 | set_intercept(svm, INTERCEPT_TASK_SWITCH); | |
1242 | set_intercept(svm, INTERCEPT_SHUTDOWN); | |
1243 | set_intercept(svm, INTERCEPT_VMRUN); | |
1244 | set_intercept(svm, INTERCEPT_VMMCALL); | |
1245 | set_intercept(svm, INTERCEPT_VMLOAD); | |
1246 | set_intercept(svm, INTERCEPT_VMSAVE); | |
1247 | set_intercept(svm, INTERCEPT_STGI); | |
1248 | set_intercept(svm, INTERCEPT_CLGI); | |
1249 | set_intercept(svm, INTERCEPT_SKINIT); | |
1250 | set_intercept(svm, INTERCEPT_WBINVD); | |
81dd35d4 | 1251 | set_intercept(svm, INTERCEPT_XSETBV); |
6aa8b732 | 1252 | |
668fffa3 MT |
1253 | if (!kvm_mwait_in_guest()) { |
1254 | set_intercept(svm, INTERCEPT_MONITOR); | |
1255 | set_intercept(svm, INTERCEPT_MWAIT); | |
1256 | } | |
1257 | ||
d0ec49d4 TL |
1258 | control->iopm_base_pa = __sme_set(iopm_base); |
1259 | control->msrpm_base_pa = __sme_set(__pa(svm->msrpm)); | |
6aa8b732 AK |
1260 | control->int_ctl = V_INTR_MASKING_MASK; |
1261 | ||
1262 | init_seg(&save->es); | |
1263 | init_seg(&save->ss); | |
1264 | init_seg(&save->ds); | |
1265 | init_seg(&save->fs); | |
1266 | init_seg(&save->gs); | |
1267 | ||
1268 | save->cs.selector = 0xf000; | |
04b66839 | 1269 | save->cs.base = 0xffff0000; |
6aa8b732 AK |
1270 | /* Executable/Readable Code Segment */ |
1271 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
1272 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
1273 | save->cs.limit = 0xffff; | |
6aa8b732 AK |
1274 | |
1275 | save->gdtr.limit = 0xffff; | |
1276 | save->idtr.limit = 0xffff; | |
1277 | ||
1278 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
1279 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
1280 | ||
5690891b | 1281 | svm_set_efer(&svm->vcpu, 0); |
d77c26fc | 1282 | save->dr6 = 0xffff0ff0; |
f6e78475 | 1283 | kvm_set_rflags(&svm->vcpu, 2); |
6aa8b732 | 1284 | save->rip = 0x0000fff0; |
5fdbf976 | 1285 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 1286 | |
e0231715 | 1287 | /* |
18fa000a | 1288 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
d28bc9dd | 1289 | * It also updates the guest-visible cr0 value. |
6aa8b732 | 1290 | */ |
79a8059d | 1291 | svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); |
ebae871a | 1292 | kvm_mmu_reset_context(&svm->vcpu); |
18fa000a | 1293 | |
66aee91a | 1294 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 1295 | /* rdx = ?? */ |
709ddebf JR |
1296 | |
1297 | if (npt_enabled) { | |
1298 | /* Setup VMCB for Nested Paging */ | |
1299 | control->nested_ctl = 1; | |
8a05a1b8 | 1300 | clr_intercept(svm, INTERCEPT_INVLPG); |
18c918c5 | 1301 | clr_exception_intercept(svm, PF_VECTOR); |
4ee546b4 RJ |
1302 | clr_cr_intercept(svm, INTERCEPT_CR3_READ); |
1303 | clr_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
74545705 | 1304 | save->g_pat = svm->vcpu.arch.pat; |
709ddebf JR |
1305 | save->cr3 = 0; |
1306 | save->cr4 = 0; | |
1307 | } | |
f40f6a45 | 1308 | svm->asid_generation = 0; |
1371d904 | 1309 | |
e6aa9abd | 1310 | svm->nested.vmcb = 0; |
2af9194d JR |
1311 | svm->vcpu.arch.hflags = 0; |
1312 | ||
2a6b20b8 | 1313 | if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { |
565d0998 | 1314 | control->pause_filter_count = 3000; |
8a05a1b8 | 1315 | set_intercept(svm, INTERCEPT_PAUSE); |
565d0998 ML |
1316 | } |
1317 | ||
67034bb9 | 1318 | if (kvm_vcpu_apicv_active(&svm->vcpu)) |
44a95dae SS |
1319 | avic_init_vmcb(svm); |
1320 | ||
89c8a498 JN |
1321 | /* |
1322 | * If hardware supports Virtual VMLOAD VMSAVE then enable it | |
1323 | * in VMCB and clear intercepts to avoid #VMEXIT. | |
1324 | */ | |
1325 | if (vls) { | |
1326 | clr_intercept(svm, INTERCEPT_VMLOAD); | |
1327 | clr_intercept(svm, INTERCEPT_VMSAVE); | |
1328 | svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK; | |
1329 | } | |
1330 | ||
640bd6e5 JN |
1331 | if (vgif) { |
1332 | clr_intercept(svm, INTERCEPT_STGI); | |
1333 | clr_intercept(svm, INTERCEPT_CLGI); | |
1334 | svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK; | |
1335 | } | |
1336 | ||
8d28fec4 RJ |
1337 | mark_all_dirty(svm->vmcb); |
1338 | ||
2af9194d | 1339 | enable_gif(svm); |
44a95dae SS |
1340 | |
1341 | } | |
1342 | ||
d3e7dec0 DC |
1343 | static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, |
1344 | unsigned int index) | |
44a95dae SS |
1345 | { |
1346 | u64 *avic_physical_id_table; | |
1347 | struct kvm_arch *vm_data = &vcpu->kvm->arch; | |
1348 | ||
1349 | if (index >= AVIC_MAX_PHYSICAL_ID_COUNT) | |
1350 | return NULL; | |
1351 | ||
1352 | avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page); | |
1353 | ||
1354 | return &avic_physical_id_table[index]; | |
1355 | } | |
1356 | ||
1357 | /** | |
1358 | * Note: | |
1359 | * AVIC hardware walks the nested page table to check permissions, | |
1360 | * but does not use the SPA address specified in the leaf page | |
1361 | * table entry since it uses address in the AVIC_BACKING_PAGE pointer | |
1362 | * field of the VMCB. Therefore, we set up the | |
1363 | * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here. | |
1364 | */ | |
1365 | static int avic_init_access_page(struct kvm_vcpu *vcpu) | |
1366 | { | |
1367 | struct kvm *kvm = vcpu->kvm; | |
1368 | int ret; | |
1369 | ||
1370 | if (kvm->arch.apic_access_page_done) | |
1371 | return 0; | |
1372 | ||
1373 | ret = x86_set_memory_region(kvm, | |
1374 | APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
1375 | APIC_DEFAULT_PHYS_BASE, | |
1376 | PAGE_SIZE); | |
1377 | if (ret) | |
1378 | return ret; | |
1379 | ||
1380 | kvm->arch.apic_access_page_done = true; | |
1381 | return 0; | |
1382 | } | |
1383 | ||
1384 | static int avic_init_backing_page(struct kvm_vcpu *vcpu) | |
1385 | { | |
1386 | int ret; | |
1387 | u64 *entry, new_entry; | |
1388 | int id = vcpu->vcpu_id; | |
1389 | struct vcpu_svm *svm = to_svm(vcpu); | |
1390 | ||
1391 | ret = avic_init_access_page(vcpu); | |
1392 | if (ret) | |
1393 | return ret; | |
1394 | ||
1395 | if (id >= AVIC_MAX_PHYSICAL_ID_COUNT) | |
1396 | return -EINVAL; | |
1397 | ||
1398 | if (!svm->vcpu.arch.apic->regs) | |
1399 | return -EINVAL; | |
1400 | ||
1401 | svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs); | |
1402 | ||
1403 | /* Setting AVIC backing page address in the phy APIC ID table */ | |
1404 | entry = avic_get_physical_id_entry(vcpu, id); | |
1405 | if (!entry) | |
1406 | return -EINVAL; | |
1407 | ||
1408 | new_entry = READ_ONCE(*entry); | |
d0ec49d4 TL |
1409 | new_entry = __sme_set((page_to_phys(svm->avic_backing_page) & |
1410 | AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) | | |
1411 | AVIC_PHYSICAL_ID_ENTRY_VALID_MASK); | |
44a95dae SS |
1412 | WRITE_ONCE(*entry, new_entry); |
1413 | ||
1414 | svm->avic_physical_id_cache = entry; | |
1415 | ||
1416 | return 0; | |
1417 | } | |
1418 | ||
1419 | static void avic_vm_destroy(struct kvm *kvm) | |
1420 | { | |
5881f737 | 1421 | unsigned long flags; |
44a95dae SS |
1422 | struct kvm_arch *vm_data = &kvm->arch; |
1423 | ||
3863dff0 DV |
1424 | if (!avic) |
1425 | return; | |
1426 | ||
44a95dae SS |
1427 | if (vm_data->avic_logical_id_table_page) |
1428 | __free_page(vm_data->avic_logical_id_table_page); | |
1429 | if (vm_data->avic_physical_id_table_page) | |
1430 | __free_page(vm_data->avic_physical_id_table_page); | |
5881f737 SS |
1431 | |
1432 | spin_lock_irqsave(&svm_vm_data_hash_lock, flags); | |
1433 | hash_del(&vm_data->hnode); | |
1434 | spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); | |
44a95dae SS |
1435 | } |
1436 | ||
1437 | static int avic_vm_init(struct kvm *kvm) | |
1438 | { | |
5881f737 | 1439 | unsigned long flags; |
3f0d4db7 | 1440 | int err = -ENOMEM; |
44a95dae SS |
1441 | struct kvm_arch *vm_data = &kvm->arch; |
1442 | struct page *p_page; | |
1443 | struct page *l_page; | |
3f0d4db7 DV |
1444 | struct kvm_arch *ka; |
1445 | u32 vm_id; | |
44a95dae SS |
1446 | |
1447 | if (!avic) | |
1448 | return 0; | |
1449 | ||
1450 | /* Allocating physical APIC ID table (4KB) */ | |
1451 | p_page = alloc_page(GFP_KERNEL); | |
1452 | if (!p_page) | |
1453 | goto free_avic; | |
1454 | ||
1455 | vm_data->avic_physical_id_table_page = p_page; | |
1456 | clear_page(page_address(p_page)); | |
1457 | ||
1458 | /* Allocating logical APIC ID table (4KB) */ | |
1459 | l_page = alloc_page(GFP_KERNEL); | |
1460 | if (!l_page) | |
1461 | goto free_avic; | |
1462 | ||
1463 | vm_data->avic_logical_id_table_page = l_page; | |
1464 | clear_page(page_address(l_page)); | |
1465 | ||
5881f737 | 1466 | spin_lock_irqsave(&svm_vm_data_hash_lock, flags); |
3f0d4db7 DV |
1467 | again: |
1468 | vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK; | |
1469 | if (vm_id == 0) { /* id is 1-based, zero is not okay */ | |
1470 | next_vm_id_wrapped = 1; | |
1471 | goto again; | |
1472 | } | |
1473 | /* Is it still in use? Only possible if wrapped at least once */ | |
1474 | if (next_vm_id_wrapped) { | |
1475 | hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) { | |
1476 | struct kvm *k2 = container_of(ka, struct kvm, arch); | |
1477 | struct kvm_arch *vd2 = &k2->arch; | |
1478 | if (vd2->avic_vm_id == vm_id) | |
1479 | goto again; | |
1480 | } | |
1481 | } | |
1482 | vm_data->avic_vm_id = vm_id; | |
5881f737 SS |
1483 | hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id); |
1484 | spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); | |
1485 | ||
44a95dae SS |
1486 | return 0; |
1487 | ||
1488 | free_avic: | |
1489 | avic_vm_destroy(kvm); | |
1490 | return err; | |
6aa8b732 AK |
1491 | } |
1492 | ||
411b44ba SS |
1493 | static inline int |
1494 | avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r) | |
8221c137 | 1495 | { |
411b44ba SS |
1496 | int ret = 0; |
1497 | unsigned long flags; | |
1498 | struct amd_svm_iommu_ir *ir; | |
8221c137 SS |
1499 | struct vcpu_svm *svm = to_svm(vcpu); |
1500 | ||
411b44ba SS |
1501 | if (!kvm_arch_has_assigned_device(vcpu->kvm)) |
1502 | return 0; | |
8221c137 | 1503 | |
411b44ba SS |
1504 | /* |
1505 | * Here, we go through the per-vcpu ir_list to update all existing | |
1506 | * interrupt remapping table entry targeting this vcpu. | |
1507 | */ | |
1508 | spin_lock_irqsave(&svm->ir_list_lock, flags); | |
8221c137 | 1509 | |
411b44ba SS |
1510 | if (list_empty(&svm->ir_list)) |
1511 | goto out; | |
8221c137 | 1512 | |
411b44ba SS |
1513 | list_for_each_entry(ir, &svm->ir_list, node) { |
1514 | ret = amd_iommu_update_ga(cpu, r, ir->data); | |
1515 | if (ret) | |
1516 | break; | |
1517 | } | |
1518 | out: | |
1519 | spin_unlock_irqrestore(&svm->ir_list_lock, flags); | |
1520 | return ret; | |
8221c137 SS |
1521 | } |
1522 | ||
1523 | static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) | |
1524 | { | |
1525 | u64 entry; | |
1526 | /* ID = 0xff (broadcast), ID > 0xff (reserved) */ | |
7d669f50 | 1527 | int h_physical_id = kvm_cpu_get_apicid(cpu); |
8221c137 SS |
1528 | struct vcpu_svm *svm = to_svm(vcpu); |
1529 | ||
1530 | if (!kvm_vcpu_apicv_active(vcpu)) | |
1531 | return; | |
1532 | ||
1533 | if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT)) | |
1534 | return; | |
1535 | ||
1536 | entry = READ_ONCE(*(svm->avic_physical_id_cache)); | |
1537 | WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); | |
1538 | ||
1539 | entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK; | |
1540 | entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK); | |
1541 | ||
1542 | entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; | |
1543 | if (svm->avic_is_running) | |
1544 | entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; | |
1545 | ||
1546 | WRITE_ONCE(*(svm->avic_physical_id_cache), entry); | |
411b44ba SS |
1547 | avic_update_iommu_vcpu_affinity(vcpu, h_physical_id, |
1548 | svm->avic_is_running); | |
8221c137 SS |
1549 | } |
1550 | ||
1551 | static void avic_vcpu_put(struct kvm_vcpu *vcpu) | |
1552 | { | |
1553 | u64 entry; | |
1554 | struct vcpu_svm *svm = to_svm(vcpu); | |
1555 | ||
1556 | if (!kvm_vcpu_apicv_active(vcpu)) | |
1557 | return; | |
1558 | ||
1559 | entry = READ_ONCE(*(svm->avic_physical_id_cache)); | |
411b44ba SS |
1560 | if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) |
1561 | avic_update_iommu_vcpu_affinity(vcpu, -1, 0); | |
1562 | ||
8221c137 SS |
1563 | entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; |
1564 | WRITE_ONCE(*(svm->avic_physical_id_cache), entry); | |
6aa8b732 AK |
1565 | } |
1566 | ||
411b44ba SS |
1567 | /** |
1568 | * This function is called during VCPU halt/unhalt. | |
1569 | */ | |
1570 | static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run) | |
1571 | { | |
1572 | struct vcpu_svm *svm = to_svm(vcpu); | |
1573 | ||
1574 | svm->avic_is_running = is_run; | |
1575 | if (is_run) | |
1576 | avic_vcpu_load(vcpu, vcpu->cpu); | |
1577 | else | |
1578 | avic_vcpu_put(vcpu); | |
1579 | } | |
1580 | ||
d28bc9dd | 1581 | static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
04d2cc77 AK |
1582 | { |
1583 | struct vcpu_svm *svm = to_svm(vcpu); | |
66f7b72e JS |
1584 | u32 dummy; |
1585 | u32 eax = 1; | |
04d2cc77 | 1586 | |
d28bc9dd NA |
1587 | if (!init_event) { |
1588 | svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE | | |
1589 | MSR_IA32_APICBASE_ENABLE; | |
1590 | if (kvm_vcpu_is_reset_bsp(&svm->vcpu)) | |
1591 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; | |
1592 | } | |
5690891b | 1593 | init_vmcb(svm); |
70433389 | 1594 | |
e911eb3b | 1595 | kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true); |
66f7b72e | 1596 | kvm_register_write(vcpu, VCPU_REGS_RDX, eax); |
44a95dae SS |
1597 | |
1598 | if (kvm_vcpu_apicv_active(vcpu) && !init_event) | |
1599 | avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE); | |
04d2cc77 AK |
1600 | } |
1601 | ||
dfa20099 SS |
1602 | static int avic_init_vcpu(struct vcpu_svm *svm) |
1603 | { | |
1604 | int ret; | |
1605 | ||
67034bb9 | 1606 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) |
dfa20099 SS |
1607 | return 0; |
1608 | ||
1609 | ret = avic_init_backing_page(&svm->vcpu); | |
1610 | if (ret) | |
1611 | return ret; | |
1612 | ||
1613 | INIT_LIST_HEAD(&svm->ir_list); | |
1614 | spin_lock_init(&svm->ir_list_lock); | |
1615 | ||
1616 | return ret; | |
1617 | } | |
1618 | ||
fb3f0f51 | 1619 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 1620 | { |
a2fa3e9f | 1621 | struct vcpu_svm *svm; |
6aa8b732 | 1622 | struct page *page; |
f65c229c | 1623 | struct page *msrpm_pages; |
b286d5d8 | 1624 | struct page *hsave_page; |
3d6368ef | 1625 | struct page *nested_msrpm_pages; |
fb3f0f51 | 1626 | int err; |
6aa8b732 | 1627 | |
c16f862d | 1628 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
1629 | if (!svm) { |
1630 | err = -ENOMEM; | |
1631 | goto out; | |
1632 | } | |
1633 | ||
1634 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
1635 | if (err) | |
1636 | goto free_svm; | |
1637 | ||
b7af4043 | 1638 | err = -ENOMEM; |
6aa8b732 | 1639 | page = alloc_page(GFP_KERNEL); |
b7af4043 | 1640 | if (!page) |
fb3f0f51 | 1641 | goto uninit; |
6aa8b732 | 1642 | |
f65c229c JR |
1643 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); |
1644 | if (!msrpm_pages) | |
b7af4043 | 1645 | goto free_page1; |
3d6368ef AG |
1646 | |
1647 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
1648 | if (!nested_msrpm_pages) | |
b7af4043 | 1649 | goto free_page2; |
f65c229c | 1650 | |
b286d5d8 AG |
1651 | hsave_page = alloc_page(GFP_KERNEL); |
1652 | if (!hsave_page) | |
b7af4043 TY |
1653 | goto free_page3; |
1654 | ||
dfa20099 SS |
1655 | err = avic_init_vcpu(svm); |
1656 | if (err) | |
1657 | goto free_page4; | |
44a95dae | 1658 | |
8221c137 SS |
1659 | /* We initialize this flag to true to make sure that the is_running |
1660 | * bit would be set the first time the vcpu is loaded. | |
1661 | */ | |
1662 | svm->avic_is_running = true; | |
1663 | ||
e6aa9abd | 1664 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 1665 | |
b7af4043 TY |
1666 | svm->msrpm = page_address(msrpm_pages); |
1667 | svm_vcpu_init_msrpm(svm->msrpm); | |
1668 | ||
e6aa9abd | 1669 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 1670 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 1671 | |
a2fa3e9f GH |
1672 | svm->vmcb = page_address(page); |
1673 | clear_page(svm->vmcb); | |
d0ec49d4 | 1674 | svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT); |
a2fa3e9f | 1675 | svm->asid_generation = 0; |
5690891b | 1676 | init_vmcb(svm); |
6aa8b732 | 1677 | |
2b036c6b BO |
1678 | svm_init_osvw(&svm->vcpu); |
1679 | ||
fb3f0f51 | 1680 | return &svm->vcpu; |
36241b8c | 1681 | |
44a95dae SS |
1682 | free_page4: |
1683 | __free_page(hsave_page); | |
b7af4043 TY |
1684 | free_page3: |
1685 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
1686 | free_page2: | |
1687 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
1688 | free_page1: | |
1689 | __free_page(page); | |
fb3f0f51 RR |
1690 | uninit: |
1691 | kvm_vcpu_uninit(&svm->vcpu); | |
1692 | free_svm: | |
a4770347 | 1693 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
1694 | out: |
1695 | return ERR_PTR(err); | |
6aa8b732 AK |
1696 | } |
1697 | ||
1698 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
1699 | { | |
a2fa3e9f GH |
1700 | struct vcpu_svm *svm = to_svm(vcpu); |
1701 | ||
d0ec49d4 | 1702 | __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT)); |
f65c229c | 1703 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
1704 | __free_page(virt_to_page(svm->nested.hsave)); |
1705 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 1706 | kvm_vcpu_uninit(vcpu); |
a4770347 | 1707 | kmem_cache_free(kvm_vcpu_cache, svm); |
15d45071 AR |
1708 | /* |
1709 | * The vmcb page can be recycled, causing a false negative in | |
1710 | * svm_vcpu_load(). So do a full IBPB now. | |
1711 | */ | |
1712 | indirect_branch_prediction_barrier(); | |
6aa8b732 AK |
1713 | } |
1714 | ||
15ad7146 | 1715 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 1716 | { |
a2fa3e9f | 1717 | struct vcpu_svm *svm = to_svm(vcpu); |
15d45071 | 1718 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
15ad7146 | 1719 | int i; |
0cc5064d | 1720 | |
0cc5064d | 1721 | if (unlikely(cpu != vcpu->cpu)) { |
4b656b12 | 1722 | svm->asid_generation = 0; |
8d28fec4 | 1723 | mark_all_dirty(svm->vmcb); |
0cc5064d | 1724 | } |
94dfbdb3 | 1725 | |
82ca2d10 AK |
1726 | #ifdef CONFIG_X86_64 |
1727 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); | |
1728 | #endif | |
dacccfdd AK |
1729 | savesegment(fs, svm->host.fs); |
1730 | savesegment(gs, svm->host.gs); | |
1731 | svm->host.ldt = kvm_read_ldt(); | |
1732 | ||
94dfbdb3 | 1733 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1734 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
fbc0db76 | 1735 | |
ad721883 HZ |
1736 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
1737 | u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio; | |
1738 | if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) { | |
1739 | __this_cpu_write(current_tsc_ratio, tsc_ratio); | |
1740 | wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio); | |
1741 | } | |
fbc0db76 | 1742 | } |
46896c73 PB |
1743 | /* This assumes that the kernel never uses MSR_TSC_AUX */ |
1744 | if (static_cpu_has(X86_FEATURE_RDTSCP)) | |
1745 | wrmsrl(MSR_TSC_AUX, svm->tsc_aux); | |
8221c137 | 1746 | |
15d45071 AR |
1747 | if (sd->current_vmcb != svm->vmcb) { |
1748 | sd->current_vmcb = svm->vmcb; | |
1749 | indirect_branch_prediction_barrier(); | |
1750 | } | |
8221c137 | 1751 | avic_vcpu_load(vcpu, cpu); |
6aa8b732 AK |
1752 | } |
1753 | ||
1754 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
1755 | { | |
a2fa3e9f | 1756 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
1757 | int i; |
1758 | ||
8221c137 SS |
1759 | avic_vcpu_put(vcpu); |
1760 | ||
e1beb1d3 | 1761 | ++vcpu->stat.host_state_reload; |
dacccfdd AK |
1762 | kvm_load_ldt(svm->host.ldt); |
1763 | #ifdef CONFIG_X86_64 | |
1764 | loadsegment(fs, svm->host.fs); | |
296f781a | 1765 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase); |
893a5ab6 | 1766 | load_gs_index(svm->host.gs); |
dacccfdd | 1767 | #else |
831ca609 | 1768 | #ifdef CONFIG_X86_32_LAZY_GS |
dacccfdd | 1769 | loadsegment(gs, svm->host.gs); |
831ca609 | 1770 | #endif |
dacccfdd | 1771 | #endif |
94dfbdb3 | 1772 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1773 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1774 | } |
1775 | ||
8221c137 SS |
1776 | static void svm_vcpu_blocking(struct kvm_vcpu *vcpu) |
1777 | { | |
1778 | avic_set_running(vcpu, false); | |
1779 | } | |
1780 | ||
1781 | static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu) | |
1782 | { | |
1783 | avic_set_running(vcpu, true); | |
1784 | } | |
1785 | ||
6aa8b732 AK |
1786 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
1787 | { | |
9b611747 LP |
1788 | struct vcpu_svm *svm = to_svm(vcpu); |
1789 | unsigned long rflags = svm->vmcb->save.rflags; | |
1790 | ||
1791 | if (svm->nmi_singlestep) { | |
1792 | /* Hide our flags if they were not set by the guest */ | |
1793 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF)) | |
1794 | rflags &= ~X86_EFLAGS_TF; | |
1795 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF)) | |
1796 | rflags &= ~X86_EFLAGS_RF; | |
1797 | } | |
1798 | return rflags; | |
6aa8b732 AK |
1799 | } |
1800 | ||
1801 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
1802 | { | |
9b611747 LP |
1803 | if (to_svm(vcpu)->nmi_singlestep) |
1804 | rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); | |
1805 | ||
ae9fedc7 | 1806 | /* |
bb3541f1 | 1807 | * Any change of EFLAGS.VM is accompanied by a reload of SS |
ae9fedc7 PB |
1808 | * (caused by either a task switch or an inter-privilege IRET), |
1809 | * so we do not need to update the CPL here. | |
1810 | */ | |
a2fa3e9f | 1811 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
1812 | } |
1813 | ||
6de4f3ad AK |
1814 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
1815 | { | |
1816 | switch (reg) { | |
1817 | case VCPU_EXREG_PDPTR: | |
1818 | BUG_ON(!npt_enabled); | |
9f8fe504 | 1819 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
6de4f3ad AK |
1820 | break; |
1821 | default: | |
1822 | BUG(); | |
1823 | } | |
1824 | } | |
1825 | ||
f0b85051 AG |
1826 | static void svm_set_vintr(struct vcpu_svm *svm) |
1827 | { | |
8a05a1b8 | 1828 | set_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1829 | } |
1830 | ||
1831 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
1832 | { | |
8a05a1b8 | 1833 | clr_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1834 | } |
1835 | ||
6aa8b732 AK |
1836 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
1837 | { | |
a2fa3e9f | 1838 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
1839 | |
1840 | switch (seg) { | |
1841 | case VCPU_SREG_CS: return &save->cs; | |
1842 | case VCPU_SREG_DS: return &save->ds; | |
1843 | case VCPU_SREG_ES: return &save->es; | |
1844 | case VCPU_SREG_FS: return &save->fs; | |
1845 | case VCPU_SREG_GS: return &save->gs; | |
1846 | case VCPU_SREG_SS: return &save->ss; | |
1847 | case VCPU_SREG_TR: return &save->tr; | |
1848 | case VCPU_SREG_LDTR: return &save->ldtr; | |
1849 | } | |
1850 | BUG(); | |
8b6d44c7 | 1851 | return NULL; |
6aa8b732 AK |
1852 | } |
1853 | ||
1854 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1855 | { | |
1856 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1857 | ||
1858 | return s->base; | |
1859 | } | |
1860 | ||
1861 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
1862 | struct kvm_segment *var, int seg) | |
1863 | { | |
1864 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1865 | ||
1866 | var->base = s->base; | |
1867 | var->limit = s->limit; | |
1868 | var->selector = s->selector; | |
1869 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
1870 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
1871 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
1872 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
1873 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
1874 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
1875 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
80112c89 JM |
1876 | |
1877 | /* | |
1878 | * AMD CPUs circa 2014 track the G bit for all segments except CS. | |
1879 | * However, the SVM spec states that the G bit is not observed by the | |
1880 | * CPU, and some VMware virtual CPUs drop the G bit for all segments. | |
1881 | * So let's synthesize a legal G bit for all segments, this helps | |
1882 | * running KVM nested. It also helps cross-vendor migration, because | |
1883 | * Intel's vmentry has a check on the 'G' bit. | |
1884 | */ | |
1885 | var->g = s->limit > 0xfffff; | |
25022acc | 1886 | |
e0231715 JR |
1887 | /* |
1888 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
1889 | * for cross vendor migration purposes by "not present" |
1890 | */ | |
8eae9570 | 1891 | var->unusable = !var->present; |
19bca6ab | 1892 | |
1fbdc7a5 | 1893 | switch (seg) { |
1fbdc7a5 AP |
1894 | case VCPU_SREG_TR: |
1895 | /* | |
1896 | * Work around a bug where the busy flag in the tr selector | |
1897 | * isn't exposed | |
1898 | */ | |
c0d09828 | 1899 | var->type |= 0x2; |
1fbdc7a5 AP |
1900 | break; |
1901 | case VCPU_SREG_DS: | |
1902 | case VCPU_SREG_ES: | |
1903 | case VCPU_SREG_FS: | |
1904 | case VCPU_SREG_GS: | |
1905 | /* | |
1906 | * The accessed bit must always be set in the segment | |
1907 | * descriptor cache, although it can be cleared in the | |
1908 | * descriptor, the cached bit always remains at 1. Since | |
1909 | * Intel has a check on this, set it here to support | |
1910 | * cross-vendor migration. | |
1911 | */ | |
1912 | if (!var->unusable) | |
1913 | var->type |= 0x1; | |
1914 | break; | |
b586eb02 | 1915 | case VCPU_SREG_SS: |
e0231715 JR |
1916 | /* |
1917 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
1918 | * descriptor is left as 1, although the whole segment has |
1919 | * been made unusable. Clear it here to pass an Intel VMX | |
1920 | * entry check when cross vendor migrating. | |
1921 | */ | |
1922 | if (var->unusable) | |
1923 | var->db = 0; | |
d9c1b543 | 1924 | /* This is symmetric with svm_set_segment() */ |
33b458d2 | 1925 | var->dpl = to_svm(vcpu)->vmcb->save.cpl; |
b586eb02 | 1926 | break; |
1fbdc7a5 | 1927 | } |
6aa8b732 AK |
1928 | } |
1929 | ||
2e4d2653 IE |
1930 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
1931 | { | |
1932 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
1933 | ||
1934 | return save->cpl; | |
1935 | } | |
1936 | ||
89a27f4d | 1937 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1938 | { |
a2fa3e9f GH |
1939 | struct vcpu_svm *svm = to_svm(vcpu); |
1940 | ||
89a27f4d GN |
1941 | dt->size = svm->vmcb->save.idtr.limit; |
1942 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
1943 | } |
1944 | ||
89a27f4d | 1945 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1946 | { |
a2fa3e9f GH |
1947 | struct vcpu_svm *svm = to_svm(vcpu); |
1948 | ||
89a27f4d GN |
1949 | svm->vmcb->save.idtr.limit = dt->size; |
1950 | svm->vmcb->save.idtr.base = dt->address ; | |
17a703cb | 1951 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1952 | } |
1953 | ||
89a27f4d | 1954 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1955 | { |
a2fa3e9f GH |
1956 | struct vcpu_svm *svm = to_svm(vcpu); |
1957 | ||
89a27f4d GN |
1958 | dt->size = svm->vmcb->save.gdtr.limit; |
1959 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
1960 | } |
1961 | ||
89a27f4d | 1962 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1963 | { |
a2fa3e9f GH |
1964 | struct vcpu_svm *svm = to_svm(vcpu); |
1965 | ||
89a27f4d GN |
1966 | svm->vmcb->save.gdtr.limit = dt->size; |
1967 | svm->vmcb->save.gdtr.base = dt->address ; | |
17a703cb | 1968 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1969 | } |
1970 | ||
e8467fda AK |
1971 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
1972 | { | |
1973 | } | |
1974 | ||
aff48baa AK |
1975 | static void svm_decache_cr3(struct kvm_vcpu *vcpu) |
1976 | { | |
1977 | } | |
1978 | ||
25c4c276 | 1979 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
1980 | { |
1981 | } | |
1982 | ||
d225157b AK |
1983 | static void update_cr0_intercept(struct vcpu_svm *svm) |
1984 | { | |
1985 | ulong gcr0 = svm->vcpu.arch.cr0; | |
1986 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
1987 | ||
bd7e5b08 PB |
1988 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) |
1989 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
d225157b | 1990 | |
dcca1a65 | 1991 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 1992 | |
bd7e5b08 | 1993 | if (gcr0 == *hcr0) { |
4ee546b4 RJ |
1994 | clr_cr_intercept(svm, INTERCEPT_CR0_READ); |
1995 | clr_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b | 1996 | } else { |
4ee546b4 RJ |
1997 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1998 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b AK |
1999 | } |
2000 | } | |
2001 | ||
6aa8b732 AK |
2002 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
2003 | { | |
a2fa3e9f GH |
2004 | struct vcpu_svm *svm = to_svm(vcpu); |
2005 | ||
05b3e0c2 | 2006 | #ifdef CONFIG_X86_64 |
f6801dff | 2007 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 2008 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 2009 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 2010 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
2011 | } |
2012 | ||
d77c26fc | 2013 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 2014 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 2015 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
2016 | } |
2017 | } | |
2018 | #endif | |
ad312c7c | 2019 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
2020 | |
2021 | if (!npt_enabled) | |
2022 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 | 2023 | |
bcf166a9 PB |
2024 | /* |
2025 | * re-enable caching here because the QEMU bios | |
2026 | * does not do it - this results in some delay at | |
2027 | * reboot | |
2028 | */ | |
2029 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
2030 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 2031 | svm->vmcb->save.cr0 = cr0; |
dcca1a65 | 2032 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 2033 | update_cr0_intercept(svm); |
6aa8b732 AK |
2034 | } |
2035 | ||
5e1746d6 | 2036 | static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 2037 | { |
1e02ce4c | 2038 | unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE; |
e5eab0ce JR |
2039 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
2040 | ||
5e1746d6 NHE |
2041 | if (cr4 & X86_CR4_VMXE) |
2042 | return 1; | |
2043 | ||
e5eab0ce | 2044 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) |
f40f6a45 | 2045 | svm_flush_tlb(vcpu); |
6394b649 | 2046 | |
ec077263 JR |
2047 | vcpu->arch.cr4 = cr4; |
2048 | if (!npt_enabled) | |
2049 | cr4 |= X86_CR4_PAE; | |
6394b649 | 2050 | cr4 |= host_cr4_mce; |
ec077263 | 2051 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
dcca1a65 | 2052 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
5e1746d6 | 2053 | return 0; |
6aa8b732 AK |
2054 | } |
2055 | ||
2056 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
2057 | struct kvm_segment *var, int seg) | |
2058 | { | |
a2fa3e9f | 2059 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
2060 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
2061 | ||
2062 | s->base = var->base; | |
2063 | s->limit = var->limit; | |
2064 | s->selector = var->selector; | |
d9c1b543 RP |
2065 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); |
2066 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
2067 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
2068 | s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT; | |
2069 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
2070 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
2071 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
2072 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
ae9fedc7 PB |
2073 | |
2074 | /* | |
2075 | * This is always accurate, except if SYSRET returned to a segment | |
2076 | * with SS.DPL != 3. Intel does not have this quirk, and always | |
2077 | * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it | |
2078 | * would entail passing the CPL to userspace and back. | |
2079 | */ | |
2080 | if (seg == VCPU_SREG_SS) | |
d9c1b543 RP |
2081 | /* This is symmetric with svm_get_segment() */ |
2082 | svm->vmcb->save.cpl = (var->dpl & 3); | |
6aa8b732 | 2083 | |
060d0c9a | 2084 | mark_dirty(svm->vmcb, VMCB_SEG); |
6aa8b732 AK |
2085 | } |
2086 | ||
cbdb967a | 2087 | static void update_bp_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 2088 | { |
d0bfb940 JK |
2089 | struct vcpu_svm *svm = to_svm(vcpu); |
2090 | ||
18c918c5 | 2091 | clr_exception_intercept(svm, BP_VECTOR); |
44c11430 | 2092 | |
d0bfb940 | 2093 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
d0bfb940 | 2094 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
18c918c5 | 2095 | set_exception_intercept(svm, BP_VECTOR); |
d0bfb940 JK |
2096 | } else |
2097 | vcpu->guest_debug = 0; | |
44c11430 GN |
2098 | } |
2099 | ||
0fe1e009 | 2100 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 2101 | { |
0fe1e009 TH |
2102 | if (sd->next_asid > sd->max_asid) { |
2103 | ++sd->asid_generation; | |
2104 | sd->next_asid = 1; | |
a2fa3e9f | 2105 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
2106 | } |
2107 | ||
0fe1e009 TH |
2108 | svm->asid_generation = sd->asid_generation; |
2109 | svm->vmcb->control.asid = sd->next_asid++; | |
d48086d1 JR |
2110 | |
2111 | mark_dirty(svm->vmcb, VMCB_ASID); | |
6aa8b732 AK |
2112 | } |
2113 | ||
73aaf249 JK |
2114 | static u64 svm_get_dr6(struct kvm_vcpu *vcpu) |
2115 | { | |
2116 | return to_svm(vcpu)->vmcb->save.dr6; | |
2117 | } | |
2118 | ||
2119 | static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value) | |
2120 | { | |
2121 | struct vcpu_svm *svm = to_svm(vcpu); | |
2122 | ||
2123 | svm->vmcb->save.dr6 = value; | |
2124 | mark_dirty(svm->vmcb, VMCB_DR); | |
2125 | } | |
2126 | ||
facb0139 PB |
2127 | static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
2128 | { | |
2129 | struct vcpu_svm *svm = to_svm(vcpu); | |
2130 | ||
2131 | get_debugreg(vcpu->arch.db[0], 0); | |
2132 | get_debugreg(vcpu->arch.db[1], 1); | |
2133 | get_debugreg(vcpu->arch.db[2], 2); | |
2134 | get_debugreg(vcpu->arch.db[3], 3); | |
2135 | vcpu->arch.dr6 = svm_get_dr6(vcpu); | |
2136 | vcpu->arch.dr7 = svm->vmcb->save.dr7; | |
2137 | ||
2138 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
2139 | set_dr_intercepts(svm); | |
2140 | } | |
2141 | ||
020df079 | 2142 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 2143 | { |
42dbaa5a | 2144 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 2145 | |
020df079 | 2146 | svm->vmcb->save.dr7 = value; |
72214b96 | 2147 | mark_dirty(svm->vmcb, VMCB_DR); |
6aa8b732 AK |
2148 | } |
2149 | ||
851ba692 | 2150 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 2151 | { |
631bc487 | 2152 | u64 fault_address = svm->vmcb->control.exit_info_2; |
1261bfa3 | 2153 | u64 error_code = svm->vmcb->control.exit_info_1; |
6aa8b732 | 2154 | |
1261bfa3 | 2155 | return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address, |
dc25e89e | 2156 | svm->vmcb->control.insn_bytes, |
d0006530 PB |
2157 | svm->vmcb->control.insn_len); |
2158 | } | |
2159 | ||
2160 | static int npf_interception(struct vcpu_svm *svm) | |
2161 | { | |
2162 | u64 fault_address = svm->vmcb->control.exit_info_2; | |
2163 | u64 error_code = svm->vmcb->control.exit_info_1; | |
2164 | ||
2165 | trace_kvm_page_fault(fault_address, error_code); | |
2166 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code, | |
2167 | svm->vmcb->control.insn_bytes, | |
2168 | svm->vmcb->control.insn_len); | |
6aa8b732 AK |
2169 | } |
2170 | ||
851ba692 | 2171 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 2172 | { |
851ba692 AK |
2173 | struct kvm_run *kvm_run = svm->vcpu.run; |
2174 | ||
d0bfb940 | 2175 | if (!(svm->vcpu.guest_debug & |
44c11430 | 2176 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 2177 | !svm->nmi_singlestep) { |
d0bfb940 JK |
2178 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
2179 | return 1; | |
2180 | } | |
44c11430 | 2181 | |
6be7d306 | 2182 | if (svm->nmi_singlestep) { |
4aebd0e9 | 2183 | disable_nmi_singlestep(svm); |
44c11430 GN |
2184 | } |
2185 | ||
2186 | if (svm->vcpu.guest_debug & | |
e0231715 | 2187 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
2188 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
2189 | kvm_run->debug.arch.pc = | |
2190 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
2191 | kvm_run->debug.arch.exception = DB_VECTOR; | |
2192 | return 0; | |
2193 | } | |
2194 | ||
2195 | return 1; | |
d0bfb940 JK |
2196 | } |
2197 | ||
851ba692 | 2198 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 2199 | { |
851ba692 AK |
2200 | struct kvm_run *kvm_run = svm->vcpu.run; |
2201 | ||
d0bfb940 JK |
2202 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
2203 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
2204 | kvm_run->debug.arch.exception = BP_VECTOR; | |
2205 | return 0; | |
2206 | } | |
2207 | ||
851ba692 | 2208 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
2209 | { |
2210 | int er; | |
2211 | ||
51d8b661 | 2212 | er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD); |
61cb57c9 LA |
2213 | if (er == EMULATE_USER_EXIT) |
2214 | return 0; | |
7aa81cc0 | 2215 | if (er != EMULATE_DONE) |
7ee5d940 | 2216 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
2217 | return 1; |
2218 | } | |
2219 | ||
54a20552 EN |
2220 | static int ac_interception(struct vcpu_svm *svm) |
2221 | { | |
2222 | kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0); | |
2223 | return 1; | |
2224 | } | |
2225 | ||
67ec6607 JR |
2226 | static bool is_erratum_383(void) |
2227 | { | |
2228 | int err, i; | |
2229 | u64 value; | |
2230 | ||
2231 | if (!erratum_383_found) | |
2232 | return false; | |
2233 | ||
2234 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
2235 | if (err) | |
2236 | return false; | |
2237 | ||
2238 | /* Bit 62 may or may not be set for this mce */ | |
2239 | value &= ~(1ULL << 62); | |
2240 | ||
2241 | if (value != 0xb600000000010015ULL) | |
2242 | return false; | |
2243 | ||
2244 | /* Clear MCi_STATUS registers */ | |
2245 | for (i = 0; i < 6; ++i) | |
2246 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
2247 | ||
2248 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
2249 | if (!err) { | |
2250 | u32 low, high; | |
2251 | ||
2252 | value &= ~(1ULL << 2); | |
2253 | low = lower_32_bits(value); | |
2254 | high = upper_32_bits(value); | |
2255 | ||
2256 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
2257 | } | |
2258 | ||
2259 | /* Flush tlb to evict multi-match entries */ | |
2260 | __flush_tlb_all(); | |
2261 | ||
2262 | return true; | |
2263 | } | |
2264 | ||
fe5913e4 | 2265 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 2266 | { |
67ec6607 JR |
2267 | if (is_erratum_383()) { |
2268 | /* | |
2269 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
2270 | * guest. | |
2271 | */ | |
2272 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
2273 | ||
a8eeb04a | 2274 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
2275 | |
2276 | return; | |
2277 | } | |
2278 | ||
53371b50 JR |
2279 | /* |
2280 | * On an #MC intercept the MCE handler is not called automatically in | |
2281 | * the host. So do it by hand here. | |
2282 | */ | |
2283 | asm volatile ( | |
2284 | "int $0x12\n"); | |
2285 | /* not sure if we ever come back to this point */ | |
2286 | ||
fe5913e4 JR |
2287 | return; |
2288 | } | |
2289 | ||
2290 | static int mc_interception(struct vcpu_svm *svm) | |
2291 | { | |
53371b50 JR |
2292 | return 1; |
2293 | } | |
2294 | ||
851ba692 | 2295 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 2296 | { |
851ba692 AK |
2297 | struct kvm_run *kvm_run = svm->vcpu.run; |
2298 | ||
46fe4ddd JR |
2299 | /* |
2300 | * VMCB is undefined after a SHUTDOWN intercept | |
2301 | * so reinitialize it. | |
2302 | */ | |
a2fa3e9f | 2303 | clear_page(svm->vmcb); |
5690891b | 2304 | init_vmcb(svm); |
46fe4ddd JR |
2305 | |
2306 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
2307 | return 0; | |
2308 | } | |
2309 | ||
851ba692 | 2310 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 2311 | { |
cf8f70bf | 2312 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 2313 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
b742c1e6 | 2314 | int size, in, string, ret; |
039576c0 | 2315 | unsigned port; |
6aa8b732 | 2316 | |
e756fc62 | 2317 | ++svm->vcpu.stat.io_exits; |
e70669ab | 2318 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 2319 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
8370c3d0 | 2320 | if (string) |
51d8b661 | 2321 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
cf8f70bf | 2322 | |
039576c0 AK |
2323 | port = io_info >> 16; |
2324 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 2325 | svm->next_rip = svm->vmcb->control.exit_info_2; |
b742c1e6 | 2326 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
cf8f70bf | 2327 | |
b742c1e6 LP |
2328 | /* |
2329 | * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered | |
2330 | * KVM_EXIT_DEBUG here. | |
2331 | */ | |
2332 | if (in) | |
2333 | return kvm_fast_pio_in(vcpu, size, port) && ret; | |
2334 | else | |
2335 | return kvm_fast_pio_out(vcpu, size, port) && ret; | |
6aa8b732 AK |
2336 | } |
2337 | ||
851ba692 | 2338 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
2339 | { |
2340 | return 1; | |
2341 | } | |
2342 | ||
851ba692 | 2343 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
2344 | { |
2345 | ++svm->vcpu.stat.irq_exits; | |
2346 | return 1; | |
2347 | } | |
2348 | ||
851ba692 | 2349 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
2350 | { |
2351 | return 1; | |
2352 | } | |
2353 | ||
851ba692 | 2354 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 2355 | { |
5fdbf976 | 2356 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 | 2357 | return kvm_emulate_halt(&svm->vcpu); |
6aa8b732 AK |
2358 | } |
2359 | ||
851ba692 | 2360 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 2361 | { |
5fdbf976 | 2362 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
0d9c055e | 2363 | return kvm_emulate_hypercall(&svm->vcpu); |
02e235bc AK |
2364 | } |
2365 | ||
5bd2edc3 JR |
2366 | static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) |
2367 | { | |
2368 | struct vcpu_svm *svm = to_svm(vcpu); | |
2369 | ||
2370 | return svm->nested.nested_cr3; | |
2371 | } | |
2372 | ||
e4e517b4 AK |
2373 | static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index) |
2374 | { | |
2375 | struct vcpu_svm *svm = to_svm(vcpu); | |
2376 | u64 cr3 = svm->nested.nested_cr3; | |
2377 | u64 pdpte; | |
2378 | int ret; | |
2379 | ||
d0ec49d4 | 2380 | ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte, |
54bf36aa | 2381 | offset_in_page(cr3) + index * 8, 8); |
e4e517b4 AK |
2382 | if (ret) |
2383 | return 0; | |
2384 | return pdpte; | |
2385 | } | |
2386 | ||
5bd2edc3 JR |
2387 | static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu, |
2388 | unsigned long root) | |
2389 | { | |
2390 | struct vcpu_svm *svm = to_svm(vcpu); | |
2391 | ||
d0ec49d4 | 2392 | svm->vmcb->control.nested_cr3 = __sme_set(root); |
b2747166 | 2393 | mark_dirty(svm->vmcb, VMCB_NPT); |
f40f6a45 | 2394 | svm_flush_tlb(vcpu); |
5bd2edc3 JR |
2395 | } |
2396 | ||
6389ee94 AK |
2397 | static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, |
2398 | struct x86_exception *fault) | |
5bd2edc3 JR |
2399 | { |
2400 | struct vcpu_svm *svm = to_svm(vcpu); | |
2401 | ||
5e352519 PB |
2402 | if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) { |
2403 | /* | |
2404 | * TODO: track the cause of the nested page fault, and | |
2405 | * correctly fill in the high bits of exit_info_1. | |
2406 | */ | |
2407 | svm->vmcb->control.exit_code = SVM_EXIT_NPF; | |
2408 | svm->vmcb->control.exit_code_hi = 0; | |
2409 | svm->vmcb->control.exit_info_1 = (1ULL << 32); | |
2410 | svm->vmcb->control.exit_info_2 = fault->address; | |
2411 | } | |
2412 | ||
2413 | svm->vmcb->control.exit_info_1 &= ~0xffffffffULL; | |
2414 | svm->vmcb->control.exit_info_1 |= fault->error_code; | |
2415 | ||
2416 | /* | |
2417 | * The present bit is always zero for page structure faults on real | |
2418 | * hardware. | |
2419 | */ | |
2420 | if (svm->vmcb->control.exit_info_1 & (2ULL << 32)) | |
2421 | svm->vmcb->control.exit_info_1 &= ~1; | |
5bd2edc3 JR |
2422 | |
2423 | nested_svm_vmexit(svm); | |
2424 | } | |
2425 | ||
8a3c1a33 | 2426 | static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) |
4b16184c | 2427 | { |
ad896af0 PB |
2428 | WARN_ON(mmu_is_nested(vcpu)); |
2429 | kvm_init_shadow_mmu(vcpu); | |
4b16184c JR |
2430 | vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3; |
2431 | vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3; | |
e4e517b4 | 2432 | vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr; |
4b16184c | 2433 | vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit; |
855feb67 | 2434 | vcpu->arch.mmu.shadow_root_level = get_npt_level(vcpu); |
c258b62b | 2435 | reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu); |
4b16184c | 2436 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; |
4b16184c JR |
2437 | } |
2438 | ||
2439 | static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
2440 | { | |
2441 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
2442 | } | |
2443 | ||
c0725420 AG |
2444 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
2445 | { | |
e9196ceb DC |
2446 | if (!(svm->vcpu.arch.efer & EFER_SVME) || |
2447 | !is_paging(&svm->vcpu)) { | |
c0725420 AG |
2448 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
2449 | return 1; | |
2450 | } | |
2451 | ||
2452 | if (svm->vmcb->save.cpl) { | |
2453 | kvm_inject_gp(&svm->vcpu, 0); | |
2454 | return 1; | |
2455 | } | |
2456 | ||
e9196ceb | 2457 | return 0; |
c0725420 AG |
2458 | } |
2459 | ||
cf74a78b AG |
2460 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
2461 | bool has_error_code, u32 error_code) | |
2462 | { | |
b8e88bc8 JR |
2463 | int vmexit; |
2464 | ||
2030753d | 2465 | if (!is_guest_mode(&svm->vcpu)) |
0295ad7d | 2466 | return 0; |
cf74a78b | 2467 | |
adfe20fb WL |
2468 | vmexit = nested_svm_intercept(svm); |
2469 | if (vmexit != NESTED_EXIT_DONE) | |
2470 | return 0; | |
2471 | ||
0295ad7d JR |
2472 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
2473 | svm->vmcb->control.exit_code_hi = 0; | |
2474 | svm->vmcb->control.exit_info_1 = error_code; | |
b96fb439 PB |
2475 | |
2476 | /* | |
2477 | * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception. | |
2478 | * The fix is to add the ancillary datum (CR2 or DR6) to structs | |
2479 | * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be | |
2480 | * written only when inject_pending_event runs (DR6 would written here | |
2481 | * too). This should be conditional on a new capability---if the | |
2482 | * capability is disabled, kvm_multiple_exception would write the | |
2483 | * ancillary information to CR2 or DR6, for backwards ABI-compatibility. | |
2484 | */ | |
adfe20fb WL |
2485 | if (svm->vcpu.arch.exception.nested_apf) |
2486 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token; | |
2487 | else | |
2488 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
b8e88bc8 | 2489 | |
adfe20fb | 2490 | svm->nested.exit_required = true; |
b8e88bc8 | 2491 | return vmexit; |
cf74a78b AG |
2492 | } |
2493 | ||
8fe54654 JR |
2494 | /* This function returns true if it is save to enable the irq window */ |
2495 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 2496 | { |
2030753d | 2497 | if (!is_guest_mode(&svm->vcpu)) |
8fe54654 | 2498 | return true; |
cf74a78b | 2499 | |
26666957 | 2500 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 2501 | return true; |
cf74a78b | 2502 | |
26666957 | 2503 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 2504 | return false; |
cf74a78b | 2505 | |
a0a07cd2 GN |
2506 | /* |
2507 | * if vmexit was already requested (by intercepted exception | |
2508 | * for instance) do not overwrite it with "external interrupt" | |
2509 | * vmexit. | |
2510 | */ | |
2511 | if (svm->nested.exit_required) | |
2512 | return false; | |
2513 | ||
197717d5 JR |
2514 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
2515 | svm->vmcb->control.exit_info_1 = 0; | |
2516 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 2517 | |
cd3ff653 JR |
2518 | if (svm->nested.intercept & 1ULL) { |
2519 | /* | |
2520 | * The #vmexit can't be emulated here directly because this | |
c5ec2e56 | 2521 | * code path runs with irqs and preemption disabled. A |
cd3ff653 JR |
2522 | * #vmexit emulation might sleep. Only signal request for |
2523 | * the #vmexit here. | |
2524 | */ | |
2525 | svm->nested.exit_required = true; | |
236649de | 2526 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 2527 | return false; |
cf74a78b AG |
2528 | } |
2529 | ||
8fe54654 | 2530 | return true; |
cf74a78b AG |
2531 | } |
2532 | ||
887f500c JR |
2533 | /* This function returns true if it is save to enable the nmi window */ |
2534 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
2535 | { | |
2030753d | 2536 | if (!is_guest_mode(&svm->vcpu)) |
887f500c JR |
2537 | return true; |
2538 | ||
2539 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
2540 | return true; | |
2541 | ||
2542 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
2543 | svm->nested.exit_required = true; | |
2544 | ||
2545 | return false; | |
cf74a78b AG |
2546 | } |
2547 | ||
7597f129 | 2548 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) |
34f80cfa JR |
2549 | { |
2550 | struct page *page; | |
2551 | ||
6c3bd3d7 JR |
2552 | might_sleep(); |
2553 | ||
54bf36aa | 2554 | page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT); |
34f80cfa JR |
2555 | if (is_error_page(page)) |
2556 | goto error; | |
2557 | ||
7597f129 JR |
2558 | *_page = page; |
2559 | ||
2560 | return kmap(page); | |
34f80cfa JR |
2561 | |
2562 | error: | |
34f80cfa JR |
2563 | kvm_inject_gp(&svm->vcpu, 0); |
2564 | ||
2565 | return NULL; | |
2566 | } | |
2567 | ||
7597f129 | 2568 | static void nested_svm_unmap(struct page *page) |
34f80cfa | 2569 | { |
7597f129 | 2570 | kunmap(page); |
34f80cfa JR |
2571 | kvm_release_page_dirty(page); |
2572 | } | |
34f80cfa | 2573 | |
ce2ac085 JR |
2574 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
2575 | { | |
9bf41833 JK |
2576 | unsigned port, size, iopm_len; |
2577 | u16 val, mask; | |
2578 | u8 start_bit; | |
ce2ac085 | 2579 | u64 gpa; |
34f80cfa | 2580 | |
ce2ac085 JR |
2581 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
2582 | return NESTED_EXIT_HOST; | |
34f80cfa | 2583 | |
ce2ac085 | 2584 | port = svm->vmcb->control.exit_info_1 >> 16; |
9bf41833 JK |
2585 | size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >> |
2586 | SVM_IOIO_SIZE_SHIFT; | |
ce2ac085 | 2587 | gpa = svm->nested.vmcb_iopm + (port / 8); |
9bf41833 JK |
2588 | start_bit = port % 8; |
2589 | iopm_len = (start_bit + size > 8) ? 2 : 1; | |
2590 | mask = (0xf >> (4 - size)) << start_bit; | |
2591 | val = 0; | |
ce2ac085 | 2592 | |
54bf36aa | 2593 | if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len)) |
9bf41833 | 2594 | return NESTED_EXIT_DONE; |
ce2ac085 | 2595 | |
9bf41833 | 2596 | return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
34f80cfa JR |
2597 | } |
2598 | ||
d2477826 | 2599 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 2600 | { |
0d6b3537 JR |
2601 | u32 offset, msr, value; |
2602 | int write, mask; | |
4c2161ae | 2603 | |
3d62d9aa | 2604 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 2605 | return NESTED_EXIT_HOST; |
3d62d9aa | 2606 | |
0d6b3537 JR |
2607 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
2608 | offset = svm_msrpm_offset(msr); | |
2609 | write = svm->vmcb->control.exit_info_1 & 1; | |
2610 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 2611 | |
0d6b3537 JR |
2612 | if (offset == MSR_INVALID) |
2613 | return NESTED_EXIT_DONE; | |
4c2161ae | 2614 | |
0d6b3537 JR |
2615 | /* Offset is in 32 bit units but need in 8 bit units */ |
2616 | offset *= 4; | |
4c2161ae | 2617 | |
54bf36aa | 2618 | if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4)) |
0d6b3537 | 2619 | return NESTED_EXIT_DONE; |
3d62d9aa | 2620 | |
0d6b3537 | 2621 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
2622 | } |
2623 | ||
ab2f4d73 LP |
2624 | /* DB exceptions for our internal use must not cause vmexit */ |
2625 | static int nested_svm_intercept_db(struct vcpu_svm *svm) | |
2626 | { | |
2627 | unsigned long dr6; | |
2628 | ||
2629 | /* if we're not singlestepping, it's not ours */ | |
2630 | if (!svm->nmi_singlestep) | |
2631 | return NESTED_EXIT_DONE; | |
2632 | ||
2633 | /* if it's not a singlestep exception, it's not ours */ | |
2634 | if (kvm_get_dr(&svm->vcpu, 6, &dr6)) | |
2635 | return NESTED_EXIT_DONE; | |
2636 | if (!(dr6 & DR6_BS)) | |
2637 | return NESTED_EXIT_DONE; | |
2638 | ||
2639 | /* if the guest is singlestepping, it should get the vmexit */ | |
2640 | if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) { | |
2641 | disable_nmi_singlestep(svm); | |
2642 | return NESTED_EXIT_DONE; | |
2643 | } | |
2644 | ||
2645 | /* it's ours, the nested hypervisor must not see this one */ | |
2646 | return NESTED_EXIT_HOST; | |
2647 | } | |
2648 | ||
410e4d57 | 2649 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 2650 | { |
cf74a78b | 2651 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 2652 | |
410e4d57 JR |
2653 | switch (exit_code) { |
2654 | case SVM_EXIT_INTR: | |
2655 | case SVM_EXIT_NMI: | |
ff47a49b | 2656 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 2657 | return NESTED_EXIT_HOST; |
410e4d57 | 2658 | case SVM_EXIT_NPF: |
e0231715 | 2659 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
2660 | if (npt_enabled) |
2661 | return NESTED_EXIT_HOST; | |
2662 | break; | |
410e4d57 | 2663 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
631bc487 | 2664 | /* When we're shadowing, trap PFs, but not async PF */ |
1261bfa3 | 2665 | if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0) |
410e4d57 JR |
2666 | return NESTED_EXIT_HOST; |
2667 | break; | |
2668 | default: | |
2669 | break; | |
cf74a78b AG |
2670 | } |
2671 | ||
410e4d57 JR |
2672 | return NESTED_EXIT_CONTINUE; |
2673 | } | |
2674 | ||
2675 | /* | |
2676 | * If this function returns true, this #vmexit was already handled | |
2677 | */ | |
b8e88bc8 | 2678 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
2679 | { |
2680 | u32 exit_code = svm->vmcb->control.exit_code; | |
2681 | int vmexit = NESTED_EXIT_HOST; | |
2682 | ||
cf74a78b | 2683 | switch (exit_code) { |
9c4e40b9 | 2684 | case SVM_EXIT_MSR: |
3d62d9aa | 2685 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 2686 | break; |
ce2ac085 JR |
2687 | case SVM_EXIT_IOIO: |
2688 | vmexit = nested_svm_intercept_ioio(svm); | |
2689 | break; | |
4ee546b4 RJ |
2690 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: { |
2691 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0); | |
2692 | if (svm->nested.intercept_cr & bit) | |
410e4d57 | 2693 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2694 | break; |
2695 | } | |
3aed041a JR |
2696 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: { |
2697 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0); | |
2698 | if (svm->nested.intercept_dr & bit) | |
410e4d57 | 2699 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2700 | break; |
2701 | } | |
2702 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
2703 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
ab2f4d73 LP |
2704 | if (svm->nested.intercept_exceptions & excp_bits) { |
2705 | if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR) | |
2706 | vmexit = nested_svm_intercept_db(svm); | |
2707 | else | |
2708 | vmexit = NESTED_EXIT_DONE; | |
2709 | } | |
631bc487 GN |
2710 | /* async page fault always cause vmexit */ |
2711 | else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) && | |
adfe20fb | 2712 | svm->vcpu.arch.exception.nested_apf != 0) |
631bc487 | 2713 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2714 | break; |
2715 | } | |
228070b1 JR |
2716 | case SVM_EXIT_ERR: { |
2717 | vmexit = NESTED_EXIT_DONE; | |
2718 | break; | |
2719 | } | |
cf74a78b AG |
2720 | default: { |
2721 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 2722 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 2723 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2724 | } |
2725 | } | |
2726 | ||
b8e88bc8 JR |
2727 | return vmexit; |
2728 | } | |
2729 | ||
2730 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
2731 | { | |
2732 | int vmexit; | |
2733 | ||
2734 | vmexit = nested_svm_intercept(svm); | |
2735 | ||
2736 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 2737 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
2738 | |
2739 | return vmexit; | |
cf74a78b AG |
2740 | } |
2741 | ||
0460a979 JR |
2742 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
2743 | { | |
2744 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
2745 | struct vmcb_control_area *from = &from_vmcb->control; | |
2746 | ||
4ee546b4 | 2747 | dst->intercept_cr = from->intercept_cr; |
3aed041a | 2748 | dst->intercept_dr = from->intercept_dr; |
0460a979 JR |
2749 | dst->intercept_exceptions = from->intercept_exceptions; |
2750 | dst->intercept = from->intercept; | |
2751 | dst->iopm_base_pa = from->iopm_base_pa; | |
2752 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
2753 | dst->tsc_offset = from->tsc_offset; | |
2754 | dst->asid = from->asid; | |
2755 | dst->tlb_ctl = from->tlb_ctl; | |
2756 | dst->int_ctl = from->int_ctl; | |
2757 | dst->int_vector = from->int_vector; | |
2758 | dst->int_state = from->int_state; | |
2759 | dst->exit_code = from->exit_code; | |
2760 | dst->exit_code_hi = from->exit_code_hi; | |
2761 | dst->exit_info_1 = from->exit_info_1; | |
2762 | dst->exit_info_2 = from->exit_info_2; | |
2763 | dst->exit_int_info = from->exit_int_info; | |
2764 | dst->exit_int_info_err = from->exit_int_info_err; | |
2765 | dst->nested_ctl = from->nested_ctl; | |
2766 | dst->event_inj = from->event_inj; | |
2767 | dst->event_inj_err = from->event_inj_err; | |
2768 | dst->nested_cr3 = from->nested_cr3; | |
0dc92119 | 2769 | dst->virt_ext = from->virt_ext; |
0460a979 JR |
2770 | } |
2771 | ||
34f80cfa | 2772 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 2773 | { |
34f80cfa | 2774 | struct vmcb *nested_vmcb; |
e6aa9abd | 2775 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 2776 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2777 | struct page *page; |
cf74a78b | 2778 | |
17897f36 JR |
2779 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
2780 | vmcb->control.exit_info_1, | |
2781 | vmcb->control.exit_info_2, | |
2782 | vmcb->control.exit_int_info, | |
e097e5ff SH |
2783 | vmcb->control.exit_int_info_err, |
2784 | KVM_ISA_SVM); | |
17897f36 | 2785 | |
7597f129 | 2786 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); |
34f80cfa JR |
2787 | if (!nested_vmcb) |
2788 | return 1; | |
2789 | ||
2030753d JR |
2790 | /* Exit Guest-Mode */ |
2791 | leave_guest_mode(&svm->vcpu); | |
06fc7772 JR |
2792 | svm->nested.vmcb = 0; |
2793 | ||
cf74a78b | 2794 | /* Give the current vmcb to the guest */ |
33740e40 JR |
2795 | disable_gif(svm); |
2796 | ||
2797 | nested_vmcb->save.es = vmcb->save.es; | |
2798 | nested_vmcb->save.cs = vmcb->save.cs; | |
2799 | nested_vmcb->save.ss = vmcb->save.ss; | |
2800 | nested_vmcb->save.ds = vmcb->save.ds; | |
2801 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
2802 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
3f6a9d16 | 2803 | nested_vmcb->save.efer = svm->vcpu.arch.efer; |
cdbbdc12 | 2804 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
9f8fe504 | 2805 | nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu); |
33740e40 | 2806 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 2807 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2808 | nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu); |
33740e40 JR |
2809 | nested_vmcb->save.rip = vmcb->save.rip; |
2810 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
2811 | nested_vmcb->save.rax = vmcb->save.rax; | |
2812 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
2813 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
2814 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
2815 | ||
2816 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
2817 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
2818 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
2819 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
2820 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
2821 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
2822 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
2823 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
2824 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
6092d3d3 JR |
2825 | |
2826 | if (svm->nrips_enabled) | |
2827 | nested_vmcb->control.next_rip = vmcb->control.next_rip; | |
8d23c466 AG |
2828 | |
2829 | /* | |
2830 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
2831 | * to make sure that we do not lose injected events. So check event_inj | |
2832 | * here and copy it to exit_int_info if it is valid. | |
2833 | * Exit_int_info and event_inj can't be both valid because the case | |
2834 | * below only happens on a VMRUN instruction intercept which has | |
2835 | * no valid exit_int_info set. | |
2836 | */ | |
2837 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
2838 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
2839 | ||
2840 | nc->exit_int_info = vmcb->control.event_inj; | |
2841 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
2842 | } | |
2843 | ||
33740e40 JR |
2844 | nested_vmcb->control.tlb_ctl = 0; |
2845 | nested_vmcb->control.event_inj = 0; | |
2846 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
2847 | |
2848 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
2849 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
2850 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
2851 | ||
cf74a78b | 2852 | /* Restore the original control entries */ |
0460a979 | 2853 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 2854 | |
219b65dc AG |
2855 | kvm_clear_exception_queue(&svm->vcpu); |
2856 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b | 2857 | |
4b16184c JR |
2858 | svm->nested.nested_cr3 = 0; |
2859 | ||
cf74a78b AG |
2860 | /* Restore selected save entries */ |
2861 | svm->vmcb->save.es = hsave->save.es; | |
2862 | svm->vmcb->save.cs = hsave->save.cs; | |
2863 | svm->vmcb->save.ss = hsave->save.ss; | |
2864 | svm->vmcb->save.ds = hsave->save.ds; | |
2865 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
2866 | svm->vmcb->save.idtr = hsave->save.idtr; | |
f6e78475 | 2867 | kvm_set_rflags(&svm->vcpu, hsave->save.rflags); |
cf74a78b AG |
2868 | svm_set_efer(&svm->vcpu, hsave->save.efer); |
2869 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
2870 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
2871 | if (npt_enabled) { | |
2872 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
2873 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
2874 | } else { | |
2390218b | 2875 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b AG |
2876 | } |
2877 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
2878 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
2879 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
2880 | svm->vmcb->save.dr7 = 0; | |
2881 | svm->vmcb->save.cpl = 0; | |
2882 | svm->vmcb->control.exit_int_info = 0; | |
2883 | ||
8d28fec4 RJ |
2884 | mark_all_dirty(svm->vmcb); |
2885 | ||
7597f129 | 2886 | nested_svm_unmap(page); |
cf74a78b | 2887 | |
4b16184c | 2888 | nested_svm_uninit_mmu_context(&svm->vcpu); |
cf74a78b AG |
2889 | kvm_mmu_reset_context(&svm->vcpu); |
2890 | kvm_mmu_load(&svm->vcpu); | |
2891 | ||
2892 | return 0; | |
2893 | } | |
3d6368ef | 2894 | |
9738b2c9 | 2895 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 2896 | { |
323c3d80 JR |
2897 | /* |
2898 | * This function merges the msr permission bitmaps of kvm and the | |
c5ec2e56 | 2899 | * nested vmcb. It is optimized in that it only merges the parts where |
323c3d80 JR |
2900 | * the kvm msr permission bitmap may contain zero bits |
2901 | */ | |
3d6368ef | 2902 | int i; |
9738b2c9 | 2903 | |
323c3d80 JR |
2904 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
2905 | return true; | |
9738b2c9 | 2906 | |
323c3d80 JR |
2907 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
2908 | u32 value, p; | |
2909 | u64 offset; | |
9738b2c9 | 2910 | |
323c3d80 JR |
2911 | if (msrpm_offsets[i] == 0xffffffff) |
2912 | break; | |
3d6368ef | 2913 | |
0d6b3537 JR |
2914 | p = msrpm_offsets[i]; |
2915 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 | 2916 | |
54bf36aa | 2917 | if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4)) |
323c3d80 JR |
2918 | return false; |
2919 | ||
2920 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
2921 | } | |
3d6368ef | 2922 | |
d0ec49d4 | 2923 | svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm)); |
9738b2c9 JR |
2924 | |
2925 | return true; | |
3d6368ef AG |
2926 | } |
2927 | ||
52c65a30 JR |
2928 | static bool nested_vmcb_checks(struct vmcb *vmcb) |
2929 | { | |
2930 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
2931 | return false; | |
2932 | ||
dbe77584 JR |
2933 | if (vmcb->control.asid == 0) |
2934 | return false; | |
2935 | ||
4b16184c JR |
2936 | if (vmcb->control.nested_ctl && !npt_enabled) |
2937 | return false; | |
2938 | ||
52c65a30 JR |
2939 | return true; |
2940 | } | |
2941 | ||
c2634065 LP |
2942 | static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa, |
2943 | struct vmcb *nested_vmcb, struct page *page) | |
3d6368ef | 2944 | { |
f6e78475 | 2945 | if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF) |
3d6368ef AG |
2946 | svm->vcpu.arch.hflags |= HF_HIF_MASK; |
2947 | else | |
2948 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
2949 | ||
4b16184c JR |
2950 | if (nested_vmcb->control.nested_ctl) { |
2951 | kvm_mmu_unload(&svm->vcpu); | |
2952 | svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; | |
2953 | nested_svm_init_mmu_context(&svm->vcpu); | |
2954 | } | |
2955 | ||
3d6368ef AG |
2956 | /* Load the nested guest state */ |
2957 | svm->vmcb->save.es = nested_vmcb->save.es; | |
2958 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
2959 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
2960 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
2961 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
2962 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
f6e78475 | 2963 | kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags); |
3d6368ef AG |
2964 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); |
2965 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
2966 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
2967 | if (npt_enabled) { | |
2968 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
2969 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 2970 | } else |
2390218b | 2971 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
2972 | |
2973 | /* Guest paging mode is active - reset mmu */ | |
2974 | kvm_mmu_reset_context(&svm->vcpu); | |
2975 | ||
defbba56 | 2976 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
2977 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
2978 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
2979 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
e0231715 | 2980 | |
3d6368ef AG |
2981 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
2982 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
2983 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
2984 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
2985 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
2986 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
2987 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
2988 | ||
f7138538 | 2989 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 2990 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 2991 | |
aad42c64 | 2992 | /* cache intercepts */ |
4ee546b4 | 2993 | svm->nested.intercept_cr = nested_vmcb->control.intercept_cr; |
3aed041a | 2994 | svm->nested.intercept_dr = nested_vmcb->control.intercept_dr; |
aad42c64 JR |
2995 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; |
2996 | svm->nested.intercept = nested_vmcb->control.intercept; | |
2997 | ||
f40f6a45 | 2998 | svm_flush_tlb(&svm->vcpu); |
3d6368ef | 2999 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
3000 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
3001 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
3002 | else | |
3003 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
3004 | ||
88ab24ad JR |
3005 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
3006 | /* We only want the cr8 intercept bits of the guest */ | |
4ee546b4 RJ |
3007 | clr_cr_intercept(svm, INTERCEPT_CR8_READ); |
3008 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
88ab24ad JR |
3009 | } |
3010 | ||
0d945bd9 | 3011 | /* We don't want to see VMMCALLs from a nested guest */ |
8a05a1b8 | 3012 | clr_intercept(svm, INTERCEPT_VMMCALL); |
0d945bd9 | 3013 | |
0dc92119 | 3014 | svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext; |
3d6368ef AG |
3015 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
3016 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
3017 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
3018 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
3019 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
3020 | ||
7597f129 | 3021 | nested_svm_unmap(page); |
9738b2c9 | 3022 | |
2030753d JR |
3023 | /* Enter Guest-Mode */ |
3024 | enter_guest_mode(&svm->vcpu); | |
3025 | ||
384c6368 JR |
3026 | /* |
3027 | * Merge guest and host intercepts - must be called with vcpu in | |
3028 | * guest-mode to take affect here | |
3029 | */ | |
3030 | recalc_intercepts(svm); | |
3031 | ||
06fc7772 | 3032 | svm->nested.vmcb = vmcb_gpa; |
9738b2c9 | 3033 | |
2af9194d | 3034 | enable_gif(svm); |
3d6368ef | 3035 | |
8d28fec4 | 3036 | mark_all_dirty(svm->vmcb); |
c2634065 LP |
3037 | } |
3038 | ||
3039 | static bool nested_svm_vmrun(struct vcpu_svm *svm) | |
3040 | { | |
3041 | struct vmcb *nested_vmcb; | |
3042 | struct vmcb *hsave = svm->nested.hsave; | |
3043 | struct vmcb *vmcb = svm->vmcb; | |
3044 | struct page *page; | |
3045 | u64 vmcb_gpa; | |
3046 | ||
3047 | vmcb_gpa = svm->vmcb->save.rax; | |
3048 | ||
3049 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); | |
3050 | if (!nested_vmcb) | |
3051 | return false; | |
3052 | ||
3053 | if (!nested_vmcb_checks(nested_vmcb)) { | |
3054 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
3055 | nested_vmcb->control.exit_code_hi = 0; | |
3056 | nested_vmcb->control.exit_info_1 = 0; | |
3057 | nested_vmcb->control.exit_info_2 = 0; | |
3058 | ||
3059 | nested_svm_unmap(page); | |
3060 | ||
3061 | return false; | |
3062 | } | |
3063 | ||
3064 | trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa, | |
3065 | nested_vmcb->save.rip, | |
3066 | nested_vmcb->control.int_ctl, | |
3067 | nested_vmcb->control.event_inj, | |
3068 | nested_vmcb->control.nested_ctl); | |
3069 | ||
3070 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, | |
3071 | nested_vmcb->control.intercept_cr >> 16, | |
3072 | nested_vmcb->control.intercept_exceptions, | |
3073 | nested_vmcb->control.intercept); | |
3074 | ||
3075 | /* Clear internal status */ | |
3076 | kvm_clear_exception_queue(&svm->vcpu); | |
3077 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3078 | ||
3079 | /* | |
3080 | * Save the old vmcb, so we don't need to pick what we save, but can | |
3081 | * restore everything when a VMEXIT occurs | |
3082 | */ | |
3083 | hsave->save.es = vmcb->save.es; | |
3084 | hsave->save.cs = vmcb->save.cs; | |
3085 | hsave->save.ss = vmcb->save.ss; | |
3086 | hsave->save.ds = vmcb->save.ds; | |
3087 | hsave->save.gdtr = vmcb->save.gdtr; | |
3088 | hsave->save.idtr = vmcb->save.idtr; | |
3089 | hsave->save.efer = svm->vcpu.arch.efer; | |
3090 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); | |
3091 | hsave->save.cr4 = svm->vcpu.arch.cr4; | |
3092 | hsave->save.rflags = kvm_get_rflags(&svm->vcpu); | |
3093 | hsave->save.rip = kvm_rip_read(&svm->vcpu); | |
3094 | hsave->save.rsp = vmcb->save.rsp; | |
3095 | hsave->save.rax = vmcb->save.rax; | |
3096 | if (npt_enabled) | |
3097 | hsave->save.cr3 = vmcb->save.cr3; | |
3098 | else | |
3099 | hsave->save.cr3 = kvm_read_cr3(&svm->vcpu); | |
3100 | ||
3101 | copy_vmcb_control_area(hsave, vmcb); | |
3102 | ||
3103 | enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, page); | |
8d28fec4 | 3104 | |
9738b2c9 | 3105 | return true; |
3d6368ef AG |
3106 | } |
3107 | ||
9966bf68 | 3108 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
3109 | { |
3110 | to_vmcb->save.fs = from_vmcb->save.fs; | |
3111 | to_vmcb->save.gs = from_vmcb->save.gs; | |
3112 | to_vmcb->save.tr = from_vmcb->save.tr; | |
3113 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
3114 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
3115 | to_vmcb->save.star = from_vmcb->save.star; | |
3116 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
3117 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
3118 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
3119 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
3120 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
3121 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
3122 | } |
3123 | ||
851ba692 | 3124 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 3125 | { |
9966bf68 | 3126 | struct vmcb *nested_vmcb; |
7597f129 | 3127 | struct page *page; |
b742c1e6 | 3128 | int ret; |
9966bf68 | 3129 | |
5542675b AG |
3130 | if (nested_svm_check_permissions(svm)) |
3131 | return 1; | |
3132 | ||
7597f129 | 3133 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
3134 | if (!nested_vmcb) |
3135 | return 1; | |
3136 | ||
e3e9ed3d | 3137 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
b742c1e6 | 3138 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
e3e9ed3d | 3139 | |
9966bf68 | 3140 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); |
7597f129 | 3141 | nested_svm_unmap(page); |
5542675b | 3142 | |
b742c1e6 | 3143 | return ret; |
5542675b AG |
3144 | } |
3145 | ||
851ba692 | 3146 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 3147 | { |
9966bf68 | 3148 | struct vmcb *nested_vmcb; |
7597f129 | 3149 | struct page *page; |
b742c1e6 | 3150 | int ret; |
9966bf68 | 3151 | |
5542675b AG |
3152 | if (nested_svm_check_permissions(svm)) |
3153 | return 1; | |
3154 | ||
7597f129 | 3155 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
3156 | if (!nested_vmcb) |
3157 | return 1; | |
3158 | ||
e3e9ed3d | 3159 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
b742c1e6 | 3160 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
e3e9ed3d | 3161 | |
9966bf68 | 3162 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); |
7597f129 | 3163 | nested_svm_unmap(page); |
5542675b | 3164 | |
b742c1e6 | 3165 | return ret; |
5542675b AG |
3166 | } |
3167 | ||
851ba692 | 3168 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 3169 | { |
3d6368ef AG |
3170 | if (nested_svm_check_permissions(svm)) |
3171 | return 1; | |
3172 | ||
b75f4eb3 RJ |
3173 | /* Save rip after vmrun instruction */ |
3174 | kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3); | |
3d6368ef | 3175 | |
9738b2c9 | 3176 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
3177 | return 1; |
3178 | ||
9738b2c9 | 3179 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
3180 | goto failed; |
3181 | ||
3182 | return 1; | |
3183 | ||
3184 | failed: | |
3185 | ||
3186 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
3187 | svm->vmcb->control.exit_code_hi = 0; | |
3188 | svm->vmcb->control.exit_info_1 = 0; | |
3189 | svm->vmcb->control.exit_info_2 = 0; | |
3190 | ||
3191 | nested_svm_vmexit(svm); | |
3d6368ef AG |
3192 | |
3193 | return 1; | |
3194 | } | |
3195 | ||
851ba692 | 3196 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 | 3197 | { |
b742c1e6 LP |
3198 | int ret; |
3199 | ||
1371d904 AG |
3200 | if (nested_svm_check_permissions(svm)) |
3201 | return 1; | |
3202 | ||
640bd6e5 JN |
3203 | /* |
3204 | * If VGIF is enabled, the STGI intercept is only added to | |
cc3d967f | 3205 | * detect the opening of the SMI/NMI window; remove it now. |
640bd6e5 JN |
3206 | */ |
3207 | if (vgif_enabled(svm)) | |
3208 | clr_intercept(svm, INTERCEPT_STGI); | |
3209 | ||
1371d904 | 3210 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
b742c1e6 | 3211 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
3842d135 | 3212 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
1371d904 | 3213 | |
2af9194d | 3214 | enable_gif(svm); |
1371d904 | 3215 | |
b742c1e6 | 3216 | return ret; |
1371d904 AG |
3217 | } |
3218 | ||
851ba692 | 3219 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 | 3220 | { |
b742c1e6 LP |
3221 | int ret; |
3222 | ||
1371d904 AG |
3223 | if (nested_svm_check_permissions(svm)) |
3224 | return 1; | |
3225 | ||
3226 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
b742c1e6 | 3227 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
1371d904 | 3228 | |
2af9194d | 3229 | disable_gif(svm); |
1371d904 AG |
3230 | |
3231 | /* After a CLGI no interrupts should come */ | |
340d3bc3 SS |
3232 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) { |
3233 | svm_clear_vintr(svm); | |
3234 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
3235 | mark_dirty(svm->vmcb, VMCB_INTR); | |
3236 | } | |
decdbf6a | 3237 | |
b742c1e6 | 3238 | return ret; |
1371d904 AG |
3239 | } |
3240 | ||
851ba692 | 3241 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
3242 | { |
3243 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 3244 | |
668f198f DK |
3245 | trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX), |
3246 | kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); | |
ec1ff790 | 3247 | |
ff092385 | 3248 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
668f198f | 3249 | kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); |
ff092385 AG |
3250 | |
3251 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
b742c1e6 | 3252 | return kvm_skip_emulated_instruction(&svm->vcpu); |
ff092385 AG |
3253 | } |
3254 | ||
532a46b9 JR |
3255 | static int skinit_interception(struct vcpu_svm *svm) |
3256 | { | |
668f198f | 3257 | trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); |
532a46b9 JR |
3258 | |
3259 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3260 | return 1; | |
3261 | } | |
3262 | ||
dab429a7 DK |
3263 | static int wbinvd_interception(struct vcpu_svm *svm) |
3264 | { | |
6affcbed | 3265 | return kvm_emulate_wbinvd(&svm->vcpu); |
dab429a7 DK |
3266 | } |
3267 | ||
81dd35d4 JR |
3268 | static int xsetbv_interception(struct vcpu_svm *svm) |
3269 | { | |
3270 | u64 new_bv = kvm_read_edx_eax(&svm->vcpu); | |
3271 | u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); | |
3272 | ||
3273 | if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) { | |
3274 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
b742c1e6 | 3275 | return kvm_skip_emulated_instruction(&svm->vcpu); |
81dd35d4 JR |
3276 | } |
3277 | ||
3278 | return 1; | |
3279 | } | |
3280 | ||
851ba692 | 3281 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 3282 | { |
37817f29 | 3283 | u16 tss_selector; |
64a7ec06 GN |
3284 | int reason; |
3285 | int int_type = svm->vmcb->control.exit_int_info & | |
3286 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 3287 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
3288 | uint32_t type = |
3289 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
3290 | uint32_t idt_v = | |
3291 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
3292 | bool has_error_code = false; |
3293 | u32 error_code = 0; | |
37817f29 IE |
3294 | |
3295 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 3296 | |
37817f29 IE |
3297 | if (svm->vmcb->control.exit_info_2 & |
3298 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
3299 | reason = TASK_SWITCH_IRET; |
3300 | else if (svm->vmcb->control.exit_info_2 & | |
3301 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
3302 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 3303 | else if (idt_v) |
64a7ec06 GN |
3304 | reason = TASK_SWITCH_GATE; |
3305 | else | |
3306 | reason = TASK_SWITCH_CALL; | |
3307 | ||
fe8e7f83 GN |
3308 | if (reason == TASK_SWITCH_GATE) { |
3309 | switch (type) { | |
3310 | case SVM_EXITINTINFO_TYPE_NMI: | |
3311 | svm->vcpu.arch.nmi_injected = false; | |
3312 | break; | |
3313 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
3314 | if (svm->vmcb->control.exit_info_2 & |
3315 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
3316 | has_error_code = true; | |
3317 | error_code = | |
3318 | (u32)svm->vmcb->control.exit_info_2; | |
3319 | } | |
fe8e7f83 GN |
3320 | kvm_clear_exception_queue(&svm->vcpu); |
3321 | break; | |
3322 | case SVM_EXITINTINFO_TYPE_INTR: | |
3323 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3324 | break; | |
3325 | default: | |
3326 | break; | |
3327 | } | |
3328 | } | |
64a7ec06 | 3329 | |
8317c298 GN |
3330 | if (reason != TASK_SWITCH_GATE || |
3331 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
3332 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
3333 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
3334 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 | 3335 | |
7f3d35fd KW |
3336 | if (int_type != SVM_EXITINTINFO_TYPE_SOFT) |
3337 | int_vec = -1; | |
3338 | ||
3339 | if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason, | |
acb54517 GN |
3340 | has_error_code, error_code) == EMULATE_FAIL) { |
3341 | svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
3342 | svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
3343 | svm->vcpu.run->internal.ndata = 0; | |
3344 | return 0; | |
3345 | } | |
3346 | return 1; | |
6aa8b732 AK |
3347 | } |
3348 | ||
851ba692 | 3349 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 3350 | { |
5fdbf976 | 3351 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
6a908b62 | 3352 | return kvm_emulate_cpuid(&svm->vcpu); |
6aa8b732 AK |
3353 | } |
3354 | ||
851ba692 | 3355 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
3356 | { |
3357 | ++svm->vcpu.stat.nmi_window_exits; | |
8a05a1b8 | 3358 | clr_intercept(svm, INTERCEPT_IRET); |
44c11430 | 3359 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
bd3d1ec3 | 3360 | svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu); |
f303b4ce | 3361 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
95ba8273 GN |
3362 | return 1; |
3363 | } | |
3364 | ||
851ba692 | 3365 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 3366 | { |
df4f3108 AP |
3367 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) |
3368 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; | |
3369 | ||
3370 | kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1); | |
b742c1e6 | 3371 | return kvm_skip_emulated_instruction(&svm->vcpu); |
a7052897 MT |
3372 | } |
3373 | ||
851ba692 | 3374 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 3375 | { |
51d8b661 | 3376 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; |
6aa8b732 AK |
3377 | } |
3378 | ||
332b56e4 AK |
3379 | static int rdpmc_interception(struct vcpu_svm *svm) |
3380 | { | |
3381 | int err; | |
3382 | ||
3383 | if (!static_cpu_has(X86_FEATURE_NRIPS)) | |
3384 | return emulate_on_interception(svm); | |
3385 | ||
3386 | err = kvm_rdpmc(&svm->vcpu); | |
6affcbed | 3387 | return kvm_complete_insn_gp(&svm->vcpu, err); |
332b56e4 AK |
3388 | } |
3389 | ||
52eb5a6d XL |
3390 | static bool check_selective_cr0_intercepted(struct vcpu_svm *svm, |
3391 | unsigned long val) | |
628afd2a JR |
3392 | { |
3393 | unsigned long cr0 = svm->vcpu.arch.cr0; | |
3394 | bool ret = false; | |
3395 | u64 intercept; | |
3396 | ||
3397 | intercept = svm->nested.intercept; | |
3398 | ||
3399 | if (!is_guest_mode(&svm->vcpu) || | |
3400 | (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))) | |
3401 | return false; | |
3402 | ||
3403 | cr0 &= ~SVM_CR0_SELECTIVE_MASK; | |
3404 | val &= ~SVM_CR0_SELECTIVE_MASK; | |
3405 | ||
3406 | if (cr0 ^ val) { | |
3407 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
3408 | ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE); | |
3409 | } | |
3410 | ||
3411 | return ret; | |
3412 | } | |
3413 | ||
7ff76d58 AP |
3414 | #define CR_VALID (1ULL << 63) |
3415 | ||
3416 | static int cr_interception(struct vcpu_svm *svm) | |
3417 | { | |
3418 | int reg, cr; | |
3419 | unsigned long val; | |
3420 | int err; | |
3421 | ||
3422 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
3423 | return emulate_on_interception(svm); | |
3424 | ||
3425 | if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) | |
3426 | return emulate_on_interception(svm); | |
3427 | ||
3428 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
5e57518d DK |
3429 | if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE) |
3430 | cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0; | |
3431 | else | |
3432 | cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0; | |
7ff76d58 AP |
3433 | |
3434 | err = 0; | |
3435 | if (cr >= 16) { /* mov to cr */ | |
3436 | cr -= 16; | |
3437 | val = kvm_register_read(&svm->vcpu, reg); | |
3438 | switch (cr) { | |
3439 | case 0: | |
628afd2a JR |
3440 | if (!check_selective_cr0_intercepted(svm, val)) |
3441 | err = kvm_set_cr0(&svm->vcpu, val); | |
977b2d03 JR |
3442 | else |
3443 | return 1; | |
3444 | ||
7ff76d58 AP |
3445 | break; |
3446 | case 3: | |
3447 | err = kvm_set_cr3(&svm->vcpu, val); | |
3448 | break; | |
3449 | case 4: | |
3450 | err = kvm_set_cr4(&svm->vcpu, val); | |
3451 | break; | |
3452 | case 8: | |
3453 | err = kvm_set_cr8(&svm->vcpu, val); | |
3454 | break; | |
3455 | default: | |
3456 | WARN(1, "unhandled write to CR%d", cr); | |
3457 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3458 | return 1; | |
3459 | } | |
3460 | } else { /* mov from cr */ | |
3461 | switch (cr) { | |
3462 | case 0: | |
3463 | val = kvm_read_cr0(&svm->vcpu); | |
3464 | break; | |
3465 | case 2: | |
3466 | val = svm->vcpu.arch.cr2; | |
3467 | break; | |
3468 | case 3: | |
9f8fe504 | 3469 | val = kvm_read_cr3(&svm->vcpu); |
7ff76d58 AP |
3470 | break; |
3471 | case 4: | |
3472 | val = kvm_read_cr4(&svm->vcpu); | |
3473 | break; | |
3474 | case 8: | |
3475 | val = kvm_get_cr8(&svm->vcpu); | |
3476 | break; | |
3477 | default: | |
3478 | WARN(1, "unhandled read from CR%d", cr); | |
3479 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3480 | return 1; | |
3481 | } | |
3482 | kvm_register_write(&svm->vcpu, reg, val); | |
3483 | } | |
6affcbed | 3484 | return kvm_complete_insn_gp(&svm->vcpu, err); |
7ff76d58 AP |
3485 | } |
3486 | ||
cae3797a AP |
3487 | static int dr_interception(struct vcpu_svm *svm) |
3488 | { | |
3489 | int reg, dr; | |
3490 | unsigned long val; | |
cae3797a | 3491 | |
facb0139 PB |
3492 | if (svm->vcpu.guest_debug == 0) { |
3493 | /* | |
3494 | * No more DR vmexits; force a reload of the debug registers | |
3495 | * and reenter on this instruction. The next vmexit will | |
3496 | * retrieve the full state of the debug registers. | |
3497 | */ | |
3498 | clr_dr_intercepts(svm); | |
3499 | svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
3500 | return 1; | |
3501 | } | |
3502 | ||
cae3797a AP |
3503 | if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS)) |
3504 | return emulate_on_interception(svm); | |
3505 | ||
3506 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
3507 | dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0; | |
3508 | ||
3509 | if (dr >= 16) { /* mov to DRn */ | |
16f8a6f9 NA |
3510 | if (!kvm_require_dr(&svm->vcpu, dr - 16)) |
3511 | return 1; | |
cae3797a AP |
3512 | val = kvm_register_read(&svm->vcpu, reg); |
3513 | kvm_set_dr(&svm->vcpu, dr - 16, val); | |
3514 | } else { | |
16f8a6f9 NA |
3515 | if (!kvm_require_dr(&svm->vcpu, dr)) |
3516 | return 1; | |
3517 | kvm_get_dr(&svm->vcpu, dr, &val); | |
3518 | kvm_register_write(&svm->vcpu, reg, val); | |
cae3797a AP |
3519 | } |
3520 | ||
b742c1e6 | 3521 | return kvm_skip_emulated_instruction(&svm->vcpu); |
cae3797a AP |
3522 | } |
3523 | ||
851ba692 | 3524 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 3525 | { |
851ba692 | 3526 | struct kvm_run *kvm_run = svm->vcpu.run; |
eea1cff9 | 3527 | int r; |
851ba692 | 3528 | |
0a5fff19 GN |
3529 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
3530 | /* instruction emulation calls kvm_set_cr8() */ | |
7ff76d58 | 3531 | r = cr_interception(svm); |
35754c98 | 3532 | if (lapic_in_kernel(&svm->vcpu)) |
7ff76d58 | 3533 | return r; |
0a5fff19 | 3534 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
7ff76d58 | 3535 | return r; |
1d075434 JR |
3536 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
3537 | return 0; | |
3538 | } | |
3539 | ||
609e36d3 | 3540 | static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3541 | { |
a2fa3e9f GH |
3542 | struct vcpu_svm *svm = to_svm(vcpu); |
3543 | ||
609e36d3 | 3544 | switch (msr_info->index) { |
af24a4e4 | 3545 | case MSR_IA32_TSC: { |
609e36d3 | 3546 | msr_info->data = svm->vmcb->control.tsc_offset + |
35181e86 | 3547 | kvm_scale_tsc(vcpu, rdtsc()); |
fbc0db76 | 3548 | |
6aa8b732 AK |
3549 | break; |
3550 | } | |
8c06585d | 3551 | case MSR_STAR: |
609e36d3 | 3552 | msr_info->data = svm->vmcb->save.star; |
6aa8b732 | 3553 | break; |
0e859cac | 3554 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3555 | case MSR_LSTAR: |
609e36d3 | 3556 | msr_info->data = svm->vmcb->save.lstar; |
6aa8b732 AK |
3557 | break; |
3558 | case MSR_CSTAR: | |
609e36d3 | 3559 | msr_info->data = svm->vmcb->save.cstar; |
6aa8b732 AK |
3560 | break; |
3561 | case MSR_KERNEL_GS_BASE: | |
609e36d3 | 3562 | msr_info->data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
3563 | break; |
3564 | case MSR_SYSCALL_MASK: | |
609e36d3 | 3565 | msr_info->data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
3566 | break; |
3567 | #endif | |
3568 | case MSR_IA32_SYSENTER_CS: | |
609e36d3 | 3569 | msr_info->data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
3570 | break; |
3571 | case MSR_IA32_SYSENTER_EIP: | |
609e36d3 | 3572 | msr_info->data = svm->sysenter_eip; |
6aa8b732 AK |
3573 | break; |
3574 | case MSR_IA32_SYSENTER_ESP: | |
609e36d3 | 3575 | msr_info->data = svm->sysenter_esp; |
6aa8b732 | 3576 | break; |
46896c73 PB |
3577 | case MSR_TSC_AUX: |
3578 | if (!boot_cpu_has(X86_FEATURE_RDTSCP)) | |
3579 | return 1; | |
3580 | msr_info->data = svm->tsc_aux; | |
3581 | break; | |
e0231715 JR |
3582 | /* |
3583 | * Nobody will change the following 5 values in the VMCB so we can | |
3584 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
3585 | * implemented. | |
3586 | */ | |
a2938c80 | 3587 | case MSR_IA32_DEBUGCTLMSR: |
609e36d3 | 3588 | msr_info->data = svm->vmcb->save.dbgctl; |
a2938c80 JR |
3589 | break; |
3590 | case MSR_IA32_LASTBRANCHFROMIP: | |
609e36d3 | 3591 | msr_info->data = svm->vmcb->save.br_from; |
a2938c80 JR |
3592 | break; |
3593 | case MSR_IA32_LASTBRANCHTOIP: | |
609e36d3 | 3594 | msr_info->data = svm->vmcb->save.br_to; |
a2938c80 JR |
3595 | break; |
3596 | case MSR_IA32_LASTINTFROMIP: | |
609e36d3 | 3597 | msr_info->data = svm->vmcb->save.last_excp_from; |
a2938c80 JR |
3598 | break; |
3599 | case MSR_IA32_LASTINTTOIP: | |
609e36d3 | 3600 | msr_info->data = svm->vmcb->save.last_excp_to; |
a2938c80 | 3601 | break; |
b286d5d8 | 3602 | case MSR_VM_HSAVE_PA: |
609e36d3 | 3603 | msr_info->data = svm->nested.hsave_msr; |
b286d5d8 | 3604 | break; |
eb6f302e | 3605 | case MSR_VM_CR: |
609e36d3 | 3606 | msr_info->data = svm->nested.vm_cr_msr; |
eb6f302e | 3607 | break; |
c8a73f18 | 3608 | case MSR_IA32_UCODE_REV: |
609e36d3 | 3609 | msr_info->data = 0x01000065; |
c8a73f18 | 3610 | break; |
ae8b7875 BP |
3611 | case MSR_F15H_IC_CFG: { |
3612 | ||
3613 | int family, model; | |
3614 | ||
3615 | family = guest_cpuid_family(vcpu); | |
3616 | model = guest_cpuid_model(vcpu); | |
3617 | ||
3618 | if (family < 0 || model < 0) | |
3619 | return kvm_get_msr_common(vcpu, msr_info); | |
3620 | ||
3621 | msr_info->data = 0; | |
3622 | ||
3623 | if (family == 0x15 && | |
3624 | (model >= 0x2 && model < 0x20)) | |
3625 | msr_info->data = 0x1E; | |
3626 | } | |
3627 | break; | |
6aa8b732 | 3628 | default: |
609e36d3 | 3629 | return kvm_get_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3630 | } |
3631 | return 0; | |
3632 | } | |
3633 | ||
851ba692 | 3634 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3635 | { |
668f198f | 3636 | u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); |
609e36d3 | 3637 | struct msr_data msr_info; |
6aa8b732 | 3638 | |
609e36d3 PB |
3639 | msr_info.index = ecx; |
3640 | msr_info.host_initiated = false; | |
3641 | if (svm_get_msr(&svm->vcpu, &msr_info)) { | |
59200273 | 3642 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 3643 | kvm_inject_gp(&svm->vcpu, 0); |
b742c1e6 | 3644 | return 1; |
59200273 | 3645 | } else { |
609e36d3 | 3646 | trace_kvm_msr_read(ecx, msr_info.data); |
af9ca2d7 | 3647 | |
609e36d3 PB |
3648 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, |
3649 | msr_info.data & 0xffffffff); | |
3650 | kvm_register_write(&svm->vcpu, VCPU_REGS_RDX, | |
3651 | msr_info.data >> 32); | |
5fdbf976 | 3652 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
b742c1e6 | 3653 | return kvm_skip_emulated_instruction(&svm->vcpu); |
6aa8b732 | 3654 | } |
6aa8b732 AK |
3655 | } |
3656 | ||
4a810181 JR |
3657 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
3658 | { | |
3659 | struct vcpu_svm *svm = to_svm(vcpu); | |
3660 | int svm_dis, chg_mask; | |
3661 | ||
3662 | if (data & ~SVM_VM_CR_VALID_MASK) | |
3663 | return 1; | |
3664 | ||
3665 | chg_mask = SVM_VM_CR_VALID_MASK; | |
3666 | ||
3667 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
3668 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
3669 | ||
3670 | svm->nested.vm_cr_msr &= ~chg_mask; | |
3671 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
3672 | ||
3673 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
3674 | ||
3675 | /* check for svm_disable while efer.svme is set */ | |
3676 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
3677 | return 1; | |
3678 | ||
3679 | return 0; | |
3680 | } | |
3681 | ||
8fe8ab46 | 3682 | static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
6aa8b732 | 3683 | { |
a2fa3e9f GH |
3684 | struct vcpu_svm *svm = to_svm(vcpu); |
3685 | ||
8fe8ab46 WA |
3686 | u32 ecx = msr->index; |
3687 | u64 data = msr->data; | |
6aa8b732 | 3688 | switch (ecx) { |
15038e14 PB |
3689 | case MSR_IA32_CR_PAT: |
3690 | if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data)) | |
3691 | return 1; | |
3692 | vcpu->arch.pat = data; | |
3693 | svm->vmcb->save.g_pat = data; | |
3694 | mark_dirty(svm->vmcb, VMCB_NPT); | |
3695 | break; | |
f4e1b3c8 | 3696 | case MSR_IA32_TSC: |
8fe8ab46 | 3697 | kvm_write_tsc(vcpu, msr); |
6aa8b732 | 3698 | break; |
15d45071 AR |
3699 | case MSR_IA32_PRED_CMD: |
3700 | if (!msr->host_initiated && | |
3701 | !guest_cpuid_has(vcpu, X86_FEATURE_IBPB)) | |
3702 | return 1; | |
3703 | ||
3704 | if (data & ~PRED_CMD_IBPB) | |
3705 | return 1; | |
3706 | ||
3707 | if (!data) | |
3708 | break; | |
3709 | ||
3710 | wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); | |
3711 | if (is_guest_mode(vcpu)) | |
3712 | break; | |
3713 | set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1); | |
3714 | break; | |
8c06585d | 3715 | case MSR_STAR: |
a2fa3e9f | 3716 | svm->vmcb->save.star = data; |
6aa8b732 | 3717 | break; |
49b14f24 | 3718 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3719 | case MSR_LSTAR: |
a2fa3e9f | 3720 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
3721 | break; |
3722 | case MSR_CSTAR: | |
a2fa3e9f | 3723 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
3724 | break; |
3725 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 3726 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
3727 | break; |
3728 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 3729 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
3730 | break; |
3731 | #endif | |
3732 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 3733 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
3734 | break; |
3735 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 3736 | svm->sysenter_eip = data; |
a2fa3e9f | 3737 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
3738 | break; |
3739 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 3740 | svm->sysenter_esp = data; |
a2fa3e9f | 3741 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 3742 | break; |
46896c73 PB |
3743 | case MSR_TSC_AUX: |
3744 | if (!boot_cpu_has(X86_FEATURE_RDTSCP)) | |
3745 | return 1; | |
3746 | ||
3747 | /* | |
3748 | * This is rare, so we update the MSR here instead of using | |
3749 | * direct_access_msrs. Doing that would require a rdmsr in | |
3750 | * svm_vcpu_put. | |
3751 | */ | |
3752 | svm->tsc_aux = data; | |
3753 | wrmsrl(MSR_TSC_AUX, svm->tsc_aux); | |
3754 | break; | |
a2938c80 | 3755 | case MSR_IA32_DEBUGCTLMSR: |
2a6b20b8 | 3756 | if (!boot_cpu_has(X86_FEATURE_LBRV)) { |
a737f256 CD |
3757 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", |
3758 | __func__, data); | |
24e09cbf JR |
3759 | break; |
3760 | } | |
3761 | if (data & DEBUGCTL_RESERVED_BITS) | |
3762 | return 1; | |
3763 | ||
3764 | svm->vmcb->save.dbgctl = data; | |
b53ba3f9 | 3765 | mark_dirty(svm->vmcb, VMCB_LBR); |
24e09cbf JR |
3766 | if (data & (1ULL<<0)) |
3767 | svm_enable_lbrv(svm); | |
3768 | else | |
3769 | svm_disable_lbrv(svm); | |
a2938c80 | 3770 | break; |
b286d5d8 | 3771 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 3772 | svm->nested.hsave_msr = data; |
62b9abaa | 3773 | break; |
3c5d0a44 | 3774 | case MSR_VM_CR: |
4a810181 | 3775 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 3776 | case MSR_VM_IGNNE: |
a737f256 | 3777 | vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
3c5d0a44 | 3778 | break; |
44a95dae SS |
3779 | case MSR_IA32_APICBASE: |
3780 | if (kvm_vcpu_apicv_active(vcpu)) | |
3781 | avic_update_vapic_bar(to_svm(vcpu), data); | |
3782 | /* Follow through */ | |
6aa8b732 | 3783 | default: |
8fe8ab46 | 3784 | return kvm_set_msr_common(vcpu, msr); |
6aa8b732 AK |
3785 | } |
3786 | return 0; | |
3787 | } | |
3788 | ||
851ba692 | 3789 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3790 | { |
8fe8ab46 | 3791 | struct msr_data msr; |
668f198f DK |
3792 | u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); |
3793 | u64 data = kvm_read_edx_eax(&svm->vcpu); | |
af9ca2d7 | 3794 | |
8fe8ab46 WA |
3795 | msr.data = data; |
3796 | msr.index = ecx; | |
3797 | msr.host_initiated = false; | |
af9ca2d7 | 3798 | |
5fdbf976 | 3799 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
854e8bb1 | 3800 | if (kvm_set_msr(&svm->vcpu, &msr)) { |
59200273 | 3801 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 3802 | kvm_inject_gp(&svm->vcpu, 0); |
b742c1e6 | 3803 | return 1; |
59200273 AK |
3804 | } else { |
3805 | trace_kvm_msr_write(ecx, data); | |
b742c1e6 | 3806 | return kvm_skip_emulated_instruction(&svm->vcpu); |
59200273 | 3807 | } |
6aa8b732 AK |
3808 | } |
3809 | ||
851ba692 | 3810 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3811 | { |
e756fc62 | 3812 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 3813 | return wrmsr_interception(svm); |
6aa8b732 | 3814 | else |
851ba692 | 3815 | return rdmsr_interception(svm); |
6aa8b732 AK |
3816 | } |
3817 | ||
851ba692 | 3818 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 3819 | { |
3842d135 | 3820 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
f0b85051 | 3821 | svm_clear_vintr(svm); |
85f455f7 | 3822 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
decdbf6a | 3823 | mark_dirty(svm->vmcb, VMCB_INTR); |
675acb75 | 3824 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
3825 | return 1; |
3826 | } | |
3827 | ||
565d0998 ML |
3828 | static int pause_interception(struct vcpu_svm *svm) |
3829 | { | |
de63ad4c LM |
3830 | struct kvm_vcpu *vcpu = &svm->vcpu; |
3831 | bool in_kernel = (svm_get_cpl(vcpu) == 0); | |
3832 | ||
3833 | kvm_vcpu_on_spin(vcpu, in_kernel); | |
565d0998 ML |
3834 | return 1; |
3835 | } | |
3836 | ||
87c00572 GS |
3837 | static int nop_interception(struct vcpu_svm *svm) |
3838 | { | |
b742c1e6 | 3839 | return kvm_skip_emulated_instruction(&(svm->vcpu)); |
87c00572 GS |
3840 | } |
3841 | ||
3842 | static int monitor_interception(struct vcpu_svm *svm) | |
3843 | { | |
3844 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
3845 | return nop_interception(svm); | |
3846 | } | |
3847 | ||
3848 | static int mwait_interception(struct vcpu_svm *svm) | |
3849 | { | |
3850 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
3851 | return nop_interception(svm); | |
3852 | } | |
3853 | ||
18f40c53 SS |
3854 | enum avic_ipi_failure_cause { |
3855 | AVIC_IPI_FAILURE_INVALID_INT_TYPE, | |
3856 | AVIC_IPI_FAILURE_TARGET_NOT_RUNNING, | |
3857 | AVIC_IPI_FAILURE_INVALID_TARGET, | |
3858 | AVIC_IPI_FAILURE_INVALID_BACKING_PAGE, | |
3859 | }; | |
3860 | ||
3861 | static int avic_incomplete_ipi_interception(struct vcpu_svm *svm) | |
3862 | { | |
3863 | u32 icrh = svm->vmcb->control.exit_info_1 >> 32; | |
3864 | u32 icrl = svm->vmcb->control.exit_info_1; | |
3865 | u32 id = svm->vmcb->control.exit_info_2 >> 32; | |
5446a979 | 3866 | u32 index = svm->vmcb->control.exit_info_2 & 0xFF; |
18f40c53 SS |
3867 | struct kvm_lapic *apic = svm->vcpu.arch.apic; |
3868 | ||
3869 | trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index); | |
3870 | ||
3871 | switch (id) { | |
3872 | case AVIC_IPI_FAILURE_INVALID_INT_TYPE: | |
3873 | /* | |
3874 | * AVIC hardware handles the generation of | |
3875 | * IPIs when the specified Message Type is Fixed | |
3876 | * (also known as fixed delivery mode) and | |
3877 | * the Trigger Mode is edge-triggered. The hardware | |
3878 | * also supports self and broadcast delivery modes | |
3879 | * specified via the Destination Shorthand(DSH) | |
3880 | * field of the ICRL. Logical and physical APIC ID | |
3881 | * formats are supported. All other IPI types cause | |
3882 | * a #VMEXIT, which needs to emulated. | |
3883 | */ | |
3884 | kvm_lapic_reg_write(apic, APIC_ICR2, icrh); | |
3885 | kvm_lapic_reg_write(apic, APIC_ICR, icrl); | |
3886 | break; | |
3887 | case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: { | |
3888 | int i; | |
3889 | struct kvm_vcpu *vcpu; | |
3890 | struct kvm *kvm = svm->vcpu.kvm; | |
3891 | struct kvm_lapic *apic = svm->vcpu.arch.apic; | |
3892 | ||
3893 | /* | |
3894 | * At this point, we expect that the AVIC HW has already | |
3895 | * set the appropriate IRR bits on the valid target | |
3896 | * vcpus. So, we just need to kick the appropriate vcpu. | |
3897 | */ | |
3898 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
3899 | bool m = kvm_apic_match_dest(vcpu, apic, | |
3900 | icrl & KVM_APIC_SHORT_MASK, | |
3901 | GET_APIC_DEST_FIELD(icrh), | |
3902 | icrl & KVM_APIC_DEST_MASK); | |
3903 | ||
3904 | if (m && !avic_vcpu_is_running(vcpu)) | |
3905 | kvm_vcpu_wake_up(vcpu); | |
3906 | } | |
3907 | break; | |
3908 | } | |
3909 | case AVIC_IPI_FAILURE_INVALID_TARGET: | |
3910 | break; | |
3911 | case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE: | |
3912 | WARN_ONCE(1, "Invalid backing page\n"); | |
3913 | break; | |
3914 | default: | |
3915 | pr_err("Unknown IPI interception\n"); | |
3916 | } | |
3917 | ||
3918 | return 1; | |
3919 | } | |
3920 | ||
3921 | static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat) | |
3922 | { | |
3923 | struct kvm_arch *vm_data = &vcpu->kvm->arch; | |
3924 | int index; | |
3925 | u32 *logical_apic_id_table; | |
3926 | int dlid = GET_APIC_LOGICAL_ID(ldr); | |
3927 | ||
3928 | if (!dlid) | |
3929 | return NULL; | |
3930 | ||
3931 | if (flat) { /* flat */ | |
3932 | index = ffs(dlid) - 1; | |
3933 | if (index > 7) | |
3934 | return NULL; | |
3935 | } else { /* cluster */ | |
3936 | int cluster = (dlid & 0xf0) >> 4; | |
3937 | int apic = ffs(dlid & 0x0f) - 1; | |
3938 | ||
3939 | if ((apic < 0) || (apic > 7) || | |
3940 | (cluster >= 0xf)) | |
3941 | return NULL; | |
3942 | index = (cluster << 2) + apic; | |
3943 | } | |
3944 | ||
3945 | logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page); | |
3946 | ||
3947 | return &logical_apic_id_table[index]; | |
3948 | } | |
3949 | ||
3950 | static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr, | |
3951 | bool valid) | |
3952 | { | |
3953 | bool flat; | |
3954 | u32 *entry, new_entry; | |
3955 | ||
3956 | flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT; | |
3957 | entry = avic_get_logical_id_entry(vcpu, ldr, flat); | |
3958 | if (!entry) | |
3959 | return -EINVAL; | |
3960 | ||
3961 | new_entry = READ_ONCE(*entry); | |
3962 | new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK; | |
3963 | new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK); | |
3964 | if (valid) | |
3965 | new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK; | |
3966 | else | |
3967 | new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK; | |
3968 | WRITE_ONCE(*entry, new_entry); | |
3969 | ||
3970 | return 0; | |
3971 | } | |
3972 | ||
3973 | static int avic_handle_ldr_update(struct kvm_vcpu *vcpu) | |
3974 | { | |
3975 | int ret; | |
3976 | struct vcpu_svm *svm = to_svm(vcpu); | |
3977 | u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR); | |
3978 | ||
3979 | if (!ldr) | |
3980 | return 1; | |
3981 | ||
3982 | ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true); | |
3983 | if (ret && svm->ldr_reg) { | |
3984 | avic_ldr_write(vcpu, 0, svm->ldr_reg, false); | |
3985 | svm->ldr_reg = 0; | |
3986 | } else { | |
3987 | svm->ldr_reg = ldr; | |
3988 | } | |
3989 | return ret; | |
3990 | } | |
3991 | ||
3992 | static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu) | |
3993 | { | |
3994 | u64 *old, *new; | |
3995 | struct vcpu_svm *svm = to_svm(vcpu); | |
3996 | u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID); | |
3997 | u32 id = (apic_id_reg >> 24) & 0xff; | |
3998 | ||
3999 | if (vcpu->vcpu_id == id) | |
4000 | return 0; | |
4001 | ||
4002 | old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id); | |
4003 | new = avic_get_physical_id_entry(vcpu, id); | |
4004 | if (!new || !old) | |
4005 | return 1; | |
4006 | ||
4007 | /* We need to move physical_id_entry to new offset */ | |
4008 | *new = *old; | |
4009 | *old = 0ULL; | |
4010 | to_svm(vcpu)->avic_physical_id_cache = new; | |
4011 | ||
4012 | /* | |
4013 | * Also update the guest physical APIC ID in the logical | |
4014 | * APIC ID table entry if already setup the LDR. | |
4015 | */ | |
4016 | if (svm->ldr_reg) | |
4017 | avic_handle_ldr_update(vcpu); | |
4018 | ||
4019 | return 0; | |
4020 | } | |
4021 | ||
4022 | static int avic_handle_dfr_update(struct kvm_vcpu *vcpu) | |
4023 | { | |
4024 | struct vcpu_svm *svm = to_svm(vcpu); | |
4025 | struct kvm_arch *vm_data = &vcpu->kvm->arch; | |
4026 | u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR); | |
4027 | u32 mod = (dfr >> 28) & 0xf; | |
4028 | ||
4029 | /* | |
4030 | * We assume that all local APICs are using the same type. | |
4031 | * If this changes, we need to flush the AVIC logical | |
4032 | * APID id table. | |
4033 | */ | |
4034 | if (vm_data->ldr_mode == mod) | |
4035 | return 0; | |
4036 | ||
4037 | clear_page(page_address(vm_data->avic_logical_id_table_page)); | |
4038 | vm_data->ldr_mode = mod; | |
4039 | ||
4040 | if (svm->ldr_reg) | |
4041 | avic_handle_ldr_update(vcpu); | |
4042 | return 0; | |
4043 | } | |
4044 | ||
4045 | static int avic_unaccel_trap_write(struct vcpu_svm *svm) | |
4046 | { | |
4047 | struct kvm_lapic *apic = svm->vcpu.arch.apic; | |
4048 | u32 offset = svm->vmcb->control.exit_info_1 & | |
4049 | AVIC_UNACCEL_ACCESS_OFFSET_MASK; | |
4050 | ||
4051 | switch (offset) { | |
4052 | case APIC_ID: | |
4053 | if (avic_handle_apic_id_update(&svm->vcpu)) | |
4054 | return 0; | |
4055 | break; | |
4056 | case APIC_LDR: | |
4057 | if (avic_handle_ldr_update(&svm->vcpu)) | |
4058 | return 0; | |
4059 | break; | |
4060 | case APIC_DFR: | |
4061 | avic_handle_dfr_update(&svm->vcpu); | |
4062 | break; | |
4063 | default: | |
4064 | break; | |
4065 | } | |
4066 | ||
4067 | kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset)); | |
4068 | ||
4069 | return 1; | |
4070 | } | |
4071 | ||
4072 | static bool is_avic_unaccelerated_access_trap(u32 offset) | |
4073 | { | |
4074 | bool ret = false; | |
4075 | ||
4076 | switch (offset) { | |
4077 | case APIC_ID: | |
4078 | case APIC_EOI: | |
4079 | case APIC_RRR: | |
4080 | case APIC_LDR: | |
4081 | case APIC_DFR: | |
4082 | case APIC_SPIV: | |
4083 | case APIC_ESR: | |
4084 | case APIC_ICR: | |
4085 | case APIC_LVTT: | |
4086 | case APIC_LVTTHMR: | |
4087 | case APIC_LVTPC: | |
4088 | case APIC_LVT0: | |
4089 | case APIC_LVT1: | |
4090 | case APIC_LVTERR: | |
4091 | case APIC_TMICT: | |
4092 | case APIC_TDCR: | |
4093 | ret = true; | |
4094 | break; | |
4095 | default: | |
4096 | break; | |
4097 | } | |
4098 | return ret; | |
4099 | } | |
4100 | ||
4101 | static int avic_unaccelerated_access_interception(struct vcpu_svm *svm) | |
4102 | { | |
4103 | int ret = 0; | |
4104 | u32 offset = svm->vmcb->control.exit_info_1 & | |
4105 | AVIC_UNACCEL_ACCESS_OFFSET_MASK; | |
4106 | u32 vector = svm->vmcb->control.exit_info_2 & | |
4107 | AVIC_UNACCEL_ACCESS_VECTOR_MASK; | |
4108 | bool write = (svm->vmcb->control.exit_info_1 >> 32) & | |
4109 | AVIC_UNACCEL_ACCESS_WRITE_MASK; | |
4110 | bool trap = is_avic_unaccelerated_access_trap(offset); | |
4111 | ||
4112 | trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset, | |
4113 | trap, write, vector); | |
4114 | if (trap) { | |
4115 | /* Handling Trap */ | |
4116 | WARN_ONCE(!write, "svm: Handling trap read.\n"); | |
4117 | ret = avic_unaccel_trap_write(svm); | |
4118 | } else { | |
4119 | /* Handling Fault */ | |
4120 | ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE); | |
4121 | } | |
4122 | ||
4123 | return ret; | |
4124 | } | |
4125 | ||
09941fbb | 4126 | static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = { |
7ff76d58 AP |
4127 | [SVM_EXIT_READ_CR0] = cr_interception, |
4128 | [SVM_EXIT_READ_CR3] = cr_interception, | |
4129 | [SVM_EXIT_READ_CR4] = cr_interception, | |
4130 | [SVM_EXIT_READ_CR8] = cr_interception, | |
5e57518d | 4131 | [SVM_EXIT_CR0_SEL_WRITE] = cr_interception, |
628afd2a | 4132 | [SVM_EXIT_WRITE_CR0] = cr_interception, |
7ff76d58 AP |
4133 | [SVM_EXIT_WRITE_CR3] = cr_interception, |
4134 | [SVM_EXIT_WRITE_CR4] = cr_interception, | |
e0231715 | 4135 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
cae3797a AP |
4136 | [SVM_EXIT_READ_DR0] = dr_interception, |
4137 | [SVM_EXIT_READ_DR1] = dr_interception, | |
4138 | [SVM_EXIT_READ_DR2] = dr_interception, | |
4139 | [SVM_EXIT_READ_DR3] = dr_interception, | |
4140 | [SVM_EXIT_READ_DR4] = dr_interception, | |
4141 | [SVM_EXIT_READ_DR5] = dr_interception, | |
4142 | [SVM_EXIT_READ_DR6] = dr_interception, | |
4143 | [SVM_EXIT_READ_DR7] = dr_interception, | |
4144 | [SVM_EXIT_WRITE_DR0] = dr_interception, | |
4145 | [SVM_EXIT_WRITE_DR1] = dr_interception, | |
4146 | [SVM_EXIT_WRITE_DR2] = dr_interception, | |
4147 | [SVM_EXIT_WRITE_DR3] = dr_interception, | |
4148 | [SVM_EXIT_WRITE_DR4] = dr_interception, | |
4149 | [SVM_EXIT_WRITE_DR5] = dr_interception, | |
4150 | [SVM_EXIT_WRITE_DR6] = dr_interception, | |
4151 | [SVM_EXIT_WRITE_DR7] = dr_interception, | |
d0bfb940 JK |
4152 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
4153 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 4154 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 | 4155 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
e0231715 | 4156 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, |
54a20552 | 4157 | [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception, |
e0231715 | 4158 | [SVM_EXIT_INTR] = intr_interception, |
c47f098d | 4159 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
4160 | [SVM_EXIT_SMI] = nop_on_interception, |
4161 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 4162 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
332b56e4 | 4163 | [SVM_EXIT_RDPMC] = rdpmc_interception, |
6aa8b732 | 4164 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 4165 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 4166 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 4167 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 4168 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 4169 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 4170 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 4171 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
4172 | [SVM_EXIT_MSR] = msr_interception, |
4173 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 4174 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 4175 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 4176 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
4177 | [SVM_EXIT_VMLOAD] = vmload_interception, |
4178 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
4179 | [SVM_EXIT_STGI] = stgi_interception, |
4180 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 4181 | [SVM_EXIT_SKINIT] = skinit_interception, |
dab429a7 | 4182 | [SVM_EXIT_WBINVD] = wbinvd_interception, |
87c00572 GS |
4183 | [SVM_EXIT_MONITOR] = monitor_interception, |
4184 | [SVM_EXIT_MWAIT] = mwait_interception, | |
81dd35d4 | 4185 | [SVM_EXIT_XSETBV] = xsetbv_interception, |
d0006530 | 4186 | [SVM_EXIT_NPF] = npf_interception, |
64d60670 | 4187 | [SVM_EXIT_RSM] = emulate_on_interception, |
18f40c53 SS |
4188 | [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception, |
4189 | [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception, | |
6aa8b732 AK |
4190 | }; |
4191 | ||
ae8cc059 | 4192 | static void dump_vmcb(struct kvm_vcpu *vcpu) |
3f10c846 JR |
4193 | { |
4194 | struct vcpu_svm *svm = to_svm(vcpu); | |
4195 | struct vmcb_control_area *control = &svm->vmcb->control; | |
4196 | struct vmcb_save_area *save = &svm->vmcb->save; | |
4197 | ||
4198 | pr_err("VMCB Control Area:\n"); | |
ae8cc059 JP |
4199 | pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff); |
4200 | pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16); | |
4201 | pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff); | |
4202 | pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16); | |
4203 | pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions); | |
4204 | pr_err("%-20s%016llx\n", "intercepts:", control->intercept); | |
4205 | pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count); | |
4206 | pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa); | |
4207 | pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa); | |
4208 | pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset); | |
4209 | pr_err("%-20s%d\n", "asid:", control->asid); | |
4210 | pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl); | |
4211 | pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl); | |
4212 | pr_err("%-20s%08x\n", "int_vector:", control->int_vector); | |
4213 | pr_err("%-20s%08x\n", "int_state:", control->int_state); | |
4214 | pr_err("%-20s%08x\n", "exit_code:", control->exit_code); | |
4215 | pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1); | |
4216 | pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2); | |
4217 | pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info); | |
4218 | pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err); | |
4219 | pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl); | |
4220 | pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3); | |
44a95dae | 4221 | pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar); |
ae8cc059 JP |
4222 | pr_err("%-20s%08x\n", "event_inj:", control->event_inj); |
4223 | pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err); | |
0dc92119 | 4224 | pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext); |
ae8cc059 | 4225 | pr_err("%-20s%016llx\n", "next_rip:", control->next_rip); |
44a95dae SS |
4226 | pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page); |
4227 | pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id); | |
4228 | pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id); | |
3f10c846 | 4229 | pr_err("VMCB State Save Area:\n"); |
ae8cc059 JP |
4230 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", |
4231 | "es:", | |
4232 | save->es.selector, save->es.attrib, | |
4233 | save->es.limit, save->es.base); | |
4234 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4235 | "cs:", | |
4236 | save->cs.selector, save->cs.attrib, | |
4237 | save->cs.limit, save->cs.base); | |
4238 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4239 | "ss:", | |
4240 | save->ss.selector, save->ss.attrib, | |
4241 | save->ss.limit, save->ss.base); | |
4242 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4243 | "ds:", | |
4244 | save->ds.selector, save->ds.attrib, | |
4245 | save->ds.limit, save->ds.base); | |
4246 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4247 | "fs:", | |
4248 | save->fs.selector, save->fs.attrib, | |
4249 | save->fs.limit, save->fs.base); | |
4250 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4251 | "gs:", | |
4252 | save->gs.selector, save->gs.attrib, | |
4253 | save->gs.limit, save->gs.base); | |
4254 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4255 | "gdtr:", | |
4256 | save->gdtr.selector, save->gdtr.attrib, | |
4257 | save->gdtr.limit, save->gdtr.base); | |
4258 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4259 | "ldtr:", | |
4260 | save->ldtr.selector, save->ldtr.attrib, | |
4261 | save->ldtr.limit, save->ldtr.base); | |
4262 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4263 | "idtr:", | |
4264 | save->idtr.selector, save->idtr.attrib, | |
4265 | save->idtr.limit, save->idtr.base); | |
4266 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4267 | "tr:", | |
4268 | save->tr.selector, save->tr.attrib, | |
4269 | save->tr.limit, save->tr.base); | |
3f10c846 JR |
4270 | pr_err("cpl: %d efer: %016llx\n", |
4271 | save->cpl, save->efer); | |
ae8cc059 JP |
4272 | pr_err("%-15s %016llx %-13s %016llx\n", |
4273 | "cr0:", save->cr0, "cr2:", save->cr2); | |
4274 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4275 | "cr3:", save->cr3, "cr4:", save->cr4); | |
4276 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4277 | "dr6:", save->dr6, "dr7:", save->dr7); | |
4278 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4279 | "rip:", save->rip, "rflags:", save->rflags); | |
4280 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4281 | "rsp:", save->rsp, "rax:", save->rax); | |
4282 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4283 | "star:", save->star, "lstar:", save->lstar); | |
4284 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4285 | "cstar:", save->cstar, "sfmask:", save->sfmask); | |
4286 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4287 | "kernel_gs_base:", save->kernel_gs_base, | |
4288 | "sysenter_cs:", save->sysenter_cs); | |
4289 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4290 | "sysenter_esp:", save->sysenter_esp, | |
4291 | "sysenter_eip:", save->sysenter_eip); | |
4292 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4293 | "gpat:", save->g_pat, "dbgctl:", save->dbgctl); | |
4294 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4295 | "br_from:", save->br_from, "br_to:", save->br_to); | |
4296 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4297 | "excp_from:", save->last_excp_from, | |
4298 | "excp_to:", save->last_excp_to); | |
3f10c846 JR |
4299 | } |
4300 | ||
586f9607 AK |
4301 | static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
4302 | { | |
4303 | struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; | |
4304 | ||
4305 | *info1 = control->exit_info_1; | |
4306 | *info2 = control->exit_info_2; | |
4307 | } | |
4308 | ||
851ba692 | 4309 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 4310 | { |
04d2cc77 | 4311 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 4312 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 4313 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 4314 | |
8b89fe1f PB |
4315 | trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM); |
4316 | ||
4ee546b4 | 4317 | if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE)) |
2be4fc7a JR |
4318 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
4319 | if (npt_enabled) | |
4320 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 4321 | |
cd3ff653 JR |
4322 | if (unlikely(svm->nested.exit_required)) { |
4323 | nested_svm_vmexit(svm); | |
4324 | svm->nested.exit_required = false; | |
4325 | ||
4326 | return 1; | |
4327 | } | |
4328 | ||
2030753d | 4329 | if (is_guest_mode(vcpu)) { |
410e4d57 JR |
4330 | int vmexit; |
4331 | ||
d8cabddf JR |
4332 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
4333 | svm->vmcb->control.exit_info_1, | |
4334 | svm->vmcb->control.exit_info_2, | |
4335 | svm->vmcb->control.exit_int_info, | |
e097e5ff SH |
4336 | svm->vmcb->control.exit_int_info_err, |
4337 | KVM_ISA_SVM); | |
d8cabddf | 4338 | |
410e4d57 JR |
4339 | vmexit = nested_svm_exit_special(svm); |
4340 | ||
4341 | if (vmexit == NESTED_EXIT_CONTINUE) | |
4342 | vmexit = nested_svm_exit_handled(svm); | |
4343 | ||
4344 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 4345 | return 1; |
cf74a78b AG |
4346 | } |
4347 | ||
a5c3832d JR |
4348 | svm_complete_interrupts(svm); |
4349 | ||
04d2cc77 AK |
4350 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
4351 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
4352 | kvm_run->fail_entry.hardware_entry_failure_reason | |
4353 | = svm->vmcb->control.exit_code; | |
3f10c846 JR |
4354 | pr_err("KVM: FAILED VMRUN WITH VMCB:\n"); |
4355 | dump_vmcb(vcpu); | |
04d2cc77 AK |
4356 | return 0; |
4357 | } | |
4358 | ||
a2fa3e9f | 4359 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 4360 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
55c5e464 JR |
4361 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH && |
4362 | exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI) | |
6614c7d0 | 4363 | printk(KERN_ERR "%s: unexpected exit_int_info 0x%x " |
6aa8b732 | 4364 | "exit_code 0x%x\n", |
b8688d51 | 4365 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
4366 | exit_code); |
4367 | ||
9d8f549d | 4368 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 4369 | || !svm_exit_handlers[exit_code]) { |
faac2458 | 4370 | WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code); |
2bc19dc3 MT |
4371 | kvm_queue_exception(vcpu, UD_VECTOR); |
4372 | return 1; | |
6aa8b732 AK |
4373 | } |
4374 | ||
851ba692 | 4375 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
4376 | } |
4377 | ||
4378 | static void reload_tss(struct kvm_vcpu *vcpu) | |
4379 | { | |
4380 | int cpu = raw_smp_processor_id(); | |
4381 | ||
0fe1e009 TH |
4382 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
4383 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
4384 | load_TR_desc(); |
4385 | } | |
4386 | ||
e756fc62 | 4387 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
4388 | { |
4389 | int cpu = raw_smp_processor_id(); | |
4390 | ||
0fe1e009 | 4391 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 4392 | |
4b656b12 | 4393 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
4394 | if (svm->asid_generation != sd->asid_generation) |
4395 | new_asid(svm, sd); | |
6aa8b732 AK |
4396 | } |
4397 | ||
95ba8273 GN |
4398 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
4399 | { | |
4400 | struct vcpu_svm *svm = to_svm(vcpu); | |
4401 | ||
4402 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
4403 | vcpu->arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 4404 | set_intercept(svm, INTERCEPT_IRET); |
95ba8273 GN |
4405 | ++vcpu->stat.nmi_injections; |
4406 | } | |
6aa8b732 | 4407 | |
85f455f7 | 4408 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
4409 | { |
4410 | struct vmcb_control_area *control; | |
4411 | ||
340d3bc3 | 4412 | /* The following fields are ignored when AVIC is enabled */ |
e756fc62 | 4413 | control = &svm->vmcb->control; |
85f455f7 | 4414 | control->int_vector = irq; |
6aa8b732 AK |
4415 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
4416 | control->int_ctl |= V_IRQ_MASK | | |
4417 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
decdbf6a | 4418 | mark_dirty(svm->vmcb, VMCB_INTR); |
6aa8b732 AK |
4419 | } |
4420 | ||
66fd3f7f | 4421 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
4422 | { |
4423 | struct vcpu_svm *svm = to_svm(vcpu); | |
4424 | ||
2af9194d | 4425 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 4426 | |
9fb2d2b4 GN |
4427 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
4428 | ++vcpu->stat.irq_injections; | |
4429 | ||
219b65dc AG |
4430 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
4431 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
4432 | } |
4433 | ||
3bbf3565 SS |
4434 | static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu) |
4435 | { | |
4436 | return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK); | |
4437 | } | |
4438 | ||
95ba8273 | 4439 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
4440 | { |
4441 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 4442 | |
3bbf3565 SS |
4443 | if (svm_nested_virtualize_tpr(vcpu) || |
4444 | kvm_vcpu_apicv_active(vcpu)) | |
88ab24ad JR |
4445 | return; |
4446 | ||
596f3142 RK |
4447 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
4448 | ||
95ba8273 | 4449 | if (irr == -1) |
aaacfc9a JR |
4450 | return; |
4451 | ||
95ba8273 | 4452 | if (tpr >= irr) |
4ee546b4 | 4453 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
95ba8273 | 4454 | } |
aaacfc9a | 4455 | |
8d14695f YZ |
4456 | static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) |
4457 | { | |
4458 | return; | |
4459 | } | |
4460 | ||
b2a05fef | 4461 | static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu) |
d62caabb | 4462 | { |
67034bb9 | 4463 | return avic && irqchip_split(vcpu->kvm); |
44a95dae SS |
4464 | } |
4465 | ||
4466 | static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) | |
4467 | { | |
d62caabb AS |
4468 | } |
4469 | ||
67c9dddc | 4470 | static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) |
44a95dae | 4471 | { |
d62caabb AS |
4472 | } |
4473 | ||
44a95dae | 4474 | /* Note: Currently only used by Hyper-V. */ |
d62caabb | 4475 | static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) |
c7c9c56c | 4476 | { |
44a95dae SS |
4477 | struct vcpu_svm *svm = to_svm(vcpu); |
4478 | struct vmcb *vmcb = svm->vmcb; | |
4479 | ||
67034bb9 | 4480 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) |
44a95dae SS |
4481 | return; |
4482 | ||
4483 | vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK; | |
4484 | mark_dirty(vmcb, VMCB_INTR); | |
c7c9c56c YZ |
4485 | } |
4486 | ||
6308630b | 4487 | static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
c7c9c56c YZ |
4488 | { |
4489 | return; | |
4490 | } | |
4491 | ||
340d3bc3 SS |
4492 | static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec) |
4493 | { | |
4494 | kvm_lapic_set_irr(vec, vcpu->arch.apic); | |
4495 | smp_mb__after_atomic(); | |
4496 | ||
4497 | if (avic_vcpu_is_running(vcpu)) | |
4498 | wrmsrl(SVM_AVIC_DOORBELL, | |
7d669f50 | 4499 | kvm_cpu_get_apicid(vcpu->cpu)); |
340d3bc3 SS |
4500 | else |
4501 | kvm_vcpu_wake_up(vcpu); | |
4502 | } | |
4503 | ||
411b44ba SS |
4504 | static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi) |
4505 | { | |
4506 | unsigned long flags; | |
4507 | struct amd_svm_iommu_ir *cur; | |
4508 | ||
4509 | spin_lock_irqsave(&svm->ir_list_lock, flags); | |
4510 | list_for_each_entry(cur, &svm->ir_list, node) { | |
4511 | if (cur->data != pi->ir_data) | |
4512 | continue; | |
4513 | list_del(&cur->node); | |
4514 | kfree(cur); | |
4515 | break; | |
4516 | } | |
4517 | spin_unlock_irqrestore(&svm->ir_list_lock, flags); | |
4518 | } | |
4519 | ||
4520 | static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi) | |
4521 | { | |
4522 | int ret = 0; | |
4523 | unsigned long flags; | |
4524 | struct amd_svm_iommu_ir *ir; | |
4525 | ||
4526 | /** | |
4527 | * In some cases, the existing irte is updaed and re-set, | |
4528 | * so we need to check here if it's already been * added | |
4529 | * to the ir_list. | |
4530 | */ | |
4531 | if (pi->ir_data && (pi->prev_ga_tag != 0)) { | |
4532 | struct kvm *kvm = svm->vcpu.kvm; | |
4533 | u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag); | |
4534 | struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id); | |
4535 | struct vcpu_svm *prev_svm; | |
4536 | ||
4537 | if (!prev_vcpu) { | |
4538 | ret = -EINVAL; | |
4539 | goto out; | |
4540 | } | |
4541 | ||
4542 | prev_svm = to_svm(prev_vcpu); | |
4543 | svm_ir_list_del(prev_svm, pi); | |
4544 | } | |
4545 | ||
4546 | /** | |
4547 | * Allocating new amd_iommu_pi_data, which will get | |
4548 | * add to the per-vcpu ir_list. | |
4549 | */ | |
4550 | ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL); | |
4551 | if (!ir) { | |
4552 | ret = -ENOMEM; | |
4553 | goto out; | |
4554 | } | |
4555 | ir->data = pi->ir_data; | |
4556 | ||
4557 | spin_lock_irqsave(&svm->ir_list_lock, flags); | |
4558 | list_add(&ir->node, &svm->ir_list); | |
4559 | spin_unlock_irqrestore(&svm->ir_list_lock, flags); | |
4560 | out: | |
4561 | return ret; | |
4562 | } | |
4563 | ||
4564 | /** | |
4565 | * Note: | |
4566 | * The HW cannot support posting multicast/broadcast | |
4567 | * interrupts to a vCPU. So, we still use legacy interrupt | |
4568 | * remapping for these kind of interrupts. | |
4569 | * | |
4570 | * For lowest-priority interrupts, we only support | |
4571 | * those with single CPU as the destination, e.g. user | |
4572 | * configures the interrupts via /proc/irq or uses | |
4573 | * irqbalance to make the interrupts single-CPU. | |
4574 | */ | |
4575 | static int | |
4576 | get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, | |
4577 | struct vcpu_data *vcpu_info, struct vcpu_svm **svm) | |
4578 | { | |
4579 | struct kvm_lapic_irq irq; | |
4580 | struct kvm_vcpu *vcpu = NULL; | |
4581 | ||
4582 | kvm_set_msi_irq(kvm, e, &irq); | |
4583 | ||
4584 | if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) { | |
4585 | pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n", | |
4586 | __func__, irq.vector); | |
4587 | return -1; | |
4588 | } | |
4589 | ||
4590 | pr_debug("SVM: %s: use GA mode for irq %u\n", __func__, | |
4591 | irq.vector); | |
4592 | *svm = to_svm(vcpu); | |
d0ec49d4 | 4593 | vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page)); |
411b44ba SS |
4594 | vcpu_info->vector = irq.vector; |
4595 | ||
4596 | return 0; | |
4597 | } | |
4598 | ||
4599 | /* | |
4600 | * svm_update_pi_irte - set IRTE for Posted-Interrupts | |
4601 | * | |
4602 | * @kvm: kvm | |
4603 | * @host_irq: host irq of the interrupt | |
4604 | * @guest_irq: gsi of the interrupt | |
4605 | * @set: set or unset PI | |
4606 | * returns 0 on success, < 0 on failure | |
4607 | */ | |
4608 | static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq, | |
4609 | uint32_t guest_irq, bool set) | |
4610 | { | |
4611 | struct kvm_kernel_irq_routing_entry *e; | |
4612 | struct kvm_irq_routing_table *irq_rt; | |
4613 | int idx, ret = -EINVAL; | |
4614 | ||
4615 | if (!kvm_arch_has_assigned_device(kvm) || | |
4616 | !irq_remapping_cap(IRQ_POSTING_CAP)) | |
4617 | return 0; | |
4618 | ||
4619 | pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n", | |
4620 | __func__, host_irq, guest_irq, set); | |
4621 | ||
4622 | idx = srcu_read_lock(&kvm->irq_srcu); | |
4623 | irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); | |
4624 | WARN_ON(guest_irq >= irq_rt->nr_rt_entries); | |
4625 | ||
4626 | hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { | |
4627 | struct vcpu_data vcpu_info; | |
4628 | struct vcpu_svm *svm = NULL; | |
4629 | ||
4630 | if (e->type != KVM_IRQ_ROUTING_MSI) | |
4631 | continue; | |
4632 | ||
4633 | /** | |
4634 | * Here, we setup with legacy mode in the following cases: | |
4635 | * 1. When cannot target interrupt to a specific vcpu. | |
4636 | * 2. Unsetting posted interrupt. | |
4637 | * 3. APIC virtialization is disabled for the vcpu. | |
4638 | */ | |
4639 | if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set && | |
4640 | kvm_vcpu_apicv_active(&svm->vcpu)) { | |
4641 | struct amd_iommu_pi_data pi; | |
4642 | ||
4643 | /* Try to enable guest_mode in IRTE */ | |
d0ec49d4 TL |
4644 | pi.base = __sme_set(page_to_phys(svm->avic_backing_page) & |
4645 | AVIC_HPA_MASK); | |
411b44ba SS |
4646 | pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id, |
4647 | svm->vcpu.vcpu_id); | |
4648 | pi.is_guest_mode = true; | |
4649 | pi.vcpu_data = &vcpu_info; | |
4650 | ret = irq_set_vcpu_affinity(host_irq, &pi); | |
4651 | ||
4652 | /** | |
4653 | * Here, we successfully setting up vcpu affinity in | |
4654 | * IOMMU guest mode. Now, we need to store the posted | |
4655 | * interrupt information in a per-vcpu ir_list so that | |
4656 | * we can reference to them directly when we update vcpu | |
4657 | * scheduling information in IOMMU irte. | |
4658 | */ | |
4659 | if (!ret && pi.is_guest_mode) | |
4660 | svm_ir_list_add(svm, &pi); | |
4661 | } else { | |
4662 | /* Use legacy mode in IRTE */ | |
4663 | struct amd_iommu_pi_data pi; | |
4664 | ||
4665 | /** | |
4666 | * Here, pi is used to: | |
4667 | * - Tell IOMMU to use legacy mode for this interrupt. | |
4668 | * - Retrieve ga_tag of prior interrupt remapping data. | |
4669 | */ | |
4670 | pi.is_guest_mode = false; | |
4671 | ret = irq_set_vcpu_affinity(host_irq, &pi); | |
4672 | ||
4673 | /** | |
4674 | * Check if the posted interrupt was previously | |
4675 | * setup with the guest_mode by checking if the ga_tag | |
4676 | * was cached. If so, we need to clean up the per-vcpu | |
4677 | * ir_list. | |
4678 | */ | |
4679 | if (!ret && pi.prev_ga_tag) { | |
4680 | int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag); | |
4681 | struct kvm_vcpu *vcpu; | |
4682 | ||
4683 | vcpu = kvm_get_vcpu_by_id(kvm, id); | |
4684 | if (vcpu) | |
4685 | svm_ir_list_del(to_svm(vcpu), &pi); | |
4686 | } | |
4687 | } | |
4688 | ||
4689 | if (!ret && svm) { | |
4690 | trace_kvm_pi_irte_update(svm->vcpu.vcpu_id, | |
4691 | host_irq, e->gsi, | |
4692 | vcpu_info.vector, | |
4693 | vcpu_info.pi_desc_addr, set); | |
4694 | } | |
4695 | ||
4696 | if (ret < 0) { | |
4697 | pr_err("%s: failed to update PI IRTE\n", __func__); | |
4698 | goto out; | |
4699 | } | |
4700 | } | |
4701 | ||
4702 | ret = 0; | |
4703 | out: | |
4704 | srcu_read_unlock(&kvm->irq_srcu, idx); | |
4705 | return ret; | |
4706 | } | |
4707 | ||
95ba8273 GN |
4708 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
4709 | { | |
4710 | struct vcpu_svm *svm = to_svm(vcpu); | |
4711 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
4712 | int ret; |
4713 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
4714 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
4715 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
4716 | ||
4717 | return ret; | |
aaacfc9a JR |
4718 | } |
4719 | ||
3cfc3092 JK |
4720 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
4721 | { | |
4722 | struct vcpu_svm *svm = to_svm(vcpu); | |
4723 | ||
4724 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
4725 | } | |
4726 | ||
4727 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
4728 | { | |
4729 | struct vcpu_svm *svm = to_svm(vcpu); | |
4730 | ||
4731 | if (masked) { | |
4732 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 4733 | set_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
4734 | } else { |
4735 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
8a05a1b8 | 4736 | clr_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
4737 | } |
4738 | } | |
4739 | ||
78646121 GN |
4740 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
4741 | { | |
4742 | struct vcpu_svm *svm = to_svm(vcpu); | |
4743 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
4744 | int ret; |
4745 | ||
4746 | if (!gif_set(svm) || | |
4747 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
4748 | return 0; | |
4749 | ||
f6e78475 | 4750 | ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF); |
7fcdb510 | 4751 | |
2030753d | 4752 | if (is_guest_mode(vcpu)) |
7fcdb510 JR |
4753 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); |
4754 | ||
4755 | return ret; | |
78646121 GN |
4756 | } |
4757 | ||
c9a7953f | 4758 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 4759 | { |
219b65dc | 4760 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 4761 | |
340d3bc3 SS |
4762 | if (kvm_vcpu_apicv_active(vcpu)) |
4763 | return; | |
4764 | ||
e0231715 JR |
4765 | /* |
4766 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
4767 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
4768 | * get that intercept, this function will be called again though and | |
640bd6e5 JN |
4769 | * we'll get the vintr intercept. However, if the vGIF feature is |
4770 | * enabled, the STGI interception will not occur. Enable the irq | |
4771 | * window under the assumption that the hardware will set the GIF. | |
e0231715 | 4772 | */ |
640bd6e5 | 4773 | if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) { |
219b65dc AG |
4774 | svm_set_vintr(svm); |
4775 | svm_inject_irq(svm, 0x0); | |
4776 | } | |
85f455f7 ED |
4777 | } |
4778 | ||
c9a7953f | 4779 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 4780 | { |
04d2cc77 | 4781 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 4782 | |
44c11430 GN |
4783 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
4784 | == HF_NMI_MASK) | |
c9a7953f | 4785 | return; /* IRET will cause a vm exit */ |
44c11430 | 4786 | |
640bd6e5 JN |
4787 | if (!gif_set(svm)) { |
4788 | if (vgif_enabled(svm)) | |
4789 | set_intercept(svm, INTERCEPT_STGI); | |
1a5e1852 | 4790 | return; /* STGI will cause a vm exit */ |
640bd6e5 | 4791 | } |
1a5e1852 LP |
4792 | |
4793 | if (svm->nested.exit_required) | |
4794 | return; /* we're not going to run the guest yet */ | |
4795 | ||
e0231715 JR |
4796 | /* |
4797 | * Something prevents NMI from been injected. Single step over possible | |
4798 | * problem (IRET or exception injection or interrupt shadow) | |
4799 | */ | |
ab2f4d73 | 4800 | svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu); |
6be7d306 | 4801 | svm->nmi_singlestep = true; |
44c11430 | 4802 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
c1150d8c DL |
4803 | } |
4804 | ||
cbc94022 IE |
4805 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
4806 | { | |
4807 | return 0; | |
4808 | } | |
4809 | ||
d9e368d6 AK |
4810 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
4811 | { | |
38e5e92f JR |
4812 | struct vcpu_svm *svm = to_svm(vcpu); |
4813 | ||
4814 | if (static_cpu_has(X86_FEATURE_FLUSHBYASID)) | |
4815 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; | |
4816 | else | |
4817 | svm->asid_generation--; | |
d9e368d6 AK |
4818 | } |
4819 | ||
04d2cc77 AK |
4820 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
4821 | { | |
4822 | } | |
4823 | ||
d7bf8221 JR |
4824 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
4825 | { | |
4826 | struct vcpu_svm *svm = to_svm(vcpu); | |
4827 | ||
3bbf3565 | 4828 | if (svm_nested_virtualize_tpr(vcpu)) |
88ab24ad JR |
4829 | return; |
4830 | ||
4ee546b4 | 4831 | if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) { |
d7bf8221 | 4832 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; |
615d5193 | 4833 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
4834 | } |
4835 | } | |
4836 | ||
649d6864 JR |
4837 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
4838 | { | |
4839 | struct vcpu_svm *svm = to_svm(vcpu); | |
4840 | u64 cr8; | |
4841 | ||
3bbf3565 SS |
4842 | if (svm_nested_virtualize_tpr(vcpu) || |
4843 | kvm_vcpu_apicv_active(vcpu)) | |
88ab24ad JR |
4844 | return; |
4845 | ||
649d6864 JR |
4846 | cr8 = kvm_get_cr8(vcpu); |
4847 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
4848 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
4849 | } | |
4850 | ||
9222be18 GN |
4851 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
4852 | { | |
4853 | u8 vector; | |
4854 | int type; | |
4855 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
4856 | unsigned int3_injected = svm->int3_injected; |
4857 | ||
4858 | svm->int3_injected = 0; | |
9222be18 | 4859 | |
bd3d1ec3 AK |
4860 | /* |
4861 | * If we've made progress since setting HF_IRET_MASK, we've | |
4862 | * executed an IRET and can allow NMI injection. | |
4863 | */ | |
4864 | if ((svm->vcpu.arch.hflags & HF_IRET_MASK) | |
4865 | && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) { | |
44c11430 | 4866 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); |
3842d135 AK |
4867 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
4868 | } | |
44c11430 | 4869 | |
9222be18 GN |
4870 | svm->vcpu.arch.nmi_injected = false; |
4871 | kvm_clear_exception_queue(&svm->vcpu); | |
4872 | kvm_clear_interrupt_queue(&svm->vcpu); | |
4873 | ||
4874 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
4875 | return; | |
4876 | ||
3842d135 AK |
4877 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
4878 | ||
9222be18 GN |
4879 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; |
4880 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
4881 | ||
4882 | switch (type) { | |
4883 | case SVM_EXITINTINFO_TYPE_NMI: | |
4884 | svm->vcpu.arch.nmi_injected = true; | |
4885 | break; | |
4886 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
4887 | /* |
4888 | * In case of software exceptions, do not reinject the vector, | |
4889 | * but re-execute the instruction instead. Rewind RIP first | |
4890 | * if we emulated INT3 before. | |
4891 | */ | |
4892 | if (kvm_exception_is_soft(vector)) { | |
4893 | if (vector == BP_VECTOR && int3_injected && | |
4894 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
4895 | kvm_rip_write(&svm->vcpu, | |
4896 | kvm_rip_read(&svm->vcpu) - | |
4897 | int3_injected); | |
9222be18 | 4898 | break; |
66b7138f | 4899 | } |
9222be18 GN |
4900 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
4901 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 4902 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
4903 | |
4904 | } else | |
ce7ddec4 | 4905 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
4906 | break; |
4907 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 4908 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
4909 | break; |
4910 | default: | |
4911 | break; | |
4912 | } | |
4913 | } | |
4914 | ||
b463a6f7 AK |
4915 | static void svm_cancel_injection(struct kvm_vcpu *vcpu) |
4916 | { | |
4917 | struct vcpu_svm *svm = to_svm(vcpu); | |
4918 | struct vmcb_control_area *control = &svm->vmcb->control; | |
4919 | ||
4920 | control->exit_int_info = control->event_inj; | |
4921 | control->exit_int_info_err = control->event_inj_err; | |
4922 | control->event_inj = 0; | |
4923 | svm_complete_interrupts(svm); | |
4924 | } | |
4925 | ||
851ba692 | 4926 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 4927 | { |
a2fa3e9f | 4928 | struct vcpu_svm *svm = to_svm(vcpu); |
d9e368d6 | 4929 | |
2041a06a JR |
4930 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
4931 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
4932 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
4933 | ||
cd3ff653 JR |
4934 | /* |
4935 | * A vmexit emulation is required before the vcpu can be executed | |
4936 | * again. | |
4937 | */ | |
4938 | if (unlikely(svm->nested.exit_required)) | |
4939 | return; | |
4940 | ||
a12713c2 LP |
4941 | /* |
4942 | * Disable singlestep if we're injecting an interrupt/exception. | |
4943 | * We don't want our modified rflags to be pushed on the stack where | |
4944 | * we might not be able to easily reset them if we disabled NMI | |
4945 | * singlestep later. | |
4946 | */ | |
4947 | if (svm->nmi_singlestep && svm->vmcb->control.event_inj) { | |
4948 | /* | |
4949 | * Event injection happens before external interrupts cause a | |
4950 | * vmexit and interrupts are disabled here, so smp_send_reschedule | |
4951 | * is enough to force an immediate vmexit. | |
4952 | */ | |
4953 | disable_nmi_singlestep(svm); | |
4954 | smp_send_reschedule(vcpu->cpu); | |
4955 | } | |
4956 | ||
e756fc62 | 4957 | pre_svm_run(svm); |
6aa8b732 | 4958 | |
649d6864 JR |
4959 | sync_lapic_to_cr8(vcpu); |
4960 | ||
cda0ffdd | 4961 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 4962 | |
04d2cc77 AK |
4963 | clgi(); |
4964 | ||
4965 | local_irq_enable(); | |
36241b8c | 4966 | |
6aa8b732 | 4967 | asm volatile ( |
7454766f AK |
4968 | "push %%" _ASM_BP "; \n\t" |
4969 | "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t" | |
4970 | "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t" | |
4971 | "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t" | |
4972 | "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t" | |
4973 | "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t" | |
4974 | "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 4975 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
4976 | "mov %c[r8](%[svm]), %%r8 \n\t" |
4977 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
4978 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
4979 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
4980 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
4981 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
4982 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
4983 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
4984 | #endif |
4985 | ||
6aa8b732 | 4986 | /* Enter guest mode */ |
7454766f AK |
4987 | "push %%" _ASM_AX " \n\t" |
4988 | "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t" | |
4ecac3fd AK |
4989 | __ex(SVM_VMLOAD) "\n\t" |
4990 | __ex(SVM_VMRUN) "\n\t" | |
4991 | __ex(SVM_VMSAVE) "\n\t" | |
7454766f | 4992 | "pop %%" _ASM_AX " \n\t" |
6aa8b732 AK |
4993 | |
4994 | /* Save guest registers, load host registers */ | |
7454766f AK |
4995 | "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t" |
4996 | "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t" | |
4997 | "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t" | |
4998 | "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t" | |
4999 | "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t" | |
5000 | "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 5001 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
5002 | "mov %%r8, %c[r8](%[svm]) \n\t" |
5003 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
5004 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
5005 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
5006 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
5007 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
5008 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
5009 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
0cb5b306 JM |
5010 | #endif |
5011 | /* | |
5012 | * Clear host registers marked as clobbered to prevent | |
5013 | * speculative use. | |
5014 | */ | |
5015 | "xor %%" _ASM_BX ", %%" _ASM_BX " \n\t" | |
5016 | "xor %%" _ASM_CX ", %%" _ASM_CX " \n\t" | |
5017 | "xor %%" _ASM_DX ", %%" _ASM_DX " \n\t" | |
5018 | "xor %%" _ASM_SI ", %%" _ASM_SI " \n\t" | |
5019 | "xor %%" _ASM_DI ", %%" _ASM_DI " \n\t" | |
5020 | #ifdef CONFIG_X86_64 | |
5021 | "xor %%r8, %%r8 \n\t" | |
5022 | "xor %%r9, %%r9 \n\t" | |
5023 | "xor %%r10, %%r10 \n\t" | |
5024 | "xor %%r11, %%r11 \n\t" | |
5025 | "xor %%r12, %%r12 \n\t" | |
5026 | "xor %%r13, %%r13 \n\t" | |
5027 | "xor %%r14, %%r14 \n\t" | |
5028 | "xor %%r15, %%r15 \n\t" | |
6aa8b732 | 5029 | #endif |
7454766f | 5030 | "pop %%" _ASM_BP |
6aa8b732 | 5031 | : |
fb3f0f51 | 5032 | : [svm]"a"(svm), |
6aa8b732 | 5033 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
5034 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
5035 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
5036 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
5037 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
5038 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
5039 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 5040 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
5041 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
5042 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
5043 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
5044 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
5045 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
5046 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
5047 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
5048 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 5049 | #endif |
54a08c04 LV |
5050 | : "cc", "memory" |
5051 | #ifdef CONFIG_X86_64 | |
7454766f | 5052 | , "rbx", "rcx", "rdx", "rsi", "rdi" |
54a08c04 | 5053 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
7454766f AK |
5054 | #else |
5055 | , "ebx", "ecx", "edx", "esi", "edi" | |
54a08c04 LV |
5056 | #endif |
5057 | ); | |
6aa8b732 | 5058 | |
117cc7a9 DW |
5059 | /* Eliminate branch target predictions from guest mode */ |
5060 | vmexit_fill_RSB(); | |
5061 | ||
82ca2d10 AK |
5062 | #ifdef CONFIG_X86_64 |
5063 | wrmsrl(MSR_GS_BASE, svm->host.gs_base); | |
5064 | #else | |
dacccfdd | 5065 | loadsegment(fs, svm->host.fs); |
831ca609 AK |
5066 | #ifndef CONFIG_X86_32_LAZY_GS |
5067 | loadsegment(gs, svm->host.gs); | |
5068 | #endif | |
9581d442 | 5069 | #endif |
6aa8b732 AK |
5070 | |
5071 | reload_tss(vcpu); | |
5072 | ||
56ba47dd AK |
5073 | local_irq_disable(); |
5074 | ||
13c34e07 AK |
5075 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
5076 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
5077 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
5078 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
5079 | ||
3781c01c JR |
5080 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) |
5081 | kvm_before_handle_nmi(&svm->vcpu); | |
5082 | ||
5083 | stgi(); | |
5084 | ||
5085 | /* Any pending NMI will happen here */ | |
5086 | ||
5087 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) | |
5088 | kvm_after_handle_nmi(&svm->vcpu); | |
5089 | ||
d7bf8221 JR |
5090 | sync_cr8_to_lapic(vcpu); |
5091 | ||
a2fa3e9f | 5092 | svm->next_rip = 0; |
9222be18 | 5093 | |
38e5e92f JR |
5094 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
5095 | ||
631bc487 GN |
5096 | /* if exit due to PF check for async PF */ |
5097 | if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
1261bfa3 | 5098 | svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); |
631bc487 | 5099 | |
6de4f3ad AK |
5100 | if (npt_enabled) { |
5101 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
5102 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
5103 | } | |
fe5913e4 JR |
5104 | |
5105 | /* | |
5106 | * We need to handle MC intercepts here before the vcpu has a chance to | |
5107 | * change the physical cpu | |
5108 | */ | |
5109 | if (unlikely(svm->vmcb->control.exit_code == | |
5110 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
5111 | svm_handle_mce(svm); | |
8d28fec4 RJ |
5112 | |
5113 | mark_all_clean(svm->vmcb); | |
6aa8b732 | 5114 | } |
c207aee4 | 5115 | STACK_FRAME_NON_STANDARD(svm_vcpu_run); |
6aa8b732 | 5116 | |
6aa8b732 AK |
5117 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
5118 | { | |
a2fa3e9f GH |
5119 | struct vcpu_svm *svm = to_svm(vcpu); |
5120 | ||
d0ec49d4 | 5121 | svm->vmcb->save.cr3 = __sme_set(root); |
dcca1a65 | 5122 | mark_dirty(svm->vmcb, VMCB_CR); |
f40f6a45 | 5123 | svm_flush_tlb(vcpu); |
6aa8b732 AK |
5124 | } |
5125 | ||
1c97f0a0 JR |
5126 | static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
5127 | { | |
5128 | struct vcpu_svm *svm = to_svm(vcpu); | |
5129 | ||
d0ec49d4 | 5130 | svm->vmcb->control.nested_cr3 = __sme_set(root); |
b2747166 | 5131 | mark_dirty(svm->vmcb, VMCB_NPT); |
1c97f0a0 JR |
5132 | |
5133 | /* Also sync guest cr3 here in case we live migrate */ | |
9f8fe504 | 5134 | svm->vmcb->save.cr3 = kvm_read_cr3(vcpu); |
dcca1a65 | 5135 | mark_dirty(svm->vmcb, VMCB_CR); |
1c97f0a0 | 5136 | |
f40f6a45 | 5137 | svm_flush_tlb(vcpu); |
1c97f0a0 JR |
5138 | } |
5139 | ||
6aa8b732 AK |
5140 | static int is_disabled(void) |
5141 | { | |
6031a61c JR |
5142 | u64 vm_cr; |
5143 | ||
5144 | rdmsrl(MSR_VM_CR, vm_cr); | |
5145 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
5146 | return 1; | |
5147 | ||
6aa8b732 AK |
5148 | return 0; |
5149 | } | |
5150 | ||
102d8325 IM |
5151 | static void |
5152 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
5153 | { | |
5154 | /* | |
5155 | * Patch in the VMMCALL instruction: | |
5156 | */ | |
5157 | hypercall[0] = 0x0f; | |
5158 | hypercall[1] = 0x01; | |
5159 | hypercall[2] = 0xd9; | |
102d8325 IM |
5160 | } |
5161 | ||
002c7f7c YS |
5162 | static void svm_check_processor_compat(void *rtn) |
5163 | { | |
5164 | *(int *)rtn = 0; | |
5165 | } | |
5166 | ||
774ead3a AK |
5167 | static bool svm_cpu_has_accelerated_tpr(void) |
5168 | { | |
5169 | return false; | |
5170 | } | |
5171 | ||
6d396b55 PB |
5172 | static bool svm_has_high_real_mode_segbase(void) |
5173 | { | |
5174 | return true; | |
5175 | } | |
5176 | ||
fc07e76a PB |
5177 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
5178 | { | |
5179 | return 0; | |
5180 | } | |
5181 | ||
0e851880 SY |
5182 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
5183 | { | |
6092d3d3 JR |
5184 | struct vcpu_svm *svm = to_svm(vcpu); |
5185 | ||
5186 | /* Update nrips enabled cache */ | |
d6321d49 | 5187 | svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS); |
46781eae SS |
5188 | |
5189 | if (!kvm_vcpu_apicv_active(vcpu)) | |
5190 | return; | |
5191 | ||
1b4d56b8 | 5192 | guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC); |
0e851880 SY |
5193 | } |
5194 | ||
d4330ef2 JR |
5195 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
5196 | { | |
c2c63a49 | 5197 | switch (func) { |
46781eae SS |
5198 | case 0x1: |
5199 | if (avic) | |
5200 | entry->ecx &= ~bit(X86_FEATURE_X2APIC); | |
5201 | break; | |
4c62a2dc JR |
5202 | case 0x80000001: |
5203 | if (nested) | |
5204 | entry->ecx |= (1 << 2); /* Set SVM bit */ | |
5205 | break; | |
c2c63a49 JR |
5206 | case 0x8000000A: |
5207 | entry->eax = 1; /* SVM revision 1 */ | |
5208 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
5209 | ASID emulation to nested SVM */ | |
5210 | entry->ecx = 0; /* Reserved */ | |
7a190667 JR |
5211 | entry->edx = 0; /* Per default do not support any |
5212 | additional features */ | |
5213 | ||
5214 | /* Support next_rip if host supports it */ | |
2a6b20b8 | 5215 | if (boot_cpu_has(X86_FEATURE_NRIPS)) |
7a190667 | 5216 | entry->edx |= SVM_FEATURE_NRIP; |
c2c63a49 | 5217 | |
3d4aeaad JR |
5218 | /* Support NPT for the guest if enabled */ |
5219 | if (npt_enabled) | |
5220 | entry->edx |= SVM_FEATURE_NPT; | |
5221 | ||
c2c63a49 JR |
5222 | break; |
5223 | } | |
d4330ef2 JR |
5224 | } |
5225 | ||
17cc3935 | 5226 | static int svm_get_lpage_level(void) |
344f414f | 5227 | { |
17cc3935 | 5228 | return PT_PDPE_LEVEL; |
344f414f JR |
5229 | } |
5230 | ||
4e47c7a6 SY |
5231 | static bool svm_rdtscp_supported(void) |
5232 | { | |
46896c73 | 5233 | return boot_cpu_has(X86_FEATURE_RDTSCP); |
4e47c7a6 SY |
5234 | } |
5235 | ||
ad756a16 MJ |
5236 | static bool svm_invpcid_supported(void) |
5237 | { | |
5238 | return false; | |
5239 | } | |
5240 | ||
93c4adc7 PB |
5241 | static bool svm_mpx_supported(void) |
5242 | { | |
5243 | return false; | |
5244 | } | |
5245 | ||
55412b2e WL |
5246 | static bool svm_xsaves_supported(void) |
5247 | { | |
5248 | return false; | |
5249 | } | |
5250 | ||
f5f48ee1 SY |
5251 | static bool svm_has_wbinvd_exit(void) |
5252 | { | |
5253 | return true; | |
5254 | } | |
5255 | ||
8061252e | 5256 | #define PRE_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 5257 | .stage = X86_ICPT_PRE_EXCEPT, } |
cfec82cb | 5258 | #define POST_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 5259 | .stage = X86_ICPT_POST_EXCEPT, } |
d7eb8203 | 5260 | #define POST_MEM(exit) { .exit_code = (exit), \ |
40e19b51 | 5261 | .stage = X86_ICPT_POST_MEMACCESS, } |
cfec82cb | 5262 | |
09941fbb | 5263 | static const struct __x86_intercept { |
cfec82cb JR |
5264 | u32 exit_code; |
5265 | enum x86_intercept_stage stage; | |
cfec82cb JR |
5266 | } x86_intercept_map[] = { |
5267 | [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0), | |
5268 | [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0), | |
5269 | [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0), | |
5270 | [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0), | |
5271 | [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0), | |
3b88e41a JR |
5272 | [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0), |
5273 | [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0), | |
dee6bb70 JR |
5274 | [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ), |
5275 | [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ), | |
5276 | [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE), | |
5277 | [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE), | |
5278 | [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ), | |
5279 | [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ), | |
5280 | [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE), | |
5281 | [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE), | |
01de8b09 JR |
5282 | [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN), |
5283 | [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL), | |
5284 | [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD), | |
5285 | [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE), | |
5286 | [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI), | |
5287 | [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI), | |
5288 | [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT), | |
5289 | [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA), | |
d7eb8203 JR |
5290 | [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP), |
5291 | [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR), | |
5292 | [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT), | |
8061252e JR |
5293 | [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG), |
5294 | [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD), | |
5295 | [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD), | |
5296 | [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR), | |
5297 | [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC), | |
5298 | [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR), | |
5299 | [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC), | |
5300 | [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID), | |
5301 | [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM), | |
bf608f88 JR |
5302 | [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE), |
5303 | [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF), | |
5304 | [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF), | |
5305 | [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT), | |
5306 | [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET), | |
5307 | [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP), | |
5308 | [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT), | |
f6511935 JR |
5309 | [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO), |
5310 | [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO), | |
5311 | [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO), | |
5312 | [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO), | |
cfec82cb JR |
5313 | }; |
5314 | ||
8061252e | 5315 | #undef PRE_EX |
cfec82cb | 5316 | #undef POST_EX |
d7eb8203 | 5317 | #undef POST_MEM |
cfec82cb | 5318 | |
8a76d7f2 JR |
5319 | static int svm_check_intercept(struct kvm_vcpu *vcpu, |
5320 | struct x86_instruction_info *info, | |
5321 | enum x86_intercept_stage stage) | |
5322 | { | |
cfec82cb JR |
5323 | struct vcpu_svm *svm = to_svm(vcpu); |
5324 | int vmexit, ret = X86EMUL_CONTINUE; | |
5325 | struct __x86_intercept icpt_info; | |
5326 | struct vmcb *vmcb = svm->vmcb; | |
5327 | ||
5328 | if (info->intercept >= ARRAY_SIZE(x86_intercept_map)) | |
5329 | goto out; | |
5330 | ||
5331 | icpt_info = x86_intercept_map[info->intercept]; | |
5332 | ||
40e19b51 | 5333 | if (stage != icpt_info.stage) |
cfec82cb JR |
5334 | goto out; |
5335 | ||
5336 | switch (icpt_info.exit_code) { | |
5337 | case SVM_EXIT_READ_CR0: | |
5338 | if (info->intercept == x86_intercept_cr_read) | |
5339 | icpt_info.exit_code += info->modrm_reg; | |
5340 | break; | |
5341 | case SVM_EXIT_WRITE_CR0: { | |
5342 | unsigned long cr0, val; | |
5343 | u64 intercept; | |
5344 | ||
5345 | if (info->intercept == x86_intercept_cr_write) | |
5346 | icpt_info.exit_code += info->modrm_reg; | |
5347 | ||
62baf44c JK |
5348 | if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 || |
5349 | info->intercept == x86_intercept_clts) | |
cfec82cb JR |
5350 | break; |
5351 | ||
5352 | intercept = svm->nested.intercept; | |
5353 | ||
5354 | if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))) | |
5355 | break; | |
5356 | ||
5357 | cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK; | |
5358 | val = info->src_val & ~SVM_CR0_SELECTIVE_MASK; | |
5359 | ||
5360 | if (info->intercept == x86_intercept_lmsw) { | |
5361 | cr0 &= 0xfUL; | |
5362 | val &= 0xfUL; | |
5363 | /* lmsw can't clear PE - catch this here */ | |
5364 | if (cr0 & X86_CR0_PE) | |
5365 | val |= X86_CR0_PE; | |
5366 | } | |
5367 | ||
5368 | if (cr0 ^ val) | |
5369 | icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
5370 | ||
5371 | break; | |
5372 | } | |
3b88e41a JR |
5373 | case SVM_EXIT_READ_DR0: |
5374 | case SVM_EXIT_WRITE_DR0: | |
5375 | icpt_info.exit_code += info->modrm_reg; | |
5376 | break; | |
8061252e JR |
5377 | case SVM_EXIT_MSR: |
5378 | if (info->intercept == x86_intercept_wrmsr) | |
5379 | vmcb->control.exit_info_1 = 1; | |
5380 | else | |
5381 | vmcb->control.exit_info_1 = 0; | |
5382 | break; | |
bf608f88 JR |
5383 | case SVM_EXIT_PAUSE: |
5384 | /* | |
5385 | * We get this for NOP only, but pause | |
5386 | * is rep not, check this here | |
5387 | */ | |
5388 | if (info->rep_prefix != REPE_PREFIX) | |
5389 | goto out; | |
49a8afca | 5390 | break; |
f6511935 JR |
5391 | case SVM_EXIT_IOIO: { |
5392 | u64 exit_info; | |
5393 | u32 bytes; | |
5394 | ||
f6511935 JR |
5395 | if (info->intercept == x86_intercept_in || |
5396 | info->intercept == x86_intercept_ins) { | |
6cbc5f5a JK |
5397 | exit_info = ((info->src_val & 0xffff) << 16) | |
5398 | SVM_IOIO_TYPE_MASK; | |
f6511935 | 5399 | bytes = info->dst_bytes; |
6493f157 | 5400 | } else { |
6cbc5f5a | 5401 | exit_info = (info->dst_val & 0xffff) << 16; |
6493f157 | 5402 | bytes = info->src_bytes; |
f6511935 JR |
5403 | } |
5404 | ||
5405 | if (info->intercept == x86_intercept_outs || | |
5406 | info->intercept == x86_intercept_ins) | |
5407 | exit_info |= SVM_IOIO_STR_MASK; | |
5408 | ||
5409 | if (info->rep_prefix) | |
5410 | exit_info |= SVM_IOIO_REP_MASK; | |
5411 | ||
5412 | bytes = min(bytes, 4u); | |
5413 | ||
5414 | exit_info |= bytes << SVM_IOIO_SIZE_SHIFT; | |
5415 | ||
5416 | exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1); | |
5417 | ||
5418 | vmcb->control.exit_info_1 = exit_info; | |
5419 | vmcb->control.exit_info_2 = info->next_rip; | |
5420 | ||
5421 | break; | |
5422 | } | |
cfec82cb JR |
5423 | default: |
5424 | break; | |
5425 | } | |
5426 | ||
f104765b BD |
5427 | /* TODO: Advertise NRIPS to guest hypervisor unconditionally */ |
5428 | if (static_cpu_has(X86_FEATURE_NRIPS)) | |
5429 | vmcb->control.next_rip = info->next_rip; | |
cfec82cb JR |
5430 | vmcb->control.exit_code = icpt_info.exit_code; |
5431 | vmexit = nested_svm_exit_handled(svm); | |
5432 | ||
5433 | ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED | |
5434 | : X86EMUL_CONTINUE; | |
5435 | ||
5436 | out: | |
5437 | return ret; | |
8a76d7f2 JR |
5438 | } |
5439 | ||
a547c6db YZ |
5440 | static void svm_handle_external_intr(struct kvm_vcpu *vcpu) |
5441 | { | |
5442 | local_irq_enable(); | |
f2485b3e PB |
5443 | /* |
5444 | * We must have an instruction with interrupts enabled, so | |
5445 | * the timer interrupt isn't delayed by the interrupt shadow. | |
5446 | */ | |
5447 | asm("nop"); | |
5448 | local_irq_disable(); | |
a547c6db YZ |
5449 | } |
5450 | ||
ae97a3b8 RK |
5451 | static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu) |
5452 | { | |
5453 | } | |
5454 | ||
be8ca170 SS |
5455 | static inline void avic_post_state_restore(struct kvm_vcpu *vcpu) |
5456 | { | |
5457 | if (avic_handle_apic_id_update(vcpu) != 0) | |
5458 | return; | |
5459 | if (avic_handle_dfr_update(vcpu) != 0) | |
5460 | return; | |
5461 | avic_handle_ldr_update(vcpu); | |
5462 | } | |
5463 | ||
74f16909 BP |
5464 | static void svm_setup_mce(struct kvm_vcpu *vcpu) |
5465 | { | |
5466 | /* [63:9] are reserved. */ | |
5467 | vcpu->arch.mcg_cap &= 0x1ff; | |
5468 | } | |
5469 | ||
72d7b374 LP |
5470 | static int svm_smi_allowed(struct kvm_vcpu *vcpu) |
5471 | { | |
05cade71 LP |
5472 | struct vcpu_svm *svm = to_svm(vcpu); |
5473 | ||
5474 | /* Per APM Vol.2 15.22.2 "Response to SMI" */ | |
5475 | if (!gif_set(svm)) | |
5476 | return 0; | |
5477 | ||
5478 | if (is_guest_mode(&svm->vcpu) && | |
5479 | svm->nested.intercept & (1ULL << INTERCEPT_SMI)) { | |
5480 | /* TODO: Might need to set exit_info_1 and exit_info_2 here */ | |
5481 | svm->vmcb->control.exit_code = SVM_EXIT_SMI; | |
5482 | svm->nested.exit_required = true; | |
5483 | return 0; | |
5484 | } | |
5485 | ||
72d7b374 LP |
5486 | return 1; |
5487 | } | |
5488 | ||
0234bf88 LP |
5489 | static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) |
5490 | { | |
05cade71 LP |
5491 | struct vcpu_svm *svm = to_svm(vcpu); |
5492 | int ret; | |
5493 | ||
5494 | if (is_guest_mode(vcpu)) { | |
5495 | /* FED8h - SVM Guest */ | |
5496 | put_smstate(u64, smstate, 0x7ed8, 1); | |
5497 | /* FEE0h - SVM Guest VMCB Physical Address */ | |
5498 | put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb); | |
5499 | ||
5500 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; | |
5501 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
5502 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
5503 | ||
5504 | ret = nested_svm_vmexit(svm); | |
5505 | if (ret) | |
5506 | return ret; | |
5507 | } | |
0234bf88 LP |
5508 | return 0; |
5509 | } | |
5510 | ||
5511 | static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase) | |
5512 | { | |
05cade71 LP |
5513 | struct vcpu_svm *svm = to_svm(vcpu); |
5514 | struct vmcb *nested_vmcb; | |
5515 | struct page *page; | |
5516 | struct { | |
5517 | u64 guest; | |
5518 | u64 vmcb; | |
5519 | } svm_state_save; | |
5520 | int ret; | |
5521 | ||
5522 | ret = kvm_vcpu_read_guest(vcpu, smbase + 0xfed8, &svm_state_save, | |
5523 | sizeof(svm_state_save)); | |
5524 | if (ret) | |
5525 | return ret; | |
5526 | ||
5527 | if (svm_state_save.guest) { | |
5528 | vcpu->arch.hflags &= ~HF_SMM_MASK; | |
5529 | nested_vmcb = nested_svm_map(svm, svm_state_save.vmcb, &page); | |
5530 | if (nested_vmcb) | |
5531 | enter_svm_guest_mode(svm, svm_state_save.vmcb, nested_vmcb, page); | |
5532 | else | |
5533 | ret = 1; | |
5534 | vcpu->arch.hflags |= HF_SMM_MASK; | |
5535 | } | |
5536 | return ret; | |
0234bf88 LP |
5537 | } |
5538 | ||
cc3d967f LP |
5539 | static int enable_smi_window(struct kvm_vcpu *vcpu) |
5540 | { | |
5541 | struct vcpu_svm *svm = to_svm(vcpu); | |
5542 | ||
5543 | if (!gif_set(svm)) { | |
5544 | if (vgif_enabled(svm)) | |
5545 | set_intercept(svm, INTERCEPT_STGI); | |
5546 | /* STGI will cause a vm exit */ | |
5547 | return 1; | |
5548 | } | |
5549 | return 0; | |
5550 | } | |
5551 | ||
404f6aac | 5552 | static struct kvm_x86_ops svm_x86_ops __ro_after_init = { |
6aa8b732 AK |
5553 | .cpu_has_kvm_support = has_svm, |
5554 | .disabled_by_bios = is_disabled, | |
5555 | .hardware_setup = svm_hardware_setup, | |
5556 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 5557 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
5558 | .hardware_enable = svm_hardware_enable, |
5559 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 5560 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6d396b55 | 5561 | .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase, |
6aa8b732 AK |
5562 | |
5563 | .vcpu_create = svm_create_vcpu, | |
5564 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 5565 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 5566 | |
44a95dae SS |
5567 | .vm_init = avic_vm_init, |
5568 | .vm_destroy = avic_vm_destroy, | |
5569 | ||
04d2cc77 | 5570 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
5571 | .vcpu_load = svm_vcpu_load, |
5572 | .vcpu_put = svm_vcpu_put, | |
8221c137 SS |
5573 | .vcpu_blocking = svm_vcpu_blocking, |
5574 | .vcpu_unblocking = svm_vcpu_unblocking, | |
6aa8b732 | 5575 | |
a96036b8 | 5576 | .update_bp_intercept = update_bp_intercept, |
6aa8b732 AK |
5577 | .get_msr = svm_get_msr, |
5578 | .set_msr = svm_set_msr, | |
5579 | .get_segment_base = svm_get_segment_base, | |
5580 | .get_segment = svm_get_segment, | |
5581 | .set_segment = svm_set_segment, | |
2e4d2653 | 5582 | .get_cpl = svm_get_cpl, |
1747fb71 | 5583 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 5584 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
aff48baa | 5585 | .decache_cr3 = svm_decache_cr3, |
25c4c276 | 5586 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 5587 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
5588 | .set_cr3 = svm_set_cr3, |
5589 | .set_cr4 = svm_set_cr4, | |
5590 | .set_efer = svm_set_efer, | |
5591 | .get_idt = svm_get_idt, | |
5592 | .set_idt = svm_set_idt, | |
5593 | .get_gdt = svm_get_gdt, | |
5594 | .set_gdt = svm_set_gdt, | |
73aaf249 JK |
5595 | .get_dr6 = svm_get_dr6, |
5596 | .set_dr6 = svm_set_dr6, | |
020df079 | 5597 | .set_dr7 = svm_set_dr7, |
facb0139 | 5598 | .sync_dirty_debug_regs = svm_sync_dirty_debug_regs, |
6de4f3ad | 5599 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
5600 | .get_rflags = svm_get_rflags, |
5601 | .set_rflags = svm_set_rflags, | |
be94f6b7 | 5602 | |
6aa8b732 | 5603 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 5604 | |
6aa8b732 | 5605 | .run = svm_vcpu_run, |
04d2cc77 | 5606 | .handle_exit = handle_exit, |
6aa8b732 | 5607 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
5608 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
5609 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 5610 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 5611 | .set_irq = svm_set_irq, |
95ba8273 | 5612 | .set_nmi = svm_inject_nmi, |
298101da | 5613 | .queue_exception = svm_queue_exception, |
b463a6f7 | 5614 | .cancel_injection = svm_cancel_injection, |
78646121 | 5615 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 5616 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
5617 | .get_nmi_mask = svm_get_nmi_mask, |
5618 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
5619 | .enable_nmi_window = enable_nmi_window, |
5620 | .enable_irq_window = enable_irq_window, | |
5621 | .update_cr8_intercept = update_cr8_intercept, | |
8d14695f | 5622 | .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode, |
d62caabb AS |
5623 | .get_enable_apicv = svm_get_enable_apicv, |
5624 | .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl, | |
c7c9c56c | 5625 | .load_eoi_exitmap = svm_load_eoi_exitmap, |
44a95dae SS |
5626 | .hwapic_irr_update = svm_hwapic_irr_update, |
5627 | .hwapic_isr_update = svm_hwapic_isr_update, | |
be8ca170 | 5628 | .apicv_post_state_restore = avic_post_state_restore, |
cbc94022 IE |
5629 | |
5630 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 5631 | .get_tdp_level = get_npt_level, |
4b12f0de | 5632 | .get_mt_mask = svm_get_mt_mask, |
229456fc | 5633 | |
586f9607 | 5634 | .get_exit_info = svm_get_exit_info, |
586f9607 | 5635 | |
17cc3935 | 5636 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
5637 | |
5638 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
5639 | |
5640 | .rdtscp_supported = svm_rdtscp_supported, | |
ad756a16 | 5641 | .invpcid_supported = svm_invpcid_supported, |
93c4adc7 | 5642 | .mpx_supported = svm_mpx_supported, |
55412b2e | 5643 | .xsaves_supported = svm_xsaves_supported, |
d4330ef2 JR |
5644 | |
5645 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
5646 | |
5647 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
99e3e30a ZA |
5648 | |
5649 | .write_tsc_offset = svm_write_tsc_offset, | |
1c97f0a0 JR |
5650 | |
5651 | .set_tdp_cr3 = set_tdp_cr3, | |
8a76d7f2 JR |
5652 | |
5653 | .check_intercept = svm_check_intercept, | |
a547c6db | 5654 | .handle_external_intr = svm_handle_external_intr, |
ae97a3b8 RK |
5655 | |
5656 | .sched_in = svm_sched_in, | |
25462f7f WH |
5657 | |
5658 | .pmu_ops = &amd_pmu_ops, | |
340d3bc3 | 5659 | .deliver_posted_interrupt = svm_deliver_avic_intr, |
411b44ba | 5660 | .update_pi_irte = svm_update_pi_irte, |
74f16909 | 5661 | .setup_mce = svm_setup_mce, |
0234bf88 | 5662 | |
72d7b374 | 5663 | .smi_allowed = svm_smi_allowed, |
0234bf88 LP |
5664 | .pre_enter_smm = svm_pre_enter_smm, |
5665 | .pre_leave_smm = svm_pre_leave_smm, | |
cc3d967f | 5666 | .enable_smi_window = enable_smi_window, |
6aa8b732 AK |
5667 | }; |
5668 | ||
5669 | static int __init svm_init(void) | |
5670 | { | |
cb498ea2 | 5671 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 5672 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
5673 | } |
5674 | ||
5675 | static void __exit svm_exit(void) | |
5676 | { | |
cb498ea2 | 5677 | kvm_exit(); |
6aa8b732 AK |
5678 | } |
5679 | ||
5680 | module_init(svm_init) | |
5681 | module_exit(svm_exit) |