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KVM: remove redundant prototype of load_pdptrs()
[linux-block.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
5a0e3ad6 29#include <linux/slab.h>
6aa8b732 30
e495606d 31#include <asm/desc.h>
6aa8b732 32
63d1142f 33#include <asm/virtext.h>
229456fc 34#include "trace.h"
63d1142f 35
4ecac3fd
AK		 36#define __ex(x) __kvm_handle_fault_on_reboot(x)
37
6aa8b732
AK		 38MODULE_AUTHOR("Qumranet");
39MODULE_LICENSE("GPL");
40
41#define IOPM_ALLOC_ORDER 2
42#define MSRPM_ALLOC_ORDER 1
43
6aa8b732
AK		 44#define SEG_TYPE_LDT 2
45#define SEG_TYPE_BUSY_TSS16 3
46
80b7706e
JR		 47#define SVM_FEATURE_NPT (1 << 0)
48#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 49#define SVM_FEATURE_SVML (1 << 2)
565d0998 50#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 51
410e4d57
JR		 52#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
53#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
54#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
55
24e09cbf
JR		 56#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
57
6c8166a7
AK		 58static const u32 host_save_user_msrs[] = {
59#ifdef CONFIG_X86_64
60 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
61 MSR_FS_BASE,
62#endif
63 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
64};
65
66#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
67
68struct kvm_vcpu;
69
e6aa9abd
JR		 70struct nested_state {
71 struct vmcb *hsave;
72 u64 hsave_msr;
73 u64 vmcb;
74
75 /* These are the merged vectors */
76 u32 *msrpm;
77
78 /* gpa pointers to the real vectors */
79 u64 vmcb_msrpm;
aad42c64 80
cd3ff653
JR		 81 /* A VMEXIT is required but not yet emulated */
82 bool exit_required;
83
aad42c64
JR		 84 /* cache for intercepts of the guest */
85 u16 intercept_cr_read;
86 u16 intercept_cr_write;
87 u16 intercept_dr_read;
88 u16 intercept_dr_write;
89 u32 intercept_exceptions;
90 u64 intercept;
91
e6aa9abd
JR		 92};
93
6c8166a7
AK		 94struct vcpu_svm {
95 struct kvm_vcpu vcpu;
96 struct vmcb *vmcb;
97 unsigned long vmcb_pa;
98 struct svm_cpu_data *svm_data;
99 uint64_t asid_generation;
100 uint64_t sysenter_esp;
101 uint64_t sysenter_eip;
102
103 u64 next_rip;
104
105 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
106 u64 host_gs_base;
6c8166a7
AK		 107
108 u32 *msrpm;
6c8166a7 109
e6aa9abd 110 struct nested_state nested;
6be7d306
JK		 111
112 bool nmi_singlestep;
6c8166a7
AK		 113};
114
709ddebf
JR		 115/* enable NPT for AMD64 and X86 with PAE */
116#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
117static bool npt_enabled = true;
118#else
e3da3acd 119static bool npt_enabled = false;
709ddebf 120#endif
6c7dac72
JR		 121static int npt = 1;
122
123module_param(npt, int, S_IRUGO);
e3da3acd 124
4b6e4dca 125static int nested = 1;
236de055
AG		 126module_param(nested, int, S_IRUGO);
127
44874f84 128static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 129static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 130
410e4d57 131static int nested_svm_exit_handled(struct vcpu_svm *svm);
cf74a78b 132static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 133static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
134 bool has_error_code, u32 error_code);
135
a2fa3e9f
GH		 136static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
137{
fb3f0f51 138 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 139}
140
3d6368ef
AG		 141static inline bool is_nested(struct vcpu_svm *svm)
142{
e6aa9abd 143 return svm->nested.vmcb;
3d6368ef
AG		 144}
145
2af9194d
JR		 146static inline void enable_gif(struct vcpu_svm *svm)
147{
148 svm->vcpu.arch.hflags |= HF_GIF_MASK;
149}
150
151static inline void disable_gif(struct vcpu_svm *svm)
152{
153 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
154}
155
156static inline bool gif_set(struct vcpu_svm *svm)
157{
158 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
159}
160
4866d5e3 161static unsigned long iopm_base;
6aa8b732
AK		 162
163struct kvm_ldttss_desc {
164 u16 limit0;
165 u16 base0;
166 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
167 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
168 u32 base3;
169 u32 zero1;
170} __attribute__((packed));
171
172struct svm_cpu_data {
173 int cpu;
174
5008fdf5
AK		 175 u64 asid_generation;
176 u32 max_asid;
177 u32 next_asid;
6aa8b732
AK		 178 struct kvm_ldttss_desc *tss_desc;
179
180 struct page *save_area;
181};
182
183static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 184static uint32_t svm_features;
6aa8b732
AK		 185
186struct svm_init_data {
187 int cpu;
188 int r;
189};
190
191static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
192
9d8f549d 193#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 194#define MSRS_RANGE_SIZE 2048
195#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
196
197#define MAX_INST_SIZE 15
198
80b7706e
JR		 199static inline u32 svm_has(u32 feat)
200{
201 return svm_features & feat;
202}
203
6aa8b732
AK		 204static inline void clgi(void)
205{
4ecac3fd 206 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 207}
208
209static inline void stgi(void)
210{
4ecac3fd 211 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 212}
213
214static inline void invlpga(unsigned long addr, u32 asid)
215{
4ecac3fd 216 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 217}
218
6aa8b732
AK		 219static inline void force_new_asid(struct kvm_vcpu *vcpu)
220{
a2fa3e9f 221 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 222}
223
224static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
225{
226 force_new_asid(vcpu);
227}
228
229static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
230{
709ddebf 231 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 232 efer &= ~EFER_LME;
6aa8b732 233
9962d032 234 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
f6801dff 235 vcpu->arch.efer = efer;
6aa8b732
AK		 236}
237
298101da
AK		 238static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
239 bool has_error_code, u32 error_code)
240{
241 struct vcpu_svm *svm = to_svm(vcpu);
242
cf74a78b
AG		 243 /* If we are within a nested VM we'd better #VMEXIT and let the
244 guest handle the exception */
245 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
246 return;
247
298101da
AK		 248 svm->vmcb->control.event_inj = nr
249 | SVM_EVTINJ_VALID
250 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
251 | SVM_EVTINJ_TYPE_EXEPT;
252 svm->vmcb->control.event_inj_err = error_code;
253}
254
6aa8b732
AK		 255static int is_external_interrupt(u32 info)
256{
257 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
258 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
259}
260
2809f5d2
GC		 261static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
262{
263 struct vcpu_svm *svm = to_svm(vcpu);
264 u32 ret = 0;
265
266 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
267 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
268 return ret & mask;
269}
270
271static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
272{
273 struct vcpu_svm *svm = to_svm(vcpu);
274
275 if (mask == 0)
276 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
277 else
278 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
279
280}
281
6aa8b732
AK		 282static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
283{
a2fa3e9f
GH		 284 struct vcpu_svm *svm = to_svm(vcpu);
285
286 if (!svm->next_rip) {
851ba692 287 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 288 EMULATE_DONE)
289 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 290 return;
291 }
5fdbf976
MT		 292 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
293 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
294 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 295
5fdbf976 296 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 297 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 298}
299
300static int has_svm(void)
301{
63d1142f 302 const char *msg;
6aa8b732 303
63d1142f 304 if (!cpu_has_svm(&msg)) {
ff81ff10 305 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 306 return 0;
307 }
308
6aa8b732
AK		 309 return 1;
310}
311
312static void svm_hardware_disable(void *garbage)
313{
2c8dceeb 314 cpu_svm_disable();
6aa8b732
AK		 315}
316
10474ae8 317static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 318{
319
0fe1e009 320 struct svm_cpu_data *sd;
6aa8b732 321 uint64_t efer;
89a27f4d 322 struct desc_ptr gdt_descr;
6aa8b732
AK		 323 struct desc_struct *gdt;
324 int me = raw_smp_processor_id();
325
10474ae8
AG		 326 rdmsrl(MSR_EFER, efer);
327 if (efer & EFER_SVME)
328 return -EBUSY;
329
6aa8b732 330 if (!has_svm()) {
e6732a5a
ZA		 331 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
332 me);
10474ae8 333 return -EINVAL;
6aa8b732 334 }
0fe1e009 335 sd = per_cpu(svm_data, me);
6aa8b732 336
0fe1e009 337 if (!sd) {
e6732a5a 338 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 339 me);
10474ae8 340 return -EINVAL;
6aa8b732
AK		 341 }
342
0fe1e009
TH		 343 sd->asid_generation = 1;
344 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
345 sd->next_asid = sd->max_asid + 1;
6aa8b732 346
b792c344 347 kvm_get_gdt(&gdt_descr);
89a27f4d 348 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 349 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 350
9962d032 351 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 352
d0316554 353 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8
AG		 354
355 return 0;
6aa8b732
AK		 356}
357
0da1db75
JR		 358static void svm_cpu_uninit(int cpu)
359{
0fe1e009 360 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 361
0fe1e009 362 if (!sd)
0da1db75
JR		 363 return;
364
365 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 366 __free_page(sd->save_area);
367 kfree(sd);
0da1db75
JR		 368}
369
6aa8b732
AK		 370static int svm_cpu_init(int cpu)
371{
0fe1e009 372 struct svm_cpu_data *sd;
6aa8b732
AK		 373 int r;
374
0fe1e009
TH		 375 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
376 if (!sd)
6aa8b732 377 return -ENOMEM;
0fe1e009
TH		 378 sd->cpu = cpu;
379 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 380 r = -ENOMEM;
0fe1e009 381 if (!sd->save_area)
6aa8b732
AK		 382 goto err_1;
383
0fe1e009 384 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 385
386 return 0;
387
388err_1:
0fe1e009 389 kfree(sd);
6aa8b732
AK		 390 return r;
391
392}
393
bfc733a7
RR		 394static void set_msr_interception(u32 *msrpm, unsigned msr,
395 int read, int write)
6aa8b732
AK		 396{
397 int i;
398
399 for (i = 0; i < NUM_MSR_MAPS; i++) {
400 if (msr >= msrpm_ranges[i] &&
401 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
402 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
403 msrpm_ranges[i]) * 2;
404
405 u32 *base = msrpm + (msr_offset / 32);
406 u32 msr_shift = msr_offset % 32;
407 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
408 *base = (*base & ~(0x3 << msr_shift)) |
409 (mask << msr_shift);
bfc733a7 410 return;
6aa8b732
AK		 411 }
412 }
bfc733a7 413 BUG();
6aa8b732
AK		 414}
415
f65c229c
JR		 416static void svm_vcpu_init_msrpm(u32 *msrpm)
417{
418 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
419
420#ifdef CONFIG_X86_64
421 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
422 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
423 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
424 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
425 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
426 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
427#endif
428 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
429 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
f65c229c
JR		 430}
431
24e09cbf
JR		 432static void svm_enable_lbrv(struct vcpu_svm *svm)
433{
434 u32 *msrpm = svm->msrpm;
435
436 svm->vmcb->control.lbr_ctl = 1;
437 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
438 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
439 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
440 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
441}
442
443static void svm_disable_lbrv(struct vcpu_svm *svm)
444{
445 u32 *msrpm = svm->msrpm;
446
447 svm->vmcb->control.lbr_ctl = 0;
448 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
449 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
450 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
451 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
452}
453
6aa8b732
AK		 454static __init int svm_hardware_setup(void)
455{
456 int cpu;
457 struct page *iopm_pages;
f65c229c 458 void *iopm_va;
6aa8b732
AK		 459 int r;
460
6aa8b732
AK		 461 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
462
463 if (!iopm_pages)
464 return -ENOMEM;
c8681339
AL		 465
466 iopm_va = page_address(iopm_pages);
467 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 468 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
469
50a37eb4
JR		 470 if (boot_cpu_has(X86_FEATURE_NX))
471 kvm_enable_efer_bits(EFER_NX);
472
1b2fd70c
AG		 473 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
474 kvm_enable_efer_bits(EFER_FFXSR);
475
236de055
AG		 476 if (nested) {
477 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
478 kvm_enable_efer_bits(EFER_SVME);
479 }
480
3230bb47 481 for_each_possible_cpu(cpu) {
6aa8b732
AK		 482 r = svm_cpu_init(cpu);
483 if (r)
f65c229c 484 goto err;
6aa8b732 485 }
33bd6a0b
JR		 486
487 svm_features = cpuid_edx(SVM_CPUID_FUNC);
488
e3da3acd
JR		 489 if (!svm_has(SVM_FEATURE_NPT))
490 npt_enabled = false;
491
6c7dac72
JR		 492 if (npt_enabled && !npt) {
493 printk(KERN_INFO "kvm: Nested Paging disabled\n");
494 npt_enabled = false;
495 }
496
18552672 497 if (npt_enabled) {
e3da3acd 498 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 499 kvm_enable_tdp();
5f4cb662
JR		 500 } else
501 kvm_disable_tdp();
e3da3acd 502
6aa8b732
AK		 503 return 0;
504
f65c229c 505err:
6aa8b732
AK		 506 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
507 iopm_base = 0;
508 return r;
509}
510
511static __exit void svm_hardware_unsetup(void)
512{
0da1db75
JR		 513 int cpu;
514
3230bb47 515 for_each_possible_cpu(cpu)
0da1db75
JR		 516 svm_cpu_uninit(cpu);
517
6aa8b732 518 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 519 iopm_base = 0;
6aa8b732
AK		 520}
521
522static void init_seg(struct vmcb_seg *seg)
523{
524 seg->selector = 0;
525 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
526 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
527 seg->limit = 0xffff;
528 seg->base = 0;
529}
530
531static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
532{
533 seg->selector = 0;
534 seg->attrib = SVM_SELECTOR_P_MASK | type;
535 seg->limit = 0xffff;
536 seg->base = 0;
537}
538
e6101a96 539static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 540{
e6101a96
JR		 541 struct vmcb_control_area *control = &svm->vmcb->control;
542 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 543
bff78274
AK		 544 svm->vcpu.fpu_active = 1;
545
6aa8b732
AK		 546 control->intercept_cr_read = INTERCEPT_CR0_MASK |
547 INTERCEPT_CR3_MASK |
649d6864 548 INTERCEPT_CR4_MASK;
6aa8b732
AK		 549
550 control->intercept_cr_write = INTERCEPT_CR0_MASK |
551 INTERCEPT_CR3_MASK |
80a8119c
AK		 552 INTERCEPT_CR4_MASK |
553 INTERCEPT_CR8_MASK;
6aa8b732
AK		 554
555 control->intercept_dr_read = INTERCEPT_DR0_MASK |
556 INTERCEPT_DR1_MASK |
557 INTERCEPT_DR2_MASK |
727f5a23
JK		 558 INTERCEPT_DR3_MASK |
559 INTERCEPT_DR4_MASK |
560 INTERCEPT_DR5_MASK |
561 INTERCEPT_DR6_MASK |
562 INTERCEPT_DR7_MASK;
6aa8b732
AK		 563
564 control->intercept_dr_write = INTERCEPT_DR0_MASK |
565 INTERCEPT_DR1_MASK |
566 INTERCEPT_DR2_MASK |
567 INTERCEPT_DR3_MASK |
727f5a23 568 INTERCEPT_DR4_MASK |
6aa8b732 569 INTERCEPT_DR5_MASK |
727f5a23 570 INTERCEPT_DR6_MASK |
6aa8b732
AK		 571 INTERCEPT_DR7_MASK;
572
7aa81cc0 573 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 574 (1 << UD_VECTOR) |
575 (1 << MC_VECTOR);
6aa8b732
AK		 576
577
578 control->intercept = (1ULL << INTERCEPT_INTR) |
579 (1ULL << INTERCEPT_NMI) |
0152527b 580 (1ULL << INTERCEPT_SMI) |
d225157b 581 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 582 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 583 (1ULL << INTERCEPT_INVD) |
6aa8b732 584 (1ULL << INTERCEPT_HLT) |
a7052897 585 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 586 (1ULL << INTERCEPT_INVLPGA) |
587 (1ULL << INTERCEPT_IOIO_PROT) |
588 (1ULL << INTERCEPT_MSR_PROT) |
589 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 590 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 591 (1ULL << INTERCEPT_VMRUN) |
592 (1ULL << INTERCEPT_VMMCALL) |
593 (1ULL << INTERCEPT_VMLOAD) |
594 (1ULL << INTERCEPT_VMSAVE) |
595 (1ULL << INTERCEPT_STGI) |
596 (1ULL << INTERCEPT_CLGI) |
916ce236 597 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 598 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 599 (1ULL << INTERCEPT_MONITOR) |
600 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 601
602 control->iopm_base_pa = iopm_base;
f65c229c 603 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 604 control->tsc_offset = 0;
6aa8b732
AK		 605 control->int_ctl = V_INTR_MASKING_MASK;
606
607 init_seg(&save->es);
608 init_seg(&save->ss);
609 init_seg(&save->ds);
610 init_seg(&save->fs);
611 init_seg(&save->gs);
612
613 save->cs.selector = 0xf000;
614 /* Executable/Readable Code Segment */
615 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
616 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
617 save->cs.limit = 0xffff;
d92899a0
AK		 618 /*
619 * cs.base should really be 0xffff0000, but vmx can't handle that, so
620 * be consistent with it.
621 *
622 * Replace when we have real mode working for vmx.
623 */
624 save->cs.base = 0xf0000;
6aa8b732
AK		 625
626 save->gdtr.limit = 0xffff;
627 save->idtr.limit = 0xffff;
628
629 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
630 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
631
9962d032 632 save->efer = EFER_SVME;
d77c26fc 633 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 634 save->dr7 = 0x400;
635 save->rflags = 2;
636 save->rip = 0x0000fff0;
5fdbf976 637 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 638
18fa000a
EH		 639 /* This is the guest-visible cr0 value.
640 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 641 */
18fa000a
EH		 642 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
643 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
644
66aee91a 645 save->cr4 = X86_CR4_PAE;
6aa8b732 646 /* rdx = ?? */
709ddebf
JR		 647
648 if (npt_enabled) {
649 /* Setup VMCB for Nested Paging */
650 control->nested_ctl = 1;
a7052897
MT		 651 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
652 (1ULL << INTERCEPT_INVLPG));
709ddebf 653 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 654 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
655 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 656 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 657 save->cr3 = 0;
658 save->cr4 = 0;
659 }
a79d2f18 660 force_new_asid(&svm->vcpu);
1371d904 661
e6aa9abd 662 svm->nested.vmcb = 0;
2af9194d
JR		 663 svm->vcpu.arch.hflags = 0;
664
565d0998
ML		 665 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
666 control->pause_filter_count = 3000;
667 control->intercept |= (1ULL << INTERCEPT_PAUSE);
668 }
669
2af9194d 670 enable_gif(svm);
6aa8b732
AK		 671}
672
e00c8cf2 673static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 674{
675 struct vcpu_svm *svm = to_svm(vcpu);
676
e6101a96 677 init_vmcb(svm);
70433389 678
c5af89b6 679 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 680 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 681 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
682 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 683 }
5fdbf976
MT		 684 vcpu->arch.regs_avail = ~0;
685 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 686
687 return 0;
04d2cc77
AK		 688}
689
fb3f0f51 690static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 691{
a2fa3e9f 692 struct vcpu_svm *svm;
6aa8b732 693 struct page *page;
f65c229c 694 struct page *msrpm_pages;
b286d5d8 695 struct page *hsave_page;
3d6368ef 696 struct page *nested_msrpm_pages;
fb3f0f51 697 int err;
6aa8b732 698
c16f862d 699 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 700 if (!svm) {
701 err = -ENOMEM;
702 goto out;
703 }
704
705 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
706 if (err)
707 goto free_svm;
708
b7af4043 709 err = -ENOMEM;
6aa8b732 710 page = alloc_page(GFP_KERNEL);
b7af4043 711 if (!page)
fb3f0f51 712 goto uninit;
6aa8b732 713
f65c229c
JR		 714 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
715 if (!msrpm_pages)
b7af4043 716 goto free_page1;
3d6368ef
AG		 717
718 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
719 if (!nested_msrpm_pages)
b7af4043 720 goto free_page2;
f65c229c 721
b286d5d8
AG		 722 hsave_page = alloc_page(GFP_KERNEL);
723 if (!hsave_page)
b7af4043
TY		 724 goto free_page3;
725
e6aa9abd 726 svm->nested.hsave = page_address(hsave_page);
b286d5d8 727
b7af4043
TY		 728 svm->msrpm = page_address(msrpm_pages);
729 svm_vcpu_init_msrpm(svm->msrpm);
730
e6aa9abd 731 svm->nested.msrpm = page_address(nested_msrpm_pages);
3d6368ef 732
a2fa3e9f
GH		 733 svm->vmcb = page_address(page);
734 clear_page(svm->vmcb);
735 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
736 svm->asid_generation = 0;
e6101a96 737 init_vmcb(svm);
a2fa3e9f 738
fb3f0f51 739 fx_init(&svm->vcpu);
ad312c7c 740 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 741 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 742 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 743
fb3f0f51 744 return &svm->vcpu;
36241b8c 745
b7af4043
TY		 746free_page3:
747 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
748free_page2:
749 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
750free_page1:
751 __free_page(page);
fb3f0f51
RR		 752uninit:
753 kvm_vcpu_uninit(&svm->vcpu);
754free_svm:
a4770347 755 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 756out:
757 return ERR_PTR(err);
6aa8b732
AK		 758}
759
760static void svm_free_vcpu(struct kvm_vcpu *vcpu)
761{
a2fa3e9f
GH		 762 struct vcpu_svm *svm = to_svm(vcpu);
763
fb3f0f51 764 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 765 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 766 __free_page(virt_to_page(svm->nested.hsave));
767 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 768 kvm_vcpu_uninit(vcpu);
a4770347 769 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 770}
771
15ad7146 772static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 773{
a2fa3e9f 774 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 775 int i;
0cc5064d 776
0cc5064d 777 if (unlikely(cpu != vcpu->cpu)) {
e935d48e 778 u64 delta;
0cc5064d 779
953899b6
JR		 780 if (check_tsc_unstable()) {
781 /*
782 * Make sure that the guest sees a monotonically
783 * increasing TSC.
784 */
785 delta = vcpu->arch.host_tsc - native_read_tsc();
786 svm->vmcb->control.tsc_offset += delta;
787 if (is_nested(svm))
788 svm->nested.hsave->control.tsc_offset += delta;
789 }
0cc5064d 790 vcpu->cpu = cpu;
2f599714 791 kvm_migrate_timers(vcpu);
4b656b12 792 svm->asid_generation = 0;
0cc5064d 793 }
94dfbdb3
AL		 794
795 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 796 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 797}
798
799static void svm_vcpu_put(struct kvm_vcpu *vcpu)
800{
a2fa3e9f 801 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 802 int i;
803
e1beb1d3 804 ++vcpu->stat.host_state_reload;
94dfbdb3 805 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 806 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 807
e935d48e 808 vcpu->arch.host_tsc = native_read_tsc();
6aa8b732
AK		 809}
810
6aa8b732
AK		 811static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
812{
a2fa3e9f 813 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 814}
815
816static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
817{
a2fa3e9f 818 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 819}
820
6de4f3ad
AK		 821static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
822{
823 switch (reg) {
824 case VCPU_EXREG_PDPTR:
825 BUG_ON(!npt_enabled);
826 load_pdptrs(vcpu, vcpu->arch.cr3);
827 break;
828 default:
829 BUG();
830 }
831}
832
f0b85051
AG		 833static void svm_set_vintr(struct vcpu_svm *svm)
834{
835 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
836}
837
838static void svm_clear_vintr(struct vcpu_svm *svm)
839{
840 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
841}
842
6aa8b732
AK		 843static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
844{
a2fa3e9f 845 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 846
847 switch (seg) {
848 case VCPU_SREG_CS: return &save->cs;
849 case VCPU_SREG_DS: return &save->ds;
850 case VCPU_SREG_ES: return &save->es;
851 case VCPU_SREG_FS: return &save->fs;
852 case VCPU_SREG_GS: return &save->gs;
853 case VCPU_SREG_SS: return &save->ss;
854 case VCPU_SREG_TR: return &save->tr;
855 case VCPU_SREG_LDTR: return &save->ldtr;
856 }
857 BUG();
8b6d44c7 858 return NULL;
6aa8b732
AK		 859}
860
861static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
862{
863 struct vmcb_seg *s = svm_seg(vcpu, seg);
864
865 return s->base;
866}
867
868static void svm_get_segment(struct kvm_vcpu *vcpu,
869 struct kvm_segment *var, int seg)
870{
871 struct vmcb_seg *s = svm_seg(vcpu, seg);
872
873 var->base = s->base;
874 var->limit = s->limit;
875 var->selector = s->selector;
876 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
877 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
878 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
879 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
880 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
881 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
882 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
883 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 884
19bca6ab
AP		 885 /* AMD's VMCB does not have an explicit unusable field, so emulate it
886 * for cross vendor migration purposes by "not present"
887 */
888 var->unusable = !var->present || (var->type == 0);
889
1fbdc7a5
AP		 890 switch (seg) {
891 case VCPU_SREG_CS:
892 /*
893 * SVM always stores 0 for the 'G' bit in the CS selector in
894 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
895 * Intel's VMENTRY has a check on the 'G' bit.
896 */
25022acc 897 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 898 break;
899 case VCPU_SREG_TR:
900 /*
901 * Work around a bug where the busy flag in the tr selector
902 * isn't exposed
903 */
c0d09828 904 var->type |= 0x2;
1fbdc7a5
AP		 905 break;
906 case VCPU_SREG_DS:
907 case VCPU_SREG_ES:
908 case VCPU_SREG_FS:
909 case VCPU_SREG_GS:
910 /*
911 * The accessed bit must always be set in the segment
912 * descriptor cache, although it can be cleared in the
913 * descriptor, the cached bit always remains at 1. Since
914 * Intel has a check on this, set it here to support
915 * cross-vendor migration.
916 */
917 if (!var->unusable)
918 var->type |= 0x1;
919 break;
b586eb02
AP		 920 case VCPU_SREG_SS:
921 /* On AMD CPUs sometimes the DB bit in the segment
922 * descriptor is left as 1, although the whole segment has
923 * been made unusable. Clear it here to pass an Intel VMX
924 * entry check when cross vendor migrating.
925 */
926 if (var->unusable)
927 var->db = 0;
928 break;
1fbdc7a5 929 }
6aa8b732
AK		 930}
931
2e4d2653
IE		 932static int svm_get_cpl(struct kvm_vcpu *vcpu)
933{
934 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
935
936 return save->cpl;
937}
938
89a27f4d 939static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 940{
a2fa3e9f
GH		 941 struct vcpu_svm *svm = to_svm(vcpu);
942
89a27f4d
GN		 943 dt->size = svm->vmcb->save.idtr.limit;
944 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 945}
946
89a27f4d 947static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 948{
a2fa3e9f
GH		 949 struct vcpu_svm *svm = to_svm(vcpu);
950
89a27f4d
GN		 951 svm->vmcb->save.idtr.limit = dt->size;
952 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 953}
954
89a27f4d 955static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 956{
a2fa3e9f
GH		 957 struct vcpu_svm *svm = to_svm(vcpu);
958
89a27f4d
GN		 959 dt->size = svm->vmcb->save.gdtr.limit;
960 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 961}
962
89a27f4d 963static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 964{
a2fa3e9f
GH		 965 struct vcpu_svm *svm = to_svm(vcpu);
966
89a27f4d
GN		 967 svm->vmcb->save.gdtr.limit = dt->size;
968 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 969}
970
e8467fda
AK		 971static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
972{
973}
974
25c4c276 975static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 976{
977}
978
d225157b
AK		 979static void update_cr0_intercept(struct vcpu_svm *svm)
980{
981 ulong gcr0 = svm->vcpu.arch.cr0;
982 u64 *hcr0 = &svm->vmcb->save.cr0;
983
984 if (!svm->vcpu.fpu_active)
985 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
986 else
987 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
988 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
989
990
991 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
992 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
993 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
994 } else {
995 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
996 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
997 }
998}
999
6aa8b732
AK		 1000static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1001{
a2fa3e9f
GH		 1002 struct vcpu_svm *svm = to_svm(vcpu);
1003
05b3e0c2 1004#ifdef CONFIG_X86_64
f6801dff 1005 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1006 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1007 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1008 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1009 }
1010
d77c26fc 1011 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1012 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1013 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1014 }
1015 }
1016#endif
ad312c7c 1017 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1018
1019 if (!npt_enabled)
1020 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1021
1022 if (!vcpu->fpu_active)
334df50a 1023 cr0 |= X86_CR0_TS;
709ddebf
JR		 1024 /*
1025 * re-enable caching here because the QEMU bios
1026 * does not do it - this results in some delay at
1027 * reboot
1028 */
1029 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1030 svm->vmcb->save.cr0 = cr0;
d225157b 1031 update_cr0_intercept(svm);
6aa8b732
AK		 1032}
1033
1034static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1035{
6394b649 1036 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1037 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1038
1039 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1040 force_new_asid(vcpu);
6394b649 1041
ec077263
JR		 1042 vcpu->arch.cr4 = cr4;
1043 if (!npt_enabled)
1044 cr4 |= X86_CR4_PAE;
6394b649 1045 cr4 |= host_cr4_mce;
ec077263 1046 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1047}
1048
1049static void svm_set_segment(struct kvm_vcpu *vcpu,
1050 struct kvm_segment *var, int seg)
1051{
a2fa3e9f 1052 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1053 struct vmcb_seg *s = svm_seg(vcpu, seg);
1054
1055 s->base = var->base;
1056 s->limit = var->limit;
1057 s->selector = var->selector;
1058 if (var->unusable)
1059 s->attrib = 0;
1060 else {
1061 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1062 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1063 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1064 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1065 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1066 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1067 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1068 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1069 }
1070 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1071 svm->vmcb->save.cpl
1072 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1073 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1074
1075}
1076
44c11430 1077static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1078{
d0bfb940
JK		 1079 struct vcpu_svm *svm = to_svm(vcpu);
1080
d0bfb940
JK		 1081 svm->vmcb->control.intercept_exceptions &=
1082 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1083
6be7d306 1084 if (svm->nmi_singlestep)
44c11430
GN		 1085 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1086
d0bfb940
JK		 1087 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1088 if (vcpu->guest_debug &
1089 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1090 svm->vmcb->control.intercept_exceptions |=
1091 1 << DB_VECTOR;
1092 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1093 svm->vmcb->control.intercept_exceptions |=
1094 1 << BP_VECTOR;
1095 } else
1096 vcpu->guest_debug = 0;
44c11430
GN		 1097}
1098
355be0b9 1099static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1100{
44c11430
GN		 1101 struct vcpu_svm *svm = to_svm(vcpu);
1102
ae675ef0
JK		 1103 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1104 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1105 else
1106 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1107
355be0b9 1108 update_db_intercept(vcpu);
6aa8b732
AK		 1109}
1110
1111static void load_host_msrs(struct kvm_vcpu *vcpu)
1112{
94dfbdb3 1113#ifdef CONFIG_X86_64
a2fa3e9f 1114 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1115#endif
6aa8b732
AK		 1116}
1117
1118static void save_host_msrs(struct kvm_vcpu *vcpu)
1119{
94dfbdb3 1120#ifdef CONFIG_X86_64
a2fa3e9f 1121 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1122#endif
6aa8b732
AK		 1123}
1124
0fe1e009 1125static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1126{
0fe1e009
TH		 1127 if (sd->next_asid > sd->max_asid) {
1128 ++sd->asid_generation;
1129 sd->next_asid = 1;
a2fa3e9f 1130 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1131 }
1132
0fe1e009
TH		 1133 svm->asid_generation = sd->asid_generation;
1134 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1135}
1136
c76de350 1137static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest)
6aa8b732 1138{
42dbaa5a 1139 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a
JK		 1140
1141 switch (dr) {
1142 case 0 ... 3:
c76de350 1143 *dest = vcpu->arch.db[dr];
42dbaa5a 1144 break;
c76de350
JK		 1145 case 4:
1146 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1147 return EMULATE_FAIL; /* will re-inject UD */
1148 /* fall through */
42dbaa5a
JK		 1149 case 6:
1150 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1151 *dest = vcpu->arch.dr6;
42dbaa5a 1152 else
c76de350 1153 *dest = svm->vmcb->save.dr6;
42dbaa5a 1154 break;
c76de350
JK		 1155 case 5:
1156 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1157 return EMULATE_FAIL; /* will re-inject UD */
1158 /* fall through */
42dbaa5a
JK		 1159 case 7:
1160 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1161 *dest = vcpu->arch.dr7;
42dbaa5a 1162 else
c76de350 1163 *dest = svm->vmcb->save.dr7;
42dbaa5a 1164 break;
42dbaa5a
JK		 1165 }
1166
c76de350 1167 return EMULATE_DONE;
6aa8b732
AK		 1168}
1169
c76de350 1170static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value)
6aa8b732 1171{
a2fa3e9f
GH		 1172 struct vcpu_svm *svm = to_svm(vcpu);
1173
6aa8b732
AK		 1174 switch (dr) {
1175 case 0 ... 3:
42dbaa5a
JK		 1176 vcpu->arch.db[dr] = value;
1177 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1178 vcpu->arch.eff_db[dr] = value;
c76de350
JK		 1179 break;
1180 case 4:
1181 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1182 return EMULATE_FAIL; /* will re-inject UD */
1183 /* fall through */
42dbaa5a 1184 case 6:
42dbaa5a 1185 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
c76de350
JK		 1186 break;
1187 case 5:
1188 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1189 return EMULATE_FAIL; /* will re-inject UD */
1190 /* fall through */
42dbaa5a 1191 case 7:
42dbaa5a
JK		 1192 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1193 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1194 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1195 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1196 }
c76de350 1197 break;
6aa8b732 1198 }
c76de350
JK		 1199
1200 return EMULATE_DONE;
6aa8b732
AK		 1201}
1202
851ba692 1203static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1204{
6aa8b732
AK		 1205 u64 fault_address;
1206 u32 error_code;
6aa8b732 1207
a2fa3e9f
GH		 1208 fault_address = svm->vmcb->control.exit_info_2;
1209 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1210
229456fc 1211 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1212 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1213 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1214 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1215}
1216
851ba692 1217static int db_interception(struct vcpu_svm *svm)
d0bfb940 1218{
851ba692
AK		 1219 struct kvm_run *kvm_run = svm->vcpu.run;
1220
d0bfb940 1221 if (!(svm->vcpu.guest_debug &
44c11430 1222 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1223 !svm->nmi_singlestep) {
d0bfb940
JK		 1224 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1225 return 1;
1226 }
44c11430 1227
6be7d306
JK		 1228 if (svm->nmi_singlestep) {
1229 svm->nmi_singlestep = false;
44c11430
GN		 1230 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1231 svm->vmcb->save.rflags &=
1232 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1233 update_db_intercept(&svm->vcpu);
1234 }
1235
1236 if (svm->vcpu.guest_debug &
1237 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1238 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1239 kvm_run->debug.arch.pc =
1240 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1241 kvm_run->debug.arch.exception = DB_VECTOR;
1242 return 0;
1243 }
1244
1245 return 1;
d0bfb940
JK		 1246}
1247
851ba692 1248static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1249{
851ba692
AK		 1250 struct kvm_run *kvm_run = svm->vcpu.run;
1251
d0bfb940
JK		 1252 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1253 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1254 kvm_run->debug.arch.exception = BP_VECTOR;
1255 return 0;
1256}
1257
851ba692 1258static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1259{
1260 int er;
1261
851ba692 1262 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1263 if (er != EMULATE_DONE)
7ee5d940 1264 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1265 return 1;
1266}
1267
6b52d186 1268static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1269{
6b52d186 1270 struct vcpu_svm *svm = to_svm(vcpu);
a2fa3e9f 1271 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
e756fc62 1272 svm->vcpu.fpu_active = 1;
d225157b 1273 update_cr0_intercept(svm);
6b52d186 1274}
a2fa3e9f 1275
6b52d186
AK		 1276static int nm_interception(struct vcpu_svm *svm)
1277{
1278 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1279 return 1;
7807fa6c
AL		 1280}
1281
851ba692 1282static int mc_interception(struct vcpu_svm *svm)
53371b50
JR		 1283{
1284 /*
1285 * On an #MC intercept the MCE handler is not called automatically in
1286 * the host. So do it by hand here.
1287 */
1288 asm volatile (
1289 "int $0x12\n");
1290 /* not sure if we ever come back to this point */
1291
1292 return 1;
1293}
1294
851ba692 1295static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1296{
851ba692
AK		 1297 struct kvm_run *kvm_run = svm->vcpu.run;
1298
46fe4ddd
JR		 1299 /*
1300 * VMCB is undefined after a SHUTDOWN intercept
1301 * so reinitialize it.
1302 */
a2fa3e9f 1303 clear_page(svm->vmcb);
e6101a96 1304 init_vmcb(svm);
46fe4ddd
JR		 1305
1306 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1307 return 0;
1308}
1309
851ba692 1310static int io_interception(struct vcpu_svm *svm)
6aa8b732 1311{
d77c26fc 1312 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1313 int size, in, string;
039576c0 1314 unsigned port;
6aa8b732 1315
e756fc62 1316 ++svm->vcpu.stat.io_exits;
6aa8b732 1317
a2fa3e9f 1318 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1319
e70669ab
LV		 1320 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1321
1322 if (string) {
3427318f 1323 if (emulate_instruction(&svm->vcpu,
851ba692 1324 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1325 return 0;
1326 return 1;
1327 }
1328
039576c0
AK		 1329 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1330 port = io_info >> 16;
1331 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1332
e93f36bc 1333 skip_emulated_instruction(&svm->vcpu);
851ba692 1334 return kvm_emulate_pio(&svm->vcpu, in, size, port);
6aa8b732
AK		 1335}
1336
851ba692 1337static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1338{
1339 return 1;
1340}
1341
851ba692 1342static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1343{
1344 ++svm->vcpu.stat.irq_exits;
1345 return 1;
1346}
1347
851ba692 1348static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1349{
1350 return 1;
1351}
1352
851ba692 1353static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1354{
5fdbf976 1355 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1356 skip_emulated_instruction(&svm->vcpu);
1357 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1358}
1359
851ba692 1360static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1361{
5fdbf976 1362 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1363 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1364 kvm_emulate_hypercall(&svm->vcpu);
1365 return 1;
02e235bc
AK		 1366}
1367
c0725420
AG		 1368static int nested_svm_check_permissions(struct vcpu_svm *svm)
1369{
f6801dff 1370 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1371 || !is_paging(&svm->vcpu)) {
1372 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1373 return 1;
1374 }
1375
1376 if (svm->vmcb->save.cpl) {
1377 kvm_inject_gp(&svm->vcpu, 0);
1378 return 1;
1379 }
1380
1381 return 0;
1382}
1383
cf74a78b
AG		 1384static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1385 bool has_error_code, u32 error_code)
1386{
0295ad7d
JR		 1387 if (!is_nested(svm))
1388 return 0;
cf74a78b 1389
0295ad7d
JR		 1390 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1391 svm->vmcb->control.exit_code_hi = 0;
1392 svm->vmcb->control.exit_info_1 = error_code;
1393 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1394
410e4d57 1395 return nested_svm_exit_handled(svm);
cf74a78b
AG		 1396}
1397
1398static inline int nested_svm_intr(struct vcpu_svm *svm)
1399{
26666957
JR		 1400 if (!is_nested(svm))
1401 return 0;
cf74a78b 1402
26666957
JR		 1403 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1404 return 0;
cf74a78b 1405
26666957
JR		 1406 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1407 return 0;
cf74a78b 1408
26666957
JR		 1409 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1410
cd3ff653
JR		 1411 if (svm->nested.intercept & 1ULL) {
1412 /*
1413 * The #vmexit can't be emulated here directly because this
1414 * code path runs with irqs and preemtion disabled. A
1415 * #vmexit emulation might sleep. Only signal request for
1416 * the #vmexit here.
1417 */
1418 svm->nested.exit_required = true;
236649de 1419 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
26666957 1420 return 1;
cf74a78b
AG		 1421 }
1422
1423 return 0;
1424}
1425
34f80cfa
JR		 1426static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1427{
1428 struct page *page;
1429
34f80cfa 1430 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1431 if (is_error_page(page))
1432 goto error;
1433
1434 return kmap_atomic(page, idx);
1435
1436error:
1437 kvm_release_page_clean(page);
1438 kvm_inject_gp(&svm->vcpu, 0);
1439
1440 return NULL;
1441}
1442
1443static void nested_svm_unmap(void *addr, enum km_type idx)
1444{
1445 struct page *page;
1446
1447 if (!addr)
1448 return;
1449
1450 page = kmap_atomic_to_page(addr);
1451
1452 kunmap_atomic(addr, idx);
1453 kvm_release_page_dirty(page);
1454}
1455
3d62d9aa 1456static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1457{
4c2161ae 1458 u32 param = svm->vmcb->control.exit_info_1 & 1;
3d62d9aa
JR		 1459 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1460 bool ret = false;
1461 u32 t0, t1;
1462 u8 *msrpm;
4c2161ae 1463
3d62d9aa
JR		 1464 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1465 return false;
1466
1467 msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1468
1469 if (!msrpm)
1470 goto out;
4c2161ae
JR		 1471
1472 switch (msr) {
1473 case 0 ... 0x1fff:
1474 t0 = (msr * 2) % 8;
1475 t1 = msr / 8;
1476 break;
1477 case 0xc0000000 ... 0xc0001fff:
1478 t0 = (8192 + msr - 0xc0000000) * 2;
1479 t1 = (t0 / 8);
1480 t0 %= 8;
1481 break;
1482 case 0xc0010000 ... 0xc0011fff:
1483 t0 = (16384 + msr - 0xc0010000) * 2;
1484 t1 = (t0 / 8);
1485 t0 %= 8;
1486 break;
1487 default:
3d62d9aa
JR		 1488 ret = true;
1489 goto out;
4c2161ae 1490 }
4c2161ae 1491
3d62d9aa
JR		 1492 ret = msrpm[t1] & ((1 << param) << t0);
1493
1494out:
1495 nested_svm_unmap(msrpm, KM_USER0);
1496
1497 return ret;
4c2161ae
JR		 1498}
1499
410e4d57 1500static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1501{
cf74a78b 1502 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1503
410e4d57
JR		 1504 switch (exit_code) {
1505 case SVM_EXIT_INTR:
1506 case SVM_EXIT_NMI:
1507 return NESTED_EXIT_HOST;
cf74a78b 1508 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1509 case SVM_EXIT_NPF:
1510 if (npt_enabled)
1511 return NESTED_EXIT_HOST;
1512 break;
1513 /* When we're shadowing, trap PFs */
1514 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1515 if (!npt_enabled)
1516 return NESTED_EXIT_HOST;
1517 break;
1518 default:
1519 break;
cf74a78b
AG		 1520 }
1521
410e4d57
JR		 1522 return NESTED_EXIT_CONTINUE;
1523}
1524
1525/*
1526 * If this function returns true, this #vmexit was already handled
1527 */
1528static int nested_svm_exit_handled(struct vcpu_svm *svm)
1529{
1530 u32 exit_code = svm->vmcb->control.exit_code;
1531 int vmexit = NESTED_EXIT_HOST;
1532
cf74a78b 1533 switch (exit_code) {
9c4e40b9 1534 case SVM_EXIT_MSR:
3d62d9aa 1535 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1536 break;
cf74a78b
AG		 1537 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1538 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1539 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1540 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1541 break;
1542 }
1543 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1544 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1545 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1546 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1547 break;
1548 }
1549 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1550 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1551 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1552 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1553 break;
1554 }
1555 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1556 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1557 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1558 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1559 break;
1560 }
1561 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1562 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1563 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1564 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1565 break;
1566 }
1567 default: {
1568 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1569 if (svm->nested.intercept & exit_bits)
410e4d57 1570 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1571 }
1572 }
1573
410e4d57 1574 if (vmexit == NESTED_EXIT_DONE) {
9c4e40b9
JR		 1575 nested_svm_vmexit(svm);
1576 }
1577
1578 return vmexit;
cf74a78b
AG		 1579}
1580
0460a979
JR		 1581static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1582{
1583 struct vmcb_control_area *dst = &dst_vmcb->control;
1584 struct vmcb_control_area *from = &from_vmcb->control;
1585
1586 dst->intercept_cr_read = from->intercept_cr_read;
1587 dst->intercept_cr_write = from->intercept_cr_write;
1588 dst->intercept_dr_read = from->intercept_dr_read;
1589 dst->intercept_dr_write = from->intercept_dr_write;
1590 dst->intercept_exceptions = from->intercept_exceptions;
1591 dst->intercept = from->intercept;
1592 dst->iopm_base_pa = from->iopm_base_pa;
1593 dst->msrpm_base_pa = from->msrpm_base_pa;
1594 dst->tsc_offset = from->tsc_offset;
1595 dst->asid = from->asid;
1596 dst->tlb_ctl = from->tlb_ctl;
1597 dst->int_ctl = from->int_ctl;
1598 dst->int_vector = from->int_vector;
1599 dst->int_state = from->int_state;
1600 dst->exit_code = from->exit_code;
1601 dst->exit_code_hi = from->exit_code_hi;
1602 dst->exit_info_1 = from->exit_info_1;
1603 dst->exit_info_2 = from->exit_info_2;
1604 dst->exit_int_info = from->exit_int_info;
1605 dst->exit_int_info_err = from->exit_int_info_err;
1606 dst->nested_ctl = from->nested_ctl;
1607 dst->event_inj = from->event_inj;
1608 dst->event_inj_err = from->event_inj_err;
1609 dst->nested_cr3 = from->nested_cr3;
1610 dst->lbr_ctl = from->lbr_ctl;
1611}
1612
34f80cfa 1613static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1614{
34f80cfa 1615 struct vmcb *nested_vmcb;
e6aa9abd 1616 struct vmcb *hsave = svm->nested.hsave;
33740e40 1617 struct vmcb *vmcb = svm->vmcb;
cf74a78b 1618
17897f36
JR		 1619 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1620 vmcb->control.exit_info_1,
1621 vmcb->control.exit_info_2,
1622 vmcb->control.exit_int_info,
1623 vmcb->control.exit_int_info_err);
1624
34f80cfa
JR		 1625 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1626 if (!nested_vmcb)
1627 return 1;
1628
cf74a78b 1629 /* Give the current vmcb to the guest */
33740e40
JR		 1630 disable_gif(svm);
1631
1632 nested_vmcb->save.es = vmcb->save.es;
1633 nested_vmcb->save.cs = vmcb->save.cs;
1634 nested_vmcb->save.ss = vmcb->save.ss;
1635 nested_vmcb->save.ds = vmcb->save.ds;
1636 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1637 nested_vmcb->save.idtr = vmcb->save.idtr;
1638 if (npt_enabled)
1639 nested_vmcb->save.cr3 = vmcb->save.cr3;
1640 nested_vmcb->save.cr2 = vmcb->save.cr2;
1641 nested_vmcb->save.rflags = vmcb->save.rflags;
1642 nested_vmcb->save.rip = vmcb->save.rip;
1643 nested_vmcb->save.rsp = vmcb->save.rsp;
1644 nested_vmcb->save.rax = vmcb->save.rax;
1645 nested_vmcb->save.dr7 = vmcb->save.dr7;
1646 nested_vmcb->save.dr6 = vmcb->save.dr6;
1647 nested_vmcb->save.cpl = vmcb->save.cpl;
1648
1649 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1650 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1651 nested_vmcb->control.int_state = vmcb->control.int_state;
1652 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1653 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1654 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1655 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1656 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1657 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
8d23c466
AG		 1658
1659 /*
1660 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1661 * to make sure that we do not lose injected events. So check event_inj
1662 * here and copy it to exit_int_info if it is valid.
1663 * Exit_int_info and event_inj can't be both valid because the case
1664 * below only happens on a VMRUN instruction intercept which has
1665 * no valid exit_int_info set.
1666 */
1667 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1668 struct vmcb_control_area *nc = &nested_vmcb->control;
1669
1670 nc->exit_int_info = vmcb->control.event_inj;
1671 nc->exit_int_info_err = vmcb->control.event_inj_err;
1672 }
1673
33740e40
JR		 1674 nested_vmcb->control.tlb_ctl = 0;
1675 nested_vmcb->control.event_inj = 0;
1676 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1677
1678 /* We always set V_INTR_MASKING and remember the old value in hflags */
1679 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1680 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1681
cf74a78b 1682 /* Restore the original control entries */
0460a979 1683 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1684
219b65dc
AG		 1685 kvm_clear_exception_queue(&svm->vcpu);
1686 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1687
1688 /* Restore selected save entries */
1689 svm->vmcb->save.es = hsave->save.es;
1690 svm->vmcb->save.cs = hsave->save.cs;
1691 svm->vmcb->save.ss = hsave->save.ss;
1692 svm->vmcb->save.ds = hsave->save.ds;
1693 svm->vmcb->save.gdtr = hsave->save.gdtr;
1694 svm->vmcb->save.idtr = hsave->save.idtr;
1695 svm->vmcb->save.rflags = hsave->save.rflags;
1696 svm_set_efer(&svm->vcpu, hsave->save.efer);
1697 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1698 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1699 if (npt_enabled) {
1700 svm->vmcb->save.cr3 = hsave->save.cr3;
1701 svm->vcpu.arch.cr3 = hsave->save.cr3;
1702 } else {
1703 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1704 }
1705 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1706 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1707 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1708 svm->vmcb->save.dr7 = 0;
1709 svm->vmcb->save.cpl = 0;
1710 svm->vmcb->control.exit_int_info = 0;
1711
cf74a78b 1712 /* Exit nested SVM mode */
e6aa9abd 1713 svm->nested.vmcb = 0;
cf74a78b 1714
34f80cfa 1715 nested_svm_unmap(nested_vmcb, KM_USER0);
cf74a78b
AG		 1716
1717 kvm_mmu_reset_context(&svm->vcpu);
1718 kvm_mmu_load(&svm->vcpu);
1719
1720 return 0;
1721}
3d6368ef 1722
9738b2c9 1723static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1724{
9738b2c9 1725 u32 *nested_msrpm;
3d6368ef 1726 int i;
9738b2c9
JR		 1727
1728 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1729 if (!nested_msrpm)
1730 return false;
1731
3d6368ef 1732 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
e6aa9abd 1733 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
9738b2c9 1734
e6aa9abd 1735 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
3d6368ef 1736
9738b2c9
JR		 1737 nested_svm_unmap(nested_msrpm, KM_USER0);
1738
1739 return true;
3d6368ef
AG		 1740}
1741
9738b2c9 1742static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 1743{
9738b2c9 1744 struct vmcb *nested_vmcb;
e6aa9abd 1745 struct vmcb *hsave = svm->nested.hsave;
defbba56 1746 struct vmcb *vmcb = svm->vmcb;
3d6368ef 1747
9738b2c9
JR		 1748 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1749 if (!nested_vmcb)
1750 return false;
1751
3d6368ef 1752 /* nested_vmcb is our indicator if nested SVM is activated */
e6aa9abd 1753 svm->nested.vmcb = svm->vmcb->save.rax;
3d6368ef 1754
0ac406de
JR		 1755 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1756 nested_vmcb->save.rip,
1757 nested_vmcb->control.int_ctl,
1758 nested_vmcb->control.event_inj,
1759 nested_vmcb->control.nested_ctl);
1760
3d6368ef 1761 /* Clear internal status */
219b65dc
AG		 1762 kvm_clear_exception_queue(&svm->vcpu);
1763 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef
AG		 1764
1765 /* Save the old vmcb, so we don't need to pick what we save, but
1766 can restore everything when a VMEXIT occurs */
defbba56
JR		 1767 hsave->save.es = vmcb->save.es;
1768 hsave->save.cs = vmcb->save.cs;
1769 hsave->save.ss = vmcb->save.ss;
1770 hsave->save.ds = vmcb->save.ds;
1771 hsave->save.gdtr = vmcb->save.gdtr;
1772 hsave->save.idtr = vmcb->save.idtr;
f6801dff 1773 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 1774 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 1775 hsave->save.cr4 = svm->vcpu.arch.cr4;
1776 hsave->save.rflags = vmcb->save.rflags;
1777 hsave->save.rip = svm->next_rip;
1778 hsave->save.rsp = vmcb->save.rsp;
1779 hsave->save.rax = vmcb->save.rax;
1780 if (npt_enabled)
1781 hsave->save.cr3 = vmcb->save.cr3;
1782 else
1783 hsave->save.cr3 = svm->vcpu.arch.cr3;
1784
0460a979 1785 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 1786
1787 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1788 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1789 else
1790 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1791
1792 /* Load the nested guest state */
1793 svm->vmcb->save.es = nested_vmcb->save.es;
1794 svm->vmcb->save.cs = nested_vmcb->save.cs;
1795 svm->vmcb->save.ss = nested_vmcb->save.ss;
1796 svm->vmcb->save.ds = nested_vmcb->save.ds;
1797 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1798 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1799 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1800 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1801 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1802 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1803 if (npt_enabled) {
1804 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1805 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1806 } else {
1807 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1808 kvm_mmu_reset_context(&svm->vcpu);
1809 }
defbba56 1810 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 1811 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1812 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1813 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1814 /* In case we don't even reach vcpu_run, the fields are not updated */
1815 svm->vmcb->save.rax = nested_vmcb->save.rax;
1816 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1817 svm->vmcb->save.rip = nested_vmcb->save.rip;
1818 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1819 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1820 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1821
1822 /* We don't want a nested guest to be more powerful than the guest,
1823 so all intercepts are ORed */
1824 svm->vmcb->control.intercept_cr_read |=
1825 nested_vmcb->control.intercept_cr_read;
1826 svm->vmcb->control.intercept_cr_write |=
1827 nested_vmcb->control.intercept_cr_write;
1828 svm->vmcb->control.intercept_dr_read |=
1829 nested_vmcb->control.intercept_dr_read;
1830 svm->vmcb->control.intercept_dr_write |=
1831 nested_vmcb->control.intercept_dr_write;
1832 svm->vmcb->control.intercept_exceptions |=
1833 nested_vmcb->control.intercept_exceptions;
1834
1835 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1836
e6aa9abd 1837 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
3d6368ef 1838
aad42c64
JR		 1839 /* cache intercepts */
1840 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1841 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1842 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1843 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1844 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1845 svm->nested.intercept = nested_vmcb->control.intercept;
1846
3d6368ef 1847 force_new_asid(&svm->vcpu);
3d6368ef 1848 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 1849 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1850 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1851 else
1852 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1853
3d6368ef
AG		 1854 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1855 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1856 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 1857 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1858 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1859
9738b2c9
JR		 1860 nested_svm_unmap(nested_vmcb, KM_USER0);
1861
2af9194d 1862 enable_gif(svm);
3d6368ef 1863
9738b2c9 1864 return true;
3d6368ef
AG		 1865}
1866
9966bf68 1867static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 1868{
1869 to_vmcb->save.fs = from_vmcb->save.fs;
1870 to_vmcb->save.gs = from_vmcb->save.gs;
1871 to_vmcb->save.tr = from_vmcb->save.tr;
1872 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1873 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1874 to_vmcb->save.star = from_vmcb->save.star;
1875 to_vmcb->save.lstar = from_vmcb->save.lstar;
1876 to_vmcb->save.cstar = from_vmcb->save.cstar;
1877 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1878 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1879 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1880 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 1881}
1882
851ba692 1883static int vmload_interception(struct vcpu_svm *svm)
5542675b 1884{
9966bf68
JR		 1885 struct vmcb *nested_vmcb;
1886
5542675b
AG		 1887 if (nested_svm_check_permissions(svm))
1888 return 1;
1889
1890 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1891 skip_emulated_instruction(&svm->vcpu);
1892
9966bf68
JR		 1893 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1894 if (!nested_vmcb)
1895 return 1;
1896
1897 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1898 nested_svm_unmap(nested_vmcb, KM_USER0);
5542675b
AG		 1899
1900 return 1;
1901}
1902
851ba692 1903static int vmsave_interception(struct vcpu_svm *svm)
5542675b 1904{
9966bf68
JR		 1905 struct vmcb *nested_vmcb;
1906
5542675b
AG		 1907 if (nested_svm_check_permissions(svm))
1908 return 1;
1909
1910 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1911 skip_emulated_instruction(&svm->vcpu);
1912
9966bf68
JR		 1913 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1914 if (!nested_vmcb)
1915 return 1;
1916
1917 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1918 nested_svm_unmap(nested_vmcb, KM_USER0);
5542675b
AG		 1919
1920 return 1;
1921}
1922
851ba692 1923static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 1924{
3d6368ef
AG		 1925 if (nested_svm_check_permissions(svm))
1926 return 1;
1927
1928 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1929 skip_emulated_instruction(&svm->vcpu);
1930
9738b2c9 1931 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 1932 return 1;
1933
9738b2c9 1934 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 1935 goto failed;
1936
1937 return 1;
1938
1939failed:
1940
1941 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
1942 svm->vmcb->control.exit_code_hi = 0;
1943 svm->vmcb->control.exit_info_1 = 0;
1944 svm->vmcb->control.exit_info_2 = 0;
1945
1946 nested_svm_vmexit(svm);
3d6368ef
AG		 1947
1948 return 1;
1949}
1950
851ba692 1951static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 1952{
1953 if (nested_svm_check_permissions(svm))
1954 return 1;
1955
1956 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1957 skip_emulated_instruction(&svm->vcpu);
1958
2af9194d 1959 enable_gif(svm);
1371d904
AG		 1960
1961 return 1;
1962}
1963
851ba692 1964static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 1965{
1966 if (nested_svm_check_permissions(svm))
1967 return 1;
1968
1969 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1970 skip_emulated_instruction(&svm->vcpu);
1971
2af9194d 1972 disable_gif(svm);
1371d904
AG		 1973
1974 /* After a CLGI no interrupts should come */
1975 svm_clear_vintr(svm);
1976 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1977
1978 return 1;
1979}
1980
851ba692 1981static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 1982{
1983 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 1984
ec1ff790
JR		 1985 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
1986 vcpu->arch.regs[VCPU_REGS_RAX]);
1987
ff092385
AG		 1988 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1989 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1990
1991 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1992 skip_emulated_instruction(&svm->vcpu);
1993 return 1;
1994}
1995
532a46b9
JR		 1996static int skinit_interception(struct vcpu_svm *svm)
1997{
1998 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
1999
2000 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2001 return 1;
2002}
2003
851ba692 2004static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2005{
7ee5d940 2006 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2007 return 1;
2008}
2009
851ba692 2010static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2011{
37817f29 2012 u16 tss_selector;
64a7ec06
GN		 2013 int reason;
2014 int int_type = svm->vmcb->control.exit_int_info &
2015 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2016 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2017 uint32_t type =
2018 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2019 uint32_t idt_v =
2020 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 2021
2022 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2023
37817f29
IE		 2024 if (svm->vmcb->control.exit_info_2 &
2025 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2026 reason = TASK_SWITCH_IRET;
2027 else if (svm->vmcb->control.exit_info_2 &
2028 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2029 reason = TASK_SWITCH_JMP;
fe8e7f83 2030 else if (idt_v)
64a7ec06
GN		 2031 reason = TASK_SWITCH_GATE;
2032 else
2033 reason = TASK_SWITCH_CALL;
2034
fe8e7f83
GN		 2035 if (reason == TASK_SWITCH_GATE) {
2036 switch (type) {
2037 case SVM_EXITINTINFO_TYPE_NMI:
2038 svm->vcpu.arch.nmi_injected = false;
2039 break;
2040 case SVM_EXITINTINFO_TYPE_EXEPT:
2041 kvm_clear_exception_queue(&svm->vcpu);
2042 break;
2043 case SVM_EXITINTINFO_TYPE_INTR:
2044 kvm_clear_interrupt_queue(&svm->vcpu);
2045 break;
2046 default:
2047 break;
2048 }
2049 }
64a7ec06 2050
8317c298
GN		 2051 if (reason != TASK_SWITCH_GATE ||
2052 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2053 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2054 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2055 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2056
2057 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2058}
2059
851ba692 2060static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2061{
5fdbf976 2062 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2063 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2064 return 1;
6aa8b732
AK		 2065}
2066
851ba692 2067static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2068{
2069 ++svm->vcpu.stat.nmi_window_exits;
2070 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2071 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2072 return 1;
2073}
2074
851ba692 2075static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2076{
851ba692 2077 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
a7052897
MT		 2078 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2079 return 1;
2080}
2081
851ba692 2082static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2083{
851ba692 2084 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
b8688d51 2085 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2086 return 1;
2087}
2088
851ba692 2089static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2090{
851ba692
AK		 2091 struct kvm_run *kvm_run = svm->vcpu.run;
2092
0a5fff19
GN		 2093 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2094 /* instruction emulation calls kvm_set_cr8() */
851ba692 2095 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2096 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2097 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2098 return 1;
95ba8273 2099 }
0a5fff19
GN		 2100 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2101 return 1;
1d075434
JR		 2102 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2103 return 0;
2104}
2105
6aa8b732
AK		 2106static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2107{
a2fa3e9f
GH		 2108 struct vcpu_svm *svm = to_svm(vcpu);
2109
6aa8b732 2110 switch (ecx) {
af24a4e4 2111 case MSR_IA32_TSC: {
20824f30 2112 u64 tsc_offset;
6aa8b732 2113
20824f30
JR		 2114 if (is_nested(svm))
2115 tsc_offset = svm->nested.hsave->control.tsc_offset;
2116 else
2117 tsc_offset = svm->vmcb->control.tsc_offset;
2118
2119 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2120 break;
2121 }
0e859cac 2122 case MSR_K6_STAR:
a2fa3e9f 2123 *data = svm->vmcb->save.star;
6aa8b732 2124 break;
0e859cac 2125#ifdef CONFIG_X86_64
6aa8b732 2126 case MSR_LSTAR:
a2fa3e9f 2127 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2128 break;
2129 case MSR_CSTAR:
a2fa3e9f 2130 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2131 break;
2132 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2133 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2134 break;
2135 case MSR_SYSCALL_MASK:
a2fa3e9f 2136 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2137 break;
2138#endif
2139 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2140 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2141 break;
2142 case MSR_IA32_SYSENTER_EIP:
017cb99e 2143 *data = svm->sysenter_eip;
6aa8b732
AK		 2144 break;
2145 case MSR_IA32_SYSENTER_ESP:
017cb99e 2146 *data = svm->sysenter_esp;
6aa8b732 2147 break;
a2938c80
JR		 2148 /* Nobody will change the following 5 values in the VMCB so
2149 we can safely return them on rdmsr. They will always be 0
2150 until LBRV is implemented. */
2151 case MSR_IA32_DEBUGCTLMSR:
2152 *data = svm->vmcb->save.dbgctl;
2153 break;
2154 case MSR_IA32_LASTBRANCHFROMIP:
2155 *data = svm->vmcb->save.br_from;
2156 break;
2157 case MSR_IA32_LASTBRANCHTOIP:
2158 *data = svm->vmcb->save.br_to;
2159 break;
2160 case MSR_IA32_LASTINTFROMIP:
2161 *data = svm->vmcb->save.last_excp_from;
2162 break;
2163 case MSR_IA32_LASTINTTOIP:
2164 *data = svm->vmcb->save.last_excp_to;
2165 break;
b286d5d8 2166 case MSR_VM_HSAVE_PA:
e6aa9abd 2167 *data = svm->nested.hsave_msr;
b286d5d8 2168 break;
eb6f302e
JR		 2169 case MSR_VM_CR:
2170 *data = 0;
2171 break;
c8a73f18
AG		 2172 case MSR_IA32_UCODE_REV:
2173 *data = 0x01000065;
2174 break;
6aa8b732 2175 default:
3bab1f5d 2176 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2177 }
2178 return 0;
2179}
2180
851ba692 2181static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2182{
ad312c7c 2183 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2184 u64 data;
2185
59200273
AK		 2186 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2187 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2188 kvm_inject_gp(&svm->vcpu, 0);
59200273 2189 } else {
229456fc 2190 trace_kvm_msr_read(ecx, data);
af9ca2d7 2191
5fdbf976 2192 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2193 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2194 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2195 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2196 }
2197 return 1;
2198}
2199
2200static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2201{
a2fa3e9f
GH		 2202 struct vcpu_svm *svm = to_svm(vcpu);
2203
6aa8b732 2204 switch (ecx) {
af24a4e4 2205 case MSR_IA32_TSC: {
20824f30
JR		 2206 u64 tsc_offset = data - native_read_tsc();
2207 u64 g_tsc_offset = 0;
2208
2209 if (is_nested(svm)) {
2210 g_tsc_offset = svm->vmcb->control.tsc_offset -
2211 svm->nested.hsave->control.tsc_offset;
2212 svm->nested.hsave->control.tsc_offset = tsc_offset;
2213 }
2214
2215 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
6aa8b732 2216
6aa8b732
AK		 2217 break;
2218 }
0e859cac 2219 case MSR_K6_STAR:
a2fa3e9f 2220 svm->vmcb->save.star = data;
6aa8b732 2221 break;
49b14f24 2222#ifdef CONFIG_X86_64
6aa8b732 2223 case MSR_LSTAR:
a2fa3e9f 2224 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2225 break;
2226 case MSR_CSTAR:
a2fa3e9f 2227 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2228 break;
2229 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2230 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2231 break;
2232 case MSR_SYSCALL_MASK:
a2fa3e9f 2233 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2234 break;
2235#endif
2236 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2237 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2238 break;
2239 case MSR_IA32_SYSENTER_EIP:
017cb99e 2240 svm->sysenter_eip = data;
a2fa3e9f 2241 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2242 break;
2243 case MSR_IA32_SYSENTER_ESP:
017cb99e 2244 svm->sysenter_esp = data;
a2fa3e9f 2245 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2246 break;
a2938c80 2247 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2248 if (!svm_has(SVM_FEATURE_LBRV)) {
2249 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2250 __func__, data);
24e09cbf
JR		 2251 break;
2252 }
2253 if (data & DEBUGCTL_RESERVED_BITS)
2254 return 1;
2255
2256 svm->vmcb->save.dbgctl = data;
2257 if (data & (1ULL<<0))
2258 svm_enable_lbrv(svm);
2259 else
2260 svm_disable_lbrv(svm);
a2938c80 2261 break;
b286d5d8 2262 case MSR_VM_HSAVE_PA:
e6aa9abd 2263 svm->nested.hsave_msr = data;
62b9abaa 2264 break;
3c5d0a44
AG		 2265 case MSR_VM_CR:
2266 case MSR_VM_IGNNE:
3c5d0a44
AG		 2267 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2268 break;
6aa8b732 2269 default:
3bab1f5d 2270 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2271 }
2272 return 0;
2273}
2274
851ba692 2275static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2276{
ad312c7c 2277 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2278 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2279 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2280
af9ca2d7 2281
5fdbf976 2282 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2283 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2284 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2285 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2286 } else {
2287 trace_kvm_msr_write(ecx, data);
e756fc62 2288 skip_emulated_instruction(&svm->vcpu);
59200273 2289 }
6aa8b732
AK		 2290 return 1;
2291}
2292
851ba692 2293static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2294{
e756fc62 2295 if (svm->vmcb->control.exit_info_1)
851ba692 2296 return wrmsr_interception(svm);
6aa8b732 2297 else
851ba692 2298 return rdmsr_interception(svm);
6aa8b732
AK		 2299}
2300
851ba692 2301static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2302{
851ba692
AK		 2303 struct kvm_run *kvm_run = svm->vcpu.run;
2304
f0b85051 2305 svm_clear_vintr(svm);
85f455f7 2306 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2307 /*
2308 * If the user space waits to inject interrupts, exit as soon as
2309 * possible
2310 */
8061823a
GN		 2311 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2312 kvm_run->request_interrupt_window &&
2313 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2314 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2315 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2316 return 0;
2317 }
2318
2319 return 1;
2320}
2321
565d0998
ML		 2322static int pause_interception(struct vcpu_svm *svm)
2323{
2324 kvm_vcpu_on_spin(&(svm->vcpu));
2325 return 1;
2326}
2327
851ba692 2328static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
6aa8b732
AK		 2329 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2330 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2331 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2332 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2333 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
6aa8b732
AK		 2334 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2335 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2336 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2337 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2338 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2339 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2340 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2341 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2342 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2343 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2344 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2345 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2346 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2347 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2348 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2349 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2350 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2351 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2352 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2353 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2354 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2355 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2356 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2357 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2358 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2359 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2360 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2361 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2362 [SVM_EXIT_SMI] = nop_on_interception,
2363 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2364 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2365 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2366 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2367 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2368 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2369 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2370 [SVM_EXIT_HLT] = halt_interception,
a7052897 2371 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2372 [SVM_EXIT_INVLPGA] = invlpga_interception,
6aa8b732
AK		 2373 [SVM_EXIT_IOIO] = io_interception,
2374 [SVM_EXIT_MSR] = msr_interception,
2375 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2376 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2377 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2378 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2379 [SVM_EXIT_VMLOAD] = vmload_interception,
2380 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2381 [SVM_EXIT_STGI] = stgi_interception,
2382 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2383 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2384 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2385 [SVM_EXIT_MONITOR] = invalid_op_interception,
2386 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2387 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2388};
2389
851ba692 2390static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2391{
04d2cc77 2392 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2393 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2394 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2395
229456fc 2396 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
af9ca2d7 2397
cd3ff653
JR		 2398 if (unlikely(svm->nested.exit_required)) {
2399 nested_svm_vmexit(svm);
2400 svm->nested.exit_required = false;
2401
2402 return 1;
2403 }
2404
cf74a78b 2405 if (is_nested(svm)) {
410e4d57
JR		 2406 int vmexit;
2407
d8cabddf
JR		 2408 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2409 svm->vmcb->control.exit_info_1,
2410 svm->vmcb->control.exit_info_2,
2411 svm->vmcb->control.exit_int_info,
2412 svm->vmcb->control.exit_int_info_err);
2413
410e4d57
JR		 2414 vmexit = nested_svm_exit_special(svm);
2415
2416 if (vmexit == NESTED_EXIT_CONTINUE)
2417 vmexit = nested_svm_exit_handled(svm);
2418
2419 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2420 return 1;
cf74a78b
AG		 2421 }
2422
a5c3832d
JR		 2423 svm_complete_interrupts(svm);
2424
888f9f3e 2425 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
709ddebf 2426 vcpu->arch.cr0 = svm->vmcb->save.cr0;
888f9f3e 2427 if (npt_enabled)
709ddebf 2428 vcpu->arch.cr3 = svm->vmcb->save.cr3;
04d2cc77
AK		 2429
2430 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2431 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2432 kvm_run->fail_entry.hardware_entry_failure_reason
2433 = svm->vmcb->control.exit_code;
2434 return 0;
2435 }
2436
a2fa3e9f 2437 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2438 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2439 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2440 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2441 "exit_code 0x%x\n",
b8688d51 2442 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2443 exit_code);
2444
9d8f549d 2445 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2446 || !svm_exit_handlers[exit_code]) {
6aa8b732 2447 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2448 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2449 return 0;
2450 }
2451
851ba692 2452 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2453}
2454
2455static void reload_tss(struct kvm_vcpu *vcpu)
2456{
2457 int cpu = raw_smp_processor_id();
2458
0fe1e009
TH		 2459 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2460 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2461 load_TR_desc();
2462}
2463
e756fc62 2464static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2465{
2466 int cpu = raw_smp_processor_id();
2467
0fe1e009 2468 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2469
a2fa3e9f 2470 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2471 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2472 if (svm->asid_generation != sd->asid_generation)
2473 new_asid(svm, sd);
6aa8b732
AK		 2474}
2475
95ba8273
GN		 2476static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2477{
2478 struct vcpu_svm *svm = to_svm(vcpu);
2479
2480 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2481 vcpu->arch.hflags |= HF_NMI_MASK;
2482 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2483 ++vcpu->stat.nmi_injections;
2484}
6aa8b732 2485
85f455f7 2486static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2487{
2488 struct vmcb_control_area *control;
2489
229456fc 2490 trace_kvm_inj_virq(irq);
af9ca2d7 2491
fa89a817 2492 ++svm->vcpu.stat.irq_injections;
e756fc62 2493 control = &svm->vmcb->control;
85f455f7 2494 control->int_vector = irq;
6aa8b732
AK		 2495 control->int_ctl &= ~V_INTR_PRIO_MASK;
2496 control->int_ctl |= V_IRQ_MASK |
2497 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2498}
2499
66fd3f7f 2500static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2501{
2502 struct vcpu_svm *svm = to_svm(vcpu);
2503
2af9194d 2504 BUG_ON(!(gif_set(svm)));
cf74a78b 2505
219b65dc
AG		 2506 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2507 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2508}
2509
95ba8273 2510static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2511{
2512 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2513
95ba8273 2514 if (irr == -1)
aaacfc9a
JR		 2515 return;
2516
95ba8273
GN		 2517 if (tpr >= irr)
2518 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2519}
aaacfc9a 2520
95ba8273
GN		 2521static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2522{
2523 struct vcpu_svm *svm = to_svm(vcpu);
2524 struct vmcb *vmcb = svm->vmcb;
2525 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2526 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2527}
2528
3cfc3092
JK		 2529static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2530{
2531 struct vcpu_svm *svm = to_svm(vcpu);
2532
2533 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2534}
2535
2536static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2537{
2538 struct vcpu_svm *svm = to_svm(vcpu);
2539
2540 if (masked) {
2541 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2542 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2543 } else {
2544 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2545 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2546 }
2547}
2548
78646121
GN		 2549static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2550{
2551 struct vcpu_svm *svm = to_svm(vcpu);
2552 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 2553 int ret;
2554
2555 if (!gif_set(svm) ||
2556 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2557 return 0;
2558
2559 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2560
2561 if (is_nested(svm))
2562 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2563
2564 return ret;
78646121
GN		 2565}
2566
9222be18 2567static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2568{
219b65dc 2569 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc
AG		 2570
2571 nested_svm_intr(svm);
2572
2573 /* In case GIF=0 we can't rely on the CPU to tell us when
2574 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2575 * The next time we get that intercept, this function will be
2576 * called again though and we'll get the vintr intercept. */
2af9194d 2577 if (gif_set(svm)) {
219b65dc
AG		 2578 svm_set_vintr(svm);
2579 svm_inject_irq(svm, 0x0);
2580 }
85f455f7
ED		 2581}
2582
95ba8273 2583static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2584{
04d2cc77 2585 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2586
44c11430
GN		 2587 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2588 == HF_NMI_MASK)
2589 return; /* IRET will cause a vm exit */
2590
2591 /* Something prevents NMI from been injected. Single step over
2592 possible problem (IRET or exception injection or interrupt
2593 shadow) */
6be7d306 2594 svm->nmi_singlestep = true;
44c11430
GN		 2595 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2596 update_db_intercept(vcpu);
c1150d8c
DL		 2597}
2598
cbc94022
IE		 2599static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2600{
2601 return 0;
2602}
2603
d9e368d6
AK		 2604static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2605{
2606 force_new_asid(vcpu);
2607}
2608
04d2cc77
AK		 2609static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2610{
2611}
2612
d7bf8221
JR		 2613static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2614{
2615 struct vcpu_svm *svm = to_svm(vcpu);
2616
2617 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2618 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2619 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2620 }
2621}
2622
649d6864
JR		 2623static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2624{
2625 struct vcpu_svm *svm = to_svm(vcpu);
2626 u64 cr8;
2627
649d6864
JR		 2628 cr8 = kvm_get_cr8(vcpu);
2629 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2630 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2631}
2632
9222be18
GN		 2633static void svm_complete_interrupts(struct vcpu_svm *svm)
2634{
2635 u8 vector;
2636 int type;
2637 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2638
44c11430
GN		 2639 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2640 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2641
9222be18
GN		 2642 svm->vcpu.arch.nmi_injected = false;
2643 kvm_clear_exception_queue(&svm->vcpu);
2644 kvm_clear_interrupt_queue(&svm->vcpu);
2645
2646 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2647 return;
2648
2649 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2650 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2651
2652 switch (type) {
2653 case SVM_EXITINTINFO_TYPE_NMI:
2654 svm->vcpu.arch.nmi_injected = true;
2655 break;
2656 case SVM_EXITINTINFO_TYPE_EXEPT:
2657 /* In case of software exception do not reinject an exception
2658 vector, but re-execute and instruction instead */
219b65dc
AG		 2659 if (is_nested(svm))
2660 break;
66fd3f7f 2661 if (kvm_exception_is_soft(vector))
9222be18
GN		 2662 break;
2663 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2664 u32 err = svm->vmcb->control.exit_int_info_err;
2665 kvm_queue_exception_e(&svm->vcpu, vector, err);
2666
2667 } else
2668 kvm_queue_exception(&svm->vcpu, vector);
2669 break;
2670 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2671 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2672 break;
2673 default:
2674 break;
2675 }
2676}
2677
80e31d4f
AK		 2678#ifdef CONFIG_X86_64
2679#define R "r"
2680#else
2681#define R "e"
2682#endif
2683
851ba692 2684static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 2685{
a2fa3e9f 2686 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2687 u16 fs_selector;
2688 u16 gs_selector;
2689 u16 ldt_selector;
d9e368d6 2690
cd3ff653
JR		 2691 /*
2692 * A vmexit emulation is required before the vcpu can be executed
2693 * again.
2694 */
2695 if (unlikely(svm->nested.exit_required))
2696 return;
2697
5fdbf976
MT		 2698 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2699 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2700 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2701
e756fc62 2702 pre_svm_run(svm);
6aa8b732 2703
649d6864
JR		 2704 sync_lapic_to_cr8(vcpu);
2705
6aa8b732 2706 save_host_msrs(vcpu);
d6e88aec
AK		 2707 fs_selector = kvm_read_fs();
2708 gs_selector = kvm_read_gs();
2709 ldt_selector = kvm_read_ldt();
cda0ffdd 2710 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2711 /* required for live migration with NPT */
2712 if (npt_enabled)
2713 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2714
04d2cc77
AK		 2715 clgi();
2716
2717 local_irq_enable();
36241b8c 2718
6aa8b732 2719 asm volatile (
80e31d4f
AK		 2720 "push %%"R"bp; \n\t"
2721 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2722 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2723 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2724 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2725 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2726 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2727#ifdef CONFIG_X86_64
fb3f0f51
RR		 2728 "mov %c[r8](%[svm]), %%r8 \n\t"
2729 "mov %c[r9](%[svm]), %%r9 \n\t"
2730 "mov %c[r10](%[svm]), %%r10 \n\t"
2731 "mov %c[r11](%[svm]), %%r11 \n\t"
2732 "mov %c[r12](%[svm]), %%r12 \n\t"
2733 "mov %c[r13](%[svm]), %%r13 \n\t"
2734 "mov %c[r14](%[svm]), %%r14 \n\t"
2735 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2736#endif
2737
6aa8b732 2738 /* Enter guest mode */
80e31d4f
AK		 2739 "push %%"R"ax \n\t"
2740 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2741 __ex(SVM_VMLOAD) "\n\t"
2742 __ex(SVM_VMRUN) "\n\t"
2743 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2744 "pop %%"R"ax \n\t"
6aa8b732
AK		 2745
2746 /* Save guest registers, load host registers */
80e31d4f
AK		 2747 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2748 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2749 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2750 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2751 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2752 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2753#ifdef CONFIG_X86_64
fb3f0f51
RR		 2754 "mov %%r8, %c[r8](%[svm]) \n\t"
2755 "mov %%r9, %c[r9](%[svm]) \n\t"
2756 "mov %%r10, %c[r10](%[svm]) \n\t"
2757 "mov %%r11, %c[r11](%[svm]) \n\t"
2758 "mov %%r12, %c[r12](%[svm]) \n\t"
2759 "mov %%r13, %c[r13](%[svm]) \n\t"
2760 "mov %%r14, %c[r14](%[svm]) \n\t"
2761 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2762#endif
80e31d4f 2763 "pop %%"R"bp"
6aa8b732 2764 :
fb3f0f51 2765 : [svm]"a"(svm),
6aa8b732 2766 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2767 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2768 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2769 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2770 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2771 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2772 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2773#ifdef CONFIG_X86_64
ad312c7c
ZX		 2774 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2775 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2776 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2777 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2778 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2779 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2780 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2781 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2782#endif
54a08c04 2783 : "cc", "memory"
80e31d4f 2784 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2785#ifdef CONFIG_X86_64
54a08c04
LV		 2786 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2787#endif
2788 );
6aa8b732 2789
ad312c7c 2790 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2791 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2792 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2793 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2794
d6e88aec
AK		 2795 kvm_load_fs(fs_selector);
2796 kvm_load_gs(gs_selector);
2797 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2798 load_host_msrs(vcpu);
2799
2800 reload_tss(vcpu);
2801
56ba47dd
AK		 2802 local_irq_disable();
2803
2804 stgi();
2805
d7bf8221
JR		 2806 sync_cr8_to_lapic(vcpu);
2807
a2fa3e9f 2808 svm->next_rip = 0;
9222be18 2809
6de4f3ad
AK		 2810 if (npt_enabled) {
2811 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2812 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2813 }
6aa8b732
AK		 2814}
2815
80e31d4f
AK		 2816#undef R
2817
6aa8b732
AK		 2818static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2819{
a2fa3e9f
GH		 2820 struct vcpu_svm *svm = to_svm(vcpu);
2821
709ddebf
JR		 2822 if (npt_enabled) {
2823 svm->vmcb->control.nested_cr3 = root;
2824 force_new_asid(vcpu);
2825 return;
2826 }
2827
a2fa3e9f 2828 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 2829 force_new_asid(vcpu);
2830}
2831
6aa8b732
AK		 2832static int is_disabled(void)
2833{
6031a61c
JR		 2834 u64 vm_cr;
2835
2836 rdmsrl(MSR_VM_CR, vm_cr);
2837 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2838 return 1;
2839
6aa8b732
AK		 2840 return 0;
2841}
2842
102d8325
IM		 2843static void
2844svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2845{
2846 /*
2847 * Patch in the VMMCALL instruction:
2848 */
2849 hypercall[0] = 0x0f;
2850 hypercall[1] = 0x01;
2851 hypercall[2] = 0xd9;
102d8325
IM		 2852}
2853
002c7f7c
YS		 2854static void svm_check_processor_compat(void *rtn)
2855{
2856 *(int *)rtn = 0;
2857}
2858
774ead3a
AK		 2859static bool svm_cpu_has_accelerated_tpr(void)
2860{
2861 return false;
2862}
2863
67253af5
SY		 2864static int get_npt_level(void)
2865{
2866#ifdef CONFIG_X86_64
2867 return PT64_ROOT_LEVEL;
2868#else
2869 return PT32E_ROOT_LEVEL;
2870#endif
2871}
2872
4b12f0de 2873static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 2874{
2875 return 0;
2876}
2877
0e851880
SY		 2878static void svm_cpuid_update(struct kvm_vcpu *vcpu)
2879{
2880}
2881
229456fc
MT		 2882static const struct trace_print_flags svm_exit_reasons_str[] = {
2883 { SVM_EXIT_READ_CR0, "read_cr0" },
2884 { SVM_EXIT_READ_CR3, "read_cr3" },
2885 { SVM_EXIT_READ_CR4, "read_cr4" },
2886 { SVM_EXIT_READ_CR8, "read_cr8" },
2887 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2888 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2889 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2890 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2891 { SVM_EXIT_READ_DR0, "read_dr0" },
2892 { SVM_EXIT_READ_DR1, "read_dr1" },
2893 { SVM_EXIT_READ_DR2, "read_dr2" },
2894 { SVM_EXIT_READ_DR3, "read_dr3" },
2895 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2896 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2897 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2898 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2899 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2900 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2901 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2902 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2903 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2904 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2905 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2906 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2907 { SVM_EXIT_INTR, "interrupt" },
2908 { SVM_EXIT_NMI, "nmi" },
2909 { SVM_EXIT_SMI, "smi" },
2910 { SVM_EXIT_INIT, "init" },
2911 { SVM_EXIT_VINTR, "vintr" },
2912 { SVM_EXIT_CPUID, "cpuid" },
2913 { SVM_EXIT_INVD, "invd" },
2914 { SVM_EXIT_HLT, "hlt" },
2915 { SVM_EXIT_INVLPG, "invlpg" },
2916 { SVM_EXIT_INVLPGA, "invlpga" },
2917 { SVM_EXIT_IOIO, "io" },
2918 { SVM_EXIT_MSR, "msr" },
2919 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2920 { SVM_EXIT_SHUTDOWN, "shutdown" },
2921 { SVM_EXIT_VMRUN, "vmrun" },
2922 { SVM_EXIT_VMMCALL, "hypercall" },
2923 { SVM_EXIT_VMLOAD, "vmload" },
2924 { SVM_EXIT_VMSAVE, "vmsave" },
2925 { SVM_EXIT_STGI, "stgi" },
2926 { SVM_EXIT_CLGI, "clgi" },
2927 { SVM_EXIT_SKINIT, "skinit" },
2928 { SVM_EXIT_WBINVD, "wbinvd" },
2929 { SVM_EXIT_MONITOR, "monitor" },
2930 { SVM_EXIT_MWAIT, "mwait" },
2931 { SVM_EXIT_NPF, "npf" },
2932 { -1, NULL }
2933};
2934
17cc3935 2935static int svm_get_lpage_level(void)
344f414f 2936{
17cc3935 2937 return PT_PDPE_LEVEL;
344f414f
JR		 2938}
2939
4e47c7a6
SY		 2940static bool svm_rdtscp_supported(void)
2941{
2942 return false;
2943}
2944
02daab21
AK		 2945static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
2946{
2947 struct vcpu_svm *svm = to_svm(vcpu);
2948
d225157b 2949 update_cr0_intercept(svm);
02daab21 2950 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
02daab21
AK		 2951}
2952
cbdd1bea 2953static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 2954 .cpu_has_kvm_support = has_svm,
2955 .disabled_by_bios = is_disabled,
2956 .hardware_setup = svm_hardware_setup,
2957 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 2958 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 2959 .hardware_enable = svm_hardware_enable,
2960 .hardware_disable = svm_hardware_disable,
774ead3a 2961 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 2962
2963 .vcpu_create = svm_create_vcpu,
2964 .vcpu_free = svm_free_vcpu,
04d2cc77 2965 .vcpu_reset = svm_vcpu_reset,
6aa8b732 2966
04d2cc77 2967 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 2968 .vcpu_load = svm_vcpu_load,
2969 .vcpu_put = svm_vcpu_put,
2970
2971 .set_guest_debug = svm_guest_debug,
2972 .get_msr = svm_get_msr,
2973 .set_msr = svm_set_msr,
2974 .get_segment_base = svm_get_segment_base,
2975 .get_segment = svm_get_segment,
2976 .set_segment = svm_set_segment,
2e4d2653 2977 .get_cpl = svm_get_cpl,
1747fb71 2978 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 2979 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 2980 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 2981 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 2982 .set_cr3 = svm_set_cr3,
2983 .set_cr4 = svm_set_cr4,
2984 .set_efer = svm_set_efer,
2985 .get_idt = svm_get_idt,
2986 .set_idt = svm_set_idt,
2987 .get_gdt = svm_get_gdt,
2988 .set_gdt = svm_set_gdt,
2989 .get_dr = svm_get_dr,
2990 .set_dr = svm_set_dr,
6de4f3ad 2991 .cache_reg = svm_cache_reg,
6aa8b732
AK		 2992 .get_rflags = svm_get_rflags,
2993 .set_rflags = svm_set_rflags,
6b52d186 2994 .fpu_activate = svm_fpu_activate,
02daab21 2995 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 2996
6aa8b732 2997 .tlb_flush = svm_flush_tlb,
6aa8b732 2998
6aa8b732 2999 .run = svm_vcpu_run,
04d2cc77 3000 .handle_exit = handle_exit,
6aa8b732 3001 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3002 .set_interrupt_shadow = svm_set_interrupt_shadow,
3003 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3004 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3005 .set_irq = svm_set_irq,
95ba8273 3006 .set_nmi = svm_inject_nmi,
298101da 3007 .queue_exception = svm_queue_exception,
78646121 3008 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3009 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3010 .get_nmi_mask = svm_get_nmi_mask,
3011 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3012 .enable_nmi_window = enable_nmi_window,
3013 .enable_irq_window = enable_irq_window,
3014 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3015
3016 .set_tss_addr = svm_set_tss_addr,
67253af5 3017 .get_tdp_level = get_npt_level,
4b12f0de 3018 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3019
3020 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3021 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3022
3023 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3024
3025 .rdtscp_supported = svm_rdtscp_supported,
6aa8b732
AK		 3026};
3027
3028static int __init svm_init(void)
3029{
cb498ea2 3030 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 3031 THIS_MODULE);
6aa8b732
AK		 3032}
3033
3034static void __exit svm_exit(void)
3035{
cb498ea2 3036 kvm_exit();
6aa8b732
AK		 3037}
3038
3039module_init(svm_init)
3040module_exit(svm_exit)
Linux 6.x block layer and io_uring tree(s)