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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
6aa8b732 AK |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * AMD SVM support | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 8 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
9 | * |
10 | * Authors: | |
11 | * Yaniv Kamay <yaniv@qumranet.com> | |
12 | * Avi Kivity <avi@qumranet.com> | |
6aa8b732 | 13 | */ |
44a95dae SS |
14 | |
15 | #define pr_fmt(fmt) "SVM: " fmt | |
16 | ||
edf88417 AK |
17 | #include <linux/kvm_host.h> |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
5fdbf976 | 21 | #include "kvm_cache_regs.h" |
fe4c7b19 | 22 | #include "x86.h" |
66f7b72e | 23 | #include "cpuid.h" |
25462f7f | 24 | #include "pmu.h" |
e495606d | 25 | |
6aa8b732 | 26 | #include <linux/module.h> |
ae759544 | 27 | #include <linux/mod_devicetable.h> |
9d8f549d | 28 | #include <linux/kernel.h> |
6aa8b732 AK |
29 | #include <linux/vmalloc.h> |
30 | #include <linux/highmem.h> | |
e8edc6e0 | 31 | #include <linux/sched.h> |
af658dca | 32 | #include <linux/trace_events.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
5881f737 SS |
34 | #include <linux/amd-iommu.h> |
35 | #include <linux/hashtable.h> | |
c207aee4 | 36 | #include <linux/frame.h> |
e9df0942 | 37 | #include <linux/psp-sev.h> |
1654efcb | 38 | #include <linux/file.h> |
89c50580 BS |
39 | #include <linux/pagemap.h> |
40 | #include <linux/swap.h> | |
33af3a7e | 41 | #include <linux/rwsem.h> |
6aa8b732 | 42 | |
8221c137 | 43 | #include <asm/apic.h> |
1018faa6 | 44 | #include <asm/perf_event.h> |
67ec6607 | 45 | #include <asm/tlbflush.h> |
e495606d | 46 | #include <asm/desc.h> |
facb0139 | 47 | #include <asm/debugreg.h> |
631bc487 | 48 | #include <asm/kvm_para.h> |
411b44ba | 49 | #include <asm/irq_remapping.h> |
28a27752 | 50 | #include <asm/spec-ctrl.h> |
6aa8b732 | 51 | |
63d1142f | 52 | #include <asm/virtext.h> |
229456fc | 53 | #include "trace.h" |
63d1142f | 54 | |
4ecac3fd AK |
55 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
56 | ||
6aa8b732 AK |
57 | MODULE_AUTHOR("Qumranet"); |
58 | MODULE_LICENSE("GPL"); | |
59 | ||
ae759544 JT |
60 | static const struct x86_cpu_id svm_cpu_id[] = { |
61 | X86_FEATURE_MATCH(X86_FEATURE_SVM), | |
62 | {} | |
63 | }; | |
64 | MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id); | |
65 | ||
6aa8b732 AK |
66 | #define IOPM_ALLOC_ORDER 2 |
67 | #define MSRPM_ALLOC_ORDER 1 | |
68 | ||
6aa8b732 AK |
69 | #define SEG_TYPE_LDT 2 |
70 | #define SEG_TYPE_BUSY_TSS16 3 | |
71 | ||
6bc31bdc AP |
72 | #define SVM_FEATURE_LBRV (1 << 1) |
73 | #define SVM_FEATURE_SVML (1 << 2) | |
ddce97aa AP |
74 | #define SVM_FEATURE_TSC_RATE (1 << 4) |
75 | #define SVM_FEATURE_VMCB_CLEAN (1 << 5) | |
76 | #define SVM_FEATURE_FLUSH_ASID (1 << 6) | |
77 | #define SVM_FEATURE_DECODE_ASSIST (1 << 7) | |
6bc31bdc | 78 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) |
80b7706e | 79 | |
340d3bc3 SS |
80 | #define SVM_AVIC_DOORBELL 0xc001011b |
81 | ||
410e4d57 JR |
82 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
83 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
84 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
85 | ||
24e09cbf JR |
86 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
87 | ||
fbc0db76 | 88 | #define TSC_RATIO_RSVD 0xffffff0000000000ULL |
92a1f12d JR |
89 | #define TSC_RATIO_MIN 0x0000000000000001ULL |
90 | #define TSC_RATIO_MAX 0x000000ffffffffffULL | |
fbc0db76 | 91 | |
5446a979 | 92 | #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF) |
44a95dae SS |
93 | |
94 | /* | |
95 | * 0xff is broadcast, so the max index allowed for physical APIC ID | |
96 | * table is 0xfe. APIC IDs above 0xff are reserved. | |
97 | */ | |
98 | #define AVIC_MAX_PHYSICAL_ID_COUNT 255 | |
99 | ||
18f40c53 SS |
100 | #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1 |
101 | #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0 | |
102 | #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF | |
103 | ||
5ea11f2b SS |
104 | /* AVIC GATAG is encoded using VM and VCPU IDs */ |
105 | #define AVIC_VCPU_ID_BITS 8 | |
106 | #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1) | |
107 | ||
108 | #define AVIC_VM_ID_BITS 24 | |
109 | #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS) | |
110 | #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1) | |
111 | ||
112 | #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \ | |
113 | (y & AVIC_VCPU_ID_MASK)) | |
114 | #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK) | |
115 | #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK) | |
116 | ||
67ec6607 JR |
117 | static bool erratum_383_found __read_mostly; |
118 | ||
6c8166a7 AK |
119 | static const u32 host_save_user_msrs[] = { |
120 | #ifdef CONFIG_X86_64 | |
121 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
122 | MSR_FS_BASE, | |
123 | #endif | |
124 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
46896c73 | 125 | MSR_TSC_AUX, |
6c8166a7 AK |
126 | }; |
127 | ||
128 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
129 | ||
81811c16 SC |
130 | struct kvm_sev_info { |
131 | bool active; /* SEV enabled guest */ | |
132 | unsigned int asid; /* ASID used for this guest */ | |
133 | unsigned int handle; /* SEV firmware handle */ | |
134 | int fd; /* SEV device fd */ | |
135 | unsigned long pages_locked; /* Number of pages locked */ | |
136 | struct list_head regions_list; /* List of registered regions */ | |
137 | }; | |
138 | ||
139 | struct kvm_svm { | |
140 | struct kvm kvm; | |
141 | ||
142 | /* Struct members for AVIC */ | |
143 | u32 avic_vm_id; | |
81811c16 SC |
144 | struct page *avic_logical_id_table_page; |
145 | struct page *avic_physical_id_table_page; | |
146 | struct hlist_node hnode; | |
147 | ||
148 | struct kvm_sev_info sev_info; | |
149 | }; | |
150 | ||
6c8166a7 AK |
151 | struct kvm_vcpu; |
152 | ||
e6aa9abd JR |
153 | struct nested_state { |
154 | struct vmcb *hsave; | |
155 | u64 hsave_msr; | |
4a810181 | 156 | u64 vm_cr_msr; |
e6aa9abd JR |
157 | u64 vmcb; |
158 | ||
159 | /* These are the merged vectors */ | |
160 | u32 *msrpm; | |
161 | ||
162 | /* gpa pointers to the real vectors */ | |
163 | u64 vmcb_msrpm; | |
ce2ac085 | 164 | u64 vmcb_iopm; |
aad42c64 | 165 | |
cd3ff653 JR |
166 | /* A VMEXIT is required but not yet emulated */ |
167 | bool exit_required; | |
168 | ||
aad42c64 | 169 | /* cache for intercepts of the guest */ |
4ee546b4 | 170 | u32 intercept_cr; |
3aed041a | 171 | u32 intercept_dr; |
aad42c64 JR |
172 | u32 intercept_exceptions; |
173 | u64 intercept; | |
174 | ||
5bd2edc3 JR |
175 | /* Nested Paging related state */ |
176 | u64 nested_cr3; | |
e6aa9abd JR |
177 | }; |
178 | ||
323c3d80 JR |
179 | #define MSRPM_OFFSETS 16 |
180 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
181 | ||
2b036c6b BO |
182 | /* |
183 | * Set osvw_len to higher value when updated Revision Guides | |
184 | * are published and we know what the new status bits are | |
185 | */ | |
186 | static uint64_t osvw_len = 4, osvw_status; | |
187 | ||
6c8166a7 AK |
188 | struct vcpu_svm { |
189 | struct kvm_vcpu vcpu; | |
190 | struct vmcb *vmcb; | |
191 | unsigned long vmcb_pa; | |
192 | struct svm_cpu_data *svm_data; | |
193 | uint64_t asid_generation; | |
194 | uint64_t sysenter_esp; | |
195 | uint64_t sysenter_eip; | |
46896c73 | 196 | uint64_t tsc_aux; |
6c8166a7 | 197 | |
d1d93fa9 TL |
198 | u64 msr_decfg; |
199 | ||
6c8166a7 AK |
200 | u64 next_rip; |
201 | ||
202 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
afe9e66f | 203 | struct { |
dacccfdd AK |
204 | u16 fs; |
205 | u16 gs; | |
206 | u16 ldt; | |
afe9e66f AK |
207 | u64 gs_base; |
208 | } host; | |
6c8166a7 | 209 | |
b2ac58f9 | 210 | u64 spec_ctrl; |
ccbcd267 TG |
211 | /* |
212 | * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be | |
213 | * translated into the appropriate L2_CFG bits on the host to | |
214 | * perform speculative control. | |
215 | */ | |
216 | u64 virt_spec_ctrl; | |
b2ac58f9 | 217 | |
6c8166a7 | 218 | u32 *msrpm; |
6c8166a7 | 219 | |
bd3d1ec3 AK |
220 | ulong nmi_iret_rip; |
221 | ||
e6aa9abd | 222 | struct nested_state nested; |
6be7d306 JK |
223 | |
224 | bool nmi_singlestep; | |
ab2f4d73 | 225 | u64 nmi_singlestep_guest_rflags; |
66b7138f JK |
226 | |
227 | unsigned int3_injected; | |
228 | unsigned long int3_rip; | |
fbc0db76 | 229 | |
6092d3d3 JR |
230 | /* cached guest cpuid flags for faster access */ |
231 | bool nrips_enabled : 1; | |
44a95dae | 232 | |
18f40c53 | 233 | u32 ldr_reg; |
98d90582 | 234 | u32 dfr_reg; |
44a95dae SS |
235 | struct page *avic_backing_page; |
236 | u64 *avic_physical_id_cache; | |
8221c137 | 237 | bool avic_is_running; |
411b44ba SS |
238 | |
239 | /* | |
240 | * Per-vcpu list of struct amd_svm_iommu_ir: | |
241 | * This is used mainly to store interrupt remapping information used | |
242 | * when update the vcpu affinity. This avoids the need to scan for | |
243 | * IRTE and try to match ga_tag in the IOMMU driver. | |
244 | */ | |
245 | struct list_head ir_list; | |
246 | spinlock_t ir_list_lock; | |
70cd94e6 BS |
247 | |
248 | /* which host CPU was used for running this vcpu */ | |
249 | unsigned int last_cpu; | |
411b44ba SS |
250 | }; |
251 | ||
252 | /* | |
253 | * This is a wrapper of struct amd_iommu_ir_data. | |
254 | */ | |
255 | struct amd_svm_iommu_ir { | |
256 | struct list_head node; /* Used by SVM for per-vcpu ir_list */ | |
257 | void *data; /* Storing pointer to struct amd_ir_data */ | |
6c8166a7 AK |
258 | }; |
259 | ||
44a95dae | 260 | #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF) |
e44e3eac | 261 | #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31 |
44a95dae SS |
262 | #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) |
263 | ||
264 | #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL) | |
265 | #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12) | |
266 | #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) | |
267 | #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63) | |
268 | ||
fbc0db76 JR |
269 | static DEFINE_PER_CPU(u64, current_tsc_ratio); |
270 | #define TSC_RATIO_DEFAULT 0x0100000000ULL | |
271 | ||
455716fa JR |
272 | #define MSR_INVALID 0xffffffffU |
273 | ||
09941fbb | 274 | static const struct svm_direct_access_msrs { |
ac72a9b7 JR |
275 | u32 index; /* Index of the MSR */ |
276 | bool always; /* True if intercept is always on */ | |
277 | } direct_access_msrs[] = { | |
8c06585d | 278 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
279 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
280 | #ifdef CONFIG_X86_64 | |
281 | { .index = MSR_GS_BASE, .always = true }, | |
282 | { .index = MSR_FS_BASE, .always = true }, | |
283 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
284 | { .index = MSR_LSTAR, .always = true }, | |
285 | { .index = MSR_CSTAR, .always = true }, | |
286 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
287 | #endif | |
b2ac58f9 | 288 | { .index = MSR_IA32_SPEC_CTRL, .always = false }, |
15d45071 | 289 | { .index = MSR_IA32_PRED_CMD, .always = false }, |
ac72a9b7 JR |
290 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, |
291 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
292 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
293 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
294 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
295 | }; |
296 | ||
709ddebf JR |
297 | /* enable NPT for AMD64 and X86 with PAE */ |
298 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
299 | static bool npt_enabled = true; | |
300 | #else | |
e0231715 | 301 | static bool npt_enabled; |
709ddebf | 302 | #endif |
6c7dac72 | 303 | |
8566ac8b BM |
304 | /* |
305 | * These 2 parameters are used to config the controls for Pause-Loop Exiting: | |
306 | * pause_filter_count: On processors that support Pause filtering(indicated | |
307 | * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter | |
308 | * count value. On VMRUN this value is loaded into an internal counter. | |
309 | * Each time a pause instruction is executed, this counter is decremented | |
310 | * until it reaches zero at which time a #VMEXIT is generated if pause | |
311 | * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause | |
312 | * Intercept Filtering for more details. | |
313 | * This also indicate if ple logic enabled. | |
314 | * | |
315 | * pause_filter_thresh: In addition, some processor families support advanced | |
316 | * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on | |
317 | * the amount of time a guest is allowed to execute in a pause loop. | |
318 | * In this mode, a 16-bit pause filter threshold field is added in the | |
319 | * VMCB. The threshold value is a cycle count that is used to reset the | |
320 | * pause counter. As with simple pause filtering, VMRUN loads the pause | |
321 | * count value from VMCB into an internal counter. Then, on each pause | |
322 | * instruction the hardware checks the elapsed number of cycles since | |
323 | * the most recent pause instruction against the pause filter threshold. | |
324 | * If the elapsed cycle count is greater than the pause filter threshold, | |
325 | * then the internal pause count is reloaded from the VMCB and execution | |
326 | * continues. If the elapsed cycle count is less than the pause filter | |
327 | * threshold, then the internal pause count is decremented. If the count | |
328 | * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is | |
329 | * triggered. If advanced pause filtering is supported and pause filter | |
330 | * threshold field is set to zero, the filter will operate in the simpler, | |
331 | * count only mode. | |
332 | */ | |
333 | ||
334 | static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP; | |
335 | module_param(pause_filter_thresh, ushort, 0444); | |
336 | ||
337 | static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW; | |
338 | module_param(pause_filter_count, ushort, 0444); | |
339 | ||
340 | /* Default doubles per-vcpu window every exit. */ | |
341 | static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW; | |
342 | module_param(pause_filter_count_grow, ushort, 0444); | |
343 | ||
344 | /* Default resets per-vcpu window every exit to pause_filter_count. */ | |
345 | static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK; | |
346 | module_param(pause_filter_count_shrink, ushort, 0444); | |
347 | ||
348 | /* Default is to compute the maximum so we can never overflow. */ | |
349 | static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX; | |
350 | module_param(pause_filter_count_max, ushort, 0444); | |
351 | ||
e2358851 DB |
352 | /* allow nested paging (virtualized MMU) for all guests */ |
353 | static int npt = true; | |
6c7dac72 | 354 | module_param(npt, int, S_IRUGO); |
e3da3acd | 355 | |
e2358851 DB |
356 | /* allow nested virtualization in KVM/SVM */ |
357 | static int nested = true; | |
236de055 AG |
358 | module_param(nested, int, S_IRUGO); |
359 | ||
44a95dae SS |
360 | /* enable / disable AVIC */ |
361 | static int avic; | |
5b8abf1f | 362 | #ifdef CONFIG_X86_LOCAL_APIC |
44a95dae | 363 | module_param(avic, int, S_IRUGO); |
5b8abf1f | 364 | #endif |
44a95dae | 365 | |
d647eb63 PB |
366 | /* enable/disable Next RIP Save */ |
367 | static int nrips = true; | |
368 | module_param(nrips, int, 0444); | |
369 | ||
89c8a498 JN |
370 | /* enable/disable Virtual VMLOAD VMSAVE */ |
371 | static int vls = true; | |
372 | module_param(vls, int, 0444); | |
373 | ||
640bd6e5 JN |
374 | /* enable/disable Virtual GIF */ |
375 | static int vgif = true; | |
376 | module_param(vgif, int, 0444); | |
5ea11f2b | 377 | |
e9df0942 BS |
378 | /* enable/disable SEV support */ |
379 | static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT); | |
380 | module_param(sev, int, 0444); | |
381 | ||
6f2f8453 PB |
382 | static bool __read_mostly dump_invalid_vmcb = 0; |
383 | module_param(dump_invalid_vmcb, bool, 0644); | |
384 | ||
7607b717 BS |
385 | static u8 rsm_ins_bytes[] = "\x0f\xaa"; |
386 | ||
79a8059d | 387 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
c2ba05cc | 388 | static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa); |
a5c3832d | 389 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 390 | |
410e4d57 | 391 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 392 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 393 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
394 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
395 | bool has_error_code, u32 error_code); | |
396 | ||
8d28fec4 | 397 | enum { |
116a0a23 JR |
398 | VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, |
399 | pause filter count */ | |
f56838e4 | 400 | VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ |
d48086d1 | 401 | VMCB_ASID, /* ASID */ |
decdbf6a | 402 | VMCB_INTR, /* int_ctl, int_vector */ |
b2747166 | 403 | VMCB_NPT, /* npt_en, nCR3, gPAT */ |
dcca1a65 | 404 | VMCB_CR, /* CR0, CR3, CR4, EFER */ |
72214b96 | 405 | VMCB_DR, /* DR6, DR7 */ |
17a703cb | 406 | VMCB_DT, /* GDT, IDT */ |
060d0c9a | 407 | VMCB_SEG, /* CS, DS, SS, ES, CPL */ |
0574dec0 | 408 | VMCB_CR2, /* CR2 only */ |
b53ba3f9 | 409 | VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ |
44a95dae SS |
410 | VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, |
411 | * AVIC PHYSICAL_TABLE pointer, | |
412 | * AVIC LOGICAL_TABLE pointer | |
413 | */ | |
8d28fec4 RJ |
414 | VMCB_DIRTY_MAX, |
415 | }; | |
416 | ||
0574dec0 JR |
417 | /* TPR and CR2 are always written before VMRUN */ |
418 | #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) | |
8d28fec4 | 419 | |
44a95dae SS |
420 | #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL |
421 | ||
33af3a7e TL |
422 | static int sev_flush_asids(void); |
423 | static DECLARE_RWSEM(sev_deactivate_lock); | |
e3b9a9e1 | 424 | static DEFINE_MUTEX(sev_bitmap_lock); |
ed3cd233 | 425 | static unsigned int max_sev_asid; |
1654efcb BS |
426 | static unsigned int min_sev_asid; |
427 | static unsigned long *sev_asid_bitmap; | |
33af3a7e | 428 | static unsigned long *sev_reclaim_asid_bitmap; |
89c50580 | 429 | #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT) |
1654efcb | 430 | |
1e80fdc0 BS |
431 | struct enc_region { |
432 | struct list_head list; | |
433 | unsigned long npages; | |
434 | struct page **pages; | |
435 | unsigned long uaddr; | |
436 | unsigned long size; | |
437 | }; | |
438 | ||
81811c16 SC |
439 | |
440 | static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm) | |
441 | { | |
442 | return container_of(kvm, struct kvm_svm, kvm); | |
443 | } | |
444 | ||
1654efcb BS |
445 | static inline bool svm_sev_enabled(void) |
446 | { | |
853c1109 | 447 | return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0; |
1654efcb BS |
448 | } |
449 | ||
450 | static inline bool sev_guest(struct kvm *kvm) | |
451 | { | |
853c1109 | 452 | #ifdef CONFIG_KVM_AMD_SEV |
81811c16 | 453 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
1654efcb BS |
454 | |
455 | return sev->active; | |
853c1109 PB |
456 | #else |
457 | return false; | |
458 | #endif | |
1654efcb | 459 | } |
ed3cd233 | 460 | |
70cd94e6 BS |
461 | static inline int sev_get_asid(struct kvm *kvm) |
462 | { | |
81811c16 | 463 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
70cd94e6 BS |
464 | |
465 | return sev->asid; | |
466 | } | |
467 | ||
8d28fec4 RJ |
468 | static inline void mark_all_dirty(struct vmcb *vmcb) |
469 | { | |
470 | vmcb->control.clean = 0; | |
471 | } | |
472 | ||
473 | static inline void mark_all_clean(struct vmcb *vmcb) | |
474 | { | |
475 | vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) | |
476 | & ~VMCB_ALWAYS_DIRTY_MASK; | |
477 | } | |
478 | ||
479 | static inline void mark_dirty(struct vmcb *vmcb, int bit) | |
480 | { | |
481 | vmcb->control.clean &= ~(1 << bit); | |
482 | } | |
483 | ||
a2fa3e9f GH |
484 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
485 | { | |
fb3f0f51 | 486 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
487 | } |
488 | ||
44a95dae SS |
489 | static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data) |
490 | { | |
491 | svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK; | |
492 | mark_dirty(svm->vmcb, VMCB_AVIC); | |
493 | } | |
494 | ||
340d3bc3 SS |
495 | static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu) |
496 | { | |
497 | struct vcpu_svm *svm = to_svm(vcpu); | |
498 | u64 *entry = svm->avic_physical_id_cache; | |
499 | ||
500 | if (!entry) | |
501 | return false; | |
502 | ||
503 | return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); | |
504 | } | |
505 | ||
384c6368 JR |
506 | static void recalc_intercepts(struct vcpu_svm *svm) |
507 | { | |
508 | struct vmcb_control_area *c, *h; | |
509 | struct nested_state *g; | |
510 | ||
116a0a23 JR |
511 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
512 | ||
384c6368 JR |
513 | if (!is_guest_mode(&svm->vcpu)) |
514 | return; | |
515 | ||
516 | c = &svm->vmcb->control; | |
517 | h = &svm->nested.hsave->control; | |
518 | g = &svm->nested; | |
519 | ||
4ee546b4 | 520 | c->intercept_cr = h->intercept_cr | g->intercept_cr; |
3aed041a | 521 | c->intercept_dr = h->intercept_dr | g->intercept_dr; |
bd89525a | 522 | c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions; |
384c6368 JR |
523 | c->intercept = h->intercept | g->intercept; |
524 | } | |
525 | ||
4ee546b4 RJ |
526 | static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) |
527 | { | |
528 | if (is_guest_mode(&svm->vcpu)) | |
529 | return svm->nested.hsave; | |
530 | else | |
531 | return svm->vmcb; | |
532 | } | |
533 | ||
534 | static inline void set_cr_intercept(struct vcpu_svm *svm, int bit) | |
535 | { | |
536 | struct vmcb *vmcb = get_host_vmcb(svm); | |
537 | ||
538 | vmcb->control.intercept_cr |= (1U << bit); | |
539 | ||
540 | recalc_intercepts(svm); | |
541 | } | |
542 | ||
543 | static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit) | |
544 | { | |
545 | struct vmcb *vmcb = get_host_vmcb(svm); | |
546 | ||
547 | vmcb->control.intercept_cr &= ~(1U << bit); | |
548 | ||
549 | recalc_intercepts(svm); | |
550 | } | |
551 | ||
552 | static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit) | |
553 | { | |
554 | struct vmcb *vmcb = get_host_vmcb(svm); | |
555 | ||
556 | return vmcb->control.intercept_cr & (1U << bit); | |
557 | } | |
558 | ||
5315c716 | 559 | static inline void set_dr_intercepts(struct vcpu_svm *svm) |
3aed041a JR |
560 | { |
561 | struct vmcb *vmcb = get_host_vmcb(svm); | |
562 | ||
5315c716 PB |
563 | vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ) |
564 | | (1 << INTERCEPT_DR1_READ) | |
565 | | (1 << INTERCEPT_DR2_READ) | |
566 | | (1 << INTERCEPT_DR3_READ) | |
567 | | (1 << INTERCEPT_DR4_READ) | |
568 | | (1 << INTERCEPT_DR5_READ) | |
569 | | (1 << INTERCEPT_DR6_READ) | |
570 | | (1 << INTERCEPT_DR7_READ) | |
571 | | (1 << INTERCEPT_DR0_WRITE) | |
572 | | (1 << INTERCEPT_DR1_WRITE) | |
573 | | (1 << INTERCEPT_DR2_WRITE) | |
574 | | (1 << INTERCEPT_DR3_WRITE) | |
575 | | (1 << INTERCEPT_DR4_WRITE) | |
576 | | (1 << INTERCEPT_DR5_WRITE) | |
577 | | (1 << INTERCEPT_DR6_WRITE) | |
578 | | (1 << INTERCEPT_DR7_WRITE); | |
3aed041a JR |
579 | |
580 | recalc_intercepts(svm); | |
581 | } | |
582 | ||
5315c716 | 583 | static inline void clr_dr_intercepts(struct vcpu_svm *svm) |
3aed041a JR |
584 | { |
585 | struct vmcb *vmcb = get_host_vmcb(svm); | |
586 | ||
5315c716 | 587 | vmcb->control.intercept_dr = 0; |
3aed041a JR |
588 | |
589 | recalc_intercepts(svm); | |
590 | } | |
591 | ||
18c918c5 JR |
592 | static inline void set_exception_intercept(struct vcpu_svm *svm, int bit) |
593 | { | |
594 | struct vmcb *vmcb = get_host_vmcb(svm); | |
595 | ||
596 | vmcb->control.intercept_exceptions |= (1U << bit); | |
597 | ||
598 | recalc_intercepts(svm); | |
599 | } | |
600 | ||
601 | static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit) | |
602 | { | |
603 | struct vmcb *vmcb = get_host_vmcb(svm); | |
604 | ||
605 | vmcb->control.intercept_exceptions &= ~(1U << bit); | |
606 | ||
607 | recalc_intercepts(svm); | |
608 | } | |
609 | ||
8a05a1b8 JR |
610 | static inline void set_intercept(struct vcpu_svm *svm, int bit) |
611 | { | |
612 | struct vmcb *vmcb = get_host_vmcb(svm); | |
613 | ||
614 | vmcb->control.intercept |= (1ULL << bit); | |
615 | ||
616 | recalc_intercepts(svm); | |
617 | } | |
618 | ||
619 | static inline void clr_intercept(struct vcpu_svm *svm, int bit) | |
620 | { | |
621 | struct vmcb *vmcb = get_host_vmcb(svm); | |
622 | ||
623 | vmcb->control.intercept &= ~(1ULL << bit); | |
624 | ||
625 | recalc_intercepts(svm); | |
626 | } | |
627 | ||
640bd6e5 JN |
628 | static inline bool vgif_enabled(struct vcpu_svm *svm) |
629 | { | |
630 | return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK); | |
631 | } | |
632 | ||
2af9194d JR |
633 | static inline void enable_gif(struct vcpu_svm *svm) |
634 | { | |
640bd6e5 JN |
635 | if (vgif_enabled(svm)) |
636 | svm->vmcb->control.int_ctl |= V_GIF_MASK; | |
637 | else | |
638 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
2af9194d JR |
639 | } |
640 | ||
641 | static inline void disable_gif(struct vcpu_svm *svm) | |
642 | { | |
640bd6e5 JN |
643 | if (vgif_enabled(svm)) |
644 | svm->vmcb->control.int_ctl &= ~V_GIF_MASK; | |
645 | else | |
646 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
2af9194d JR |
647 | } |
648 | ||
649 | static inline bool gif_set(struct vcpu_svm *svm) | |
650 | { | |
640bd6e5 JN |
651 | if (vgif_enabled(svm)) |
652 | return !!(svm->vmcb->control.int_ctl & V_GIF_MASK); | |
653 | else | |
654 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
2af9194d JR |
655 | } |
656 | ||
4866d5e3 | 657 | static unsigned long iopm_base; |
6aa8b732 AK |
658 | |
659 | struct kvm_ldttss_desc { | |
660 | u16 limit0; | |
661 | u16 base0; | |
e0231715 JR |
662 | unsigned base1:8, type:5, dpl:2, p:1; |
663 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
664 | u32 base3; |
665 | u32 zero1; | |
666 | } __attribute__((packed)); | |
667 | ||
668 | struct svm_cpu_data { | |
669 | int cpu; | |
670 | ||
5008fdf5 AK |
671 | u64 asid_generation; |
672 | u32 max_asid; | |
673 | u32 next_asid; | |
4faefff3 | 674 | u32 min_asid; |
6aa8b732 AK |
675 | struct kvm_ldttss_desc *tss_desc; |
676 | ||
677 | struct page *save_area; | |
15d45071 | 678 | struct vmcb *current_vmcb; |
70cd94e6 BS |
679 | |
680 | /* index = sev_asid, value = vmcb pointer */ | |
681 | struct vmcb **sev_vmcbs; | |
6aa8b732 AK |
682 | }; |
683 | ||
684 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
685 | ||
09941fbb | 686 | static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; |
6aa8b732 | 687 | |
9d8f549d | 688 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
689 | #define MSRS_RANGE_SIZE 2048 |
690 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
691 | ||
455716fa JR |
692 | static u32 svm_msrpm_offset(u32 msr) |
693 | { | |
694 | u32 offset; | |
695 | int i; | |
696 | ||
697 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
698 | if (msr < msrpm_ranges[i] || | |
699 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
700 | continue; | |
701 | ||
702 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
703 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
704 | ||
705 | /* Now we have the u8 offset - but need the u32 offset */ | |
706 | return offset / 4; | |
707 | } | |
708 | ||
709 | /* MSR not in any range */ | |
710 | return MSR_INVALID; | |
711 | } | |
712 | ||
6aa8b732 AK |
713 | #define MAX_INST_SIZE 15 |
714 | ||
6aa8b732 AK |
715 | static inline void clgi(void) |
716 | { | |
ac5ffda2 | 717 | asm volatile (__ex("clgi")); |
6aa8b732 AK |
718 | } |
719 | ||
720 | static inline void stgi(void) | |
721 | { | |
ac5ffda2 | 722 | asm volatile (__ex("stgi")); |
6aa8b732 AK |
723 | } |
724 | ||
725 | static inline void invlpga(unsigned long addr, u32 asid) | |
726 | { | |
ac5ffda2 | 727 | asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr)); |
6aa8b732 AK |
728 | } |
729 | ||
855feb67 | 730 | static int get_npt_level(struct kvm_vcpu *vcpu) |
4b16184c JR |
731 | { |
732 | #ifdef CONFIG_X86_64 | |
2a7266a8 | 733 | return PT64_ROOT_4LEVEL; |
4b16184c JR |
734 | #else |
735 | return PT32E_ROOT_LEVEL; | |
736 | #endif | |
737 | } | |
738 | ||
6aa8b732 AK |
739 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
740 | { | |
6dc696d4 | 741 | vcpu->arch.efer = efer; |
709ddebf | 742 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 743 | efer &= ~EFER_LME; |
6aa8b732 | 744 | |
9962d032 | 745 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
dcca1a65 | 746 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
747 | } |
748 | ||
6aa8b732 AK |
749 | static int is_external_interrupt(u32 info) |
750 | { | |
751 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
752 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
753 | } | |
754 | ||
37ccdcbe | 755 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
756 | { |
757 | struct vcpu_svm *svm = to_svm(vcpu); | |
758 | u32 ret = 0; | |
759 | ||
760 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
37ccdcbe PB |
761 | ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
762 | return ret; | |
2809f5d2 GC |
763 | } |
764 | ||
765 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
766 | { | |
767 | struct vcpu_svm *svm = to_svm(vcpu); | |
768 | ||
769 | if (mask == 0) | |
770 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
771 | else | |
772 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
773 | ||
774 | } | |
775 | ||
f8ea7c60 | 776 | static int skip_emulated_instruction(struct kvm_vcpu *vcpu) |
6aa8b732 | 777 | { |
a2fa3e9f GH |
778 | struct vcpu_svm *svm = to_svm(vcpu); |
779 | ||
d647eb63 | 780 | if (nrips && svm->vmcb->control.next_rip != 0) { |
d2922422 | 781 | WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS)); |
6bc31bdc | 782 | svm->next_rip = svm->vmcb->control.next_rip; |
f104765b | 783 | } |
6bc31bdc | 784 | |
1957aa63 SC |
785 | if (!svm->next_rip) { |
786 | if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP)) | |
787 | return 0; | |
788 | } else { | |
789 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) | |
790 | pr_err("%s: ip 0x%lx next 0x%llx\n", | |
791 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
792 | kvm_rip_write(vcpu, svm->next_rip); | |
793 | } | |
2809f5d2 | 794 | svm_set_interrupt_shadow(vcpu, 0); |
f8ea7c60 | 795 | |
60fc3d02 | 796 | return 1; |
6aa8b732 AK |
797 | } |
798 | ||
cfcd20e5 | 799 | static void svm_queue_exception(struct kvm_vcpu *vcpu) |
116a4752 JK |
800 | { |
801 | struct vcpu_svm *svm = to_svm(vcpu); | |
cfcd20e5 WL |
802 | unsigned nr = vcpu->arch.exception.nr; |
803 | bool has_error_code = vcpu->arch.exception.has_error_code; | |
664f8e26 | 804 | bool reinject = vcpu->arch.exception.injected; |
cfcd20e5 | 805 | u32 error_code = vcpu->arch.exception.error_code; |
116a4752 | 806 | |
e0231715 JR |
807 | /* |
808 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
809 | * handle the exception | |
810 | */ | |
ce7ddec4 JR |
811 | if (!reinject && |
812 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
813 | return; |
814 | ||
da998b46 JM |
815 | kvm_deliver_exception_payload(&svm->vcpu); |
816 | ||
d647eb63 | 817 | if (nr == BP_VECTOR && !nrips) { |
66b7138f JK |
818 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); |
819 | ||
820 | /* | |
821 | * For guest debugging where we have to reinject #BP if some | |
822 | * INT3 is guest-owned: | |
823 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
824 | * raises a fault that is not intercepted. Still better than | |
825 | * failing in all cases. | |
826 | */ | |
f8ea7c60 | 827 | (void)skip_emulated_instruction(&svm->vcpu); |
66b7138f JK |
828 | rip = kvm_rip_read(&svm->vcpu); |
829 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
830 | svm->int3_injected = rip - old_rip; | |
831 | } | |
832 | ||
116a4752 JK |
833 | svm->vmcb->control.event_inj = nr |
834 | | SVM_EVTINJ_VALID | |
835 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
836 | | SVM_EVTINJ_TYPE_EXEPT; | |
837 | svm->vmcb->control.event_inj_err = error_code; | |
838 | } | |
839 | ||
67ec6607 JR |
840 | static void svm_init_erratum_383(void) |
841 | { | |
842 | u32 low, high; | |
843 | int err; | |
844 | u64 val; | |
845 | ||
e6ee94d5 | 846 | if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH)) |
67ec6607 JR |
847 | return; |
848 | ||
849 | /* Use _safe variants to not break nested virtualization */ | |
850 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
851 | if (err) | |
852 | return; | |
853 | ||
854 | val |= (1ULL << 47); | |
855 | ||
856 | low = lower_32_bits(val); | |
857 | high = upper_32_bits(val); | |
858 | ||
859 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
860 | ||
861 | erratum_383_found = true; | |
862 | } | |
863 | ||
2b036c6b BO |
864 | static void svm_init_osvw(struct kvm_vcpu *vcpu) |
865 | { | |
866 | /* | |
867 | * Guests should see errata 400 and 415 as fixed (assuming that | |
868 | * HLT and IO instructions are intercepted). | |
869 | */ | |
870 | vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3; | |
871 | vcpu->arch.osvw.status = osvw_status & ~(6ULL); | |
872 | ||
873 | /* | |
874 | * By increasing VCPU's osvw.length to 3 we are telling the guest that | |
875 | * all osvw.status bits inside that length, including bit 0 (which is | |
876 | * reserved for erratum 298), are valid. However, if host processor's | |
877 | * osvw_len is 0 then osvw_status[0] carries no information. We need to | |
878 | * be conservative here and therefore we tell the guest that erratum 298 | |
879 | * is present (because we really don't know). | |
880 | */ | |
881 | if (osvw_len == 0 && boot_cpu_data.x86 == 0x10) | |
882 | vcpu->arch.osvw.status |= 1; | |
883 | } | |
884 | ||
6aa8b732 AK |
885 | static int has_svm(void) |
886 | { | |
63d1142f | 887 | const char *msg; |
6aa8b732 | 888 | |
63d1142f | 889 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 890 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
891 | return 0; |
892 | } | |
893 | ||
6aa8b732 AK |
894 | return 1; |
895 | } | |
896 | ||
13a34e06 | 897 | static void svm_hardware_disable(void) |
6aa8b732 | 898 | { |
fbc0db76 JR |
899 | /* Make sure we clean up behind us */ |
900 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) | |
901 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
902 | ||
2c8dceeb | 903 | cpu_svm_disable(); |
1018faa6 JR |
904 | |
905 | amd_pmu_disable_virt(); | |
6aa8b732 AK |
906 | } |
907 | ||
13a34e06 | 908 | static int svm_hardware_enable(void) |
6aa8b732 AK |
909 | { |
910 | ||
0fe1e009 | 911 | struct svm_cpu_data *sd; |
6aa8b732 | 912 | uint64_t efer; |
6aa8b732 AK |
913 | struct desc_struct *gdt; |
914 | int me = raw_smp_processor_id(); | |
915 | ||
10474ae8 AG |
916 | rdmsrl(MSR_EFER, efer); |
917 | if (efer & EFER_SVME) | |
918 | return -EBUSY; | |
919 | ||
6aa8b732 | 920 | if (!has_svm()) { |
1f5b77f5 | 921 | pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me); |
10474ae8 | 922 | return -EINVAL; |
6aa8b732 | 923 | } |
0fe1e009 | 924 | sd = per_cpu(svm_data, me); |
0fe1e009 | 925 | if (!sd) { |
1f5b77f5 | 926 | pr_err("%s: svm_data is NULL on %d\n", __func__, me); |
10474ae8 | 927 | return -EINVAL; |
6aa8b732 AK |
928 | } |
929 | ||
0fe1e009 TH |
930 | sd->asid_generation = 1; |
931 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
932 | sd->next_asid = sd->max_asid + 1; | |
ed3cd233 | 933 | sd->min_asid = max_sev_asid + 1; |
6aa8b732 | 934 | |
45fc8757 | 935 | gdt = get_current_gdt_rw(); |
0fe1e009 | 936 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 937 | |
9962d032 | 938 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 939 | |
d0316554 | 940 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 941 | |
fbc0db76 JR |
942 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
943 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
89cbc767 | 944 | __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT); |
fbc0db76 JR |
945 | } |
946 | ||
2b036c6b BO |
947 | |
948 | /* | |
949 | * Get OSVW bits. | |
950 | * | |
951 | * Note that it is possible to have a system with mixed processor | |
952 | * revisions and therefore different OSVW bits. If bits are not the same | |
953 | * on different processors then choose the worst case (i.e. if erratum | |
954 | * is present on one processor and not on another then assume that the | |
955 | * erratum is present everywhere). | |
956 | */ | |
957 | if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) { | |
958 | uint64_t len, status = 0; | |
959 | int err; | |
960 | ||
961 | len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err); | |
962 | if (!err) | |
963 | status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS, | |
964 | &err); | |
965 | ||
966 | if (err) | |
967 | osvw_status = osvw_len = 0; | |
968 | else { | |
969 | if (len < osvw_len) | |
970 | osvw_len = len; | |
971 | osvw_status |= status; | |
972 | osvw_status &= (1ULL << osvw_len) - 1; | |
973 | } | |
974 | } else | |
975 | osvw_status = osvw_len = 0; | |
976 | ||
67ec6607 JR |
977 | svm_init_erratum_383(); |
978 | ||
1018faa6 JR |
979 | amd_pmu_enable_virt(); |
980 | ||
10474ae8 | 981 | return 0; |
6aa8b732 AK |
982 | } |
983 | ||
0da1db75 JR |
984 | static void svm_cpu_uninit(int cpu) |
985 | { | |
0fe1e009 | 986 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 987 | |
0fe1e009 | 988 | if (!sd) |
0da1db75 JR |
989 | return; |
990 | ||
991 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
70cd94e6 | 992 | kfree(sd->sev_vmcbs); |
0fe1e009 TH |
993 | __free_page(sd->save_area); |
994 | kfree(sd); | |
0da1db75 JR |
995 | } |
996 | ||
6aa8b732 AK |
997 | static int svm_cpu_init(int cpu) |
998 | { | |
0fe1e009 | 999 | struct svm_cpu_data *sd; |
6aa8b732 AK |
1000 | int r; |
1001 | ||
0fe1e009 TH |
1002 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
1003 | if (!sd) | |
6aa8b732 | 1004 | return -ENOMEM; |
0fe1e009 | 1005 | sd->cpu = cpu; |
6aa8b732 | 1006 | r = -ENOMEM; |
70cd94e6 | 1007 | sd->save_area = alloc_page(GFP_KERNEL); |
0fe1e009 | 1008 | if (!sd->save_area) |
6aa8b732 AK |
1009 | goto err_1; |
1010 | ||
70cd94e6 BS |
1011 | if (svm_sev_enabled()) { |
1012 | r = -ENOMEM; | |
6da2ec56 KC |
1013 | sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1, |
1014 | sizeof(void *), | |
1015 | GFP_KERNEL); | |
70cd94e6 BS |
1016 | if (!sd->sev_vmcbs) |
1017 | goto err_1; | |
1018 | } | |
1019 | ||
0fe1e009 | 1020 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
1021 | |
1022 | return 0; | |
1023 | ||
1024 | err_1: | |
0fe1e009 | 1025 | kfree(sd); |
6aa8b732 AK |
1026 | return r; |
1027 | ||
1028 | } | |
1029 | ||
ac72a9b7 JR |
1030 | static bool valid_msr_intercept(u32 index) |
1031 | { | |
1032 | int i; | |
1033 | ||
1034 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
1035 | if (direct_access_msrs[i].index == index) | |
1036 | return true; | |
1037 | ||
1038 | return false; | |
1039 | } | |
1040 | ||
b2ac58f9 KA |
1041 | static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr) |
1042 | { | |
1043 | u8 bit_write; | |
1044 | unsigned long tmp; | |
1045 | u32 offset; | |
1046 | u32 *msrpm; | |
1047 | ||
1048 | msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm: | |
1049 | to_svm(vcpu)->msrpm; | |
1050 | ||
1051 | offset = svm_msrpm_offset(msr); | |
1052 | bit_write = 2 * (msr & 0x0f) + 1; | |
1053 | tmp = msrpm[offset]; | |
1054 | ||
1055 | BUG_ON(offset == MSR_INVALID); | |
1056 | ||
1057 | return !!test_bit(bit_write, &tmp); | |
1058 | } | |
1059 | ||
bfc733a7 RR |
1060 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
1061 | int read, int write) | |
6aa8b732 | 1062 | { |
455716fa JR |
1063 | u8 bit_read, bit_write; |
1064 | unsigned long tmp; | |
1065 | u32 offset; | |
6aa8b732 | 1066 | |
ac72a9b7 JR |
1067 | /* |
1068 | * If this warning triggers extend the direct_access_msrs list at the | |
1069 | * beginning of the file | |
1070 | */ | |
1071 | WARN_ON(!valid_msr_intercept(msr)); | |
1072 | ||
455716fa JR |
1073 | offset = svm_msrpm_offset(msr); |
1074 | bit_read = 2 * (msr & 0x0f); | |
1075 | bit_write = 2 * (msr & 0x0f) + 1; | |
1076 | tmp = msrpm[offset]; | |
1077 | ||
1078 | BUG_ON(offset == MSR_INVALID); | |
1079 | ||
1080 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
1081 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
1082 | ||
1083 | msrpm[offset] = tmp; | |
6aa8b732 AK |
1084 | } |
1085 | ||
f65c229c | 1086 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
1087 | { |
1088 | int i; | |
1089 | ||
f65c229c JR |
1090 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
1091 | ||
ac72a9b7 JR |
1092 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
1093 | if (!direct_access_msrs[i].always) | |
1094 | continue; | |
1095 | ||
1096 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
1097 | } | |
f65c229c JR |
1098 | } |
1099 | ||
323c3d80 JR |
1100 | static void add_msr_offset(u32 offset) |
1101 | { | |
1102 | int i; | |
1103 | ||
1104 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
1105 | ||
1106 | /* Offset already in list? */ | |
1107 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 1108 | return; |
323c3d80 JR |
1109 | |
1110 | /* Slot used by another offset? */ | |
1111 | if (msrpm_offsets[i] != MSR_INVALID) | |
1112 | continue; | |
1113 | ||
1114 | /* Add offset to list */ | |
1115 | msrpm_offsets[i] = offset; | |
1116 | ||
1117 | return; | |
6aa8b732 | 1118 | } |
323c3d80 JR |
1119 | |
1120 | /* | |
1121 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
1122 | * increase MSRPM_OFFSETS in this case. | |
1123 | */ | |
bfc733a7 | 1124 | BUG(); |
6aa8b732 AK |
1125 | } |
1126 | ||
323c3d80 | 1127 | static void init_msrpm_offsets(void) |
f65c229c | 1128 | { |
323c3d80 | 1129 | int i; |
f65c229c | 1130 | |
323c3d80 JR |
1131 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
1132 | ||
1133 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
1134 | u32 offset; | |
1135 | ||
1136 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
1137 | BUG_ON(offset == MSR_INVALID); | |
1138 | ||
1139 | add_msr_offset(offset); | |
1140 | } | |
f65c229c JR |
1141 | } |
1142 | ||
24e09cbf JR |
1143 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
1144 | { | |
1145 | u32 *msrpm = svm->msrpm; | |
1146 | ||
0dc92119 | 1147 | svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK; |
24e09cbf JR |
1148 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); |
1149 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
1150 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
1151 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
1152 | } | |
1153 | ||
1154 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
1155 | { | |
1156 | u32 *msrpm = svm->msrpm; | |
1157 | ||
0dc92119 | 1158 | svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK; |
24e09cbf JR |
1159 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); |
1160 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
1161 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
1162 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
1163 | } | |
1164 | ||
4aebd0e9 LP |
1165 | static void disable_nmi_singlestep(struct vcpu_svm *svm) |
1166 | { | |
1167 | svm->nmi_singlestep = false; | |
640bd6e5 | 1168 | |
ab2f4d73 LP |
1169 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) { |
1170 | /* Clear our flags if they were not set by the guest */ | |
1171 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF)) | |
1172 | svm->vmcb->save.rflags &= ~X86_EFLAGS_TF; | |
1173 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF)) | |
1174 | svm->vmcb->save.rflags &= ~X86_EFLAGS_RF; | |
1175 | } | |
4aebd0e9 LP |
1176 | } |
1177 | ||
5881f737 | 1178 | /* Note: |
81811c16 | 1179 | * This hash table is used to map VM_ID to a struct kvm_svm, |
5881f737 SS |
1180 | * when handling AMD IOMMU GALOG notification to schedule in |
1181 | * a particular vCPU. | |
1182 | */ | |
1183 | #define SVM_VM_DATA_HASH_BITS 8 | |
681bcea8 | 1184 | static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS); |
3f0d4db7 DV |
1185 | static u32 next_vm_id = 0; |
1186 | static bool next_vm_id_wrapped = 0; | |
681bcea8 | 1187 | static DEFINE_SPINLOCK(svm_vm_data_hash_lock); |
5881f737 SS |
1188 | |
1189 | /* Note: | |
1190 | * This function is called from IOMMU driver to notify | |
1191 | * SVM to schedule in a particular vCPU of a particular VM. | |
1192 | */ | |
1193 | static int avic_ga_log_notifier(u32 ga_tag) | |
1194 | { | |
1195 | unsigned long flags; | |
81811c16 | 1196 | struct kvm_svm *kvm_svm; |
5881f737 SS |
1197 | struct kvm_vcpu *vcpu = NULL; |
1198 | u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag); | |
1199 | u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag); | |
1200 | ||
1201 | pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id); | |
1202 | ||
1203 | spin_lock_irqsave(&svm_vm_data_hash_lock, flags); | |
81811c16 SC |
1204 | hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) { |
1205 | if (kvm_svm->avic_vm_id != vm_id) | |
5881f737 | 1206 | continue; |
81811c16 | 1207 | vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id); |
5881f737 SS |
1208 | break; |
1209 | } | |
1210 | spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); | |
1211 | ||
5881f737 SS |
1212 | /* Note: |
1213 | * At this point, the IOMMU should have already set the pending | |
1214 | * bit in the vAPIC backing page. So, we just need to schedule | |
1215 | * in the vcpu. | |
1216 | */ | |
1cf53587 | 1217 | if (vcpu) |
5881f737 SS |
1218 | kvm_vcpu_wake_up(vcpu); |
1219 | ||
1220 | return 0; | |
1221 | } | |
1222 | ||
e9df0942 BS |
1223 | static __init int sev_hardware_setup(void) |
1224 | { | |
1225 | struct sev_user_data_status *status; | |
1226 | int rc; | |
1227 | ||
1228 | /* Maximum number of encrypted guests supported simultaneously */ | |
1229 | max_sev_asid = cpuid_ecx(0x8000001F); | |
1230 | ||
1231 | if (!max_sev_asid) | |
1232 | return 1; | |
1233 | ||
1654efcb BS |
1234 | /* Minimum ASID value that should be used for SEV guest */ |
1235 | min_sev_asid = cpuid_edx(0x8000001F); | |
1236 | ||
33af3a7e | 1237 | /* Initialize SEV ASID bitmaps */ |
a101c9d6 | 1238 | sev_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL); |
1654efcb BS |
1239 | if (!sev_asid_bitmap) |
1240 | return 1; | |
1241 | ||
33af3a7e TL |
1242 | sev_reclaim_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL); |
1243 | if (!sev_reclaim_asid_bitmap) | |
1244 | return 1; | |
1245 | ||
e9df0942 BS |
1246 | status = kmalloc(sizeof(*status), GFP_KERNEL); |
1247 | if (!status) | |
1248 | return 1; | |
1249 | ||
1250 | /* | |
1251 | * Check SEV platform status. | |
1252 | * | |
1253 | * PLATFORM_STATUS can be called in any state, if we failed to query | |
1254 | * the PLATFORM status then either PSP firmware does not support SEV | |
1255 | * feature or SEV firmware is dead. | |
1256 | */ | |
1257 | rc = sev_platform_status(status, NULL); | |
1258 | if (rc) | |
1259 | goto err; | |
1260 | ||
1261 | pr_info("SEV supported\n"); | |
1262 | ||
1263 | err: | |
1264 | kfree(status); | |
1265 | return rc; | |
1266 | } | |
1267 | ||
8566ac8b BM |
1268 | static void grow_ple_window(struct kvm_vcpu *vcpu) |
1269 | { | |
1270 | struct vcpu_svm *svm = to_svm(vcpu); | |
1271 | struct vmcb_control_area *control = &svm->vmcb->control; | |
1272 | int old = control->pause_filter_count; | |
1273 | ||
1274 | control->pause_filter_count = __grow_ple_window(old, | |
1275 | pause_filter_count, | |
1276 | pause_filter_count_grow, | |
1277 | pause_filter_count_max); | |
1278 | ||
4f75bcc3 | 1279 | if (control->pause_filter_count != old) { |
8566ac8b | 1280 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
4f75bcc3 PX |
1281 | trace_kvm_ple_window_update(vcpu->vcpu_id, |
1282 | control->pause_filter_count, old); | |
1283 | } | |
8566ac8b BM |
1284 | } |
1285 | ||
1286 | static void shrink_ple_window(struct kvm_vcpu *vcpu) | |
1287 | { | |
1288 | struct vcpu_svm *svm = to_svm(vcpu); | |
1289 | struct vmcb_control_area *control = &svm->vmcb->control; | |
1290 | int old = control->pause_filter_count; | |
1291 | ||
1292 | control->pause_filter_count = | |
1293 | __shrink_ple_window(old, | |
1294 | pause_filter_count, | |
1295 | pause_filter_count_shrink, | |
1296 | pause_filter_count); | |
4f75bcc3 | 1297 | if (control->pause_filter_count != old) { |
8566ac8b | 1298 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
4f75bcc3 PX |
1299 | trace_kvm_ple_window_update(vcpu->vcpu_id, |
1300 | control->pause_filter_count, old); | |
1301 | } | |
8566ac8b BM |
1302 | } |
1303 | ||
6aa8b732 AK |
1304 | static __init int svm_hardware_setup(void) |
1305 | { | |
1306 | int cpu; | |
1307 | struct page *iopm_pages; | |
f65c229c | 1308 | void *iopm_va; |
6aa8b732 AK |
1309 | int r; |
1310 | ||
6aa8b732 AK |
1311 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
1312 | ||
1313 | if (!iopm_pages) | |
1314 | return -ENOMEM; | |
c8681339 AL |
1315 | |
1316 | iopm_va = page_address(iopm_pages); | |
1317 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
1318 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
1319 | ||
323c3d80 JR |
1320 | init_msrpm_offsets(); |
1321 | ||
50a37eb4 JR |
1322 | if (boot_cpu_has(X86_FEATURE_NX)) |
1323 | kvm_enable_efer_bits(EFER_NX); | |
1324 | ||
1b2fd70c AG |
1325 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
1326 | kvm_enable_efer_bits(EFER_FFXSR); | |
1327 | ||
92a1f12d | 1328 | if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
92a1f12d | 1329 | kvm_has_tsc_control = true; |
bc9b961b HZ |
1330 | kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX; |
1331 | kvm_tsc_scaling_ratio_frac_bits = 32; | |
92a1f12d JR |
1332 | } |
1333 | ||
8566ac8b BM |
1334 | /* Check for pause filtering support */ |
1335 | if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { | |
1336 | pause_filter_count = 0; | |
1337 | pause_filter_thresh = 0; | |
1338 | } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) { | |
1339 | pause_filter_thresh = 0; | |
1340 | } | |
1341 | ||
236de055 AG |
1342 | if (nested) { |
1343 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 1344 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
1345 | } |
1346 | ||
e9df0942 BS |
1347 | if (sev) { |
1348 | if (boot_cpu_has(X86_FEATURE_SEV) && | |
1349 | IS_ENABLED(CONFIG_KVM_AMD_SEV)) { | |
1350 | r = sev_hardware_setup(); | |
1351 | if (r) | |
1352 | sev = false; | |
1353 | } else { | |
1354 | sev = false; | |
1355 | } | |
1356 | } | |
1357 | ||
3230bb47 | 1358 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
1359 | r = svm_cpu_init(cpu); |
1360 | if (r) | |
f65c229c | 1361 | goto err; |
6aa8b732 | 1362 | } |
33bd6a0b | 1363 | |
2a6b20b8 | 1364 | if (!boot_cpu_has(X86_FEATURE_NPT)) |
e3da3acd JR |
1365 | npt_enabled = false; |
1366 | ||
6c7dac72 JR |
1367 | if (npt_enabled && !npt) { |
1368 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
1369 | npt_enabled = false; | |
1370 | } | |
1371 | ||
18552672 | 1372 | if (npt_enabled) { |
e3da3acd | 1373 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 1374 | kvm_enable_tdp(); |
5f4cb662 JR |
1375 | } else |
1376 | kvm_disable_tdp(); | |
e3da3acd | 1377 | |
d647eb63 PB |
1378 | if (nrips) { |
1379 | if (!boot_cpu_has(X86_FEATURE_NRIPS)) | |
1380 | nrips = false; | |
1381 | } | |
1382 | ||
5b8abf1f SS |
1383 | if (avic) { |
1384 | if (!npt_enabled || | |
1385 | !boot_cpu_has(X86_FEATURE_AVIC) || | |
5881f737 | 1386 | !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) { |
5b8abf1f | 1387 | avic = false; |
5881f737 | 1388 | } else { |
5b8abf1f | 1389 | pr_info("AVIC enabled\n"); |
5881f737 | 1390 | |
5881f737 SS |
1391 | amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier); |
1392 | } | |
5b8abf1f | 1393 | } |
44a95dae | 1394 | |
89c8a498 JN |
1395 | if (vls) { |
1396 | if (!npt_enabled || | |
5442c269 | 1397 | !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) || |
89c8a498 JN |
1398 | !IS_ENABLED(CONFIG_X86_64)) { |
1399 | vls = false; | |
1400 | } else { | |
1401 | pr_info("Virtual VMLOAD VMSAVE supported\n"); | |
1402 | } | |
1403 | } | |
1404 | ||
640bd6e5 JN |
1405 | if (vgif) { |
1406 | if (!boot_cpu_has(X86_FEATURE_VGIF)) | |
1407 | vgif = false; | |
1408 | else | |
1409 | pr_info("Virtual GIF supported\n"); | |
1410 | } | |
1411 | ||
6aa8b732 AK |
1412 | return 0; |
1413 | ||
f65c229c | 1414 | err: |
6aa8b732 AK |
1415 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
1416 | iopm_base = 0; | |
1417 | return r; | |
1418 | } | |
1419 | ||
1420 | static __exit void svm_hardware_unsetup(void) | |
1421 | { | |
0da1db75 JR |
1422 | int cpu; |
1423 | ||
33af3a7e | 1424 | if (svm_sev_enabled()) { |
a101c9d6 | 1425 | bitmap_free(sev_asid_bitmap); |
33af3a7e TL |
1426 | bitmap_free(sev_reclaim_asid_bitmap); |
1427 | ||
1428 | sev_flush_asids(); | |
1429 | } | |
1654efcb | 1430 | |
3230bb47 | 1431 | for_each_possible_cpu(cpu) |
0da1db75 JR |
1432 | svm_cpu_uninit(cpu); |
1433 | ||
6aa8b732 | 1434 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 1435 | iopm_base = 0; |
6aa8b732 AK |
1436 | } |
1437 | ||
1438 | static void init_seg(struct vmcb_seg *seg) | |
1439 | { | |
1440 | seg->selector = 0; | |
1441 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 1442 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
1443 | seg->limit = 0xffff; |
1444 | seg->base = 0; | |
1445 | } | |
1446 | ||
1447 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
1448 | { | |
1449 | seg->selector = 0; | |
1450 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
1451 | seg->limit = 0xffff; | |
1452 | seg->base = 0; | |
1453 | } | |
1454 | ||
e79f245d KA |
1455 | static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu) |
1456 | { | |
1457 | struct vcpu_svm *svm = to_svm(vcpu); | |
1458 | ||
1459 | if (is_guest_mode(vcpu)) | |
1460 | return svm->nested.hsave->control.tsc_offset; | |
1461 | ||
1462 | return vcpu->arch.tsc_offset; | |
1463 | } | |
1464 | ||
326e7425 | 1465 | static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
f4e1b3c8 ZA |
1466 | { |
1467 | struct vcpu_svm *svm = to_svm(vcpu); | |
1468 | u64 g_tsc_offset = 0; | |
1469 | ||
2030753d | 1470 | if (is_guest_mode(vcpu)) { |
e79f245d | 1471 | /* Write L1's TSC offset. */ |
f4e1b3c8 ZA |
1472 | g_tsc_offset = svm->vmcb->control.tsc_offset - |
1473 | svm->nested.hsave->control.tsc_offset; | |
1474 | svm->nested.hsave->control.tsc_offset = offset; | |
45c3af97 PB |
1475 | } |
1476 | ||
1477 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, | |
1478 | svm->vmcb->control.tsc_offset - g_tsc_offset, | |
1479 | offset); | |
f4e1b3c8 ZA |
1480 | |
1481 | svm->vmcb->control.tsc_offset = offset + g_tsc_offset; | |
116a0a23 JR |
1482 | |
1483 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); | |
326e7425 | 1484 | return svm->vmcb->control.tsc_offset; |
f4e1b3c8 ZA |
1485 | } |
1486 | ||
44a95dae SS |
1487 | static void avic_init_vmcb(struct vcpu_svm *svm) |
1488 | { | |
1489 | struct vmcb *vmcb = svm->vmcb; | |
81811c16 | 1490 | struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm); |
d0ec49d4 | 1491 | phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page)); |
81811c16 SC |
1492 | phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page)); |
1493 | phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page)); | |
44a95dae SS |
1494 | |
1495 | vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK; | |
1496 | vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK; | |
1497 | vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK; | |
1498 | vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT; | |
1499 | vmcb->control.int_ctl |= AVIC_ENABLE_MASK; | |
44a95dae SS |
1500 | } |
1501 | ||
5690891b | 1502 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 1503 | { |
e6101a96 JR |
1504 | struct vmcb_control_area *control = &svm->vmcb->control; |
1505 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 1506 | |
4ee546b4 | 1507 | svm->vcpu.arch.hflags = 0; |
bff78274 | 1508 | |
4ee546b4 RJ |
1509 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1510 | set_cr_intercept(svm, INTERCEPT_CR3_READ); | |
1511 | set_cr_intercept(svm, INTERCEPT_CR4_READ); | |
1512 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
1513 | set_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
1514 | set_cr_intercept(svm, INTERCEPT_CR4_WRITE); | |
3bbf3565 SS |
1515 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) |
1516 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
6aa8b732 | 1517 | |
5315c716 | 1518 | set_dr_intercepts(svm); |
6aa8b732 | 1519 | |
18c918c5 JR |
1520 | set_exception_intercept(svm, PF_VECTOR); |
1521 | set_exception_intercept(svm, UD_VECTOR); | |
1522 | set_exception_intercept(svm, MC_VECTOR); | |
54a20552 | 1523 | set_exception_intercept(svm, AC_VECTOR); |
cbdb967a | 1524 | set_exception_intercept(svm, DB_VECTOR); |
9718420e LA |
1525 | /* |
1526 | * Guest access to VMware backdoor ports could legitimately | |
1527 | * trigger #GP because of TSS I/O permission bitmap. | |
1528 | * We intercept those #GP and allow access to them anyway | |
1529 | * as VMware does. | |
1530 | */ | |
1531 | if (enable_vmware_backdoor) | |
1532 | set_exception_intercept(svm, GP_VECTOR); | |
6aa8b732 | 1533 | |
8a05a1b8 JR |
1534 | set_intercept(svm, INTERCEPT_INTR); |
1535 | set_intercept(svm, INTERCEPT_NMI); | |
1536 | set_intercept(svm, INTERCEPT_SMI); | |
1537 | set_intercept(svm, INTERCEPT_SELECTIVE_CR0); | |
332b56e4 | 1538 | set_intercept(svm, INTERCEPT_RDPMC); |
8a05a1b8 JR |
1539 | set_intercept(svm, INTERCEPT_CPUID); |
1540 | set_intercept(svm, INTERCEPT_INVD); | |
8a05a1b8 JR |
1541 | set_intercept(svm, INTERCEPT_INVLPG); |
1542 | set_intercept(svm, INTERCEPT_INVLPGA); | |
1543 | set_intercept(svm, INTERCEPT_IOIO_PROT); | |
1544 | set_intercept(svm, INTERCEPT_MSR_PROT); | |
1545 | set_intercept(svm, INTERCEPT_TASK_SWITCH); | |
1546 | set_intercept(svm, INTERCEPT_SHUTDOWN); | |
1547 | set_intercept(svm, INTERCEPT_VMRUN); | |
1548 | set_intercept(svm, INTERCEPT_VMMCALL); | |
1549 | set_intercept(svm, INTERCEPT_VMLOAD); | |
1550 | set_intercept(svm, INTERCEPT_VMSAVE); | |
1551 | set_intercept(svm, INTERCEPT_STGI); | |
1552 | set_intercept(svm, INTERCEPT_CLGI); | |
1553 | set_intercept(svm, INTERCEPT_SKINIT); | |
1554 | set_intercept(svm, INTERCEPT_WBINVD); | |
81dd35d4 | 1555 | set_intercept(svm, INTERCEPT_XSETBV); |
0cb8410b | 1556 | set_intercept(svm, INTERCEPT_RDPRU); |
7607b717 | 1557 | set_intercept(svm, INTERCEPT_RSM); |
6aa8b732 | 1558 | |
4d5422ce | 1559 | if (!kvm_mwait_in_guest(svm->vcpu.kvm)) { |
668fffa3 MT |
1560 | set_intercept(svm, INTERCEPT_MONITOR); |
1561 | set_intercept(svm, INTERCEPT_MWAIT); | |
1562 | } | |
1563 | ||
caa057a2 WL |
1564 | if (!kvm_hlt_in_guest(svm->vcpu.kvm)) |
1565 | set_intercept(svm, INTERCEPT_HLT); | |
1566 | ||
d0ec49d4 TL |
1567 | control->iopm_base_pa = __sme_set(iopm_base); |
1568 | control->msrpm_base_pa = __sme_set(__pa(svm->msrpm)); | |
6aa8b732 AK |
1569 | control->int_ctl = V_INTR_MASKING_MASK; |
1570 | ||
1571 | init_seg(&save->es); | |
1572 | init_seg(&save->ss); | |
1573 | init_seg(&save->ds); | |
1574 | init_seg(&save->fs); | |
1575 | init_seg(&save->gs); | |
1576 | ||
1577 | save->cs.selector = 0xf000; | |
04b66839 | 1578 | save->cs.base = 0xffff0000; |
6aa8b732 AK |
1579 | /* Executable/Readable Code Segment */ |
1580 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
1581 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
1582 | save->cs.limit = 0xffff; | |
6aa8b732 AK |
1583 | |
1584 | save->gdtr.limit = 0xffff; | |
1585 | save->idtr.limit = 0xffff; | |
1586 | ||
1587 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
1588 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
1589 | ||
5690891b | 1590 | svm_set_efer(&svm->vcpu, 0); |
d77c26fc | 1591 | save->dr6 = 0xffff0ff0; |
f6e78475 | 1592 | kvm_set_rflags(&svm->vcpu, 2); |
6aa8b732 | 1593 | save->rip = 0x0000fff0; |
5fdbf976 | 1594 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 1595 | |
e0231715 | 1596 | /* |
18fa000a | 1597 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
d28bc9dd | 1598 | * It also updates the guest-visible cr0 value. |
6aa8b732 | 1599 | */ |
79a8059d | 1600 | svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); |
ebae871a | 1601 | kvm_mmu_reset_context(&svm->vcpu); |
18fa000a | 1602 | |
66aee91a | 1603 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 1604 | /* rdx = ?? */ |
709ddebf JR |
1605 | |
1606 | if (npt_enabled) { | |
1607 | /* Setup VMCB for Nested Paging */ | |
cea3a19b | 1608 | control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE; |
8a05a1b8 | 1609 | clr_intercept(svm, INTERCEPT_INVLPG); |
18c918c5 | 1610 | clr_exception_intercept(svm, PF_VECTOR); |
4ee546b4 RJ |
1611 | clr_cr_intercept(svm, INTERCEPT_CR3_READ); |
1612 | clr_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
74545705 | 1613 | save->g_pat = svm->vcpu.arch.pat; |
709ddebf JR |
1614 | save->cr3 = 0; |
1615 | save->cr4 = 0; | |
1616 | } | |
f40f6a45 | 1617 | svm->asid_generation = 0; |
1371d904 | 1618 | |
e6aa9abd | 1619 | svm->nested.vmcb = 0; |
2af9194d JR |
1620 | svm->vcpu.arch.hflags = 0; |
1621 | ||
8566ac8b BM |
1622 | if (pause_filter_count) { |
1623 | control->pause_filter_count = pause_filter_count; | |
1624 | if (pause_filter_thresh) | |
1625 | control->pause_filter_thresh = pause_filter_thresh; | |
8a05a1b8 | 1626 | set_intercept(svm, INTERCEPT_PAUSE); |
8566ac8b BM |
1627 | } else { |
1628 | clr_intercept(svm, INTERCEPT_PAUSE); | |
565d0998 ML |
1629 | } |
1630 | ||
67034bb9 | 1631 | if (kvm_vcpu_apicv_active(&svm->vcpu)) |
44a95dae SS |
1632 | avic_init_vmcb(svm); |
1633 | ||
89c8a498 JN |
1634 | /* |
1635 | * If hardware supports Virtual VMLOAD VMSAVE then enable it | |
1636 | * in VMCB and clear intercepts to avoid #VMEXIT. | |
1637 | */ | |
1638 | if (vls) { | |
1639 | clr_intercept(svm, INTERCEPT_VMLOAD); | |
1640 | clr_intercept(svm, INTERCEPT_VMSAVE); | |
1641 | svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK; | |
1642 | } | |
1643 | ||
640bd6e5 JN |
1644 | if (vgif) { |
1645 | clr_intercept(svm, INTERCEPT_STGI); | |
1646 | clr_intercept(svm, INTERCEPT_CLGI); | |
1647 | svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK; | |
1648 | } | |
1649 | ||
35c6f649 | 1650 | if (sev_guest(svm->vcpu.kvm)) { |
1654efcb | 1651 | svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE; |
35c6f649 BS |
1652 | clr_exception_intercept(svm, UD_VECTOR); |
1653 | } | |
1654efcb | 1654 | |
8d28fec4 RJ |
1655 | mark_all_dirty(svm->vmcb); |
1656 | ||
2af9194d | 1657 | enable_gif(svm); |
44a95dae SS |
1658 | |
1659 | } | |
1660 | ||
d3e7dec0 DC |
1661 | static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, |
1662 | unsigned int index) | |
44a95dae SS |
1663 | { |
1664 | u64 *avic_physical_id_table; | |
81811c16 | 1665 | struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm); |
44a95dae SS |
1666 | |
1667 | if (index >= AVIC_MAX_PHYSICAL_ID_COUNT) | |
1668 | return NULL; | |
1669 | ||
81811c16 | 1670 | avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page); |
44a95dae SS |
1671 | |
1672 | return &avic_physical_id_table[index]; | |
1673 | } | |
1674 | ||
1675 | /** | |
1676 | * Note: | |
1677 | * AVIC hardware walks the nested page table to check permissions, | |
1678 | * but does not use the SPA address specified in the leaf page | |
1679 | * table entry since it uses address in the AVIC_BACKING_PAGE pointer | |
1680 | * field of the VMCB. Therefore, we set up the | |
1681 | * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here. | |
1682 | */ | |
1683 | static int avic_init_access_page(struct kvm_vcpu *vcpu) | |
1684 | { | |
1685 | struct kvm *kvm = vcpu->kvm; | |
30510387 | 1686 | int ret = 0; |
44a95dae | 1687 | |
30510387 | 1688 | mutex_lock(&kvm->slots_lock); |
44a95dae | 1689 | if (kvm->arch.apic_access_page_done) |
30510387 | 1690 | goto out; |
44a95dae | 1691 | |
30510387 WW |
1692 | ret = __x86_set_memory_region(kvm, |
1693 | APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
1694 | APIC_DEFAULT_PHYS_BASE, | |
1695 | PAGE_SIZE); | |
44a95dae | 1696 | if (ret) |
30510387 | 1697 | goto out; |
44a95dae SS |
1698 | |
1699 | kvm->arch.apic_access_page_done = true; | |
30510387 WW |
1700 | out: |
1701 | mutex_unlock(&kvm->slots_lock); | |
1702 | return ret; | |
44a95dae SS |
1703 | } |
1704 | ||
1705 | static int avic_init_backing_page(struct kvm_vcpu *vcpu) | |
1706 | { | |
1707 | int ret; | |
1708 | u64 *entry, new_entry; | |
1709 | int id = vcpu->vcpu_id; | |
1710 | struct vcpu_svm *svm = to_svm(vcpu); | |
1711 | ||
1712 | ret = avic_init_access_page(vcpu); | |
1713 | if (ret) | |
1714 | return ret; | |
1715 | ||
1716 | if (id >= AVIC_MAX_PHYSICAL_ID_COUNT) | |
1717 | return -EINVAL; | |
1718 | ||
1719 | if (!svm->vcpu.arch.apic->regs) | |
1720 | return -EINVAL; | |
1721 | ||
1722 | svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs); | |
1723 | ||
1724 | /* Setting AVIC backing page address in the phy APIC ID table */ | |
1725 | entry = avic_get_physical_id_entry(vcpu, id); | |
1726 | if (!entry) | |
1727 | return -EINVAL; | |
1728 | ||
d0ec49d4 TL |
1729 | new_entry = __sme_set((page_to_phys(svm->avic_backing_page) & |
1730 | AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) | | |
1731 | AVIC_PHYSICAL_ID_ENTRY_VALID_MASK); | |
44a95dae SS |
1732 | WRITE_ONCE(*entry, new_entry); |
1733 | ||
1734 | svm->avic_physical_id_cache = entry; | |
1735 | ||
1736 | return 0; | |
1737 | } | |
1738 | ||
e3b9a9e1 | 1739 | static void sev_asid_free(int asid) |
1654efcb | 1740 | { |
70cd94e6 BS |
1741 | struct svm_cpu_data *sd; |
1742 | int cpu, pos; | |
1654efcb | 1743 | |
e3b9a9e1 TL |
1744 | mutex_lock(&sev_bitmap_lock); |
1745 | ||
1654efcb | 1746 | pos = asid - 1; |
33af3a7e | 1747 | __set_bit(pos, sev_reclaim_asid_bitmap); |
70cd94e6 BS |
1748 | |
1749 | for_each_possible_cpu(cpu) { | |
1750 | sd = per_cpu(svm_data, cpu); | |
1751 | sd->sev_vmcbs[pos] = NULL; | |
1752 | } | |
1654efcb | 1753 | |
e3b9a9e1 | 1754 | mutex_unlock(&sev_bitmap_lock); |
1654efcb BS |
1755 | } |
1756 | ||
59414c98 BS |
1757 | static void sev_unbind_asid(struct kvm *kvm, unsigned int handle) |
1758 | { | |
1759 | struct sev_data_decommission *decommission; | |
1760 | struct sev_data_deactivate *data; | |
1761 | ||
1762 | if (!handle) | |
1763 | return; | |
1764 | ||
1765 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
1766 | if (!data) | |
1767 | return; | |
1768 | ||
1769 | /* deactivate handle */ | |
1770 | data->handle = handle; | |
83af5e65 | 1771 | |
33af3a7e TL |
1772 | /* Guard DEACTIVATE against WBINVD/DF_FLUSH used in ASID recycling */ |
1773 | down_read(&sev_deactivate_lock); | |
59414c98 | 1774 | sev_guest_deactivate(data, NULL); |
33af3a7e | 1775 | up_read(&sev_deactivate_lock); |
83af5e65 | 1776 | |
59414c98 BS |
1777 | kfree(data); |
1778 | ||
1779 | decommission = kzalloc(sizeof(*decommission), GFP_KERNEL); | |
1780 | if (!decommission) | |
1781 | return; | |
1782 | ||
1783 | /* decommission handle */ | |
1784 | decommission->handle = handle; | |
1785 | sev_guest_decommission(decommission, NULL); | |
1786 | ||
1787 | kfree(decommission); | |
1788 | } | |
1789 | ||
89c50580 BS |
1790 | static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr, |
1791 | unsigned long ulen, unsigned long *n, | |
1792 | int write) | |
1793 | { | |
81811c16 | 1794 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
89c50580 BS |
1795 | unsigned long npages, npinned, size; |
1796 | unsigned long locked, lock_limit; | |
1797 | struct page **pages; | |
86bf20cb DC |
1798 | unsigned long first, last; |
1799 | ||
1800 | if (ulen == 0 || uaddr + ulen < uaddr) | |
1801 | return NULL; | |
89c50580 BS |
1802 | |
1803 | /* Calculate number of pages. */ | |
1804 | first = (uaddr & PAGE_MASK) >> PAGE_SHIFT; | |
1805 | last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT; | |
1806 | npages = (last - first + 1); | |
1807 | ||
1808 | locked = sev->pages_locked + npages; | |
1809 | lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT; | |
1810 | if (locked > lock_limit && !capable(CAP_IPC_LOCK)) { | |
1811 | pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit); | |
1812 | return NULL; | |
1813 | } | |
1814 | ||
1815 | /* Avoid using vmalloc for smaller buffers. */ | |
1816 | size = npages * sizeof(struct page *); | |
1817 | if (size > PAGE_SIZE) | |
1ec69647 BG |
1818 | pages = __vmalloc(size, GFP_KERNEL_ACCOUNT | __GFP_ZERO, |
1819 | PAGE_KERNEL); | |
89c50580 | 1820 | else |
1ec69647 | 1821 | pages = kmalloc(size, GFP_KERNEL_ACCOUNT); |
89c50580 BS |
1822 | |
1823 | if (!pages) | |
1824 | return NULL; | |
1825 | ||
1826 | /* Pin the user virtual address. */ | |
73b0140b | 1827 | npinned = get_user_pages_fast(uaddr, npages, FOLL_WRITE, pages); |
89c50580 BS |
1828 | if (npinned != npages) { |
1829 | pr_err("SEV: Failure locking %lu pages.\n", npages); | |
1830 | goto err; | |
1831 | } | |
1832 | ||
1833 | *n = npages; | |
1834 | sev->pages_locked = locked; | |
1835 | ||
1836 | return pages; | |
1837 | ||
1838 | err: | |
1839 | if (npinned > 0) | |
1840 | release_pages(pages, npinned); | |
1841 | ||
1842 | kvfree(pages); | |
1843 | return NULL; | |
1844 | } | |
1845 | ||
1846 | static void sev_unpin_memory(struct kvm *kvm, struct page **pages, | |
1847 | unsigned long npages) | |
1848 | { | |
81811c16 | 1849 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
89c50580 BS |
1850 | |
1851 | release_pages(pages, npages); | |
1852 | kvfree(pages); | |
1853 | sev->pages_locked -= npages; | |
1854 | } | |
1855 | ||
1856 | static void sev_clflush_pages(struct page *pages[], unsigned long npages) | |
1857 | { | |
1858 | uint8_t *page_virtual; | |
1859 | unsigned long i; | |
1860 | ||
1861 | if (npages == 0 || pages == NULL) | |
1862 | return; | |
1863 | ||
1864 | for (i = 0; i < npages; i++) { | |
1865 | page_virtual = kmap_atomic(pages[i]); | |
1866 | clflush_cache_range(page_virtual, PAGE_SIZE); | |
1867 | kunmap_atomic(page_virtual); | |
1868 | } | |
1869 | } | |
1870 | ||
1e80fdc0 BS |
1871 | static void __unregister_enc_region_locked(struct kvm *kvm, |
1872 | struct enc_region *region) | |
1873 | { | |
1874 | /* | |
1875 | * The guest may change the memory encryption attribute from C=0 -> C=1 | |
1876 | * or vice versa for this memory range. Lets make sure caches are | |
1877 | * flushed to ensure that guest data gets written into memory with | |
1878 | * correct C-bit. | |
1879 | */ | |
1880 | sev_clflush_pages(region->pages, region->npages); | |
1881 | ||
1882 | sev_unpin_memory(kvm, region->pages, region->npages); | |
1883 | list_del(®ion->list); | |
1884 | kfree(region); | |
1885 | } | |
1886 | ||
434a1e94 SC |
1887 | static struct kvm *svm_vm_alloc(void) |
1888 | { | |
1ec69647 BG |
1889 | struct kvm_svm *kvm_svm = __vmalloc(sizeof(struct kvm_svm), |
1890 | GFP_KERNEL_ACCOUNT | __GFP_ZERO, | |
1891 | PAGE_KERNEL); | |
81811c16 | 1892 | return &kvm_svm->kvm; |
434a1e94 SC |
1893 | } |
1894 | ||
1895 | static void svm_vm_free(struct kvm *kvm) | |
1896 | { | |
d1e5b0e9 | 1897 | vfree(to_kvm_svm(kvm)); |
434a1e94 SC |
1898 | } |
1899 | ||
1654efcb BS |
1900 | static void sev_vm_destroy(struct kvm *kvm) |
1901 | { | |
81811c16 | 1902 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
1e80fdc0 BS |
1903 | struct list_head *head = &sev->regions_list; |
1904 | struct list_head *pos, *q; | |
59414c98 | 1905 | |
1654efcb BS |
1906 | if (!sev_guest(kvm)) |
1907 | return; | |
1908 | ||
1e80fdc0 BS |
1909 | mutex_lock(&kvm->lock); |
1910 | ||
1911 | /* | |
1912 | * if userspace was terminated before unregistering the memory regions | |
1913 | * then lets unpin all the registered memory. | |
1914 | */ | |
1915 | if (!list_empty(head)) { | |
1916 | list_for_each_safe(pos, q, head) { | |
1917 | __unregister_enc_region_locked(kvm, | |
1918 | list_entry(pos, struct enc_region, list)); | |
1919 | } | |
1920 | } | |
1921 | ||
1922 | mutex_unlock(&kvm->lock); | |
1923 | ||
59414c98 | 1924 | sev_unbind_asid(kvm, sev->handle); |
e3b9a9e1 | 1925 | sev_asid_free(sev->asid); |
1654efcb BS |
1926 | } |
1927 | ||
44a95dae SS |
1928 | static void avic_vm_destroy(struct kvm *kvm) |
1929 | { | |
5881f737 | 1930 | unsigned long flags; |
81811c16 | 1931 | struct kvm_svm *kvm_svm = to_kvm_svm(kvm); |
44a95dae | 1932 | |
3863dff0 DV |
1933 | if (!avic) |
1934 | return; | |
1935 | ||
81811c16 SC |
1936 | if (kvm_svm->avic_logical_id_table_page) |
1937 | __free_page(kvm_svm->avic_logical_id_table_page); | |
1938 | if (kvm_svm->avic_physical_id_table_page) | |
1939 | __free_page(kvm_svm->avic_physical_id_table_page); | |
5881f737 SS |
1940 | |
1941 | spin_lock_irqsave(&svm_vm_data_hash_lock, flags); | |
81811c16 | 1942 | hash_del(&kvm_svm->hnode); |
5881f737 | 1943 | spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); |
44a95dae SS |
1944 | } |
1945 | ||
1654efcb BS |
1946 | static void svm_vm_destroy(struct kvm *kvm) |
1947 | { | |
1948 | avic_vm_destroy(kvm); | |
1949 | sev_vm_destroy(kvm); | |
1950 | } | |
1951 | ||
44a95dae SS |
1952 | static int avic_vm_init(struct kvm *kvm) |
1953 | { | |
5881f737 | 1954 | unsigned long flags; |
3f0d4db7 | 1955 | int err = -ENOMEM; |
81811c16 SC |
1956 | struct kvm_svm *kvm_svm = to_kvm_svm(kvm); |
1957 | struct kvm_svm *k2; | |
44a95dae SS |
1958 | struct page *p_page; |
1959 | struct page *l_page; | |
3f0d4db7 | 1960 | u32 vm_id; |
44a95dae SS |
1961 | |
1962 | if (!avic) | |
1963 | return 0; | |
1964 | ||
1965 | /* Allocating physical APIC ID table (4KB) */ | |
1ec69647 | 1966 | p_page = alloc_page(GFP_KERNEL_ACCOUNT); |
44a95dae SS |
1967 | if (!p_page) |
1968 | goto free_avic; | |
1969 | ||
81811c16 | 1970 | kvm_svm->avic_physical_id_table_page = p_page; |
44a95dae SS |
1971 | clear_page(page_address(p_page)); |
1972 | ||
1973 | /* Allocating logical APIC ID table (4KB) */ | |
1ec69647 | 1974 | l_page = alloc_page(GFP_KERNEL_ACCOUNT); |
44a95dae SS |
1975 | if (!l_page) |
1976 | goto free_avic; | |
1977 | ||
81811c16 | 1978 | kvm_svm->avic_logical_id_table_page = l_page; |
44a95dae SS |
1979 | clear_page(page_address(l_page)); |
1980 | ||
5881f737 | 1981 | spin_lock_irqsave(&svm_vm_data_hash_lock, flags); |
3f0d4db7 DV |
1982 | again: |
1983 | vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK; | |
1984 | if (vm_id == 0) { /* id is 1-based, zero is not okay */ | |
1985 | next_vm_id_wrapped = 1; | |
1986 | goto again; | |
1987 | } | |
1988 | /* Is it still in use? Only possible if wrapped at least once */ | |
1989 | if (next_vm_id_wrapped) { | |
81811c16 SC |
1990 | hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) { |
1991 | if (k2->avic_vm_id == vm_id) | |
3f0d4db7 DV |
1992 | goto again; |
1993 | } | |
1994 | } | |
81811c16 SC |
1995 | kvm_svm->avic_vm_id = vm_id; |
1996 | hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id); | |
5881f737 SS |
1997 | spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); |
1998 | ||
44a95dae SS |
1999 | return 0; |
2000 | ||
2001 | free_avic: | |
2002 | avic_vm_destroy(kvm); | |
2003 | return err; | |
6aa8b732 AK |
2004 | } |
2005 | ||
411b44ba SS |
2006 | static inline int |
2007 | avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r) | |
8221c137 | 2008 | { |
411b44ba SS |
2009 | int ret = 0; |
2010 | unsigned long flags; | |
2011 | struct amd_svm_iommu_ir *ir; | |
8221c137 SS |
2012 | struct vcpu_svm *svm = to_svm(vcpu); |
2013 | ||
411b44ba SS |
2014 | if (!kvm_arch_has_assigned_device(vcpu->kvm)) |
2015 | return 0; | |
8221c137 | 2016 | |
411b44ba SS |
2017 | /* |
2018 | * Here, we go through the per-vcpu ir_list to update all existing | |
2019 | * interrupt remapping table entry targeting this vcpu. | |
2020 | */ | |
2021 | spin_lock_irqsave(&svm->ir_list_lock, flags); | |
8221c137 | 2022 | |
411b44ba SS |
2023 | if (list_empty(&svm->ir_list)) |
2024 | goto out; | |
8221c137 | 2025 | |
411b44ba SS |
2026 | list_for_each_entry(ir, &svm->ir_list, node) { |
2027 | ret = amd_iommu_update_ga(cpu, r, ir->data); | |
2028 | if (ret) | |
2029 | break; | |
2030 | } | |
2031 | out: | |
2032 | spin_unlock_irqrestore(&svm->ir_list_lock, flags); | |
2033 | return ret; | |
8221c137 SS |
2034 | } |
2035 | ||
2036 | static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) | |
2037 | { | |
2038 | u64 entry; | |
2039 | /* ID = 0xff (broadcast), ID > 0xff (reserved) */ | |
7d669f50 | 2040 | int h_physical_id = kvm_cpu_get_apicid(cpu); |
8221c137 SS |
2041 | struct vcpu_svm *svm = to_svm(vcpu); |
2042 | ||
2043 | if (!kvm_vcpu_apicv_active(vcpu)) | |
2044 | return; | |
2045 | ||
c9bcd3e3 SS |
2046 | /* |
2047 | * Since the host physical APIC id is 8 bits, | |
2048 | * we can support host APIC ID upto 255. | |
2049 | */ | |
2050 | if (WARN_ON(h_physical_id > AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK)) | |
8221c137 SS |
2051 | return; |
2052 | ||
2053 | entry = READ_ONCE(*(svm->avic_physical_id_cache)); | |
2054 | WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); | |
2055 | ||
2056 | entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK; | |
2057 | entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK); | |
2058 | ||
2059 | entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; | |
2060 | if (svm->avic_is_running) | |
2061 | entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; | |
2062 | ||
2063 | WRITE_ONCE(*(svm->avic_physical_id_cache), entry); | |
411b44ba SS |
2064 | avic_update_iommu_vcpu_affinity(vcpu, h_physical_id, |
2065 | svm->avic_is_running); | |
8221c137 SS |
2066 | } |
2067 | ||
2068 | static void avic_vcpu_put(struct kvm_vcpu *vcpu) | |
2069 | { | |
2070 | u64 entry; | |
2071 | struct vcpu_svm *svm = to_svm(vcpu); | |
2072 | ||
2073 | if (!kvm_vcpu_apicv_active(vcpu)) | |
2074 | return; | |
2075 | ||
2076 | entry = READ_ONCE(*(svm->avic_physical_id_cache)); | |
411b44ba SS |
2077 | if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) |
2078 | avic_update_iommu_vcpu_affinity(vcpu, -1, 0); | |
2079 | ||
8221c137 SS |
2080 | entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; |
2081 | WRITE_ONCE(*(svm->avic_physical_id_cache), entry); | |
6aa8b732 AK |
2082 | } |
2083 | ||
411b44ba SS |
2084 | /** |
2085 | * This function is called during VCPU halt/unhalt. | |
2086 | */ | |
2087 | static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run) | |
2088 | { | |
2089 | struct vcpu_svm *svm = to_svm(vcpu); | |
2090 | ||
2091 | svm->avic_is_running = is_run; | |
2092 | if (is_run) | |
2093 | avic_vcpu_load(vcpu, vcpu->cpu); | |
2094 | else | |
2095 | avic_vcpu_put(vcpu); | |
2096 | } | |
2097 | ||
d28bc9dd | 2098 | static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
04d2cc77 AK |
2099 | { |
2100 | struct vcpu_svm *svm = to_svm(vcpu); | |
66f7b72e JS |
2101 | u32 dummy; |
2102 | u32 eax = 1; | |
04d2cc77 | 2103 | |
518e7b94 | 2104 | vcpu->arch.microcode_version = 0x01000065; |
b2ac58f9 | 2105 | svm->spec_ctrl = 0; |
ccbcd267 | 2106 | svm->virt_spec_ctrl = 0; |
b2ac58f9 | 2107 | |
d28bc9dd NA |
2108 | if (!init_event) { |
2109 | svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE | | |
2110 | MSR_IA32_APICBASE_ENABLE; | |
2111 | if (kvm_vcpu_is_reset_bsp(&svm->vcpu)) | |
2112 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; | |
2113 | } | |
5690891b | 2114 | init_vmcb(svm); |
70433389 | 2115 | |
e911eb3b | 2116 | kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true); |
de3cd117 | 2117 | kvm_rdx_write(vcpu, eax); |
44a95dae SS |
2118 | |
2119 | if (kvm_vcpu_apicv_active(vcpu) && !init_event) | |
2120 | avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE); | |
04d2cc77 AK |
2121 | } |
2122 | ||
dfa20099 SS |
2123 | static int avic_init_vcpu(struct vcpu_svm *svm) |
2124 | { | |
2125 | int ret; | |
2126 | ||
67034bb9 | 2127 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) |
dfa20099 SS |
2128 | return 0; |
2129 | ||
2130 | ret = avic_init_backing_page(&svm->vcpu); | |
2131 | if (ret) | |
2132 | return ret; | |
2133 | ||
2134 | INIT_LIST_HEAD(&svm->ir_list); | |
2135 | spin_lock_init(&svm->ir_list_lock); | |
98d90582 | 2136 | svm->dfr_reg = APIC_DFR_FLAT; |
dfa20099 SS |
2137 | |
2138 | return ret; | |
2139 | } | |
2140 | ||
fb3f0f51 | 2141 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 2142 | { |
a2fa3e9f | 2143 | struct vcpu_svm *svm; |
6aa8b732 | 2144 | struct page *page; |
f65c229c | 2145 | struct page *msrpm_pages; |
b286d5d8 | 2146 | struct page *hsave_page; |
3d6368ef | 2147 | struct page *nested_msrpm_pages; |
fb3f0f51 | 2148 | int err; |
6aa8b732 | 2149 | |
12b58f4e SC |
2150 | BUILD_BUG_ON_MSG(offsetof(struct vcpu_svm, vcpu) != 0, |
2151 | "struct kvm_vcpu must be at offset 0 for arch usercopy region"); | |
2152 | ||
1ec69647 | 2153 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT); |
fb3f0f51 RR |
2154 | if (!svm) { |
2155 | err = -ENOMEM; | |
2156 | goto out; | |
2157 | } | |
2158 | ||
d9a710e5 WL |
2159 | svm->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, |
2160 | GFP_KERNEL_ACCOUNT); | |
2161 | if (!svm->vcpu.arch.user_fpu) { | |
2162 | printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n"); | |
2163 | err = -ENOMEM; | |
2164 | goto free_partial_svm; | |
2165 | } | |
2166 | ||
1ec69647 BG |
2167 | svm->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, |
2168 | GFP_KERNEL_ACCOUNT); | |
b666a4b6 MO |
2169 | if (!svm->vcpu.arch.guest_fpu) { |
2170 | printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n"); | |
2171 | err = -ENOMEM; | |
d9a710e5 | 2172 | goto free_user_fpu; |
b666a4b6 MO |
2173 | } |
2174 | ||
fb3f0f51 RR |
2175 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); |
2176 | if (err) | |
2177 | goto free_svm; | |
2178 | ||
b7af4043 | 2179 | err = -ENOMEM; |
1ec69647 | 2180 | page = alloc_page(GFP_KERNEL_ACCOUNT); |
b7af4043 | 2181 | if (!page) |
fb3f0f51 | 2182 | goto uninit; |
6aa8b732 | 2183 | |
1ec69647 | 2184 | msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER); |
f65c229c | 2185 | if (!msrpm_pages) |
b7af4043 | 2186 | goto free_page1; |
3d6368ef | 2187 | |
1ec69647 | 2188 | nested_msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER); |
3d6368ef | 2189 | if (!nested_msrpm_pages) |
b7af4043 | 2190 | goto free_page2; |
f65c229c | 2191 | |
1ec69647 | 2192 | hsave_page = alloc_page(GFP_KERNEL_ACCOUNT); |
b286d5d8 | 2193 | if (!hsave_page) |
b7af4043 TY |
2194 | goto free_page3; |
2195 | ||
dfa20099 SS |
2196 | err = avic_init_vcpu(svm); |
2197 | if (err) | |
2198 | goto free_page4; | |
44a95dae | 2199 | |
8221c137 SS |
2200 | /* We initialize this flag to true to make sure that the is_running |
2201 | * bit would be set the first time the vcpu is loaded. | |
2202 | */ | |
2203 | svm->avic_is_running = true; | |
2204 | ||
e6aa9abd | 2205 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 2206 | |
b7af4043 TY |
2207 | svm->msrpm = page_address(msrpm_pages); |
2208 | svm_vcpu_init_msrpm(svm->msrpm); | |
2209 | ||
e6aa9abd | 2210 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 2211 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 2212 | |
a2fa3e9f GH |
2213 | svm->vmcb = page_address(page); |
2214 | clear_page(svm->vmcb); | |
d0ec49d4 | 2215 | svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT); |
a2fa3e9f | 2216 | svm->asid_generation = 0; |
5690891b | 2217 | init_vmcb(svm); |
6aa8b732 | 2218 | |
2b036c6b BO |
2219 | svm_init_osvw(&svm->vcpu); |
2220 | ||
fb3f0f51 | 2221 | return &svm->vcpu; |
36241b8c | 2222 | |
44a95dae SS |
2223 | free_page4: |
2224 | __free_page(hsave_page); | |
b7af4043 TY |
2225 | free_page3: |
2226 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
2227 | free_page2: | |
2228 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
2229 | free_page1: | |
2230 | __free_page(page); | |
fb3f0f51 RR |
2231 | uninit: |
2232 | kvm_vcpu_uninit(&svm->vcpu); | |
2233 | free_svm: | |
b666a4b6 | 2234 | kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu); |
d9a710e5 WL |
2235 | free_user_fpu: |
2236 | kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.user_fpu); | |
b666a4b6 | 2237 | free_partial_svm: |
a4770347 | 2238 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
2239 | out: |
2240 | return ERR_PTR(err); | |
6aa8b732 AK |
2241 | } |
2242 | ||
fd65d314 JM |
2243 | static void svm_clear_current_vmcb(struct vmcb *vmcb) |
2244 | { | |
2245 | int i; | |
2246 | ||
2247 | for_each_online_cpu(i) | |
2248 | cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL); | |
2249 | } | |
2250 | ||
6aa8b732 AK |
2251 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) |
2252 | { | |
a2fa3e9f GH |
2253 | struct vcpu_svm *svm = to_svm(vcpu); |
2254 | ||
fd65d314 JM |
2255 | /* |
2256 | * The vmcb page can be recycled, causing a false negative in | |
2257 | * svm_vcpu_load(). So, ensure that no logical CPU has this | |
2258 | * vmcb page recorded as its current vmcb. | |
2259 | */ | |
2260 | svm_clear_current_vmcb(svm->vmcb); | |
2261 | ||
d0ec49d4 | 2262 | __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT)); |
f65c229c | 2263 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
2264 | __free_page(virt_to_page(svm->nested.hsave)); |
2265 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 2266 | kvm_vcpu_uninit(vcpu); |
d9a710e5 | 2267 | kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.user_fpu); |
b666a4b6 | 2268 | kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu); |
a4770347 | 2269 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
2270 | } |
2271 | ||
15ad7146 | 2272 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 2273 | { |
a2fa3e9f | 2274 | struct vcpu_svm *svm = to_svm(vcpu); |
15d45071 | 2275 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
15ad7146 | 2276 | int i; |
0cc5064d | 2277 | |
0cc5064d | 2278 | if (unlikely(cpu != vcpu->cpu)) { |
4b656b12 | 2279 | svm->asid_generation = 0; |
8d28fec4 | 2280 | mark_all_dirty(svm->vmcb); |
0cc5064d | 2281 | } |
94dfbdb3 | 2282 | |
82ca2d10 AK |
2283 | #ifdef CONFIG_X86_64 |
2284 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); | |
2285 | #endif | |
dacccfdd AK |
2286 | savesegment(fs, svm->host.fs); |
2287 | savesegment(gs, svm->host.gs); | |
2288 | svm->host.ldt = kvm_read_ldt(); | |
2289 | ||
94dfbdb3 | 2290 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 2291 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
fbc0db76 | 2292 | |
ad721883 HZ |
2293 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
2294 | u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio; | |
2295 | if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) { | |
2296 | __this_cpu_write(current_tsc_ratio, tsc_ratio); | |
2297 | wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio); | |
2298 | } | |
fbc0db76 | 2299 | } |
46896c73 PB |
2300 | /* This assumes that the kernel never uses MSR_TSC_AUX */ |
2301 | if (static_cpu_has(X86_FEATURE_RDTSCP)) | |
2302 | wrmsrl(MSR_TSC_AUX, svm->tsc_aux); | |
8221c137 | 2303 | |
15d45071 AR |
2304 | if (sd->current_vmcb != svm->vmcb) { |
2305 | sd->current_vmcb = svm->vmcb; | |
2306 | indirect_branch_prediction_barrier(); | |
2307 | } | |
8221c137 | 2308 | avic_vcpu_load(vcpu, cpu); |
6aa8b732 AK |
2309 | } |
2310 | ||
2311 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
2312 | { | |
a2fa3e9f | 2313 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
2314 | int i; |
2315 | ||
8221c137 SS |
2316 | avic_vcpu_put(vcpu); |
2317 | ||
e1beb1d3 | 2318 | ++vcpu->stat.host_state_reload; |
dacccfdd AK |
2319 | kvm_load_ldt(svm->host.ldt); |
2320 | #ifdef CONFIG_X86_64 | |
2321 | loadsegment(fs, svm->host.fs); | |
296f781a | 2322 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase); |
893a5ab6 | 2323 | load_gs_index(svm->host.gs); |
dacccfdd | 2324 | #else |
831ca609 | 2325 | #ifdef CONFIG_X86_32_LAZY_GS |
dacccfdd | 2326 | loadsegment(gs, svm->host.gs); |
831ca609 | 2327 | #endif |
dacccfdd | 2328 | #endif |
94dfbdb3 | 2329 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 2330 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
2331 | } |
2332 | ||
8221c137 SS |
2333 | static void svm_vcpu_blocking(struct kvm_vcpu *vcpu) |
2334 | { | |
2335 | avic_set_running(vcpu, false); | |
2336 | } | |
2337 | ||
2338 | static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu) | |
2339 | { | |
2340 | avic_set_running(vcpu, true); | |
2341 | } | |
2342 | ||
6aa8b732 AK |
2343 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
2344 | { | |
9b611747 LP |
2345 | struct vcpu_svm *svm = to_svm(vcpu); |
2346 | unsigned long rflags = svm->vmcb->save.rflags; | |
2347 | ||
2348 | if (svm->nmi_singlestep) { | |
2349 | /* Hide our flags if they were not set by the guest */ | |
2350 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF)) | |
2351 | rflags &= ~X86_EFLAGS_TF; | |
2352 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF)) | |
2353 | rflags &= ~X86_EFLAGS_RF; | |
2354 | } | |
2355 | return rflags; | |
6aa8b732 AK |
2356 | } |
2357 | ||
2358 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
2359 | { | |
9b611747 LP |
2360 | if (to_svm(vcpu)->nmi_singlestep) |
2361 | rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); | |
2362 | ||
ae9fedc7 | 2363 | /* |
bb3541f1 | 2364 | * Any change of EFLAGS.VM is accompanied by a reload of SS |
ae9fedc7 PB |
2365 | * (caused by either a task switch or an inter-privilege IRET), |
2366 | * so we do not need to update the CPL here. | |
2367 | */ | |
a2fa3e9f | 2368 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
2369 | } |
2370 | ||
6de4f3ad AK |
2371 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
2372 | { | |
2373 | switch (reg) { | |
2374 | case VCPU_EXREG_PDPTR: | |
2375 | BUG_ON(!npt_enabled); | |
9f8fe504 | 2376 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
6de4f3ad AK |
2377 | break; |
2378 | default: | |
34059c25 | 2379 | WARN_ON_ONCE(1); |
6de4f3ad AK |
2380 | } |
2381 | } | |
2382 | ||
f0b85051 AG |
2383 | static void svm_set_vintr(struct vcpu_svm *svm) |
2384 | { | |
8a05a1b8 | 2385 | set_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
2386 | } |
2387 | ||
2388 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
2389 | { | |
8a05a1b8 | 2390 | clr_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
2391 | } |
2392 | ||
6aa8b732 AK |
2393 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
2394 | { | |
a2fa3e9f | 2395 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
2396 | |
2397 | switch (seg) { | |
2398 | case VCPU_SREG_CS: return &save->cs; | |
2399 | case VCPU_SREG_DS: return &save->ds; | |
2400 | case VCPU_SREG_ES: return &save->es; | |
2401 | case VCPU_SREG_FS: return &save->fs; | |
2402 | case VCPU_SREG_GS: return &save->gs; | |
2403 | case VCPU_SREG_SS: return &save->ss; | |
2404 | case VCPU_SREG_TR: return &save->tr; | |
2405 | case VCPU_SREG_LDTR: return &save->ldtr; | |
2406 | } | |
2407 | BUG(); | |
8b6d44c7 | 2408 | return NULL; |
6aa8b732 AK |
2409 | } |
2410 | ||
2411 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
2412 | { | |
2413 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
2414 | ||
2415 | return s->base; | |
2416 | } | |
2417 | ||
2418 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
2419 | struct kvm_segment *var, int seg) | |
2420 | { | |
2421 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
2422 | ||
2423 | var->base = s->base; | |
2424 | var->limit = s->limit; | |
2425 | var->selector = s->selector; | |
2426 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
2427 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
2428 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
2429 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
2430 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
2431 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
2432 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
80112c89 JM |
2433 | |
2434 | /* | |
2435 | * AMD CPUs circa 2014 track the G bit for all segments except CS. | |
2436 | * However, the SVM spec states that the G bit is not observed by the | |
2437 | * CPU, and some VMware virtual CPUs drop the G bit for all segments. | |
2438 | * So let's synthesize a legal G bit for all segments, this helps | |
2439 | * running KVM nested. It also helps cross-vendor migration, because | |
2440 | * Intel's vmentry has a check on the 'G' bit. | |
2441 | */ | |
2442 | var->g = s->limit > 0xfffff; | |
25022acc | 2443 | |
e0231715 JR |
2444 | /* |
2445 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
2446 | * for cross vendor migration purposes by "not present" |
2447 | */ | |
8eae9570 | 2448 | var->unusable = !var->present; |
19bca6ab | 2449 | |
1fbdc7a5 | 2450 | switch (seg) { |
1fbdc7a5 AP |
2451 | case VCPU_SREG_TR: |
2452 | /* | |
2453 | * Work around a bug where the busy flag in the tr selector | |
2454 | * isn't exposed | |
2455 | */ | |
c0d09828 | 2456 | var->type |= 0x2; |
1fbdc7a5 AP |
2457 | break; |
2458 | case VCPU_SREG_DS: | |
2459 | case VCPU_SREG_ES: | |
2460 | case VCPU_SREG_FS: | |
2461 | case VCPU_SREG_GS: | |
2462 | /* | |
2463 | * The accessed bit must always be set in the segment | |
2464 | * descriptor cache, although it can be cleared in the | |
2465 | * descriptor, the cached bit always remains at 1. Since | |
2466 | * Intel has a check on this, set it here to support | |
2467 | * cross-vendor migration. | |
2468 | */ | |
2469 | if (!var->unusable) | |
2470 | var->type |= 0x1; | |
2471 | break; | |
b586eb02 | 2472 | case VCPU_SREG_SS: |
e0231715 JR |
2473 | /* |
2474 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
2475 | * descriptor is left as 1, although the whole segment has |
2476 | * been made unusable. Clear it here to pass an Intel VMX | |
2477 | * entry check when cross vendor migrating. | |
2478 | */ | |
2479 | if (var->unusable) | |
2480 | var->db = 0; | |
d9c1b543 | 2481 | /* This is symmetric with svm_set_segment() */ |
33b458d2 | 2482 | var->dpl = to_svm(vcpu)->vmcb->save.cpl; |
b586eb02 | 2483 | break; |
1fbdc7a5 | 2484 | } |
6aa8b732 AK |
2485 | } |
2486 | ||
2e4d2653 IE |
2487 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
2488 | { | |
2489 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
2490 | ||
2491 | return save->cpl; | |
2492 | } | |
2493 | ||
89a27f4d | 2494 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2495 | { |
a2fa3e9f GH |
2496 | struct vcpu_svm *svm = to_svm(vcpu); |
2497 | ||
89a27f4d GN |
2498 | dt->size = svm->vmcb->save.idtr.limit; |
2499 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
2500 | } |
2501 | ||
89a27f4d | 2502 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2503 | { |
a2fa3e9f GH |
2504 | struct vcpu_svm *svm = to_svm(vcpu); |
2505 | ||
89a27f4d GN |
2506 | svm->vmcb->save.idtr.limit = dt->size; |
2507 | svm->vmcb->save.idtr.base = dt->address ; | |
17a703cb | 2508 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
2509 | } |
2510 | ||
89a27f4d | 2511 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2512 | { |
a2fa3e9f GH |
2513 | struct vcpu_svm *svm = to_svm(vcpu); |
2514 | ||
89a27f4d GN |
2515 | dt->size = svm->vmcb->save.gdtr.limit; |
2516 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
2517 | } |
2518 | ||
89a27f4d | 2519 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2520 | { |
a2fa3e9f GH |
2521 | struct vcpu_svm *svm = to_svm(vcpu); |
2522 | ||
89a27f4d GN |
2523 | svm->vmcb->save.gdtr.limit = dt->size; |
2524 | svm->vmcb->save.gdtr.base = dt->address ; | |
17a703cb | 2525 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
2526 | } |
2527 | ||
e8467fda AK |
2528 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
2529 | { | |
2530 | } | |
2531 | ||
25c4c276 | 2532 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
2533 | { |
2534 | } | |
2535 | ||
d225157b AK |
2536 | static void update_cr0_intercept(struct vcpu_svm *svm) |
2537 | { | |
2538 | ulong gcr0 = svm->vcpu.arch.cr0; | |
2539 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
2540 | ||
bd7e5b08 PB |
2541 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) |
2542 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
d225157b | 2543 | |
dcca1a65 | 2544 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 2545 | |
bd7e5b08 | 2546 | if (gcr0 == *hcr0) { |
4ee546b4 RJ |
2547 | clr_cr_intercept(svm, INTERCEPT_CR0_READ); |
2548 | clr_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b | 2549 | } else { |
4ee546b4 RJ |
2550 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
2551 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b AK |
2552 | } |
2553 | } | |
2554 | ||
6aa8b732 AK |
2555 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
2556 | { | |
a2fa3e9f GH |
2557 | struct vcpu_svm *svm = to_svm(vcpu); |
2558 | ||
05b3e0c2 | 2559 | #ifdef CONFIG_X86_64 |
f6801dff | 2560 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 2561 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 2562 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 2563 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
2564 | } |
2565 | ||
d77c26fc | 2566 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 2567 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 2568 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
2569 | } |
2570 | } | |
2571 | #endif | |
ad312c7c | 2572 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
2573 | |
2574 | if (!npt_enabled) | |
2575 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 | 2576 | |
bcf166a9 PB |
2577 | /* |
2578 | * re-enable caching here because the QEMU bios | |
2579 | * does not do it - this results in some delay at | |
2580 | * reboot | |
2581 | */ | |
2582 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
2583 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 2584 | svm->vmcb->save.cr0 = cr0; |
dcca1a65 | 2585 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 2586 | update_cr0_intercept(svm); |
6aa8b732 AK |
2587 | } |
2588 | ||
5e1746d6 | 2589 | static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 2590 | { |
1e02ce4c | 2591 | unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE; |
e5eab0ce JR |
2592 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
2593 | ||
5e1746d6 NHE |
2594 | if (cr4 & X86_CR4_VMXE) |
2595 | return 1; | |
2596 | ||
e5eab0ce | 2597 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) |
c2ba05cc | 2598 | svm_flush_tlb(vcpu, true); |
6394b649 | 2599 | |
ec077263 JR |
2600 | vcpu->arch.cr4 = cr4; |
2601 | if (!npt_enabled) | |
2602 | cr4 |= X86_CR4_PAE; | |
6394b649 | 2603 | cr4 |= host_cr4_mce; |
ec077263 | 2604 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
dcca1a65 | 2605 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
5e1746d6 | 2606 | return 0; |
6aa8b732 AK |
2607 | } |
2608 | ||
2609 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
2610 | struct kvm_segment *var, int seg) | |
2611 | { | |
a2fa3e9f | 2612 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
2613 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
2614 | ||
2615 | s->base = var->base; | |
2616 | s->limit = var->limit; | |
2617 | s->selector = var->selector; | |
d9c1b543 RP |
2618 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); |
2619 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
2620 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
2621 | s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT; | |
2622 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
2623 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
2624 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
2625 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
ae9fedc7 PB |
2626 | |
2627 | /* | |
2628 | * This is always accurate, except if SYSRET returned to a segment | |
2629 | * with SS.DPL != 3. Intel does not have this quirk, and always | |
2630 | * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it | |
2631 | * would entail passing the CPL to userspace and back. | |
2632 | */ | |
2633 | if (seg == VCPU_SREG_SS) | |
d9c1b543 RP |
2634 | /* This is symmetric with svm_get_segment() */ |
2635 | svm->vmcb->save.cpl = (var->dpl & 3); | |
6aa8b732 | 2636 | |
060d0c9a | 2637 | mark_dirty(svm->vmcb, VMCB_SEG); |
6aa8b732 AK |
2638 | } |
2639 | ||
cbdb967a | 2640 | static void update_bp_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 2641 | { |
d0bfb940 JK |
2642 | struct vcpu_svm *svm = to_svm(vcpu); |
2643 | ||
18c918c5 | 2644 | clr_exception_intercept(svm, BP_VECTOR); |
44c11430 | 2645 | |
d0bfb940 | 2646 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
d0bfb940 | 2647 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
18c918c5 | 2648 | set_exception_intercept(svm, BP_VECTOR); |
d0bfb940 JK |
2649 | } else |
2650 | vcpu->guest_debug = 0; | |
44c11430 GN |
2651 | } |
2652 | ||
0fe1e009 | 2653 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 2654 | { |
0fe1e009 TH |
2655 | if (sd->next_asid > sd->max_asid) { |
2656 | ++sd->asid_generation; | |
4faefff3 | 2657 | sd->next_asid = sd->min_asid; |
a2fa3e9f | 2658 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
2659 | } |
2660 | ||
0fe1e009 TH |
2661 | svm->asid_generation = sd->asid_generation; |
2662 | svm->vmcb->control.asid = sd->next_asid++; | |
d48086d1 JR |
2663 | |
2664 | mark_dirty(svm->vmcb, VMCB_ASID); | |
6aa8b732 AK |
2665 | } |
2666 | ||
73aaf249 JK |
2667 | static u64 svm_get_dr6(struct kvm_vcpu *vcpu) |
2668 | { | |
2669 | return to_svm(vcpu)->vmcb->save.dr6; | |
2670 | } | |
2671 | ||
2672 | static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value) | |
2673 | { | |
2674 | struct vcpu_svm *svm = to_svm(vcpu); | |
2675 | ||
2676 | svm->vmcb->save.dr6 = value; | |
2677 | mark_dirty(svm->vmcb, VMCB_DR); | |
2678 | } | |
2679 | ||
facb0139 PB |
2680 | static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
2681 | { | |
2682 | struct vcpu_svm *svm = to_svm(vcpu); | |
2683 | ||
2684 | get_debugreg(vcpu->arch.db[0], 0); | |
2685 | get_debugreg(vcpu->arch.db[1], 1); | |
2686 | get_debugreg(vcpu->arch.db[2], 2); | |
2687 | get_debugreg(vcpu->arch.db[3], 3); | |
2688 | vcpu->arch.dr6 = svm_get_dr6(vcpu); | |
2689 | vcpu->arch.dr7 = svm->vmcb->save.dr7; | |
2690 | ||
2691 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
2692 | set_dr_intercepts(svm); | |
2693 | } | |
2694 | ||
020df079 | 2695 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 2696 | { |
42dbaa5a | 2697 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 2698 | |
020df079 | 2699 | svm->vmcb->save.dr7 = value; |
72214b96 | 2700 | mark_dirty(svm->vmcb, VMCB_DR); |
6aa8b732 AK |
2701 | } |
2702 | ||
851ba692 | 2703 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 2704 | { |
0ede79e1 | 2705 | u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2); |
1261bfa3 | 2706 | u64 error_code = svm->vmcb->control.exit_info_1; |
6aa8b732 | 2707 | |
1261bfa3 | 2708 | return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address, |
00b10fe1 BS |
2709 | static_cpu_has(X86_FEATURE_DECODEASSISTS) ? |
2710 | svm->vmcb->control.insn_bytes : NULL, | |
d0006530 PB |
2711 | svm->vmcb->control.insn_len); |
2712 | } | |
2713 | ||
2714 | static int npf_interception(struct vcpu_svm *svm) | |
2715 | { | |
0ede79e1 | 2716 | u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2); |
d0006530 PB |
2717 | u64 error_code = svm->vmcb->control.exit_info_1; |
2718 | ||
2719 | trace_kvm_page_fault(fault_address, error_code); | |
2720 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code, | |
00b10fe1 BS |
2721 | static_cpu_has(X86_FEATURE_DECODEASSISTS) ? |
2722 | svm->vmcb->control.insn_bytes : NULL, | |
d0006530 | 2723 | svm->vmcb->control.insn_len); |
6aa8b732 AK |
2724 | } |
2725 | ||
851ba692 | 2726 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 2727 | { |
851ba692 | 2728 | struct kvm_run *kvm_run = svm->vcpu.run; |
99c22179 | 2729 | struct kvm_vcpu *vcpu = &svm->vcpu; |
851ba692 | 2730 | |
d0bfb940 | 2731 | if (!(svm->vcpu.guest_debug & |
44c11430 | 2732 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 2733 | !svm->nmi_singlestep) { |
d0bfb940 JK |
2734 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
2735 | return 1; | |
2736 | } | |
44c11430 | 2737 | |
6be7d306 | 2738 | if (svm->nmi_singlestep) { |
4aebd0e9 | 2739 | disable_nmi_singlestep(svm); |
99c22179 VK |
2740 | /* Make sure we check for pending NMIs upon entry */ |
2741 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
44c11430 GN |
2742 | } |
2743 | ||
2744 | if (svm->vcpu.guest_debug & | |
e0231715 | 2745 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
2746 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
2747 | kvm_run->debug.arch.pc = | |
2748 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
2749 | kvm_run->debug.arch.exception = DB_VECTOR; | |
2750 | return 0; | |
2751 | } | |
2752 | ||
2753 | return 1; | |
d0bfb940 JK |
2754 | } |
2755 | ||
851ba692 | 2756 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 2757 | { |
851ba692 AK |
2758 | struct kvm_run *kvm_run = svm->vcpu.run; |
2759 | ||
d0bfb940 JK |
2760 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
2761 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
2762 | kvm_run->debug.arch.exception = BP_VECTOR; | |
2763 | return 0; | |
2764 | } | |
2765 | ||
851ba692 | 2766 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 | 2767 | { |
082d06ed | 2768 | return handle_ud(&svm->vcpu); |
7aa81cc0 AL |
2769 | } |
2770 | ||
54a20552 EN |
2771 | static int ac_interception(struct vcpu_svm *svm) |
2772 | { | |
2773 | kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0); | |
2774 | return 1; | |
2775 | } | |
2776 | ||
9718420e LA |
2777 | static int gp_interception(struct vcpu_svm *svm) |
2778 | { | |
2779 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
2780 | u32 error_code = svm->vmcb->control.exit_info_1; | |
9718420e LA |
2781 | |
2782 | WARN_ON_ONCE(!enable_vmware_backdoor); | |
2783 | ||
a6c6ed1e SC |
2784 | /* |
2785 | * VMware backdoor emulation on #GP interception only handles IN{S}, | |
2786 | * OUT{S}, and RDPMC, none of which generate a non-zero error code. | |
2787 | */ | |
2788 | if (error_code) { | |
2789 | kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); | |
2790 | return 1; | |
2791 | } | |
60fc3d02 | 2792 | return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP); |
9718420e LA |
2793 | } |
2794 | ||
67ec6607 JR |
2795 | static bool is_erratum_383(void) |
2796 | { | |
2797 | int err, i; | |
2798 | u64 value; | |
2799 | ||
2800 | if (!erratum_383_found) | |
2801 | return false; | |
2802 | ||
2803 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
2804 | if (err) | |
2805 | return false; | |
2806 | ||
2807 | /* Bit 62 may or may not be set for this mce */ | |
2808 | value &= ~(1ULL << 62); | |
2809 | ||
2810 | if (value != 0xb600000000010015ULL) | |
2811 | return false; | |
2812 | ||
2813 | /* Clear MCi_STATUS registers */ | |
2814 | for (i = 0; i < 6; ++i) | |
2815 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
2816 | ||
2817 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
2818 | if (!err) { | |
2819 | u32 low, high; | |
2820 | ||
2821 | value &= ~(1ULL << 2); | |
2822 | low = lower_32_bits(value); | |
2823 | high = upper_32_bits(value); | |
2824 | ||
2825 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
2826 | } | |
2827 | ||
2828 | /* Flush tlb to evict multi-match entries */ | |
2829 | __flush_tlb_all(); | |
2830 | ||
2831 | return true; | |
2832 | } | |
2833 | ||
fe5913e4 | 2834 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 2835 | { |
67ec6607 JR |
2836 | if (is_erratum_383()) { |
2837 | /* | |
2838 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
2839 | * guest. | |
2840 | */ | |
2841 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
2842 | ||
a8eeb04a | 2843 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
2844 | |
2845 | return; | |
2846 | } | |
2847 | ||
53371b50 JR |
2848 | /* |
2849 | * On an #MC intercept the MCE handler is not called automatically in | |
2850 | * the host. So do it by hand here. | |
2851 | */ | |
2852 | asm volatile ( | |
2853 | "int $0x12\n"); | |
2854 | /* not sure if we ever come back to this point */ | |
2855 | ||
fe5913e4 JR |
2856 | return; |
2857 | } | |
2858 | ||
2859 | static int mc_interception(struct vcpu_svm *svm) | |
2860 | { | |
53371b50 JR |
2861 | return 1; |
2862 | } | |
2863 | ||
851ba692 | 2864 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 2865 | { |
851ba692 AK |
2866 | struct kvm_run *kvm_run = svm->vcpu.run; |
2867 | ||
46fe4ddd JR |
2868 | /* |
2869 | * VMCB is undefined after a SHUTDOWN intercept | |
2870 | * so reinitialize it. | |
2871 | */ | |
a2fa3e9f | 2872 | clear_page(svm->vmcb); |
5690891b | 2873 | init_vmcb(svm); |
46fe4ddd JR |
2874 | |
2875 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
2876 | return 0; | |
2877 | } | |
2878 | ||
851ba692 | 2879 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 2880 | { |
cf8f70bf | 2881 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 2882 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
dca7f128 | 2883 | int size, in, string; |
039576c0 | 2884 | unsigned port; |
6aa8b732 | 2885 | |
e756fc62 | 2886 | ++svm->vcpu.stat.io_exits; |
e70669ab | 2887 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 2888 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
8370c3d0 | 2889 | if (string) |
60fc3d02 | 2890 | return kvm_emulate_instruction(vcpu, 0); |
cf8f70bf | 2891 | |
039576c0 AK |
2892 | port = io_info >> 16; |
2893 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 2894 | svm->next_rip = svm->vmcb->control.exit_info_2; |
cf8f70bf | 2895 | |
dca7f128 | 2896 | return kvm_fast_pio(&svm->vcpu, size, port, in); |
6aa8b732 AK |
2897 | } |
2898 | ||
851ba692 | 2899 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
2900 | { |
2901 | return 1; | |
2902 | } | |
2903 | ||
851ba692 | 2904 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
2905 | { |
2906 | ++svm->vcpu.stat.irq_exits; | |
2907 | return 1; | |
2908 | } | |
2909 | ||
851ba692 | 2910 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
2911 | { |
2912 | return 1; | |
2913 | } | |
2914 | ||
851ba692 | 2915 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 2916 | { |
e756fc62 | 2917 | return kvm_emulate_halt(&svm->vcpu); |
6aa8b732 AK |
2918 | } |
2919 | ||
851ba692 | 2920 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 2921 | { |
0d9c055e | 2922 | return kvm_emulate_hypercall(&svm->vcpu); |
02e235bc AK |
2923 | } |
2924 | ||
5bd2edc3 JR |
2925 | static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) |
2926 | { | |
2927 | struct vcpu_svm *svm = to_svm(vcpu); | |
2928 | ||
2929 | return svm->nested.nested_cr3; | |
2930 | } | |
2931 | ||
e4e517b4 AK |
2932 | static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index) |
2933 | { | |
2934 | struct vcpu_svm *svm = to_svm(vcpu); | |
2935 | u64 cr3 = svm->nested.nested_cr3; | |
2936 | u64 pdpte; | |
2937 | int ret; | |
2938 | ||
d0ec49d4 | 2939 | ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte, |
54bf36aa | 2940 | offset_in_page(cr3) + index * 8, 8); |
e4e517b4 AK |
2941 | if (ret) |
2942 | return 0; | |
2943 | return pdpte; | |
2944 | } | |
2945 | ||
5bd2edc3 JR |
2946 | static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu, |
2947 | unsigned long root) | |
2948 | { | |
2949 | struct vcpu_svm *svm = to_svm(vcpu); | |
2950 | ||
d0ec49d4 | 2951 | svm->vmcb->control.nested_cr3 = __sme_set(root); |
b2747166 | 2952 | mark_dirty(svm->vmcb, VMCB_NPT); |
5bd2edc3 JR |
2953 | } |
2954 | ||
6389ee94 AK |
2955 | static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, |
2956 | struct x86_exception *fault) | |
5bd2edc3 JR |
2957 | { |
2958 | struct vcpu_svm *svm = to_svm(vcpu); | |
2959 | ||
5e352519 PB |
2960 | if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) { |
2961 | /* | |
2962 | * TODO: track the cause of the nested page fault, and | |
2963 | * correctly fill in the high bits of exit_info_1. | |
2964 | */ | |
2965 | svm->vmcb->control.exit_code = SVM_EXIT_NPF; | |
2966 | svm->vmcb->control.exit_code_hi = 0; | |
2967 | svm->vmcb->control.exit_info_1 = (1ULL << 32); | |
2968 | svm->vmcb->control.exit_info_2 = fault->address; | |
2969 | } | |
2970 | ||
2971 | svm->vmcb->control.exit_info_1 &= ~0xffffffffULL; | |
2972 | svm->vmcb->control.exit_info_1 |= fault->error_code; | |
2973 | ||
2974 | /* | |
2975 | * The present bit is always zero for page structure faults on real | |
2976 | * hardware. | |
2977 | */ | |
2978 | if (svm->vmcb->control.exit_info_1 & (2ULL << 32)) | |
2979 | svm->vmcb->control.exit_info_1 &= ~1; | |
5bd2edc3 JR |
2980 | |
2981 | nested_svm_vmexit(svm); | |
2982 | } | |
2983 | ||
8a3c1a33 | 2984 | static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) |
4b16184c | 2985 | { |
ad896af0 | 2986 | WARN_ON(mmu_is_nested(vcpu)); |
3cf85f9f VK |
2987 | |
2988 | vcpu->arch.mmu = &vcpu->arch.guest_mmu; | |
ad896af0 | 2989 | kvm_init_shadow_mmu(vcpu); |
44dd3ffa VK |
2990 | vcpu->arch.mmu->set_cr3 = nested_svm_set_tdp_cr3; |
2991 | vcpu->arch.mmu->get_cr3 = nested_svm_get_tdp_cr3; | |
2992 | vcpu->arch.mmu->get_pdptr = nested_svm_get_tdp_pdptr; | |
2993 | vcpu->arch.mmu->inject_page_fault = nested_svm_inject_npf_exit; | |
2994 | vcpu->arch.mmu->shadow_root_level = get_npt_level(vcpu); | |
2995 | reset_shadow_zero_bits_mask(vcpu, vcpu->arch.mmu); | |
4b16184c | 2996 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; |
4b16184c JR |
2997 | } |
2998 | ||
2999 | static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
3000 | { | |
3cf85f9f | 3001 | vcpu->arch.mmu = &vcpu->arch.root_mmu; |
44dd3ffa | 3002 | vcpu->arch.walk_mmu = &vcpu->arch.root_mmu; |
4b16184c JR |
3003 | } |
3004 | ||
c0725420 AG |
3005 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
3006 | { | |
e9196ceb DC |
3007 | if (!(svm->vcpu.arch.efer & EFER_SVME) || |
3008 | !is_paging(&svm->vcpu)) { | |
c0725420 AG |
3009 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
3010 | return 1; | |
3011 | } | |
3012 | ||
3013 | if (svm->vmcb->save.cpl) { | |
3014 | kvm_inject_gp(&svm->vcpu, 0); | |
3015 | return 1; | |
3016 | } | |
3017 | ||
e9196ceb | 3018 | return 0; |
c0725420 AG |
3019 | } |
3020 | ||
cf74a78b AG |
3021 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
3022 | bool has_error_code, u32 error_code) | |
3023 | { | |
b8e88bc8 JR |
3024 | int vmexit; |
3025 | ||
2030753d | 3026 | if (!is_guest_mode(&svm->vcpu)) |
0295ad7d | 3027 | return 0; |
cf74a78b | 3028 | |
adfe20fb WL |
3029 | vmexit = nested_svm_intercept(svm); |
3030 | if (vmexit != NESTED_EXIT_DONE) | |
3031 | return 0; | |
3032 | ||
0295ad7d JR |
3033 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
3034 | svm->vmcb->control.exit_code_hi = 0; | |
3035 | svm->vmcb->control.exit_info_1 = error_code; | |
b96fb439 PB |
3036 | |
3037 | /* | |
da998b46 JM |
3038 | * EXITINFO2 is undefined for all exception intercepts other |
3039 | * than #PF. | |
b96fb439 | 3040 | */ |
adfe20fb WL |
3041 | if (svm->vcpu.arch.exception.nested_apf) |
3042 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token; | |
da998b46 JM |
3043 | else if (svm->vcpu.arch.exception.has_payload) |
3044 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.exception.payload; | |
adfe20fb WL |
3045 | else |
3046 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
b8e88bc8 | 3047 | |
adfe20fb | 3048 | svm->nested.exit_required = true; |
b8e88bc8 | 3049 | return vmexit; |
cf74a78b AG |
3050 | } |
3051 | ||
8fe54654 JR |
3052 | /* This function returns true if it is save to enable the irq window */ |
3053 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 3054 | { |
2030753d | 3055 | if (!is_guest_mode(&svm->vcpu)) |
8fe54654 | 3056 | return true; |
cf74a78b | 3057 | |
26666957 | 3058 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 3059 | return true; |
cf74a78b | 3060 | |
26666957 | 3061 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 3062 | return false; |
cf74a78b | 3063 | |
a0a07cd2 GN |
3064 | /* |
3065 | * if vmexit was already requested (by intercepted exception | |
3066 | * for instance) do not overwrite it with "external interrupt" | |
3067 | * vmexit. | |
3068 | */ | |
3069 | if (svm->nested.exit_required) | |
3070 | return false; | |
3071 | ||
197717d5 JR |
3072 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
3073 | svm->vmcb->control.exit_info_1 = 0; | |
3074 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 3075 | |
cd3ff653 JR |
3076 | if (svm->nested.intercept & 1ULL) { |
3077 | /* | |
3078 | * The #vmexit can't be emulated here directly because this | |
c5ec2e56 | 3079 | * code path runs with irqs and preemption disabled. A |
cd3ff653 JR |
3080 | * #vmexit emulation might sleep. Only signal request for |
3081 | * the #vmexit here. | |
3082 | */ | |
3083 | svm->nested.exit_required = true; | |
236649de | 3084 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 3085 | return false; |
cf74a78b AG |
3086 | } |
3087 | ||
8fe54654 | 3088 | return true; |
cf74a78b AG |
3089 | } |
3090 | ||
887f500c JR |
3091 | /* This function returns true if it is save to enable the nmi window */ |
3092 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
3093 | { | |
2030753d | 3094 | if (!is_guest_mode(&svm->vcpu)) |
887f500c JR |
3095 | return true; |
3096 | ||
3097 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
3098 | return true; | |
3099 | ||
3100 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
3101 | svm->nested.exit_required = true; | |
3102 | ||
3103 | return false; | |
cf74a78b AG |
3104 | } |
3105 | ||
ce2ac085 JR |
3106 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
3107 | { | |
9bf41833 JK |
3108 | unsigned port, size, iopm_len; |
3109 | u16 val, mask; | |
3110 | u8 start_bit; | |
ce2ac085 | 3111 | u64 gpa; |
34f80cfa | 3112 | |
ce2ac085 JR |
3113 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
3114 | return NESTED_EXIT_HOST; | |
34f80cfa | 3115 | |
ce2ac085 | 3116 | port = svm->vmcb->control.exit_info_1 >> 16; |
9bf41833 JK |
3117 | size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >> |
3118 | SVM_IOIO_SIZE_SHIFT; | |
ce2ac085 | 3119 | gpa = svm->nested.vmcb_iopm + (port / 8); |
9bf41833 JK |
3120 | start_bit = port % 8; |
3121 | iopm_len = (start_bit + size > 8) ? 2 : 1; | |
3122 | mask = (0xf >> (4 - size)) << start_bit; | |
3123 | val = 0; | |
ce2ac085 | 3124 | |
54bf36aa | 3125 | if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len)) |
9bf41833 | 3126 | return NESTED_EXIT_DONE; |
ce2ac085 | 3127 | |
9bf41833 | 3128 | return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
34f80cfa JR |
3129 | } |
3130 | ||
d2477826 | 3131 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 3132 | { |
0d6b3537 JR |
3133 | u32 offset, msr, value; |
3134 | int write, mask; | |
4c2161ae | 3135 | |
3d62d9aa | 3136 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 3137 | return NESTED_EXIT_HOST; |
3d62d9aa | 3138 | |
0d6b3537 JR |
3139 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
3140 | offset = svm_msrpm_offset(msr); | |
3141 | write = svm->vmcb->control.exit_info_1 & 1; | |
3142 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 3143 | |
0d6b3537 JR |
3144 | if (offset == MSR_INVALID) |
3145 | return NESTED_EXIT_DONE; | |
4c2161ae | 3146 | |
0d6b3537 JR |
3147 | /* Offset is in 32 bit units but need in 8 bit units */ |
3148 | offset *= 4; | |
4c2161ae | 3149 | |
54bf36aa | 3150 | if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4)) |
0d6b3537 | 3151 | return NESTED_EXIT_DONE; |
3d62d9aa | 3152 | |
0d6b3537 | 3153 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
3154 | } |
3155 | ||
ab2f4d73 LP |
3156 | /* DB exceptions for our internal use must not cause vmexit */ |
3157 | static int nested_svm_intercept_db(struct vcpu_svm *svm) | |
3158 | { | |
3159 | unsigned long dr6; | |
3160 | ||
3161 | /* if we're not singlestepping, it's not ours */ | |
3162 | if (!svm->nmi_singlestep) | |
3163 | return NESTED_EXIT_DONE; | |
3164 | ||
3165 | /* if it's not a singlestep exception, it's not ours */ | |
3166 | if (kvm_get_dr(&svm->vcpu, 6, &dr6)) | |
3167 | return NESTED_EXIT_DONE; | |
3168 | if (!(dr6 & DR6_BS)) | |
3169 | return NESTED_EXIT_DONE; | |
3170 | ||
3171 | /* if the guest is singlestepping, it should get the vmexit */ | |
3172 | if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) { | |
3173 | disable_nmi_singlestep(svm); | |
3174 | return NESTED_EXIT_DONE; | |
3175 | } | |
3176 | ||
3177 | /* it's ours, the nested hypervisor must not see this one */ | |
3178 | return NESTED_EXIT_HOST; | |
3179 | } | |
3180 | ||
410e4d57 | 3181 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 3182 | { |
cf74a78b | 3183 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 3184 | |
410e4d57 JR |
3185 | switch (exit_code) { |
3186 | case SVM_EXIT_INTR: | |
3187 | case SVM_EXIT_NMI: | |
ff47a49b | 3188 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 3189 | return NESTED_EXIT_HOST; |
410e4d57 | 3190 | case SVM_EXIT_NPF: |
e0231715 | 3191 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
3192 | if (npt_enabled) |
3193 | return NESTED_EXIT_HOST; | |
3194 | break; | |
410e4d57 | 3195 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
631bc487 | 3196 | /* When we're shadowing, trap PFs, but not async PF */ |
1261bfa3 | 3197 | if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0) |
410e4d57 JR |
3198 | return NESTED_EXIT_HOST; |
3199 | break; | |
3200 | default: | |
3201 | break; | |
cf74a78b AG |
3202 | } |
3203 | ||
410e4d57 JR |
3204 | return NESTED_EXIT_CONTINUE; |
3205 | } | |
3206 | ||
3207 | /* | |
3208 | * If this function returns true, this #vmexit was already handled | |
3209 | */ | |
b8e88bc8 | 3210 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
3211 | { |
3212 | u32 exit_code = svm->vmcb->control.exit_code; | |
3213 | int vmexit = NESTED_EXIT_HOST; | |
3214 | ||
cf74a78b | 3215 | switch (exit_code) { |
9c4e40b9 | 3216 | case SVM_EXIT_MSR: |
3d62d9aa | 3217 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 3218 | break; |
ce2ac085 JR |
3219 | case SVM_EXIT_IOIO: |
3220 | vmexit = nested_svm_intercept_ioio(svm); | |
3221 | break; | |
4ee546b4 RJ |
3222 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: { |
3223 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0); | |
3224 | if (svm->nested.intercept_cr & bit) | |
410e4d57 | 3225 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
3226 | break; |
3227 | } | |
3aed041a JR |
3228 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: { |
3229 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0); | |
3230 | if (svm->nested.intercept_dr & bit) | |
410e4d57 | 3231 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
3232 | break; |
3233 | } | |
3234 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
3235 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
ab2f4d73 LP |
3236 | if (svm->nested.intercept_exceptions & excp_bits) { |
3237 | if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR) | |
3238 | vmexit = nested_svm_intercept_db(svm); | |
3239 | else | |
3240 | vmexit = NESTED_EXIT_DONE; | |
3241 | } | |
631bc487 GN |
3242 | /* async page fault always cause vmexit */ |
3243 | else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) && | |
adfe20fb | 3244 | svm->vcpu.arch.exception.nested_apf != 0) |
631bc487 | 3245 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
3246 | break; |
3247 | } | |
228070b1 JR |
3248 | case SVM_EXIT_ERR: { |
3249 | vmexit = NESTED_EXIT_DONE; | |
3250 | break; | |
3251 | } | |
cf74a78b AG |
3252 | default: { |
3253 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 3254 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 3255 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
3256 | } |
3257 | } | |
3258 | ||
b8e88bc8 JR |
3259 | return vmexit; |
3260 | } | |
3261 | ||
3262 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
3263 | { | |
3264 | int vmexit; | |
3265 | ||
3266 | vmexit = nested_svm_intercept(svm); | |
3267 | ||
3268 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 3269 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
3270 | |
3271 | return vmexit; | |
cf74a78b AG |
3272 | } |
3273 | ||
0460a979 JR |
3274 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
3275 | { | |
3276 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
3277 | struct vmcb_control_area *from = &from_vmcb->control; | |
3278 | ||
4ee546b4 | 3279 | dst->intercept_cr = from->intercept_cr; |
3aed041a | 3280 | dst->intercept_dr = from->intercept_dr; |
0460a979 JR |
3281 | dst->intercept_exceptions = from->intercept_exceptions; |
3282 | dst->intercept = from->intercept; | |
3283 | dst->iopm_base_pa = from->iopm_base_pa; | |
3284 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
3285 | dst->tsc_offset = from->tsc_offset; | |
3286 | dst->asid = from->asid; | |
3287 | dst->tlb_ctl = from->tlb_ctl; | |
3288 | dst->int_ctl = from->int_ctl; | |
3289 | dst->int_vector = from->int_vector; | |
3290 | dst->int_state = from->int_state; | |
3291 | dst->exit_code = from->exit_code; | |
3292 | dst->exit_code_hi = from->exit_code_hi; | |
3293 | dst->exit_info_1 = from->exit_info_1; | |
3294 | dst->exit_info_2 = from->exit_info_2; | |
3295 | dst->exit_int_info = from->exit_int_info; | |
3296 | dst->exit_int_info_err = from->exit_int_info_err; | |
3297 | dst->nested_ctl = from->nested_ctl; | |
3298 | dst->event_inj = from->event_inj; | |
3299 | dst->event_inj_err = from->event_inj_err; | |
3300 | dst->nested_cr3 = from->nested_cr3; | |
0dc92119 | 3301 | dst->virt_ext = from->virt_ext; |
e081354d TW |
3302 | dst->pause_filter_count = from->pause_filter_count; |
3303 | dst->pause_filter_thresh = from->pause_filter_thresh; | |
0460a979 JR |
3304 | } |
3305 | ||
34f80cfa | 3306 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 3307 | { |
8c5fbf1a | 3308 | int rc; |
34f80cfa | 3309 | struct vmcb *nested_vmcb; |
e6aa9abd | 3310 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 3311 | struct vmcb *vmcb = svm->vmcb; |
8c5fbf1a | 3312 | struct kvm_host_map map; |
cf74a78b | 3313 | |
17897f36 JR |
3314 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
3315 | vmcb->control.exit_info_1, | |
3316 | vmcb->control.exit_info_2, | |
3317 | vmcb->control.exit_int_info, | |
e097e5ff SH |
3318 | vmcb->control.exit_int_info_err, |
3319 | KVM_ISA_SVM); | |
17897f36 | 3320 | |
8f38302c | 3321 | rc = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->nested.vmcb), &map); |
8c5fbf1a KA |
3322 | if (rc) { |
3323 | if (rc == -EINVAL) | |
3324 | kvm_inject_gp(&svm->vcpu, 0); | |
34f80cfa | 3325 | return 1; |
8c5fbf1a KA |
3326 | } |
3327 | ||
3328 | nested_vmcb = map.hva; | |
34f80cfa | 3329 | |
2030753d JR |
3330 | /* Exit Guest-Mode */ |
3331 | leave_guest_mode(&svm->vcpu); | |
06fc7772 JR |
3332 | svm->nested.vmcb = 0; |
3333 | ||
cf74a78b | 3334 | /* Give the current vmcb to the guest */ |
33740e40 JR |
3335 | disable_gif(svm); |
3336 | ||
3337 | nested_vmcb->save.es = vmcb->save.es; | |
3338 | nested_vmcb->save.cs = vmcb->save.cs; | |
3339 | nested_vmcb->save.ss = vmcb->save.ss; | |
3340 | nested_vmcb->save.ds = vmcb->save.ds; | |
3341 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
3342 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
3f6a9d16 | 3343 | nested_vmcb->save.efer = svm->vcpu.arch.efer; |
cdbbdc12 | 3344 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
9f8fe504 | 3345 | nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu); |
33740e40 | 3346 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 3347 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 3348 | nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu); |
33740e40 JR |
3349 | nested_vmcb->save.rip = vmcb->save.rip; |
3350 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
3351 | nested_vmcb->save.rax = vmcb->save.rax; | |
3352 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
3353 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
3354 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
3355 | ||
3356 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
3357 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
3358 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
3359 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
3360 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
3361 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
3362 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
3363 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
3364 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
6092d3d3 JR |
3365 | |
3366 | if (svm->nrips_enabled) | |
3367 | nested_vmcb->control.next_rip = vmcb->control.next_rip; | |
8d23c466 AG |
3368 | |
3369 | /* | |
3370 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
3371 | * to make sure that we do not lose injected events. So check event_inj | |
3372 | * here and copy it to exit_int_info if it is valid. | |
3373 | * Exit_int_info and event_inj can't be both valid because the case | |
3374 | * below only happens on a VMRUN instruction intercept which has | |
3375 | * no valid exit_int_info set. | |
3376 | */ | |
3377 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
3378 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
3379 | ||
3380 | nc->exit_int_info = vmcb->control.event_inj; | |
3381 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
3382 | } | |
3383 | ||
33740e40 JR |
3384 | nested_vmcb->control.tlb_ctl = 0; |
3385 | nested_vmcb->control.event_inj = 0; | |
3386 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b | 3387 | |
e081354d TW |
3388 | nested_vmcb->control.pause_filter_count = |
3389 | svm->vmcb->control.pause_filter_count; | |
3390 | nested_vmcb->control.pause_filter_thresh = | |
3391 | svm->vmcb->control.pause_filter_thresh; | |
3392 | ||
cf74a78b AG |
3393 | /* We always set V_INTR_MASKING and remember the old value in hflags */ |
3394 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
3395 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
3396 | ||
cf74a78b | 3397 | /* Restore the original control entries */ |
0460a979 | 3398 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 3399 | |
e79f245d | 3400 | svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset; |
219b65dc AG |
3401 | kvm_clear_exception_queue(&svm->vcpu); |
3402 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b | 3403 | |
4b16184c JR |
3404 | svm->nested.nested_cr3 = 0; |
3405 | ||
cf74a78b AG |
3406 | /* Restore selected save entries */ |
3407 | svm->vmcb->save.es = hsave->save.es; | |
3408 | svm->vmcb->save.cs = hsave->save.cs; | |
3409 | svm->vmcb->save.ss = hsave->save.ss; | |
3410 | svm->vmcb->save.ds = hsave->save.ds; | |
3411 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
3412 | svm->vmcb->save.idtr = hsave->save.idtr; | |
f6e78475 | 3413 | kvm_set_rflags(&svm->vcpu, hsave->save.rflags); |
cf74a78b AG |
3414 | svm_set_efer(&svm->vcpu, hsave->save.efer); |
3415 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
3416 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
3417 | if (npt_enabled) { | |
3418 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
3419 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
3420 | } else { | |
2390218b | 3421 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b | 3422 | } |
de3cd117 | 3423 | kvm_rax_write(&svm->vcpu, hsave->save.rax); |
e9c16c78 PB |
3424 | kvm_rsp_write(&svm->vcpu, hsave->save.rsp); |
3425 | kvm_rip_write(&svm->vcpu, hsave->save.rip); | |
cf74a78b AG |
3426 | svm->vmcb->save.dr7 = 0; |
3427 | svm->vmcb->save.cpl = 0; | |
3428 | svm->vmcb->control.exit_int_info = 0; | |
3429 | ||
8d28fec4 RJ |
3430 | mark_all_dirty(svm->vmcb); |
3431 | ||
8c5fbf1a | 3432 | kvm_vcpu_unmap(&svm->vcpu, &map, true); |
cf74a78b | 3433 | |
4b16184c | 3434 | nested_svm_uninit_mmu_context(&svm->vcpu); |
cf74a78b AG |
3435 | kvm_mmu_reset_context(&svm->vcpu); |
3436 | kvm_mmu_load(&svm->vcpu); | |
3437 | ||
619ad846 VK |
3438 | /* |
3439 | * Drop what we picked up for L2 via svm_complete_interrupts() so it | |
3440 | * doesn't end up in L1. | |
3441 | */ | |
3442 | svm->vcpu.arch.nmi_injected = false; | |
3443 | kvm_clear_exception_queue(&svm->vcpu); | |
3444 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3445 | ||
cf74a78b AG |
3446 | return 0; |
3447 | } | |
3d6368ef | 3448 | |
9738b2c9 | 3449 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 3450 | { |
323c3d80 JR |
3451 | /* |
3452 | * This function merges the msr permission bitmaps of kvm and the | |
c5ec2e56 | 3453 | * nested vmcb. It is optimized in that it only merges the parts where |
323c3d80 JR |
3454 | * the kvm msr permission bitmap may contain zero bits |
3455 | */ | |
3d6368ef | 3456 | int i; |
9738b2c9 | 3457 | |
323c3d80 JR |
3458 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
3459 | return true; | |
9738b2c9 | 3460 | |
323c3d80 JR |
3461 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
3462 | u32 value, p; | |
3463 | u64 offset; | |
9738b2c9 | 3464 | |
323c3d80 JR |
3465 | if (msrpm_offsets[i] == 0xffffffff) |
3466 | break; | |
3d6368ef | 3467 | |
0d6b3537 JR |
3468 | p = msrpm_offsets[i]; |
3469 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 | 3470 | |
54bf36aa | 3471 | if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4)) |
323c3d80 JR |
3472 | return false; |
3473 | ||
3474 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
3475 | } | |
3d6368ef | 3476 | |
d0ec49d4 | 3477 | svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm)); |
9738b2c9 JR |
3478 | |
3479 | return true; | |
3d6368ef AG |
3480 | } |
3481 | ||
52c65a30 JR |
3482 | static bool nested_vmcb_checks(struct vmcb *vmcb) |
3483 | { | |
3484 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
3485 | return false; | |
3486 | ||
dbe77584 JR |
3487 | if (vmcb->control.asid == 0) |
3488 | return false; | |
3489 | ||
cea3a19b TL |
3490 | if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) && |
3491 | !npt_enabled) | |
4b16184c JR |
3492 | return false; |
3493 | ||
52c65a30 JR |
3494 | return true; |
3495 | } | |
3496 | ||
c2634065 | 3497 | static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa, |
8c5fbf1a | 3498 | struct vmcb *nested_vmcb, struct kvm_host_map *map) |
3d6368ef | 3499 | { |
f6e78475 | 3500 | if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF) |
3d6368ef AG |
3501 | svm->vcpu.arch.hflags |= HF_HIF_MASK; |
3502 | else | |
3503 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
3504 | ||
cea3a19b | 3505 | if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) { |
4b16184c JR |
3506 | svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; |
3507 | nested_svm_init_mmu_context(&svm->vcpu); | |
3508 | } | |
3509 | ||
3d6368ef AG |
3510 | /* Load the nested guest state */ |
3511 | svm->vmcb->save.es = nested_vmcb->save.es; | |
3512 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
3513 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
3514 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
3515 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
3516 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
f6e78475 | 3517 | kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags); |
3d6368ef AG |
3518 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); |
3519 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
3520 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
3521 | if (npt_enabled) { | |
3522 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
3523 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 3524 | } else |
2390218b | 3525 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
3526 | |
3527 | /* Guest paging mode is active - reset mmu */ | |
3528 | kvm_mmu_reset_context(&svm->vcpu); | |
3529 | ||
defbba56 | 3530 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
de3cd117 | 3531 | kvm_rax_write(&svm->vcpu, nested_vmcb->save.rax); |
e9c16c78 PB |
3532 | kvm_rsp_write(&svm->vcpu, nested_vmcb->save.rsp); |
3533 | kvm_rip_write(&svm->vcpu, nested_vmcb->save.rip); | |
e0231715 | 3534 | |
3d6368ef AG |
3535 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
3536 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
3537 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
3538 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
3539 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
3540 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
3541 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
3542 | ||
f7138538 | 3543 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 3544 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 3545 | |
aad42c64 | 3546 | /* cache intercepts */ |
4ee546b4 | 3547 | svm->nested.intercept_cr = nested_vmcb->control.intercept_cr; |
3aed041a | 3548 | svm->nested.intercept_dr = nested_vmcb->control.intercept_dr; |
aad42c64 JR |
3549 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; |
3550 | svm->nested.intercept = nested_vmcb->control.intercept; | |
3551 | ||
c2ba05cc | 3552 | svm_flush_tlb(&svm->vcpu, true); |
3d6368ef | 3553 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
3554 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
3555 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
3556 | else | |
3557 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
3558 | ||
88ab24ad JR |
3559 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
3560 | /* We only want the cr8 intercept bits of the guest */ | |
4ee546b4 RJ |
3561 | clr_cr_intercept(svm, INTERCEPT_CR8_READ); |
3562 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
88ab24ad JR |
3563 | } |
3564 | ||
0d945bd9 | 3565 | /* We don't want to see VMMCALLs from a nested guest */ |
8a05a1b8 | 3566 | clr_intercept(svm, INTERCEPT_VMMCALL); |
0d945bd9 | 3567 | |
e79f245d KA |
3568 | svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset; |
3569 | svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset; | |
3570 | ||
0dc92119 | 3571 | svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext; |
3d6368ef AG |
3572 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
3573 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
3d6368ef AG |
3574 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
3575 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
3576 | ||
e081354d TW |
3577 | svm->vmcb->control.pause_filter_count = |
3578 | nested_vmcb->control.pause_filter_count; | |
3579 | svm->vmcb->control.pause_filter_thresh = | |
3580 | nested_vmcb->control.pause_filter_thresh; | |
3581 | ||
8c5fbf1a | 3582 | kvm_vcpu_unmap(&svm->vcpu, map, true); |
9738b2c9 | 3583 | |
2030753d JR |
3584 | /* Enter Guest-Mode */ |
3585 | enter_guest_mode(&svm->vcpu); | |
3586 | ||
384c6368 JR |
3587 | /* |
3588 | * Merge guest and host intercepts - must be called with vcpu in | |
3589 | * guest-mode to take affect here | |
3590 | */ | |
3591 | recalc_intercepts(svm); | |
3592 | ||
06fc7772 | 3593 | svm->nested.vmcb = vmcb_gpa; |
9738b2c9 | 3594 | |
2af9194d | 3595 | enable_gif(svm); |
3d6368ef | 3596 | |
8d28fec4 | 3597 | mark_all_dirty(svm->vmcb); |
c2634065 LP |
3598 | } |
3599 | ||
e7134c1b | 3600 | static int nested_svm_vmrun(struct vcpu_svm *svm) |
c2634065 | 3601 | { |
c8e16b78 | 3602 | int ret; |
c2634065 LP |
3603 | struct vmcb *nested_vmcb; |
3604 | struct vmcb *hsave = svm->nested.hsave; | |
3605 | struct vmcb *vmcb = svm->vmcb; | |
8c5fbf1a | 3606 | struct kvm_host_map map; |
c2634065 LP |
3607 | u64 vmcb_gpa; |
3608 | ||
3609 | vmcb_gpa = svm->vmcb->save.rax; | |
3610 | ||
c8e16b78 | 3611 | ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb_gpa), &map); |
a061985b | 3612 | if (ret == -EINVAL) { |
c8e16b78 | 3613 | kvm_inject_gp(&svm->vcpu, 0); |
e7134c1b | 3614 | return 1; |
c8e16b78 VK |
3615 | } else if (ret) { |
3616 | return kvm_skip_emulated_instruction(&svm->vcpu); | |
8c5fbf1a KA |
3617 | } |
3618 | ||
c8e16b78 VK |
3619 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
3620 | ||
8c5fbf1a | 3621 | nested_vmcb = map.hva; |
c2634065 LP |
3622 | |
3623 | if (!nested_vmcb_checks(nested_vmcb)) { | |
3624 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
3625 | nested_vmcb->control.exit_code_hi = 0; | |
3626 | nested_vmcb->control.exit_info_1 = 0; | |
3627 | nested_vmcb->control.exit_info_2 = 0; | |
3628 | ||
8c5fbf1a | 3629 | kvm_vcpu_unmap(&svm->vcpu, &map, true); |
c2634065 | 3630 | |
c8e16b78 | 3631 | return ret; |
c2634065 LP |
3632 | } |
3633 | ||
3634 | trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa, | |
3635 | nested_vmcb->save.rip, | |
3636 | nested_vmcb->control.int_ctl, | |
3637 | nested_vmcb->control.event_inj, | |
3638 | nested_vmcb->control.nested_ctl); | |
3639 | ||
3640 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, | |
3641 | nested_vmcb->control.intercept_cr >> 16, | |
3642 | nested_vmcb->control.intercept_exceptions, | |
3643 | nested_vmcb->control.intercept); | |
3644 | ||
3645 | /* Clear internal status */ | |
3646 | kvm_clear_exception_queue(&svm->vcpu); | |
3647 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3648 | ||
3649 | /* | |
3650 | * Save the old vmcb, so we don't need to pick what we save, but can | |
3651 | * restore everything when a VMEXIT occurs | |
3652 | */ | |
3653 | hsave->save.es = vmcb->save.es; | |
3654 | hsave->save.cs = vmcb->save.cs; | |
3655 | hsave->save.ss = vmcb->save.ss; | |
3656 | hsave->save.ds = vmcb->save.ds; | |
3657 | hsave->save.gdtr = vmcb->save.gdtr; | |
3658 | hsave->save.idtr = vmcb->save.idtr; | |
3659 | hsave->save.efer = svm->vcpu.arch.efer; | |
3660 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); | |
3661 | hsave->save.cr4 = svm->vcpu.arch.cr4; | |
3662 | hsave->save.rflags = kvm_get_rflags(&svm->vcpu); | |
3663 | hsave->save.rip = kvm_rip_read(&svm->vcpu); | |
3664 | hsave->save.rsp = vmcb->save.rsp; | |
3665 | hsave->save.rax = vmcb->save.rax; | |
3666 | if (npt_enabled) | |
3667 | hsave->save.cr3 = vmcb->save.cr3; | |
3668 | else | |
3669 | hsave->save.cr3 = kvm_read_cr3(&svm->vcpu); | |
3670 | ||
3671 | copy_vmcb_control_area(hsave, vmcb); | |
3672 | ||
8c5fbf1a | 3673 | enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, &map); |
8d28fec4 | 3674 | |
e7134c1b VK |
3675 | if (!nested_svm_vmrun_msrpm(svm)) { |
3676 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
3677 | svm->vmcb->control.exit_code_hi = 0; | |
3678 | svm->vmcb->control.exit_info_1 = 0; | |
3679 | svm->vmcb->control.exit_info_2 = 0; | |
3680 | ||
3681 | nested_svm_vmexit(svm); | |
3682 | } | |
3683 | ||
c8e16b78 | 3684 | return ret; |
3d6368ef AG |
3685 | } |
3686 | ||
9966bf68 | 3687 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
3688 | { |
3689 | to_vmcb->save.fs = from_vmcb->save.fs; | |
3690 | to_vmcb->save.gs = from_vmcb->save.gs; | |
3691 | to_vmcb->save.tr = from_vmcb->save.tr; | |
3692 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
3693 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
3694 | to_vmcb->save.star = from_vmcb->save.star; | |
3695 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
3696 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
3697 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
3698 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
3699 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
3700 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
3701 | } |
3702 | ||
851ba692 | 3703 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 3704 | { |
9966bf68 | 3705 | struct vmcb *nested_vmcb; |
8c5fbf1a | 3706 | struct kvm_host_map map; |
b742c1e6 | 3707 | int ret; |
9966bf68 | 3708 | |
5542675b AG |
3709 | if (nested_svm_check_permissions(svm)) |
3710 | return 1; | |
3711 | ||
8c5fbf1a KA |
3712 | ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map); |
3713 | if (ret) { | |
3714 | if (ret == -EINVAL) | |
3715 | kvm_inject_gp(&svm->vcpu, 0); | |
9966bf68 | 3716 | return 1; |
8c5fbf1a KA |
3717 | } |
3718 | ||
3719 | nested_vmcb = map.hva; | |
9966bf68 | 3720 | |
b742c1e6 | 3721 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
e3e9ed3d | 3722 | |
9966bf68 | 3723 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); |
8c5fbf1a | 3724 | kvm_vcpu_unmap(&svm->vcpu, &map, true); |
5542675b | 3725 | |
b742c1e6 | 3726 | return ret; |
5542675b AG |
3727 | } |
3728 | ||
851ba692 | 3729 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 3730 | { |
9966bf68 | 3731 | struct vmcb *nested_vmcb; |
8c5fbf1a | 3732 | struct kvm_host_map map; |
b742c1e6 | 3733 | int ret; |
9966bf68 | 3734 | |
5542675b AG |
3735 | if (nested_svm_check_permissions(svm)) |
3736 | return 1; | |
3737 | ||
8c5fbf1a KA |
3738 | ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map); |
3739 | if (ret) { | |
3740 | if (ret == -EINVAL) | |
3741 | kvm_inject_gp(&svm->vcpu, 0); | |
9966bf68 | 3742 | return 1; |
8c5fbf1a KA |
3743 | } |
3744 | ||
3745 | nested_vmcb = map.hva; | |
9966bf68 | 3746 | |
b742c1e6 | 3747 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
e3e9ed3d | 3748 | |
9966bf68 | 3749 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); |
8c5fbf1a | 3750 | kvm_vcpu_unmap(&svm->vcpu, &map, true); |
5542675b | 3751 | |
b742c1e6 | 3752 | return ret; |
5542675b AG |
3753 | } |
3754 | ||
851ba692 | 3755 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 3756 | { |
3d6368ef AG |
3757 | if (nested_svm_check_permissions(svm)) |
3758 | return 1; | |
3759 | ||
e7134c1b | 3760 | return nested_svm_vmrun(svm); |
3d6368ef AG |
3761 | } |
3762 | ||
851ba692 | 3763 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 | 3764 | { |
b742c1e6 LP |
3765 | int ret; |
3766 | ||
1371d904 AG |
3767 | if (nested_svm_check_permissions(svm)) |
3768 | return 1; | |
3769 | ||
640bd6e5 JN |
3770 | /* |
3771 | * If VGIF is enabled, the STGI intercept is only added to | |
cc3d967f | 3772 | * detect the opening of the SMI/NMI window; remove it now. |
640bd6e5 JN |
3773 | */ |
3774 | if (vgif_enabled(svm)) | |
3775 | clr_intercept(svm, INTERCEPT_STGI); | |
3776 | ||
b742c1e6 | 3777 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
3842d135 | 3778 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
1371d904 | 3779 | |
2af9194d | 3780 | enable_gif(svm); |
1371d904 | 3781 | |
b742c1e6 | 3782 | return ret; |
1371d904 AG |
3783 | } |
3784 | ||
851ba692 | 3785 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 | 3786 | { |
b742c1e6 LP |
3787 | int ret; |
3788 | ||
1371d904 AG |
3789 | if (nested_svm_check_permissions(svm)) |
3790 | return 1; | |
3791 | ||
b742c1e6 | 3792 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
1371d904 | 3793 | |
2af9194d | 3794 | disable_gif(svm); |
1371d904 AG |
3795 | |
3796 | /* After a CLGI no interrupts should come */ | |
340d3bc3 SS |
3797 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) { |
3798 | svm_clear_vintr(svm); | |
3799 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
3800 | mark_dirty(svm->vmcb, VMCB_INTR); | |
3801 | } | |
decdbf6a | 3802 | |
b742c1e6 | 3803 | return ret; |
1371d904 AG |
3804 | } |
3805 | ||
851ba692 | 3806 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
3807 | { |
3808 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 3809 | |
de3cd117 SC |
3810 | trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu), |
3811 | kvm_rax_read(&svm->vcpu)); | |
ec1ff790 | 3812 | |
ff092385 | 3813 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
de3cd117 | 3814 | kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu)); |
ff092385 | 3815 | |
b742c1e6 | 3816 | return kvm_skip_emulated_instruction(&svm->vcpu); |
ff092385 AG |
3817 | } |
3818 | ||
532a46b9 JR |
3819 | static int skinit_interception(struct vcpu_svm *svm) |
3820 | { | |
de3cd117 | 3821 | trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu)); |
532a46b9 JR |
3822 | |
3823 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3824 | return 1; | |
3825 | } | |
3826 | ||
dab429a7 DK |
3827 | static int wbinvd_interception(struct vcpu_svm *svm) |
3828 | { | |
6affcbed | 3829 | return kvm_emulate_wbinvd(&svm->vcpu); |
dab429a7 DK |
3830 | } |
3831 | ||
81dd35d4 JR |
3832 | static int xsetbv_interception(struct vcpu_svm *svm) |
3833 | { | |
3834 | u64 new_bv = kvm_read_edx_eax(&svm->vcpu); | |
de3cd117 | 3835 | u32 index = kvm_rcx_read(&svm->vcpu); |
81dd35d4 JR |
3836 | |
3837 | if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) { | |
b742c1e6 | 3838 | return kvm_skip_emulated_instruction(&svm->vcpu); |
81dd35d4 JR |
3839 | } |
3840 | ||
3841 | return 1; | |
3842 | } | |
3843 | ||
0cb8410b JM |
3844 | static int rdpru_interception(struct vcpu_svm *svm) |
3845 | { | |
3846 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3847 | return 1; | |
3848 | } | |
3849 | ||
851ba692 | 3850 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 3851 | { |
37817f29 | 3852 | u16 tss_selector; |
64a7ec06 GN |
3853 | int reason; |
3854 | int int_type = svm->vmcb->control.exit_int_info & | |
3855 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 3856 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
3857 | uint32_t type = |
3858 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
3859 | uint32_t idt_v = | |
3860 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
3861 | bool has_error_code = false; |
3862 | u32 error_code = 0; | |
37817f29 IE |
3863 | |
3864 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 3865 | |
37817f29 IE |
3866 | if (svm->vmcb->control.exit_info_2 & |
3867 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
3868 | reason = TASK_SWITCH_IRET; |
3869 | else if (svm->vmcb->control.exit_info_2 & | |
3870 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
3871 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 3872 | else if (idt_v) |
64a7ec06 GN |
3873 | reason = TASK_SWITCH_GATE; |
3874 | else | |
3875 | reason = TASK_SWITCH_CALL; | |
3876 | ||
fe8e7f83 GN |
3877 | if (reason == TASK_SWITCH_GATE) { |
3878 | switch (type) { | |
3879 | case SVM_EXITINTINFO_TYPE_NMI: | |
3880 | svm->vcpu.arch.nmi_injected = false; | |
3881 | break; | |
3882 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
3883 | if (svm->vmcb->control.exit_info_2 & |
3884 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
3885 | has_error_code = true; | |
3886 | error_code = | |
3887 | (u32)svm->vmcb->control.exit_info_2; | |
3888 | } | |
fe8e7f83 GN |
3889 | kvm_clear_exception_queue(&svm->vcpu); |
3890 | break; | |
3891 | case SVM_EXITINTINFO_TYPE_INTR: | |
3892 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3893 | break; | |
3894 | default: | |
3895 | break; | |
3896 | } | |
3897 | } | |
64a7ec06 | 3898 | |
8317c298 GN |
3899 | if (reason != TASK_SWITCH_GATE || |
3900 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
3901 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f8ea7c60 | 3902 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) { |
60fc3d02 | 3903 | if (!skip_emulated_instruction(&svm->vcpu)) |
738fece4 | 3904 | return 0; |
f8ea7c60 | 3905 | } |
64a7ec06 | 3906 | |
7f3d35fd KW |
3907 | if (int_type != SVM_EXITINTINFO_TYPE_SOFT) |
3908 | int_vec = -1; | |
3909 | ||
1051778f | 3910 | return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason, |
60fc3d02 | 3911 | has_error_code, error_code); |
6aa8b732 AK |
3912 | } |
3913 | ||
851ba692 | 3914 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 3915 | { |
6a908b62 | 3916 | return kvm_emulate_cpuid(&svm->vcpu); |
6aa8b732 AK |
3917 | } |
3918 | ||
851ba692 | 3919 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
3920 | { |
3921 | ++svm->vcpu.stat.nmi_window_exits; | |
8a05a1b8 | 3922 | clr_intercept(svm, INTERCEPT_IRET); |
44c11430 | 3923 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
bd3d1ec3 | 3924 | svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu); |
f303b4ce | 3925 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
95ba8273 GN |
3926 | return 1; |
3927 | } | |
3928 | ||
851ba692 | 3929 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 3930 | { |
df4f3108 | 3931 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) |
60fc3d02 | 3932 | return kvm_emulate_instruction(&svm->vcpu, 0); |
df4f3108 AP |
3933 | |
3934 | kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1); | |
b742c1e6 | 3935 | return kvm_skip_emulated_instruction(&svm->vcpu); |
a7052897 MT |
3936 | } |
3937 | ||
851ba692 | 3938 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 3939 | { |
60fc3d02 | 3940 | return kvm_emulate_instruction(&svm->vcpu, 0); |
6aa8b732 AK |
3941 | } |
3942 | ||
7607b717 BS |
3943 | static int rsm_interception(struct vcpu_svm *svm) |
3944 | { | |
60fc3d02 | 3945 | return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2); |
7607b717 BS |
3946 | } |
3947 | ||
332b56e4 AK |
3948 | static int rdpmc_interception(struct vcpu_svm *svm) |
3949 | { | |
3950 | int err; | |
3951 | ||
d647eb63 | 3952 | if (!nrips) |
332b56e4 AK |
3953 | return emulate_on_interception(svm); |
3954 | ||
3955 | err = kvm_rdpmc(&svm->vcpu); | |
6affcbed | 3956 | return kvm_complete_insn_gp(&svm->vcpu, err); |
332b56e4 AK |
3957 | } |
3958 | ||
52eb5a6d XL |
3959 | static bool check_selective_cr0_intercepted(struct vcpu_svm *svm, |
3960 | unsigned long val) | |
628afd2a JR |
3961 | { |
3962 | unsigned long cr0 = svm->vcpu.arch.cr0; | |
3963 | bool ret = false; | |
3964 | u64 intercept; | |
3965 | ||
3966 | intercept = svm->nested.intercept; | |
3967 | ||
3968 | if (!is_guest_mode(&svm->vcpu) || | |
3969 | (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))) | |
3970 | return false; | |
3971 | ||
3972 | cr0 &= ~SVM_CR0_SELECTIVE_MASK; | |
3973 | val &= ~SVM_CR0_SELECTIVE_MASK; | |
3974 | ||
3975 | if (cr0 ^ val) { | |
3976 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
3977 | ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE); | |
3978 | } | |
3979 | ||
3980 | return ret; | |
3981 | } | |
3982 | ||
7ff76d58 AP |
3983 | #define CR_VALID (1ULL << 63) |
3984 | ||
3985 | static int cr_interception(struct vcpu_svm *svm) | |
3986 | { | |
3987 | int reg, cr; | |
3988 | unsigned long val; | |
3989 | int err; | |
3990 | ||
3991 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
3992 | return emulate_on_interception(svm); | |
3993 | ||
3994 | if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) | |
3995 | return emulate_on_interception(svm); | |
3996 | ||
3997 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
5e57518d DK |
3998 | if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE) |
3999 | cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0; | |
4000 | else | |
4001 | cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0; | |
7ff76d58 AP |
4002 | |
4003 | err = 0; | |
4004 | if (cr >= 16) { /* mov to cr */ | |
4005 | cr -= 16; | |
4006 | val = kvm_register_read(&svm->vcpu, reg); | |
4007 | switch (cr) { | |
4008 | case 0: | |
628afd2a JR |
4009 | if (!check_selective_cr0_intercepted(svm, val)) |
4010 | err = kvm_set_cr0(&svm->vcpu, val); | |
977b2d03 JR |
4011 | else |
4012 | return 1; | |
4013 | ||
7ff76d58 AP |
4014 | break; |
4015 | case 3: | |
4016 | err = kvm_set_cr3(&svm->vcpu, val); | |
4017 | break; | |
4018 | case 4: | |
4019 | err = kvm_set_cr4(&svm->vcpu, val); | |
4020 | break; | |
4021 | case 8: | |
4022 | err = kvm_set_cr8(&svm->vcpu, val); | |
4023 | break; | |
4024 | default: | |
4025 | WARN(1, "unhandled write to CR%d", cr); | |
4026 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
4027 | return 1; | |
4028 | } | |
4029 | } else { /* mov from cr */ | |
4030 | switch (cr) { | |
4031 | case 0: | |
4032 | val = kvm_read_cr0(&svm->vcpu); | |
4033 | break; | |
4034 | case 2: | |
4035 | val = svm->vcpu.arch.cr2; | |
4036 | break; | |
4037 | case 3: | |
9f8fe504 | 4038 | val = kvm_read_cr3(&svm->vcpu); |
7ff76d58 AP |
4039 | break; |
4040 | case 4: | |
4041 | val = kvm_read_cr4(&svm->vcpu); | |
4042 | break; | |
4043 | case 8: | |
4044 | val = kvm_get_cr8(&svm->vcpu); | |
4045 | break; | |
4046 | default: | |
4047 | WARN(1, "unhandled read from CR%d", cr); | |
4048 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
4049 | return 1; | |
4050 | } | |
4051 | kvm_register_write(&svm->vcpu, reg, val); | |
4052 | } | |
6affcbed | 4053 | return kvm_complete_insn_gp(&svm->vcpu, err); |
7ff76d58 AP |
4054 | } |
4055 | ||
cae3797a AP |
4056 | static int dr_interception(struct vcpu_svm *svm) |
4057 | { | |
4058 | int reg, dr; | |
4059 | unsigned long val; | |
cae3797a | 4060 | |
facb0139 PB |
4061 | if (svm->vcpu.guest_debug == 0) { |
4062 | /* | |
4063 | * No more DR vmexits; force a reload of the debug registers | |
4064 | * and reenter on this instruction. The next vmexit will | |
4065 | * retrieve the full state of the debug registers. | |
4066 | */ | |
4067 | clr_dr_intercepts(svm); | |
4068 | svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
4069 | return 1; | |
4070 | } | |
4071 | ||
cae3797a AP |
4072 | if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS)) |
4073 | return emulate_on_interception(svm); | |
4074 | ||
4075 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
4076 | dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0; | |
4077 | ||
4078 | if (dr >= 16) { /* mov to DRn */ | |
16f8a6f9 NA |
4079 | if (!kvm_require_dr(&svm->vcpu, dr - 16)) |
4080 | return 1; | |
cae3797a AP |
4081 | val = kvm_register_read(&svm->vcpu, reg); |
4082 | kvm_set_dr(&svm->vcpu, dr - 16, val); | |
4083 | } else { | |
16f8a6f9 NA |
4084 | if (!kvm_require_dr(&svm->vcpu, dr)) |
4085 | return 1; | |
4086 | kvm_get_dr(&svm->vcpu, dr, &val); | |
4087 | kvm_register_write(&svm->vcpu, reg, val); | |
cae3797a AP |
4088 | } |
4089 | ||
b742c1e6 | 4090 | return kvm_skip_emulated_instruction(&svm->vcpu); |
cae3797a AP |
4091 | } |
4092 | ||
851ba692 | 4093 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 4094 | { |
851ba692 | 4095 | struct kvm_run *kvm_run = svm->vcpu.run; |
eea1cff9 | 4096 | int r; |
851ba692 | 4097 | |
0a5fff19 GN |
4098 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
4099 | /* instruction emulation calls kvm_set_cr8() */ | |
7ff76d58 | 4100 | r = cr_interception(svm); |
35754c98 | 4101 | if (lapic_in_kernel(&svm->vcpu)) |
7ff76d58 | 4102 | return r; |
0a5fff19 | 4103 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
7ff76d58 | 4104 | return r; |
1d075434 JR |
4105 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
4106 | return 0; | |
4107 | } | |
4108 | ||
801e459a TL |
4109 | static int svm_get_msr_feature(struct kvm_msr_entry *msr) |
4110 | { | |
d1d93fa9 TL |
4111 | msr->data = 0; |
4112 | ||
4113 | switch (msr->index) { | |
4114 | case MSR_F10H_DECFG: | |
4115 | if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) | |
4116 | msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE; | |
4117 | break; | |
4118 | default: | |
4119 | return 1; | |
4120 | } | |
4121 | ||
4122 | return 0; | |
801e459a TL |
4123 | } |
4124 | ||
609e36d3 | 4125 | static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 4126 | { |
a2fa3e9f GH |
4127 | struct vcpu_svm *svm = to_svm(vcpu); |
4128 | ||
609e36d3 | 4129 | switch (msr_info->index) { |
8c06585d | 4130 | case MSR_STAR: |
609e36d3 | 4131 | msr_info->data = svm->vmcb->save.star; |
6aa8b732 | 4132 | break; |
0e859cac | 4133 | #ifdef CONFIG_X86_64 |
6aa8b732 | 4134 | case MSR_LSTAR: |
609e36d3 | 4135 | msr_info->data = svm->vmcb->save.lstar; |
6aa8b732 AK |
4136 | break; |
4137 | case MSR_CSTAR: | |
609e36d3 | 4138 | msr_info->data = svm->vmcb->save.cstar; |
6aa8b732 AK |
4139 | break; |
4140 | case MSR_KERNEL_GS_BASE: | |
609e36d3 | 4141 | msr_info->data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
4142 | break; |
4143 | case MSR_SYSCALL_MASK: | |
609e36d3 | 4144 | msr_info->data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
4145 | break; |
4146 | #endif | |
4147 | case MSR_IA32_SYSENTER_CS: | |
609e36d3 | 4148 | msr_info->data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
4149 | break; |
4150 | case MSR_IA32_SYSENTER_EIP: | |
609e36d3 | 4151 | msr_info->data = svm->sysenter_eip; |
6aa8b732 AK |
4152 | break; |
4153 | case MSR_IA32_SYSENTER_ESP: | |
609e36d3 | 4154 | msr_info->data = svm->sysenter_esp; |
6aa8b732 | 4155 | break; |
46896c73 PB |
4156 | case MSR_TSC_AUX: |
4157 | if (!boot_cpu_has(X86_FEATURE_RDTSCP)) | |
4158 | return 1; | |
4159 | msr_info->data = svm->tsc_aux; | |
4160 | break; | |
e0231715 JR |
4161 | /* |
4162 | * Nobody will change the following 5 values in the VMCB so we can | |
4163 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
4164 | * implemented. | |
4165 | */ | |
a2938c80 | 4166 | case MSR_IA32_DEBUGCTLMSR: |
609e36d3 | 4167 | msr_info->data = svm->vmcb->save.dbgctl; |
a2938c80 JR |
4168 | break; |
4169 | case MSR_IA32_LASTBRANCHFROMIP: | |
609e36d3 | 4170 | msr_info->data = svm->vmcb->save.br_from; |
a2938c80 JR |
4171 | break; |
4172 | case MSR_IA32_LASTBRANCHTOIP: | |
609e36d3 | 4173 | msr_info->data = svm->vmcb->save.br_to; |
a2938c80 JR |
4174 | break; |
4175 | case MSR_IA32_LASTINTFROMIP: | |
609e36d3 | 4176 | msr_info->data = svm->vmcb->save.last_excp_from; |
a2938c80 JR |
4177 | break; |
4178 | case MSR_IA32_LASTINTTOIP: | |
609e36d3 | 4179 | msr_info->data = svm->vmcb->save.last_excp_to; |
a2938c80 | 4180 | break; |
b286d5d8 | 4181 | case MSR_VM_HSAVE_PA: |
609e36d3 | 4182 | msr_info->data = svm->nested.hsave_msr; |
b286d5d8 | 4183 | break; |
eb6f302e | 4184 | case MSR_VM_CR: |
609e36d3 | 4185 | msr_info->data = svm->nested.vm_cr_msr; |
eb6f302e | 4186 | break; |
b2ac58f9 KA |
4187 | case MSR_IA32_SPEC_CTRL: |
4188 | if (!msr_info->host_initiated && | |
6ac2f49e KRW |
4189 | !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) && |
4190 | !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD)) | |
b2ac58f9 KA |
4191 | return 1; |
4192 | ||
4193 | msr_info->data = svm->spec_ctrl; | |
4194 | break; | |
bc226f07 TL |
4195 | case MSR_AMD64_VIRT_SPEC_CTRL: |
4196 | if (!msr_info->host_initiated && | |
4197 | !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD)) | |
4198 | return 1; | |
4199 | ||
4200 | msr_info->data = svm->virt_spec_ctrl; | |
4201 | break; | |
ae8b7875 BP |
4202 | case MSR_F15H_IC_CFG: { |
4203 | ||
4204 | int family, model; | |
4205 | ||
4206 | family = guest_cpuid_family(vcpu); | |
4207 | model = guest_cpuid_model(vcpu); | |
4208 | ||
4209 | if (family < 0 || model < 0) | |
4210 | return kvm_get_msr_common(vcpu, msr_info); | |
4211 | ||
4212 | msr_info->data = 0; | |
4213 | ||
4214 | if (family == 0x15 && | |
4215 | (model >= 0x2 && model < 0x20)) | |
4216 | msr_info->data = 0x1E; | |
4217 | } | |
4218 | break; | |
d1d93fa9 TL |
4219 | case MSR_F10H_DECFG: |
4220 | msr_info->data = svm->msr_decfg; | |
4221 | break; | |
6aa8b732 | 4222 | default: |
609e36d3 | 4223 | return kvm_get_msr_common(vcpu, msr_info); |
6aa8b732 AK |
4224 | } |
4225 | return 0; | |
4226 | } | |
4227 | ||
851ba692 | 4228 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 4229 | { |
1edce0a9 | 4230 | return kvm_emulate_rdmsr(&svm->vcpu); |
6aa8b732 AK |
4231 | } |
4232 | ||
4a810181 JR |
4233 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
4234 | { | |
4235 | struct vcpu_svm *svm = to_svm(vcpu); | |
4236 | int svm_dis, chg_mask; | |
4237 | ||
4238 | if (data & ~SVM_VM_CR_VALID_MASK) | |
4239 | return 1; | |
4240 | ||
4241 | chg_mask = SVM_VM_CR_VALID_MASK; | |
4242 | ||
4243 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
4244 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
4245 | ||
4246 | svm->nested.vm_cr_msr &= ~chg_mask; | |
4247 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
4248 | ||
4249 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
4250 | ||
4251 | /* check for svm_disable while efer.svme is set */ | |
4252 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
4253 | return 1; | |
4254 | ||
4255 | return 0; | |
4256 | } | |
4257 | ||
8fe8ab46 | 4258 | static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
6aa8b732 | 4259 | { |
a2fa3e9f GH |
4260 | struct vcpu_svm *svm = to_svm(vcpu); |
4261 | ||
8fe8ab46 WA |
4262 | u32 ecx = msr->index; |
4263 | u64 data = msr->data; | |
6aa8b732 | 4264 | switch (ecx) { |
15038e14 PB |
4265 | case MSR_IA32_CR_PAT: |
4266 | if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data)) | |
4267 | return 1; | |
4268 | vcpu->arch.pat = data; | |
4269 | svm->vmcb->save.g_pat = data; | |
4270 | mark_dirty(svm->vmcb, VMCB_NPT); | |
4271 | break; | |
b2ac58f9 KA |
4272 | case MSR_IA32_SPEC_CTRL: |
4273 | if (!msr->host_initiated && | |
6ac2f49e KRW |
4274 | !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) && |
4275 | !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD)) | |
b2ac58f9 KA |
4276 | return 1; |
4277 | ||
4278 | /* The STIBP bit doesn't fault even if it's not advertised */ | |
6ac2f49e | 4279 | if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD)) |
b2ac58f9 KA |
4280 | return 1; |
4281 | ||
4282 | svm->spec_ctrl = data; | |
4283 | ||
4284 | if (!data) | |
4285 | break; | |
4286 | ||
4287 | /* | |
4288 | * For non-nested: | |
4289 | * When it's written (to non-zero) for the first time, pass | |
4290 | * it through. | |
4291 | * | |
4292 | * For nested: | |
4293 | * The handling of the MSR bitmap for L2 guests is done in | |
4294 | * nested_svm_vmrun_msrpm. | |
4295 | * We update the L1 MSR bit as well since it will end up | |
4296 | * touching the MSR anyway now. | |
4297 | */ | |
4298 | set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1); | |
4299 | break; | |
15d45071 AR |
4300 | case MSR_IA32_PRED_CMD: |
4301 | if (!msr->host_initiated && | |
e7c587da | 4302 | !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB)) |
15d45071 AR |
4303 | return 1; |
4304 | ||
4305 | if (data & ~PRED_CMD_IBPB) | |
4306 | return 1; | |
4307 | ||
4308 | if (!data) | |
4309 | break; | |
4310 | ||
4311 | wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); | |
4312 | if (is_guest_mode(vcpu)) | |
4313 | break; | |
4314 | set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1); | |
4315 | break; | |
bc226f07 TL |
4316 | case MSR_AMD64_VIRT_SPEC_CTRL: |
4317 | if (!msr->host_initiated && | |
4318 | !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD)) | |
4319 | return 1; | |
4320 | ||
4321 | if (data & ~SPEC_CTRL_SSBD) | |
4322 | return 1; | |
4323 | ||
4324 | svm->virt_spec_ctrl = data; | |
4325 | break; | |
8c06585d | 4326 | case MSR_STAR: |
a2fa3e9f | 4327 | svm->vmcb->save.star = data; |
6aa8b732 | 4328 | break; |
49b14f24 | 4329 | #ifdef CONFIG_X86_64 |
6aa8b732 | 4330 | case MSR_LSTAR: |
a2fa3e9f | 4331 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
4332 | break; |
4333 | case MSR_CSTAR: | |
a2fa3e9f | 4334 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
4335 | break; |
4336 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 4337 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
4338 | break; |
4339 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 4340 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
4341 | break; |
4342 | #endif | |
4343 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 4344 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
4345 | break; |
4346 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 4347 | svm->sysenter_eip = data; |
a2fa3e9f | 4348 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
4349 | break; |
4350 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 4351 | svm->sysenter_esp = data; |
a2fa3e9f | 4352 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 4353 | break; |
46896c73 PB |
4354 | case MSR_TSC_AUX: |
4355 | if (!boot_cpu_has(X86_FEATURE_RDTSCP)) | |
4356 | return 1; | |
4357 | ||
4358 | /* | |
4359 | * This is rare, so we update the MSR here instead of using | |
4360 | * direct_access_msrs. Doing that would require a rdmsr in | |
4361 | * svm_vcpu_put. | |
4362 | */ | |
4363 | svm->tsc_aux = data; | |
4364 | wrmsrl(MSR_TSC_AUX, svm->tsc_aux); | |
4365 | break; | |
a2938c80 | 4366 | case MSR_IA32_DEBUGCTLMSR: |
2a6b20b8 | 4367 | if (!boot_cpu_has(X86_FEATURE_LBRV)) { |
a737f256 CD |
4368 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", |
4369 | __func__, data); | |
24e09cbf JR |
4370 | break; |
4371 | } | |
4372 | if (data & DEBUGCTL_RESERVED_BITS) | |
4373 | return 1; | |
4374 | ||
4375 | svm->vmcb->save.dbgctl = data; | |
b53ba3f9 | 4376 | mark_dirty(svm->vmcb, VMCB_LBR); |
24e09cbf JR |
4377 | if (data & (1ULL<<0)) |
4378 | svm_enable_lbrv(svm); | |
4379 | else | |
4380 | svm_disable_lbrv(svm); | |
a2938c80 | 4381 | break; |
b286d5d8 | 4382 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 4383 | svm->nested.hsave_msr = data; |
62b9abaa | 4384 | break; |
3c5d0a44 | 4385 | case MSR_VM_CR: |
4a810181 | 4386 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 4387 | case MSR_VM_IGNNE: |
a737f256 | 4388 | vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
3c5d0a44 | 4389 | break; |
d1d93fa9 TL |
4390 | case MSR_F10H_DECFG: { |
4391 | struct kvm_msr_entry msr_entry; | |
4392 | ||
4393 | msr_entry.index = msr->index; | |
4394 | if (svm_get_msr_feature(&msr_entry)) | |
4395 | return 1; | |
4396 | ||
4397 | /* Check the supported bits */ | |
4398 | if (data & ~msr_entry.data) | |
4399 | return 1; | |
4400 | ||
4401 | /* Don't allow the guest to change a bit, #GP */ | |
4402 | if (!msr->host_initiated && (data ^ msr_entry.data)) | |
4403 | return 1; | |
4404 | ||
4405 | svm->msr_decfg = data; | |
4406 | break; | |
4407 | } | |
44a95dae SS |
4408 | case MSR_IA32_APICBASE: |
4409 | if (kvm_vcpu_apicv_active(vcpu)) | |
4410 | avic_update_vapic_bar(to_svm(vcpu), data); | |
b2869f28 | 4411 | /* Fall through */ |
6aa8b732 | 4412 | default: |
8fe8ab46 | 4413 | return kvm_set_msr_common(vcpu, msr); |
6aa8b732 AK |
4414 | } |
4415 | return 0; | |
4416 | } | |
4417 | ||
851ba692 | 4418 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 4419 | { |
1edce0a9 | 4420 | return kvm_emulate_wrmsr(&svm->vcpu); |
6aa8b732 AK |
4421 | } |
4422 | ||
851ba692 | 4423 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 4424 | { |
e756fc62 | 4425 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 4426 | return wrmsr_interception(svm); |
6aa8b732 | 4427 | else |
851ba692 | 4428 | return rdmsr_interception(svm); |
6aa8b732 AK |
4429 | } |
4430 | ||
851ba692 | 4431 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 4432 | { |
3842d135 | 4433 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
f0b85051 | 4434 | svm_clear_vintr(svm); |
85f455f7 | 4435 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
decdbf6a | 4436 | mark_dirty(svm->vmcb, VMCB_INTR); |
675acb75 | 4437 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
4438 | return 1; |
4439 | } | |
4440 | ||
565d0998 ML |
4441 | static int pause_interception(struct vcpu_svm *svm) |
4442 | { | |
de63ad4c LM |
4443 | struct kvm_vcpu *vcpu = &svm->vcpu; |
4444 | bool in_kernel = (svm_get_cpl(vcpu) == 0); | |
4445 | ||
8566ac8b BM |
4446 | if (pause_filter_thresh) |
4447 | grow_ple_window(vcpu); | |
4448 | ||
de63ad4c | 4449 | kvm_vcpu_on_spin(vcpu, in_kernel); |
565d0998 ML |
4450 | return 1; |
4451 | } | |
4452 | ||
87c00572 GS |
4453 | static int nop_interception(struct vcpu_svm *svm) |
4454 | { | |
b742c1e6 | 4455 | return kvm_skip_emulated_instruction(&(svm->vcpu)); |
87c00572 GS |
4456 | } |
4457 | ||
4458 | static int monitor_interception(struct vcpu_svm *svm) | |
4459 | { | |
4460 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
4461 | return nop_interception(svm); | |
4462 | } | |
4463 | ||
4464 | static int mwait_interception(struct vcpu_svm *svm) | |
4465 | { | |
4466 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
4467 | return nop_interception(svm); | |
4468 | } | |
4469 | ||
18f40c53 SS |
4470 | enum avic_ipi_failure_cause { |
4471 | AVIC_IPI_FAILURE_INVALID_INT_TYPE, | |
4472 | AVIC_IPI_FAILURE_TARGET_NOT_RUNNING, | |
4473 | AVIC_IPI_FAILURE_INVALID_TARGET, | |
4474 | AVIC_IPI_FAILURE_INVALID_BACKING_PAGE, | |
4475 | }; | |
4476 | ||
4477 | static int avic_incomplete_ipi_interception(struct vcpu_svm *svm) | |
4478 | { | |
4479 | u32 icrh = svm->vmcb->control.exit_info_1 >> 32; | |
4480 | u32 icrl = svm->vmcb->control.exit_info_1; | |
4481 | u32 id = svm->vmcb->control.exit_info_2 >> 32; | |
5446a979 | 4482 | u32 index = svm->vmcb->control.exit_info_2 & 0xFF; |
18f40c53 SS |
4483 | struct kvm_lapic *apic = svm->vcpu.arch.apic; |
4484 | ||
4485 | trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index); | |
4486 | ||
4487 | switch (id) { | |
4488 | case AVIC_IPI_FAILURE_INVALID_INT_TYPE: | |
4489 | /* | |
4490 | * AVIC hardware handles the generation of | |
4491 | * IPIs when the specified Message Type is Fixed | |
4492 | * (also known as fixed delivery mode) and | |
4493 | * the Trigger Mode is edge-triggered. The hardware | |
4494 | * also supports self and broadcast delivery modes | |
4495 | * specified via the Destination Shorthand(DSH) | |
4496 | * field of the ICRL. Logical and physical APIC ID | |
4497 | * formats are supported. All other IPI types cause | |
4498 | * a #VMEXIT, which needs to emulated. | |
4499 | */ | |
4500 | kvm_lapic_reg_write(apic, APIC_ICR2, icrh); | |
4501 | kvm_lapic_reg_write(apic, APIC_ICR, icrl); | |
4502 | break; | |
4503 | case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: { | |
4a58038b SS |
4504 | int i; |
4505 | struct kvm_vcpu *vcpu; | |
4506 | struct kvm *kvm = svm->vcpu.kvm; | |
18f40c53 SS |
4507 | struct kvm_lapic *apic = svm->vcpu.arch.apic; |
4508 | ||
4509 | /* | |
4a58038b SS |
4510 | * At this point, we expect that the AVIC HW has already |
4511 | * set the appropriate IRR bits on the valid target | |
4512 | * vcpus. So, we just need to kick the appropriate vcpu. | |
18f40c53 | 4513 | */ |
4a58038b SS |
4514 | kvm_for_each_vcpu(i, vcpu, kvm) { |
4515 | bool m = kvm_apic_match_dest(vcpu, apic, | |
4516 | icrl & KVM_APIC_SHORT_MASK, | |
4517 | GET_APIC_DEST_FIELD(icrh), | |
4518 | icrl & KVM_APIC_DEST_MASK); | |
4519 | ||
4520 | if (m && !avic_vcpu_is_running(vcpu)) | |
4521 | kvm_vcpu_wake_up(vcpu); | |
4522 | } | |
18f40c53 SS |
4523 | break; |
4524 | } | |
4525 | case AVIC_IPI_FAILURE_INVALID_TARGET: | |
37ef0c44 SS |
4526 | WARN_ONCE(1, "Invalid IPI target: index=%u, vcpu=%d, icr=%#0x:%#0x\n", |
4527 | index, svm->vcpu.vcpu_id, icrh, icrl); | |
18f40c53 SS |
4528 | break; |
4529 | case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE: | |
4530 | WARN_ONCE(1, "Invalid backing page\n"); | |
4531 | break; | |
4532 | default: | |
4533 | pr_err("Unknown IPI interception\n"); | |
4534 | } | |
4535 | ||
4536 | return 1; | |
4537 | } | |
4538 | ||
4539 | static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat) | |
4540 | { | |
81811c16 | 4541 | struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm); |
18f40c53 SS |
4542 | int index; |
4543 | u32 *logical_apic_id_table; | |
4544 | int dlid = GET_APIC_LOGICAL_ID(ldr); | |
4545 | ||
4546 | if (!dlid) | |
4547 | return NULL; | |
4548 | ||
4549 | if (flat) { /* flat */ | |
4550 | index = ffs(dlid) - 1; | |
4551 | if (index > 7) | |
4552 | return NULL; | |
4553 | } else { /* cluster */ | |
4554 | int cluster = (dlid & 0xf0) >> 4; | |
4555 | int apic = ffs(dlid & 0x0f) - 1; | |
4556 | ||
4557 | if ((apic < 0) || (apic > 7) || | |
4558 | (cluster >= 0xf)) | |
4559 | return NULL; | |
4560 | index = (cluster << 2) + apic; | |
4561 | } | |
4562 | ||
81811c16 | 4563 | logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page); |
18f40c53 SS |
4564 | |
4565 | return &logical_apic_id_table[index]; | |
4566 | } | |
4567 | ||
98d90582 | 4568 | static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr) |
18f40c53 SS |
4569 | { |
4570 | bool flat; | |
4571 | u32 *entry, new_entry; | |
4572 | ||
4573 | flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT; | |
4574 | entry = avic_get_logical_id_entry(vcpu, ldr, flat); | |
4575 | if (!entry) | |
4576 | return -EINVAL; | |
4577 | ||
4578 | new_entry = READ_ONCE(*entry); | |
4579 | new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK; | |
4580 | new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK); | |
98d90582 | 4581 | new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK; |
18f40c53 SS |
4582 | WRITE_ONCE(*entry, new_entry); |
4583 | ||
4584 | return 0; | |
4585 | } | |
4586 | ||
98d90582 SS |
4587 | static void avic_invalidate_logical_id_entry(struct kvm_vcpu *vcpu) |
4588 | { | |
4589 | struct vcpu_svm *svm = to_svm(vcpu); | |
4590 | bool flat = svm->dfr_reg == APIC_DFR_FLAT; | |
4591 | u32 *entry = avic_get_logical_id_entry(vcpu, svm->ldr_reg, flat); | |
4592 | ||
4593 | if (entry) | |
e44e3eac | 4594 | clear_bit(AVIC_LOGICAL_ID_ENTRY_VALID_BIT, (unsigned long *)entry); |
98d90582 SS |
4595 | } |
4596 | ||
18f40c53 SS |
4597 | static int avic_handle_ldr_update(struct kvm_vcpu *vcpu) |
4598 | { | |
98d90582 | 4599 | int ret = 0; |
18f40c53 SS |
4600 | struct vcpu_svm *svm = to_svm(vcpu); |
4601 | u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR); | |
4602 | ||
98d90582 SS |
4603 | if (ldr == svm->ldr_reg) |
4604 | return 0; | |
18f40c53 | 4605 | |
98d90582 SS |
4606 | avic_invalidate_logical_id_entry(vcpu); |
4607 | ||
4608 | if (ldr) | |
4609 | ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr); | |
4610 | ||
4611 | if (!ret) | |
18f40c53 | 4612 | svm->ldr_reg = ldr; |
98d90582 | 4613 | |
18f40c53 SS |
4614 | return ret; |
4615 | } | |
4616 | ||
4617 | static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu) | |
4618 | { | |
4619 | u64 *old, *new; | |
4620 | struct vcpu_svm *svm = to_svm(vcpu); | |
4621 | u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID); | |
4622 | u32 id = (apic_id_reg >> 24) & 0xff; | |
4623 | ||
4624 | if (vcpu->vcpu_id == id) | |
4625 | return 0; | |
4626 | ||
4627 | old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id); | |
4628 | new = avic_get_physical_id_entry(vcpu, id); | |
4629 | if (!new || !old) | |
4630 | return 1; | |
4631 | ||
4632 | /* We need to move physical_id_entry to new offset */ | |
4633 | *new = *old; | |
4634 | *old = 0ULL; | |
4635 | to_svm(vcpu)->avic_physical_id_cache = new; | |
4636 | ||
4637 | /* | |
4638 | * Also update the guest physical APIC ID in the logical | |
4639 | * APIC ID table entry if already setup the LDR. | |
4640 | */ | |
4641 | if (svm->ldr_reg) | |
4642 | avic_handle_ldr_update(vcpu); | |
4643 | ||
4644 | return 0; | |
4645 | } | |
4646 | ||
98d90582 | 4647 | static void avic_handle_dfr_update(struct kvm_vcpu *vcpu) |
18f40c53 SS |
4648 | { |
4649 | struct vcpu_svm *svm = to_svm(vcpu); | |
18f40c53 | 4650 | u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR); |
18f40c53 | 4651 | |
98d90582 SS |
4652 | if (svm->dfr_reg == dfr) |
4653 | return; | |
18f40c53 | 4654 | |
98d90582 SS |
4655 | avic_invalidate_logical_id_entry(vcpu); |
4656 | svm->dfr_reg = dfr; | |
18f40c53 SS |
4657 | } |
4658 | ||
4659 | static int avic_unaccel_trap_write(struct vcpu_svm *svm) | |
4660 | { | |
4661 | struct kvm_lapic *apic = svm->vcpu.arch.apic; | |
4662 | u32 offset = svm->vmcb->control.exit_info_1 & | |
4663 | AVIC_UNACCEL_ACCESS_OFFSET_MASK; | |
4664 | ||
4665 | switch (offset) { | |
4666 | case APIC_ID: | |
4667 | if (avic_handle_apic_id_update(&svm->vcpu)) | |
4668 | return 0; | |
4669 | break; | |
4670 | case APIC_LDR: | |
4671 | if (avic_handle_ldr_update(&svm->vcpu)) | |
4672 | return 0; | |
4673 | break; | |
4674 | case APIC_DFR: | |
4675 | avic_handle_dfr_update(&svm->vcpu); | |
4676 | break; | |
4677 | default: | |
4678 | break; | |
4679 | } | |
4680 | ||
4681 | kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset)); | |
4682 | ||
4683 | return 1; | |
4684 | } | |
4685 | ||
4686 | static bool is_avic_unaccelerated_access_trap(u32 offset) | |
4687 | { | |
4688 | bool ret = false; | |
4689 | ||
4690 | switch (offset) { | |
4691 | case APIC_ID: | |
4692 | case APIC_EOI: | |
4693 | case APIC_RRR: | |
4694 | case APIC_LDR: | |
4695 | case APIC_DFR: | |
4696 | case APIC_SPIV: | |
4697 | case APIC_ESR: | |
4698 | case APIC_ICR: | |
4699 | case APIC_LVTT: | |
4700 | case APIC_LVTTHMR: | |
4701 | case APIC_LVTPC: | |
4702 | case APIC_LVT0: | |
4703 | case APIC_LVT1: | |
4704 | case APIC_LVTERR: | |
4705 | case APIC_TMICT: | |
4706 | case APIC_TDCR: | |
4707 | ret = true; | |
4708 | break; | |
4709 | default: | |
4710 | break; | |
4711 | } | |
4712 | return ret; | |
4713 | } | |
4714 | ||
4715 | static int avic_unaccelerated_access_interception(struct vcpu_svm *svm) | |
4716 | { | |
4717 | int ret = 0; | |
4718 | u32 offset = svm->vmcb->control.exit_info_1 & | |
4719 | AVIC_UNACCEL_ACCESS_OFFSET_MASK; | |
4720 | u32 vector = svm->vmcb->control.exit_info_2 & | |
4721 | AVIC_UNACCEL_ACCESS_VECTOR_MASK; | |
4722 | bool write = (svm->vmcb->control.exit_info_1 >> 32) & | |
4723 | AVIC_UNACCEL_ACCESS_WRITE_MASK; | |
4724 | bool trap = is_avic_unaccelerated_access_trap(offset); | |
4725 | ||
4726 | trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset, | |
4727 | trap, write, vector); | |
4728 | if (trap) { | |
4729 | /* Handling Trap */ | |
4730 | WARN_ONCE(!write, "svm: Handling trap read.\n"); | |
4731 | ret = avic_unaccel_trap_write(svm); | |
4732 | } else { | |
4733 | /* Handling Fault */ | |
60fc3d02 | 4734 | ret = kvm_emulate_instruction(&svm->vcpu, 0); |
18f40c53 SS |
4735 | } |
4736 | ||
4737 | return ret; | |
4738 | } | |
4739 | ||
09941fbb | 4740 | static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = { |
7ff76d58 AP |
4741 | [SVM_EXIT_READ_CR0] = cr_interception, |
4742 | [SVM_EXIT_READ_CR3] = cr_interception, | |
4743 | [SVM_EXIT_READ_CR4] = cr_interception, | |
4744 | [SVM_EXIT_READ_CR8] = cr_interception, | |
5e57518d | 4745 | [SVM_EXIT_CR0_SEL_WRITE] = cr_interception, |
628afd2a | 4746 | [SVM_EXIT_WRITE_CR0] = cr_interception, |
7ff76d58 AP |
4747 | [SVM_EXIT_WRITE_CR3] = cr_interception, |
4748 | [SVM_EXIT_WRITE_CR4] = cr_interception, | |
e0231715 | 4749 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
cae3797a AP |
4750 | [SVM_EXIT_READ_DR0] = dr_interception, |
4751 | [SVM_EXIT_READ_DR1] = dr_interception, | |
4752 | [SVM_EXIT_READ_DR2] = dr_interception, | |
4753 | [SVM_EXIT_READ_DR3] = dr_interception, | |
4754 | [SVM_EXIT_READ_DR4] = dr_interception, | |
4755 | [SVM_EXIT_READ_DR5] = dr_interception, | |
4756 | [SVM_EXIT_READ_DR6] = dr_interception, | |
4757 | [SVM_EXIT_READ_DR7] = dr_interception, | |
4758 | [SVM_EXIT_WRITE_DR0] = dr_interception, | |
4759 | [SVM_EXIT_WRITE_DR1] = dr_interception, | |
4760 | [SVM_EXIT_WRITE_DR2] = dr_interception, | |
4761 | [SVM_EXIT_WRITE_DR3] = dr_interception, | |
4762 | [SVM_EXIT_WRITE_DR4] = dr_interception, | |
4763 | [SVM_EXIT_WRITE_DR5] = dr_interception, | |
4764 | [SVM_EXIT_WRITE_DR6] = dr_interception, | |
4765 | [SVM_EXIT_WRITE_DR7] = dr_interception, | |
d0bfb940 JK |
4766 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
4767 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 4768 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 | 4769 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
e0231715 | 4770 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, |
54a20552 | 4771 | [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception, |
9718420e | 4772 | [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception, |
e0231715 | 4773 | [SVM_EXIT_INTR] = intr_interception, |
c47f098d | 4774 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
4775 | [SVM_EXIT_SMI] = nop_on_interception, |
4776 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 4777 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
332b56e4 | 4778 | [SVM_EXIT_RDPMC] = rdpmc_interception, |
6aa8b732 | 4779 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 4780 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 4781 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 4782 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 4783 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 4784 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 4785 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 4786 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
4787 | [SVM_EXIT_MSR] = msr_interception, |
4788 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 4789 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 4790 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 4791 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
4792 | [SVM_EXIT_VMLOAD] = vmload_interception, |
4793 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
4794 | [SVM_EXIT_STGI] = stgi_interception, |
4795 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 4796 | [SVM_EXIT_SKINIT] = skinit_interception, |
dab429a7 | 4797 | [SVM_EXIT_WBINVD] = wbinvd_interception, |
87c00572 GS |
4798 | [SVM_EXIT_MONITOR] = monitor_interception, |
4799 | [SVM_EXIT_MWAIT] = mwait_interception, | |
81dd35d4 | 4800 | [SVM_EXIT_XSETBV] = xsetbv_interception, |
0cb8410b | 4801 | [SVM_EXIT_RDPRU] = rdpru_interception, |
d0006530 | 4802 | [SVM_EXIT_NPF] = npf_interception, |
7607b717 | 4803 | [SVM_EXIT_RSM] = rsm_interception, |
18f40c53 SS |
4804 | [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception, |
4805 | [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception, | |
6aa8b732 AK |
4806 | }; |
4807 | ||
ae8cc059 | 4808 | static void dump_vmcb(struct kvm_vcpu *vcpu) |
3f10c846 JR |
4809 | { |
4810 | struct vcpu_svm *svm = to_svm(vcpu); | |
4811 | struct vmcb_control_area *control = &svm->vmcb->control; | |
4812 | struct vmcb_save_area *save = &svm->vmcb->save; | |
4813 | ||
6f2f8453 PB |
4814 | if (!dump_invalid_vmcb) { |
4815 | pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n"); | |
4816 | return; | |
4817 | } | |
4818 | ||
3f10c846 | 4819 | pr_err("VMCB Control Area:\n"); |
ae8cc059 JP |
4820 | pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff); |
4821 | pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16); | |
4822 | pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff); | |
4823 | pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16); | |
4824 | pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions); | |
4825 | pr_err("%-20s%016llx\n", "intercepts:", control->intercept); | |
4826 | pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count); | |
1d8fb44a BM |
4827 | pr_err("%-20s%d\n", "pause filter threshold:", |
4828 | control->pause_filter_thresh); | |
ae8cc059 JP |
4829 | pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa); |
4830 | pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa); | |
4831 | pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset); | |
4832 | pr_err("%-20s%d\n", "asid:", control->asid); | |
4833 | pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl); | |
4834 | pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl); | |
4835 | pr_err("%-20s%08x\n", "int_vector:", control->int_vector); | |
4836 | pr_err("%-20s%08x\n", "int_state:", control->int_state); | |
4837 | pr_err("%-20s%08x\n", "exit_code:", control->exit_code); | |
4838 | pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1); | |
4839 | pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2); | |
4840 | pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info); | |
4841 | pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err); | |
4842 | pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl); | |
4843 | pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3); | |
44a95dae | 4844 | pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar); |
ae8cc059 JP |
4845 | pr_err("%-20s%08x\n", "event_inj:", control->event_inj); |
4846 | pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err); | |
0dc92119 | 4847 | pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext); |
ae8cc059 | 4848 | pr_err("%-20s%016llx\n", "next_rip:", control->next_rip); |
44a95dae SS |
4849 | pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page); |
4850 | pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id); | |
4851 | pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id); | |
3f10c846 | 4852 | pr_err("VMCB State Save Area:\n"); |
ae8cc059 JP |
4853 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", |
4854 | "es:", | |
4855 | save->es.selector, save->es.attrib, | |
4856 | save->es.limit, save->es.base); | |
4857 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4858 | "cs:", | |
4859 | save->cs.selector, save->cs.attrib, | |
4860 | save->cs.limit, save->cs.base); | |
4861 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4862 | "ss:", | |
4863 | save->ss.selector, save->ss.attrib, | |
4864 | save->ss.limit, save->ss.base); | |
4865 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4866 | "ds:", | |
4867 | save->ds.selector, save->ds.attrib, | |
4868 | save->ds.limit, save->ds.base); | |
4869 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4870 | "fs:", | |
4871 | save->fs.selector, save->fs.attrib, | |
4872 | save->fs.limit, save->fs.base); | |
4873 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4874 | "gs:", | |
4875 | save->gs.selector, save->gs.attrib, | |
4876 | save->gs.limit, save->gs.base); | |
4877 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4878 | "gdtr:", | |
4879 | save->gdtr.selector, save->gdtr.attrib, | |
4880 | save->gdtr.limit, save->gdtr.base); | |
4881 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4882 | "ldtr:", | |
4883 | save->ldtr.selector, save->ldtr.attrib, | |
4884 | save->ldtr.limit, save->ldtr.base); | |
4885 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4886 | "idtr:", | |
4887 | save->idtr.selector, save->idtr.attrib, | |
4888 | save->idtr.limit, save->idtr.base); | |
4889 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4890 | "tr:", | |
4891 | save->tr.selector, save->tr.attrib, | |
4892 | save->tr.limit, save->tr.base); | |
3f10c846 JR |
4893 | pr_err("cpl: %d efer: %016llx\n", |
4894 | save->cpl, save->efer); | |
ae8cc059 JP |
4895 | pr_err("%-15s %016llx %-13s %016llx\n", |
4896 | "cr0:", save->cr0, "cr2:", save->cr2); | |
4897 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4898 | "cr3:", save->cr3, "cr4:", save->cr4); | |
4899 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4900 | "dr6:", save->dr6, "dr7:", save->dr7); | |
4901 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4902 | "rip:", save->rip, "rflags:", save->rflags); | |
4903 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4904 | "rsp:", save->rsp, "rax:", save->rax); | |
4905 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4906 | "star:", save->star, "lstar:", save->lstar); | |
4907 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4908 | "cstar:", save->cstar, "sfmask:", save->sfmask); | |
4909 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4910 | "kernel_gs_base:", save->kernel_gs_base, | |
4911 | "sysenter_cs:", save->sysenter_cs); | |
4912 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4913 | "sysenter_esp:", save->sysenter_esp, | |
4914 | "sysenter_eip:", save->sysenter_eip); | |
4915 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4916 | "gpat:", save->g_pat, "dbgctl:", save->dbgctl); | |
4917 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4918 | "br_from:", save->br_from, "br_to:", save->br_to); | |
4919 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4920 | "excp_from:", save->last_excp_from, | |
4921 | "excp_to:", save->last_excp_to); | |
3f10c846 JR |
4922 | } |
4923 | ||
586f9607 AK |
4924 | static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
4925 | { | |
4926 | struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; | |
4927 | ||
4928 | *info1 = control->exit_info_1; | |
4929 | *info2 = control->exit_info_2; | |
4930 | } | |
4931 | ||
851ba692 | 4932 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 4933 | { |
04d2cc77 | 4934 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 4935 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 4936 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 4937 | |
8b89fe1f PB |
4938 | trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM); |
4939 | ||
4ee546b4 | 4940 | if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE)) |
2be4fc7a JR |
4941 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
4942 | if (npt_enabled) | |
4943 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 4944 | |
cd3ff653 JR |
4945 | if (unlikely(svm->nested.exit_required)) { |
4946 | nested_svm_vmexit(svm); | |
4947 | svm->nested.exit_required = false; | |
4948 | ||
4949 | return 1; | |
4950 | } | |
4951 | ||
2030753d | 4952 | if (is_guest_mode(vcpu)) { |
410e4d57 JR |
4953 | int vmexit; |
4954 | ||
d8cabddf JR |
4955 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
4956 | svm->vmcb->control.exit_info_1, | |
4957 | svm->vmcb->control.exit_info_2, | |
4958 | svm->vmcb->control.exit_int_info, | |
e097e5ff SH |
4959 | svm->vmcb->control.exit_int_info_err, |
4960 | KVM_ISA_SVM); | |
d8cabddf | 4961 | |
410e4d57 JR |
4962 | vmexit = nested_svm_exit_special(svm); |
4963 | ||
4964 | if (vmexit == NESTED_EXIT_CONTINUE) | |
4965 | vmexit = nested_svm_exit_handled(svm); | |
4966 | ||
4967 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 4968 | return 1; |
cf74a78b AG |
4969 | } |
4970 | ||
a5c3832d JR |
4971 | svm_complete_interrupts(svm); |
4972 | ||
04d2cc77 AK |
4973 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
4974 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
4975 | kvm_run->fail_entry.hardware_entry_failure_reason | |
4976 | = svm->vmcb->control.exit_code; | |
3f10c846 | 4977 | dump_vmcb(vcpu); |
04d2cc77 AK |
4978 | return 0; |
4979 | } | |
4980 | ||
a2fa3e9f | 4981 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 4982 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
55c5e464 JR |
4983 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH && |
4984 | exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI) | |
6614c7d0 | 4985 | printk(KERN_ERR "%s: unexpected exit_int_info 0x%x " |
6aa8b732 | 4986 | "exit_code 0x%x\n", |
b8688d51 | 4987 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
4988 | exit_code); |
4989 | ||
9d8f549d | 4990 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 4991 | || !svm_exit_handlers[exit_code]) { |
7396d337 LA |
4992 | vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code); |
4993 | dump_vmcb(vcpu); | |
4994 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
4995 | vcpu->run->internal.suberror = | |
4996 | KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON; | |
4997 | vcpu->run->internal.ndata = 1; | |
4998 | vcpu->run->internal.data[0] = exit_code; | |
4999 | return 0; | |
6aa8b732 AK |
5000 | } |
5001 | ||
851ba692 | 5002 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
5003 | } |
5004 | ||
5005 | static void reload_tss(struct kvm_vcpu *vcpu) | |
5006 | { | |
5007 | int cpu = raw_smp_processor_id(); | |
5008 | ||
0fe1e009 TH |
5009 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
5010 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
5011 | load_TR_desc(); |
5012 | } | |
5013 | ||
70cd94e6 BS |
5014 | static void pre_sev_run(struct vcpu_svm *svm, int cpu) |
5015 | { | |
5016 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); | |
5017 | int asid = sev_get_asid(svm->vcpu.kvm); | |
5018 | ||
5019 | /* Assign the asid allocated with this SEV guest */ | |
5020 | svm->vmcb->control.asid = asid; | |
5021 | ||
5022 | /* | |
5023 | * Flush guest TLB: | |
5024 | * | |
5025 | * 1) when different VMCB for the same ASID is to be run on the same host CPU. | |
5026 | * 2) or this VMCB was executed on different host CPU in previous VMRUNs. | |
5027 | */ | |
5028 | if (sd->sev_vmcbs[asid] == svm->vmcb && | |
5029 | svm->last_cpu == cpu) | |
5030 | return; | |
5031 | ||
5032 | svm->last_cpu = cpu; | |
5033 | sd->sev_vmcbs[asid] = svm->vmcb; | |
5034 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; | |
5035 | mark_dirty(svm->vmcb, VMCB_ASID); | |
5036 | } | |
5037 | ||
e756fc62 | 5038 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
5039 | { |
5040 | int cpu = raw_smp_processor_id(); | |
5041 | ||
0fe1e009 | 5042 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 5043 | |
70cd94e6 BS |
5044 | if (sev_guest(svm->vcpu.kvm)) |
5045 | return pre_sev_run(svm, cpu); | |
5046 | ||
4b656b12 | 5047 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
5048 | if (svm->asid_generation != sd->asid_generation) |
5049 | new_asid(svm, sd); | |
6aa8b732 AK |
5050 | } |
5051 | ||
95ba8273 GN |
5052 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
5053 | { | |
5054 | struct vcpu_svm *svm = to_svm(vcpu); | |
5055 | ||
5056 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
5057 | vcpu->arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 5058 | set_intercept(svm, INTERCEPT_IRET); |
95ba8273 GN |
5059 | ++vcpu->stat.nmi_injections; |
5060 | } | |
6aa8b732 | 5061 | |
85f455f7 | 5062 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
5063 | { |
5064 | struct vmcb_control_area *control; | |
5065 | ||
340d3bc3 | 5066 | /* The following fields are ignored when AVIC is enabled */ |
e756fc62 | 5067 | control = &svm->vmcb->control; |
85f455f7 | 5068 | control->int_vector = irq; |
6aa8b732 AK |
5069 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
5070 | control->int_ctl |= V_IRQ_MASK | | |
5071 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
decdbf6a | 5072 | mark_dirty(svm->vmcb, VMCB_INTR); |
6aa8b732 AK |
5073 | } |
5074 | ||
66fd3f7f | 5075 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
5076 | { |
5077 | struct vcpu_svm *svm = to_svm(vcpu); | |
5078 | ||
2af9194d | 5079 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 5080 | |
9fb2d2b4 GN |
5081 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
5082 | ++vcpu->stat.irq_injections; | |
5083 | ||
219b65dc AG |
5084 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
5085 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
5086 | } |
5087 | ||
3bbf3565 SS |
5088 | static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu) |
5089 | { | |
5090 | return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK); | |
5091 | } | |
5092 | ||
95ba8273 | 5093 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
5094 | { |
5095 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 5096 | |
3bbf3565 SS |
5097 | if (svm_nested_virtualize_tpr(vcpu) || |
5098 | kvm_vcpu_apicv_active(vcpu)) | |
88ab24ad JR |
5099 | return; |
5100 | ||
596f3142 RK |
5101 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
5102 | ||
95ba8273 | 5103 | if (irr == -1) |
aaacfc9a JR |
5104 | return; |
5105 | ||
95ba8273 | 5106 | if (tpr >= irr) |
4ee546b4 | 5107 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
95ba8273 | 5108 | } |
aaacfc9a | 5109 | |
8d860bbe | 5110 | static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu) |
8d14695f YZ |
5111 | { |
5112 | return; | |
5113 | } | |
5114 | ||
2cf9af0b | 5115 | static bool svm_get_enable_apicv(struct kvm *kvm) |
d62caabb | 5116 | { |
2cf9af0b | 5117 | return avic && irqchip_split(kvm); |
44a95dae SS |
5118 | } |
5119 | ||
5120 | static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) | |
5121 | { | |
d62caabb AS |
5122 | } |
5123 | ||
67c9dddc | 5124 | static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) |
44a95dae | 5125 | { |
d62caabb AS |
5126 | } |
5127 | ||
44a95dae | 5128 | /* Note: Currently only used by Hyper-V. */ |
d62caabb | 5129 | static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) |
c7c9c56c | 5130 | { |
44a95dae SS |
5131 | struct vcpu_svm *svm = to_svm(vcpu); |
5132 | struct vmcb *vmcb = svm->vmcb; | |
5133 | ||
c57cd3c8 SS |
5134 | if (kvm_vcpu_apicv_active(vcpu)) |
5135 | vmcb->control.int_ctl |= AVIC_ENABLE_MASK; | |
5136 | else | |
5137 | vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK; | |
5138 | mark_dirty(vmcb, VMCB_AVIC); | |
c7c9c56c YZ |
5139 | } |
5140 | ||
6308630b | 5141 | static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
c7c9c56c YZ |
5142 | { |
5143 | return; | |
5144 | } | |
5145 | ||
340d3bc3 SS |
5146 | static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec) |
5147 | { | |
5148 | kvm_lapic_set_irr(vec, vcpu->arch.apic); | |
5149 | smp_mb__after_atomic(); | |
5150 | ||
0532dd52 SS |
5151 | if (avic_vcpu_is_running(vcpu)) { |
5152 | int cpuid = vcpu->cpu; | |
5153 | ||
5154 | if (cpuid != get_cpu()) | |
5155 | wrmsrl(SVM_AVIC_DOORBELL, kvm_cpu_get_apicid(cpuid)); | |
5156 | put_cpu(); | |
5157 | } else | |
340d3bc3 SS |
5158 | kvm_vcpu_wake_up(vcpu); |
5159 | } | |
5160 | ||
17e433b5 WL |
5161 | static bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu) |
5162 | { | |
5163 | return false; | |
5164 | } | |
5165 | ||
411b44ba SS |
5166 | static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi) |
5167 | { | |
5168 | unsigned long flags; | |
5169 | struct amd_svm_iommu_ir *cur; | |
5170 | ||
5171 | spin_lock_irqsave(&svm->ir_list_lock, flags); | |
5172 | list_for_each_entry(cur, &svm->ir_list, node) { | |
5173 | if (cur->data != pi->ir_data) | |
5174 | continue; | |
5175 | list_del(&cur->node); | |
5176 | kfree(cur); | |
5177 | break; | |
5178 | } | |
5179 | spin_unlock_irqrestore(&svm->ir_list_lock, flags); | |
5180 | } | |
5181 | ||
5182 | static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi) | |
5183 | { | |
5184 | int ret = 0; | |
5185 | unsigned long flags; | |
5186 | struct amd_svm_iommu_ir *ir; | |
5187 | ||
5188 | /** | |
5189 | * In some cases, the existing irte is updaed and re-set, | |
5190 | * so we need to check here if it's already been * added | |
5191 | * to the ir_list. | |
5192 | */ | |
5193 | if (pi->ir_data && (pi->prev_ga_tag != 0)) { | |
5194 | struct kvm *kvm = svm->vcpu.kvm; | |
5195 | u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag); | |
5196 | struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id); | |
5197 | struct vcpu_svm *prev_svm; | |
5198 | ||
5199 | if (!prev_vcpu) { | |
5200 | ret = -EINVAL; | |
5201 | goto out; | |
5202 | } | |
5203 | ||
5204 | prev_svm = to_svm(prev_vcpu); | |
5205 | svm_ir_list_del(prev_svm, pi); | |
5206 | } | |
5207 | ||
5208 | /** | |
5209 | * Allocating new amd_iommu_pi_data, which will get | |
5210 | * add to the per-vcpu ir_list. | |
5211 | */ | |
1ec69647 | 5212 | ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL_ACCOUNT); |
411b44ba SS |
5213 | if (!ir) { |
5214 | ret = -ENOMEM; | |
5215 | goto out; | |
5216 | } | |
5217 | ir->data = pi->ir_data; | |
5218 | ||
5219 | spin_lock_irqsave(&svm->ir_list_lock, flags); | |
5220 | list_add(&ir->node, &svm->ir_list); | |
5221 | spin_unlock_irqrestore(&svm->ir_list_lock, flags); | |
5222 | out: | |
5223 | return ret; | |
5224 | } | |
5225 | ||
5226 | /** | |
5227 | * Note: | |
5228 | * The HW cannot support posting multicast/broadcast | |
5229 | * interrupts to a vCPU. So, we still use legacy interrupt | |
5230 | * remapping for these kind of interrupts. | |
5231 | * | |
5232 | * For lowest-priority interrupts, we only support | |
5233 | * those with single CPU as the destination, e.g. user | |
5234 | * configures the interrupts via /proc/irq or uses | |
5235 | * irqbalance to make the interrupts single-CPU. | |
5236 | */ | |
5237 | static int | |
5238 | get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, | |
5239 | struct vcpu_data *vcpu_info, struct vcpu_svm **svm) | |
5240 | { | |
5241 | struct kvm_lapic_irq irq; | |
5242 | struct kvm_vcpu *vcpu = NULL; | |
5243 | ||
5244 | kvm_set_msi_irq(kvm, e, &irq); | |
5245 | ||
fdcf7562 AG |
5246 | if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) || |
5247 | !kvm_irq_is_postable(&irq)) { | |
411b44ba SS |
5248 | pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n", |
5249 | __func__, irq.vector); | |
5250 | return -1; | |
5251 | } | |
5252 | ||
5253 | pr_debug("SVM: %s: use GA mode for irq %u\n", __func__, | |
5254 | irq.vector); | |
5255 | *svm = to_svm(vcpu); | |
d0ec49d4 | 5256 | vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page)); |
411b44ba SS |
5257 | vcpu_info->vector = irq.vector; |
5258 | ||
5259 | return 0; | |
5260 | } | |
5261 | ||
5262 | /* | |
5263 | * svm_update_pi_irte - set IRTE for Posted-Interrupts | |
5264 | * | |
5265 | * @kvm: kvm | |
5266 | * @host_irq: host irq of the interrupt | |
5267 | * @guest_irq: gsi of the interrupt | |
5268 | * @set: set or unset PI | |
5269 | * returns 0 on success, < 0 on failure | |
5270 | */ | |
5271 | static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq, | |
5272 | uint32_t guest_irq, bool set) | |
5273 | { | |
5274 | struct kvm_kernel_irq_routing_entry *e; | |
5275 | struct kvm_irq_routing_table *irq_rt; | |
5276 | int idx, ret = -EINVAL; | |
5277 | ||
5278 | if (!kvm_arch_has_assigned_device(kvm) || | |
5279 | !irq_remapping_cap(IRQ_POSTING_CAP)) | |
5280 | return 0; | |
5281 | ||
5282 | pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n", | |
5283 | __func__, host_irq, guest_irq, set); | |
5284 | ||
5285 | idx = srcu_read_lock(&kvm->irq_srcu); | |
5286 | irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); | |
5287 | WARN_ON(guest_irq >= irq_rt->nr_rt_entries); | |
5288 | ||
5289 | hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { | |
5290 | struct vcpu_data vcpu_info; | |
5291 | struct vcpu_svm *svm = NULL; | |
5292 | ||
5293 | if (e->type != KVM_IRQ_ROUTING_MSI) | |
5294 | continue; | |
5295 | ||
5296 | /** | |
5297 | * Here, we setup with legacy mode in the following cases: | |
5298 | * 1. When cannot target interrupt to a specific vcpu. | |
5299 | * 2. Unsetting posted interrupt. | |
5300 | * 3. APIC virtialization is disabled for the vcpu. | |
fdcf7562 | 5301 | * 4. IRQ has incompatible delivery mode (SMI, INIT, etc) |
411b44ba SS |
5302 | */ |
5303 | if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set && | |
5304 | kvm_vcpu_apicv_active(&svm->vcpu)) { | |
5305 | struct amd_iommu_pi_data pi; | |
5306 | ||
5307 | /* Try to enable guest_mode in IRTE */ | |
d0ec49d4 TL |
5308 | pi.base = __sme_set(page_to_phys(svm->avic_backing_page) & |
5309 | AVIC_HPA_MASK); | |
81811c16 | 5310 | pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id, |
411b44ba SS |
5311 | svm->vcpu.vcpu_id); |
5312 | pi.is_guest_mode = true; | |
5313 | pi.vcpu_data = &vcpu_info; | |
5314 | ret = irq_set_vcpu_affinity(host_irq, &pi); | |
5315 | ||
5316 | /** | |
5317 | * Here, we successfully setting up vcpu affinity in | |
5318 | * IOMMU guest mode. Now, we need to store the posted | |
5319 | * interrupt information in a per-vcpu ir_list so that | |
5320 | * we can reference to them directly when we update vcpu | |
5321 | * scheduling information in IOMMU irte. | |
5322 | */ | |
5323 | if (!ret && pi.is_guest_mode) | |
5324 | svm_ir_list_add(svm, &pi); | |
5325 | } else { | |
5326 | /* Use legacy mode in IRTE */ | |
5327 | struct amd_iommu_pi_data pi; | |
5328 | ||
5329 | /** | |
5330 | * Here, pi is used to: | |
5331 | * - Tell IOMMU to use legacy mode for this interrupt. | |
5332 | * - Retrieve ga_tag of prior interrupt remapping data. | |
5333 | */ | |
5334 | pi.is_guest_mode = false; | |
5335 | ret = irq_set_vcpu_affinity(host_irq, &pi); | |
5336 | ||
5337 | /** | |
5338 | * Check if the posted interrupt was previously | |
5339 | * setup with the guest_mode by checking if the ga_tag | |
5340 | * was cached. If so, we need to clean up the per-vcpu | |
5341 | * ir_list. | |
5342 | */ | |
5343 | if (!ret && pi.prev_ga_tag) { | |
5344 | int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag); | |
5345 | struct kvm_vcpu *vcpu; | |
5346 | ||
5347 | vcpu = kvm_get_vcpu_by_id(kvm, id); | |
5348 | if (vcpu) | |
5349 | svm_ir_list_del(to_svm(vcpu), &pi); | |
5350 | } | |
5351 | } | |
5352 | ||
5353 | if (!ret && svm) { | |
2698d82e | 5354 | trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id, |
5355 | e->gsi, vcpu_info.vector, | |
411b44ba SS |
5356 | vcpu_info.pi_desc_addr, set); |
5357 | } | |
5358 | ||
5359 | if (ret < 0) { | |
5360 | pr_err("%s: failed to update PI IRTE\n", __func__); | |
5361 | goto out; | |
5362 | } | |
5363 | } | |
5364 | ||
5365 | ret = 0; | |
5366 | out: | |
5367 | srcu_read_unlock(&kvm->irq_srcu, idx); | |
5368 | return ret; | |
5369 | } | |
5370 | ||
95ba8273 GN |
5371 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
5372 | { | |
5373 | struct vcpu_svm *svm = to_svm(vcpu); | |
5374 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
5375 | int ret; |
5376 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
5377 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
5378 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
5379 | ||
5380 | return ret; | |
aaacfc9a JR |
5381 | } |
5382 | ||
3cfc3092 JK |
5383 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
5384 | { | |
5385 | struct vcpu_svm *svm = to_svm(vcpu); | |
5386 | ||
5387 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
5388 | } | |
5389 | ||
5390 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
5391 | { | |
5392 | struct vcpu_svm *svm = to_svm(vcpu); | |
5393 | ||
5394 | if (masked) { | |
5395 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 5396 | set_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
5397 | } else { |
5398 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
8a05a1b8 | 5399 | clr_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
5400 | } |
5401 | } | |
5402 | ||
78646121 GN |
5403 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
5404 | { | |
5405 | struct vcpu_svm *svm = to_svm(vcpu); | |
5406 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
5407 | int ret; |
5408 | ||
5409 | if (!gif_set(svm) || | |
5410 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
5411 | return 0; | |
5412 | ||
f6e78475 | 5413 | ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF); |
7fcdb510 | 5414 | |
2030753d | 5415 | if (is_guest_mode(vcpu)) |
7fcdb510 JR |
5416 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); |
5417 | ||
5418 | return ret; | |
78646121 GN |
5419 | } |
5420 | ||
c9a7953f | 5421 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 5422 | { |
219b65dc | 5423 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 5424 | |
340d3bc3 SS |
5425 | if (kvm_vcpu_apicv_active(vcpu)) |
5426 | return; | |
5427 | ||
e0231715 JR |
5428 | /* |
5429 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
5430 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
5431 | * get that intercept, this function will be called again though and | |
640bd6e5 JN |
5432 | * we'll get the vintr intercept. However, if the vGIF feature is |
5433 | * enabled, the STGI interception will not occur. Enable the irq | |
5434 | * window under the assumption that the hardware will set the GIF. | |
e0231715 | 5435 | */ |
640bd6e5 | 5436 | if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) { |
219b65dc AG |
5437 | svm_set_vintr(svm); |
5438 | svm_inject_irq(svm, 0x0); | |
5439 | } | |
85f455f7 ED |
5440 | } |
5441 | ||
c9a7953f | 5442 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 5443 | { |
04d2cc77 | 5444 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 5445 | |
44c11430 GN |
5446 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
5447 | == HF_NMI_MASK) | |
c9a7953f | 5448 | return; /* IRET will cause a vm exit */ |
44c11430 | 5449 | |
640bd6e5 JN |
5450 | if (!gif_set(svm)) { |
5451 | if (vgif_enabled(svm)) | |
5452 | set_intercept(svm, INTERCEPT_STGI); | |
1a5e1852 | 5453 | return; /* STGI will cause a vm exit */ |
640bd6e5 | 5454 | } |
1a5e1852 LP |
5455 | |
5456 | if (svm->nested.exit_required) | |
5457 | return; /* we're not going to run the guest yet */ | |
5458 | ||
e0231715 JR |
5459 | /* |
5460 | * Something prevents NMI from been injected. Single step over possible | |
5461 | * problem (IRET or exception injection or interrupt shadow) | |
5462 | */ | |
ab2f4d73 | 5463 | svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu); |
6be7d306 | 5464 | svm->nmi_singlestep = true; |
44c11430 | 5465 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
c1150d8c DL |
5466 | } |
5467 | ||
cbc94022 IE |
5468 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
5469 | { | |
5470 | return 0; | |
5471 | } | |
5472 | ||
2ac52ab8 SC |
5473 | static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr) |
5474 | { | |
5475 | return 0; | |
5476 | } | |
5477 | ||
c2ba05cc | 5478 | static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa) |
d9e368d6 | 5479 | { |
38e5e92f JR |
5480 | struct vcpu_svm *svm = to_svm(vcpu); |
5481 | ||
5482 | if (static_cpu_has(X86_FEATURE_FLUSHBYASID)) | |
5483 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; | |
5484 | else | |
5485 | svm->asid_generation--; | |
d9e368d6 AK |
5486 | } |
5487 | ||
faff8758 JS |
5488 | static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva) |
5489 | { | |
5490 | struct vcpu_svm *svm = to_svm(vcpu); | |
5491 | ||
5492 | invlpga(gva, svm->vmcb->control.asid); | |
5493 | } | |
5494 | ||
04d2cc77 AK |
5495 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
5496 | { | |
5497 | } | |
5498 | ||
d7bf8221 JR |
5499 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
5500 | { | |
5501 | struct vcpu_svm *svm = to_svm(vcpu); | |
5502 | ||
3bbf3565 | 5503 | if (svm_nested_virtualize_tpr(vcpu)) |
88ab24ad JR |
5504 | return; |
5505 | ||
4ee546b4 | 5506 | if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) { |
d7bf8221 | 5507 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; |
615d5193 | 5508 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
5509 | } |
5510 | } | |
5511 | ||
649d6864 JR |
5512 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
5513 | { | |
5514 | struct vcpu_svm *svm = to_svm(vcpu); | |
5515 | u64 cr8; | |
5516 | ||
3bbf3565 SS |
5517 | if (svm_nested_virtualize_tpr(vcpu) || |
5518 | kvm_vcpu_apicv_active(vcpu)) | |
88ab24ad JR |
5519 | return; |
5520 | ||
649d6864 JR |
5521 | cr8 = kvm_get_cr8(vcpu); |
5522 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
5523 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
5524 | } | |
5525 | ||
9222be18 GN |
5526 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
5527 | { | |
5528 | u8 vector; | |
5529 | int type; | |
5530 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
5531 | unsigned int3_injected = svm->int3_injected; |
5532 | ||
5533 | svm->int3_injected = 0; | |
9222be18 | 5534 | |
bd3d1ec3 AK |
5535 | /* |
5536 | * If we've made progress since setting HF_IRET_MASK, we've | |
5537 | * executed an IRET and can allow NMI injection. | |
5538 | */ | |
5539 | if ((svm->vcpu.arch.hflags & HF_IRET_MASK) | |
5540 | && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) { | |
44c11430 | 5541 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); |
3842d135 AK |
5542 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
5543 | } | |
44c11430 | 5544 | |
9222be18 GN |
5545 | svm->vcpu.arch.nmi_injected = false; |
5546 | kvm_clear_exception_queue(&svm->vcpu); | |
5547 | kvm_clear_interrupt_queue(&svm->vcpu); | |
5548 | ||
5549 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
5550 | return; | |
5551 | ||
3842d135 AK |
5552 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
5553 | ||
9222be18 GN |
5554 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; |
5555 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
5556 | ||
5557 | switch (type) { | |
5558 | case SVM_EXITINTINFO_TYPE_NMI: | |
5559 | svm->vcpu.arch.nmi_injected = true; | |
5560 | break; | |
5561 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
5562 | /* |
5563 | * In case of software exceptions, do not reinject the vector, | |
5564 | * but re-execute the instruction instead. Rewind RIP first | |
5565 | * if we emulated INT3 before. | |
5566 | */ | |
5567 | if (kvm_exception_is_soft(vector)) { | |
5568 | if (vector == BP_VECTOR && int3_injected && | |
5569 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
5570 | kvm_rip_write(&svm->vcpu, | |
5571 | kvm_rip_read(&svm->vcpu) - | |
5572 | int3_injected); | |
9222be18 | 5573 | break; |
66b7138f | 5574 | } |
9222be18 GN |
5575 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
5576 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 5577 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
5578 | |
5579 | } else | |
ce7ddec4 | 5580 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
5581 | break; |
5582 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 5583 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
5584 | break; |
5585 | default: | |
5586 | break; | |
5587 | } | |
5588 | } | |
5589 | ||
b463a6f7 AK |
5590 | static void svm_cancel_injection(struct kvm_vcpu *vcpu) |
5591 | { | |
5592 | struct vcpu_svm *svm = to_svm(vcpu); | |
5593 | struct vmcb_control_area *control = &svm->vmcb->control; | |
5594 | ||
5595 | control->exit_int_info = control->event_inj; | |
5596 | control->exit_int_info_err = control->event_inj_err; | |
5597 | control->event_inj = 0; | |
5598 | svm_complete_interrupts(svm); | |
5599 | } | |
5600 | ||
851ba692 | 5601 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 5602 | { |
a2fa3e9f | 5603 | struct vcpu_svm *svm = to_svm(vcpu); |
d9e368d6 | 5604 | |
2041a06a JR |
5605 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
5606 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
5607 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
5608 | ||
cd3ff653 JR |
5609 | /* |
5610 | * A vmexit emulation is required before the vcpu can be executed | |
5611 | * again. | |
5612 | */ | |
5613 | if (unlikely(svm->nested.exit_required)) | |
5614 | return; | |
5615 | ||
a12713c2 LP |
5616 | /* |
5617 | * Disable singlestep if we're injecting an interrupt/exception. | |
5618 | * We don't want our modified rflags to be pushed on the stack where | |
5619 | * we might not be able to easily reset them if we disabled NMI | |
5620 | * singlestep later. | |
5621 | */ | |
5622 | if (svm->nmi_singlestep && svm->vmcb->control.event_inj) { | |
5623 | /* | |
5624 | * Event injection happens before external interrupts cause a | |
5625 | * vmexit and interrupts are disabled here, so smp_send_reschedule | |
5626 | * is enough to force an immediate vmexit. | |
5627 | */ | |
5628 | disable_nmi_singlestep(svm); | |
5629 | smp_send_reschedule(vcpu->cpu); | |
5630 | } | |
5631 | ||
e756fc62 | 5632 | pre_svm_run(svm); |
6aa8b732 | 5633 | |
649d6864 JR |
5634 | sync_lapic_to_cr8(vcpu); |
5635 | ||
cda0ffdd | 5636 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 5637 | |
04d2cc77 | 5638 | clgi(); |
139a12cf | 5639 | kvm_load_guest_xsave_state(vcpu); |
04d2cc77 | 5640 | |
b6c4bc65 WL |
5641 | if (lapic_in_kernel(vcpu) && |
5642 | vcpu->arch.apic->lapic_timer.timer_advance_ns) | |
5643 | kvm_wait_lapic_expire(vcpu); | |
5644 | ||
b2ac58f9 KA |
5645 | /* |
5646 | * If this vCPU has touched SPEC_CTRL, restore the guest's value if | |
5647 | * it's non-zero. Since vmentry is serialising on affected CPUs, there | |
5648 | * is no need to worry about the conditional branch over the wrmsr | |
5649 | * being speculatively taken. | |
5650 | */ | |
ccbcd267 | 5651 | x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl); |
b2ac58f9 | 5652 | |
024d83ca TG |
5653 | local_irq_enable(); |
5654 | ||
6aa8b732 | 5655 | asm volatile ( |
7454766f AK |
5656 | "push %%" _ASM_BP "; \n\t" |
5657 | "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t" | |
5658 | "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t" | |
5659 | "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t" | |
5660 | "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t" | |
5661 | "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t" | |
5662 | "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 5663 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
5664 | "mov %c[r8](%[svm]), %%r8 \n\t" |
5665 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
5666 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
5667 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
5668 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
5669 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
5670 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
5671 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
5672 | #endif |
5673 | ||
6aa8b732 | 5674 | /* Enter guest mode */ |
7454766f AK |
5675 | "push %%" _ASM_AX " \n\t" |
5676 | "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t" | |
ac5ffda2 UB |
5677 | __ex("vmload %%" _ASM_AX) "\n\t" |
5678 | __ex("vmrun %%" _ASM_AX) "\n\t" | |
5679 | __ex("vmsave %%" _ASM_AX) "\n\t" | |
7454766f | 5680 | "pop %%" _ASM_AX " \n\t" |
6aa8b732 AK |
5681 | |
5682 | /* Save guest registers, load host registers */ | |
7454766f AK |
5683 | "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t" |
5684 | "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t" | |
5685 | "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t" | |
5686 | "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t" | |
5687 | "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t" | |
5688 | "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 5689 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
5690 | "mov %%r8, %c[r8](%[svm]) \n\t" |
5691 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
5692 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
5693 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
5694 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
5695 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
5696 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
5697 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
0cb5b306 JM |
5698 | /* |
5699 | * Clear host registers marked as clobbered to prevent | |
5700 | * speculative use. | |
5701 | */ | |
43ce76ce UB |
5702 | "xor %%r8d, %%r8d \n\t" |
5703 | "xor %%r9d, %%r9d \n\t" | |
5704 | "xor %%r10d, %%r10d \n\t" | |
5705 | "xor %%r11d, %%r11d \n\t" | |
5706 | "xor %%r12d, %%r12d \n\t" | |
5707 | "xor %%r13d, %%r13d \n\t" | |
5708 | "xor %%r14d, %%r14d \n\t" | |
5709 | "xor %%r15d, %%r15d \n\t" | |
6aa8b732 | 5710 | #endif |
43ce76ce UB |
5711 | "xor %%ebx, %%ebx \n\t" |
5712 | "xor %%ecx, %%ecx \n\t" | |
5713 | "xor %%edx, %%edx \n\t" | |
5714 | "xor %%esi, %%esi \n\t" | |
5715 | "xor %%edi, %%edi \n\t" | |
7454766f | 5716 | "pop %%" _ASM_BP |
6aa8b732 | 5717 | : |
fb3f0f51 | 5718 | : [svm]"a"(svm), |
6aa8b732 | 5719 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
5720 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
5721 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
5722 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
5723 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
5724 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
5725 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 5726 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
5727 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
5728 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
5729 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
5730 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
5731 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
5732 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
5733 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
5734 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 5735 | #endif |
54a08c04 LV |
5736 | : "cc", "memory" |
5737 | #ifdef CONFIG_X86_64 | |
7454766f | 5738 | , "rbx", "rcx", "rdx", "rsi", "rdi" |
54a08c04 | 5739 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
7454766f AK |
5740 | #else |
5741 | , "ebx", "ecx", "edx", "esi", "edi" | |
54a08c04 LV |
5742 | #endif |
5743 | ); | |
6aa8b732 | 5744 | |
15e6c22f TG |
5745 | /* Eliminate branch target predictions from guest mode */ |
5746 | vmexit_fill_RSB(); | |
5747 | ||
5748 | #ifdef CONFIG_X86_64 | |
5749 | wrmsrl(MSR_GS_BASE, svm->host.gs_base); | |
5750 | #else | |
5751 | loadsegment(fs, svm->host.fs); | |
5752 | #ifndef CONFIG_X86_32_LAZY_GS | |
5753 | loadsegment(gs, svm->host.gs); | |
5754 | #endif | |
5755 | #endif | |
5756 | ||
b2ac58f9 KA |
5757 | /* |
5758 | * We do not use IBRS in the kernel. If this vCPU has used the | |
5759 | * SPEC_CTRL MSR it may have left it on; save the value and | |
5760 | * turn it off. This is much more efficient than blindly adding | |
5761 | * it to the atomic save/restore list. Especially as the former | |
5762 | * (Saving guest MSRs on vmexit) doesn't even exist in KVM. | |
5763 | * | |
5764 | * For non-nested case: | |
5765 | * If the L01 MSR bitmap does not intercept the MSR, then we need to | |
5766 | * save it. | |
5767 | * | |
5768 | * For nested case: | |
5769 | * If the L02 MSR bitmap does not intercept the MSR, then we need to | |
5770 | * save it. | |
5771 | */ | |
946fbbc1 | 5772 | if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))) |
ecb586bd | 5773 | svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL); |
b2ac58f9 | 5774 | |
6aa8b732 AK |
5775 | reload_tss(vcpu); |
5776 | ||
56ba47dd AK |
5777 | local_irq_disable(); |
5778 | ||
024d83ca TG |
5779 | x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl); |
5780 | ||
13c34e07 AK |
5781 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
5782 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
5783 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
5784 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
5785 | ||
3781c01c | 5786 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) |
dd60d217 | 5787 | kvm_before_interrupt(&svm->vcpu); |
3781c01c | 5788 | |
139a12cf | 5789 | kvm_load_host_xsave_state(vcpu); |
3781c01c JR |
5790 | stgi(); |
5791 | ||
5792 | /* Any pending NMI will happen here */ | |
5793 | ||
5794 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) | |
dd60d217 | 5795 | kvm_after_interrupt(&svm->vcpu); |
3781c01c | 5796 | |
d7bf8221 JR |
5797 | sync_cr8_to_lapic(vcpu); |
5798 | ||
a2fa3e9f | 5799 | svm->next_rip = 0; |
9222be18 | 5800 | |
38e5e92f JR |
5801 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
5802 | ||
631bc487 GN |
5803 | /* if exit due to PF check for async PF */ |
5804 | if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
1261bfa3 | 5805 | svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); |
631bc487 | 5806 | |
6de4f3ad AK |
5807 | if (npt_enabled) { |
5808 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
5809 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
5810 | } | |
fe5913e4 JR |
5811 | |
5812 | /* | |
5813 | * We need to handle MC intercepts here before the vcpu has a chance to | |
5814 | * change the physical cpu | |
5815 | */ | |
5816 | if (unlikely(svm->vmcb->control.exit_code == | |
5817 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
5818 | svm_handle_mce(svm); | |
8d28fec4 RJ |
5819 | |
5820 | mark_all_clean(svm->vmcb); | |
6aa8b732 | 5821 | } |
c207aee4 | 5822 | STACK_FRAME_NON_STANDARD(svm_vcpu_run); |
6aa8b732 | 5823 | |
6aa8b732 AK |
5824 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
5825 | { | |
a2fa3e9f GH |
5826 | struct vcpu_svm *svm = to_svm(vcpu); |
5827 | ||
d0ec49d4 | 5828 | svm->vmcb->save.cr3 = __sme_set(root); |
dcca1a65 | 5829 | mark_dirty(svm->vmcb, VMCB_CR); |
6aa8b732 AK |
5830 | } |
5831 | ||
1c97f0a0 JR |
5832 | static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
5833 | { | |
5834 | struct vcpu_svm *svm = to_svm(vcpu); | |
5835 | ||
d0ec49d4 | 5836 | svm->vmcb->control.nested_cr3 = __sme_set(root); |
b2747166 | 5837 | mark_dirty(svm->vmcb, VMCB_NPT); |
1c97f0a0 JR |
5838 | |
5839 | /* Also sync guest cr3 here in case we live migrate */ | |
9f8fe504 | 5840 | svm->vmcb->save.cr3 = kvm_read_cr3(vcpu); |
dcca1a65 | 5841 | mark_dirty(svm->vmcb, VMCB_CR); |
1c97f0a0 JR |
5842 | } |
5843 | ||
6aa8b732 AK |
5844 | static int is_disabled(void) |
5845 | { | |
6031a61c JR |
5846 | u64 vm_cr; |
5847 | ||
5848 | rdmsrl(MSR_VM_CR, vm_cr); | |
5849 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
5850 | return 1; | |
5851 | ||
6aa8b732 AK |
5852 | return 0; |
5853 | } | |
5854 | ||
102d8325 IM |
5855 | static void |
5856 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
5857 | { | |
5858 | /* | |
5859 | * Patch in the VMMCALL instruction: | |
5860 | */ | |
5861 | hypercall[0] = 0x0f; | |
5862 | hypercall[1] = 0x01; | |
5863 | hypercall[2] = 0xd9; | |
102d8325 IM |
5864 | } |
5865 | ||
f257d6dc | 5866 | static int __init svm_check_processor_compat(void) |
002c7f7c | 5867 | { |
f257d6dc | 5868 | return 0; |
002c7f7c YS |
5869 | } |
5870 | ||
774ead3a AK |
5871 | static bool svm_cpu_has_accelerated_tpr(void) |
5872 | { | |
5873 | return false; | |
5874 | } | |
5875 | ||
bc226f07 | 5876 | static bool svm_has_emulated_msr(int index) |
6d396b55 | 5877 | { |
e87555e5 VK |
5878 | switch (index) { |
5879 | case MSR_IA32_MCG_EXT_CTL: | |
95c5c7c7 | 5880 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: |
e87555e5 VK |
5881 | return false; |
5882 | default: | |
5883 | break; | |
5884 | } | |
5885 | ||
6d396b55 PB |
5886 | return true; |
5887 | } | |
5888 | ||
fc07e76a PB |
5889 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
5890 | { | |
5891 | return 0; | |
5892 | } | |
5893 | ||
0e851880 SY |
5894 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
5895 | { | |
6092d3d3 JR |
5896 | struct vcpu_svm *svm = to_svm(vcpu); |
5897 | ||
7204160e AL |
5898 | vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && |
5899 | boot_cpu_has(X86_FEATURE_XSAVES); | |
5900 | ||
6092d3d3 | 5901 | /* Update nrips enabled cache */ |
d6321d49 | 5902 | svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS); |
46781eae SS |
5903 | |
5904 | if (!kvm_vcpu_apicv_active(vcpu)) | |
5905 | return; | |
5906 | ||
1b4d56b8 | 5907 | guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC); |
0e851880 SY |
5908 | } |
5909 | ||
50896de4 PB |
5910 | #define F(x) bit(X86_FEATURE_##x) |
5911 | ||
d4330ef2 JR |
5912 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
5913 | { | |
c2c63a49 | 5914 | switch (func) { |
46781eae SS |
5915 | case 0x1: |
5916 | if (avic) | |
5917 | entry->ecx &= ~bit(X86_FEATURE_X2APIC); | |
5918 | break; | |
4c62a2dc JR |
5919 | case 0x80000001: |
5920 | if (nested) | |
5921 | entry->ecx |= (1 << 2); /* Set SVM bit */ | |
5922 | break; | |
50896de4 PB |
5923 | case 0x80000008: |
5924 | if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) || | |
5925 | boot_cpu_has(X86_FEATURE_AMD_SSBD)) | |
5926 | entry->ebx |= F(VIRT_SSBD); | |
5927 | break; | |
c2c63a49 JR |
5928 | case 0x8000000A: |
5929 | entry->eax = 1; /* SVM revision 1 */ | |
5930 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
5931 | ASID emulation to nested SVM */ | |
5932 | entry->ecx = 0; /* Reserved */ | |
7a190667 JR |
5933 | entry->edx = 0; /* Per default do not support any |
5934 | additional features */ | |
5935 | ||
5936 | /* Support next_rip if host supports it */ | |
2a6b20b8 | 5937 | if (boot_cpu_has(X86_FEATURE_NRIPS)) |
50896de4 | 5938 | entry->edx |= F(NRIPS); |
c2c63a49 | 5939 | |
3d4aeaad JR |
5940 | /* Support NPT for the guest if enabled */ |
5941 | if (npt_enabled) | |
50896de4 | 5942 | entry->edx |= F(NPT); |
3d4aeaad | 5943 | |
c2c63a49 | 5944 | break; |
8765d753 BS |
5945 | case 0x8000001F: |
5946 | /* Support memory encryption cpuid if host supports it */ | |
5947 | if (boot_cpu_has(X86_FEATURE_SEV)) | |
5948 | cpuid(0x8000001f, &entry->eax, &entry->ebx, | |
5949 | &entry->ecx, &entry->edx); | |
5950 | ||
c2c63a49 | 5951 | } |
d4330ef2 JR |
5952 | } |
5953 | ||
17cc3935 | 5954 | static int svm_get_lpage_level(void) |
344f414f | 5955 | { |
17cc3935 | 5956 | return PT_PDPE_LEVEL; |
344f414f JR |
5957 | } |
5958 | ||
4e47c7a6 SY |
5959 | static bool svm_rdtscp_supported(void) |
5960 | { | |
46896c73 | 5961 | return boot_cpu_has(X86_FEATURE_RDTSCP); |
4e47c7a6 SY |
5962 | } |
5963 | ||
ad756a16 MJ |
5964 | static bool svm_invpcid_supported(void) |
5965 | { | |
5966 | return false; | |
5967 | } | |
5968 | ||
93c4adc7 PB |
5969 | static bool svm_mpx_supported(void) |
5970 | { | |
5971 | return false; | |
5972 | } | |
5973 | ||
55412b2e WL |
5974 | static bool svm_xsaves_supported(void) |
5975 | { | |
52297436 | 5976 | return boot_cpu_has(X86_FEATURE_XSAVES); |
55412b2e WL |
5977 | } |
5978 | ||
66336cab PB |
5979 | static bool svm_umip_emulated(void) |
5980 | { | |
5981 | return false; | |
5982 | } | |
5983 | ||
86f5201d CP |
5984 | static bool svm_pt_supported(void) |
5985 | { | |
5986 | return false; | |
5987 | } | |
5988 | ||
f5f48ee1 SY |
5989 | static bool svm_has_wbinvd_exit(void) |
5990 | { | |
5991 | return true; | |
5992 | } | |
5993 | ||
8061252e | 5994 | #define PRE_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 5995 | .stage = X86_ICPT_PRE_EXCEPT, } |
cfec82cb | 5996 | #define POST_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 5997 | .stage = X86_ICPT_POST_EXCEPT, } |
d7eb8203 | 5998 | #define POST_MEM(exit) { .exit_code = (exit), \ |
40e19b51 | 5999 | .stage = X86_ICPT_POST_MEMACCESS, } |
cfec82cb | 6000 | |
09941fbb | 6001 | static const struct __x86_intercept { |
cfec82cb JR |
6002 | u32 exit_code; |
6003 | enum x86_intercept_stage stage; | |
cfec82cb JR |
6004 | } x86_intercept_map[] = { |
6005 | [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0), | |
6006 | [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0), | |
6007 | [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0), | |
6008 | [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0), | |
6009 | [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0), | |
3b88e41a JR |
6010 | [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0), |
6011 | [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0), | |
dee6bb70 JR |
6012 | [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ), |
6013 | [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ), | |
6014 | [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE), | |
6015 | [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE), | |
6016 | [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ), | |
6017 | [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ), | |
6018 | [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE), | |
6019 | [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE), | |
01de8b09 JR |
6020 | [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN), |
6021 | [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL), | |
6022 | [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD), | |
6023 | [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE), | |
6024 | [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI), | |
6025 | [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI), | |
6026 | [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT), | |
6027 | [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA), | |
d7eb8203 JR |
6028 | [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP), |
6029 | [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR), | |
6030 | [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT), | |
8061252e JR |
6031 | [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG), |
6032 | [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD), | |
6033 | [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD), | |
6034 | [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR), | |
6035 | [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC), | |
6036 | [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR), | |
6037 | [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC), | |
6038 | [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID), | |
6039 | [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM), | |
bf608f88 JR |
6040 | [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE), |
6041 | [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF), | |
6042 | [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF), | |
6043 | [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT), | |
6044 | [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET), | |
6045 | [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP), | |
6046 | [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT), | |
f6511935 JR |
6047 | [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO), |
6048 | [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO), | |
6049 | [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO), | |
6050 | [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO), | |
02d4160f | 6051 | [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV), |
cfec82cb JR |
6052 | }; |
6053 | ||
8061252e | 6054 | #undef PRE_EX |
cfec82cb | 6055 | #undef POST_EX |
d7eb8203 | 6056 | #undef POST_MEM |
cfec82cb | 6057 | |
8a76d7f2 JR |
6058 | static int svm_check_intercept(struct kvm_vcpu *vcpu, |
6059 | struct x86_instruction_info *info, | |
6060 | enum x86_intercept_stage stage) | |
6061 | { | |
cfec82cb JR |
6062 | struct vcpu_svm *svm = to_svm(vcpu); |
6063 | int vmexit, ret = X86EMUL_CONTINUE; | |
6064 | struct __x86_intercept icpt_info; | |
6065 | struct vmcb *vmcb = svm->vmcb; | |
6066 | ||
6067 | if (info->intercept >= ARRAY_SIZE(x86_intercept_map)) | |
6068 | goto out; | |
6069 | ||
6070 | icpt_info = x86_intercept_map[info->intercept]; | |
6071 | ||
40e19b51 | 6072 | if (stage != icpt_info.stage) |
cfec82cb JR |
6073 | goto out; |
6074 | ||
6075 | switch (icpt_info.exit_code) { | |
6076 | case SVM_EXIT_READ_CR0: | |
6077 | if (info->intercept == x86_intercept_cr_read) | |
6078 | icpt_info.exit_code += info->modrm_reg; | |
6079 | break; | |
6080 | case SVM_EXIT_WRITE_CR0: { | |
6081 | unsigned long cr0, val; | |
6082 | u64 intercept; | |
6083 | ||
6084 | if (info->intercept == x86_intercept_cr_write) | |
6085 | icpt_info.exit_code += info->modrm_reg; | |
6086 | ||
62baf44c JK |
6087 | if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 || |
6088 | info->intercept == x86_intercept_clts) | |
cfec82cb JR |
6089 | break; |
6090 | ||
6091 | intercept = svm->nested.intercept; | |
6092 | ||
6093 | if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))) | |
6094 | break; | |
6095 | ||
6096 | cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK; | |
6097 | val = info->src_val & ~SVM_CR0_SELECTIVE_MASK; | |
6098 | ||
6099 | if (info->intercept == x86_intercept_lmsw) { | |
6100 | cr0 &= 0xfUL; | |
6101 | val &= 0xfUL; | |
6102 | /* lmsw can't clear PE - catch this here */ | |
6103 | if (cr0 & X86_CR0_PE) | |
6104 | val |= X86_CR0_PE; | |
6105 | } | |
6106 | ||
6107 | if (cr0 ^ val) | |
6108 | icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
6109 | ||
6110 | break; | |
6111 | } | |
3b88e41a JR |
6112 | case SVM_EXIT_READ_DR0: |
6113 | case SVM_EXIT_WRITE_DR0: | |
6114 | icpt_info.exit_code += info->modrm_reg; | |
6115 | break; | |
8061252e JR |
6116 | case SVM_EXIT_MSR: |
6117 | if (info->intercept == x86_intercept_wrmsr) | |
6118 | vmcb->control.exit_info_1 = 1; | |
6119 | else | |
6120 | vmcb->control.exit_info_1 = 0; | |
6121 | break; | |
bf608f88 JR |
6122 | case SVM_EXIT_PAUSE: |
6123 | /* | |
6124 | * We get this for NOP only, but pause | |
6125 | * is rep not, check this here | |
6126 | */ | |
6127 | if (info->rep_prefix != REPE_PREFIX) | |
6128 | goto out; | |
49a8afca | 6129 | break; |
f6511935 JR |
6130 | case SVM_EXIT_IOIO: { |
6131 | u64 exit_info; | |
6132 | u32 bytes; | |
6133 | ||
f6511935 JR |
6134 | if (info->intercept == x86_intercept_in || |
6135 | info->intercept == x86_intercept_ins) { | |
6cbc5f5a JK |
6136 | exit_info = ((info->src_val & 0xffff) << 16) | |
6137 | SVM_IOIO_TYPE_MASK; | |
f6511935 | 6138 | bytes = info->dst_bytes; |
6493f157 | 6139 | } else { |
6cbc5f5a | 6140 | exit_info = (info->dst_val & 0xffff) << 16; |
6493f157 | 6141 | bytes = info->src_bytes; |
f6511935 JR |
6142 | } |
6143 | ||
6144 | if (info->intercept == x86_intercept_outs || | |
6145 | info->intercept == x86_intercept_ins) | |
6146 | exit_info |= SVM_IOIO_STR_MASK; | |
6147 | ||
6148 | if (info->rep_prefix) | |
6149 | exit_info |= SVM_IOIO_REP_MASK; | |
6150 | ||
6151 | bytes = min(bytes, 4u); | |
6152 | ||
6153 | exit_info |= bytes << SVM_IOIO_SIZE_SHIFT; | |
6154 | ||
6155 | exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1); | |
6156 | ||
6157 | vmcb->control.exit_info_1 = exit_info; | |
6158 | vmcb->control.exit_info_2 = info->next_rip; | |
6159 | ||
6160 | break; | |
6161 | } | |
cfec82cb JR |
6162 | default: |
6163 | break; | |
6164 | } | |
6165 | ||
f104765b BD |
6166 | /* TODO: Advertise NRIPS to guest hypervisor unconditionally */ |
6167 | if (static_cpu_has(X86_FEATURE_NRIPS)) | |
6168 | vmcb->control.next_rip = info->next_rip; | |
cfec82cb JR |
6169 | vmcb->control.exit_code = icpt_info.exit_code; |
6170 | vmexit = nested_svm_exit_handled(svm); | |
6171 | ||
6172 | ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED | |
6173 | : X86EMUL_CONTINUE; | |
6174 | ||
6175 | out: | |
6176 | return ret; | |
8a76d7f2 JR |
6177 | } |
6178 | ||
95b5a48c | 6179 | static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu) |
a547c6db | 6180 | { |
d7a08882 | 6181 | |
a547c6db YZ |
6182 | } |
6183 | ||
ae97a3b8 RK |
6184 | static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu) |
6185 | { | |
8566ac8b BM |
6186 | if (pause_filter_thresh) |
6187 | shrink_ple_window(vcpu); | |
ae97a3b8 RK |
6188 | } |
6189 | ||
be8ca170 SS |
6190 | static inline void avic_post_state_restore(struct kvm_vcpu *vcpu) |
6191 | { | |
6192 | if (avic_handle_apic_id_update(vcpu) != 0) | |
6193 | return; | |
98d90582 | 6194 | avic_handle_dfr_update(vcpu); |
be8ca170 SS |
6195 | avic_handle_ldr_update(vcpu); |
6196 | } | |
6197 | ||
74f16909 BP |
6198 | static void svm_setup_mce(struct kvm_vcpu *vcpu) |
6199 | { | |
6200 | /* [63:9] are reserved. */ | |
6201 | vcpu->arch.mcg_cap &= 0x1ff; | |
6202 | } | |
6203 | ||
72d7b374 LP |
6204 | static int svm_smi_allowed(struct kvm_vcpu *vcpu) |
6205 | { | |
05cade71 LP |
6206 | struct vcpu_svm *svm = to_svm(vcpu); |
6207 | ||
6208 | /* Per APM Vol.2 15.22.2 "Response to SMI" */ | |
6209 | if (!gif_set(svm)) | |
6210 | return 0; | |
6211 | ||
6212 | if (is_guest_mode(&svm->vcpu) && | |
6213 | svm->nested.intercept & (1ULL << INTERCEPT_SMI)) { | |
6214 | /* TODO: Might need to set exit_info_1 and exit_info_2 here */ | |
6215 | svm->vmcb->control.exit_code = SVM_EXIT_SMI; | |
6216 | svm->nested.exit_required = true; | |
6217 | return 0; | |
6218 | } | |
6219 | ||
72d7b374 LP |
6220 | return 1; |
6221 | } | |
6222 | ||
0234bf88 LP |
6223 | static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) |
6224 | { | |
05cade71 LP |
6225 | struct vcpu_svm *svm = to_svm(vcpu); |
6226 | int ret; | |
6227 | ||
6228 | if (is_guest_mode(vcpu)) { | |
6229 | /* FED8h - SVM Guest */ | |
6230 | put_smstate(u64, smstate, 0x7ed8, 1); | |
6231 | /* FEE0h - SVM Guest VMCB Physical Address */ | |
6232 | put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb); | |
6233 | ||
6234 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; | |
6235 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
6236 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
6237 | ||
6238 | ret = nested_svm_vmexit(svm); | |
6239 | if (ret) | |
6240 | return ret; | |
6241 | } | |
0234bf88 LP |
6242 | return 0; |
6243 | } | |
6244 | ||
ed19321f | 6245 | static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate) |
0234bf88 | 6246 | { |
05cade71 LP |
6247 | struct vcpu_svm *svm = to_svm(vcpu); |
6248 | struct vmcb *nested_vmcb; | |
8c5fbf1a | 6249 | struct kvm_host_map map; |
ed19321f SC |
6250 | u64 guest; |
6251 | u64 vmcb; | |
05cade71 | 6252 | |
ed19321f SC |
6253 | guest = GET_SMSTATE(u64, smstate, 0x7ed8); |
6254 | vmcb = GET_SMSTATE(u64, smstate, 0x7ee0); | |
05cade71 | 6255 | |
ed19321f | 6256 | if (guest) { |
8c5fbf1a | 6257 | if (kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb), &map) == -EINVAL) |
9ec19493 | 6258 | return 1; |
8c5fbf1a KA |
6259 | nested_vmcb = map.hva; |
6260 | enter_svm_guest_mode(svm, vmcb, nested_vmcb, &map); | |
05cade71 | 6261 | } |
9ec19493 | 6262 | return 0; |
0234bf88 LP |
6263 | } |
6264 | ||
cc3d967f LP |
6265 | static int enable_smi_window(struct kvm_vcpu *vcpu) |
6266 | { | |
6267 | struct vcpu_svm *svm = to_svm(vcpu); | |
6268 | ||
6269 | if (!gif_set(svm)) { | |
6270 | if (vgif_enabled(svm)) | |
6271 | set_intercept(svm, INTERCEPT_STGI); | |
6272 | /* STGI will cause a vm exit */ | |
6273 | return 1; | |
6274 | } | |
6275 | return 0; | |
6276 | } | |
6277 | ||
33af3a7e TL |
6278 | static int sev_flush_asids(void) |
6279 | { | |
6280 | int ret, error; | |
6281 | ||
6282 | /* | |
6283 | * DEACTIVATE will clear the WBINVD indicator causing DF_FLUSH to fail, | |
6284 | * so it must be guarded. | |
6285 | */ | |
6286 | down_write(&sev_deactivate_lock); | |
6287 | ||
6288 | wbinvd_on_all_cpus(); | |
6289 | ret = sev_guest_df_flush(&error); | |
6290 | ||
6291 | up_write(&sev_deactivate_lock); | |
6292 | ||
6293 | if (ret) | |
6294 | pr_err("SEV: DF_FLUSH failed, ret=%d, error=%#x\n", ret, error); | |
6295 | ||
6296 | return ret; | |
6297 | } | |
6298 | ||
6299 | /* Must be called with the sev_bitmap_lock held */ | |
6300 | static bool __sev_recycle_asids(void) | |
6301 | { | |
6302 | int pos; | |
6303 | ||
6304 | /* Check if there are any ASIDs to reclaim before performing a flush */ | |
6305 | pos = find_next_bit(sev_reclaim_asid_bitmap, | |
6306 | max_sev_asid, min_sev_asid - 1); | |
6307 | if (pos >= max_sev_asid) | |
6308 | return false; | |
6309 | ||
6310 | if (sev_flush_asids()) | |
6311 | return false; | |
6312 | ||
6313 | bitmap_xor(sev_asid_bitmap, sev_asid_bitmap, sev_reclaim_asid_bitmap, | |
6314 | max_sev_asid); | |
6315 | bitmap_zero(sev_reclaim_asid_bitmap, max_sev_asid); | |
6316 | ||
6317 | return true; | |
6318 | } | |
6319 | ||
1654efcb BS |
6320 | static int sev_asid_new(void) |
6321 | { | |
33af3a7e | 6322 | bool retry = true; |
1654efcb BS |
6323 | int pos; |
6324 | ||
e3b9a9e1 TL |
6325 | mutex_lock(&sev_bitmap_lock); |
6326 | ||
1654efcb BS |
6327 | /* |
6328 | * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid. | |
6329 | */ | |
33af3a7e | 6330 | again: |
1654efcb | 6331 | pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1); |
e3b9a9e1 | 6332 | if (pos >= max_sev_asid) { |
33af3a7e TL |
6333 | if (retry && __sev_recycle_asids()) { |
6334 | retry = false; | |
6335 | goto again; | |
6336 | } | |
e3b9a9e1 | 6337 | mutex_unlock(&sev_bitmap_lock); |
1654efcb | 6338 | return -EBUSY; |
e3b9a9e1 TL |
6339 | } |
6340 | ||
6341 | __set_bit(pos, sev_asid_bitmap); | |
6342 | ||
6343 | mutex_unlock(&sev_bitmap_lock); | |
1654efcb | 6344 | |
1654efcb BS |
6345 | return pos + 1; |
6346 | } | |
6347 | ||
6348 | static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp) | |
6349 | { | |
81811c16 | 6350 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
1654efcb BS |
6351 | int asid, ret; |
6352 | ||
6353 | ret = -EBUSY; | |
3f14a89d DR |
6354 | if (unlikely(sev->active)) |
6355 | return ret; | |
6356 | ||
1654efcb BS |
6357 | asid = sev_asid_new(); |
6358 | if (asid < 0) | |
6359 | return ret; | |
6360 | ||
6361 | ret = sev_platform_init(&argp->error); | |
6362 | if (ret) | |
6363 | goto e_free; | |
6364 | ||
6365 | sev->active = true; | |
6366 | sev->asid = asid; | |
1e80fdc0 | 6367 | INIT_LIST_HEAD(&sev->regions_list); |
1654efcb BS |
6368 | |
6369 | return 0; | |
6370 | ||
6371 | e_free: | |
e3b9a9e1 | 6372 | sev_asid_free(asid); |
1654efcb BS |
6373 | return ret; |
6374 | } | |
6375 | ||
59414c98 BS |
6376 | static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error) |
6377 | { | |
6378 | struct sev_data_activate *data; | |
6379 | int asid = sev_get_asid(kvm); | |
6380 | int ret; | |
6381 | ||
1ec69647 | 6382 | data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT); |
59414c98 BS |
6383 | if (!data) |
6384 | return -ENOMEM; | |
6385 | ||
6386 | /* activate ASID on the given handle */ | |
6387 | data->handle = handle; | |
6388 | data->asid = asid; | |
6389 | ret = sev_guest_activate(data, error); | |
6390 | kfree(data); | |
6391 | ||
6392 | return ret; | |
6393 | } | |
6394 | ||
89c50580 | 6395 | static int __sev_issue_cmd(int fd, int id, void *data, int *error) |
59414c98 BS |
6396 | { |
6397 | struct fd f; | |
6398 | int ret; | |
6399 | ||
6400 | f = fdget(fd); | |
6401 | if (!f.file) | |
6402 | return -EBADF; | |
6403 | ||
6404 | ret = sev_issue_cmd_external_user(f.file, id, data, error); | |
6405 | ||
6406 | fdput(f); | |
6407 | return ret; | |
6408 | } | |
6409 | ||
89c50580 BS |
6410 | static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error) |
6411 | { | |
81811c16 | 6412 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
89c50580 BS |
6413 | |
6414 | return __sev_issue_cmd(sev->fd, id, data, error); | |
6415 | } | |
6416 | ||
59414c98 BS |
6417 | static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp) |
6418 | { | |
81811c16 | 6419 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
59414c98 BS |
6420 | struct sev_data_launch_start *start; |
6421 | struct kvm_sev_launch_start params; | |
6422 | void *dh_blob, *session_blob; | |
6423 | int *error = &argp->error; | |
6424 | int ret; | |
6425 | ||
6426 | if (!sev_guest(kvm)) | |
6427 | return -ENOTTY; | |
6428 | ||
6429 | if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params))) | |
6430 | return -EFAULT; | |
6431 | ||
1ec69647 | 6432 | start = kzalloc(sizeof(*start), GFP_KERNEL_ACCOUNT); |
59414c98 BS |
6433 | if (!start) |
6434 | return -ENOMEM; | |
6435 | ||
6436 | dh_blob = NULL; | |
6437 | if (params.dh_uaddr) { | |
6438 | dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len); | |
6439 | if (IS_ERR(dh_blob)) { | |
6440 | ret = PTR_ERR(dh_blob); | |
6441 | goto e_free; | |
6442 | } | |
6443 | ||
6444 | start->dh_cert_address = __sme_set(__pa(dh_blob)); | |
6445 | start->dh_cert_len = params.dh_len; | |
6446 | } | |
6447 | ||
6448 | session_blob = NULL; | |
6449 | if (params.session_uaddr) { | |
6450 | session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len); | |
6451 | if (IS_ERR(session_blob)) { | |
6452 | ret = PTR_ERR(session_blob); | |
6453 | goto e_free_dh; | |
6454 | } | |
6455 | ||
6456 | start->session_address = __sme_set(__pa(session_blob)); | |
6457 | start->session_len = params.session_len; | |
6458 | } | |
6459 | ||
6460 | start->handle = params.handle; | |
6461 | start->policy = params.policy; | |
6462 | ||
6463 | /* create memory encryption context */ | |
89c50580 | 6464 | ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error); |
59414c98 BS |
6465 | if (ret) |
6466 | goto e_free_session; | |
6467 | ||
6468 | /* Bind ASID to this guest */ | |
6469 | ret = sev_bind_asid(kvm, start->handle, error); | |
6470 | if (ret) | |
6471 | goto e_free_session; | |
6472 | ||
6473 | /* return handle to userspace */ | |
6474 | params.handle = start->handle; | |
6475 | if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params))) { | |
6476 | sev_unbind_asid(kvm, start->handle); | |
6477 | ret = -EFAULT; | |
6478 | goto e_free_session; | |
6479 | } | |
6480 | ||
6481 | sev->handle = start->handle; | |
6482 | sev->fd = argp->sev_fd; | |
6483 | ||
6484 | e_free_session: | |
6485 | kfree(session_blob); | |
6486 | e_free_dh: | |
6487 | kfree(dh_blob); | |
6488 | e_free: | |
6489 | kfree(start); | |
6490 | return ret; | |
6491 | } | |
6492 | ||
ede885ec DR |
6493 | static unsigned long get_num_contig_pages(unsigned long idx, |
6494 | struct page **inpages, unsigned long npages) | |
89c50580 BS |
6495 | { |
6496 | unsigned long paddr, next_paddr; | |
ede885ec | 6497 | unsigned long i = idx + 1, pages = 1; |
89c50580 BS |
6498 | |
6499 | /* find the number of contiguous pages starting from idx */ | |
6500 | paddr = __sme_page_pa(inpages[idx]); | |
6501 | while (i < npages) { | |
6502 | next_paddr = __sme_page_pa(inpages[i++]); | |
6503 | if ((paddr + PAGE_SIZE) == next_paddr) { | |
6504 | pages++; | |
6505 | paddr = next_paddr; | |
6506 | continue; | |
6507 | } | |
6508 | break; | |
6509 | } | |
6510 | ||
6511 | return pages; | |
6512 | } | |
6513 | ||
6514 | static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp) | |
6515 | { | |
ede885ec | 6516 | unsigned long vaddr, vaddr_end, next_vaddr, npages, pages, size, i; |
81811c16 | 6517 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
89c50580 BS |
6518 | struct kvm_sev_launch_update_data params; |
6519 | struct sev_data_launch_update_data *data; | |
6520 | struct page **inpages; | |
ede885ec | 6521 | int ret; |
89c50580 BS |
6522 | |
6523 | if (!sev_guest(kvm)) | |
6524 | return -ENOTTY; | |
6525 | ||
6526 | if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params))) | |
6527 | return -EFAULT; | |
6528 | ||
1ec69647 | 6529 | data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT); |
89c50580 BS |
6530 | if (!data) |
6531 | return -ENOMEM; | |
6532 | ||
6533 | vaddr = params.uaddr; | |
6534 | size = params.len; | |
6535 | vaddr_end = vaddr + size; | |
6536 | ||
6537 | /* Lock the user memory. */ | |
6538 | inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1); | |
6539 | if (!inpages) { | |
6540 | ret = -ENOMEM; | |
6541 | goto e_free; | |
6542 | } | |
6543 | ||
6544 | /* | |
6545 | * The LAUNCH_UPDATE command will perform in-place encryption of the | |
6546 | * memory content (i.e it will write the same memory region with C=1). | |
6547 | * It's possible that the cache may contain the data with C=0, i.e., | |
6548 | * unencrypted so invalidate it first. | |
6549 | */ | |
6550 | sev_clflush_pages(inpages, npages); | |
6551 | ||
6552 | for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) { | |
6553 | int offset, len; | |
6554 | ||
6555 | /* | |
6556 | * If the user buffer is not page-aligned, calculate the offset | |
6557 | * within the page. | |
6558 | */ | |
6559 | offset = vaddr & (PAGE_SIZE - 1); | |
6560 | ||
6561 | /* Calculate the number of pages that can be encrypted in one go. */ | |
6562 | pages = get_num_contig_pages(i, inpages, npages); | |
6563 | ||
6564 | len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size); | |
6565 | ||
6566 | data->handle = sev->handle; | |
6567 | data->len = len; | |
6568 | data->address = __sme_page_pa(inpages[i]) + offset; | |
6569 | ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error); | |
6570 | if (ret) | |
6571 | goto e_unpin; | |
6572 | ||
6573 | size -= len; | |
6574 | next_vaddr = vaddr + len; | |
6575 | } | |
6576 | ||
6577 | e_unpin: | |
6578 | /* content of memory is updated, mark pages dirty */ | |
6579 | for (i = 0; i < npages; i++) { | |
6580 | set_page_dirty_lock(inpages[i]); | |
6581 | mark_page_accessed(inpages[i]); | |
6582 | } | |
6583 | /* unlock the user pages */ | |
6584 | sev_unpin_memory(kvm, inpages, npages); | |
6585 | e_free: | |
6586 | kfree(data); | |
6587 | return ret; | |
6588 | } | |
6589 | ||
0d0736f7 BS |
6590 | static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp) |
6591 | { | |
3e233385 | 6592 | void __user *measure = (void __user *)(uintptr_t)argp->data; |
81811c16 | 6593 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
0d0736f7 BS |
6594 | struct sev_data_launch_measure *data; |
6595 | struct kvm_sev_launch_measure params; | |
3e233385 | 6596 | void __user *p = NULL; |
0d0736f7 BS |
6597 | void *blob = NULL; |
6598 | int ret; | |
6599 | ||
6600 | if (!sev_guest(kvm)) | |
6601 | return -ENOTTY; | |
6602 | ||
3e233385 | 6603 | if (copy_from_user(¶ms, measure, sizeof(params))) |
0d0736f7 BS |
6604 | return -EFAULT; |
6605 | ||
1ec69647 | 6606 | data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT); |
0d0736f7 BS |
6607 | if (!data) |
6608 | return -ENOMEM; | |
6609 | ||
6610 | /* User wants to query the blob length */ | |
6611 | if (!params.len) | |
6612 | goto cmd; | |
6613 | ||
3e233385 BS |
6614 | p = (void __user *)(uintptr_t)params.uaddr; |
6615 | if (p) { | |
0d0736f7 BS |
6616 | if (params.len > SEV_FW_BLOB_MAX_SIZE) { |
6617 | ret = -EINVAL; | |
6618 | goto e_free; | |
6619 | } | |
6620 | ||
0d0736f7 BS |
6621 | ret = -ENOMEM; |
6622 | blob = kmalloc(params.len, GFP_KERNEL); | |
6623 | if (!blob) | |
6624 | goto e_free; | |
6625 | ||
6626 | data->address = __psp_pa(blob); | |
6627 | data->len = params.len; | |
6628 | } | |
6629 | ||
6630 | cmd: | |
6631 | data->handle = sev->handle; | |
6632 | ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error); | |
6633 | ||
6634 | /* | |
6635 | * If we query the session length, FW responded with expected data. | |
6636 | */ | |
6637 | if (!params.len) | |
6638 | goto done; | |
6639 | ||
6640 | if (ret) | |
6641 | goto e_free_blob; | |
6642 | ||
6643 | if (blob) { | |
3e233385 | 6644 | if (copy_to_user(p, blob, params.len)) |
0d0736f7 BS |
6645 | ret = -EFAULT; |
6646 | } | |
6647 | ||
6648 | done: | |
6649 | params.len = data->len; | |
3e233385 | 6650 | if (copy_to_user(measure, ¶ms, sizeof(params))) |
0d0736f7 BS |
6651 | ret = -EFAULT; |
6652 | e_free_blob: | |
6653 | kfree(blob); | |
6654 | e_free: | |
6655 | kfree(data); | |
6656 | return ret; | |
6657 | } | |
6658 | ||
5bdb0e2f BS |
6659 | static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp) |
6660 | { | |
81811c16 | 6661 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
5bdb0e2f BS |
6662 | struct sev_data_launch_finish *data; |
6663 | int ret; | |
6664 | ||
6665 | if (!sev_guest(kvm)) | |
6666 | return -ENOTTY; | |
6667 | ||
1ec69647 | 6668 | data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT); |
5bdb0e2f BS |
6669 | if (!data) |
6670 | return -ENOMEM; | |
6671 | ||
6672 | data->handle = sev->handle; | |
6673 | ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error); | |
6674 | ||
6675 | kfree(data); | |
6676 | return ret; | |
6677 | } | |
6678 | ||
255d9e75 BS |
6679 | static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp) |
6680 | { | |
81811c16 | 6681 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
255d9e75 BS |
6682 | struct kvm_sev_guest_status params; |
6683 | struct sev_data_guest_status *data; | |
6684 | int ret; | |
6685 | ||
6686 | if (!sev_guest(kvm)) | |
6687 | return -ENOTTY; | |
6688 | ||
1ec69647 | 6689 | data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT); |
255d9e75 BS |
6690 | if (!data) |
6691 | return -ENOMEM; | |
6692 | ||
6693 | data->handle = sev->handle; | |
6694 | ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error); | |
6695 | if (ret) | |
6696 | goto e_free; | |
6697 | ||
6698 | params.policy = data->policy; | |
6699 | params.state = data->state; | |
6700 | params.handle = data->handle; | |
6701 | ||
6702 | if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params))) | |
6703 | ret = -EFAULT; | |
6704 | e_free: | |
6705 | kfree(data); | |
6706 | return ret; | |
6707 | } | |
6708 | ||
24f41fb2 BS |
6709 | static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src, |
6710 | unsigned long dst, int size, | |
6711 | int *error, bool enc) | |
6712 | { | |
81811c16 | 6713 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
24f41fb2 BS |
6714 | struct sev_data_dbg *data; |
6715 | int ret; | |
6716 | ||
1ec69647 | 6717 | data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT); |
24f41fb2 BS |
6718 | if (!data) |
6719 | return -ENOMEM; | |
6720 | ||
6721 | data->handle = sev->handle; | |
6722 | data->dst_addr = dst; | |
6723 | data->src_addr = src; | |
6724 | data->len = size; | |
6725 | ||
6726 | ret = sev_issue_cmd(kvm, | |
6727 | enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT, | |
6728 | data, error); | |
6729 | kfree(data); | |
6730 | return ret; | |
6731 | } | |
6732 | ||
6733 | static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr, | |
6734 | unsigned long dst_paddr, int sz, int *err) | |
6735 | { | |
6736 | int offset; | |
6737 | ||
6738 | /* | |
6739 | * Its safe to read more than we are asked, caller should ensure that | |
6740 | * destination has enough space. | |
6741 | */ | |
6742 | src_paddr = round_down(src_paddr, 16); | |
6743 | offset = src_paddr & 15; | |
6744 | sz = round_up(sz + offset, 16); | |
6745 | ||
6746 | return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false); | |
6747 | } | |
6748 | ||
6749 | static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr, | |
6750 | unsigned long __user dst_uaddr, | |
6751 | unsigned long dst_paddr, | |
6752 | int size, int *err) | |
6753 | { | |
6754 | struct page *tpage = NULL; | |
6755 | int ret, offset; | |
6756 | ||
6757 | /* if inputs are not 16-byte then use intermediate buffer */ | |
6758 | if (!IS_ALIGNED(dst_paddr, 16) || | |
6759 | !IS_ALIGNED(paddr, 16) || | |
6760 | !IS_ALIGNED(size, 16)) { | |
6761 | tpage = (void *)alloc_page(GFP_KERNEL); | |
6762 | if (!tpage) | |
6763 | return -ENOMEM; | |
6764 | ||
6765 | dst_paddr = __sme_page_pa(tpage); | |
6766 | } | |
6767 | ||
6768 | ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err); | |
6769 | if (ret) | |
6770 | goto e_free; | |
6771 | ||
6772 | if (tpage) { | |
6773 | offset = paddr & 15; | |
6774 | if (copy_to_user((void __user *)(uintptr_t)dst_uaddr, | |
6775 | page_address(tpage) + offset, size)) | |
6776 | ret = -EFAULT; | |
6777 | } | |
6778 | ||
6779 | e_free: | |
6780 | if (tpage) | |
6781 | __free_page(tpage); | |
6782 | ||
6783 | return ret; | |
6784 | } | |
6785 | ||
7d1594f5 BS |
6786 | static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr, |
6787 | unsigned long __user vaddr, | |
6788 | unsigned long dst_paddr, | |
6789 | unsigned long __user dst_vaddr, | |
6790 | int size, int *error) | |
6791 | { | |
6792 | struct page *src_tpage = NULL; | |
6793 | struct page *dst_tpage = NULL; | |
6794 | int ret, len = size; | |
6795 | ||
6796 | /* If source buffer is not aligned then use an intermediate buffer */ | |
6797 | if (!IS_ALIGNED(vaddr, 16)) { | |
6798 | src_tpage = alloc_page(GFP_KERNEL); | |
6799 | if (!src_tpage) | |
6800 | return -ENOMEM; | |
6801 | ||
6802 | if (copy_from_user(page_address(src_tpage), | |
6803 | (void __user *)(uintptr_t)vaddr, size)) { | |
6804 | __free_page(src_tpage); | |
6805 | return -EFAULT; | |
6806 | } | |
6807 | ||
6808 | paddr = __sme_page_pa(src_tpage); | |
6809 | } | |
6810 | ||
6811 | /* | |
6812 | * If destination buffer or length is not aligned then do read-modify-write: | |
6813 | * - decrypt destination in an intermediate buffer | |
6814 | * - copy the source buffer in an intermediate buffer | |
6815 | * - use the intermediate buffer as source buffer | |
6816 | */ | |
6817 | if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) { | |
6818 | int dst_offset; | |
6819 | ||
6820 | dst_tpage = alloc_page(GFP_KERNEL); | |
6821 | if (!dst_tpage) { | |
6822 | ret = -ENOMEM; | |
6823 | goto e_free; | |
6824 | } | |
6825 | ||
6826 | ret = __sev_dbg_decrypt(kvm, dst_paddr, | |
6827 | __sme_page_pa(dst_tpage), size, error); | |
6828 | if (ret) | |
6829 | goto e_free; | |
6830 | ||
6831 | /* | |
6832 | * If source is kernel buffer then use memcpy() otherwise | |
6833 | * copy_from_user(). | |
6834 | */ | |
6835 | dst_offset = dst_paddr & 15; | |
6836 | ||
6837 | if (src_tpage) | |
6838 | memcpy(page_address(dst_tpage) + dst_offset, | |
6839 | page_address(src_tpage), size); | |
6840 | else { | |
6841 | if (copy_from_user(page_address(dst_tpage) + dst_offset, | |
6842 | (void __user *)(uintptr_t)vaddr, size)) { | |
6843 | ret = -EFAULT; | |
6844 | goto e_free; | |
6845 | } | |
6846 | } | |
6847 | ||
6848 | paddr = __sme_page_pa(dst_tpage); | |
6849 | dst_paddr = round_down(dst_paddr, 16); | |
6850 | len = round_up(size, 16); | |
6851 | } | |
6852 | ||
6853 | ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true); | |
6854 | ||
6855 | e_free: | |
6856 | if (src_tpage) | |
6857 | __free_page(src_tpage); | |
6858 | if (dst_tpage) | |
6859 | __free_page(dst_tpage); | |
6860 | return ret; | |
6861 | } | |
6862 | ||
24f41fb2 BS |
6863 | static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec) |
6864 | { | |
6865 | unsigned long vaddr, vaddr_end, next_vaddr; | |
0186ec82 | 6866 | unsigned long dst_vaddr; |
24f41fb2 BS |
6867 | struct page **src_p, **dst_p; |
6868 | struct kvm_sev_dbg debug; | |
6869 | unsigned long n; | |
b86bc285 DR |
6870 | unsigned int size; |
6871 | int ret; | |
24f41fb2 BS |
6872 | |
6873 | if (!sev_guest(kvm)) | |
6874 | return -ENOTTY; | |
6875 | ||
6876 | if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug))) | |
6877 | return -EFAULT; | |
6878 | ||
b86bc285 DR |
6879 | if (!debug.len || debug.src_uaddr + debug.len < debug.src_uaddr) |
6880 | return -EINVAL; | |
6881 | if (!debug.dst_uaddr) | |
6882 | return -EINVAL; | |
6883 | ||
24f41fb2 BS |
6884 | vaddr = debug.src_uaddr; |
6885 | size = debug.len; | |
6886 | vaddr_end = vaddr + size; | |
6887 | dst_vaddr = debug.dst_uaddr; | |
24f41fb2 BS |
6888 | |
6889 | for (; vaddr < vaddr_end; vaddr = next_vaddr) { | |
6890 | int len, s_off, d_off; | |
6891 | ||
6892 | /* lock userspace source and destination page */ | |
6893 | src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0); | |
6894 | if (!src_p) | |
6895 | return -EFAULT; | |
6896 | ||
6897 | dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1); | |
6898 | if (!dst_p) { | |
6899 | sev_unpin_memory(kvm, src_p, n); | |
6900 | return -EFAULT; | |
6901 | } | |
6902 | ||
6903 | /* | |
6904 | * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the | |
6905 | * memory content (i.e it will write the same memory region with C=1). | |
6906 | * It's possible that the cache may contain the data with C=0, i.e., | |
6907 | * unencrypted so invalidate it first. | |
6908 | */ | |
6909 | sev_clflush_pages(src_p, 1); | |
6910 | sev_clflush_pages(dst_p, 1); | |
6911 | ||
6912 | /* | |
6913 | * Since user buffer may not be page aligned, calculate the | |
6914 | * offset within the page. | |
6915 | */ | |
6916 | s_off = vaddr & ~PAGE_MASK; | |
6917 | d_off = dst_vaddr & ~PAGE_MASK; | |
6918 | len = min_t(size_t, (PAGE_SIZE - s_off), size); | |
6919 | ||
7d1594f5 BS |
6920 | if (dec) |
6921 | ret = __sev_dbg_decrypt_user(kvm, | |
6922 | __sme_page_pa(src_p[0]) + s_off, | |
6923 | dst_vaddr, | |
6924 | __sme_page_pa(dst_p[0]) + d_off, | |
6925 | len, &argp->error); | |
6926 | else | |
6927 | ret = __sev_dbg_encrypt_user(kvm, | |
6928 | __sme_page_pa(src_p[0]) + s_off, | |
6929 | vaddr, | |
6930 | __sme_page_pa(dst_p[0]) + d_off, | |
6931 | dst_vaddr, | |
6932 | len, &argp->error); | |
24f41fb2 | 6933 | |
b86bc285 DR |
6934 | sev_unpin_memory(kvm, src_p, n); |
6935 | sev_unpin_memory(kvm, dst_p, n); | |
24f41fb2 BS |
6936 | |
6937 | if (ret) | |
6938 | goto err; | |
6939 | ||
6940 | next_vaddr = vaddr + len; | |
6941 | dst_vaddr = dst_vaddr + len; | |
6942 | size -= len; | |
6943 | } | |
6944 | err: | |
6945 | return ret; | |
6946 | } | |
6947 | ||
9f5b5b95 BS |
6948 | static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp) |
6949 | { | |
81811c16 | 6950 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
9f5b5b95 BS |
6951 | struct sev_data_launch_secret *data; |
6952 | struct kvm_sev_launch_secret params; | |
6953 | struct page **pages; | |
6954 | void *blob, *hdr; | |
6955 | unsigned long n; | |
9c5e0afa | 6956 | int ret, offset; |
9f5b5b95 BS |
6957 | |
6958 | if (!sev_guest(kvm)) | |
6959 | return -ENOTTY; | |
6960 | ||
6961 | if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params))) | |
6962 | return -EFAULT; | |
6963 | ||
6964 | pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1); | |
6965 | if (!pages) | |
6966 | return -ENOMEM; | |
6967 | ||
6968 | /* | |
6969 | * The secret must be copied into contiguous memory region, lets verify | |
6970 | * that userspace memory pages are contiguous before we issue command. | |
6971 | */ | |
6972 | if (get_num_contig_pages(0, pages, n) != n) { | |
6973 | ret = -EINVAL; | |
6974 | goto e_unpin_memory; | |
6975 | } | |
6976 | ||
6977 | ret = -ENOMEM; | |
1ec69647 | 6978 | data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT); |
9f5b5b95 BS |
6979 | if (!data) |
6980 | goto e_unpin_memory; | |
6981 | ||
9c5e0afa BS |
6982 | offset = params.guest_uaddr & (PAGE_SIZE - 1); |
6983 | data->guest_address = __sme_page_pa(pages[0]) + offset; | |
6984 | data->guest_len = params.guest_len; | |
6985 | ||
9f5b5b95 BS |
6986 | blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len); |
6987 | if (IS_ERR(blob)) { | |
6988 | ret = PTR_ERR(blob); | |
6989 | goto e_free; | |
6990 | } | |
6991 | ||
6992 | data->trans_address = __psp_pa(blob); | |
6993 | data->trans_len = params.trans_len; | |
6994 | ||
6995 | hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len); | |
6996 | if (IS_ERR(hdr)) { | |
6997 | ret = PTR_ERR(hdr); | |
6998 | goto e_free_blob; | |
6999 | } | |
9c5e0afa BS |
7000 | data->hdr_address = __psp_pa(hdr); |
7001 | data->hdr_len = params.hdr_len; | |
9f5b5b95 BS |
7002 | |
7003 | data->handle = sev->handle; | |
7004 | ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error); | |
7005 | ||
7006 | kfree(hdr); | |
7007 | ||
7008 | e_free_blob: | |
7009 | kfree(blob); | |
7010 | e_free: | |
7011 | kfree(data); | |
7012 | e_unpin_memory: | |
7013 | sev_unpin_memory(kvm, pages, n); | |
7014 | return ret; | |
7015 | } | |
7016 | ||
1654efcb BS |
7017 | static int svm_mem_enc_op(struct kvm *kvm, void __user *argp) |
7018 | { | |
7019 | struct kvm_sev_cmd sev_cmd; | |
7020 | int r; | |
7021 | ||
7022 | if (!svm_sev_enabled()) | |
7023 | return -ENOTTY; | |
7024 | ||
7025 | if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd))) | |
7026 | return -EFAULT; | |
7027 | ||
7028 | mutex_lock(&kvm->lock); | |
7029 | ||
7030 | switch (sev_cmd.id) { | |
7031 | case KVM_SEV_INIT: | |
7032 | r = sev_guest_init(kvm, &sev_cmd); | |
7033 | break; | |
59414c98 BS |
7034 | case KVM_SEV_LAUNCH_START: |
7035 | r = sev_launch_start(kvm, &sev_cmd); | |
7036 | break; | |
89c50580 BS |
7037 | case KVM_SEV_LAUNCH_UPDATE_DATA: |
7038 | r = sev_launch_update_data(kvm, &sev_cmd); | |
7039 | break; | |
0d0736f7 BS |
7040 | case KVM_SEV_LAUNCH_MEASURE: |
7041 | r = sev_launch_measure(kvm, &sev_cmd); | |
7042 | break; | |
5bdb0e2f BS |
7043 | case KVM_SEV_LAUNCH_FINISH: |
7044 | r = sev_launch_finish(kvm, &sev_cmd); | |
7045 | break; | |
255d9e75 BS |
7046 | case KVM_SEV_GUEST_STATUS: |
7047 | r = sev_guest_status(kvm, &sev_cmd); | |
7048 | break; | |
24f41fb2 BS |
7049 | case KVM_SEV_DBG_DECRYPT: |
7050 | r = sev_dbg_crypt(kvm, &sev_cmd, true); | |
7051 | break; | |
7d1594f5 BS |
7052 | case KVM_SEV_DBG_ENCRYPT: |
7053 | r = sev_dbg_crypt(kvm, &sev_cmd, false); | |
7054 | break; | |
9f5b5b95 BS |
7055 | case KVM_SEV_LAUNCH_SECRET: |
7056 | r = sev_launch_secret(kvm, &sev_cmd); | |
7057 | break; | |
1654efcb BS |
7058 | default: |
7059 | r = -EINVAL; | |
7060 | goto out; | |
7061 | } | |
7062 | ||
7063 | if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd))) | |
7064 | r = -EFAULT; | |
7065 | ||
7066 | out: | |
7067 | mutex_unlock(&kvm->lock); | |
7068 | return r; | |
7069 | } | |
7070 | ||
1e80fdc0 BS |
7071 | static int svm_register_enc_region(struct kvm *kvm, |
7072 | struct kvm_enc_region *range) | |
7073 | { | |
81811c16 | 7074 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
1e80fdc0 BS |
7075 | struct enc_region *region; |
7076 | int ret = 0; | |
7077 | ||
7078 | if (!sev_guest(kvm)) | |
7079 | return -ENOTTY; | |
7080 | ||
86bf20cb DC |
7081 | if (range->addr > ULONG_MAX || range->size > ULONG_MAX) |
7082 | return -EINVAL; | |
7083 | ||
1ec69647 | 7084 | region = kzalloc(sizeof(*region), GFP_KERNEL_ACCOUNT); |
1e80fdc0 BS |
7085 | if (!region) |
7086 | return -ENOMEM; | |
7087 | ||
7088 | region->pages = sev_pin_memory(kvm, range->addr, range->size, ®ion->npages, 1); | |
7089 | if (!region->pages) { | |
7090 | ret = -ENOMEM; | |
7091 | goto e_free; | |
7092 | } | |
7093 | ||
7094 | /* | |
7095 | * The guest may change the memory encryption attribute from C=0 -> C=1 | |
7096 | * or vice versa for this memory range. Lets make sure caches are | |
7097 | * flushed to ensure that guest data gets written into memory with | |
7098 | * correct C-bit. | |
7099 | */ | |
7100 | sev_clflush_pages(region->pages, region->npages); | |
7101 | ||
7102 | region->uaddr = range->addr; | |
7103 | region->size = range->size; | |
7104 | ||
7105 | mutex_lock(&kvm->lock); | |
7106 | list_add_tail(®ion->list, &sev->regions_list); | |
7107 | mutex_unlock(&kvm->lock); | |
7108 | ||
7109 | return ret; | |
7110 | ||
7111 | e_free: | |
7112 | kfree(region); | |
7113 | return ret; | |
7114 | } | |
7115 | ||
7116 | static struct enc_region * | |
7117 | find_enc_region(struct kvm *kvm, struct kvm_enc_region *range) | |
7118 | { | |
81811c16 | 7119 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
1e80fdc0 BS |
7120 | struct list_head *head = &sev->regions_list; |
7121 | struct enc_region *i; | |
7122 | ||
7123 | list_for_each_entry(i, head, list) { | |
7124 | if (i->uaddr == range->addr && | |
7125 | i->size == range->size) | |
7126 | return i; | |
7127 | } | |
7128 | ||
7129 | return NULL; | |
7130 | } | |
7131 | ||
7132 | ||
7133 | static int svm_unregister_enc_region(struct kvm *kvm, | |
7134 | struct kvm_enc_region *range) | |
7135 | { | |
7136 | struct enc_region *region; | |
7137 | int ret; | |
7138 | ||
7139 | mutex_lock(&kvm->lock); | |
7140 | ||
7141 | if (!sev_guest(kvm)) { | |
7142 | ret = -ENOTTY; | |
7143 | goto failed; | |
7144 | } | |
7145 | ||
7146 | region = find_enc_region(kvm, range); | |
7147 | if (!region) { | |
7148 | ret = -EINVAL; | |
7149 | goto failed; | |
7150 | } | |
7151 | ||
7152 | __unregister_enc_region_locked(kvm, region); | |
7153 | ||
7154 | mutex_unlock(&kvm->lock); | |
7155 | return 0; | |
7156 | ||
7157 | failed: | |
7158 | mutex_unlock(&kvm->lock); | |
7159 | return ret; | |
7160 | } | |
7161 | ||
05d5a486 SB |
7162 | static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu) |
7163 | { | |
118154bd LA |
7164 | unsigned long cr4 = kvm_read_cr4(vcpu); |
7165 | bool smep = cr4 & X86_CR4_SMEP; | |
7166 | bool smap = cr4 & X86_CR4_SMAP; | |
7167 | bool is_user = svm_get_cpl(vcpu) == 3; | |
05d5a486 SB |
7168 | |
7169 | /* | |
118154bd LA |
7170 | * Detect and workaround Errata 1096 Fam_17h_00_0Fh. |
7171 | * | |
7172 | * Errata: | |
7173 | * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is | |
7174 | * possible that CPU microcode implementing DecodeAssist will fail | |
7175 | * to read bytes of instruction which caused #NPF. In this case, | |
7176 | * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly | |
7177 | * return 0 instead of the correct guest instruction bytes. | |
7178 | * | |
7179 | * This happens because CPU microcode reading instruction bytes | |
7180 | * uses a special opcode which attempts to read data using CPL=0 | |
7181 | * priviledges. The microcode reads CS:RIP and if it hits a SMAP | |
7182 | * fault, it gives up and returns no instruction bytes. | |
7183 | * | |
7184 | * Detection: | |
7185 | * We reach here in case CPU supports DecodeAssist, raised #NPF and | |
7186 | * returned 0 in GuestIntrBytes field of the VMCB. | |
7187 | * First, errata can only be triggered in case vCPU CR4.SMAP=1. | |
7188 | * Second, if vCPU CR4.SMEP=1, errata could only be triggered | |
7189 | * in case vCPU CPL==3 (Because otherwise guest would have triggered | |
7190 | * a SMEP fault instead of #NPF). | |
7191 | * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL. | |
7192 | * As most guests enable SMAP if they have also enabled SMEP, use above | |
7193 | * logic in order to attempt minimize false-positive of detecting errata | |
7194 | * while still preserving all cases semantic correctness. | |
7195 | * | |
7196 | * Workaround: | |
7197 | * To determine what instruction the guest was executing, the hypervisor | |
7198 | * will have to decode the instruction at the instruction pointer. | |
05d5a486 SB |
7199 | * |
7200 | * In non SEV guest, hypervisor will be able to read the guest | |
7201 | * memory to decode the instruction pointer when insn_len is zero | |
7202 | * so we return true to indicate that decoding is possible. | |
7203 | * | |
7204 | * But in the SEV guest, the guest memory is encrypted with the | |
7205 | * guest specific key and hypervisor will not be able to decode the | |
7206 | * instruction pointer so we will not able to workaround it. Lets | |
7207 | * print the error and request to kill the guest. | |
7208 | */ | |
118154bd | 7209 | if (smap && (!smep || is_user)) { |
05d5a486 SB |
7210 | if (!sev_guest(vcpu->kvm)) |
7211 | return true; | |
7212 | ||
118154bd | 7213 | pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n"); |
05d5a486 SB |
7214 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
7215 | } | |
7216 | ||
7217 | return false; | |
7218 | } | |
7219 | ||
4b9852f4 LA |
7220 | static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu) |
7221 | { | |
7222 | struct vcpu_svm *svm = to_svm(vcpu); | |
7223 | ||
7224 | /* | |
7225 | * TODO: Last condition latch INIT signals on vCPU when | |
7226 | * vCPU is in guest-mode and vmcb12 defines intercept on INIT. | |
7227 | * To properly emulate the INIT intercept, SVM should implement | |
7228 | * kvm_x86_ops->check_nested_events() and call nested_svm_vmexit() | |
7229 | * there if an INIT signal is pending. | |
7230 | */ | |
7231 | return !gif_set(svm) || | |
7232 | (svm->vmcb->control.intercept & (1ULL << INTERCEPT_INIT)); | |
7233 | } | |
7234 | ||
404f6aac | 7235 | static struct kvm_x86_ops svm_x86_ops __ro_after_init = { |
6aa8b732 AK |
7236 | .cpu_has_kvm_support = has_svm, |
7237 | .disabled_by_bios = is_disabled, | |
7238 | .hardware_setup = svm_hardware_setup, | |
7239 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 7240 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
7241 | .hardware_enable = svm_hardware_enable, |
7242 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 7243 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
bc226f07 | 7244 | .has_emulated_msr = svm_has_emulated_msr, |
6aa8b732 AK |
7245 | |
7246 | .vcpu_create = svm_create_vcpu, | |
7247 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 7248 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 7249 | |
434a1e94 SC |
7250 | .vm_alloc = svm_vm_alloc, |
7251 | .vm_free = svm_vm_free, | |
44a95dae | 7252 | .vm_init = avic_vm_init, |
1654efcb | 7253 | .vm_destroy = svm_vm_destroy, |
44a95dae | 7254 | |
04d2cc77 | 7255 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
7256 | .vcpu_load = svm_vcpu_load, |
7257 | .vcpu_put = svm_vcpu_put, | |
8221c137 SS |
7258 | .vcpu_blocking = svm_vcpu_blocking, |
7259 | .vcpu_unblocking = svm_vcpu_unblocking, | |
6aa8b732 | 7260 | |
a96036b8 | 7261 | .update_bp_intercept = update_bp_intercept, |
801e459a | 7262 | .get_msr_feature = svm_get_msr_feature, |
6aa8b732 AK |
7263 | .get_msr = svm_get_msr, |
7264 | .set_msr = svm_set_msr, | |
7265 | .get_segment_base = svm_get_segment_base, | |
7266 | .get_segment = svm_get_segment, | |
7267 | .set_segment = svm_set_segment, | |
2e4d2653 | 7268 | .get_cpl = svm_get_cpl, |
1747fb71 | 7269 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 7270 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
25c4c276 | 7271 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 7272 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
7273 | .set_cr3 = svm_set_cr3, |
7274 | .set_cr4 = svm_set_cr4, | |
7275 | .set_efer = svm_set_efer, | |
7276 | .get_idt = svm_get_idt, | |
7277 | .set_idt = svm_set_idt, | |
7278 | .get_gdt = svm_get_gdt, | |
7279 | .set_gdt = svm_set_gdt, | |
73aaf249 JK |
7280 | .get_dr6 = svm_get_dr6, |
7281 | .set_dr6 = svm_set_dr6, | |
020df079 | 7282 | .set_dr7 = svm_set_dr7, |
facb0139 | 7283 | .sync_dirty_debug_regs = svm_sync_dirty_debug_regs, |
6de4f3ad | 7284 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
7285 | .get_rflags = svm_get_rflags, |
7286 | .set_rflags = svm_set_rflags, | |
be94f6b7 | 7287 | |
6aa8b732 | 7288 | .tlb_flush = svm_flush_tlb, |
faff8758 | 7289 | .tlb_flush_gva = svm_flush_tlb_gva, |
6aa8b732 | 7290 | |
6aa8b732 | 7291 | .run = svm_vcpu_run, |
04d2cc77 | 7292 | .handle_exit = handle_exit, |
6aa8b732 | 7293 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
7294 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
7295 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 7296 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 7297 | .set_irq = svm_set_irq, |
95ba8273 | 7298 | .set_nmi = svm_inject_nmi, |
298101da | 7299 | .queue_exception = svm_queue_exception, |
b463a6f7 | 7300 | .cancel_injection = svm_cancel_injection, |
78646121 | 7301 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 7302 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
7303 | .get_nmi_mask = svm_get_nmi_mask, |
7304 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
7305 | .enable_nmi_window = enable_nmi_window, |
7306 | .enable_irq_window = enable_irq_window, | |
7307 | .update_cr8_intercept = update_cr8_intercept, | |
8d860bbe | 7308 | .set_virtual_apic_mode = svm_set_virtual_apic_mode, |
d62caabb AS |
7309 | .get_enable_apicv = svm_get_enable_apicv, |
7310 | .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl, | |
c7c9c56c | 7311 | .load_eoi_exitmap = svm_load_eoi_exitmap, |
44a95dae SS |
7312 | .hwapic_irr_update = svm_hwapic_irr_update, |
7313 | .hwapic_isr_update = svm_hwapic_isr_update, | |
fa59cc00 | 7314 | .sync_pir_to_irr = kvm_lapic_find_highest_irr, |
be8ca170 | 7315 | .apicv_post_state_restore = avic_post_state_restore, |
cbc94022 IE |
7316 | |
7317 | .set_tss_addr = svm_set_tss_addr, | |
2ac52ab8 | 7318 | .set_identity_map_addr = svm_set_identity_map_addr, |
67253af5 | 7319 | .get_tdp_level = get_npt_level, |
4b12f0de | 7320 | .get_mt_mask = svm_get_mt_mask, |
229456fc | 7321 | |
586f9607 | 7322 | .get_exit_info = svm_get_exit_info, |
586f9607 | 7323 | |
17cc3935 | 7324 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
7325 | |
7326 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
7327 | |
7328 | .rdtscp_supported = svm_rdtscp_supported, | |
ad756a16 | 7329 | .invpcid_supported = svm_invpcid_supported, |
93c4adc7 | 7330 | .mpx_supported = svm_mpx_supported, |
55412b2e | 7331 | .xsaves_supported = svm_xsaves_supported, |
66336cab | 7332 | .umip_emulated = svm_umip_emulated, |
86f5201d | 7333 | .pt_supported = svm_pt_supported, |
d4330ef2 JR |
7334 | |
7335 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
7336 | |
7337 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
99e3e30a | 7338 | |
e79f245d | 7339 | .read_l1_tsc_offset = svm_read_l1_tsc_offset, |
326e7425 | 7340 | .write_l1_tsc_offset = svm_write_l1_tsc_offset, |
1c97f0a0 JR |
7341 | |
7342 | .set_tdp_cr3 = set_tdp_cr3, | |
8a76d7f2 JR |
7343 | |
7344 | .check_intercept = svm_check_intercept, | |
95b5a48c | 7345 | .handle_exit_irqoff = svm_handle_exit_irqoff, |
ae97a3b8 | 7346 | |
d264ee0c SC |
7347 | .request_immediate_exit = __kvm_request_immediate_exit, |
7348 | ||
ae97a3b8 | 7349 | .sched_in = svm_sched_in, |
25462f7f WH |
7350 | |
7351 | .pmu_ops = &amd_pmu_ops, | |
340d3bc3 | 7352 | .deliver_posted_interrupt = svm_deliver_avic_intr, |
17e433b5 | 7353 | .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt, |
411b44ba | 7354 | .update_pi_irte = svm_update_pi_irte, |
74f16909 | 7355 | .setup_mce = svm_setup_mce, |
0234bf88 | 7356 | |
72d7b374 | 7357 | .smi_allowed = svm_smi_allowed, |
0234bf88 LP |
7358 | .pre_enter_smm = svm_pre_enter_smm, |
7359 | .pre_leave_smm = svm_pre_leave_smm, | |
cc3d967f | 7360 | .enable_smi_window = enable_smi_window, |
1654efcb BS |
7361 | |
7362 | .mem_enc_op = svm_mem_enc_op, | |
1e80fdc0 BS |
7363 | .mem_enc_reg_region = svm_register_enc_region, |
7364 | .mem_enc_unreg_region = svm_unregister_enc_region, | |
57b119da | 7365 | |
956e255c | 7366 | .nested_enable_evmcs = NULL, |
ea152987 | 7367 | .nested_get_evmcs_version = NULL, |
05d5a486 SB |
7368 | |
7369 | .need_emulation_on_page_fault = svm_need_emulation_on_page_fault, | |
4b9852f4 LA |
7370 | |
7371 | .apic_init_signal_blocked = svm_apic_init_signal_blocked, | |
6aa8b732 AK |
7372 | }; |
7373 | ||
7374 | static int __init svm_init(void) | |
7375 | { | |
cb498ea2 | 7376 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 7377 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
7378 | } |
7379 | ||
7380 | static void __exit svm_exit(void) | |
7381 | { | |
cb498ea2 | 7382 | kvm_exit(); |
6aa8b732 AK |
7383 | } |
7384 | ||
7385 | module_init(svm_init) | |
7386 | module_exit(svm_exit) |