Commit | Line | Data |
---|---|---|
6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 7 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
8 | * |
9 | * Authors: | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
edf88417 AK |
17 | #include <linux/kvm_host.h> |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
5fdbf976 | 21 | #include "kvm_cache_regs.h" |
fe4c7b19 | 22 | #include "x86.h" |
e495606d | 23 | |
6aa8b732 | 24 | #include <linux/module.h> |
9d8f549d | 25 | #include <linux/kernel.h> |
6aa8b732 AK |
26 | #include <linux/vmalloc.h> |
27 | #include <linux/highmem.h> | |
e8edc6e0 | 28 | #include <linux/sched.h> |
229456fc | 29 | #include <linux/ftrace_event.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
6aa8b732 | 31 | |
67ec6607 | 32 | #include <asm/tlbflush.h> |
e495606d | 33 | #include <asm/desc.h> |
631bc487 | 34 | #include <asm/kvm_para.h> |
6aa8b732 | 35 | |
63d1142f | 36 | #include <asm/virtext.h> |
229456fc | 37 | #include "trace.h" |
63d1142f | 38 | |
4ecac3fd AK |
39 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
40 | ||
6aa8b732 AK |
41 | MODULE_AUTHOR("Qumranet"); |
42 | MODULE_LICENSE("GPL"); | |
43 | ||
44 | #define IOPM_ALLOC_ORDER 2 | |
45 | #define MSRPM_ALLOC_ORDER 1 | |
46 | ||
6aa8b732 AK |
47 | #define SEG_TYPE_LDT 2 |
48 | #define SEG_TYPE_BUSY_TSS16 3 | |
49 | ||
6bc31bdc AP |
50 | #define SVM_FEATURE_NPT (1 << 0) |
51 | #define SVM_FEATURE_LBRV (1 << 1) | |
52 | #define SVM_FEATURE_SVML (1 << 2) | |
53 | #define SVM_FEATURE_NRIP (1 << 3) | |
ddce97aa AP |
54 | #define SVM_FEATURE_TSC_RATE (1 << 4) |
55 | #define SVM_FEATURE_VMCB_CLEAN (1 << 5) | |
56 | #define SVM_FEATURE_FLUSH_ASID (1 << 6) | |
57 | #define SVM_FEATURE_DECODE_ASSIST (1 << 7) | |
6bc31bdc | 58 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) |
80b7706e | 59 | |
410e4d57 JR |
60 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
61 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
62 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
63 | ||
24e09cbf JR |
64 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
65 | ||
67ec6607 JR |
66 | static bool erratum_383_found __read_mostly; |
67 | ||
6c8166a7 AK |
68 | static const u32 host_save_user_msrs[] = { |
69 | #ifdef CONFIG_X86_64 | |
70 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
71 | MSR_FS_BASE, | |
72 | #endif | |
73 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
74 | }; | |
75 | ||
76 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
77 | ||
78 | struct kvm_vcpu; | |
79 | ||
e6aa9abd JR |
80 | struct nested_state { |
81 | struct vmcb *hsave; | |
82 | u64 hsave_msr; | |
4a810181 | 83 | u64 vm_cr_msr; |
e6aa9abd JR |
84 | u64 vmcb; |
85 | ||
86 | /* These are the merged vectors */ | |
87 | u32 *msrpm; | |
88 | ||
89 | /* gpa pointers to the real vectors */ | |
90 | u64 vmcb_msrpm; | |
ce2ac085 | 91 | u64 vmcb_iopm; |
aad42c64 | 92 | |
cd3ff653 JR |
93 | /* A VMEXIT is required but not yet emulated */ |
94 | bool exit_required; | |
95 | ||
cda00082 JR |
96 | /* |
97 | * If we vmexit during an instruction emulation we need this to restore | |
98 | * the l1 guest rip after the emulation | |
99 | */ | |
100 | unsigned long vmexit_rip; | |
101 | unsigned long vmexit_rsp; | |
102 | unsigned long vmexit_rax; | |
103 | ||
aad42c64 | 104 | /* cache for intercepts of the guest */ |
4ee546b4 | 105 | u32 intercept_cr; |
3aed041a | 106 | u32 intercept_dr; |
aad42c64 JR |
107 | u32 intercept_exceptions; |
108 | u64 intercept; | |
109 | ||
5bd2edc3 JR |
110 | /* Nested Paging related state */ |
111 | u64 nested_cr3; | |
e6aa9abd JR |
112 | }; |
113 | ||
323c3d80 JR |
114 | #define MSRPM_OFFSETS 16 |
115 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
116 | ||
6c8166a7 AK |
117 | struct vcpu_svm { |
118 | struct kvm_vcpu vcpu; | |
119 | struct vmcb *vmcb; | |
120 | unsigned long vmcb_pa; | |
121 | struct svm_cpu_data *svm_data; | |
122 | uint64_t asid_generation; | |
123 | uint64_t sysenter_esp; | |
124 | uint64_t sysenter_eip; | |
125 | ||
126 | u64 next_rip; | |
127 | ||
128 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
afe9e66f | 129 | struct { |
dacccfdd AK |
130 | u16 fs; |
131 | u16 gs; | |
132 | u16 ldt; | |
afe9e66f AK |
133 | u64 gs_base; |
134 | } host; | |
6c8166a7 AK |
135 | |
136 | u32 *msrpm; | |
6c8166a7 | 137 | |
bd3d1ec3 AK |
138 | ulong nmi_iret_rip; |
139 | ||
e6aa9abd | 140 | struct nested_state nested; |
6be7d306 JK |
141 | |
142 | bool nmi_singlestep; | |
66b7138f JK |
143 | |
144 | unsigned int3_injected; | |
145 | unsigned long int3_rip; | |
631bc487 | 146 | u32 apf_reason; |
6c8166a7 AK |
147 | }; |
148 | ||
455716fa JR |
149 | #define MSR_INVALID 0xffffffffU |
150 | ||
ac72a9b7 JR |
151 | static struct svm_direct_access_msrs { |
152 | u32 index; /* Index of the MSR */ | |
153 | bool always; /* True if intercept is always on */ | |
154 | } direct_access_msrs[] = { | |
8c06585d | 155 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
156 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
157 | #ifdef CONFIG_X86_64 | |
158 | { .index = MSR_GS_BASE, .always = true }, | |
159 | { .index = MSR_FS_BASE, .always = true }, | |
160 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
161 | { .index = MSR_LSTAR, .always = true }, | |
162 | { .index = MSR_CSTAR, .always = true }, | |
163 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
164 | #endif | |
165 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, | |
166 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
167 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
168 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
169 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
170 | }; |
171 | ||
709ddebf JR |
172 | /* enable NPT for AMD64 and X86 with PAE */ |
173 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
174 | static bool npt_enabled = true; | |
175 | #else | |
e0231715 | 176 | static bool npt_enabled; |
709ddebf | 177 | #endif |
6c7dac72 JR |
178 | static int npt = 1; |
179 | ||
180 | module_param(npt, int, S_IRUGO); | |
e3da3acd | 181 | |
4b6e4dca | 182 | static int nested = 1; |
236de055 AG |
183 | module_param(nested, int, S_IRUGO); |
184 | ||
44874f84 | 185 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 186 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 187 | |
410e4d57 | 188 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 189 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 190 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
191 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
192 | bool has_error_code, u32 error_code); | |
193 | ||
8d28fec4 | 194 | enum { |
116a0a23 JR |
195 | VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, |
196 | pause filter count */ | |
f56838e4 | 197 | VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ |
d48086d1 | 198 | VMCB_ASID, /* ASID */ |
decdbf6a | 199 | VMCB_INTR, /* int_ctl, int_vector */ |
b2747166 | 200 | VMCB_NPT, /* npt_en, nCR3, gPAT */ |
dcca1a65 | 201 | VMCB_CR, /* CR0, CR3, CR4, EFER */ |
72214b96 | 202 | VMCB_DR, /* DR6, DR7 */ |
17a703cb | 203 | VMCB_DT, /* GDT, IDT */ |
060d0c9a | 204 | VMCB_SEG, /* CS, DS, SS, ES, CPL */ |
0574dec0 | 205 | VMCB_CR2, /* CR2 only */ |
b53ba3f9 | 206 | VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ |
8d28fec4 RJ |
207 | VMCB_DIRTY_MAX, |
208 | }; | |
209 | ||
0574dec0 JR |
210 | /* TPR and CR2 are always written before VMRUN */ |
211 | #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) | |
8d28fec4 RJ |
212 | |
213 | static inline void mark_all_dirty(struct vmcb *vmcb) | |
214 | { | |
215 | vmcb->control.clean = 0; | |
216 | } | |
217 | ||
218 | static inline void mark_all_clean(struct vmcb *vmcb) | |
219 | { | |
220 | vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) | |
221 | & ~VMCB_ALWAYS_DIRTY_MASK; | |
222 | } | |
223 | ||
224 | static inline void mark_dirty(struct vmcb *vmcb, int bit) | |
225 | { | |
226 | vmcb->control.clean &= ~(1 << bit); | |
227 | } | |
228 | ||
a2fa3e9f GH |
229 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
230 | { | |
fb3f0f51 | 231 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
232 | } |
233 | ||
384c6368 JR |
234 | static void recalc_intercepts(struct vcpu_svm *svm) |
235 | { | |
236 | struct vmcb_control_area *c, *h; | |
237 | struct nested_state *g; | |
238 | ||
116a0a23 JR |
239 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
240 | ||
384c6368 JR |
241 | if (!is_guest_mode(&svm->vcpu)) |
242 | return; | |
243 | ||
244 | c = &svm->vmcb->control; | |
245 | h = &svm->nested.hsave->control; | |
246 | g = &svm->nested; | |
247 | ||
4ee546b4 | 248 | c->intercept_cr = h->intercept_cr | g->intercept_cr; |
3aed041a | 249 | c->intercept_dr = h->intercept_dr | g->intercept_dr; |
384c6368 JR |
250 | c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions; |
251 | c->intercept = h->intercept | g->intercept; | |
252 | } | |
253 | ||
4ee546b4 RJ |
254 | static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) |
255 | { | |
256 | if (is_guest_mode(&svm->vcpu)) | |
257 | return svm->nested.hsave; | |
258 | else | |
259 | return svm->vmcb; | |
260 | } | |
261 | ||
262 | static inline void set_cr_intercept(struct vcpu_svm *svm, int bit) | |
263 | { | |
264 | struct vmcb *vmcb = get_host_vmcb(svm); | |
265 | ||
266 | vmcb->control.intercept_cr |= (1U << bit); | |
267 | ||
268 | recalc_intercepts(svm); | |
269 | } | |
270 | ||
271 | static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit) | |
272 | { | |
273 | struct vmcb *vmcb = get_host_vmcb(svm); | |
274 | ||
275 | vmcb->control.intercept_cr &= ~(1U << bit); | |
276 | ||
277 | recalc_intercepts(svm); | |
278 | } | |
279 | ||
280 | static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit) | |
281 | { | |
282 | struct vmcb *vmcb = get_host_vmcb(svm); | |
283 | ||
284 | return vmcb->control.intercept_cr & (1U << bit); | |
285 | } | |
286 | ||
3aed041a JR |
287 | static inline void set_dr_intercept(struct vcpu_svm *svm, int bit) |
288 | { | |
289 | struct vmcb *vmcb = get_host_vmcb(svm); | |
290 | ||
291 | vmcb->control.intercept_dr |= (1U << bit); | |
292 | ||
293 | recalc_intercepts(svm); | |
294 | } | |
295 | ||
296 | static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit) | |
297 | { | |
298 | struct vmcb *vmcb = get_host_vmcb(svm); | |
299 | ||
300 | vmcb->control.intercept_dr &= ~(1U << bit); | |
301 | ||
302 | recalc_intercepts(svm); | |
303 | } | |
304 | ||
18c918c5 JR |
305 | static inline void set_exception_intercept(struct vcpu_svm *svm, int bit) |
306 | { | |
307 | struct vmcb *vmcb = get_host_vmcb(svm); | |
308 | ||
309 | vmcb->control.intercept_exceptions |= (1U << bit); | |
310 | ||
311 | recalc_intercepts(svm); | |
312 | } | |
313 | ||
314 | static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit) | |
315 | { | |
316 | struct vmcb *vmcb = get_host_vmcb(svm); | |
317 | ||
318 | vmcb->control.intercept_exceptions &= ~(1U << bit); | |
319 | ||
320 | recalc_intercepts(svm); | |
321 | } | |
322 | ||
8a05a1b8 JR |
323 | static inline void set_intercept(struct vcpu_svm *svm, int bit) |
324 | { | |
325 | struct vmcb *vmcb = get_host_vmcb(svm); | |
326 | ||
327 | vmcb->control.intercept |= (1ULL << bit); | |
328 | ||
329 | recalc_intercepts(svm); | |
330 | } | |
331 | ||
332 | static inline void clr_intercept(struct vcpu_svm *svm, int bit) | |
333 | { | |
334 | struct vmcb *vmcb = get_host_vmcb(svm); | |
335 | ||
336 | vmcb->control.intercept &= ~(1ULL << bit); | |
337 | ||
338 | recalc_intercepts(svm); | |
339 | } | |
340 | ||
2af9194d JR |
341 | static inline void enable_gif(struct vcpu_svm *svm) |
342 | { | |
343 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
344 | } | |
345 | ||
346 | static inline void disable_gif(struct vcpu_svm *svm) | |
347 | { | |
348 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
349 | } | |
350 | ||
351 | static inline bool gif_set(struct vcpu_svm *svm) | |
352 | { | |
353 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
354 | } | |
355 | ||
4866d5e3 | 356 | static unsigned long iopm_base; |
6aa8b732 AK |
357 | |
358 | struct kvm_ldttss_desc { | |
359 | u16 limit0; | |
360 | u16 base0; | |
e0231715 JR |
361 | unsigned base1:8, type:5, dpl:2, p:1; |
362 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
363 | u32 base3; |
364 | u32 zero1; | |
365 | } __attribute__((packed)); | |
366 | ||
367 | struct svm_cpu_data { | |
368 | int cpu; | |
369 | ||
5008fdf5 AK |
370 | u64 asid_generation; |
371 | u32 max_asid; | |
372 | u32 next_asid; | |
6aa8b732 AK |
373 | struct kvm_ldttss_desc *tss_desc; |
374 | ||
375 | struct page *save_area; | |
376 | }; | |
377 | ||
378 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 379 | static uint32_t svm_features; |
6aa8b732 AK |
380 | |
381 | struct svm_init_data { | |
382 | int cpu; | |
383 | int r; | |
384 | }; | |
385 | ||
386 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
387 | ||
9d8f549d | 388 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
389 | #define MSRS_RANGE_SIZE 2048 |
390 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
391 | ||
455716fa JR |
392 | static u32 svm_msrpm_offset(u32 msr) |
393 | { | |
394 | u32 offset; | |
395 | int i; | |
396 | ||
397 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
398 | if (msr < msrpm_ranges[i] || | |
399 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
400 | continue; | |
401 | ||
402 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
403 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
404 | ||
405 | /* Now we have the u8 offset - but need the u32 offset */ | |
406 | return offset / 4; | |
407 | } | |
408 | ||
409 | /* MSR not in any range */ | |
410 | return MSR_INVALID; | |
411 | } | |
412 | ||
6aa8b732 AK |
413 | #define MAX_INST_SIZE 15 |
414 | ||
6aa8b732 AK |
415 | static inline void clgi(void) |
416 | { | |
4ecac3fd | 417 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
418 | } |
419 | ||
420 | static inline void stgi(void) | |
421 | { | |
4ecac3fd | 422 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
423 | } |
424 | ||
425 | static inline void invlpga(unsigned long addr, u32 asid) | |
426 | { | |
e0231715 | 427 | asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); |
6aa8b732 AK |
428 | } |
429 | ||
4b16184c JR |
430 | static int get_npt_level(void) |
431 | { | |
432 | #ifdef CONFIG_X86_64 | |
433 | return PT64_ROOT_LEVEL; | |
434 | #else | |
435 | return PT32E_ROOT_LEVEL; | |
436 | #endif | |
437 | } | |
438 | ||
6aa8b732 AK |
439 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
440 | { | |
6dc696d4 | 441 | vcpu->arch.efer = efer; |
709ddebf | 442 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 443 | efer &= ~EFER_LME; |
6aa8b732 | 444 | |
9962d032 | 445 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
dcca1a65 | 446 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
447 | } |
448 | ||
6aa8b732 AK |
449 | static int is_external_interrupt(u32 info) |
450 | { | |
451 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
452 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
453 | } | |
454 | ||
2809f5d2 GC |
455 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
456 | { | |
457 | struct vcpu_svm *svm = to_svm(vcpu); | |
458 | u32 ret = 0; | |
459 | ||
460 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
48005f64 | 461 | ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 GC |
462 | return ret & mask; |
463 | } | |
464 | ||
465 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
466 | { | |
467 | struct vcpu_svm *svm = to_svm(vcpu); | |
468 | ||
469 | if (mask == 0) | |
470 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
471 | else | |
472 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
473 | ||
474 | } | |
475 | ||
6aa8b732 AK |
476 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
477 | { | |
a2fa3e9f GH |
478 | struct vcpu_svm *svm = to_svm(vcpu); |
479 | ||
6bc31bdc AP |
480 | if (svm->vmcb->control.next_rip != 0) |
481 | svm->next_rip = svm->vmcb->control.next_rip; | |
482 | ||
a2fa3e9f | 483 | if (!svm->next_rip) { |
51d8b661 | 484 | if (emulate_instruction(vcpu, EMULTYPE_SKIP) != |
f629cf84 GN |
485 | EMULATE_DONE) |
486 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
487 | return; |
488 | } | |
5fdbf976 MT |
489 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
490 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
491 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 492 | |
5fdbf976 | 493 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 494 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
495 | } |
496 | ||
116a4752 | 497 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
498 | bool has_error_code, u32 error_code, |
499 | bool reinject) | |
116a4752 JK |
500 | { |
501 | struct vcpu_svm *svm = to_svm(vcpu); | |
502 | ||
e0231715 JR |
503 | /* |
504 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
505 | * handle the exception | |
506 | */ | |
ce7ddec4 JR |
507 | if (!reinject && |
508 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
509 | return; |
510 | ||
2a6b20b8 | 511 | if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) { |
66b7138f JK |
512 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); |
513 | ||
514 | /* | |
515 | * For guest debugging where we have to reinject #BP if some | |
516 | * INT3 is guest-owned: | |
517 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
518 | * raises a fault that is not intercepted. Still better than | |
519 | * failing in all cases. | |
520 | */ | |
521 | skip_emulated_instruction(&svm->vcpu); | |
522 | rip = kvm_rip_read(&svm->vcpu); | |
523 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
524 | svm->int3_injected = rip - old_rip; | |
525 | } | |
526 | ||
116a4752 JK |
527 | svm->vmcb->control.event_inj = nr |
528 | | SVM_EVTINJ_VALID | |
529 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
530 | | SVM_EVTINJ_TYPE_EXEPT; | |
531 | svm->vmcb->control.event_inj_err = error_code; | |
532 | } | |
533 | ||
67ec6607 JR |
534 | static void svm_init_erratum_383(void) |
535 | { | |
536 | u32 low, high; | |
537 | int err; | |
538 | u64 val; | |
539 | ||
1be85a6d | 540 | if (!cpu_has_amd_erratum(amd_erratum_383)) |
67ec6607 JR |
541 | return; |
542 | ||
543 | /* Use _safe variants to not break nested virtualization */ | |
544 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
545 | if (err) | |
546 | return; | |
547 | ||
548 | val |= (1ULL << 47); | |
549 | ||
550 | low = lower_32_bits(val); | |
551 | high = upper_32_bits(val); | |
552 | ||
553 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
554 | ||
555 | erratum_383_found = true; | |
556 | } | |
557 | ||
6aa8b732 AK |
558 | static int has_svm(void) |
559 | { | |
63d1142f | 560 | const char *msg; |
6aa8b732 | 561 | |
63d1142f | 562 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 563 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
564 | return 0; |
565 | } | |
566 | ||
6aa8b732 AK |
567 | return 1; |
568 | } | |
569 | ||
570 | static void svm_hardware_disable(void *garbage) | |
571 | { | |
2c8dceeb | 572 | cpu_svm_disable(); |
6aa8b732 AK |
573 | } |
574 | ||
10474ae8 | 575 | static int svm_hardware_enable(void *garbage) |
6aa8b732 AK |
576 | { |
577 | ||
0fe1e009 | 578 | struct svm_cpu_data *sd; |
6aa8b732 | 579 | uint64_t efer; |
89a27f4d | 580 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
581 | struct desc_struct *gdt; |
582 | int me = raw_smp_processor_id(); | |
583 | ||
10474ae8 AG |
584 | rdmsrl(MSR_EFER, efer); |
585 | if (efer & EFER_SVME) | |
586 | return -EBUSY; | |
587 | ||
6aa8b732 | 588 | if (!has_svm()) { |
e6732a5a ZA |
589 | printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n", |
590 | me); | |
10474ae8 | 591 | return -EINVAL; |
6aa8b732 | 592 | } |
0fe1e009 | 593 | sd = per_cpu(svm_data, me); |
6aa8b732 | 594 | |
0fe1e009 | 595 | if (!sd) { |
e6732a5a | 596 | printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n", |
6aa8b732 | 597 | me); |
10474ae8 | 598 | return -EINVAL; |
6aa8b732 AK |
599 | } |
600 | ||
0fe1e009 TH |
601 | sd->asid_generation = 1; |
602 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
603 | sd->next_asid = sd->max_asid + 1; | |
6aa8b732 | 604 | |
d6ab1ed4 | 605 | native_store_gdt(&gdt_descr); |
89a27f4d | 606 | gdt = (struct desc_struct *)gdt_descr.address; |
0fe1e009 | 607 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 608 | |
9962d032 | 609 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 610 | |
d0316554 | 611 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 612 | |
67ec6607 JR |
613 | svm_init_erratum_383(); |
614 | ||
10474ae8 | 615 | return 0; |
6aa8b732 AK |
616 | } |
617 | ||
0da1db75 JR |
618 | static void svm_cpu_uninit(int cpu) |
619 | { | |
0fe1e009 | 620 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 621 | |
0fe1e009 | 622 | if (!sd) |
0da1db75 JR |
623 | return; |
624 | ||
625 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
0fe1e009 TH |
626 | __free_page(sd->save_area); |
627 | kfree(sd); | |
0da1db75 JR |
628 | } |
629 | ||
6aa8b732 AK |
630 | static int svm_cpu_init(int cpu) |
631 | { | |
0fe1e009 | 632 | struct svm_cpu_data *sd; |
6aa8b732 AK |
633 | int r; |
634 | ||
0fe1e009 TH |
635 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
636 | if (!sd) | |
6aa8b732 | 637 | return -ENOMEM; |
0fe1e009 TH |
638 | sd->cpu = cpu; |
639 | sd->save_area = alloc_page(GFP_KERNEL); | |
6aa8b732 | 640 | r = -ENOMEM; |
0fe1e009 | 641 | if (!sd->save_area) |
6aa8b732 AK |
642 | goto err_1; |
643 | ||
0fe1e009 | 644 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
645 | |
646 | return 0; | |
647 | ||
648 | err_1: | |
0fe1e009 | 649 | kfree(sd); |
6aa8b732 AK |
650 | return r; |
651 | ||
652 | } | |
653 | ||
ac72a9b7 JR |
654 | static bool valid_msr_intercept(u32 index) |
655 | { | |
656 | int i; | |
657 | ||
658 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
659 | if (direct_access_msrs[i].index == index) | |
660 | return true; | |
661 | ||
662 | return false; | |
663 | } | |
664 | ||
bfc733a7 RR |
665 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
666 | int read, int write) | |
6aa8b732 | 667 | { |
455716fa JR |
668 | u8 bit_read, bit_write; |
669 | unsigned long tmp; | |
670 | u32 offset; | |
6aa8b732 | 671 | |
ac72a9b7 JR |
672 | /* |
673 | * If this warning triggers extend the direct_access_msrs list at the | |
674 | * beginning of the file | |
675 | */ | |
676 | WARN_ON(!valid_msr_intercept(msr)); | |
677 | ||
455716fa JR |
678 | offset = svm_msrpm_offset(msr); |
679 | bit_read = 2 * (msr & 0x0f); | |
680 | bit_write = 2 * (msr & 0x0f) + 1; | |
681 | tmp = msrpm[offset]; | |
682 | ||
683 | BUG_ON(offset == MSR_INVALID); | |
684 | ||
685 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
686 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
687 | ||
688 | msrpm[offset] = tmp; | |
6aa8b732 AK |
689 | } |
690 | ||
f65c229c | 691 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
692 | { |
693 | int i; | |
694 | ||
f65c229c JR |
695 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
696 | ||
ac72a9b7 JR |
697 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
698 | if (!direct_access_msrs[i].always) | |
699 | continue; | |
700 | ||
701 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
702 | } | |
f65c229c JR |
703 | } |
704 | ||
323c3d80 JR |
705 | static void add_msr_offset(u32 offset) |
706 | { | |
707 | int i; | |
708 | ||
709 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
710 | ||
711 | /* Offset already in list? */ | |
712 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 713 | return; |
323c3d80 JR |
714 | |
715 | /* Slot used by another offset? */ | |
716 | if (msrpm_offsets[i] != MSR_INVALID) | |
717 | continue; | |
718 | ||
719 | /* Add offset to list */ | |
720 | msrpm_offsets[i] = offset; | |
721 | ||
722 | return; | |
6aa8b732 | 723 | } |
323c3d80 JR |
724 | |
725 | /* | |
726 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
727 | * increase MSRPM_OFFSETS in this case. | |
728 | */ | |
bfc733a7 | 729 | BUG(); |
6aa8b732 AK |
730 | } |
731 | ||
323c3d80 | 732 | static void init_msrpm_offsets(void) |
f65c229c | 733 | { |
323c3d80 | 734 | int i; |
f65c229c | 735 | |
323c3d80 JR |
736 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
737 | ||
738 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
739 | u32 offset; | |
740 | ||
741 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
742 | BUG_ON(offset == MSR_INVALID); | |
743 | ||
744 | add_msr_offset(offset); | |
745 | } | |
f65c229c JR |
746 | } |
747 | ||
24e09cbf JR |
748 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
749 | { | |
750 | u32 *msrpm = svm->msrpm; | |
751 | ||
752 | svm->vmcb->control.lbr_ctl = 1; | |
753 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
754 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
755 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
756 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
757 | } | |
758 | ||
759 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
760 | { | |
761 | u32 *msrpm = svm->msrpm; | |
762 | ||
763 | svm->vmcb->control.lbr_ctl = 0; | |
764 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
765 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
766 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
767 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
768 | } | |
769 | ||
6aa8b732 AK |
770 | static __init int svm_hardware_setup(void) |
771 | { | |
772 | int cpu; | |
773 | struct page *iopm_pages; | |
f65c229c | 774 | void *iopm_va; |
6aa8b732 AK |
775 | int r; |
776 | ||
6aa8b732 AK |
777 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
778 | ||
779 | if (!iopm_pages) | |
780 | return -ENOMEM; | |
c8681339 AL |
781 | |
782 | iopm_va = page_address(iopm_pages); | |
783 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
784 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
785 | ||
323c3d80 JR |
786 | init_msrpm_offsets(); |
787 | ||
50a37eb4 JR |
788 | if (boot_cpu_has(X86_FEATURE_NX)) |
789 | kvm_enable_efer_bits(EFER_NX); | |
790 | ||
1b2fd70c AG |
791 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
792 | kvm_enable_efer_bits(EFER_FFXSR); | |
793 | ||
236de055 AG |
794 | if (nested) { |
795 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 796 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
797 | } |
798 | ||
3230bb47 | 799 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
800 | r = svm_cpu_init(cpu); |
801 | if (r) | |
f65c229c | 802 | goto err; |
6aa8b732 | 803 | } |
33bd6a0b JR |
804 | |
805 | svm_features = cpuid_edx(SVM_CPUID_FUNC); | |
806 | ||
2a6b20b8 | 807 | if (!boot_cpu_has(X86_FEATURE_NPT)) |
e3da3acd JR |
808 | npt_enabled = false; |
809 | ||
6c7dac72 JR |
810 | if (npt_enabled && !npt) { |
811 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
812 | npt_enabled = false; | |
813 | } | |
814 | ||
18552672 | 815 | if (npt_enabled) { |
e3da3acd | 816 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 817 | kvm_enable_tdp(); |
5f4cb662 JR |
818 | } else |
819 | kvm_disable_tdp(); | |
e3da3acd | 820 | |
6aa8b732 AK |
821 | return 0; |
822 | ||
f65c229c | 823 | err: |
6aa8b732 AK |
824 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
825 | iopm_base = 0; | |
826 | return r; | |
827 | } | |
828 | ||
829 | static __exit void svm_hardware_unsetup(void) | |
830 | { | |
0da1db75 JR |
831 | int cpu; |
832 | ||
3230bb47 | 833 | for_each_possible_cpu(cpu) |
0da1db75 JR |
834 | svm_cpu_uninit(cpu); |
835 | ||
6aa8b732 | 836 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 837 | iopm_base = 0; |
6aa8b732 AK |
838 | } |
839 | ||
840 | static void init_seg(struct vmcb_seg *seg) | |
841 | { | |
842 | seg->selector = 0; | |
843 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 844 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
845 | seg->limit = 0xffff; |
846 | seg->base = 0; | |
847 | } | |
848 | ||
849 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
850 | { | |
851 | seg->selector = 0; | |
852 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
853 | seg->limit = 0xffff; | |
854 | seg->base = 0; | |
855 | } | |
856 | ||
f4e1b3c8 ZA |
857 | static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
858 | { | |
859 | struct vcpu_svm *svm = to_svm(vcpu); | |
860 | u64 g_tsc_offset = 0; | |
861 | ||
2030753d | 862 | if (is_guest_mode(vcpu)) { |
f4e1b3c8 ZA |
863 | g_tsc_offset = svm->vmcb->control.tsc_offset - |
864 | svm->nested.hsave->control.tsc_offset; | |
865 | svm->nested.hsave->control.tsc_offset = offset; | |
866 | } | |
867 | ||
868 | svm->vmcb->control.tsc_offset = offset + g_tsc_offset; | |
116a0a23 JR |
869 | |
870 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); | |
f4e1b3c8 ZA |
871 | } |
872 | ||
e48672fa ZA |
873 | static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment) |
874 | { | |
875 | struct vcpu_svm *svm = to_svm(vcpu); | |
876 | ||
877 | svm->vmcb->control.tsc_offset += adjustment; | |
2030753d | 878 | if (is_guest_mode(vcpu)) |
e48672fa | 879 | svm->nested.hsave->control.tsc_offset += adjustment; |
116a0a23 | 880 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
e48672fa ZA |
881 | } |
882 | ||
e6101a96 | 883 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 884 | { |
e6101a96 JR |
885 | struct vmcb_control_area *control = &svm->vmcb->control; |
886 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 887 | |
bff78274 | 888 | svm->vcpu.fpu_active = 1; |
4ee546b4 | 889 | svm->vcpu.arch.hflags = 0; |
bff78274 | 890 | |
4ee546b4 RJ |
891 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
892 | set_cr_intercept(svm, INTERCEPT_CR3_READ); | |
893 | set_cr_intercept(svm, INTERCEPT_CR4_READ); | |
894 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
895 | set_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
896 | set_cr_intercept(svm, INTERCEPT_CR4_WRITE); | |
897 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
6aa8b732 | 898 | |
3aed041a JR |
899 | set_dr_intercept(svm, INTERCEPT_DR0_READ); |
900 | set_dr_intercept(svm, INTERCEPT_DR1_READ); | |
901 | set_dr_intercept(svm, INTERCEPT_DR2_READ); | |
902 | set_dr_intercept(svm, INTERCEPT_DR3_READ); | |
903 | set_dr_intercept(svm, INTERCEPT_DR4_READ); | |
904 | set_dr_intercept(svm, INTERCEPT_DR5_READ); | |
905 | set_dr_intercept(svm, INTERCEPT_DR6_READ); | |
906 | set_dr_intercept(svm, INTERCEPT_DR7_READ); | |
907 | ||
908 | set_dr_intercept(svm, INTERCEPT_DR0_WRITE); | |
909 | set_dr_intercept(svm, INTERCEPT_DR1_WRITE); | |
910 | set_dr_intercept(svm, INTERCEPT_DR2_WRITE); | |
911 | set_dr_intercept(svm, INTERCEPT_DR3_WRITE); | |
912 | set_dr_intercept(svm, INTERCEPT_DR4_WRITE); | |
913 | set_dr_intercept(svm, INTERCEPT_DR5_WRITE); | |
914 | set_dr_intercept(svm, INTERCEPT_DR6_WRITE); | |
915 | set_dr_intercept(svm, INTERCEPT_DR7_WRITE); | |
6aa8b732 | 916 | |
18c918c5 JR |
917 | set_exception_intercept(svm, PF_VECTOR); |
918 | set_exception_intercept(svm, UD_VECTOR); | |
919 | set_exception_intercept(svm, MC_VECTOR); | |
6aa8b732 | 920 | |
8a05a1b8 JR |
921 | set_intercept(svm, INTERCEPT_INTR); |
922 | set_intercept(svm, INTERCEPT_NMI); | |
923 | set_intercept(svm, INTERCEPT_SMI); | |
924 | set_intercept(svm, INTERCEPT_SELECTIVE_CR0); | |
925 | set_intercept(svm, INTERCEPT_CPUID); | |
926 | set_intercept(svm, INTERCEPT_INVD); | |
927 | set_intercept(svm, INTERCEPT_HLT); | |
928 | set_intercept(svm, INTERCEPT_INVLPG); | |
929 | set_intercept(svm, INTERCEPT_INVLPGA); | |
930 | set_intercept(svm, INTERCEPT_IOIO_PROT); | |
931 | set_intercept(svm, INTERCEPT_MSR_PROT); | |
932 | set_intercept(svm, INTERCEPT_TASK_SWITCH); | |
933 | set_intercept(svm, INTERCEPT_SHUTDOWN); | |
934 | set_intercept(svm, INTERCEPT_VMRUN); | |
935 | set_intercept(svm, INTERCEPT_VMMCALL); | |
936 | set_intercept(svm, INTERCEPT_VMLOAD); | |
937 | set_intercept(svm, INTERCEPT_VMSAVE); | |
938 | set_intercept(svm, INTERCEPT_STGI); | |
939 | set_intercept(svm, INTERCEPT_CLGI); | |
940 | set_intercept(svm, INTERCEPT_SKINIT); | |
941 | set_intercept(svm, INTERCEPT_WBINVD); | |
942 | set_intercept(svm, INTERCEPT_MONITOR); | |
943 | set_intercept(svm, INTERCEPT_MWAIT); | |
81dd35d4 | 944 | set_intercept(svm, INTERCEPT_XSETBV); |
6aa8b732 AK |
945 | |
946 | control->iopm_base_pa = iopm_base; | |
f65c229c | 947 | control->msrpm_base_pa = __pa(svm->msrpm); |
6aa8b732 AK |
948 | control->int_ctl = V_INTR_MASKING_MASK; |
949 | ||
950 | init_seg(&save->es); | |
951 | init_seg(&save->ss); | |
952 | init_seg(&save->ds); | |
953 | init_seg(&save->fs); | |
954 | init_seg(&save->gs); | |
955 | ||
956 | save->cs.selector = 0xf000; | |
957 | /* Executable/Readable Code Segment */ | |
958 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
959 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
960 | save->cs.limit = 0xffff; | |
d92899a0 AK |
961 | /* |
962 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
963 | * be consistent with it. | |
964 | * | |
965 | * Replace when we have real mode working for vmx. | |
966 | */ | |
967 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
968 | |
969 | save->gdtr.limit = 0xffff; | |
970 | save->idtr.limit = 0xffff; | |
971 | ||
972 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
973 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
974 | ||
eaa48512 | 975 | svm_set_efer(&svm->vcpu, 0); |
d77c26fc | 976 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
977 | save->dr7 = 0x400; |
978 | save->rflags = 2; | |
979 | save->rip = 0x0000fff0; | |
5fdbf976 | 980 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 981 | |
e0231715 JR |
982 | /* |
983 | * This is the guest-visible cr0 value. | |
18fa000a | 984 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
6aa8b732 | 985 | */ |
678041ad MT |
986 | svm->vcpu.arch.cr0 = 0; |
987 | (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); | |
18fa000a | 988 | |
66aee91a | 989 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 990 | /* rdx = ?? */ |
709ddebf JR |
991 | |
992 | if (npt_enabled) { | |
993 | /* Setup VMCB for Nested Paging */ | |
994 | control->nested_ctl = 1; | |
8a05a1b8 JR |
995 | clr_intercept(svm, INTERCEPT_TASK_SWITCH); |
996 | clr_intercept(svm, INTERCEPT_INVLPG); | |
18c918c5 | 997 | clr_exception_intercept(svm, PF_VECTOR); |
4ee546b4 RJ |
998 | clr_cr_intercept(svm, INTERCEPT_CR3_READ); |
999 | clr_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
709ddebf | 1000 | save->g_pat = 0x0007040600070406ULL; |
709ddebf JR |
1001 | save->cr3 = 0; |
1002 | save->cr4 = 0; | |
1003 | } | |
f40f6a45 | 1004 | svm->asid_generation = 0; |
1371d904 | 1005 | |
e6aa9abd | 1006 | svm->nested.vmcb = 0; |
2af9194d JR |
1007 | svm->vcpu.arch.hflags = 0; |
1008 | ||
2a6b20b8 | 1009 | if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { |
565d0998 | 1010 | control->pause_filter_count = 3000; |
8a05a1b8 | 1011 | set_intercept(svm, INTERCEPT_PAUSE); |
565d0998 ML |
1012 | } |
1013 | ||
8d28fec4 RJ |
1014 | mark_all_dirty(svm->vmcb); |
1015 | ||
2af9194d | 1016 | enable_gif(svm); |
6aa8b732 AK |
1017 | } |
1018 | ||
e00c8cf2 | 1019 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
1020 | { |
1021 | struct vcpu_svm *svm = to_svm(vcpu); | |
1022 | ||
e6101a96 | 1023 | init_vmcb(svm); |
70433389 | 1024 | |
c5af89b6 | 1025 | if (!kvm_vcpu_is_bsp(vcpu)) { |
5fdbf976 | 1026 | kvm_rip_write(vcpu, 0); |
ad312c7c ZX |
1027 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
1028 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 1029 | } |
5fdbf976 MT |
1030 | vcpu->arch.regs_avail = ~0; |
1031 | vcpu->arch.regs_dirty = ~0; | |
e00c8cf2 AK |
1032 | |
1033 | return 0; | |
04d2cc77 AK |
1034 | } |
1035 | ||
fb3f0f51 | 1036 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 1037 | { |
a2fa3e9f | 1038 | struct vcpu_svm *svm; |
6aa8b732 | 1039 | struct page *page; |
f65c229c | 1040 | struct page *msrpm_pages; |
b286d5d8 | 1041 | struct page *hsave_page; |
3d6368ef | 1042 | struct page *nested_msrpm_pages; |
fb3f0f51 | 1043 | int err; |
6aa8b732 | 1044 | |
c16f862d | 1045 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
1046 | if (!svm) { |
1047 | err = -ENOMEM; | |
1048 | goto out; | |
1049 | } | |
1050 | ||
1051 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
1052 | if (err) | |
1053 | goto free_svm; | |
1054 | ||
b7af4043 | 1055 | err = -ENOMEM; |
6aa8b732 | 1056 | page = alloc_page(GFP_KERNEL); |
b7af4043 | 1057 | if (!page) |
fb3f0f51 | 1058 | goto uninit; |
6aa8b732 | 1059 | |
f65c229c JR |
1060 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); |
1061 | if (!msrpm_pages) | |
b7af4043 | 1062 | goto free_page1; |
3d6368ef AG |
1063 | |
1064 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
1065 | if (!nested_msrpm_pages) | |
b7af4043 | 1066 | goto free_page2; |
f65c229c | 1067 | |
b286d5d8 AG |
1068 | hsave_page = alloc_page(GFP_KERNEL); |
1069 | if (!hsave_page) | |
b7af4043 TY |
1070 | goto free_page3; |
1071 | ||
e6aa9abd | 1072 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 1073 | |
b7af4043 TY |
1074 | svm->msrpm = page_address(msrpm_pages); |
1075 | svm_vcpu_init_msrpm(svm->msrpm); | |
1076 | ||
e6aa9abd | 1077 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 1078 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 1079 | |
a2fa3e9f GH |
1080 | svm->vmcb = page_address(page); |
1081 | clear_page(svm->vmcb); | |
1082 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
1083 | svm->asid_generation = 0; | |
e6101a96 | 1084 | init_vmcb(svm); |
99e3e30a | 1085 | kvm_write_tsc(&svm->vcpu, 0); |
a2fa3e9f | 1086 | |
10ab25cd JK |
1087 | err = fx_init(&svm->vcpu); |
1088 | if (err) | |
1089 | goto free_page4; | |
1090 | ||
ad312c7c | 1091 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 1092 | if (kvm_vcpu_is_bsp(&svm->vcpu)) |
ad312c7c | 1093 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 1094 | |
fb3f0f51 | 1095 | return &svm->vcpu; |
36241b8c | 1096 | |
10ab25cd JK |
1097 | free_page4: |
1098 | __free_page(hsave_page); | |
b7af4043 TY |
1099 | free_page3: |
1100 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
1101 | free_page2: | |
1102 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
1103 | free_page1: | |
1104 | __free_page(page); | |
fb3f0f51 RR |
1105 | uninit: |
1106 | kvm_vcpu_uninit(&svm->vcpu); | |
1107 | free_svm: | |
a4770347 | 1108 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
1109 | out: |
1110 | return ERR_PTR(err); | |
6aa8b732 AK |
1111 | } |
1112 | ||
1113 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
1114 | { | |
a2fa3e9f GH |
1115 | struct vcpu_svm *svm = to_svm(vcpu); |
1116 | ||
fb3f0f51 | 1117 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 1118 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
1119 | __free_page(virt_to_page(svm->nested.hsave)); |
1120 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 1121 | kvm_vcpu_uninit(vcpu); |
a4770347 | 1122 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
1123 | } |
1124 | ||
15ad7146 | 1125 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 1126 | { |
a2fa3e9f | 1127 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 1128 | int i; |
0cc5064d | 1129 | |
0cc5064d | 1130 | if (unlikely(cpu != vcpu->cpu)) { |
4b656b12 | 1131 | svm->asid_generation = 0; |
8d28fec4 | 1132 | mark_all_dirty(svm->vmcb); |
0cc5064d | 1133 | } |
94dfbdb3 | 1134 | |
82ca2d10 AK |
1135 | #ifdef CONFIG_X86_64 |
1136 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); | |
1137 | #endif | |
dacccfdd AK |
1138 | savesegment(fs, svm->host.fs); |
1139 | savesegment(gs, svm->host.gs); | |
1140 | svm->host.ldt = kvm_read_ldt(); | |
1141 | ||
94dfbdb3 | 1142 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1143 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1144 | } |
1145 | ||
1146 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
1147 | { | |
a2fa3e9f | 1148 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
1149 | int i; |
1150 | ||
e1beb1d3 | 1151 | ++vcpu->stat.host_state_reload; |
dacccfdd AK |
1152 | kvm_load_ldt(svm->host.ldt); |
1153 | #ifdef CONFIG_X86_64 | |
1154 | loadsegment(fs, svm->host.fs); | |
dacccfdd | 1155 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs); |
893a5ab6 | 1156 | load_gs_index(svm->host.gs); |
dacccfdd | 1157 | #else |
831ca609 | 1158 | #ifdef CONFIG_X86_32_LAZY_GS |
dacccfdd | 1159 | loadsegment(gs, svm->host.gs); |
831ca609 | 1160 | #endif |
dacccfdd | 1161 | #endif |
94dfbdb3 | 1162 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1163 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1164 | } |
1165 | ||
6aa8b732 AK |
1166 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
1167 | { | |
a2fa3e9f | 1168 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
1169 | } |
1170 | ||
1171 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
1172 | { | |
a2fa3e9f | 1173 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
1174 | } |
1175 | ||
6de4f3ad AK |
1176 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
1177 | { | |
1178 | switch (reg) { | |
1179 | case VCPU_EXREG_PDPTR: | |
1180 | BUG_ON(!npt_enabled); | |
9f8fe504 | 1181 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
6de4f3ad AK |
1182 | break; |
1183 | default: | |
1184 | BUG(); | |
1185 | } | |
1186 | } | |
1187 | ||
f0b85051 AG |
1188 | static void svm_set_vintr(struct vcpu_svm *svm) |
1189 | { | |
8a05a1b8 | 1190 | set_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1191 | } |
1192 | ||
1193 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
1194 | { | |
8a05a1b8 | 1195 | clr_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1196 | } |
1197 | ||
6aa8b732 AK |
1198 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
1199 | { | |
a2fa3e9f | 1200 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
1201 | |
1202 | switch (seg) { | |
1203 | case VCPU_SREG_CS: return &save->cs; | |
1204 | case VCPU_SREG_DS: return &save->ds; | |
1205 | case VCPU_SREG_ES: return &save->es; | |
1206 | case VCPU_SREG_FS: return &save->fs; | |
1207 | case VCPU_SREG_GS: return &save->gs; | |
1208 | case VCPU_SREG_SS: return &save->ss; | |
1209 | case VCPU_SREG_TR: return &save->tr; | |
1210 | case VCPU_SREG_LDTR: return &save->ldtr; | |
1211 | } | |
1212 | BUG(); | |
8b6d44c7 | 1213 | return NULL; |
6aa8b732 AK |
1214 | } |
1215 | ||
1216 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1217 | { | |
1218 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1219 | ||
1220 | return s->base; | |
1221 | } | |
1222 | ||
1223 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
1224 | struct kvm_segment *var, int seg) | |
1225 | { | |
1226 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1227 | ||
1228 | var->base = s->base; | |
1229 | var->limit = s->limit; | |
1230 | var->selector = s->selector; | |
1231 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
1232 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
1233 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
1234 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
1235 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
1236 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
1237 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
1238 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
25022acc | 1239 | |
e0231715 JR |
1240 | /* |
1241 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
1242 | * for cross vendor migration purposes by "not present" |
1243 | */ | |
1244 | var->unusable = !var->present || (var->type == 0); | |
1245 | ||
1fbdc7a5 AP |
1246 | switch (seg) { |
1247 | case VCPU_SREG_CS: | |
1248 | /* | |
1249 | * SVM always stores 0 for the 'G' bit in the CS selector in | |
1250 | * the VMCB on a VMEXIT. This hurts cross-vendor migration: | |
1251 | * Intel's VMENTRY has a check on the 'G' bit. | |
1252 | */ | |
25022acc | 1253 | var->g = s->limit > 0xfffff; |
1fbdc7a5 AP |
1254 | break; |
1255 | case VCPU_SREG_TR: | |
1256 | /* | |
1257 | * Work around a bug where the busy flag in the tr selector | |
1258 | * isn't exposed | |
1259 | */ | |
c0d09828 | 1260 | var->type |= 0x2; |
1fbdc7a5 AP |
1261 | break; |
1262 | case VCPU_SREG_DS: | |
1263 | case VCPU_SREG_ES: | |
1264 | case VCPU_SREG_FS: | |
1265 | case VCPU_SREG_GS: | |
1266 | /* | |
1267 | * The accessed bit must always be set in the segment | |
1268 | * descriptor cache, although it can be cleared in the | |
1269 | * descriptor, the cached bit always remains at 1. Since | |
1270 | * Intel has a check on this, set it here to support | |
1271 | * cross-vendor migration. | |
1272 | */ | |
1273 | if (!var->unusable) | |
1274 | var->type |= 0x1; | |
1275 | break; | |
b586eb02 | 1276 | case VCPU_SREG_SS: |
e0231715 JR |
1277 | /* |
1278 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
1279 | * descriptor is left as 1, although the whole segment has |
1280 | * been made unusable. Clear it here to pass an Intel VMX | |
1281 | * entry check when cross vendor migrating. | |
1282 | */ | |
1283 | if (var->unusable) | |
1284 | var->db = 0; | |
1285 | break; | |
1fbdc7a5 | 1286 | } |
6aa8b732 AK |
1287 | } |
1288 | ||
2e4d2653 IE |
1289 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
1290 | { | |
1291 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
1292 | ||
1293 | return save->cpl; | |
1294 | } | |
1295 | ||
89a27f4d | 1296 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1297 | { |
a2fa3e9f GH |
1298 | struct vcpu_svm *svm = to_svm(vcpu); |
1299 | ||
89a27f4d GN |
1300 | dt->size = svm->vmcb->save.idtr.limit; |
1301 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
1302 | } |
1303 | ||
89a27f4d | 1304 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1305 | { |
a2fa3e9f GH |
1306 | struct vcpu_svm *svm = to_svm(vcpu); |
1307 | ||
89a27f4d GN |
1308 | svm->vmcb->save.idtr.limit = dt->size; |
1309 | svm->vmcb->save.idtr.base = dt->address ; | |
17a703cb | 1310 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1311 | } |
1312 | ||
89a27f4d | 1313 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1314 | { |
a2fa3e9f GH |
1315 | struct vcpu_svm *svm = to_svm(vcpu); |
1316 | ||
89a27f4d GN |
1317 | dt->size = svm->vmcb->save.gdtr.limit; |
1318 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
1319 | } |
1320 | ||
89a27f4d | 1321 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1322 | { |
a2fa3e9f GH |
1323 | struct vcpu_svm *svm = to_svm(vcpu); |
1324 | ||
89a27f4d GN |
1325 | svm->vmcb->save.gdtr.limit = dt->size; |
1326 | svm->vmcb->save.gdtr.base = dt->address ; | |
17a703cb | 1327 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1328 | } |
1329 | ||
e8467fda AK |
1330 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
1331 | { | |
1332 | } | |
1333 | ||
aff48baa AK |
1334 | static void svm_decache_cr3(struct kvm_vcpu *vcpu) |
1335 | { | |
1336 | } | |
1337 | ||
25c4c276 | 1338 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
1339 | { |
1340 | } | |
1341 | ||
d225157b AK |
1342 | static void update_cr0_intercept(struct vcpu_svm *svm) |
1343 | { | |
1344 | ulong gcr0 = svm->vcpu.arch.cr0; | |
1345 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
1346 | ||
1347 | if (!svm->vcpu.fpu_active) | |
1348 | *hcr0 |= SVM_CR0_SELECTIVE_MASK; | |
1349 | else | |
1350 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) | |
1351 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
1352 | ||
dcca1a65 | 1353 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b AK |
1354 | |
1355 | if (gcr0 == *hcr0 && svm->vcpu.fpu_active) { | |
4ee546b4 RJ |
1356 | clr_cr_intercept(svm, INTERCEPT_CR0_READ); |
1357 | clr_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b | 1358 | } else { |
4ee546b4 RJ |
1359 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1360 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b AK |
1361 | } |
1362 | } | |
1363 | ||
6aa8b732 AK |
1364 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1365 | { | |
a2fa3e9f GH |
1366 | struct vcpu_svm *svm = to_svm(vcpu); |
1367 | ||
2030753d | 1368 | if (is_guest_mode(vcpu)) { |
7f5d8b56 JR |
1369 | /* |
1370 | * We are here because we run in nested mode, the host kvm | |
1371 | * intercepts cr0 writes but the l1 hypervisor does not. | |
1372 | * But the L1 hypervisor may intercept selective cr0 writes. | |
1373 | * This needs to be checked here. | |
1374 | */ | |
1375 | unsigned long old, new; | |
1376 | ||
1377 | /* Remove bits that would trigger a real cr0 write intercept */ | |
1378 | old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK; | |
1379 | new = cr0 & SVM_CR0_SELECTIVE_MASK; | |
1380 | ||
1381 | if (old == new) { | |
1382 | /* cr0 write with ts and mp unchanged */ | |
1383 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
cda00082 JR |
1384 | if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) { |
1385 | svm->nested.vmexit_rip = kvm_rip_read(vcpu); | |
1386 | svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
1387 | svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
7f5d8b56 | 1388 | return; |
cda00082 | 1389 | } |
7f5d8b56 JR |
1390 | } |
1391 | } | |
1392 | ||
05b3e0c2 | 1393 | #ifdef CONFIG_X86_64 |
f6801dff | 1394 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 1395 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 1396 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 1397 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1398 | } |
1399 | ||
d77c26fc | 1400 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 1401 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 1402 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
1403 | } |
1404 | } | |
1405 | #endif | |
ad312c7c | 1406 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
1407 | |
1408 | if (!npt_enabled) | |
1409 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 AK |
1410 | |
1411 | if (!vcpu->fpu_active) | |
334df50a | 1412 | cr0 |= X86_CR0_TS; |
709ddebf JR |
1413 | /* |
1414 | * re-enable caching here because the QEMU bios | |
1415 | * does not do it - this results in some delay at | |
1416 | * reboot | |
1417 | */ | |
1418 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 1419 | svm->vmcb->save.cr0 = cr0; |
dcca1a65 | 1420 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 1421 | update_cr0_intercept(svm); |
6aa8b732 AK |
1422 | } |
1423 | ||
1424 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1425 | { | |
6394b649 | 1426 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
e5eab0ce JR |
1427 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
1428 | ||
1429 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) | |
f40f6a45 | 1430 | svm_flush_tlb(vcpu); |
6394b649 | 1431 | |
ec077263 JR |
1432 | vcpu->arch.cr4 = cr4; |
1433 | if (!npt_enabled) | |
1434 | cr4 |= X86_CR4_PAE; | |
6394b649 | 1435 | cr4 |= host_cr4_mce; |
ec077263 | 1436 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
dcca1a65 | 1437 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
1438 | } |
1439 | ||
1440 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
1441 | struct kvm_segment *var, int seg) | |
1442 | { | |
a2fa3e9f | 1443 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1444 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
1445 | ||
1446 | s->base = var->base; | |
1447 | s->limit = var->limit; | |
1448 | s->selector = var->selector; | |
1449 | if (var->unusable) | |
1450 | s->attrib = 0; | |
1451 | else { | |
1452 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
1453 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
1454 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
1455 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
1456 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
1457 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
1458 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
1459 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
1460 | } | |
1461 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
1462 | svm->vmcb->save.cpl |
1463 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
1464 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
1465 | ||
060d0c9a | 1466 | mark_dirty(svm->vmcb, VMCB_SEG); |
6aa8b732 AK |
1467 | } |
1468 | ||
44c11430 | 1469 | static void update_db_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 1470 | { |
d0bfb940 JK |
1471 | struct vcpu_svm *svm = to_svm(vcpu); |
1472 | ||
18c918c5 JR |
1473 | clr_exception_intercept(svm, DB_VECTOR); |
1474 | clr_exception_intercept(svm, BP_VECTOR); | |
44c11430 | 1475 | |
6be7d306 | 1476 | if (svm->nmi_singlestep) |
18c918c5 | 1477 | set_exception_intercept(svm, DB_VECTOR); |
44c11430 | 1478 | |
d0bfb940 JK |
1479 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
1480 | if (vcpu->guest_debug & | |
1481 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
18c918c5 | 1482 | set_exception_intercept(svm, DB_VECTOR); |
d0bfb940 | 1483 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
18c918c5 | 1484 | set_exception_intercept(svm, BP_VECTOR); |
d0bfb940 JK |
1485 | } else |
1486 | vcpu->guest_debug = 0; | |
44c11430 GN |
1487 | } |
1488 | ||
355be0b9 | 1489 | static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) |
44c11430 | 1490 | { |
44c11430 GN |
1491 | struct vcpu_svm *svm = to_svm(vcpu); |
1492 | ||
ae675ef0 JK |
1493 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
1494 | svm->vmcb->save.dr7 = dbg->arch.debugreg[7]; | |
1495 | else | |
1496 | svm->vmcb->save.dr7 = vcpu->arch.dr7; | |
1497 | ||
72214b96 JR |
1498 | mark_dirty(svm->vmcb, VMCB_DR); |
1499 | ||
355be0b9 | 1500 | update_db_intercept(vcpu); |
6aa8b732 AK |
1501 | } |
1502 | ||
0fe1e009 | 1503 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 1504 | { |
0fe1e009 TH |
1505 | if (sd->next_asid > sd->max_asid) { |
1506 | ++sd->asid_generation; | |
1507 | sd->next_asid = 1; | |
a2fa3e9f | 1508 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
1509 | } |
1510 | ||
0fe1e009 TH |
1511 | svm->asid_generation = sd->asid_generation; |
1512 | svm->vmcb->control.asid = sd->next_asid++; | |
d48086d1 JR |
1513 | |
1514 | mark_dirty(svm->vmcb, VMCB_ASID); | |
6aa8b732 AK |
1515 | } |
1516 | ||
020df079 | 1517 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 1518 | { |
42dbaa5a | 1519 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 1520 | |
020df079 | 1521 | svm->vmcb->save.dr7 = value; |
72214b96 | 1522 | mark_dirty(svm->vmcb, VMCB_DR); |
6aa8b732 AK |
1523 | } |
1524 | ||
851ba692 | 1525 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 1526 | { |
631bc487 | 1527 | u64 fault_address = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1528 | u32 error_code; |
631bc487 | 1529 | int r = 1; |
6aa8b732 | 1530 | |
631bc487 GN |
1531 | switch (svm->apf_reason) { |
1532 | default: | |
1533 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 | 1534 | |
631bc487 GN |
1535 | trace_kvm_page_fault(fault_address, error_code); |
1536 | if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu)) | |
1537 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
dc25e89e AP |
1538 | r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code, |
1539 | svm->vmcb->control.insn_bytes, | |
1540 | svm->vmcb->control.insn_len); | |
631bc487 GN |
1541 | break; |
1542 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
1543 | svm->apf_reason = 0; | |
1544 | local_irq_disable(); | |
1545 | kvm_async_pf_task_wait(fault_address); | |
1546 | local_irq_enable(); | |
1547 | break; | |
1548 | case KVM_PV_REASON_PAGE_READY: | |
1549 | svm->apf_reason = 0; | |
1550 | local_irq_disable(); | |
1551 | kvm_async_pf_task_wake(fault_address); | |
1552 | local_irq_enable(); | |
1553 | break; | |
1554 | } | |
1555 | return r; | |
6aa8b732 AK |
1556 | } |
1557 | ||
851ba692 | 1558 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 1559 | { |
851ba692 AK |
1560 | struct kvm_run *kvm_run = svm->vcpu.run; |
1561 | ||
d0bfb940 | 1562 | if (!(svm->vcpu.guest_debug & |
44c11430 | 1563 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 1564 | !svm->nmi_singlestep) { |
d0bfb940 JK |
1565 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
1566 | return 1; | |
1567 | } | |
44c11430 | 1568 | |
6be7d306 JK |
1569 | if (svm->nmi_singlestep) { |
1570 | svm->nmi_singlestep = false; | |
44c11430 GN |
1571 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) |
1572 | svm->vmcb->save.rflags &= | |
1573 | ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
1574 | update_db_intercept(&svm->vcpu); | |
1575 | } | |
1576 | ||
1577 | if (svm->vcpu.guest_debug & | |
e0231715 | 1578 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
1579 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1580 | kvm_run->debug.arch.pc = | |
1581 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1582 | kvm_run->debug.arch.exception = DB_VECTOR; | |
1583 | return 0; | |
1584 | } | |
1585 | ||
1586 | return 1; | |
d0bfb940 JK |
1587 | } |
1588 | ||
851ba692 | 1589 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 1590 | { |
851ba692 AK |
1591 | struct kvm_run *kvm_run = svm->vcpu.run; |
1592 | ||
d0bfb940 JK |
1593 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1594 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1595 | kvm_run->debug.arch.exception = BP_VECTOR; | |
1596 | return 0; | |
1597 | } | |
1598 | ||
851ba692 | 1599 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
1600 | { |
1601 | int er; | |
1602 | ||
51d8b661 | 1603 | er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1604 | if (er != EMULATE_DONE) |
7ee5d940 | 1605 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1606 | return 1; |
1607 | } | |
1608 | ||
6b52d186 | 1609 | static void svm_fpu_activate(struct kvm_vcpu *vcpu) |
7807fa6c | 1610 | { |
6b52d186 | 1611 | struct vcpu_svm *svm = to_svm(vcpu); |
66a562f7 | 1612 | |
18c918c5 | 1613 | clr_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 1614 | |
e756fc62 | 1615 | svm->vcpu.fpu_active = 1; |
d225157b | 1616 | update_cr0_intercept(svm); |
6b52d186 | 1617 | } |
a2fa3e9f | 1618 | |
6b52d186 AK |
1619 | static int nm_interception(struct vcpu_svm *svm) |
1620 | { | |
1621 | svm_fpu_activate(&svm->vcpu); | |
a2fa3e9f | 1622 | return 1; |
7807fa6c AL |
1623 | } |
1624 | ||
67ec6607 JR |
1625 | static bool is_erratum_383(void) |
1626 | { | |
1627 | int err, i; | |
1628 | u64 value; | |
1629 | ||
1630 | if (!erratum_383_found) | |
1631 | return false; | |
1632 | ||
1633 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
1634 | if (err) | |
1635 | return false; | |
1636 | ||
1637 | /* Bit 62 may or may not be set for this mce */ | |
1638 | value &= ~(1ULL << 62); | |
1639 | ||
1640 | if (value != 0xb600000000010015ULL) | |
1641 | return false; | |
1642 | ||
1643 | /* Clear MCi_STATUS registers */ | |
1644 | for (i = 0; i < 6; ++i) | |
1645 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
1646 | ||
1647 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
1648 | if (!err) { | |
1649 | u32 low, high; | |
1650 | ||
1651 | value &= ~(1ULL << 2); | |
1652 | low = lower_32_bits(value); | |
1653 | high = upper_32_bits(value); | |
1654 | ||
1655 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
1656 | } | |
1657 | ||
1658 | /* Flush tlb to evict multi-match entries */ | |
1659 | __flush_tlb_all(); | |
1660 | ||
1661 | return true; | |
1662 | } | |
1663 | ||
fe5913e4 | 1664 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 1665 | { |
67ec6607 JR |
1666 | if (is_erratum_383()) { |
1667 | /* | |
1668 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
1669 | * guest. | |
1670 | */ | |
1671 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
1672 | ||
a8eeb04a | 1673 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
1674 | |
1675 | return; | |
1676 | } | |
1677 | ||
53371b50 JR |
1678 | /* |
1679 | * On an #MC intercept the MCE handler is not called automatically in | |
1680 | * the host. So do it by hand here. | |
1681 | */ | |
1682 | asm volatile ( | |
1683 | "int $0x12\n"); | |
1684 | /* not sure if we ever come back to this point */ | |
1685 | ||
fe5913e4 JR |
1686 | return; |
1687 | } | |
1688 | ||
1689 | static int mc_interception(struct vcpu_svm *svm) | |
1690 | { | |
53371b50 JR |
1691 | return 1; |
1692 | } | |
1693 | ||
851ba692 | 1694 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 1695 | { |
851ba692 AK |
1696 | struct kvm_run *kvm_run = svm->vcpu.run; |
1697 | ||
46fe4ddd JR |
1698 | /* |
1699 | * VMCB is undefined after a SHUTDOWN intercept | |
1700 | * so reinitialize it. | |
1701 | */ | |
a2fa3e9f | 1702 | clear_page(svm->vmcb); |
e6101a96 | 1703 | init_vmcb(svm); |
46fe4ddd JR |
1704 | |
1705 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1706 | return 0; | |
1707 | } | |
1708 | ||
851ba692 | 1709 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 1710 | { |
cf8f70bf | 1711 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 1712 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
34c33d16 | 1713 | int size, in, string; |
039576c0 | 1714 | unsigned port; |
6aa8b732 | 1715 | |
e756fc62 | 1716 | ++svm->vcpu.stat.io_exits; |
e70669ab | 1717 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 1718 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
cf8f70bf | 1719 | if (string || in) |
51d8b661 | 1720 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
cf8f70bf | 1721 | |
039576c0 AK |
1722 | port = io_info >> 16; |
1723 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 1724 | svm->next_rip = svm->vmcb->control.exit_info_2; |
e93f36bc | 1725 | skip_emulated_instruction(&svm->vcpu); |
cf8f70bf GN |
1726 | |
1727 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
1728 | } |
1729 | ||
851ba692 | 1730 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
1731 | { |
1732 | return 1; | |
1733 | } | |
1734 | ||
851ba692 | 1735 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
1736 | { |
1737 | ++svm->vcpu.stat.irq_exits; | |
1738 | return 1; | |
1739 | } | |
1740 | ||
851ba692 | 1741 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
1742 | { |
1743 | return 1; | |
1744 | } | |
1745 | ||
851ba692 | 1746 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 1747 | { |
5fdbf976 | 1748 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 RR |
1749 | skip_emulated_instruction(&svm->vcpu); |
1750 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1751 | } |
1752 | ||
851ba692 | 1753 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 1754 | { |
5fdbf976 | 1755 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
e756fc62 | 1756 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1757 | kvm_emulate_hypercall(&svm->vcpu); |
1758 | return 1; | |
02e235bc AK |
1759 | } |
1760 | ||
5bd2edc3 JR |
1761 | static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) |
1762 | { | |
1763 | struct vcpu_svm *svm = to_svm(vcpu); | |
1764 | ||
1765 | return svm->nested.nested_cr3; | |
1766 | } | |
1767 | ||
1768 | static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu, | |
1769 | unsigned long root) | |
1770 | { | |
1771 | struct vcpu_svm *svm = to_svm(vcpu); | |
1772 | ||
1773 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 1774 | mark_dirty(svm->vmcb, VMCB_NPT); |
f40f6a45 | 1775 | svm_flush_tlb(vcpu); |
5bd2edc3 JR |
1776 | } |
1777 | ||
6389ee94 AK |
1778 | static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, |
1779 | struct x86_exception *fault) | |
5bd2edc3 JR |
1780 | { |
1781 | struct vcpu_svm *svm = to_svm(vcpu); | |
1782 | ||
1783 | svm->vmcb->control.exit_code = SVM_EXIT_NPF; | |
1784 | svm->vmcb->control.exit_code_hi = 0; | |
6389ee94 AK |
1785 | svm->vmcb->control.exit_info_1 = fault->error_code; |
1786 | svm->vmcb->control.exit_info_2 = fault->address; | |
5bd2edc3 JR |
1787 | |
1788 | nested_svm_vmexit(svm); | |
1789 | } | |
1790 | ||
4b16184c JR |
1791 | static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) |
1792 | { | |
1793 | int r; | |
1794 | ||
1795 | r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu); | |
1796 | ||
1797 | vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3; | |
1798 | vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3; | |
1799 | vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit; | |
1800 | vcpu->arch.mmu.shadow_root_level = get_npt_level(); | |
1801 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
1802 | ||
1803 | return r; | |
1804 | } | |
1805 | ||
1806 | static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
1807 | { | |
1808 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
1809 | } | |
1810 | ||
c0725420 AG |
1811 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
1812 | { | |
f6801dff | 1813 | if (!(svm->vcpu.arch.efer & EFER_SVME) |
c0725420 AG |
1814 | || !is_paging(&svm->vcpu)) { |
1815 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
1816 | return 1; | |
1817 | } | |
1818 | ||
1819 | if (svm->vmcb->save.cpl) { | |
1820 | kvm_inject_gp(&svm->vcpu, 0); | |
1821 | return 1; | |
1822 | } | |
1823 | ||
1824 | return 0; | |
1825 | } | |
1826 | ||
cf74a78b AG |
1827 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
1828 | bool has_error_code, u32 error_code) | |
1829 | { | |
b8e88bc8 JR |
1830 | int vmexit; |
1831 | ||
2030753d | 1832 | if (!is_guest_mode(&svm->vcpu)) |
0295ad7d | 1833 | return 0; |
cf74a78b | 1834 | |
0295ad7d JR |
1835 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
1836 | svm->vmcb->control.exit_code_hi = 0; | |
1837 | svm->vmcb->control.exit_info_1 = error_code; | |
1838 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
1839 | ||
b8e88bc8 JR |
1840 | vmexit = nested_svm_intercept(svm); |
1841 | if (vmexit == NESTED_EXIT_DONE) | |
1842 | svm->nested.exit_required = true; | |
1843 | ||
1844 | return vmexit; | |
cf74a78b AG |
1845 | } |
1846 | ||
8fe54654 JR |
1847 | /* This function returns true if it is save to enable the irq window */ |
1848 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 1849 | { |
2030753d | 1850 | if (!is_guest_mode(&svm->vcpu)) |
8fe54654 | 1851 | return true; |
cf74a78b | 1852 | |
26666957 | 1853 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 1854 | return true; |
cf74a78b | 1855 | |
26666957 | 1856 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 1857 | return false; |
cf74a78b | 1858 | |
a0a07cd2 GN |
1859 | /* |
1860 | * if vmexit was already requested (by intercepted exception | |
1861 | * for instance) do not overwrite it with "external interrupt" | |
1862 | * vmexit. | |
1863 | */ | |
1864 | if (svm->nested.exit_required) | |
1865 | return false; | |
1866 | ||
197717d5 JR |
1867 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
1868 | svm->vmcb->control.exit_info_1 = 0; | |
1869 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 1870 | |
cd3ff653 JR |
1871 | if (svm->nested.intercept & 1ULL) { |
1872 | /* | |
1873 | * The #vmexit can't be emulated here directly because this | |
1874 | * code path runs with irqs and preemtion disabled. A | |
1875 | * #vmexit emulation might sleep. Only signal request for | |
1876 | * the #vmexit here. | |
1877 | */ | |
1878 | svm->nested.exit_required = true; | |
236649de | 1879 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 1880 | return false; |
cf74a78b AG |
1881 | } |
1882 | ||
8fe54654 | 1883 | return true; |
cf74a78b AG |
1884 | } |
1885 | ||
887f500c JR |
1886 | /* This function returns true if it is save to enable the nmi window */ |
1887 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
1888 | { | |
2030753d | 1889 | if (!is_guest_mode(&svm->vcpu)) |
887f500c JR |
1890 | return true; |
1891 | ||
1892 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
1893 | return true; | |
1894 | ||
1895 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
1896 | svm->nested.exit_required = true; | |
1897 | ||
1898 | return false; | |
cf74a78b AG |
1899 | } |
1900 | ||
7597f129 | 1901 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) |
34f80cfa JR |
1902 | { |
1903 | struct page *page; | |
1904 | ||
6c3bd3d7 JR |
1905 | might_sleep(); |
1906 | ||
34f80cfa | 1907 | page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT); |
34f80cfa JR |
1908 | if (is_error_page(page)) |
1909 | goto error; | |
1910 | ||
7597f129 JR |
1911 | *_page = page; |
1912 | ||
1913 | return kmap(page); | |
34f80cfa JR |
1914 | |
1915 | error: | |
1916 | kvm_release_page_clean(page); | |
1917 | kvm_inject_gp(&svm->vcpu, 0); | |
1918 | ||
1919 | return NULL; | |
1920 | } | |
1921 | ||
7597f129 | 1922 | static void nested_svm_unmap(struct page *page) |
34f80cfa | 1923 | { |
7597f129 | 1924 | kunmap(page); |
34f80cfa JR |
1925 | kvm_release_page_dirty(page); |
1926 | } | |
34f80cfa | 1927 | |
ce2ac085 JR |
1928 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
1929 | { | |
1930 | unsigned port; | |
1931 | u8 val, bit; | |
1932 | u64 gpa; | |
34f80cfa | 1933 | |
ce2ac085 JR |
1934 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
1935 | return NESTED_EXIT_HOST; | |
34f80cfa | 1936 | |
ce2ac085 JR |
1937 | port = svm->vmcb->control.exit_info_1 >> 16; |
1938 | gpa = svm->nested.vmcb_iopm + (port / 8); | |
1939 | bit = port % 8; | |
1940 | val = 0; | |
1941 | ||
1942 | if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1)) | |
1943 | val &= (1 << bit); | |
1944 | ||
1945 | return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; | |
34f80cfa JR |
1946 | } |
1947 | ||
d2477826 | 1948 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 1949 | { |
0d6b3537 JR |
1950 | u32 offset, msr, value; |
1951 | int write, mask; | |
4c2161ae | 1952 | |
3d62d9aa | 1953 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 1954 | return NESTED_EXIT_HOST; |
3d62d9aa | 1955 | |
0d6b3537 JR |
1956 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
1957 | offset = svm_msrpm_offset(msr); | |
1958 | write = svm->vmcb->control.exit_info_1 & 1; | |
1959 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 1960 | |
0d6b3537 JR |
1961 | if (offset == MSR_INVALID) |
1962 | return NESTED_EXIT_DONE; | |
4c2161ae | 1963 | |
0d6b3537 JR |
1964 | /* Offset is in 32 bit units but need in 8 bit units */ |
1965 | offset *= 4; | |
4c2161ae | 1966 | |
0d6b3537 JR |
1967 | if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4)) |
1968 | return NESTED_EXIT_DONE; | |
3d62d9aa | 1969 | |
0d6b3537 | 1970 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
1971 | } |
1972 | ||
410e4d57 | 1973 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 1974 | { |
cf74a78b | 1975 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 1976 | |
410e4d57 JR |
1977 | switch (exit_code) { |
1978 | case SVM_EXIT_INTR: | |
1979 | case SVM_EXIT_NMI: | |
ff47a49b | 1980 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 1981 | return NESTED_EXIT_HOST; |
410e4d57 | 1982 | case SVM_EXIT_NPF: |
e0231715 | 1983 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
1984 | if (npt_enabled) |
1985 | return NESTED_EXIT_HOST; | |
1986 | break; | |
410e4d57 | 1987 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
631bc487 GN |
1988 | /* When we're shadowing, trap PFs, but not async PF */ |
1989 | if (!npt_enabled && svm->apf_reason == 0) | |
410e4d57 JR |
1990 | return NESTED_EXIT_HOST; |
1991 | break; | |
66a562f7 JR |
1992 | case SVM_EXIT_EXCP_BASE + NM_VECTOR: |
1993 | nm_interception(svm); | |
1994 | break; | |
410e4d57 JR |
1995 | default: |
1996 | break; | |
cf74a78b AG |
1997 | } |
1998 | ||
410e4d57 JR |
1999 | return NESTED_EXIT_CONTINUE; |
2000 | } | |
2001 | ||
2002 | /* | |
2003 | * If this function returns true, this #vmexit was already handled | |
2004 | */ | |
b8e88bc8 | 2005 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
2006 | { |
2007 | u32 exit_code = svm->vmcb->control.exit_code; | |
2008 | int vmexit = NESTED_EXIT_HOST; | |
2009 | ||
cf74a78b | 2010 | switch (exit_code) { |
9c4e40b9 | 2011 | case SVM_EXIT_MSR: |
3d62d9aa | 2012 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 2013 | break; |
ce2ac085 JR |
2014 | case SVM_EXIT_IOIO: |
2015 | vmexit = nested_svm_intercept_ioio(svm); | |
2016 | break; | |
4ee546b4 RJ |
2017 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: { |
2018 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0); | |
2019 | if (svm->nested.intercept_cr & bit) | |
410e4d57 | 2020 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2021 | break; |
2022 | } | |
3aed041a JR |
2023 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: { |
2024 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0); | |
2025 | if (svm->nested.intercept_dr & bit) | |
410e4d57 | 2026 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2027 | break; |
2028 | } | |
2029 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
2030 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
aad42c64 | 2031 | if (svm->nested.intercept_exceptions & excp_bits) |
410e4d57 | 2032 | vmexit = NESTED_EXIT_DONE; |
631bc487 GN |
2033 | /* async page fault always cause vmexit */ |
2034 | else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) && | |
2035 | svm->apf_reason != 0) | |
2036 | vmexit = NESTED_EXIT_DONE; | |
cf74a78b AG |
2037 | break; |
2038 | } | |
228070b1 JR |
2039 | case SVM_EXIT_ERR: { |
2040 | vmexit = NESTED_EXIT_DONE; | |
2041 | break; | |
2042 | } | |
cf74a78b AG |
2043 | default: { |
2044 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 2045 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 2046 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2047 | } |
2048 | } | |
2049 | ||
b8e88bc8 JR |
2050 | return vmexit; |
2051 | } | |
2052 | ||
2053 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
2054 | { | |
2055 | int vmexit; | |
2056 | ||
2057 | vmexit = nested_svm_intercept(svm); | |
2058 | ||
2059 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 2060 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
2061 | |
2062 | return vmexit; | |
cf74a78b AG |
2063 | } |
2064 | ||
0460a979 JR |
2065 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
2066 | { | |
2067 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
2068 | struct vmcb_control_area *from = &from_vmcb->control; | |
2069 | ||
4ee546b4 | 2070 | dst->intercept_cr = from->intercept_cr; |
3aed041a | 2071 | dst->intercept_dr = from->intercept_dr; |
0460a979 JR |
2072 | dst->intercept_exceptions = from->intercept_exceptions; |
2073 | dst->intercept = from->intercept; | |
2074 | dst->iopm_base_pa = from->iopm_base_pa; | |
2075 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
2076 | dst->tsc_offset = from->tsc_offset; | |
2077 | dst->asid = from->asid; | |
2078 | dst->tlb_ctl = from->tlb_ctl; | |
2079 | dst->int_ctl = from->int_ctl; | |
2080 | dst->int_vector = from->int_vector; | |
2081 | dst->int_state = from->int_state; | |
2082 | dst->exit_code = from->exit_code; | |
2083 | dst->exit_code_hi = from->exit_code_hi; | |
2084 | dst->exit_info_1 = from->exit_info_1; | |
2085 | dst->exit_info_2 = from->exit_info_2; | |
2086 | dst->exit_int_info = from->exit_int_info; | |
2087 | dst->exit_int_info_err = from->exit_int_info_err; | |
2088 | dst->nested_ctl = from->nested_ctl; | |
2089 | dst->event_inj = from->event_inj; | |
2090 | dst->event_inj_err = from->event_inj_err; | |
2091 | dst->nested_cr3 = from->nested_cr3; | |
2092 | dst->lbr_ctl = from->lbr_ctl; | |
2093 | } | |
2094 | ||
34f80cfa | 2095 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 2096 | { |
34f80cfa | 2097 | struct vmcb *nested_vmcb; |
e6aa9abd | 2098 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 2099 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2100 | struct page *page; |
cf74a78b | 2101 | |
17897f36 JR |
2102 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
2103 | vmcb->control.exit_info_1, | |
2104 | vmcb->control.exit_info_2, | |
2105 | vmcb->control.exit_int_info, | |
2106 | vmcb->control.exit_int_info_err); | |
2107 | ||
7597f129 | 2108 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); |
34f80cfa JR |
2109 | if (!nested_vmcb) |
2110 | return 1; | |
2111 | ||
2030753d JR |
2112 | /* Exit Guest-Mode */ |
2113 | leave_guest_mode(&svm->vcpu); | |
06fc7772 JR |
2114 | svm->nested.vmcb = 0; |
2115 | ||
cf74a78b | 2116 | /* Give the current vmcb to the guest */ |
33740e40 JR |
2117 | disable_gif(svm); |
2118 | ||
2119 | nested_vmcb->save.es = vmcb->save.es; | |
2120 | nested_vmcb->save.cs = vmcb->save.cs; | |
2121 | nested_vmcb->save.ss = vmcb->save.ss; | |
2122 | nested_vmcb->save.ds = vmcb->save.ds; | |
2123 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
2124 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
3f6a9d16 | 2125 | nested_vmcb->save.efer = svm->vcpu.arch.efer; |
cdbbdc12 | 2126 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
9f8fe504 | 2127 | nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu); |
33740e40 | 2128 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 2129 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
33740e40 JR |
2130 | nested_vmcb->save.rflags = vmcb->save.rflags; |
2131 | nested_vmcb->save.rip = vmcb->save.rip; | |
2132 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
2133 | nested_vmcb->save.rax = vmcb->save.rax; | |
2134 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
2135 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
2136 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
2137 | ||
2138 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
2139 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
2140 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
2141 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
2142 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
2143 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
2144 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
2145 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
2146 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
7a190667 | 2147 | nested_vmcb->control.next_rip = vmcb->control.next_rip; |
8d23c466 AG |
2148 | |
2149 | /* | |
2150 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
2151 | * to make sure that we do not lose injected events. So check event_inj | |
2152 | * here and copy it to exit_int_info if it is valid. | |
2153 | * Exit_int_info and event_inj can't be both valid because the case | |
2154 | * below only happens on a VMRUN instruction intercept which has | |
2155 | * no valid exit_int_info set. | |
2156 | */ | |
2157 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
2158 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
2159 | ||
2160 | nc->exit_int_info = vmcb->control.event_inj; | |
2161 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
2162 | } | |
2163 | ||
33740e40 JR |
2164 | nested_vmcb->control.tlb_ctl = 0; |
2165 | nested_vmcb->control.event_inj = 0; | |
2166 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
2167 | |
2168 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
2169 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
2170 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
2171 | ||
cf74a78b | 2172 | /* Restore the original control entries */ |
0460a979 | 2173 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 2174 | |
219b65dc AG |
2175 | kvm_clear_exception_queue(&svm->vcpu); |
2176 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b | 2177 | |
4b16184c JR |
2178 | svm->nested.nested_cr3 = 0; |
2179 | ||
cf74a78b AG |
2180 | /* Restore selected save entries */ |
2181 | svm->vmcb->save.es = hsave->save.es; | |
2182 | svm->vmcb->save.cs = hsave->save.cs; | |
2183 | svm->vmcb->save.ss = hsave->save.ss; | |
2184 | svm->vmcb->save.ds = hsave->save.ds; | |
2185 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
2186 | svm->vmcb->save.idtr = hsave->save.idtr; | |
2187 | svm->vmcb->save.rflags = hsave->save.rflags; | |
2188 | svm_set_efer(&svm->vcpu, hsave->save.efer); | |
2189 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
2190 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
2191 | if (npt_enabled) { | |
2192 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
2193 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
2194 | } else { | |
2390218b | 2195 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b AG |
2196 | } |
2197 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
2198 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
2199 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
2200 | svm->vmcb->save.dr7 = 0; | |
2201 | svm->vmcb->save.cpl = 0; | |
2202 | svm->vmcb->control.exit_int_info = 0; | |
2203 | ||
8d28fec4 RJ |
2204 | mark_all_dirty(svm->vmcb); |
2205 | ||
7597f129 | 2206 | nested_svm_unmap(page); |
cf74a78b | 2207 | |
4b16184c | 2208 | nested_svm_uninit_mmu_context(&svm->vcpu); |
cf74a78b AG |
2209 | kvm_mmu_reset_context(&svm->vcpu); |
2210 | kvm_mmu_load(&svm->vcpu); | |
2211 | ||
2212 | return 0; | |
2213 | } | |
3d6368ef | 2214 | |
9738b2c9 | 2215 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 2216 | { |
323c3d80 JR |
2217 | /* |
2218 | * This function merges the msr permission bitmaps of kvm and the | |
2219 | * nested vmcb. It is omptimized in that it only merges the parts where | |
2220 | * the kvm msr permission bitmap may contain zero bits | |
2221 | */ | |
3d6368ef | 2222 | int i; |
9738b2c9 | 2223 | |
323c3d80 JR |
2224 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
2225 | return true; | |
9738b2c9 | 2226 | |
323c3d80 JR |
2227 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
2228 | u32 value, p; | |
2229 | u64 offset; | |
9738b2c9 | 2230 | |
323c3d80 JR |
2231 | if (msrpm_offsets[i] == 0xffffffff) |
2232 | break; | |
3d6368ef | 2233 | |
0d6b3537 JR |
2234 | p = msrpm_offsets[i]; |
2235 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 JR |
2236 | |
2237 | if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4)) | |
2238 | return false; | |
2239 | ||
2240 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
2241 | } | |
3d6368ef | 2242 | |
323c3d80 | 2243 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); |
9738b2c9 JR |
2244 | |
2245 | return true; | |
3d6368ef AG |
2246 | } |
2247 | ||
52c65a30 JR |
2248 | static bool nested_vmcb_checks(struct vmcb *vmcb) |
2249 | { | |
2250 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
2251 | return false; | |
2252 | ||
dbe77584 JR |
2253 | if (vmcb->control.asid == 0) |
2254 | return false; | |
2255 | ||
4b16184c JR |
2256 | if (vmcb->control.nested_ctl && !npt_enabled) |
2257 | return false; | |
2258 | ||
52c65a30 JR |
2259 | return true; |
2260 | } | |
2261 | ||
9738b2c9 | 2262 | static bool nested_svm_vmrun(struct vcpu_svm *svm) |
3d6368ef | 2263 | { |
9738b2c9 | 2264 | struct vmcb *nested_vmcb; |
e6aa9abd | 2265 | struct vmcb *hsave = svm->nested.hsave; |
defbba56 | 2266 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2267 | struct page *page; |
06fc7772 | 2268 | u64 vmcb_gpa; |
3d6368ef | 2269 | |
06fc7772 | 2270 | vmcb_gpa = svm->vmcb->save.rax; |
3d6368ef | 2271 | |
7597f129 | 2272 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9738b2c9 JR |
2273 | if (!nested_vmcb) |
2274 | return false; | |
2275 | ||
52c65a30 JR |
2276 | if (!nested_vmcb_checks(nested_vmcb)) { |
2277 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
2278 | nested_vmcb->control.exit_code_hi = 0; | |
2279 | nested_vmcb->control.exit_info_1 = 0; | |
2280 | nested_vmcb->control.exit_info_2 = 0; | |
2281 | ||
2282 | nested_svm_unmap(page); | |
2283 | ||
2284 | return false; | |
2285 | } | |
2286 | ||
b75f4eb3 | 2287 | trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa, |
0ac406de JR |
2288 | nested_vmcb->save.rip, |
2289 | nested_vmcb->control.int_ctl, | |
2290 | nested_vmcb->control.event_inj, | |
2291 | nested_vmcb->control.nested_ctl); | |
2292 | ||
4ee546b4 RJ |
2293 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, |
2294 | nested_vmcb->control.intercept_cr >> 16, | |
2e554e8d JR |
2295 | nested_vmcb->control.intercept_exceptions, |
2296 | nested_vmcb->control.intercept); | |
2297 | ||
3d6368ef | 2298 | /* Clear internal status */ |
219b65dc AG |
2299 | kvm_clear_exception_queue(&svm->vcpu); |
2300 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3d6368ef | 2301 | |
e0231715 JR |
2302 | /* |
2303 | * Save the old vmcb, so we don't need to pick what we save, but can | |
2304 | * restore everything when a VMEXIT occurs | |
2305 | */ | |
defbba56 JR |
2306 | hsave->save.es = vmcb->save.es; |
2307 | hsave->save.cs = vmcb->save.cs; | |
2308 | hsave->save.ss = vmcb->save.ss; | |
2309 | hsave->save.ds = vmcb->save.ds; | |
2310 | hsave->save.gdtr = vmcb->save.gdtr; | |
2311 | hsave->save.idtr = vmcb->save.idtr; | |
f6801dff | 2312 | hsave->save.efer = svm->vcpu.arch.efer; |
4d4ec087 | 2313 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); |
defbba56 JR |
2314 | hsave->save.cr4 = svm->vcpu.arch.cr4; |
2315 | hsave->save.rflags = vmcb->save.rflags; | |
b75f4eb3 | 2316 | hsave->save.rip = kvm_rip_read(&svm->vcpu); |
defbba56 JR |
2317 | hsave->save.rsp = vmcb->save.rsp; |
2318 | hsave->save.rax = vmcb->save.rax; | |
2319 | if (npt_enabled) | |
2320 | hsave->save.cr3 = vmcb->save.cr3; | |
2321 | else | |
9f8fe504 | 2322 | hsave->save.cr3 = kvm_read_cr3(&svm->vcpu); |
defbba56 | 2323 | |
0460a979 | 2324 | copy_vmcb_control_area(hsave, vmcb); |
3d6368ef AG |
2325 | |
2326 | if (svm->vmcb->save.rflags & X86_EFLAGS_IF) | |
2327 | svm->vcpu.arch.hflags |= HF_HIF_MASK; | |
2328 | else | |
2329 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
2330 | ||
4b16184c JR |
2331 | if (nested_vmcb->control.nested_ctl) { |
2332 | kvm_mmu_unload(&svm->vcpu); | |
2333 | svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; | |
2334 | nested_svm_init_mmu_context(&svm->vcpu); | |
2335 | } | |
2336 | ||
3d6368ef AG |
2337 | /* Load the nested guest state */ |
2338 | svm->vmcb->save.es = nested_vmcb->save.es; | |
2339 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
2340 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
2341 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
2342 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
2343 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
2344 | svm->vmcb->save.rflags = nested_vmcb->save.rflags; | |
2345 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); | |
2346 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
2347 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
2348 | if (npt_enabled) { | |
2349 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
2350 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 2351 | } else |
2390218b | 2352 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
2353 | |
2354 | /* Guest paging mode is active - reset mmu */ | |
2355 | kvm_mmu_reset_context(&svm->vcpu); | |
2356 | ||
defbba56 | 2357 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
2358 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
2359 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
2360 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
e0231715 | 2361 | |
3d6368ef AG |
2362 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
2363 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
2364 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
2365 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
2366 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
2367 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
2368 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
2369 | ||
f7138538 | 2370 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 2371 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 2372 | |
aad42c64 | 2373 | /* cache intercepts */ |
4ee546b4 | 2374 | svm->nested.intercept_cr = nested_vmcb->control.intercept_cr; |
3aed041a | 2375 | svm->nested.intercept_dr = nested_vmcb->control.intercept_dr; |
aad42c64 JR |
2376 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; |
2377 | svm->nested.intercept = nested_vmcb->control.intercept; | |
2378 | ||
f40f6a45 | 2379 | svm_flush_tlb(&svm->vcpu); |
3d6368ef | 2380 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
2381 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
2382 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
2383 | else | |
2384 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
2385 | ||
88ab24ad JR |
2386 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
2387 | /* We only want the cr8 intercept bits of the guest */ | |
4ee546b4 RJ |
2388 | clr_cr_intercept(svm, INTERCEPT_CR8_READ); |
2389 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
88ab24ad JR |
2390 | } |
2391 | ||
0d945bd9 | 2392 | /* We don't want to see VMMCALLs from a nested guest */ |
8a05a1b8 | 2393 | clr_intercept(svm, INTERCEPT_VMMCALL); |
0d945bd9 | 2394 | |
88ab24ad | 2395 | svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl; |
3d6368ef AG |
2396 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
2397 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
2398 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
2399 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
2400 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
2401 | ||
7597f129 | 2402 | nested_svm_unmap(page); |
9738b2c9 | 2403 | |
2030753d JR |
2404 | /* Enter Guest-Mode */ |
2405 | enter_guest_mode(&svm->vcpu); | |
2406 | ||
384c6368 JR |
2407 | /* |
2408 | * Merge guest and host intercepts - must be called with vcpu in | |
2409 | * guest-mode to take affect here | |
2410 | */ | |
2411 | recalc_intercepts(svm); | |
2412 | ||
06fc7772 | 2413 | svm->nested.vmcb = vmcb_gpa; |
9738b2c9 | 2414 | |
2af9194d | 2415 | enable_gif(svm); |
3d6368ef | 2416 | |
8d28fec4 RJ |
2417 | mark_all_dirty(svm->vmcb); |
2418 | ||
9738b2c9 | 2419 | return true; |
3d6368ef AG |
2420 | } |
2421 | ||
9966bf68 | 2422 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
2423 | { |
2424 | to_vmcb->save.fs = from_vmcb->save.fs; | |
2425 | to_vmcb->save.gs = from_vmcb->save.gs; | |
2426 | to_vmcb->save.tr = from_vmcb->save.tr; | |
2427 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
2428 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
2429 | to_vmcb->save.star = from_vmcb->save.star; | |
2430 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
2431 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
2432 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
2433 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
2434 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
2435 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
2436 | } |
2437 | ||
851ba692 | 2438 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 2439 | { |
9966bf68 | 2440 | struct vmcb *nested_vmcb; |
7597f129 | 2441 | struct page *page; |
9966bf68 | 2442 | |
5542675b AG |
2443 | if (nested_svm_check_permissions(svm)) |
2444 | return 1; | |
2445 | ||
2446 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2447 | skip_emulated_instruction(&svm->vcpu); | |
2448 | ||
7597f129 | 2449 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2450 | if (!nested_vmcb) |
2451 | return 1; | |
2452 | ||
2453 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); | |
7597f129 | 2454 | nested_svm_unmap(page); |
5542675b AG |
2455 | |
2456 | return 1; | |
2457 | } | |
2458 | ||
851ba692 | 2459 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 2460 | { |
9966bf68 | 2461 | struct vmcb *nested_vmcb; |
7597f129 | 2462 | struct page *page; |
9966bf68 | 2463 | |
5542675b AG |
2464 | if (nested_svm_check_permissions(svm)) |
2465 | return 1; | |
2466 | ||
2467 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2468 | skip_emulated_instruction(&svm->vcpu); | |
2469 | ||
7597f129 | 2470 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2471 | if (!nested_vmcb) |
2472 | return 1; | |
2473 | ||
2474 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); | |
7597f129 | 2475 | nested_svm_unmap(page); |
5542675b AG |
2476 | |
2477 | return 1; | |
2478 | } | |
2479 | ||
851ba692 | 2480 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 2481 | { |
3d6368ef AG |
2482 | if (nested_svm_check_permissions(svm)) |
2483 | return 1; | |
2484 | ||
b75f4eb3 RJ |
2485 | /* Save rip after vmrun instruction */ |
2486 | kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3); | |
3d6368ef | 2487 | |
9738b2c9 | 2488 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
2489 | return 1; |
2490 | ||
9738b2c9 | 2491 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
2492 | goto failed; |
2493 | ||
2494 | return 1; | |
2495 | ||
2496 | failed: | |
2497 | ||
2498 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
2499 | svm->vmcb->control.exit_code_hi = 0; | |
2500 | svm->vmcb->control.exit_info_1 = 0; | |
2501 | svm->vmcb->control.exit_info_2 = 0; | |
2502 | ||
2503 | nested_svm_vmexit(svm); | |
3d6368ef AG |
2504 | |
2505 | return 1; | |
2506 | } | |
2507 | ||
851ba692 | 2508 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2509 | { |
2510 | if (nested_svm_check_permissions(svm)) | |
2511 | return 1; | |
2512 | ||
2513 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2514 | skip_emulated_instruction(&svm->vcpu); | |
3842d135 | 2515 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
1371d904 | 2516 | |
2af9194d | 2517 | enable_gif(svm); |
1371d904 AG |
2518 | |
2519 | return 1; | |
2520 | } | |
2521 | ||
851ba692 | 2522 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2523 | { |
2524 | if (nested_svm_check_permissions(svm)) | |
2525 | return 1; | |
2526 | ||
2527 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2528 | skip_emulated_instruction(&svm->vcpu); | |
2529 | ||
2af9194d | 2530 | disable_gif(svm); |
1371d904 AG |
2531 | |
2532 | /* After a CLGI no interrupts should come */ | |
2533 | svm_clear_vintr(svm); | |
2534 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
2535 | ||
decdbf6a JR |
2536 | mark_dirty(svm->vmcb, VMCB_INTR); |
2537 | ||
1371d904 AG |
2538 | return 1; |
2539 | } | |
2540 | ||
851ba692 | 2541 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
2542 | { |
2543 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 2544 | |
ec1ff790 JR |
2545 | trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX], |
2546 | vcpu->arch.regs[VCPU_REGS_RAX]); | |
2547 | ||
ff092385 AG |
2548 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
2549 | kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]); | |
2550 | ||
2551 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2552 | skip_emulated_instruction(&svm->vcpu); | |
2553 | return 1; | |
2554 | } | |
2555 | ||
532a46b9 JR |
2556 | static int skinit_interception(struct vcpu_svm *svm) |
2557 | { | |
2558 | trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]); | |
2559 | ||
2560 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2561 | return 1; | |
2562 | } | |
2563 | ||
81dd35d4 JR |
2564 | static int xsetbv_interception(struct vcpu_svm *svm) |
2565 | { | |
2566 | u64 new_bv = kvm_read_edx_eax(&svm->vcpu); | |
2567 | u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); | |
2568 | ||
2569 | if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) { | |
2570 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2571 | skip_emulated_instruction(&svm->vcpu); | |
2572 | } | |
2573 | ||
2574 | return 1; | |
2575 | } | |
2576 | ||
851ba692 | 2577 | static int invalid_op_interception(struct vcpu_svm *svm) |
6aa8b732 | 2578 | { |
7ee5d940 | 2579 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
2580 | return 1; |
2581 | } | |
2582 | ||
851ba692 | 2583 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 2584 | { |
37817f29 | 2585 | u16 tss_selector; |
64a7ec06 GN |
2586 | int reason; |
2587 | int int_type = svm->vmcb->control.exit_int_info & | |
2588 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 2589 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
2590 | uint32_t type = |
2591 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
2592 | uint32_t idt_v = | |
2593 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
2594 | bool has_error_code = false; |
2595 | u32 error_code = 0; | |
37817f29 IE |
2596 | |
2597 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 2598 | |
37817f29 IE |
2599 | if (svm->vmcb->control.exit_info_2 & |
2600 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
2601 | reason = TASK_SWITCH_IRET; |
2602 | else if (svm->vmcb->control.exit_info_2 & | |
2603 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
2604 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 2605 | else if (idt_v) |
64a7ec06 GN |
2606 | reason = TASK_SWITCH_GATE; |
2607 | else | |
2608 | reason = TASK_SWITCH_CALL; | |
2609 | ||
fe8e7f83 GN |
2610 | if (reason == TASK_SWITCH_GATE) { |
2611 | switch (type) { | |
2612 | case SVM_EXITINTINFO_TYPE_NMI: | |
2613 | svm->vcpu.arch.nmi_injected = false; | |
2614 | break; | |
2615 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
2616 | if (svm->vmcb->control.exit_info_2 & |
2617 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
2618 | has_error_code = true; | |
2619 | error_code = | |
2620 | (u32)svm->vmcb->control.exit_info_2; | |
2621 | } | |
fe8e7f83 GN |
2622 | kvm_clear_exception_queue(&svm->vcpu); |
2623 | break; | |
2624 | case SVM_EXITINTINFO_TYPE_INTR: | |
2625 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2626 | break; | |
2627 | default: | |
2628 | break; | |
2629 | } | |
2630 | } | |
64a7ec06 | 2631 | |
8317c298 GN |
2632 | if (reason != TASK_SWITCH_GATE || |
2633 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
2634 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
2635 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
2636 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 | 2637 | |
acb54517 GN |
2638 | if (kvm_task_switch(&svm->vcpu, tss_selector, reason, |
2639 | has_error_code, error_code) == EMULATE_FAIL) { | |
2640 | svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
2641 | svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
2642 | svm->vcpu.run->internal.ndata = 0; | |
2643 | return 0; | |
2644 | } | |
2645 | return 1; | |
6aa8b732 AK |
2646 | } |
2647 | ||
851ba692 | 2648 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 2649 | { |
5fdbf976 | 2650 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2651 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 2652 | return 1; |
6aa8b732 AK |
2653 | } |
2654 | ||
851ba692 | 2655 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
2656 | { |
2657 | ++svm->vcpu.stat.nmi_window_exits; | |
8a05a1b8 | 2658 | clr_intercept(svm, INTERCEPT_IRET); |
44c11430 | 2659 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
bd3d1ec3 | 2660 | svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu); |
95ba8273 GN |
2661 | return 1; |
2662 | } | |
2663 | ||
851ba692 | 2664 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 2665 | { |
df4f3108 AP |
2666 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) |
2667 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; | |
2668 | ||
2669 | kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1); | |
2670 | skip_emulated_instruction(&svm->vcpu); | |
2671 | return 1; | |
a7052897 MT |
2672 | } |
2673 | ||
851ba692 | 2674 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 2675 | { |
51d8b661 | 2676 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; |
6aa8b732 AK |
2677 | } |
2678 | ||
7ff76d58 AP |
2679 | #define CR_VALID (1ULL << 63) |
2680 | ||
2681 | static int cr_interception(struct vcpu_svm *svm) | |
2682 | { | |
2683 | int reg, cr; | |
2684 | unsigned long val; | |
2685 | int err; | |
2686 | ||
2687 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
2688 | return emulate_on_interception(svm); | |
2689 | ||
2690 | if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) | |
2691 | return emulate_on_interception(svm); | |
2692 | ||
2693 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
2694 | cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0; | |
2695 | ||
2696 | err = 0; | |
2697 | if (cr >= 16) { /* mov to cr */ | |
2698 | cr -= 16; | |
2699 | val = kvm_register_read(&svm->vcpu, reg); | |
2700 | switch (cr) { | |
2701 | case 0: | |
2702 | err = kvm_set_cr0(&svm->vcpu, val); | |
2703 | break; | |
2704 | case 3: | |
2705 | err = kvm_set_cr3(&svm->vcpu, val); | |
2706 | break; | |
2707 | case 4: | |
2708 | err = kvm_set_cr4(&svm->vcpu, val); | |
2709 | break; | |
2710 | case 8: | |
2711 | err = kvm_set_cr8(&svm->vcpu, val); | |
2712 | break; | |
2713 | default: | |
2714 | WARN(1, "unhandled write to CR%d", cr); | |
2715 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2716 | return 1; | |
2717 | } | |
2718 | } else { /* mov from cr */ | |
2719 | switch (cr) { | |
2720 | case 0: | |
2721 | val = kvm_read_cr0(&svm->vcpu); | |
2722 | break; | |
2723 | case 2: | |
2724 | val = svm->vcpu.arch.cr2; | |
2725 | break; | |
2726 | case 3: | |
9f8fe504 | 2727 | val = kvm_read_cr3(&svm->vcpu); |
7ff76d58 AP |
2728 | break; |
2729 | case 4: | |
2730 | val = kvm_read_cr4(&svm->vcpu); | |
2731 | break; | |
2732 | case 8: | |
2733 | val = kvm_get_cr8(&svm->vcpu); | |
2734 | break; | |
2735 | default: | |
2736 | WARN(1, "unhandled read from CR%d", cr); | |
2737 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2738 | return 1; | |
2739 | } | |
2740 | kvm_register_write(&svm->vcpu, reg, val); | |
2741 | } | |
2742 | kvm_complete_insn_gp(&svm->vcpu, err); | |
2743 | ||
2744 | return 1; | |
2745 | } | |
2746 | ||
cda00082 JR |
2747 | static int cr0_write_interception(struct vcpu_svm *svm) |
2748 | { | |
2749 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
2750 | int r; | |
2751 | ||
7ff76d58 | 2752 | r = cr_interception(svm); |
cda00082 JR |
2753 | |
2754 | if (svm->nested.vmexit_rip) { | |
2755 | kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip); | |
2756 | kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp); | |
2757 | kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax); | |
2758 | svm->nested.vmexit_rip = 0; | |
2759 | } | |
2760 | ||
7ff76d58 | 2761 | return r; |
cda00082 JR |
2762 | } |
2763 | ||
cae3797a AP |
2764 | static int dr_interception(struct vcpu_svm *svm) |
2765 | { | |
2766 | int reg, dr; | |
2767 | unsigned long val; | |
2768 | int err; | |
2769 | ||
2770 | if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
2771 | return emulate_on_interception(svm); | |
2772 | ||
2773 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
2774 | dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0; | |
2775 | ||
2776 | if (dr >= 16) { /* mov to DRn */ | |
2777 | val = kvm_register_read(&svm->vcpu, reg); | |
2778 | kvm_set_dr(&svm->vcpu, dr - 16, val); | |
2779 | } else { | |
2780 | err = kvm_get_dr(&svm->vcpu, dr, &val); | |
2781 | if (!err) | |
2782 | kvm_register_write(&svm->vcpu, reg, val); | |
2783 | } | |
2784 | ||
2c46d2ae JR |
2785 | skip_emulated_instruction(&svm->vcpu); |
2786 | ||
cae3797a AP |
2787 | return 1; |
2788 | } | |
2789 | ||
851ba692 | 2790 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 2791 | { |
851ba692 | 2792 | struct kvm_run *kvm_run = svm->vcpu.run; |
eea1cff9 | 2793 | int r; |
851ba692 | 2794 | |
0a5fff19 GN |
2795 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
2796 | /* instruction emulation calls kvm_set_cr8() */ | |
7ff76d58 | 2797 | r = cr_interception(svm); |
95ba8273 | 2798 | if (irqchip_in_kernel(svm->vcpu.kvm)) { |
4ee546b4 | 2799 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
7ff76d58 | 2800 | return r; |
95ba8273 | 2801 | } |
0a5fff19 | 2802 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
7ff76d58 | 2803 | return r; |
1d075434 JR |
2804 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2805 | return 0; | |
2806 | } | |
2807 | ||
6aa8b732 AK |
2808 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
2809 | { | |
a2fa3e9f GH |
2810 | struct vcpu_svm *svm = to_svm(vcpu); |
2811 | ||
6aa8b732 | 2812 | switch (ecx) { |
af24a4e4 | 2813 | case MSR_IA32_TSC: { |
4cc70310 | 2814 | struct vmcb *vmcb = get_host_vmcb(svm); |
6aa8b732 | 2815 | |
4cc70310 | 2816 | *data = vmcb->control.tsc_offset + native_read_tsc(); |
6aa8b732 AK |
2817 | break; |
2818 | } | |
8c06585d | 2819 | case MSR_STAR: |
a2fa3e9f | 2820 | *data = svm->vmcb->save.star; |
6aa8b732 | 2821 | break; |
0e859cac | 2822 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2823 | case MSR_LSTAR: |
a2fa3e9f | 2824 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
2825 | break; |
2826 | case MSR_CSTAR: | |
a2fa3e9f | 2827 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
2828 | break; |
2829 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2830 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
2831 | break; |
2832 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2833 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
2834 | break; |
2835 | #endif | |
2836 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2837 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
2838 | break; |
2839 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2840 | *data = svm->sysenter_eip; |
6aa8b732 AK |
2841 | break; |
2842 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2843 | *data = svm->sysenter_esp; |
6aa8b732 | 2844 | break; |
e0231715 JR |
2845 | /* |
2846 | * Nobody will change the following 5 values in the VMCB so we can | |
2847 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
2848 | * implemented. | |
2849 | */ | |
a2938c80 JR |
2850 | case MSR_IA32_DEBUGCTLMSR: |
2851 | *data = svm->vmcb->save.dbgctl; | |
2852 | break; | |
2853 | case MSR_IA32_LASTBRANCHFROMIP: | |
2854 | *data = svm->vmcb->save.br_from; | |
2855 | break; | |
2856 | case MSR_IA32_LASTBRANCHTOIP: | |
2857 | *data = svm->vmcb->save.br_to; | |
2858 | break; | |
2859 | case MSR_IA32_LASTINTFROMIP: | |
2860 | *data = svm->vmcb->save.last_excp_from; | |
2861 | break; | |
2862 | case MSR_IA32_LASTINTTOIP: | |
2863 | *data = svm->vmcb->save.last_excp_to; | |
2864 | break; | |
b286d5d8 | 2865 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2866 | *data = svm->nested.hsave_msr; |
b286d5d8 | 2867 | break; |
eb6f302e | 2868 | case MSR_VM_CR: |
4a810181 | 2869 | *data = svm->nested.vm_cr_msr; |
eb6f302e | 2870 | break; |
c8a73f18 AG |
2871 | case MSR_IA32_UCODE_REV: |
2872 | *data = 0x01000065; | |
2873 | break; | |
6aa8b732 | 2874 | default: |
3bab1f5d | 2875 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2876 | } |
2877 | return 0; | |
2878 | } | |
2879 | ||
851ba692 | 2880 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2881 | { |
ad312c7c | 2882 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
2883 | u64 data; |
2884 | ||
59200273 AK |
2885 | if (svm_get_msr(&svm->vcpu, ecx, &data)) { |
2886 | trace_kvm_msr_read_ex(ecx); | |
c1a5d4f9 | 2887 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 | 2888 | } else { |
229456fc | 2889 | trace_kvm_msr_read(ecx, data); |
af9ca2d7 | 2890 | |
5fdbf976 | 2891 | svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff; |
ad312c7c | 2892 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
5fdbf976 | 2893 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2894 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
2895 | } |
2896 | return 1; | |
2897 | } | |
2898 | ||
4a810181 JR |
2899 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
2900 | { | |
2901 | struct vcpu_svm *svm = to_svm(vcpu); | |
2902 | int svm_dis, chg_mask; | |
2903 | ||
2904 | if (data & ~SVM_VM_CR_VALID_MASK) | |
2905 | return 1; | |
2906 | ||
2907 | chg_mask = SVM_VM_CR_VALID_MASK; | |
2908 | ||
2909 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
2910 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
2911 | ||
2912 | svm->nested.vm_cr_msr &= ~chg_mask; | |
2913 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
2914 | ||
2915 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
2916 | ||
2917 | /* check for svm_disable while efer.svme is set */ | |
2918 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
2919 | return 1; | |
2920 | ||
2921 | return 0; | |
2922 | } | |
2923 | ||
6aa8b732 AK |
2924 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) |
2925 | { | |
a2fa3e9f GH |
2926 | struct vcpu_svm *svm = to_svm(vcpu); |
2927 | ||
6aa8b732 | 2928 | switch (ecx) { |
f4e1b3c8 | 2929 | case MSR_IA32_TSC: |
99e3e30a | 2930 | kvm_write_tsc(vcpu, data); |
6aa8b732 | 2931 | break; |
8c06585d | 2932 | case MSR_STAR: |
a2fa3e9f | 2933 | svm->vmcb->save.star = data; |
6aa8b732 | 2934 | break; |
49b14f24 | 2935 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2936 | case MSR_LSTAR: |
a2fa3e9f | 2937 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
2938 | break; |
2939 | case MSR_CSTAR: | |
a2fa3e9f | 2940 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
2941 | break; |
2942 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2943 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
2944 | break; |
2945 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2946 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
2947 | break; |
2948 | #endif | |
2949 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2950 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
2951 | break; |
2952 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2953 | svm->sysenter_eip = data; |
a2fa3e9f | 2954 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
2955 | break; |
2956 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2957 | svm->sysenter_esp = data; |
a2fa3e9f | 2958 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 2959 | break; |
a2938c80 | 2960 | case MSR_IA32_DEBUGCTLMSR: |
2a6b20b8 | 2961 | if (!boot_cpu_has(X86_FEATURE_LBRV)) { |
24e09cbf | 2962 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", |
b8688d51 | 2963 | __func__, data); |
24e09cbf JR |
2964 | break; |
2965 | } | |
2966 | if (data & DEBUGCTL_RESERVED_BITS) | |
2967 | return 1; | |
2968 | ||
2969 | svm->vmcb->save.dbgctl = data; | |
b53ba3f9 | 2970 | mark_dirty(svm->vmcb, VMCB_LBR); |
24e09cbf JR |
2971 | if (data & (1ULL<<0)) |
2972 | svm_enable_lbrv(svm); | |
2973 | else | |
2974 | svm_disable_lbrv(svm); | |
a2938c80 | 2975 | break; |
b286d5d8 | 2976 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2977 | svm->nested.hsave_msr = data; |
62b9abaa | 2978 | break; |
3c5d0a44 | 2979 | case MSR_VM_CR: |
4a810181 | 2980 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 2981 | case MSR_VM_IGNNE: |
3c5d0a44 AG |
2982 | pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
2983 | break; | |
6aa8b732 | 2984 | default: |
3bab1f5d | 2985 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2986 | } |
2987 | return 0; | |
2988 | } | |
2989 | ||
851ba692 | 2990 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2991 | { |
ad312c7c | 2992 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
5fdbf976 | 2993 | u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u) |
ad312c7c | 2994 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
af9ca2d7 | 2995 | |
af9ca2d7 | 2996 | |
5fdbf976 | 2997 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
59200273 AK |
2998 | if (svm_set_msr(&svm->vcpu, ecx, data)) { |
2999 | trace_kvm_msr_write_ex(ecx, data); | |
c1a5d4f9 | 3000 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 AK |
3001 | } else { |
3002 | trace_kvm_msr_write(ecx, data); | |
e756fc62 | 3003 | skip_emulated_instruction(&svm->vcpu); |
59200273 | 3004 | } |
6aa8b732 AK |
3005 | return 1; |
3006 | } | |
3007 | ||
851ba692 | 3008 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3009 | { |
e756fc62 | 3010 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 3011 | return wrmsr_interception(svm); |
6aa8b732 | 3012 | else |
851ba692 | 3013 | return rdmsr_interception(svm); |
6aa8b732 AK |
3014 | } |
3015 | ||
851ba692 | 3016 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 3017 | { |
851ba692 AK |
3018 | struct kvm_run *kvm_run = svm->vcpu.run; |
3019 | ||
3842d135 | 3020 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
f0b85051 | 3021 | svm_clear_vintr(svm); |
85f455f7 | 3022 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
decdbf6a | 3023 | mark_dirty(svm->vmcb, VMCB_INTR); |
c1150d8c DL |
3024 | /* |
3025 | * If the user space waits to inject interrupts, exit as soon as | |
3026 | * possible | |
3027 | */ | |
8061823a GN |
3028 | if (!irqchip_in_kernel(svm->vcpu.kvm) && |
3029 | kvm_run->request_interrupt_window && | |
3030 | !kvm_cpu_has_interrupt(&svm->vcpu)) { | |
e756fc62 | 3031 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
3032 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
3033 | return 0; | |
3034 | } | |
3035 | ||
3036 | return 1; | |
3037 | } | |
3038 | ||
565d0998 ML |
3039 | static int pause_interception(struct vcpu_svm *svm) |
3040 | { | |
3041 | kvm_vcpu_on_spin(&(svm->vcpu)); | |
3042 | return 1; | |
3043 | } | |
3044 | ||
851ba692 | 3045 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = { |
7ff76d58 AP |
3046 | [SVM_EXIT_READ_CR0] = cr_interception, |
3047 | [SVM_EXIT_READ_CR3] = cr_interception, | |
3048 | [SVM_EXIT_READ_CR4] = cr_interception, | |
3049 | [SVM_EXIT_READ_CR8] = cr_interception, | |
d225157b | 3050 | [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, |
cda00082 | 3051 | [SVM_EXIT_WRITE_CR0] = cr0_write_interception, |
7ff76d58 AP |
3052 | [SVM_EXIT_WRITE_CR3] = cr_interception, |
3053 | [SVM_EXIT_WRITE_CR4] = cr_interception, | |
e0231715 | 3054 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
cae3797a AP |
3055 | [SVM_EXIT_READ_DR0] = dr_interception, |
3056 | [SVM_EXIT_READ_DR1] = dr_interception, | |
3057 | [SVM_EXIT_READ_DR2] = dr_interception, | |
3058 | [SVM_EXIT_READ_DR3] = dr_interception, | |
3059 | [SVM_EXIT_READ_DR4] = dr_interception, | |
3060 | [SVM_EXIT_READ_DR5] = dr_interception, | |
3061 | [SVM_EXIT_READ_DR6] = dr_interception, | |
3062 | [SVM_EXIT_READ_DR7] = dr_interception, | |
3063 | [SVM_EXIT_WRITE_DR0] = dr_interception, | |
3064 | [SVM_EXIT_WRITE_DR1] = dr_interception, | |
3065 | [SVM_EXIT_WRITE_DR2] = dr_interception, | |
3066 | [SVM_EXIT_WRITE_DR3] = dr_interception, | |
3067 | [SVM_EXIT_WRITE_DR4] = dr_interception, | |
3068 | [SVM_EXIT_WRITE_DR5] = dr_interception, | |
3069 | [SVM_EXIT_WRITE_DR6] = dr_interception, | |
3070 | [SVM_EXIT_WRITE_DR7] = dr_interception, | |
d0bfb940 JK |
3071 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
3072 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 3073 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 JR |
3074 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
3075 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, | |
3076 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, | |
3077 | [SVM_EXIT_INTR] = intr_interception, | |
c47f098d | 3078 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
3079 | [SVM_EXIT_SMI] = nop_on_interception, |
3080 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 3081 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 | 3082 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 3083 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 3084 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 3085 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 3086 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 3087 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 3088 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 3089 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
3090 | [SVM_EXIT_MSR] = msr_interception, |
3091 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 3092 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 3093 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 3094 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
3095 | [SVM_EXIT_VMLOAD] = vmload_interception, |
3096 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
3097 | [SVM_EXIT_STGI] = stgi_interception, |
3098 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 3099 | [SVM_EXIT_SKINIT] = skinit_interception, |
cf5a94d1 | 3100 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
3101 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
3102 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
81dd35d4 | 3103 | [SVM_EXIT_XSETBV] = xsetbv_interception, |
709ddebf | 3104 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
3105 | }; |
3106 | ||
3f10c846 JR |
3107 | void dump_vmcb(struct kvm_vcpu *vcpu) |
3108 | { | |
3109 | struct vcpu_svm *svm = to_svm(vcpu); | |
3110 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3111 | struct vmcb_save_area *save = &svm->vmcb->save; | |
3112 | ||
3113 | pr_err("VMCB Control Area:\n"); | |
4ee546b4 RJ |
3114 | pr_err("cr_read: %04x\n", control->intercept_cr & 0xffff); |
3115 | pr_err("cr_write: %04x\n", control->intercept_cr >> 16); | |
3aed041a JR |
3116 | pr_err("dr_read: %04x\n", control->intercept_dr & 0xffff); |
3117 | pr_err("dr_write: %04x\n", control->intercept_dr >> 16); | |
3f10c846 JR |
3118 | pr_err("exceptions: %08x\n", control->intercept_exceptions); |
3119 | pr_err("intercepts: %016llx\n", control->intercept); | |
3120 | pr_err("pause filter count: %d\n", control->pause_filter_count); | |
3121 | pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa); | |
3122 | pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa); | |
3123 | pr_err("tsc_offset: %016llx\n", control->tsc_offset); | |
3124 | pr_err("asid: %d\n", control->asid); | |
3125 | pr_err("tlb_ctl: %d\n", control->tlb_ctl); | |
3126 | pr_err("int_ctl: %08x\n", control->int_ctl); | |
3127 | pr_err("int_vector: %08x\n", control->int_vector); | |
3128 | pr_err("int_state: %08x\n", control->int_state); | |
3129 | pr_err("exit_code: %08x\n", control->exit_code); | |
3130 | pr_err("exit_info1: %016llx\n", control->exit_info_1); | |
3131 | pr_err("exit_info2: %016llx\n", control->exit_info_2); | |
3132 | pr_err("exit_int_info: %08x\n", control->exit_int_info); | |
3133 | pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err); | |
3134 | pr_err("nested_ctl: %lld\n", control->nested_ctl); | |
3135 | pr_err("nested_cr3: %016llx\n", control->nested_cr3); | |
3136 | pr_err("event_inj: %08x\n", control->event_inj); | |
3137 | pr_err("event_inj_err: %08x\n", control->event_inj_err); | |
3138 | pr_err("lbr_ctl: %lld\n", control->lbr_ctl); | |
3139 | pr_err("next_rip: %016llx\n", control->next_rip); | |
3140 | pr_err("VMCB State Save Area:\n"); | |
3141 | pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n", | |
3142 | save->es.selector, save->es.attrib, | |
3143 | save->es.limit, save->es.base); | |
3144 | pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n", | |
3145 | save->cs.selector, save->cs.attrib, | |
3146 | save->cs.limit, save->cs.base); | |
3147 | pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n", | |
3148 | save->ss.selector, save->ss.attrib, | |
3149 | save->ss.limit, save->ss.base); | |
3150 | pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n", | |
3151 | save->ds.selector, save->ds.attrib, | |
3152 | save->ds.limit, save->ds.base); | |
3153 | pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n", | |
3154 | save->fs.selector, save->fs.attrib, | |
3155 | save->fs.limit, save->fs.base); | |
3156 | pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n", | |
3157 | save->gs.selector, save->gs.attrib, | |
3158 | save->gs.limit, save->gs.base); | |
3159 | pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
3160 | save->gdtr.selector, save->gdtr.attrib, | |
3161 | save->gdtr.limit, save->gdtr.base); | |
3162 | pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
3163 | save->ldtr.selector, save->ldtr.attrib, | |
3164 | save->ldtr.limit, save->ldtr.base); | |
3165 | pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
3166 | save->idtr.selector, save->idtr.attrib, | |
3167 | save->idtr.limit, save->idtr.base); | |
3168 | pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n", | |
3169 | save->tr.selector, save->tr.attrib, | |
3170 | save->tr.limit, save->tr.base); | |
3171 | pr_err("cpl: %d efer: %016llx\n", | |
3172 | save->cpl, save->efer); | |
3173 | pr_err("cr0: %016llx cr2: %016llx\n", | |
3174 | save->cr0, save->cr2); | |
3175 | pr_err("cr3: %016llx cr4: %016llx\n", | |
3176 | save->cr3, save->cr4); | |
3177 | pr_err("dr6: %016llx dr7: %016llx\n", | |
3178 | save->dr6, save->dr7); | |
3179 | pr_err("rip: %016llx rflags: %016llx\n", | |
3180 | save->rip, save->rflags); | |
3181 | pr_err("rsp: %016llx rax: %016llx\n", | |
3182 | save->rsp, save->rax); | |
3183 | pr_err("star: %016llx lstar: %016llx\n", | |
3184 | save->star, save->lstar); | |
3185 | pr_err("cstar: %016llx sfmask: %016llx\n", | |
3186 | save->cstar, save->sfmask); | |
3187 | pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n", | |
3188 | save->kernel_gs_base, save->sysenter_cs); | |
3189 | pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n", | |
3190 | save->sysenter_esp, save->sysenter_eip); | |
3191 | pr_err("gpat: %016llx dbgctl: %016llx\n", | |
3192 | save->g_pat, save->dbgctl); | |
3193 | pr_err("br_from: %016llx br_to: %016llx\n", | |
3194 | save->br_from, save->br_to); | |
3195 | pr_err("excp_from: %016llx excp_to: %016llx\n", | |
3196 | save->last_excp_from, save->last_excp_to); | |
3197 | ||
3198 | } | |
3199 | ||
586f9607 AK |
3200 | static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
3201 | { | |
3202 | struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; | |
3203 | ||
3204 | *info1 = control->exit_info_1; | |
3205 | *info2 = control->exit_info_2; | |
3206 | } | |
3207 | ||
851ba692 | 3208 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 3209 | { |
04d2cc77 | 3210 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 3211 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 3212 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 3213 | |
aa17911e | 3214 | trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM); |
af9ca2d7 | 3215 | |
4ee546b4 | 3216 | if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE)) |
2be4fc7a JR |
3217 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
3218 | if (npt_enabled) | |
3219 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 3220 | |
cd3ff653 JR |
3221 | if (unlikely(svm->nested.exit_required)) { |
3222 | nested_svm_vmexit(svm); | |
3223 | svm->nested.exit_required = false; | |
3224 | ||
3225 | return 1; | |
3226 | } | |
3227 | ||
2030753d | 3228 | if (is_guest_mode(vcpu)) { |
410e4d57 JR |
3229 | int vmexit; |
3230 | ||
d8cabddf JR |
3231 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
3232 | svm->vmcb->control.exit_info_1, | |
3233 | svm->vmcb->control.exit_info_2, | |
3234 | svm->vmcb->control.exit_int_info, | |
3235 | svm->vmcb->control.exit_int_info_err); | |
3236 | ||
410e4d57 JR |
3237 | vmexit = nested_svm_exit_special(svm); |
3238 | ||
3239 | if (vmexit == NESTED_EXIT_CONTINUE) | |
3240 | vmexit = nested_svm_exit_handled(svm); | |
3241 | ||
3242 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 3243 | return 1; |
cf74a78b AG |
3244 | } |
3245 | ||
a5c3832d JR |
3246 | svm_complete_interrupts(svm); |
3247 | ||
04d2cc77 AK |
3248 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
3249 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
3250 | kvm_run->fail_entry.hardware_entry_failure_reason | |
3251 | = svm->vmcb->control.exit_code; | |
3f10c846 JR |
3252 | pr_err("KVM: FAILED VMRUN WITH VMCB:\n"); |
3253 | dump_vmcb(vcpu); | |
04d2cc77 AK |
3254 | return 0; |
3255 | } | |
3256 | ||
a2fa3e9f | 3257 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 3258 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
55c5e464 JR |
3259 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH && |
3260 | exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI) | |
6aa8b732 AK |
3261 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " |
3262 | "exit_code 0x%x\n", | |
b8688d51 | 3263 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
3264 | exit_code); |
3265 | ||
9d8f549d | 3266 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 3267 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 3268 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 3269 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
3270 | return 0; |
3271 | } | |
3272 | ||
851ba692 | 3273 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
3274 | } |
3275 | ||
3276 | static void reload_tss(struct kvm_vcpu *vcpu) | |
3277 | { | |
3278 | int cpu = raw_smp_processor_id(); | |
3279 | ||
0fe1e009 TH |
3280 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
3281 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
3282 | load_TR_desc(); |
3283 | } | |
3284 | ||
e756fc62 | 3285 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
3286 | { |
3287 | int cpu = raw_smp_processor_id(); | |
3288 | ||
0fe1e009 | 3289 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 3290 | |
4b656b12 | 3291 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
3292 | if (svm->asid_generation != sd->asid_generation) |
3293 | new_asid(svm, sd); | |
6aa8b732 AK |
3294 | } |
3295 | ||
95ba8273 GN |
3296 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
3297 | { | |
3298 | struct vcpu_svm *svm = to_svm(vcpu); | |
3299 | ||
3300 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
3301 | vcpu->arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3302 | set_intercept(svm, INTERCEPT_IRET); |
95ba8273 GN |
3303 | ++vcpu->stat.nmi_injections; |
3304 | } | |
6aa8b732 | 3305 | |
85f455f7 | 3306 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
3307 | { |
3308 | struct vmcb_control_area *control; | |
3309 | ||
e756fc62 | 3310 | control = &svm->vmcb->control; |
85f455f7 | 3311 | control->int_vector = irq; |
6aa8b732 AK |
3312 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
3313 | control->int_ctl |= V_IRQ_MASK | | |
3314 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
decdbf6a | 3315 | mark_dirty(svm->vmcb, VMCB_INTR); |
6aa8b732 AK |
3316 | } |
3317 | ||
66fd3f7f | 3318 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
3319 | { |
3320 | struct vcpu_svm *svm = to_svm(vcpu); | |
3321 | ||
2af9194d | 3322 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 3323 | |
9fb2d2b4 GN |
3324 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
3325 | ++vcpu->stat.irq_injections; | |
3326 | ||
219b65dc AG |
3327 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
3328 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
3329 | } |
3330 | ||
95ba8273 | 3331 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
3332 | { |
3333 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 3334 | |
2030753d | 3335 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3336 | return; |
3337 | ||
95ba8273 | 3338 | if (irr == -1) |
aaacfc9a JR |
3339 | return; |
3340 | ||
95ba8273 | 3341 | if (tpr >= irr) |
4ee546b4 | 3342 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
95ba8273 | 3343 | } |
aaacfc9a | 3344 | |
95ba8273 GN |
3345 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
3346 | { | |
3347 | struct vcpu_svm *svm = to_svm(vcpu); | |
3348 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
3349 | int ret; |
3350 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
3351 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3352 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
3353 | ||
3354 | return ret; | |
aaacfc9a JR |
3355 | } |
3356 | ||
3cfc3092 JK |
3357 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
3358 | { | |
3359 | struct vcpu_svm *svm = to_svm(vcpu); | |
3360 | ||
3361 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3362 | } | |
3363 | ||
3364 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
3365 | { | |
3366 | struct vcpu_svm *svm = to_svm(vcpu); | |
3367 | ||
3368 | if (masked) { | |
3369 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3370 | set_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3371 | } else { |
3372 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
8a05a1b8 | 3373 | clr_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3374 | } |
3375 | } | |
3376 | ||
78646121 GN |
3377 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
3378 | { | |
3379 | struct vcpu_svm *svm = to_svm(vcpu); | |
3380 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
3381 | int ret; |
3382 | ||
3383 | if (!gif_set(svm) || | |
3384 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
3385 | return 0; | |
3386 | ||
3387 | ret = !!(vmcb->save.rflags & X86_EFLAGS_IF); | |
3388 | ||
2030753d | 3389 | if (is_guest_mode(vcpu)) |
7fcdb510 JR |
3390 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); |
3391 | ||
3392 | return ret; | |
78646121 GN |
3393 | } |
3394 | ||
9222be18 | 3395 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 3396 | { |
219b65dc | 3397 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 3398 | |
e0231715 JR |
3399 | /* |
3400 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
3401 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
3402 | * get that intercept, this function will be called again though and | |
3403 | * we'll get the vintr intercept. | |
3404 | */ | |
8fe54654 | 3405 | if (gif_set(svm) && nested_svm_intr(svm)) { |
219b65dc AG |
3406 | svm_set_vintr(svm); |
3407 | svm_inject_irq(svm, 0x0); | |
3408 | } | |
85f455f7 ED |
3409 | } |
3410 | ||
95ba8273 | 3411 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 3412 | { |
04d2cc77 | 3413 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 3414 | |
44c11430 GN |
3415 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
3416 | == HF_NMI_MASK) | |
3417 | return; /* IRET will cause a vm exit */ | |
3418 | ||
e0231715 JR |
3419 | /* |
3420 | * Something prevents NMI from been injected. Single step over possible | |
3421 | * problem (IRET or exception injection or interrupt shadow) | |
3422 | */ | |
6be7d306 | 3423 | svm->nmi_singlestep = true; |
44c11430 GN |
3424 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
3425 | update_db_intercept(vcpu); | |
c1150d8c DL |
3426 | } |
3427 | ||
cbc94022 IE |
3428 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
3429 | { | |
3430 | return 0; | |
3431 | } | |
3432 | ||
d9e368d6 AK |
3433 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
3434 | { | |
38e5e92f JR |
3435 | struct vcpu_svm *svm = to_svm(vcpu); |
3436 | ||
3437 | if (static_cpu_has(X86_FEATURE_FLUSHBYASID)) | |
3438 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; | |
3439 | else | |
3440 | svm->asid_generation--; | |
d9e368d6 AK |
3441 | } |
3442 | ||
04d2cc77 AK |
3443 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
3444 | { | |
3445 | } | |
3446 | ||
d7bf8221 JR |
3447 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
3448 | { | |
3449 | struct vcpu_svm *svm = to_svm(vcpu); | |
3450 | ||
2030753d | 3451 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3452 | return; |
3453 | ||
4ee546b4 | 3454 | if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) { |
d7bf8221 | 3455 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; |
615d5193 | 3456 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
3457 | } |
3458 | } | |
3459 | ||
649d6864 JR |
3460 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
3461 | { | |
3462 | struct vcpu_svm *svm = to_svm(vcpu); | |
3463 | u64 cr8; | |
3464 | ||
2030753d | 3465 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3466 | return; |
3467 | ||
649d6864 JR |
3468 | cr8 = kvm_get_cr8(vcpu); |
3469 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
3470 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
3471 | } | |
3472 | ||
9222be18 GN |
3473 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
3474 | { | |
3475 | u8 vector; | |
3476 | int type; | |
3477 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
3478 | unsigned int3_injected = svm->int3_injected; |
3479 | ||
3480 | svm->int3_injected = 0; | |
9222be18 | 3481 | |
bd3d1ec3 AK |
3482 | /* |
3483 | * If we've made progress since setting HF_IRET_MASK, we've | |
3484 | * executed an IRET and can allow NMI injection. | |
3485 | */ | |
3486 | if ((svm->vcpu.arch.hflags & HF_IRET_MASK) | |
3487 | && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) { | |
44c11430 | 3488 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); |
3842d135 AK |
3489 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3490 | } | |
44c11430 | 3491 | |
9222be18 GN |
3492 | svm->vcpu.arch.nmi_injected = false; |
3493 | kvm_clear_exception_queue(&svm->vcpu); | |
3494 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3495 | ||
3496 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
3497 | return; | |
3498 | ||
3842d135 AK |
3499 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3500 | ||
9222be18 GN |
3501 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; |
3502 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
3503 | ||
3504 | switch (type) { | |
3505 | case SVM_EXITINTINFO_TYPE_NMI: | |
3506 | svm->vcpu.arch.nmi_injected = true; | |
3507 | break; | |
3508 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
3509 | /* |
3510 | * In case of software exceptions, do not reinject the vector, | |
3511 | * but re-execute the instruction instead. Rewind RIP first | |
3512 | * if we emulated INT3 before. | |
3513 | */ | |
3514 | if (kvm_exception_is_soft(vector)) { | |
3515 | if (vector == BP_VECTOR && int3_injected && | |
3516 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
3517 | kvm_rip_write(&svm->vcpu, | |
3518 | kvm_rip_read(&svm->vcpu) - | |
3519 | int3_injected); | |
9222be18 | 3520 | break; |
66b7138f | 3521 | } |
9222be18 GN |
3522 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
3523 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 3524 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
3525 | |
3526 | } else | |
ce7ddec4 | 3527 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
3528 | break; |
3529 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 3530 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
3531 | break; |
3532 | default: | |
3533 | break; | |
3534 | } | |
3535 | } | |
3536 | ||
b463a6f7 AK |
3537 | static void svm_cancel_injection(struct kvm_vcpu *vcpu) |
3538 | { | |
3539 | struct vcpu_svm *svm = to_svm(vcpu); | |
3540 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3541 | ||
3542 | control->exit_int_info = control->event_inj; | |
3543 | control->exit_int_info_err = control->event_inj_err; | |
3544 | control->event_inj = 0; | |
3545 | svm_complete_interrupts(svm); | |
3546 | } | |
3547 | ||
80e31d4f AK |
3548 | #ifdef CONFIG_X86_64 |
3549 | #define R "r" | |
3550 | #else | |
3551 | #define R "e" | |
3552 | #endif | |
3553 | ||
851ba692 | 3554 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 3555 | { |
a2fa3e9f | 3556 | struct vcpu_svm *svm = to_svm(vcpu); |
d9e368d6 | 3557 | |
2041a06a JR |
3558 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
3559 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
3560 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
3561 | ||
cd3ff653 JR |
3562 | /* |
3563 | * A vmexit emulation is required before the vcpu can be executed | |
3564 | * again. | |
3565 | */ | |
3566 | if (unlikely(svm->nested.exit_required)) | |
3567 | return; | |
3568 | ||
e756fc62 | 3569 | pre_svm_run(svm); |
6aa8b732 | 3570 | |
649d6864 JR |
3571 | sync_lapic_to_cr8(vcpu); |
3572 | ||
cda0ffdd | 3573 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 3574 | |
04d2cc77 AK |
3575 | clgi(); |
3576 | ||
3577 | local_irq_enable(); | |
36241b8c | 3578 | |
6aa8b732 | 3579 | asm volatile ( |
80e31d4f AK |
3580 | "push %%"R"bp; \n\t" |
3581 | "mov %c[rbx](%[svm]), %%"R"bx \n\t" | |
3582 | "mov %c[rcx](%[svm]), %%"R"cx \n\t" | |
3583 | "mov %c[rdx](%[svm]), %%"R"dx \n\t" | |
3584 | "mov %c[rsi](%[svm]), %%"R"si \n\t" | |
3585 | "mov %c[rdi](%[svm]), %%"R"di \n\t" | |
3586 | "mov %c[rbp](%[svm]), %%"R"bp \n\t" | |
05b3e0c2 | 3587 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3588 | "mov %c[r8](%[svm]), %%r8 \n\t" |
3589 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
3590 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
3591 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
3592 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
3593 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
3594 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
3595 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
3596 | #endif |
3597 | ||
6aa8b732 | 3598 | /* Enter guest mode */ |
80e31d4f AK |
3599 | "push %%"R"ax \n\t" |
3600 | "mov %c[vmcb](%[svm]), %%"R"ax \n\t" | |
4ecac3fd AK |
3601 | __ex(SVM_VMLOAD) "\n\t" |
3602 | __ex(SVM_VMRUN) "\n\t" | |
3603 | __ex(SVM_VMSAVE) "\n\t" | |
80e31d4f | 3604 | "pop %%"R"ax \n\t" |
6aa8b732 AK |
3605 | |
3606 | /* Save guest registers, load host registers */ | |
80e31d4f AK |
3607 | "mov %%"R"bx, %c[rbx](%[svm]) \n\t" |
3608 | "mov %%"R"cx, %c[rcx](%[svm]) \n\t" | |
3609 | "mov %%"R"dx, %c[rdx](%[svm]) \n\t" | |
3610 | "mov %%"R"si, %c[rsi](%[svm]) \n\t" | |
3611 | "mov %%"R"di, %c[rdi](%[svm]) \n\t" | |
3612 | "mov %%"R"bp, %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 3613 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3614 | "mov %%r8, %c[r8](%[svm]) \n\t" |
3615 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
3616 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
3617 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
3618 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
3619 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
3620 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
3621 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 3622 | #endif |
80e31d4f | 3623 | "pop %%"R"bp" |
6aa8b732 | 3624 | : |
fb3f0f51 | 3625 | : [svm]"a"(svm), |
6aa8b732 | 3626 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
3627 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
3628 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
3629 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
3630 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
3631 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
3632 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 3633 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
3634 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
3635 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
3636 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
3637 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
3638 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
3639 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
3640 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
3641 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 3642 | #endif |
54a08c04 | 3643 | : "cc", "memory" |
80e31d4f | 3644 | , R"bx", R"cx", R"dx", R"si", R"di" |
54a08c04 | 3645 | #ifdef CONFIG_X86_64 |
54a08c04 LV |
3646 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
3647 | #endif | |
3648 | ); | |
6aa8b732 | 3649 | |
82ca2d10 AK |
3650 | #ifdef CONFIG_X86_64 |
3651 | wrmsrl(MSR_GS_BASE, svm->host.gs_base); | |
3652 | #else | |
dacccfdd | 3653 | loadsegment(fs, svm->host.fs); |
831ca609 AK |
3654 | #ifndef CONFIG_X86_32_LAZY_GS |
3655 | loadsegment(gs, svm->host.gs); | |
3656 | #endif | |
9581d442 | 3657 | #endif |
6aa8b732 AK |
3658 | |
3659 | reload_tss(vcpu); | |
3660 | ||
56ba47dd AK |
3661 | local_irq_disable(); |
3662 | ||
13c34e07 AK |
3663 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
3664 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
3665 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
3666 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
3667 | ||
3781c01c JR |
3668 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) |
3669 | kvm_before_handle_nmi(&svm->vcpu); | |
3670 | ||
3671 | stgi(); | |
3672 | ||
3673 | /* Any pending NMI will happen here */ | |
3674 | ||
3675 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) | |
3676 | kvm_after_handle_nmi(&svm->vcpu); | |
3677 | ||
d7bf8221 JR |
3678 | sync_cr8_to_lapic(vcpu); |
3679 | ||
a2fa3e9f | 3680 | svm->next_rip = 0; |
9222be18 | 3681 | |
38e5e92f JR |
3682 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
3683 | ||
631bc487 GN |
3684 | /* if exit due to PF check for async PF */ |
3685 | if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
3686 | svm->apf_reason = kvm_read_and_reset_pf_reason(); | |
3687 | ||
6de4f3ad AK |
3688 | if (npt_enabled) { |
3689 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
3690 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
3691 | } | |
fe5913e4 JR |
3692 | |
3693 | /* | |
3694 | * We need to handle MC intercepts here before the vcpu has a chance to | |
3695 | * change the physical cpu | |
3696 | */ | |
3697 | if (unlikely(svm->vmcb->control.exit_code == | |
3698 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
3699 | svm_handle_mce(svm); | |
8d28fec4 RJ |
3700 | |
3701 | mark_all_clean(svm->vmcb); | |
6aa8b732 AK |
3702 | } |
3703 | ||
80e31d4f AK |
3704 | #undef R |
3705 | ||
6aa8b732 AK |
3706 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3707 | { | |
a2fa3e9f GH |
3708 | struct vcpu_svm *svm = to_svm(vcpu); |
3709 | ||
3710 | svm->vmcb->save.cr3 = root; | |
dcca1a65 | 3711 | mark_dirty(svm->vmcb, VMCB_CR); |
f40f6a45 | 3712 | svm_flush_tlb(vcpu); |
6aa8b732 AK |
3713 | } |
3714 | ||
1c97f0a0 JR |
3715 | static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3716 | { | |
3717 | struct vcpu_svm *svm = to_svm(vcpu); | |
3718 | ||
3719 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 3720 | mark_dirty(svm->vmcb, VMCB_NPT); |
1c97f0a0 JR |
3721 | |
3722 | /* Also sync guest cr3 here in case we live migrate */ | |
9f8fe504 | 3723 | svm->vmcb->save.cr3 = kvm_read_cr3(vcpu); |
dcca1a65 | 3724 | mark_dirty(svm->vmcb, VMCB_CR); |
1c97f0a0 | 3725 | |
f40f6a45 | 3726 | svm_flush_tlb(vcpu); |
1c97f0a0 JR |
3727 | } |
3728 | ||
6aa8b732 AK |
3729 | static int is_disabled(void) |
3730 | { | |
6031a61c JR |
3731 | u64 vm_cr; |
3732 | ||
3733 | rdmsrl(MSR_VM_CR, vm_cr); | |
3734 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
3735 | return 1; | |
3736 | ||
6aa8b732 AK |
3737 | return 0; |
3738 | } | |
3739 | ||
102d8325 IM |
3740 | static void |
3741 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
3742 | { | |
3743 | /* | |
3744 | * Patch in the VMMCALL instruction: | |
3745 | */ | |
3746 | hypercall[0] = 0x0f; | |
3747 | hypercall[1] = 0x01; | |
3748 | hypercall[2] = 0xd9; | |
102d8325 IM |
3749 | } |
3750 | ||
002c7f7c YS |
3751 | static void svm_check_processor_compat(void *rtn) |
3752 | { | |
3753 | *(int *)rtn = 0; | |
3754 | } | |
3755 | ||
774ead3a AK |
3756 | static bool svm_cpu_has_accelerated_tpr(void) |
3757 | { | |
3758 | return false; | |
3759 | } | |
3760 | ||
4b12f0de | 3761 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 SY |
3762 | { |
3763 | return 0; | |
3764 | } | |
3765 | ||
0e851880 SY |
3766 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
3767 | { | |
3768 | } | |
3769 | ||
d4330ef2 JR |
3770 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
3771 | { | |
c2c63a49 | 3772 | switch (func) { |
4c62a2dc JR |
3773 | case 0x80000001: |
3774 | if (nested) | |
3775 | entry->ecx |= (1 << 2); /* Set SVM bit */ | |
3776 | break; | |
c2c63a49 JR |
3777 | case 0x8000000A: |
3778 | entry->eax = 1; /* SVM revision 1 */ | |
3779 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
3780 | ASID emulation to nested SVM */ | |
3781 | entry->ecx = 0; /* Reserved */ | |
7a190667 JR |
3782 | entry->edx = 0; /* Per default do not support any |
3783 | additional features */ | |
3784 | ||
3785 | /* Support next_rip if host supports it */ | |
2a6b20b8 | 3786 | if (boot_cpu_has(X86_FEATURE_NRIPS)) |
7a190667 | 3787 | entry->edx |= SVM_FEATURE_NRIP; |
c2c63a49 | 3788 | |
3d4aeaad JR |
3789 | /* Support NPT for the guest if enabled */ |
3790 | if (npt_enabled) | |
3791 | entry->edx |= SVM_FEATURE_NPT; | |
3792 | ||
c2c63a49 JR |
3793 | break; |
3794 | } | |
d4330ef2 JR |
3795 | } |
3796 | ||
229456fc | 3797 | static const struct trace_print_flags svm_exit_reasons_str[] = { |
e0231715 JR |
3798 | { SVM_EXIT_READ_CR0, "read_cr0" }, |
3799 | { SVM_EXIT_READ_CR3, "read_cr3" }, | |
3800 | { SVM_EXIT_READ_CR4, "read_cr4" }, | |
3801 | { SVM_EXIT_READ_CR8, "read_cr8" }, | |
3802 | { SVM_EXIT_WRITE_CR0, "write_cr0" }, | |
3803 | { SVM_EXIT_WRITE_CR3, "write_cr3" }, | |
3804 | { SVM_EXIT_WRITE_CR4, "write_cr4" }, | |
3805 | { SVM_EXIT_WRITE_CR8, "write_cr8" }, | |
3806 | { SVM_EXIT_READ_DR0, "read_dr0" }, | |
3807 | { SVM_EXIT_READ_DR1, "read_dr1" }, | |
3808 | { SVM_EXIT_READ_DR2, "read_dr2" }, | |
3809 | { SVM_EXIT_READ_DR3, "read_dr3" }, | |
3810 | { SVM_EXIT_WRITE_DR0, "write_dr0" }, | |
3811 | { SVM_EXIT_WRITE_DR1, "write_dr1" }, | |
3812 | { SVM_EXIT_WRITE_DR2, "write_dr2" }, | |
3813 | { SVM_EXIT_WRITE_DR3, "write_dr3" }, | |
3814 | { SVM_EXIT_WRITE_DR5, "write_dr5" }, | |
3815 | { SVM_EXIT_WRITE_DR7, "write_dr7" }, | |
229456fc MT |
3816 | { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" }, |
3817 | { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" }, | |
3818 | { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" }, | |
3819 | { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" }, | |
3820 | { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" }, | |
3821 | { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" }, | |
3822 | { SVM_EXIT_INTR, "interrupt" }, | |
3823 | { SVM_EXIT_NMI, "nmi" }, | |
3824 | { SVM_EXIT_SMI, "smi" }, | |
3825 | { SVM_EXIT_INIT, "init" }, | |
3826 | { SVM_EXIT_VINTR, "vintr" }, | |
3827 | { SVM_EXIT_CPUID, "cpuid" }, | |
3828 | { SVM_EXIT_INVD, "invd" }, | |
3829 | { SVM_EXIT_HLT, "hlt" }, | |
3830 | { SVM_EXIT_INVLPG, "invlpg" }, | |
3831 | { SVM_EXIT_INVLPGA, "invlpga" }, | |
3832 | { SVM_EXIT_IOIO, "io" }, | |
3833 | { SVM_EXIT_MSR, "msr" }, | |
3834 | { SVM_EXIT_TASK_SWITCH, "task_switch" }, | |
3835 | { SVM_EXIT_SHUTDOWN, "shutdown" }, | |
3836 | { SVM_EXIT_VMRUN, "vmrun" }, | |
3837 | { SVM_EXIT_VMMCALL, "hypercall" }, | |
3838 | { SVM_EXIT_VMLOAD, "vmload" }, | |
3839 | { SVM_EXIT_VMSAVE, "vmsave" }, | |
3840 | { SVM_EXIT_STGI, "stgi" }, | |
3841 | { SVM_EXIT_CLGI, "clgi" }, | |
3842 | { SVM_EXIT_SKINIT, "skinit" }, | |
3843 | { SVM_EXIT_WBINVD, "wbinvd" }, | |
3844 | { SVM_EXIT_MONITOR, "monitor" }, | |
3845 | { SVM_EXIT_MWAIT, "mwait" }, | |
81dd35d4 | 3846 | { SVM_EXIT_XSETBV, "xsetbv" }, |
229456fc MT |
3847 | { SVM_EXIT_NPF, "npf" }, |
3848 | { -1, NULL } | |
3849 | }; | |
3850 | ||
17cc3935 | 3851 | static int svm_get_lpage_level(void) |
344f414f | 3852 | { |
17cc3935 | 3853 | return PT_PDPE_LEVEL; |
344f414f JR |
3854 | } |
3855 | ||
4e47c7a6 SY |
3856 | static bool svm_rdtscp_supported(void) |
3857 | { | |
3858 | return false; | |
3859 | } | |
3860 | ||
f5f48ee1 SY |
3861 | static bool svm_has_wbinvd_exit(void) |
3862 | { | |
3863 | return true; | |
3864 | } | |
3865 | ||
02daab21 AK |
3866 | static void svm_fpu_deactivate(struct kvm_vcpu *vcpu) |
3867 | { | |
3868 | struct vcpu_svm *svm = to_svm(vcpu); | |
3869 | ||
18c918c5 | 3870 | set_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 3871 | update_cr0_intercept(svm); |
02daab21 AK |
3872 | } |
3873 | ||
cbdd1bea | 3874 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
3875 | .cpu_has_kvm_support = has_svm, |
3876 | .disabled_by_bios = is_disabled, | |
3877 | .hardware_setup = svm_hardware_setup, | |
3878 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 3879 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
3880 | .hardware_enable = svm_hardware_enable, |
3881 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 3882 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
3883 | |
3884 | .vcpu_create = svm_create_vcpu, | |
3885 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 3886 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 3887 | |
04d2cc77 | 3888 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
3889 | .vcpu_load = svm_vcpu_load, |
3890 | .vcpu_put = svm_vcpu_put, | |
3891 | ||
3892 | .set_guest_debug = svm_guest_debug, | |
3893 | .get_msr = svm_get_msr, | |
3894 | .set_msr = svm_set_msr, | |
3895 | .get_segment_base = svm_get_segment_base, | |
3896 | .get_segment = svm_get_segment, | |
3897 | .set_segment = svm_set_segment, | |
2e4d2653 | 3898 | .get_cpl = svm_get_cpl, |
1747fb71 | 3899 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 3900 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
aff48baa | 3901 | .decache_cr3 = svm_decache_cr3, |
25c4c276 | 3902 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 3903 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
3904 | .set_cr3 = svm_set_cr3, |
3905 | .set_cr4 = svm_set_cr4, | |
3906 | .set_efer = svm_set_efer, | |
3907 | .get_idt = svm_get_idt, | |
3908 | .set_idt = svm_set_idt, | |
3909 | .get_gdt = svm_get_gdt, | |
3910 | .set_gdt = svm_set_gdt, | |
020df079 | 3911 | .set_dr7 = svm_set_dr7, |
6de4f3ad | 3912 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
3913 | .get_rflags = svm_get_rflags, |
3914 | .set_rflags = svm_set_rflags, | |
6b52d186 | 3915 | .fpu_activate = svm_fpu_activate, |
02daab21 | 3916 | .fpu_deactivate = svm_fpu_deactivate, |
6aa8b732 | 3917 | |
6aa8b732 | 3918 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 3919 | |
6aa8b732 | 3920 | .run = svm_vcpu_run, |
04d2cc77 | 3921 | .handle_exit = handle_exit, |
6aa8b732 | 3922 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
3923 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
3924 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 3925 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 3926 | .set_irq = svm_set_irq, |
95ba8273 | 3927 | .set_nmi = svm_inject_nmi, |
298101da | 3928 | .queue_exception = svm_queue_exception, |
b463a6f7 | 3929 | .cancel_injection = svm_cancel_injection, |
78646121 | 3930 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 3931 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
3932 | .get_nmi_mask = svm_get_nmi_mask, |
3933 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
3934 | .enable_nmi_window = enable_nmi_window, |
3935 | .enable_irq_window = enable_irq_window, | |
3936 | .update_cr8_intercept = update_cr8_intercept, | |
cbc94022 IE |
3937 | |
3938 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 3939 | .get_tdp_level = get_npt_level, |
4b12f0de | 3940 | .get_mt_mask = svm_get_mt_mask, |
229456fc | 3941 | |
586f9607 | 3942 | .get_exit_info = svm_get_exit_info, |
229456fc | 3943 | .exit_reasons_str = svm_exit_reasons_str, |
586f9607 | 3944 | |
17cc3935 | 3945 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
3946 | |
3947 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
3948 | |
3949 | .rdtscp_supported = svm_rdtscp_supported, | |
d4330ef2 JR |
3950 | |
3951 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
3952 | |
3953 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
99e3e30a ZA |
3954 | |
3955 | .write_tsc_offset = svm_write_tsc_offset, | |
e48672fa | 3956 | .adjust_tsc_offset = svm_adjust_tsc_offset, |
1c97f0a0 JR |
3957 | |
3958 | .set_tdp_cr3 = set_tdp_cr3, | |
6aa8b732 AK |
3959 | }; |
3960 | ||
3961 | static int __init svm_init(void) | |
3962 | { | |
cb498ea2 | 3963 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 3964 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
3965 | } |
3966 | ||
3967 | static void __exit svm_exit(void) | |
3968 | { | |
cb498ea2 | 3969 | kvm_exit(); |
6aa8b732 AK |
3970 | } |
3971 | ||
3972 | module_init(svm_init) | |
3973 | module_exit(svm_exit) |