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883b0a91 JR |
1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* | |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * AMD SVM support | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
8 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. | |
9 | * | |
10 | * Authors: | |
11 | * Yaniv Kamay <yaniv@qumranet.com> | |
12 | * Avi Kivity <avi@qumranet.com> | |
13 | */ | |
14 | ||
15 | #ifndef __SVM_SVM_H | |
16 | #define __SVM_SVM_H | |
17 | ||
18 | #include <linux/kvm_types.h> | |
19 | #include <linux/kvm_host.h> | |
291bd20d | 20 | #include <linux/bits.h> |
883b0a91 JR |
21 | |
22 | #include <asm/svm.h> | |
23 | ||
24 | static const u32 host_save_user_msrs[] = { | |
25 | #ifdef CONFIG_X86_64 | |
26 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
27 | MSR_FS_BASE, | |
28 | #endif | |
29 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
30 | MSR_TSC_AUX, | |
31 | }; | |
32 | ||
33 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
34 | ||
fd6fa73d | 35 | #define MAX_DIRECT_ACCESS_MSRS 15 |
883b0a91 JR |
36 | #define MSRPM_OFFSETS 16 |
37 | extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
38 | extern bool npt_enabled; | |
39 | ||
40 | enum { | |
41 | VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, | |
42 | pause filter count */ | |
43 | VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ | |
44 | VMCB_ASID, /* ASID */ | |
45 | VMCB_INTR, /* int_ctl, int_vector */ | |
46 | VMCB_NPT, /* npt_en, nCR3, gPAT */ | |
47 | VMCB_CR, /* CR0, CR3, CR4, EFER */ | |
48 | VMCB_DR, /* DR6, DR7 */ | |
49 | VMCB_DT, /* GDT, IDT */ | |
50 | VMCB_SEG, /* CS, DS, SS, ES, CPL */ | |
51 | VMCB_CR2, /* CR2 only */ | |
52 | VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ | |
53 | VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, | |
54 | * AVIC PHYSICAL_TABLE pointer, | |
55 | * AVIC LOGICAL_TABLE pointer | |
56 | */ | |
57 | VMCB_DIRTY_MAX, | |
58 | }; | |
59 | ||
60 | /* TPR and CR2 are always written before VMRUN */ | |
61 | #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) | |
62 | ||
63 | struct kvm_sev_info { | |
64 | bool active; /* SEV enabled guest */ | |
916391a2 | 65 | bool es_active; /* SEV-ES enabled guest */ |
883b0a91 JR |
66 | unsigned int asid; /* ASID used for this guest */ |
67 | unsigned int handle; /* SEV firmware handle */ | |
68 | int fd; /* SEV device fd */ | |
69 | unsigned long pages_locked; /* Number of pages locked */ | |
70 | struct list_head regions_list; /* List of registered regions */ | |
71 | }; | |
72 | ||
73 | struct kvm_svm { | |
74 | struct kvm kvm; | |
75 | ||
76 | /* Struct members for AVIC */ | |
77 | u32 avic_vm_id; | |
78 | struct page *avic_logical_id_table_page; | |
79 | struct page *avic_physical_id_table_page; | |
80 | struct hlist_node hnode; | |
81 | ||
82 | struct kvm_sev_info sev_info; | |
83 | }; | |
84 | ||
85 | struct kvm_vcpu; | |
86 | ||
7693b3eb | 87 | struct svm_nested_state { |
883b0a91 JR |
88 | struct vmcb *hsave; |
89 | u64 hsave_msr; | |
90 | u64 vm_cr_msr; | |
0dd16b5b | 91 | u64 vmcb12_gpa; |
883b0a91 JR |
92 | |
93 | /* These are the merged vectors */ | |
94 | u32 *msrpm; | |
95 | ||
f74f9414 PB |
96 | /* A VMRUN has started but has not yet been performed, so |
97 | * we cannot inject a nested vmexit yet. */ | |
98 | bool nested_run_pending; | |
99 | ||
e670bf68 PB |
100 | /* cache for control fields of the guest */ |
101 | struct vmcb_control_area ctl; | |
2fcf4876 ML |
102 | |
103 | bool initialized; | |
883b0a91 JR |
104 | }; |
105 | ||
106 | struct vcpu_svm { | |
107 | struct kvm_vcpu vcpu; | |
108 | struct vmcb *vmcb; | |
109 | unsigned long vmcb_pa; | |
110 | struct svm_cpu_data *svm_data; | |
7e8e6eed | 111 | u32 asid; |
883b0a91 JR |
112 | uint64_t asid_generation; |
113 | uint64_t sysenter_esp; | |
114 | uint64_t sysenter_eip; | |
115 | uint64_t tsc_aux; | |
116 | ||
117 | u64 msr_decfg; | |
118 | ||
119 | u64 next_rip; | |
120 | ||
121 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
122 | struct { | |
123 | u16 fs; | |
124 | u16 gs; | |
125 | u16 ldt; | |
126 | u64 gs_base; | |
127 | } host; | |
128 | ||
129 | u64 spec_ctrl; | |
130 | /* | |
131 | * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be | |
132 | * translated into the appropriate L2_CFG bits on the host to | |
133 | * perform speculative control. | |
134 | */ | |
135 | u64 virt_spec_ctrl; | |
136 | ||
137 | u32 *msrpm; | |
138 | ||
139 | ulong nmi_iret_rip; | |
140 | ||
7693b3eb | 141 | struct svm_nested_state nested; |
883b0a91 JR |
142 | |
143 | bool nmi_singlestep; | |
144 | u64 nmi_singlestep_guest_rflags; | |
145 | ||
146 | unsigned int3_injected; | |
147 | unsigned long int3_rip; | |
148 | ||
149 | /* cached guest cpuid flags for faster access */ | |
150 | bool nrips_enabled : 1; | |
151 | ||
152 | u32 ldr_reg; | |
153 | u32 dfr_reg; | |
154 | struct page *avic_backing_page; | |
155 | u64 *avic_physical_id_cache; | |
156 | bool avic_is_running; | |
157 | ||
158 | /* | |
159 | * Per-vcpu list of struct amd_svm_iommu_ir: | |
160 | * This is used mainly to store interrupt remapping information used | |
161 | * when update the vcpu affinity. This avoids the need to scan for | |
162 | * IRTE and try to match ga_tag in the IOMMU driver. | |
163 | */ | |
164 | struct list_head ir_list; | |
165 | spinlock_t ir_list_lock; | |
fd6fa73d AG |
166 | |
167 | /* Save desired MSR intercept (read: pass-through) state */ | |
168 | struct { | |
169 | DECLARE_BITMAP(read, MAX_DIRECT_ACCESS_MSRS); | |
170 | DECLARE_BITMAP(write, MAX_DIRECT_ACCESS_MSRS); | |
171 | } shadow_msr_intercept; | |
add5e2f0 TL |
172 | |
173 | /* SEV-ES support */ | |
174 | struct vmcb_save_area *vmsa; | |
175 | struct ghcb *ghcb; | |
291bd20d | 176 | struct kvm_host_map ghcb_map; |
883b0a91 JR |
177 | }; |
178 | ||
eaf78265 JR |
179 | struct svm_cpu_data { |
180 | int cpu; | |
181 | ||
182 | u64 asid_generation; | |
183 | u32 max_asid; | |
184 | u32 next_asid; | |
185 | u32 min_asid; | |
186 | struct kvm_ldttss_desc *tss_desc; | |
187 | ||
188 | struct page *save_area; | |
189 | struct vmcb *current_vmcb; | |
190 | ||
191 | /* index = sev_asid, value = vmcb pointer */ | |
192 | struct vmcb **sev_vmcbs; | |
193 | }; | |
194 | ||
195 | DECLARE_PER_CPU(struct svm_cpu_data *, svm_data); | |
196 | ||
883b0a91 JR |
197 | void recalc_intercepts(struct vcpu_svm *svm); |
198 | ||
ef0f6496 JR |
199 | static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm) |
200 | { | |
201 | return container_of(kvm, struct kvm_svm, kvm); | |
202 | } | |
203 | ||
916391a2 TL |
204 | static inline bool sev_guest(struct kvm *kvm) |
205 | { | |
206 | #ifdef CONFIG_KVM_AMD_SEV | |
207 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; | |
208 | ||
209 | return sev->active; | |
210 | #else | |
211 | return false; | |
212 | #endif | |
213 | } | |
214 | ||
215 | static inline bool sev_es_guest(struct kvm *kvm) | |
216 | { | |
217 | #ifdef CONFIG_KVM_AMD_SEV | |
218 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; | |
219 | ||
220 | return sev_guest(kvm) && sev->es_active; | |
221 | #else | |
222 | return false; | |
223 | #endif | |
224 | } | |
225 | ||
06e7852c | 226 | static inline void vmcb_mark_all_dirty(struct vmcb *vmcb) |
883b0a91 JR |
227 | { |
228 | vmcb->control.clean = 0; | |
229 | } | |
230 | ||
06e7852c | 231 | static inline void vmcb_mark_all_clean(struct vmcb *vmcb) |
883b0a91 JR |
232 | { |
233 | vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) | |
234 | & ~VMCB_ALWAYS_DIRTY_MASK; | |
235 | } | |
236 | ||
06e7852c | 237 | static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit) |
883b0a91 JR |
238 | { |
239 | vmcb->control.clean &= ~(1 << bit); | |
240 | } | |
241 | ||
242 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) | |
243 | { | |
244 | return container_of(vcpu, struct vcpu_svm, vcpu); | |
245 | } | |
246 | ||
247 | static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) | |
248 | { | |
249 | if (is_guest_mode(&svm->vcpu)) | |
250 | return svm->nested.hsave; | |
251 | else | |
252 | return svm->vmcb; | |
253 | } | |
254 | ||
c45ad722 BM |
255 | static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit) |
256 | { | |
257 | WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); | |
258 | __set_bit(bit, (unsigned long *)&control->intercepts); | |
259 | } | |
260 | ||
261 | static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit) | |
262 | { | |
263 | WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); | |
264 | __clear_bit(bit, (unsigned long *)&control->intercepts); | |
265 | } | |
266 | ||
267 | static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit) | |
268 | { | |
269 | WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); | |
270 | return test_bit(bit, (unsigned long *)&control->intercepts); | |
271 | } | |
272 | ||
883b0a91 JR |
273 | static inline void set_dr_intercepts(struct vcpu_svm *svm) |
274 | { | |
275 | struct vmcb *vmcb = get_host_vmcb(svm); | |
276 | ||
8d4846b9 TL |
277 | if (!sev_es_guest(svm->vcpu.kvm)) { |
278 | vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_READ); | |
279 | vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_READ); | |
280 | vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_READ); | |
281 | vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_READ); | |
282 | vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_READ); | |
283 | vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_READ); | |
284 | vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_READ); | |
285 | vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_WRITE); | |
286 | vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_WRITE); | |
287 | vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_WRITE); | |
288 | vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_WRITE); | |
289 | vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_WRITE); | |
290 | vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_WRITE); | |
291 | vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE); | |
292 | } | |
293 | ||
30abaa88 | 294 | vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ); |
30abaa88 | 295 | vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE); |
883b0a91 JR |
296 | |
297 | recalc_intercepts(svm); | |
298 | } | |
299 | ||
300 | static inline void clr_dr_intercepts(struct vcpu_svm *svm) | |
301 | { | |
302 | struct vmcb *vmcb = get_host_vmcb(svm); | |
303 | ||
30abaa88 | 304 | vmcb->control.intercepts[INTERCEPT_DR] = 0; |
883b0a91 | 305 | |
8d4846b9 TL |
306 | /* DR7 access must remain intercepted for an SEV-ES guest */ |
307 | if (sev_es_guest(svm->vcpu.kvm)) { | |
308 | vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ); | |
309 | vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE); | |
310 | } | |
311 | ||
883b0a91 JR |
312 | recalc_intercepts(svm); |
313 | } | |
314 | ||
9780d51d | 315 | static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit) |
883b0a91 JR |
316 | { |
317 | struct vmcb *vmcb = get_host_vmcb(svm); | |
318 | ||
9780d51d BM |
319 | WARN_ON_ONCE(bit >= 32); |
320 | vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); | |
883b0a91 JR |
321 | |
322 | recalc_intercepts(svm); | |
323 | } | |
324 | ||
9780d51d | 325 | static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit) |
883b0a91 JR |
326 | { |
327 | struct vmcb *vmcb = get_host_vmcb(svm); | |
328 | ||
9780d51d BM |
329 | WARN_ON_ONCE(bit >= 32); |
330 | vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); | |
883b0a91 JR |
331 | |
332 | recalc_intercepts(svm); | |
333 | } | |
334 | ||
a284ba56 | 335 | static inline void svm_set_intercept(struct vcpu_svm *svm, int bit) |
883b0a91 JR |
336 | { |
337 | struct vmcb *vmcb = get_host_vmcb(svm); | |
338 | ||
c62e2e94 | 339 | vmcb_set_intercept(&vmcb->control, bit); |
883b0a91 JR |
340 | |
341 | recalc_intercepts(svm); | |
342 | } | |
343 | ||
a284ba56 | 344 | static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit) |
883b0a91 JR |
345 | { |
346 | struct vmcb *vmcb = get_host_vmcb(svm); | |
347 | ||
c62e2e94 | 348 | vmcb_clr_intercept(&vmcb->control, bit); |
883b0a91 JR |
349 | |
350 | recalc_intercepts(svm); | |
351 | } | |
352 | ||
a284ba56 | 353 | static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit) |
883b0a91 | 354 | { |
c62e2e94 | 355 | return vmcb_is_intercept(&svm->vmcb->control, bit); |
883b0a91 JR |
356 | } |
357 | ||
358 | static inline bool vgif_enabled(struct vcpu_svm *svm) | |
359 | { | |
360 | return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK); | |
361 | } | |
362 | ||
363 | static inline void enable_gif(struct vcpu_svm *svm) | |
364 | { | |
365 | if (vgif_enabled(svm)) | |
366 | svm->vmcb->control.int_ctl |= V_GIF_MASK; | |
367 | else | |
368 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
369 | } | |
370 | ||
371 | static inline void disable_gif(struct vcpu_svm *svm) | |
372 | { | |
373 | if (vgif_enabled(svm)) | |
374 | svm->vmcb->control.int_ctl &= ~V_GIF_MASK; | |
375 | else | |
376 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
377 | } | |
378 | ||
379 | static inline bool gif_set(struct vcpu_svm *svm) | |
380 | { | |
381 | if (vgif_enabled(svm)) | |
382 | return !!(svm->vmcb->control.int_ctl & V_GIF_MASK); | |
383 | else | |
384 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
385 | } | |
386 | ||
387 | /* svm.c */ | |
761e4169 KS |
388 | #define MSR_CR3_LEGACY_RESERVED_MASK 0xfe7U |
389 | #define MSR_CR3_LEGACY_PAE_RESERVED_MASK 0x7U | |
fb0f33fd | 390 | #define MSR_CR3_LONG_MBZ_MASK 0xfff0000000000000U |
761e4169 | 391 | #define MSR_INVALID 0xffffffffU |
883b0a91 | 392 | |
916391a2 TL |
393 | extern int sev; |
394 | extern int sev_es; | |
291bd20d | 395 | extern bool dump_invalid_vmcb; |
916391a2 | 396 | |
883b0a91 | 397 | u32 svm_msrpm_offset(u32 msr); |
2fcf4876 ML |
398 | u32 *svm_vcpu_alloc_msrpm(void); |
399 | void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm); | |
400 | void svm_vcpu_free_msrpm(u32 *msrpm); | |
401 | ||
72f211ec | 402 | int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer); |
883b0a91 | 403 | void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
c2fe3cd4 | 404 | void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
f55ac304 | 405 | void svm_flush_tlb(struct kvm_vcpu *vcpu); |
883b0a91 | 406 | void disable_nmi_singlestep(struct vcpu_svm *svm); |
cae96af1 PB |
407 | bool svm_smi_blocked(struct kvm_vcpu *vcpu); |
408 | bool svm_nmi_blocked(struct kvm_vcpu *vcpu); | |
409 | bool svm_interrupt_blocked(struct kvm_vcpu *vcpu); | |
ffdf7f9e | 410 | void svm_set_gif(struct vcpu_svm *svm, bool value); |
291bd20d | 411 | int svm_invoke_exit_handler(struct vcpu_svm *svm, u64 exit_code); |
883b0a91 JR |
412 | |
413 | /* nested.c */ | |
414 | ||
415 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ | |
416 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
417 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
418 | ||
01c3b2b5 | 419 | static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu) |
883b0a91 | 420 | { |
e9fd761a PB |
421 | struct vcpu_svm *svm = to_svm(vcpu); |
422 | ||
423 | return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK); | |
883b0a91 JR |
424 | } |
425 | ||
55714cdd PB |
426 | static inline bool nested_exit_on_smi(struct vcpu_svm *svm) |
427 | { | |
c62e2e94 | 428 | return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SMI); |
55714cdd PB |
429 | } |
430 | ||
fc6f7c03 PB |
431 | static inline bool nested_exit_on_intr(struct vcpu_svm *svm) |
432 | { | |
c62e2e94 | 433 | return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_INTR); |
fc6f7c03 PB |
434 | } |
435 | ||
bbdad0b5 PB |
436 | static inline bool nested_exit_on_nmi(struct vcpu_svm *svm) |
437 | { | |
c62e2e94 | 438 | return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_NMI); |
bbdad0b5 PB |
439 | } |
440 | ||
59cd9bc5 VK |
441 | int enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa, |
442 | struct vmcb *nested_vmcb); | |
c513f484 | 443 | void svm_leave_nested(struct vcpu_svm *svm); |
2fcf4876 ML |
444 | void svm_free_nested(struct vcpu_svm *svm); |
445 | int svm_allocate_nested(struct vcpu_svm *svm); | |
883b0a91 JR |
446 | int nested_svm_vmrun(struct vcpu_svm *svm); |
447 | void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb); | |
448 | int nested_svm_vmexit(struct vcpu_svm *svm); | |
449 | int nested_svm_exit_handled(struct vcpu_svm *svm); | |
450 | int nested_svm_check_permissions(struct vcpu_svm *svm); | |
451 | int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, | |
452 | bool has_error_code, u32 error_code); | |
883b0a91 | 453 | int nested_svm_exit_special(struct vcpu_svm *svm); |
2d8a42be | 454 | void sync_nested_vmcb_control(struct vcpu_svm *svm); |
883b0a91 | 455 | |
33b22172 PB |
456 | extern struct kvm_x86_nested_ops svm_nested_ops; |
457 | ||
ef0f6496 JR |
458 | /* avic.c */ |
459 | ||
460 | #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF) | |
461 | #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31 | |
462 | #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) | |
463 | ||
464 | #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL) | |
465 | #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12) | |
466 | #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) | |
467 | #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63) | |
468 | ||
469 | #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL | |
470 | ||
471 | extern int avic; | |
472 | ||
473 | static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data) | |
474 | { | |
475 | svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK; | |
06e7852c | 476 | vmcb_mark_dirty(svm->vmcb, VMCB_AVIC); |
ef0f6496 JR |
477 | } |
478 | ||
479 | static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu) | |
480 | { | |
481 | struct vcpu_svm *svm = to_svm(vcpu); | |
482 | u64 *entry = svm->avic_physical_id_cache; | |
483 | ||
484 | if (!entry) | |
485 | return false; | |
486 | ||
487 | return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); | |
488 | } | |
489 | ||
490 | int avic_ga_log_notifier(u32 ga_tag); | |
491 | void avic_vm_destroy(struct kvm *kvm); | |
492 | int avic_vm_init(struct kvm *kvm); | |
493 | void avic_init_vmcb(struct vcpu_svm *svm); | |
494 | void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate); | |
495 | int avic_incomplete_ipi_interception(struct vcpu_svm *svm); | |
496 | int avic_unaccelerated_access_interception(struct vcpu_svm *svm); | |
497 | int avic_init_vcpu(struct vcpu_svm *svm); | |
498 | void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu); | |
499 | void avic_vcpu_put(struct kvm_vcpu *vcpu); | |
500 | void avic_post_state_restore(struct kvm_vcpu *vcpu); | |
501 | void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu); | |
502 | void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu); | |
503 | bool svm_check_apicv_inhibit_reasons(ulong bit); | |
504 | void svm_pre_update_apicv_exec_ctrl(struct kvm *kvm, bool activate); | |
505 | void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); | |
506 | void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr); | |
507 | void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr); | |
508 | int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec); | |
509 | bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu); | |
510 | int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq, | |
511 | uint32_t guest_irq, bool set); | |
512 | void svm_vcpu_blocking(struct kvm_vcpu *vcpu); | |
513 | void svm_vcpu_unblocking(struct kvm_vcpu *vcpu); | |
514 | ||
eaf78265 JR |
515 | /* sev.c */ |
516 | ||
1edc1459 TL |
517 | #define GHCB_VERSION_MAX 1ULL |
518 | #define GHCB_VERSION_MIN 1ULL | |
519 | ||
291bd20d TL |
520 | #define GHCB_MSR_INFO_POS 0 |
521 | #define GHCB_MSR_INFO_MASK (BIT_ULL(12) - 1) | |
522 | ||
1edc1459 TL |
523 | #define GHCB_MSR_SEV_INFO_RESP 0x001 |
524 | #define GHCB_MSR_SEV_INFO_REQ 0x002 | |
525 | #define GHCB_MSR_VER_MAX_POS 48 | |
526 | #define GHCB_MSR_VER_MAX_MASK 0xffff | |
527 | #define GHCB_MSR_VER_MIN_POS 32 | |
528 | #define GHCB_MSR_VER_MIN_MASK 0xffff | |
529 | #define GHCB_MSR_CBIT_POS 24 | |
530 | #define GHCB_MSR_CBIT_MASK 0xff | |
531 | #define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \ | |
532 | ((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) | \ | |
533 | (((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) | \ | |
534 | (((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) | \ | |
535 | GHCB_MSR_SEV_INFO_RESP) | |
536 | ||
d3694667 TL |
537 | #define GHCB_MSR_CPUID_REQ 0x004 |
538 | #define GHCB_MSR_CPUID_RESP 0x005 | |
539 | #define GHCB_MSR_CPUID_FUNC_POS 32 | |
540 | #define GHCB_MSR_CPUID_FUNC_MASK 0xffffffff | |
541 | #define GHCB_MSR_CPUID_VALUE_POS 32 | |
542 | #define GHCB_MSR_CPUID_VALUE_MASK 0xffffffff | |
543 | #define GHCB_MSR_CPUID_REG_POS 30 | |
544 | #define GHCB_MSR_CPUID_REG_MASK 0x3 | |
545 | ||
eaf78265 JR |
546 | extern unsigned int max_sev_asid; |
547 | ||
eaf78265 JR |
548 | static inline bool svm_sev_enabled(void) |
549 | { | |
550 | return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0; | |
551 | } | |
552 | ||
553 | void sev_vm_destroy(struct kvm *kvm); | |
554 | int svm_mem_enc_op(struct kvm *kvm, void __user *argp); | |
555 | int svm_register_enc_region(struct kvm *kvm, | |
556 | struct kvm_enc_region *range); | |
557 | int svm_unregister_enc_region(struct kvm *kvm, | |
558 | struct kvm_enc_region *range); | |
559 | void pre_sev_run(struct vcpu_svm *svm, int cpu); | |
916391a2 | 560 | void __init sev_hardware_setup(void); |
eaf78265 | 561 | void sev_hardware_teardown(void); |
add5e2f0 | 562 | void sev_free_vcpu(struct kvm_vcpu *vcpu); |
291bd20d | 563 | int sev_handle_vmgexit(struct vcpu_svm *svm); |
eaf78265 | 564 | |
883b0a91 | 565 | #endif |