[linux-block.git] / arch / x86 / kvm / svm / svm.h

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Kernel-based Virtual Machine driver for Linux
 *
 * AMD SVM support
 *
 * Copyright (C) 2006 Qumranet, Inc.
 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
 *
 * Authors:
 *   Yaniv Kamay  <yaniv@qumranet.com>
 *   Avi Kivity   <avi@qumranet.com>
 */

#ifndef __SVM_SVM_H
#define __SVM_SVM_H

#include <linux/kvm_types.h>
#include <linux/kvm_host.h>

#include <asm/svm.h>

static const u32 host_save_user_msrs[] = {
#ifdef CONFIG_X86_64
	MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
	MSR_FS_BASE,
#endif
	MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
	MSR_TSC_AUX,
};

#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)

#define MSRPM_OFFSETS	16
extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
extern bool npt_enabled;

enum {
	VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
			    pause filter count */
	VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
	VMCB_ASID,	 /* ASID */
	VMCB_INTR,	 /* int_ctl, int_vector */
	VMCB_NPT,        /* npt_en, nCR3, gPAT */
	VMCB_CR,	 /* CR0, CR3, CR4, EFER */
	VMCB_DR,         /* DR6, DR7 */
	VMCB_DT,         /* GDT, IDT */
	VMCB_SEG,        /* CS, DS, SS, ES, CPL */
	VMCB_CR2,        /* CR2 only */
	VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
	VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
			  * AVIC PHYSICAL_TABLE pointer,
			  * AVIC LOGICAL_TABLE pointer
			  */
	VMCB_DIRTY_MAX,
};

/* TPR and CR2 are always written before VMRUN */
#define VMCB_ALWAYS_DIRTY_MASK	((1U << VMCB_INTR) | (1U << VMCB_CR2))

struct kvm_sev_info {
	bool active;		/* SEV enabled guest */
	unsigned int asid;	/* ASID used for this guest */
	unsigned int handle;	/* SEV firmware handle */
	int fd;			/* SEV device fd */
	unsigned long pages_locked; /* Number of pages locked */
	struct list_head regions_list;  /* List of registered regions */
};

struct kvm_svm {
	struct kvm kvm;

	/* Struct members for AVIC */
	u32 avic_vm_id;
	struct page *avic_logical_id_table_page;
	struct page *avic_physical_id_table_page;
	struct hlist_node hnode;

	struct kvm_sev_info sev_info;
};

struct kvm_vcpu;

struct svm_nested_state {
	struct vmcb *hsave;
	u64 hsave_msr;
	u64 vm_cr_msr;
	u64 vmcb12_gpa;

	/* These are the merged vectors */
	u32 *msrpm;

	/* A VMRUN has started but has not yet been performed, so
	 * we cannot inject a nested vmexit yet.  */
	bool nested_run_pending;

	/* cache for control fields of the guest */
	struct vmcb_control_area ctl;
};

struct vcpu_svm {
	struct kvm_vcpu vcpu;
	struct vmcb *vmcb;
	unsigned long vmcb_pa;
	struct svm_cpu_data *svm_data;
	uint64_t asid_generation;
	uint64_t sysenter_esp;
	uint64_t sysenter_eip;
	uint64_t tsc_aux;

	u64 msr_decfg;

	u64 next_rip;

	u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
	struct {
		u16 fs;
		u16 gs;
		u16 ldt;
		u64 gs_base;
	} host;

	u64 spec_ctrl;
	/*
	 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
	 * translated into the appropriate L2_CFG bits on the host to
	 * perform speculative control.
	 */
	u64 virt_spec_ctrl;

	u32 *msrpm;

	ulong nmi_iret_rip;

	struct svm_nested_state nested;

	bool nmi_singlestep;
	u64 nmi_singlestep_guest_rflags;

	unsigned int3_injected;
	unsigned long int3_rip;

	/* cached guest cpuid flags for faster access */
	bool nrips_enabled	: 1;

	u32 ldr_reg;
	u32 dfr_reg;
	struct page *avic_backing_page;
	u64 *avic_physical_id_cache;
	bool avic_is_running;

	/*
	 * Per-vcpu list of struct amd_svm_iommu_ir:
	 * This is used mainly to store interrupt remapping information used
	 * when update the vcpu affinity. This avoids the need to scan for
	 * IRTE and try to match ga_tag in the IOMMU driver.
	 */
	struct list_head ir_list;
	spinlock_t ir_list_lock;
};

struct svm_cpu_data {
	int cpu;

	u64 asid_generation;
	u32 max_asid;
	u32 next_asid;
	u32 min_asid;
	struct kvm_ldttss_desc *tss_desc;

	struct page *save_area;
	struct vmcb *current_vmcb;

	/* index = sev_asid, value = vmcb pointer */
	struct vmcb **sev_vmcbs;
};

DECLARE_PER_CPU(struct svm_cpu_data *, svm_data);

void recalc_intercepts(struct vcpu_svm *svm);

static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
{
	return container_of(kvm, struct kvm_svm, kvm);
}

static inline void vmcb_mark_all_dirty(struct vmcb *vmcb)
{
	vmcb->control.clean = 0;
}

static inline void vmcb_mark_all_clean(struct vmcb *vmcb)
{
	vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
			       & ~VMCB_ALWAYS_DIRTY_MASK;
}

static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit)
{
	vmcb->control.clean &= ~(1 << bit);
}

static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
{
	return container_of(vcpu, struct vcpu_svm, vcpu);
}

static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
{
	if (is_guest_mode(&svm->vcpu))
		return svm->nested.hsave;
	else
		return svm->vmcb;
}

static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit)
{
	WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
	__set_bit(bit, (unsigned long *)&control->intercepts);
}

static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit)
{
	WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
	__clear_bit(bit, (unsigned long *)&control->intercepts);
}

static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit)
{
	WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
	return test_bit(bit, (unsigned long *)&control->intercepts);
}

static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	vmcb_set_intercept(&vmcb->control, bit);

	recalc_intercepts(svm);
}

static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	vmcb_clr_intercept(&vmcb->control, bit);

	recalc_intercepts(svm);
}

static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	return vmcb_is_intercept(&vmcb->control, bit);
}

static inline void set_dr_intercepts(struct vcpu_svm *svm)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_READ);
	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_READ);
	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_READ);
	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_READ);
	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_READ);
	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_READ);
	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_READ);
	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ);
	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_WRITE);
	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_WRITE);
	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_WRITE);
	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_WRITE);
	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_WRITE);
	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_WRITE);
	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE);
	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE);

	recalc_intercepts(svm);
}

static inline void clr_dr_intercepts(struct vcpu_svm *svm)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	vmcb->control.intercepts[INTERCEPT_DR] = 0;

	recalc_intercepts(svm);
}

static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	WARN_ON_ONCE(bit >= 32);
	vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);

	recalc_intercepts(svm);
}

static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	WARN_ON_ONCE(bit >= 32);
	vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);

	recalc_intercepts(svm);
}

static inline void svm_set_intercept(struct vcpu_svm *svm, int bit)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	vmcb->control.intercept |= (1ULL << bit);

	recalc_intercepts(svm);
}

static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	vmcb->control.intercept &= ~(1ULL << bit);

	recalc_intercepts(svm);
}

static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit)
{
	return (svm->vmcb->control.intercept & (1ULL << bit)) != 0;
}

static inline bool vgif_enabled(struct vcpu_svm *svm)
{
	return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
}

static inline void enable_gif(struct vcpu_svm *svm)
{
	if (vgif_enabled(svm))
		svm->vmcb->control.int_ctl |= V_GIF_MASK;
	else
		svm->vcpu.arch.hflags |= HF_GIF_MASK;
}

static inline void disable_gif(struct vcpu_svm *svm)
{
	if (vgif_enabled(svm))
		svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
	else
		svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
}

static inline bool gif_set(struct vcpu_svm *svm)
{
	if (vgif_enabled(svm))
		return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
	else
		return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
}

/* svm.c */
#define MSR_CR3_LEGACY_RESERVED_MASK		0xfe7U
#define MSR_CR3_LEGACY_PAE_RESERVED_MASK	0x7U
#define MSR_CR3_LONG_RESERVED_MASK		0xfff0000000000fe7U
#define MSR_INVALID				0xffffffffU

u32 svm_msrpm_offset(u32 msr);
void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer);
void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
void svm_flush_tlb(struct kvm_vcpu *vcpu);
void disable_nmi_singlestep(struct vcpu_svm *svm);
bool svm_smi_blocked(struct kvm_vcpu *vcpu);
bool svm_nmi_blocked(struct kvm_vcpu *vcpu);
bool svm_interrupt_blocked(struct kvm_vcpu *vcpu);
void svm_set_gif(struct vcpu_svm *svm, bool value);

/* nested.c */

#define NESTED_EXIT_HOST	0	/* Exit handled on host level */
#define NESTED_EXIT_DONE	1	/* Exit caused nested vmexit  */
#define NESTED_EXIT_CONTINUE	2	/* Further checks needed      */

static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu)
{
	struct vcpu_svm *svm = to_svm(vcpu);

	return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK);
}

static inline bool nested_exit_on_smi(struct vcpu_svm *svm)
{
	return (svm->nested.ctl.intercept & (1ULL << INTERCEPT_SMI));
}

static inline bool nested_exit_on_intr(struct vcpu_svm *svm)
{
	return (svm->nested.ctl.intercept & (1ULL << INTERCEPT_INTR));
}

static inline bool nested_exit_on_nmi(struct vcpu_svm *svm)
{
	return (svm->nested.ctl.intercept & (1ULL << INTERCEPT_NMI));
}

int enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
			 struct vmcb *nested_vmcb);
void svm_leave_nested(struct vcpu_svm *svm);
int nested_svm_vmrun(struct vcpu_svm *svm);
void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb);
int nested_svm_vmexit(struct vcpu_svm *svm);
int nested_svm_exit_handled(struct vcpu_svm *svm);
int nested_svm_check_permissions(struct vcpu_svm *svm);
int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
			       bool has_error_code, u32 error_code);
int nested_svm_exit_special(struct vcpu_svm *svm);
void sync_nested_vmcb_control(struct vcpu_svm *svm);

extern struct kvm_x86_nested_ops svm_nested_ops;

/* avic.c */

#define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK	(0xFF)
#define AVIC_LOGICAL_ID_ENTRY_VALID_BIT			31
#define AVIC_LOGICAL_ID_ENTRY_VALID_MASK		(1 << 31)

#define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK	(0xFFULL)
#define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK	(0xFFFFFFFFFFULL << 12)
#define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK		(1ULL << 62)
#define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK		(1ULL << 63)

#define VMCB_AVIC_APIC_BAR_MASK		0xFFFFFFFFFF000ULL

extern int avic;

static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
{
	svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
	vmcb_mark_dirty(svm->vmcb, VMCB_AVIC);
}

static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
{
	struct vcpu_svm *svm = to_svm(vcpu);
	u64 *entry = svm->avic_physical_id_cache;

	if (!entry)
		return false;

	return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
}

int avic_ga_log_notifier(u32 ga_tag);
void avic_vm_destroy(struct kvm *kvm);
int avic_vm_init(struct kvm *kvm);
void avic_init_vmcb(struct vcpu_svm *svm);
void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate);
int avic_incomplete_ipi_interception(struct vcpu_svm *svm);
int avic_unaccelerated_access_interception(struct vcpu_svm *svm);
int avic_init_vcpu(struct vcpu_svm *svm);
void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
void avic_vcpu_put(struct kvm_vcpu *vcpu);
void avic_post_state_restore(struct kvm_vcpu *vcpu);
void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu);
bool svm_check_apicv_inhibit_reasons(ulong bit);
void svm_pre_update_apicv_exec_ctrl(struct kvm *kvm, bool activate);
void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap);
void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr);
void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr);
int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec);
bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu);
int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
		       uint32_t guest_irq, bool set);
void svm_vcpu_blocking(struct kvm_vcpu *vcpu);
void svm_vcpu_unblocking(struct kvm_vcpu *vcpu);

/* sev.c */

extern unsigned int max_sev_asid;

static inline bool sev_guest(struct kvm *kvm)
{
#ifdef CONFIG_KVM_AMD_SEV
	struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;

	return sev->active;
#else
	return false;
#endif
}

static inline bool svm_sev_enabled(void)
{
	return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
}

void sev_vm_destroy(struct kvm *kvm);
int svm_mem_enc_op(struct kvm *kvm, void __user *argp);
int svm_register_enc_region(struct kvm *kvm,
			    struct kvm_enc_region *range);
int svm_unregister_enc_region(struct kvm *kvm,
			      struct kvm_enc_region *range);
void pre_sev_run(struct vcpu_svm *svm, int cpu);
int __init sev_hardware_setup(void);
void sev_hardware_teardown(void);

#endif
Commit	Line	Data
883b0a91 JR	1	// SPDX-License-Identifier: GPL-2.0-only
	2	/*
	3	* Kernel-based Virtual Machine driver for Linux
	4	*
	5	* AMD SVM support
	6	*
	7	* Copyright (C) 2006 Qumranet, Inc.
	8	* Copyright 2010 Red Hat, Inc. and/or its affiliates.
	9	*
	10	* Authors:
	11	* Yaniv Kamay <yaniv@qumranet.com>
	12	* Avi Kivity <avi@qumranet.com>
	13	*/
	14
	15	#ifndef __SVM_SVM_H
	16	#define __SVM_SVM_H
	17
	18	#include <linux/kvm_types.h>
	19	#include <linux/kvm_host.h>
	20
	21	#include <asm/svm.h>
	22
	23	static const u32 host_save_user_msrs[] = {
	24	#ifdef CONFIG_X86_64
	25	MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
	26	MSR_FS_BASE,
	27	#endif
	28	MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
	29	MSR_TSC_AUX,
	30	};
	31
	32	#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
	33
	34	#define MSRPM_OFFSETS 16
	35	extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
	36	extern bool npt_enabled;
	37
	38	enum {
	39	VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
	40	pause filter count */
	41	VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
	42	VMCB_ASID, /* ASID */
	43	VMCB_INTR, /* int_ctl, int_vector */
	44	VMCB_NPT, /* npt_en, nCR3, gPAT */
	45	VMCB_CR, /* CR0, CR3, CR4, EFER */
	46	VMCB_DR, /* DR6, DR7 */
	47	VMCB_DT, /* GDT, IDT */
	48	VMCB_SEG, /* CS, DS, SS, ES, CPL */
	49	VMCB_CR2, /* CR2 only */
	50	VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
	51	VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
	52	* AVIC PHYSICAL_TABLE pointer,
	53	* AVIC LOGICAL_TABLE pointer
	54	*/
	55	VMCB_DIRTY_MAX,
	56	};
	57
	58	/* TPR and CR2 are always written before VMRUN */
	59	#define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) \| (1U << VMCB_CR2))
	60
	61	struct kvm_sev_info {
	62	bool active; /* SEV enabled guest */
	63	unsigned int asid; /* ASID used for this guest */
	64	unsigned int handle; /* SEV firmware handle */
65	int fd; /* SEV device fd */
66	unsigned long pages_locked; /* Number of pages locked */
67	struct list_head regions_list; /* List of registered regions */
68	};
69
70	struct kvm_svm {
71	struct kvm kvm;
72
73	/* Struct members for AVIC */
74	u32 avic_vm_id;
75	struct page *avic_logical_id_table_page;
76	struct page *avic_physical_id_table_page;
77	struct hlist_node hnode;
78
79	struct kvm_sev_info sev_info;
80	};
81
82	struct kvm_vcpu;
83
7693b3eb	84	struct svm_nested_state {
883b0a91 JR	85	struct vmcb *hsave;
	86	u64 hsave_msr;
	87	u64 vm_cr_msr;
0dd16b5b	88	u64 vmcb12_gpa;
883b0a91 JR	89
	90	/* These are the merged vectors */
	91	u32 *msrpm;
	92
f74f9414 PB	93	/* A VMRUN has started but has not yet been performed, so
	94	* we cannot inject a nested vmexit yet. */
	95	bool nested_run_pending;
	96
e670bf68 PB	97	/* cache for control fields of the guest */
e670bf68 PB	98	struct vmcb_control_area ctl;
883b0a91 JR	99	};
	100
	101	struct vcpu_svm {
	102	struct kvm_vcpu vcpu;
	103	struct vmcb *vmcb;
	104	unsigned long vmcb_pa;
	105	struct svm_cpu_data *svm_data;
	106	uint64_t asid_generation;
	107	uint64_t sysenter_esp;
	108	uint64_t sysenter_eip;
	109	uint64_t tsc_aux;
	110
	111	u64 msr_decfg;
	112
	113	u64 next_rip;
	114
	115	u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
	116	struct {
	117	u16 fs;
	118	u16 gs;
	119	u16 ldt;
	120	u64 gs_base;
	121	} host;
	122
	123	u64 spec_ctrl;
	124	/*
	125	* Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
	126	* translated into the appropriate L2_CFG bits on the host to
	127	* perform speculative control.
	128	*/
	129	u64 virt_spec_ctrl;
	130
	131	u32 *msrpm;
	132
	133	ulong nmi_iret_rip;
	134
7693b3eb	135	struct svm_nested_state nested;
883b0a91 JR	136
	137	bool nmi_singlestep;
	138	u64 nmi_singlestep_guest_rflags;
	139
	140	unsigned int3_injected;
	141	unsigned long int3_rip;
	142
	143	/* cached guest cpuid flags for faster access */
	144	bool nrips_enabled : 1;
	145
	146	u32 ldr_reg;
	147	u32 dfr_reg;
	148	struct page *avic_backing_page;
	149	u64 *avic_physical_id_cache;
	150	bool avic_is_running;
	151
	152	/*
	153	* Per-vcpu list of struct amd_svm_iommu_ir:
	154	* This is used mainly to store interrupt remapping information used
	155	* when update the vcpu affinity. This avoids the need to scan for
	156	* IRTE and try to match ga_tag in the IOMMU driver.
	157	*/
	158	struct list_head ir_list;
	159	spinlock_t ir_list_lock;
883b0a91 JR	160	};
883b0a91 JR	161
eaf78265 JR	162	struct svm_cpu_data {
	163	int cpu;
	164
	165	u64 asid_generation;
	166	u32 max_asid;
	167	u32 next_asid;
	168	u32 min_asid;
	169	struct kvm_ldttss_desc *tss_desc;
	170
	171	struct page *save_area;
	172	struct vmcb *current_vmcb;
	173
	174	/* index = sev_asid, value = vmcb pointer */
	175	struct vmcb **sev_vmcbs;
	176	};
	177
	178	DECLARE_PER_CPU(struct svm_cpu_data *, svm_data);
	179
883b0a91 JR	180	void recalc_intercepts(struct vcpu_svm *svm);
883b0a91 JR	181
ef0f6496 JR	182	static inline struct kvm_svm to_kvm_svm(struct kvm kvm)
	183	{
	184	return container_of(kvm, struct kvm_svm, kvm);
	185	}
	186
06e7852c	187	static inline void vmcb_mark_all_dirty(struct vmcb *vmcb)
883b0a91 JR	188	{
	189	vmcb->control.clean = 0;
	190	}
	191
06e7852c	192	static inline void vmcb_mark_all_clean(struct vmcb *vmcb)
883b0a91 JR	193	{
	194	vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
	195	& ~VMCB_ALWAYS_DIRTY_MASK;
	196	}
	197
06e7852c	198	static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit)
883b0a91 JR	199	{
	200	vmcb->control.clean &= ~(1 << bit);
	201	}
	202
	203	static inline struct vcpu_svm to_svm(struct kvm_vcpu vcpu)
	204	{
	205	return container_of(vcpu, struct vcpu_svm, vcpu);
	206	}
	207
	208	static inline struct vmcb get_host_vmcb(struct vcpu_svm svm)
	209	{
	210	if (is_guest_mode(&svm->vcpu))
	211	return svm->nested.hsave;
	212	else
	213	return svm->vmcb;
	214	}
	215
c45ad722 BM	216	static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit)
	217	{
	218	WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
	219	__set_bit(bit, (unsigned long *)&control->intercepts);
	220	}
	221
	222	static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit)
	223	{
	224	WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
	225	__clear_bit(bit, (unsigned long *)&control->intercepts);
	226	}
	227
	228	static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit)
	229	{
	230	WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
	231	return test_bit(bit, (unsigned long *)&control->intercepts);
	232	}
	233
883b0a91 JR	234	static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
	235	{
	236	struct vmcb *vmcb = get_host_vmcb(svm);
	237
03bfeeb9	238	vmcb_set_intercept(&vmcb->control, bit);
883b0a91 JR	239
	240	recalc_intercepts(svm);
	241	}
	242
	243	static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
	244	{
	245	struct vmcb *vmcb = get_host_vmcb(svm);
	246
03bfeeb9	247	vmcb_clr_intercept(&vmcb->control, bit);
883b0a91 JR	248
	249	recalc_intercepts(svm);
	250	}
	251
	252	static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
	253	{
	254	struct vmcb *vmcb = get_host_vmcb(svm);
	255
03bfeeb9	256	return vmcb_is_intercept(&vmcb->control, bit);
883b0a91 JR	257	}
	258
	259	static inline void set_dr_intercepts(struct vcpu_svm *svm)
	260	{
	261	struct vmcb *vmcb = get_host_vmcb(svm);
	262
30abaa88 BM	263	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_READ);
	264	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_READ);
	265	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_READ);
	266	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_READ);
	267	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_READ);
	268	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_READ);
	269	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_READ);
	270	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ);
	271	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_WRITE);
	272	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_WRITE);
	273	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_WRITE);
	274	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_WRITE);
	275	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_WRITE);
	276	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_WRITE);
	277	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE);
	278	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE);
883b0a91 JR	279
	280	recalc_intercepts(svm);
	281	}
	282
	283	static inline void clr_dr_intercepts(struct vcpu_svm *svm)
	284	{
	285	struct vmcb *vmcb = get_host_vmcb(svm);
	286
30abaa88	287	vmcb->control.intercepts[INTERCEPT_DR] = 0;
883b0a91 JR	288
	289	recalc_intercepts(svm);
	290	}
	291
9780d51d	292	static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit)
883b0a91 JR	293	{
	294	struct vmcb *vmcb = get_host_vmcb(svm);
	295
9780d51d BM	296	WARN_ON_ONCE(bit >= 32);
9780d51d BM	297	vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);
883b0a91 JR	298
	299	recalc_intercepts(svm);
	300	}
	301
9780d51d	302	static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit)
883b0a91 JR	303	{
	304	struct vmcb *vmcb = get_host_vmcb(svm);
	305
9780d51d BM	306	WARN_ON_ONCE(bit >= 32);
9780d51d BM	307	vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);
883b0a91 JR	308
	309	recalc_intercepts(svm);
	310	}
	311
a284ba56	312	static inline void svm_set_intercept(struct vcpu_svm *svm, int bit)
883b0a91 JR	313	{
	314	struct vmcb *vmcb = get_host_vmcb(svm);
	315
	316	vmcb->control.intercept \|= (1ULL << bit);
	317
	318	recalc_intercepts(svm);
	319	}
	320
a284ba56	321	static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit)
883b0a91 JR	322	{
	323	struct vmcb *vmcb = get_host_vmcb(svm);
	324
	325	vmcb->control.intercept &= ~(1ULL << bit);
	326
	327	recalc_intercepts(svm);
	328	}
	329
a284ba56	330	static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit)
883b0a91 JR	331	{
	332	return (svm->vmcb->control.intercept & (1ULL << bit)) != 0;
	333	}
	334
	335	static inline bool vgif_enabled(struct vcpu_svm *svm)
	336	{
	337	return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
	338	}
	339
	340	static inline void enable_gif(struct vcpu_svm *svm)
	341	{
	342	if (vgif_enabled(svm))
	343	svm->vmcb->control.int_ctl \|= V_GIF_MASK;
	344	else
	345	svm->vcpu.arch.hflags \|= HF_GIF_MASK;
	346	}
	347
	348	static inline void disable_gif(struct vcpu_svm *svm)
	349	{
	350	if (vgif_enabled(svm))
	351	svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
	352	else
	353	svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
	354	}
	355
	356	static inline bool gif_set(struct vcpu_svm *svm)
	357	{
	358	if (vgif_enabled(svm))
	359	return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
	360	else
	361	return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
	362	}
	363
	364	/* svm.c */
761e4169 KS	365	#define MSR_CR3_LEGACY_RESERVED_MASK 0xfe7U
	366	#define MSR_CR3_LEGACY_PAE_RESERVED_MASK 0x7U
	367	#define MSR_CR3_LONG_RESERVED_MASK 0xfff0000000000fe7U
	368	#define MSR_INVALID 0xffffffffU
883b0a91 JR	369
	370	u32 svm_msrpm_offset(u32 msr);
	371	void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer);
	372	void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
	373	int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
f55ac304	374	void svm_flush_tlb(struct kvm_vcpu *vcpu);
883b0a91	375	void disable_nmi_singlestep(struct vcpu_svm *svm);
cae96af1 PB	376	bool svm_smi_blocked(struct kvm_vcpu *vcpu);
	377	bool svm_nmi_blocked(struct kvm_vcpu *vcpu);
	378	bool svm_interrupt_blocked(struct kvm_vcpu *vcpu);
ffdf7f9e	379	void svm_set_gif(struct vcpu_svm *svm, bool value);
883b0a91 JR	380
	381	/* nested.c */
	382
	383	#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
	384	#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
	385	#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
	386
01c3b2b5	387	static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu)
883b0a91	388	{
e9fd761a PB	389	struct vcpu_svm *svm = to_svm(vcpu);
	390
	391	return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK);
883b0a91 JR	392	}
883b0a91 JR	393
55714cdd PB	394	static inline bool nested_exit_on_smi(struct vcpu_svm *svm)
55714cdd PB	395	{
e670bf68	396	return (svm->nested.ctl.intercept & (1ULL << INTERCEPT_SMI));
55714cdd PB	397	}
55714cdd PB	398
fc6f7c03 PB	399	static inline bool nested_exit_on_intr(struct vcpu_svm *svm)
fc6f7c03 PB	400	{
e670bf68	401	return (svm->nested.ctl.intercept & (1ULL << INTERCEPT_INTR));
fc6f7c03 PB	402	}
fc6f7c03 PB	403
bbdad0b5 PB	404	static inline bool nested_exit_on_nmi(struct vcpu_svm *svm)
bbdad0b5 PB	405	{
e670bf68	406	return (svm->nested.ctl.intercept & (1ULL << INTERCEPT_NMI));
bbdad0b5 PB	407	}
bbdad0b5 PB	408
59cd9bc5 VK	409	int enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
59cd9bc5 VK	410	struct vmcb *nested_vmcb);
c513f484	411	void svm_leave_nested(struct vcpu_svm *svm);
883b0a91 JR	412	int nested_svm_vmrun(struct vcpu_svm *svm);
	413	void nested_svm_vmloadsave(struct vmcb from_vmcb, struct vmcb to_vmcb);
	414	int nested_svm_vmexit(struct vcpu_svm *svm);
	415	int nested_svm_exit_handled(struct vcpu_svm *svm);
	416	int nested_svm_check_permissions(struct vcpu_svm *svm);
	417	int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
	418	bool has_error_code, u32 error_code);
883b0a91	419	int nested_svm_exit_special(struct vcpu_svm *svm);
2d8a42be	420	void sync_nested_vmcb_control(struct vcpu_svm *svm);
883b0a91	421
33b22172 PB	422	extern struct kvm_x86_nested_ops svm_nested_ops;
33b22172 PB	423
ef0f6496 JR	424	/* avic.c */
	425
	426	#define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
	427	#define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31
	428	#define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
	429
	430	#define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
	431	#define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
	432	#define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
	433	#define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
	434
	435	#define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
	436
	437	extern int avic;
	438
	439	static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
	440	{
	441	svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
06e7852c	442	vmcb_mark_dirty(svm->vmcb, VMCB_AVIC);
ef0f6496 JR	443	}
	444
	445	static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
	446	{
	447	struct vcpu_svm *svm = to_svm(vcpu);
	448	u64 *entry = svm->avic_physical_id_cache;
	449
	450	if (!entry)
	451	return false;
	452
	453	return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
	454	}
	455
	456	int avic_ga_log_notifier(u32 ga_tag);
	457	void avic_vm_destroy(struct kvm *kvm);
	458	int avic_vm_init(struct kvm *kvm);
	459	void avic_init_vmcb(struct vcpu_svm *svm);
	460	void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate);
	461	int avic_incomplete_ipi_interception(struct vcpu_svm *svm);
	462	int avic_unaccelerated_access_interception(struct vcpu_svm *svm);
	463	int avic_init_vcpu(struct vcpu_svm *svm);
	464	void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
	465	void avic_vcpu_put(struct kvm_vcpu *vcpu);
	466	void avic_post_state_restore(struct kvm_vcpu *vcpu);
	467	void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
	468	void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu);
	469	bool svm_check_apicv_inhibit_reasons(ulong bit);
	470	void svm_pre_update_apicv_exec_ctrl(struct kvm *kvm, bool activate);
	471	void svm_load_eoi_exitmap(struct kvm_vcpu vcpu, u64 eoi_exit_bitmap);
	472	void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr);
	473	void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr);
	474	int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec);
	475	bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu);
	476	int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
	477	uint32_t guest_irq, bool set);
	478	void svm_vcpu_blocking(struct kvm_vcpu *vcpu);
	479	void svm_vcpu_unblocking(struct kvm_vcpu *vcpu);
	480
eaf78265 JR	481	/* sev.c */
	482
	483	extern unsigned int max_sev_asid;
	484
	485	static inline bool sev_guest(struct kvm *kvm)
	486	{
	487	#ifdef CONFIG_KVM_AMD_SEV
	488	struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
	489
	490	return sev->active;
	491	#else
	492	return false;
	493	#endif
	494	}
	495
	496	static inline bool svm_sev_enabled(void)
	497	{
	498	return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
	499	}
	500
	501	void sev_vm_destroy(struct kvm *kvm);
	502	int svm_mem_enc_op(struct kvm kvm, void __user argp);
	503	int svm_register_enc_region(struct kvm *kvm,
	504	struct kvm_enc_region *range);
	505	int svm_unregister_enc_region(struct kvm *kvm,
	506	struct kvm_enc_region *range);
	507	void pre_sev_run(struct vcpu_svm *svm, int cpu);
	508	int __init sev_hardware_setup(void);
	509	void sev_hardware_teardown(void);
	510
883b0a91	511	#endif