[linux-block.git] / arch / x86 / kvm / svm / svm.h

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Kernel-based Virtual Machine driver for Linux
 *
 * AMD SVM support
 *
 * Copyright (C) 2006 Qumranet, Inc.
 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
 *
 * Authors:
 *   Yaniv Kamay  <yaniv@qumranet.com>
 *   Avi Kivity   <avi@qumranet.com>
 */

#ifndef __SVM_SVM_H
#define __SVM_SVM_H

#include <linux/kvm_types.h>
#include <linux/kvm_host.h>
#include <linux/bits.h>

#include <asm/svm.h>

static const u32 host_save_user_msrs[] = {
#ifdef CONFIG_X86_64
	MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
	MSR_FS_BASE,
#endif
	MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
	MSR_TSC_AUX,
};

#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)

#define MAX_DIRECT_ACCESS_MSRS	15
#define MSRPM_OFFSETS	16
extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
extern bool npt_enabled;

enum {
	VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
			    pause filter count */
	VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
	VMCB_ASID,	 /* ASID */
	VMCB_INTR,	 /* int_ctl, int_vector */
	VMCB_NPT,        /* npt_en, nCR3, gPAT */
	VMCB_CR,	 /* CR0, CR3, CR4, EFER */
	VMCB_DR,         /* DR6, DR7 */
	VMCB_DT,         /* GDT, IDT */
	VMCB_SEG,        /* CS, DS, SS, ES, CPL */
	VMCB_CR2,        /* CR2 only */
	VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
	VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
			  * AVIC PHYSICAL_TABLE pointer,
			  * AVIC LOGICAL_TABLE pointer
			  */
	VMCB_DIRTY_MAX,
};

/* TPR and CR2 are always written before VMRUN */
#define VMCB_ALWAYS_DIRTY_MASK	((1U << VMCB_INTR) | (1U << VMCB_CR2))

struct kvm_sev_info {
	bool active;		/* SEV enabled guest */
	bool es_active;		/* SEV-ES enabled guest */
	unsigned int asid;	/* ASID used for this guest */
	unsigned int handle;	/* SEV firmware handle */
	int fd;			/* SEV device fd */
	unsigned long pages_locked; /* Number of pages locked */
	struct list_head regions_list;  /* List of registered regions */
};

struct kvm_svm {
	struct kvm kvm;

	/* Struct members for AVIC */
	u32 avic_vm_id;
	struct page *avic_logical_id_table_page;
	struct page *avic_physical_id_table_page;
	struct hlist_node hnode;

	struct kvm_sev_info sev_info;
};

struct kvm_vcpu;

struct svm_nested_state {
	struct vmcb *hsave;
	u64 hsave_msr;
	u64 vm_cr_msr;
	u64 vmcb12_gpa;

	/* These are the merged vectors */
	u32 *msrpm;

	/* A VMRUN has started but has not yet been performed, so
	 * we cannot inject a nested vmexit yet.  */
	bool nested_run_pending;

	/* cache for control fields of the guest */
	struct vmcb_control_area ctl;

	bool initialized;
};

struct vcpu_svm {
	struct kvm_vcpu vcpu;
	struct vmcb *vmcb;
	unsigned long vmcb_pa;
	struct svm_cpu_data *svm_data;
	u32 asid;
	uint64_t asid_generation;
	uint64_t sysenter_esp;
	uint64_t sysenter_eip;
	uint64_t tsc_aux;

	u64 msr_decfg;

	u64 next_rip;

	u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
	struct {
		u16 fs;
		u16 gs;
		u16 ldt;
		u64 gs_base;
	} host;

	u64 spec_ctrl;
	/*
	 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
	 * translated into the appropriate L2_CFG bits on the host to
	 * perform speculative control.
	 */
	u64 virt_spec_ctrl;

	u32 *msrpm;

	ulong nmi_iret_rip;

	struct svm_nested_state nested;

	bool nmi_singlestep;
	u64 nmi_singlestep_guest_rflags;

	unsigned int3_injected;
	unsigned long int3_rip;

	/* cached guest cpuid flags for faster access */
	bool nrips_enabled	: 1;

	u32 ldr_reg;
	u32 dfr_reg;
	struct page *avic_backing_page;
	u64 *avic_physical_id_cache;
	bool avic_is_running;

	/*
	 * Per-vcpu list of struct amd_svm_iommu_ir:
	 * This is used mainly to store interrupt remapping information used
	 * when update the vcpu affinity. This avoids the need to scan for
	 * IRTE and try to match ga_tag in the IOMMU driver.
	 */
	struct list_head ir_list;
	spinlock_t ir_list_lock;

	/* Save desired MSR intercept (read: pass-through) state */
	struct {
		DECLARE_BITMAP(read, MAX_DIRECT_ACCESS_MSRS);
		DECLARE_BITMAP(write, MAX_DIRECT_ACCESS_MSRS);
	} shadow_msr_intercept;

	/* SEV-ES support */
	struct vmcb_save_area *vmsa;
	struct ghcb *ghcb;
	struct kvm_host_map ghcb_map;

	/* SEV-ES scratch area support */
	void *ghcb_sa;
	u64 ghcb_sa_len;
	bool ghcb_sa_sync;
	bool ghcb_sa_free;
};

struct svm_cpu_data {
	int cpu;

	u64 asid_generation;
	u32 max_asid;
	u32 next_asid;
	u32 min_asid;
	struct kvm_ldttss_desc *tss_desc;

	struct page *save_area;
	struct vmcb *current_vmcb;

	/* index = sev_asid, value = vmcb pointer */
	struct vmcb **sev_vmcbs;
};

DECLARE_PER_CPU(struct svm_cpu_data *, svm_data);

void recalc_intercepts(struct vcpu_svm *svm);

static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
{
	return container_of(kvm, struct kvm_svm, kvm);
}

static inline bool sev_guest(struct kvm *kvm)
{
#ifdef CONFIG_KVM_AMD_SEV
	struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;

	return sev->active;
#else
	return false;
#endif
}

static inline bool sev_es_guest(struct kvm *kvm)
{
#ifdef CONFIG_KVM_AMD_SEV
	struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;

	return sev_guest(kvm) && sev->es_active;
#else
	return false;
#endif
}

static inline void vmcb_mark_all_dirty(struct vmcb *vmcb)
{
	vmcb->control.clean = 0;
}

static inline void vmcb_mark_all_clean(struct vmcb *vmcb)
{
	vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
			       & ~VMCB_ALWAYS_DIRTY_MASK;
}

static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit)
{
	vmcb->control.clean &= ~(1 << bit);
}

static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
{
	return container_of(vcpu, struct vcpu_svm, vcpu);
}

static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
{
	if (is_guest_mode(&svm->vcpu))
		return svm->nested.hsave;
	else
		return svm->vmcb;
}

static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit)
{
	WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
	__set_bit(bit, (unsigned long *)&control->intercepts);
}

static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit)
{
	WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
	__clear_bit(bit, (unsigned long *)&control->intercepts);
}

static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit)
{
	WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
	return test_bit(bit, (unsigned long *)&control->intercepts);
}

static inline void set_dr_intercepts(struct vcpu_svm *svm)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	if (!sev_es_guest(svm->vcpu.kvm)) {
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_READ);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_READ);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_READ);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_READ);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_READ);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_READ);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_READ);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_WRITE);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_WRITE);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_WRITE);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_WRITE);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_WRITE);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_WRITE);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE);
	}

	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ);
	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE);

	recalc_intercepts(svm);
}

static inline void clr_dr_intercepts(struct vcpu_svm *svm)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	vmcb->control.intercepts[INTERCEPT_DR] = 0;

	/* DR7 access must remain intercepted for an SEV-ES guest */
	if (sev_es_guest(svm->vcpu.kvm)) {
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE);
	}

	recalc_intercepts(svm);
}

static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	WARN_ON_ONCE(bit >= 32);
	vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);

	recalc_intercepts(svm);
}

static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	WARN_ON_ONCE(bit >= 32);
	vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);

	recalc_intercepts(svm);
}

static inline void svm_set_intercept(struct vcpu_svm *svm, int bit)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	vmcb_set_intercept(&vmcb->control, bit);

	recalc_intercepts(svm);
}

static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	vmcb_clr_intercept(&vmcb->control, bit);

	recalc_intercepts(svm);
}

static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit)
{
	return vmcb_is_intercept(&svm->vmcb->control, bit);
}

static inline bool vgif_enabled(struct vcpu_svm *svm)
{
	return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
}

static inline void enable_gif(struct vcpu_svm *svm)
{
	if (vgif_enabled(svm))
		svm->vmcb->control.int_ctl |= V_GIF_MASK;
	else
		svm->vcpu.arch.hflags |= HF_GIF_MASK;
}

static inline void disable_gif(struct vcpu_svm *svm)
{
	if (vgif_enabled(svm))
		svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
	else
		svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
}

static inline bool gif_set(struct vcpu_svm *svm)
{
	if (vgif_enabled(svm))
		return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
	else
		return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
}

/* svm.c */
#define MSR_CR3_LEGACY_RESERVED_MASK		0xfe7U
#define MSR_CR3_LEGACY_PAE_RESERVED_MASK	0x7U
#define MSR_CR3_LONG_MBZ_MASK			0xfff0000000000000U
#define MSR_INVALID				0xffffffffU

extern int sev;
extern int sev_es;
extern bool dump_invalid_vmcb;

u32 svm_msrpm_offset(u32 msr);
u32 *svm_vcpu_alloc_msrpm(void);
void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm);
void svm_vcpu_free_msrpm(u32 *msrpm);

int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer);
void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
void svm_flush_tlb(struct kvm_vcpu *vcpu);
void disable_nmi_singlestep(struct vcpu_svm *svm);
bool svm_smi_blocked(struct kvm_vcpu *vcpu);
bool svm_nmi_blocked(struct kvm_vcpu *vcpu);
bool svm_interrupt_blocked(struct kvm_vcpu *vcpu);
void svm_set_gif(struct vcpu_svm *svm, bool value);
int svm_invoke_exit_handler(struct vcpu_svm *svm, u64 exit_code);

/* nested.c */

#define NESTED_EXIT_HOST	0	/* Exit handled on host level */
#define NESTED_EXIT_DONE	1	/* Exit caused nested vmexit  */
#define NESTED_EXIT_CONTINUE	2	/* Further checks needed      */

static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu)
{
	struct vcpu_svm *svm = to_svm(vcpu);

	return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK);
}

static inline bool nested_exit_on_smi(struct vcpu_svm *svm)
{
	return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SMI);
}

static inline bool nested_exit_on_intr(struct vcpu_svm *svm)
{
	return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_INTR);
}

static inline bool nested_exit_on_nmi(struct vcpu_svm *svm)
{
	return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_NMI);
}

int enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
			 struct vmcb *nested_vmcb);
void svm_leave_nested(struct vcpu_svm *svm);
void svm_free_nested(struct vcpu_svm *svm);
int svm_allocate_nested(struct vcpu_svm *svm);
int nested_svm_vmrun(struct vcpu_svm *svm);
void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb);
int nested_svm_vmexit(struct vcpu_svm *svm);
int nested_svm_exit_handled(struct vcpu_svm *svm);
int nested_svm_check_permissions(struct vcpu_svm *svm);
int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
			       bool has_error_code, u32 error_code);
int nested_svm_exit_special(struct vcpu_svm *svm);
void sync_nested_vmcb_control(struct vcpu_svm *svm);

extern struct kvm_x86_nested_ops svm_nested_ops;

/* avic.c */

#define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK	(0xFF)
#define AVIC_LOGICAL_ID_ENTRY_VALID_BIT			31
#define AVIC_LOGICAL_ID_ENTRY_VALID_MASK		(1 << 31)

#define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK	(0xFFULL)
#define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK	(0xFFFFFFFFFFULL << 12)
#define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK		(1ULL << 62)
#define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK		(1ULL << 63)

#define VMCB_AVIC_APIC_BAR_MASK		0xFFFFFFFFFF000ULL

extern int avic;

static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
{
	svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
	vmcb_mark_dirty(svm->vmcb, VMCB_AVIC);
}

static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
{
	struct vcpu_svm *svm = to_svm(vcpu);
	u64 *entry = svm->avic_physical_id_cache;

	if (!entry)
		return false;

	return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
}

int avic_ga_log_notifier(u32 ga_tag);
void avic_vm_destroy(struct kvm *kvm);
int avic_vm_init(struct kvm *kvm);
void avic_init_vmcb(struct vcpu_svm *svm);
void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate);
int avic_incomplete_ipi_interception(struct vcpu_svm *svm);
int avic_unaccelerated_access_interception(struct vcpu_svm *svm);
int avic_init_vcpu(struct vcpu_svm *svm);
void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
void avic_vcpu_put(struct kvm_vcpu *vcpu);
void avic_post_state_restore(struct kvm_vcpu *vcpu);
void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu);
bool svm_check_apicv_inhibit_reasons(ulong bit);
void svm_pre_update_apicv_exec_ctrl(struct kvm *kvm, bool activate);
void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap);
void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr);
void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr);
int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec);
bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu);
int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
		       uint32_t guest_irq, bool set);
void svm_vcpu_blocking(struct kvm_vcpu *vcpu);
void svm_vcpu_unblocking(struct kvm_vcpu *vcpu);

/* sev.c */

#define GHCB_VERSION_MAX		1ULL
#define GHCB_VERSION_MIN		1ULL

#define GHCB_MSR_INFO_POS		0
#define GHCB_MSR_INFO_MASK		(BIT_ULL(12) - 1)

#define GHCB_MSR_SEV_INFO_RESP		0x001
#define GHCB_MSR_SEV_INFO_REQ		0x002
#define GHCB_MSR_VER_MAX_POS		48
#define GHCB_MSR_VER_MAX_MASK		0xffff
#define GHCB_MSR_VER_MIN_POS		32
#define GHCB_MSR_VER_MIN_MASK		0xffff
#define GHCB_MSR_CBIT_POS		24
#define GHCB_MSR_CBIT_MASK		0xff
#define GHCB_MSR_SEV_INFO(_max, _min, _cbit)				\
	((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) |	\
	 (((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) |	\
	 (((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) |	\
	 GHCB_MSR_SEV_INFO_RESP)

#define GHCB_MSR_CPUID_REQ		0x004
#define GHCB_MSR_CPUID_RESP		0x005
#define GHCB_MSR_CPUID_FUNC_POS		32
#define GHCB_MSR_CPUID_FUNC_MASK	0xffffffff
#define GHCB_MSR_CPUID_VALUE_POS	32
#define GHCB_MSR_CPUID_VALUE_MASK	0xffffffff
#define GHCB_MSR_CPUID_REG_POS		30
#define GHCB_MSR_CPUID_REG_MASK		0x3

#define GHCB_MSR_TERM_REQ		0x100
#define GHCB_MSR_TERM_REASON_SET_POS	12
#define GHCB_MSR_TERM_REASON_SET_MASK	0xf
#define GHCB_MSR_TERM_REASON_POS	16
#define GHCB_MSR_TERM_REASON_MASK	0xff

extern unsigned int max_sev_asid;

static inline bool svm_sev_enabled(void)
{
	return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
}

void sev_vm_destroy(struct kvm *kvm);
int svm_mem_enc_op(struct kvm *kvm, void __user *argp);
int svm_register_enc_region(struct kvm *kvm,
			    struct kvm_enc_region *range);
int svm_unregister_enc_region(struct kvm *kvm,
			      struct kvm_enc_region *range);
void pre_sev_run(struct vcpu_svm *svm, int cpu);
void __init sev_hardware_setup(void);
void sev_hardware_teardown(void);
void sev_free_vcpu(struct kvm_vcpu *vcpu);
int sev_handle_vmgexit(struct vcpu_svm *svm);

#endif
Commit	Line	Data
883b0a91 JR	1	// SPDX-License-Identifier: GPL-2.0-only
	2	/*
	3	* Kernel-based Virtual Machine driver for Linux
	4	*
	5	* AMD SVM support
	6	*
	7	* Copyright (C) 2006 Qumranet, Inc.
	8	* Copyright 2010 Red Hat, Inc. and/or its affiliates.
	9	*
	10	* Authors:
	11	* Yaniv Kamay <yaniv@qumranet.com>
	12	* Avi Kivity <avi@qumranet.com>
	13	*/
	14
	15	#ifndef __SVM_SVM_H
	16	#define __SVM_SVM_H
	17
	18	#include <linux/kvm_types.h>
	19	#include <linux/kvm_host.h>
291bd20d	20	#include <linux/bits.h>
883b0a91 JR	21
	22	#include <asm/svm.h>
	23
	24	static const u32 host_save_user_msrs[] = {
	25	#ifdef CONFIG_X86_64
	26	MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
	27	MSR_FS_BASE,
	28	#endif
	29	MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
	30	MSR_TSC_AUX,
	31	};
	32
	33	#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
	34
fd6fa73d	35	#define MAX_DIRECT_ACCESS_MSRS 15
883b0a91 JR	36	#define MSRPM_OFFSETS 16
	37	extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
	38	extern bool npt_enabled;
	39
	40	enum {
	41	VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
	42	pause filter count */
	43	VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
	44	VMCB_ASID, /* ASID */
	45	VMCB_INTR, /* int_ctl, int_vector */
	46	VMCB_NPT, /* npt_en, nCR3, gPAT */
	47	VMCB_CR, /* CR0, CR3, CR4, EFER */
	48	VMCB_DR, /* DR6, DR7 */
	49	VMCB_DT, /* GDT, IDT */
	50	VMCB_SEG, /* CS, DS, SS, ES, CPL */
	51	VMCB_CR2, /* CR2 only */
	52	VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
	53	VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
	54	* AVIC PHYSICAL_TABLE pointer,
	55	* AVIC LOGICAL_TABLE pointer
	56	*/
	57	VMCB_DIRTY_MAX,
	58	};
	59
	60	/* TPR and CR2 are always written before VMRUN */
	61	#define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) \| (1U << VMCB_CR2))
	62
	63	struct kvm_sev_info {
	64	bool active; /* SEV enabled guest */
916391a2	65	bool es_active; /* SEV-ES enabled guest */
883b0a91 JR	66	unsigned int asid; /* ASID used for this guest */
	67	unsigned int handle; /* SEV firmware handle */
	68	int fd; /* SEV device fd */
	69	unsigned long pages_locked; /* Number of pages locked */
	70	struct list_head regions_list; /* List of registered regions */
	71	};
	72
	73	struct kvm_svm {
	74	struct kvm kvm;
	75
	76	/* Struct members for AVIC */
	77	u32 avic_vm_id;
	78	struct page *avic_logical_id_table_page;
	79	struct page *avic_physical_id_table_page;
	80	struct hlist_node hnode;
	81
	82	struct kvm_sev_info sev_info;
	83	};
	84
	85	struct kvm_vcpu;
	86
7693b3eb	87	struct svm_nested_state {
883b0a91 JR	88	struct vmcb *hsave;
	89	u64 hsave_msr;
	90	u64 vm_cr_msr;
0dd16b5b	91	u64 vmcb12_gpa;
883b0a91 JR	92
	93	/* These are the merged vectors */
	94	u32 *msrpm;
	95
f74f9414 PB	96	/* A VMRUN has started but has not yet been performed, so
	97	* we cannot inject a nested vmexit yet. */
	98	bool nested_run_pending;
	99
e670bf68 PB	100	/* cache for control fields of the guest */
e670bf68 PB	101	struct vmcb_control_area ctl;
2fcf4876 ML	102
2fcf4876 ML	103	bool initialized;
883b0a91 JR	104	};
	105
	106	struct vcpu_svm {
	107	struct kvm_vcpu vcpu;
	108	struct vmcb *vmcb;
	109	unsigned long vmcb_pa;
	110	struct svm_cpu_data *svm_data;
7e8e6eed	111	u32 asid;
883b0a91 JR	112	uint64_t asid_generation;
	113	uint64_t sysenter_esp;
	114	uint64_t sysenter_eip;
	115	uint64_t tsc_aux;
	116
	117	u64 msr_decfg;
	118
	119	u64 next_rip;
	120
	121	u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
	122	struct {
	123	u16 fs;
	124	u16 gs;
	125	u16 ldt;
	126	u64 gs_base;
	127	} host;
	128
	129	u64 spec_ctrl;
	130	/*
	131	* Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
	132	* translated into the appropriate L2_CFG bits on the host to
	133	* perform speculative control.
	134	*/
	135	u64 virt_spec_ctrl;
	136
	137	u32 *msrpm;
	138
	139	ulong nmi_iret_rip;
	140
7693b3eb	141	struct svm_nested_state nested;
883b0a91 JR	142
	143	bool nmi_singlestep;
	144	u64 nmi_singlestep_guest_rflags;
	145
	146	unsigned int3_injected;
	147	unsigned long int3_rip;
	148
	149	/* cached guest cpuid flags for faster access */
	150	bool nrips_enabled : 1;
	151
	152	u32 ldr_reg;
	153	u32 dfr_reg;
	154	struct page *avic_backing_page;
	155	u64 *avic_physical_id_cache;
	156	bool avic_is_running;
	157
	158	/*
	159	* Per-vcpu list of struct amd_svm_iommu_ir:
	160	* This is used mainly to store interrupt remapping information used
	161	* when update the vcpu affinity. This avoids the need to scan for
	162	* IRTE and try to match ga_tag in the IOMMU driver.
	163	*/
	164	struct list_head ir_list;
	165	spinlock_t ir_list_lock;
fd6fa73d AG	166
	167	/* Save desired MSR intercept (read: pass-through) state */
	168	struct {
	169	DECLARE_BITMAP(read, MAX_DIRECT_ACCESS_MSRS);
	170	DECLARE_BITMAP(write, MAX_DIRECT_ACCESS_MSRS);
	171	} shadow_msr_intercept;
add5e2f0 TL	172
	173	/* SEV-ES support */
	174	struct vmcb_save_area *vmsa;
	175	struct ghcb *ghcb;
291bd20d	176	struct kvm_host_map ghcb_map;
8f423a80 TL	177
	178	/* SEV-ES scratch area support */
	179	void *ghcb_sa;
	180	u64 ghcb_sa_len;
	181	bool ghcb_sa_sync;
	182	bool ghcb_sa_free;
883b0a91 JR	183	};
883b0a91 JR	184
eaf78265 JR	185	struct svm_cpu_data {
	186	int cpu;
	187
	188	u64 asid_generation;
	189	u32 max_asid;
	190	u32 next_asid;
	191	u32 min_asid;
	192	struct kvm_ldttss_desc *tss_desc;
	193
	194	struct page *save_area;
	195	struct vmcb *current_vmcb;
	196
	197	/* index = sev_asid, value = vmcb pointer */
	198	struct vmcb **sev_vmcbs;
	199	};
	200
	201	DECLARE_PER_CPU(struct svm_cpu_data *, svm_data);
	202
883b0a91 JR	203	void recalc_intercepts(struct vcpu_svm *svm);
883b0a91 JR	204
ef0f6496 JR	205	static inline struct kvm_svm to_kvm_svm(struct kvm kvm)
	206	{
	207	return container_of(kvm, struct kvm_svm, kvm);
	208	}
	209
916391a2 TL	210	static inline bool sev_guest(struct kvm *kvm)
	211	{
	212	#ifdef CONFIG_KVM_AMD_SEV
	213	struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
	214
	215	return sev->active;
	216	#else
	217	return false;
	218	#endif
	219	}
	220
	221	static inline bool sev_es_guest(struct kvm *kvm)
	222	{
	223	#ifdef CONFIG_KVM_AMD_SEV
	224	struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
	225
	226	return sev_guest(kvm) && sev->es_active;
	227	#else
	228	return false;
	229	#endif
	230	}
	231
06e7852c	232	static inline void vmcb_mark_all_dirty(struct vmcb *vmcb)
883b0a91 JR	233	{
	234	vmcb->control.clean = 0;
	235	}
	236
06e7852c	237	static inline void vmcb_mark_all_clean(struct vmcb *vmcb)
883b0a91 JR	238	{
	239	vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
	240	& ~VMCB_ALWAYS_DIRTY_MASK;
	241	}
	242
06e7852c	243	static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit)
883b0a91 JR	244	{
	245	vmcb->control.clean &= ~(1 << bit);
	246	}
	247
	248	static inline struct vcpu_svm to_svm(struct kvm_vcpu vcpu)
	249	{
	250	return container_of(vcpu, struct vcpu_svm, vcpu);
	251	}
	252
	253	static inline struct vmcb get_host_vmcb(struct vcpu_svm svm)
	254	{
	255	if (is_guest_mode(&svm->vcpu))
	256	return svm->nested.hsave;
	257	else
	258	return svm->vmcb;
	259	}
	260
c45ad722 BM	261	static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit)
	262	{
	263	WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
	264	__set_bit(bit, (unsigned long *)&control->intercepts);
	265	}
	266
	267	static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit)
	268	{
	269	WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
	270	__clear_bit(bit, (unsigned long *)&control->intercepts);
	271	}
	272
	273	static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit)
	274	{
	275	WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
	276	return test_bit(bit, (unsigned long *)&control->intercepts);
	277	}
	278
883b0a91 JR	279	static inline void set_dr_intercepts(struct vcpu_svm *svm)
	280	{
	281	struct vmcb *vmcb = get_host_vmcb(svm);
	282
8d4846b9 TL	283	if (!sev_es_guest(svm->vcpu.kvm)) {
	284	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_READ);
	285	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_READ);
	286	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_READ);
	287	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_READ);
	288	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_READ);
	289	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_READ);
	290	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_READ);
	291	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_WRITE);
	292	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_WRITE);
	293	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_WRITE);
	294	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_WRITE);
	295	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_WRITE);
	296	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_WRITE);
	297	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE);
	298	}
	299
30abaa88	300	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ);
30abaa88	301	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE);
883b0a91 JR	302
	303	recalc_intercepts(svm);
	304	}
	305
	306	static inline void clr_dr_intercepts(struct vcpu_svm *svm)
	307	{
	308	struct vmcb *vmcb = get_host_vmcb(svm);
	309
30abaa88	310	vmcb->control.intercepts[INTERCEPT_DR] = 0;
883b0a91	311
8d4846b9 TL	312	/* DR7 access must remain intercepted for an SEV-ES guest */
	313	if (sev_es_guest(svm->vcpu.kvm)) {
	314	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ);
	315	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE);
	316	}
	317
883b0a91 JR	318	recalc_intercepts(svm);
	319	}
	320
9780d51d	321	static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit)
883b0a91 JR	322	{
	323	struct vmcb *vmcb = get_host_vmcb(svm);
	324
9780d51d BM	325	WARN_ON_ONCE(bit >= 32);
9780d51d BM	326	vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);
883b0a91 JR	327
	328	recalc_intercepts(svm);
	329	}
	330
9780d51d	331	static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit)
883b0a91 JR	332	{
	333	struct vmcb *vmcb = get_host_vmcb(svm);
	334
9780d51d BM	335	WARN_ON_ONCE(bit >= 32);
9780d51d BM	336	vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);
883b0a91 JR	337
	338	recalc_intercepts(svm);
	339	}
	340
a284ba56	341	static inline void svm_set_intercept(struct vcpu_svm *svm, int bit)
883b0a91 JR	342	{
	343	struct vmcb *vmcb = get_host_vmcb(svm);
	344
c62e2e94	345	vmcb_set_intercept(&vmcb->control, bit);
883b0a91 JR	346
	347	recalc_intercepts(svm);
	348	}
	349
a284ba56	350	static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit)
883b0a91 JR	351	{
	352	struct vmcb *vmcb = get_host_vmcb(svm);
	353
c62e2e94	354	vmcb_clr_intercept(&vmcb->control, bit);
883b0a91 JR	355
	356	recalc_intercepts(svm);
	357	}
	358
a284ba56	359	static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit)
883b0a91	360	{
c62e2e94	361	return vmcb_is_intercept(&svm->vmcb->control, bit);
883b0a91 JR	362	}
	363
	364	static inline bool vgif_enabled(struct vcpu_svm *svm)
	365	{
	366	return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
	367	}
	368
	369	static inline void enable_gif(struct vcpu_svm *svm)
	370	{
	371	if (vgif_enabled(svm))
	372	svm->vmcb->control.int_ctl \|= V_GIF_MASK;
	373	else
	374	svm->vcpu.arch.hflags \|= HF_GIF_MASK;
	375	}
	376
	377	static inline void disable_gif(struct vcpu_svm *svm)
	378	{
	379	if (vgif_enabled(svm))
	380	svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
	381	else
	382	svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
	383	}
	384
	385	static inline bool gif_set(struct vcpu_svm *svm)
	386	{
	387	if (vgif_enabled(svm))
	388	return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
	389	else
	390	return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
	391	}
	392
	393	/* svm.c */
761e4169 KS	394	#define MSR_CR3_LEGACY_RESERVED_MASK 0xfe7U
761e4169 KS	395	#define MSR_CR3_LEGACY_PAE_RESERVED_MASK 0x7U
fb0f33fd	396	#define MSR_CR3_LONG_MBZ_MASK 0xfff0000000000000U
761e4169	397	#define MSR_INVALID 0xffffffffU
883b0a91	398
916391a2 TL	399	extern int sev;
916391a2 TL	400	extern int sev_es;
291bd20d	401	extern bool dump_invalid_vmcb;
916391a2	402
883b0a91	403	u32 svm_msrpm_offset(u32 msr);
2fcf4876 ML	404	u32 *svm_vcpu_alloc_msrpm(void);
	405	void svm_vcpu_init_msrpm(struct kvm_vcpu vcpu, u32 msrpm);
	406	void svm_vcpu_free_msrpm(u32 *msrpm);
	407
72f211ec	408	int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer);
883b0a91	409	void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
c2fe3cd4	410	void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
f55ac304	411	void svm_flush_tlb(struct kvm_vcpu *vcpu);
883b0a91	412	void disable_nmi_singlestep(struct vcpu_svm *svm);
cae96af1 PB	413	bool svm_smi_blocked(struct kvm_vcpu *vcpu);
	414	bool svm_nmi_blocked(struct kvm_vcpu *vcpu);
	415	bool svm_interrupt_blocked(struct kvm_vcpu *vcpu);
ffdf7f9e	416	void svm_set_gif(struct vcpu_svm *svm, bool value);
291bd20d	417	int svm_invoke_exit_handler(struct vcpu_svm *svm, u64 exit_code);
883b0a91 JR	418
	419	/* nested.c */
	420
	421	#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
	422	#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
	423	#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
	424
01c3b2b5	425	static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu)
883b0a91	426	{
e9fd761a PB	427	struct vcpu_svm *svm = to_svm(vcpu);
	428
	429	return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK);
883b0a91 JR	430	}
883b0a91 JR	431
55714cdd PB	432	static inline bool nested_exit_on_smi(struct vcpu_svm *svm)
55714cdd PB	433	{
c62e2e94	434	return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SMI);
55714cdd PB	435	}
55714cdd PB	436
fc6f7c03 PB	437	static inline bool nested_exit_on_intr(struct vcpu_svm *svm)
fc6f7c03 PB	438	{
c62e2e94	439	return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_INTR);
fc6f7c03 PB	440	}
fc6f7c03 PB	441
bbdad0b5 PB	442	static inline bool nested_exit_on_nmi(struct vcpu_svm *svm)
bbdad0b5 PB	443	{
c62e2e94	444	return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_NMI);
bbdad0b5 PB	445	}
bbdad0b5 PB	446
59cd9bc5 VK	447	int enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
59cd9bc5 VK	448	struct vmcb *nested_vmcb);
c513f484	449	void svm_leave_nested(struct vcpu_svm *svm);
2fcf4876 ML	450	void svm_free_nested(struct vcpu_svm *svm);
2fcf4876 ML	451	int svm_allocate_nested(struct vcpu_svm *svm);
883b0a91 JR	452	int nested_svm_vmrun(struct vcpu_svm *svm);
	453	void nested_svm_vmloadsave(struct vmcb from_vmcb, struct vmcb to_vmcb);
	454	int nested_svm_vmexit(struct vcpu_svm *svm);
	455	int nested_svm_exit_handled(struct vcpu_svm *svm);
	456	int nested_svm_check_permissions(struct vcpu_svm *svm);
	457	int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
	458	bool has_error_code, u32 error_code);
883b0a91	459	int nested_svm_exit_special(struct vcpu_svm *svm);
2d8a42be	460	void sync_nested_vmcb_control(struct vcpu_svm *svm);
883b0a91	461
33b22172 PB	462	extern struct kvm_x86_nested_ops svm_nested_ops;
33b22172 PB	463
ef0f6496 JR	464	/* avic.c */
	465
	466	#define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
	467	#define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31
	468	#define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
	469
	470	#define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
	471	#define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
	472	#define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
	473	#define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
	474
	475	#define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
	476
	477	extern int avic;
	478
	479	static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
	480	{
	481	svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
06e7852c	482	vmcb_mark_dirty(svm->vmcb, VMCB_AVIC);
ef0f6496 JR	483	}
	484
	485	static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
	486	{
	487	struct vcpu_svm *svm = to_svm(vcpu);
	488	u64 *entry = svm->avic_physical_id_cache;
	489
	490	if (!entry)
	491	return false;
	492
	493	return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
	494	}
	495
	496	int avic_ga_log_notifier(u32 ga_tag);
	497	void avic_vm_destroy(struct kvm *kvm);
	498	int avic_vm_init(struct kvm *kvm);
	499	void avic_init_vmcb(struct vcpu_svm *svm);
	500	void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate);
	501	int avic_incomplete_ipi_interception(struct vcpu_svm *svm);
	502	int avic_unaccelerated_access_interception(struct vcpu_svm *svm);
	503	int avic_init_vcpu(struct vcpu_svm *svm);
	504	void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
	505	void avic_vcpu_put(struct kvm_vcpu *vcpu);
	506	void avic_post_state_restore(struct kvm_vcpu *vcpu);
	507	void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
	508	void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu);
	509	bool svm_check_apicv_inhibit_reasons(ulong bit);
	510	void svm_pre_update_apicv_exec_ctrl(struct kvm *kvm, bool activate);
	511	void svm_load_eoi_exitmap(struct kvm_vcpu vcpu, u64 eoi_exit_bitmap);
	512	void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr);
	513	void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr);
	514	int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec);
	515	bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu);
	516	int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
	517	uint32_t guest_irq, bool set);
	518	void svm_vcpu_blocking(struct kvm_vcpu *vcpu);
	519	void svm_vcpu_unblocking(struct kvm_vcpu *vcpu);
	520
eaf78265 JR	521	/* sev.c */
eaf78265 JR	522
1edc1459 TL	523	#define GHCB_VERSION_MAX 1ULL
	524	#define GHCB_VERSION_MIN 1ULL
	525
291bd20d TL	526	#define GHCB_MSR_INFO_POS 0
	527	#define GHCB_MSR_INFO_MASK (BIT_ULL(12) - 1)
	528
1edc1459 TL	529	#define GHCB_MSR_SEV_INFO_RESP 0x001
	530	#define GHCB_MSR_SEV_INFO_REQ 0x002
	531	#define GHCB_MSR_VER_MAX_POS 48
	532	#define GHCB_MSR_VER_MAX_MASK 0xffff
	533	#define GHCB_MSR_VER_MIN_POS 32
	534	#define GHCB_MSR_VER_MIN_MASK 0xffff
	535	#define GHCB_MSR_CBIT_POS 24
	536	#define GHCB_MSR_CBIT_MASK 0xff
	537	#define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \
	538	((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) \| \
	539	(((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) \| \
	540	(((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) \| \
	541	GHCB_MSR_SEV_INFO_RESP)
	542
d3694667 TL	543	#define GHCB_MSR_CPUID_REQ 0x004
	544	#define GHCB_MSR_CPUID_RESP 0x005
	545	#define GHCB_MSR_CPUID_FUNC_POS 32
	546	#define GHCB_MSR_CPUID_FUNC_MASK 0xffffffff
	547	#define GHCB_MSR_CPUID_VALUE_POS 32
	548	#define GHCB_MSR_CPUID_VALUE_MASK 0xffffffff
	549	#define GHCB_MSR_CPUID_REG_POS 30
	550	#define GHCB_MSR_CPUID_REG_MASK 0x3
	551
e1d71116 TL	552	#define GHCB_MSR_TERM_REQ 0x100
	553	#define GHCB_MSR_TERM_REASON_SET_POS 12
	554	#define GHCB_MSR_TERM_REASON_SET_MASK 0xf
	555	#define GHCB_MSR_TERM_REASON_POS 16
	556	#define GHCB_MSR_TERM_REASON_MASK 0xff
	557
eaf78265 JR	558	extern unsigned int max_sev_asid;
eaf78265 JR	559
eaf78265 JR	560	static inline bool svm_sev_enabled(void)
	561	{
	562	return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
	563	}
	564
	565	void sev_vm_destroy(struct kvm *kvm);
	566	int svm_mem_enc_op(struct kvm kvm, void __user argp);
	567	int svm_register_enc_region(struct kvm *kvm,
	568	struct kvm_enc_region *range);
	569	int svm_unregister_enc_region(struct kvm *kvm,
	570	struct kvm_enc_region *range);
	571	void pre_sev_run(struct vcpu_svm *svm, int cpu);
916391a2	572	void __init sev_hardware_setup(void);
eaf78265	573	void sev_hardware_teardown(void);
add5e2f0	574	void sev_free_vcpu(struct kvm_vcpu *vcpu);
291bd20d	575	int sev_handle_vmgexit(struct vcpu_svm *svm);
eaf78265	576
883b0a91	577	#endif