[linux-block.git] / arch / x86 / kvm / svm / svm.h

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Kernel-based Virtual Machine driver for Linux
 *
 * AMD SVM support
 *
 * Copyright (C) 2006 Qumranet, Inc.
 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
 *
 * Authors:
 *   Yaniv Kamay  <yaniv@qumranet.com>
 *   Avi Kivity   <avi@qumranet.com>
 */

#ifndef __SVM_SVM_H
#define __SVM_SVM_H

#include <linux/kvm_types.h>
#include <linux/kvm_host.h>
#include <linux/bits.h>

#include <asm/svm.h>

#define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)

static const u32 host_save_user_msrs[] = {
	MSR_TSC_AUX,
};
#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)

#define MAX_DIRECT_ACCESS_MSRS	18
#define MSRPM_OFFSETS	16
extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
extern bool npt_enabled;

enum {
	VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
			    pause filter count */
	VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
	VMCB_ASID,	 /* ASID */
	VMCB_INTR,	 /* int_ctl, int_vector */
	VMCB_NPT,        /* npt_en, nCR3, gPAT */
	VMCB_CR,	 /* CR0, CR3, CR4, EFER */
	VMCB_DR,         /* DR6, DR7 */
	VMCB_DT,         /* GDT, IDT */
	VMCB_SEG,        /* CS, DS, SS, ES, CPL */
	VMCB_CR2,        /* CR2 only */
	VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
	VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
			  * AVIC PHYSICAL_TABLE pointer,
			  * AVIC LOGICAL_TABLE pointer
			  */
	VMCB_DIRTY_MAX,
};

/* TPR and CR2 are always written before VMRUN */
#define VMCB_ALWAYS_DIRTY_MASK	((1U << VMCB_INTR) | (1U << VMCB_CR2))

struct kvm_sev_info {
	bool active;		/* SEV enabled guest */
	bool es_active;		/* SEV-ES enabled guest */
	unsigned int asid;	/* ASID used for this guest */
	unsigned int handle;	/* SEV firmware handle */
	int fd;			/* SEV device fd */
	unsigned long pages_locked; /* Number of pages locked */
	struct list_head regions_list;  /* List of registered regions */
	u64 ap_jump_table;	/* SEV-ES AP Jump Table address */
};

struct kvm_svm {
	struct kvm kvm;

	/* Struct members for AVIC */
	u32 avic_vm_id;
	struct page *avic_logical_id_table_page;
	struct page *avic_physical_id_table_page;
	struct hlist_node hnode;

	struct kvm_sev_info sev_info;
};

struct kvm_vcpu;

struct kvm_vmcb_info {
	struct vmcb *ptr;
	unsigned long pa;
	int cpu;
	uint64_t asid_generation;
};

struct svm_nested_state {
	struct kvm_vmcb_info vmcb02;
	u64 hsave_msr;
	u64 vm_cr_msr;
	u64 vmcb12_gpa;

	/* These are the merged vectors */
	u32 *msrpm;

	/* A VMRUN has started but has not yet been performed, so
	 * we cannot inject a nested vmexit yet.  */
	bool nested_run_pending;

	/* cache for control fields of the guest */
	struct vmcb_control_area ctl;

	bool initialized;
};

struct vcpu_svm {
	struct kvm_vcpu vcpu;
	struct vmcb *vmcb;
	unsigned long vmcb_pa;
	struct kvm_vmcb_info vmcb01;
	struct kvm_vmcb_info *current_vmcb;
	struct svm_cpu_data *svm_data;
	u32 asid;
	uint64_t sysenter_esp;
	uint64_t sysenter_eip;
	uint64_t tsc_aux;

	u64 msr_decfg;

	u64 next_rip;

	u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];

	u64 spec_ctrl;
	/*
	 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
	 * translated into the appropriate L2_CFG bits on the host to
	 * perform speculative control.
	 */
	u64 virt_spec_ctrl;

	u32 *msrpm;

	ulong nmi_iret_rip;

	struct svm_nested_state nested;

	bool nmi_singlestep;
	u64 nmi_singlestep_guest_rflags;

	unsigned int3_injected;
	unsigned long int3_rip;

	/* cached guest cpuid flags for faster access */
	bool nrips_enabled	: 1;

	u32 ldr_reg;
	u32 dfr_reg;
	struct page *avic_backing_page;
	u64 *avic_physical_id_cache;
	bool avic_is_running;

	/*
	 * Per-vcpu list of struct amd_svm_iommu_ir:
	 * This is used mainly to store interrupt remapping information used
	 * when update the vcpu affinity. This avoids the need to scan for
	 * IRTE and try to match ga_tag in the IOMMU driver.
	 */
	struct list_head ir_list;
	spinlock_t ir_list_lock;

	/* Save desired MSR intercept (read: pass-through) state */
	struct {
		DECLARE_BITMAP(read, MAX_DIRECT_ACCESS_MSRS);
		DECLARE_BITMAP(write, MAX_DIRECT_ACCESS_MSRS);
	} shadow_msr_intercept;

	/* SEV-ES support */
	struct vmcb_save_area *vmsa;
	struct ghcb *ghcb;
	struct kvm_host_map ghcb_map;
	bool received_first_sipi;

	/* SEV-ES scratch area support */
	void *ghcb_sa;
	u64 ghcb_sa_len;
	bool ghcb_sa_sync;
	bool ghcb_sa_free;

	bool guest_state_loaded;
};

struct svm_cpu_data {
	int cpu;

	u64 asid_generation;
	u32 max_asid;
	u32 next_asid;
	u32 min_asid;
	struct kvm_ldttss_desc *tss_desc;

	struct page *save_area;
	struct vmcb *current_vmcb;

	/* index = sev_asid, value = vmcb pointer */
	struct vmcb **sev_vmcbs;
};

DECLARE_PER_CPU(struct svm_cpu_data *, svm_data);

void recalc_intercepts(struct vcpu_svm *svm);

static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
{
	return container_of(kvm, struct kvm_svm, kvm);
}

static inline bool sev_guest(struct kvm *kvm)
{
#ifdef CONFIG_KVM_AMD_SEV
	struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;

	return sev->active;
#else
	return false;
#endif
}

static inline bool sev_es_guest(struct kvm *kvm)
{
#ifdef CONFIG_KVM_AMD_SEV
	struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;

	return sev_guest(kvm) && sev->es_active;
#else
	return false;
#endif
}

static inline void vmcb_mark_all_dirty(struct vmcb *vmcb)
{
	vmcb->control.clean = 0;
}

static inline void vmcb_mark_all_clean(struct vmcb *vmcb)
{
	vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
			       & ~VMCB_ALWAYS_DIRTY_MASK;
}

static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit)
{
	vmcb->control.clean &= ~(1 << bit);
}

static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
{
	return container_of(vcpu, struct vcpu_svm, vcpu);
}

static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit)
{
	WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
	__set_bit(bit, (unsigned long *)&control->intercepts);
}

static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit)
{
	WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
	__clear_bit(bit, (unsigned long *)&control->intercepts);
}

static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit)
{
	WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
	return test_bit(bit, (unsigned long *)&control->intercepts);
}

static inline void set_dr_intercepts(struct vcpu_svm *svm)
{
	struct vmcb *vmcb = svm->vmcb01.ptr;

	if (!sev_es_guest(svm->vcpu.kvm)) {
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_READ);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_READ);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_READ);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_READ);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_READ);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_READ);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_READ);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_WRITE);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_WRITE);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_WRITE);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_WRITE);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_WRITE);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_WRITE);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE);
	}

	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ);
	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE);

	recalc_intercepts(svm);
}

static inline void clr_dr_intercepts(struct vcpu_svm *svm)
{
	struct vmcb *vmcb = svm->vmcb01.ptr;

	vmcb->control.intercepts[INTERCEPT_DR] = 0;

	/* DR7 access must remain intercepted for an SEV-ES guest */
	if (sev_es_guest(svm->vcpu.kvm)) {
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ);
		vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE);
	}

	recalc_intercepts(svm);
}

static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit)
{
	struct vmcb *vmcb = svm->vmcb01.ptr;

	WARN_ON_ONCE(bit >= 32);
	vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);

	recalc_intercepts(svm);
}

static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit)
{
	struct vmcb *vmcb = svm->vmcb01.ptr;

	WARN_ON_ONCE(bit >= 32);
	vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);

	recalc_intercepts(svm);
}

static inline void svm_set_intercept(struct vcpu_svm *svm, int bit)
{
	struct vmcb *vmcb = svm->vmcb01.ptr;

	vmcb_set_intercept(&vmcb->control, bit);

	recalc_intercepts(svm);
}

static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit)
{
	struct vmcb *vmcb = svm->vmcb01.ptr;

	vmcb_clr_intercept(&vmcb->control, bit);

	recalc_intercepts(svm);
}

static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit)
{
	return vmcb_is_intercept(&svm->vmcb->control, bit);
}

static inline bool vgif_enabled(struct vcpu_svm *svm)
{
	return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
}

static inline void enable_gif(struct vcpu_svm *svm)
{
	if (vgif_enabled(svm))
		svm->vmcb->control.int_ctl |= V_GIF_MASK;
	else
		svm->vcpu.arch.hflags |= HF_GIF_MASK;
}

static inline void disable_gif(struct vcpu_svm *svm)
{
	if (vgif_enabled(svm))
		svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
	else
		svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
}

static inline bool gif_set(struct vcpu_svm *svm)
{
	if (vgif_enabled(svm))
		return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
	else
		return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
}

/* svm.c */
#define MSR_INVALID				0xffffffffU

extern int sev;
extern int sev_es;
extern bool dump_invalid_vmcb;

u32 svm_msrpm_offset(u32 msr);
u32 *svm_vcpu_alloc_msrpm(void);
void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm);
void svm_vcpu_free_msrpm(u32 *msrpm);

int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer);
void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
void svm_flush_tlb(struct kvm_vcpu *vcpu);
void disable_nmi_singlestep(struct vcpu_svm *svm);
bool svm_smi_blocked(struct kvm_vcpu *vcpu);
bool svm_nmi_blocked(struct kvm_vcpu *vcpu);
bool svm_interrupt_blocked(struct kvm_vcpu *vcpu);
void svm_set_gif(struct vcpu_svm *svm, bool value);
int svm_invoke_exit_handler(struct vcpu_svm *svm, u64 exit_code);
void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
			  int read, int write);

/* nested.c */

#define NESTED_EXIT_HOST	0	/* Exit handled on host level */
#define NESTED_EXIT_DONE	1	/* Exit caused nested vmexit  */
#define NESTED_EXIT_CONTINUE	2	/* Further checks needed      */

static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu)
{
	struct vcpu_svm *svm = to_svm(vcpu);

	return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK);
}

static inline bool nested_exit_on_smi(struct vcpu_svm *svm)
{
	return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SMI);
}

static inline bool nested_exit_on_intr(struct vcpu_svm *svm)
{
	return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_INTR);
}

static inline bool nested_exit_on_nmi(struct vcpu_svm *svm)
{
	return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_NMI);
}

int enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa, struct vmcb *vmcb12);
void svm_leave_nested(struct vcpu_svm *svm);
void svm_free_nested(struct vcpu_svm *svm);
int svm_allocate_nested(struct vcpu_svm *svm);
int nested_svm_vmrun(struct vcpu_svm *svm);
void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb);
int nested_svm_vmexit(struct vcpu_svm *svm);
int nested_svm_exit_handled(struct vcpu_svm *svm);
int nested_svm_check_permissions(struct vcpu_svm *svm);
int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
			       bool has_error_code, u32 error_code);
int nested_svm_exit_special(struct vcpu_svm *svm);
void nested_sync_control_from_vmcb02(struct vcpu_svm *svm);
void nested_vmcb02_compute_g_pat(struct vcpu_svm *svm);
void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb);

extern struct kvm_x86_nested_ops svm_nested_ops;

/* avic.c */

#define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK	(0xFF)
#define AVIC_LOGICAL_ID_ENTRY_VALID_BIT			31
#define AVIC_LOGICAL_ID_ENTRY_VALID_MASK		(1 << 31)

#define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK	(0xFFULL)
#define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK	(0xFFFFFFFFFFULL << 12)
#define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK		(1ULL << 62)
#define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK		(1ULL << 63)

#define VMCB_AVIC_APIC_BAR_MASK		0xFFFFFFFFFF000ULL

extern int avic;

static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
{
	svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
	vmcb_mark_dirty(svm->vmcb, VMCB_AVIC);
}

static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
{
	struct vcpu_svm *svm = to_svm(vcpu);
	u64 *entry = svm->avic_physical_id_cache;

	if (!entry)
		return false;

	return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
}

int avic_ga_log_notifier(u32 ga_tag);
void avic_vm_destroy(struct kvm *kvm);
int avic_vm_init(struct kvm *kvm);
void avic_init_vmcb(struct vcpu_svm *svm);
void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate);
int avic_incomplete_ipi_interception(struct vcpu_svm *svm);
int avic_unaccelerated_access_interception(struct vcpu_svm *svm);
int avic_init_vcpu(struct vcpu_svm *svm);
void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
void avic_vcpu_put(struct kvm_vcpu *vcpu);
void avic_post_state_restore(struct kvm_vcpu *vcpu);
void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu);
bool svm_check_apicv_inhibit_reasons(ulong bit);
void svm_pre_update_apicv_exec_ctrl(struct kvm *kvm, bool activate);
void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap);
void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr);
void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr);
int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec);
bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu);
int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
		       uint32_t guest_irq, bool set);
void svm_vcpu_blocking(struct kvm_vcpu *vcpu);
void svm_vcpu_unblocking(struct kvm_vcpu *vcpu);

/* sev.c */

#define GHCB_VERSION_MAX		1ULL
#define GHCB_VERSION_MIN		1ULL

#define GHCB_MSR_INFO_POS		0
#define GHCB_MSR_INFO_MASK		(BIT_ULL(12) - 1)

#define GHCB_MSR_SEV_INFO_RESP		0x001
#define GHCB_MSR_SEV_INFO_REQ		0x002
#define GHCB_MSR_VER_MAX_POS		48
#define GHCB_MSR_VER_MAX_MASK		0xffff
#define GHCB_MSR_VER_MIN_POS		32
#define GHCB_MSR_VER_MIN_MASK		0xffff
#define GHCB_MSR_CBIT_POS		24
#define GHCB_MSR_CBIT_MASK		0xff
#define GHCB_MSR_SEV_INFO(_max, _min, _cbit)				\
	((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) |	\
	 (((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) |	\
	 (((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) |	\
	 GHCB_MSR_SEV_INFO_RESP)

#define GHCB_MSR_CPUID_REQ		0x004
#define GHCB_MSR_CPUID_RESP		0x005
#define GHCB_MSR_CPUID_FUNC_POS		32
#define GHCB_MSR_CPUID_FUNC_MASK	0xffffffff
#define GHCB_MSR_CPUID_VALUE_POS	32
#define GHCB_MSR_CPUID_VALUE_MASK	0xffffffff
#define GHCB_MSR_CPUID_REG_POS		30
#define GHCB_MSR_CPUID_REG_MASK		0x3

#define GHCB_MSR_TERM_REQ		0x100
#define GHCB_MSR_TERM_REASON_SET_POS	12
#define GHCB_MSR_TERM_REASON_SET_MASK	0xf
#define GHCB_MSR_TERM_REASON_POS	16
#define GHCB_MSR_TERM_REASON_MASK	0xff

extern unsigned int max_sev_asid;

static inline bool svm_sev_enabled(void)
{
	return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
}

void sev_vm_destroy(struct kvm *kvm);
int svm_mem_enc_op(struct kvm *kvm, void __user *argp);
int svm_register_enc_region(struct kvm *kvm,
			    struct kvm_enc_region *range);
int svm_unregister_enc_region(struct kvm *kvm,
			      struct kvm_enc_region *range);
void pre_sev_run(struct vcpu_svm *svm, int cpu);
void __init sev_hardware_setup(void);
void sev_hardware_teardown(void);
void sev_free_vcpu(struct kvm_vcpu *vcpu);
int sev_handle_vmgexit(struct vcpu_svm *svm);
int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in);
void sev_es_init_vmcb(struct vcpu_svm *svm);
void sev_es_create_vcpu(struct vcpu_svm *svm);
void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector);
void sev_es_prepare_guest_switch(struct vcpu_svm *svm, unsigned int cpu);

/* vmenter.S */

void __svm_sev_es_vcpu_run(unsigned long vmcb_pa);
void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);

#endif
Commit	Line	Data
883b0a91 JR	1	// SPDX-License-Identifier: GPL-2.0-only
	2	/*
	3	* Kernel-based Virtual Machine driver for Linux
	4	*
	5	* AMD SVM support
	6	*
	7	* Copyright (C) 2006 Qumranet, Inc.
	8	* Copyright 2010 Red Hat, Inc. and/or its affiliates.
	9	*
	10	* Authors:
	11	* Yaniv Kamay <yaniv@qumranet.com>
	12	* Avi Kivity <avi@qumranet.com>
	13	*/
	14
	15	#ifndef __SVM_SVM_H
	16	#define __SVM_SVM_H
	17
	18	#include <linux/kvm_types.h>
	19	#include <linux/kvm_host.h>
291bd20d	20	#include <linux/bits.h>
883b0a91 JR	21
	22	#include <asm/svm.h>
	23
85ca8be9 TL	24	#define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
85ca8be9 TL	25
553cc15f MR	26	static const u32 host_save_user_msrs[] = {
553cc15f MR	27	MSR_TSC_AUX,
883b0a91	28	};
883b0a91 JR	29	#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
883b0a91 JR	30
376c6d28	31	#define MAX_DIRECT_ACCESS_MSRS 18
883b0a91 JR	32	#define MSRPM_OFFSETS 16
	33	extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
	34	extern bool npt_enabled;
	35
	36	enum {
	37	VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
	38	pause filter count */
	39	VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
	40	VMCB_ASID, /* ASID */
	41	VMCB_INTR, /* int_ctl, int_vector */
	42	VMCB_NPT, /* npt_en, nCR3, gPAT */
	43	VMCB_CR, /* CR0, CR3, CR4, EFER */
	44	VMCB_DR, /* DR6, DR7 */
	45	VMCB_DT, /* GDT, IDT */
	46	VMCB_SEG, /* CS, DS, SS, ES, CPL */
	47	VMCB_CR2, /* CR2 only */
	48	VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
	49	VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
	50	* AVIC PHYSICAL_TABLE pointer,
	51	* AVIC LOGICAL_TABLE pointer
	52	*/
	53	VMCB_DIRTY_MAX,
	54	};
	55
	56	/* TPR and CR2 are always written before VMRUN */
	57	#define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) \| (1U << VMCB_CR2))
	58
	59	struct kvm_sev_info {
	60	bool active; /* SEV enabled guest */
916391a2	61	bool es_active; /* SEV-ES enabled guest */
883b0a91 JR	62	unsigned int asid; /* ASID used for this guest */
	63	unsigned int handle; /* SEV firmware handle */
	64	int fd; /* SEV device fd */
	65	unsigned long pages_locked; /* Number of pages locked */
	66	struct list_head regions_list; /* List of registered regions */
8640ca58	67	u64 ap_jump_table; /* SEV-ES AP Jump Table address */
883b0a91 JR	68	};
	69
	70	struct kvm_svm {
	71	struct kvm kvm;
	72
	73	/* Struct members for AVIC */
	74	u32 avic_vm_id;
	75	struct page *avic_logical_id_table_page;
	76	struct page *avic_physical_id_table_page;
	77	struct hlist_node hnode;
	78
	79	struct kvm_sev_info sev_info;
	80	};
	81
	82	struct kvm_vcpu;
	83
4995a368 CA	84	struct kvm_vmcb_info {
	85	struct vmcb *ptr;
	86	unsigned long pa;
af18fa77	87	int cpu;
193015ad	88	uint64_t asid_generation;
4995a368 CA	89	};
4995a368 CA	90
7693b3eb	91	struct svm_nested_state {
4995a368	92	struct kvm_vmcb_info vmcb02;
883b0a91 JR	93	u64 hsave_msr;
883b0a91 JR	94	u64 vm_cr_msr;
0dd16b5b	95	u64 vmcb12_gpa;
883b0a91 JR	96
	97	/* These are the merged vectors */
	98	u32 *msrpm;
	99
f74f9414 PB	100	/* A VMRUN has started but has not yet been performed, so
	101	* we cannot inject a nested vmexit yet. */
	102	bool nested_run_pending;
	103
e670bf68 PB	104	/* cache for control fields of the guest */
e670bf68 PB	105	struct vmcb_control_area ctl;
2fcf4876 ML	106
2fcf4876 ML	107	bool initialized;
883b0a91 JR	108	};
	109
	110	struct vcpu_svm {
	111	struct kvm_vcpu vcpu;
	112	struct vmcb *vmcb;
	113	unsigned long vmcb_pa;
4995a368 CA	114	struct kvm_vmcb_info vmcb01;
4995a368 CA	115	struct kvm_vmcb_info *current_vmcb;
883b0a91	116	struct svm_cpu_data *svm_data;
7e8e6eed	117	u32 asid;
883b0a91 JR	118	uint64_t sysenter_esp;
	119	uint64_t sysenter_eip;
	120	uint64_t tsc_aux;
	121
	122	u64 msr_decfg;
	123
	124	u64 next_rip;
	125
	126	u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
883b0a91 JR	127
	128	u64 spec_ctrl;
	129	/*
	130	* Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
	131	* translated into the appropriate L2_CFG bits on the host to
	132	* perform speculative control.
	133	*/
	134	u64 virt_spec_ctrl;
	135
	136	u32 *msrpm;
	137
	138	ulong nmi_iret_rip;
	139
7693b3eb	140	struct svm_nested_state nested;
883b0a91 JR	141
	142	bool nmi_singlestep;
	143	u64 nmi_singlestep_guest_rflags;
	144
	145	unsigned int3_injected;
	146	unsigned long int3_rip;
	147
	148	/* cached guest cpuid flags for faster access */
	149	bool nrips_enabled : 1;
	150
	151	u32 ldr_reg;
	152	u32 dfr_reg;
	153	struct page *avic_backing_page;
	154	u64 *avic_physical_id_cache;
	155	bool avic_is_running;
	156
	157	/*
	158	* Per-vcpu list of struct amd_svm_iommu_ir:
	159	* This is used mainly to store interrupt remapping information used
	160	* when update the vcpu affinity. This avoids the need to scan for
	161	* IRTE and try to match ga_tag in the IOMMU driver.
	162	*/
	163	struct list_head ir_list;
	164	spinlock_t ir_list_lock;
fd6fa73d AG	165
	166	/* Save desired MSR intercept (read: pass-through) state */
	167	struct {
	168	DECLARE_BITMAP(read, MAX_DIRECT_ACCESS_MSRS);
	169	DECLARE_BITMAP(write, MAX_DIRECT_ACCESS_MSRS);
	170	} shadow_msr_intercept;
add5e2f0 TL	171
	172	/* SEV-ES support */
	173	struct vmcb_save_area *vmsa;
	174	struct ghcb *ghcb;
291bd20d	175	struct kvm_host_map ghcb_map;
647daca2	176	bool received_first_sipi;
8f423a80 TL	177
	178	/* SEV-ES scratch area support */
	179	void *ghcb_sa;
	180	u64 ghcb_sa_len;
	181	bool ghcb_sa_sync;
	182	bool ghcb_sa_free;
a7fc06dd MR	183
a7fc06dd MR	184	bool guest_state_loaded;
883b0a91 JR	185	};
883b0a91 JR	186
eaf78265 JR	187	struct svm_cpu_data {
	188	int cpu;
	189
	190	u64 asid_generation;
	191	u32 max_asid;
	192	u32 next_asid;
	193	u32 min_asid;
	194	struct kvm_ldttss_desc *tss_desc;
	195
	196	struct page *save_area;
	197	struct vmcb *current_vmcb;
	198
	199	/* index = sev_asid, value = vmcb pointer */
	200	struct vmcb **sev_vmcbs;
	201	};
	202
	203	DECLARE_PER_CPU(struct svm_cpu_data *, svm_data);
	204
883b0a91 JR	205	void recalc_intercepts(struct vcpu_svm *svm);
883b0a91 JR	206
ef0f6496 JR	207	static inline struct kvm_svm to_kvm_svm(struct kvm kvm)
	208	{
	209	return container_of(kvm, struct kvm_svm, kvm);
	210	}
	211
916391a2 TL	212	static inline bool sev_guest(struct kvm *kvm)
	213	{
	214	#ifdef CONFIG_KVM_AMD_SEV
	215	struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
	216
	217	return sev->active;
	218	#else
	219	return false;
	220	#endif
	221	}
	222
	223	static inline bool sev_es_guest(struct kvm *kvm)
	224	{
	225	#ifdef CONFIG_KVM_AMD_SEV
	226	struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
	227
	228	return sev_guest(kvm) && sev->es_active;
	229	#else
	230	return false;
	231	#endif
	232	}
	233
06e7852c	234	static inline void vmcb_mark_all_dirty(struct vmcb *vmcb)
883b0a91 JR	235	{
	236	vmcb->control.clean = 0;
	237	}
	238
06e7852c	239	static inline void vmcb_mark_all_clean(struct vmcb *vmcb)
883b0a91 JR	240	{
	241	vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
	242	& ~VMCB_ALWAYS_DIRTY_MASK;
	243	}
	244
06e7852c	245	static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit)
883b0a91 JR	246	{
	247	vmcb->control.clean &= ~(1 << bit);
	248	}
	249
	250	static inline struct vcpu_svm to_svm(struct kvm_vcpu vcpu)
	251	{
	252	return container_of(vcpu, struct vcpu_svm, vcpu);
	253	}
	254
c45ad722 BM	255	static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit)
	256	{
	257	WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
	258	__set_bit(bit, (unsigned long *)&control->intercepts);
	259	}
	260
	261	static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit)
	262	{
	263	WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
	264	__clear_bit(bit, (unsigned long *)&control->intercepts);
	265	}
	266
	267	static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit)
	268	{
	269	WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
	270	return test_bit(bit, (unsigned long *)&control->intercepts);
	271	}
	272
883b0a91 JR	273	static inline void set_dr_intercepts(struct vcpu_svm *svm)
883b0a91 JR	274	{
4995a368	275	struct vmcb *vmcb = svm->vmcb01.ptr;
883b0a91	276
8d4846b9 TL	277	if (!sev_es_guest(svm->vcpu.kvm)) {
	278	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_READ);
	279	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_READ);
	280	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_READ);
	281	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_READ);
	282	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_READ);
	283	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_READ);
	284	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_READ);
	285	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_WRITE);
	286	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_WRITE);
	287	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_WRITE);
	288	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_WRITE);
	289	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_WRITE);
	290	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_WRITE);
	291	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE);
	292	}
	293
30abaa88	294	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ);
30abaa88	295	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE);
883b0a91 JR	296
	297	recalc_intercepts(svm);
	298	}
	299
	300	static inline void clr_dr_intercepts(struct vcpu_svm *svm)
	301	{
4995a368	302	struct vmcb *vmcb = svm->vmcb01.ptr;
883b0a91	303
30abaa88	304	vmcb->control.intercepts[INTERCEPT_DR] = 0;
883b0a91	305
8d4846b9 TL	306	/* DR7 access must remain intercepted for an SEV-ES guest */
	307	if (sev_es_guest(svm->vcpu.kvm)) {
	308	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ);
	309	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE);
	310	}
	311
883b0a91 JR	312	recalc_intercepts(svm);
	313	}
	314
9780d51d	315	static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit)
883b0a91	316	{
4995a368	317	struct vmcb *vmcb = svm->vmcb01.ptr;
883b0a91	318
9780d51d BM	319	WARN_ON_ONCE(bit >= 32);
9780d51d BM	320	vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);
883b0a91 JR	321
	322	recalc_intercepts(svm);
	323	}
	324
9780d51d	325	static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit)
883b0a91	326	{
4995a368	327	struct vmcb *vmcb = svm->vmcb01.ptr;
883b0a91	328
9780d51d BM	329	WARN_ON_ONCE(bit >= 32);
9780d51d BM	330	vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);
883b0a91 JR	331
	332	recalc_intercepts(svm);
	333	}
	334
a284ba56	335	static inline void svm_set_intercept(struct vcpu_svm *svm, int bit)
883b0a91	336	{
4995a368	337	struct vmcb *vmcb = svm->vmcb01.ptr;
883b0a91	338
c62e2e94	339	vmcb_set_intercept(&vmcb->control, bit);
883b0a91 JR	340
	341	recalc_intercepts(svm);
	342	}
	343
a284ba56	344	static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit)
883b0a91	345	{
4995a368	346	struct vmcb *vmcb = svm->vmcb01.ptr;
883b0a91	347
c62e2e94	348	vmcb_clr_intercept(&vmcb->control, bit);
883b0a91 JR	349
	350	recalc_intercepts(svm);
	351	}
	352
a284ba56	353	static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit)
883b0a91	354	{
c62e2e94	355	return vmcb_is_intercept(&svm->vmcb->control, bit);
883b0a91 JR	356	}
	357
	358	static inline bool vgif_enabled(struct vcpu_svm *svm)
	359	{
	360	return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
	361	}
	362
	363	static inline void enable_gif(struct vcpu_svm *svm)
	364	{
	365	if (vgif_enabled(svm))
	366	svm->vmcb->control.int_ctl \|= V_GIF_MASK;
	367	else
	368	svm->vcpu.arch.hflags \|= HF_GIF_MASK;
	369	}
	370
	371	static inline void disable_gif(struct vcpu_svm *svm)
	372	{
	373	if (vgif_enabled(svm))
	374	svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
	375	else
	376	svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
	377	}
	378
	379	static inline bool gif_set(struct vcpu_svm *svm)
	380	{
	381	if (vgif_enabled(svm))
	382	return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
	383	else
	384	return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
	385	}
	386
	387	/* svm.c */
761e4169	388	#define MSR_INVALID 0xffffffffU
883b0a91	389
916391a2 TL	390	extern int sev;
916391a2 TL	391	extern int sev_es;
291bd20d	392	extern bool dump_invalid_vmcb;
916391a2	393
883b0a91	394	u32 svm_msrpm_offset(u32 msr);
2fcf4876 ML	395	u32 *svm_vcpu_alloc_msrpm(void);
	396	void svm_vcpu_init_msrpm(struct kvm_vcpu vcpu, u32 msrpm);
	397	void svm_vcpu_free_msrpm(u32 *msrpm);
	398
72f211ec	399	int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer);
883b0a91	400	void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
c2fe3cd4	401	void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
f55ac304	402	void svm_flush_tlb(struct kvm_vcpu *vcpu);
883b0a91	403	void disable_nmi_singlestep(struct vcpu_svm *svm);
cae96af1 PB	404	bool svm_smi_blocked(struct kvm_vcpu *vcpu);
	405	bool svm_nmi_blocked(struct kvm_vcpu *vcpu);
	406	bool svm_interrupt_blocked(struct kvm_vcpu *vcpu);
ffdf7f9e	407	void svm_set_gif(struct vcpu_svm *svm, bool value);
291bd20d	408	int svm_invoke_exit_handler(struct vcpu_svm *svm, u64 exit_code);
376c6d28 TL	409	void set_msr_interception(struct kvm_vcpu vcpu, u32 msrpm, u32 msr,
376c6d28 TL	410	int read, int write);
883b0a91 JR	411
	412	/* nested.c */
	413
	414	#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
	415	#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
	416	#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
	417
01c3b2b5	418	static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu)
883b0a91	419	{
e9fd761a PB	420	struct vcpu_svm *svm = to_svm(vcpu);
	421
	422	return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK);
883b0a91 JR	423	}
883b0a91 JR	424
55714cdd PB	425	static inline bool nested_exit_on_smi(struct vcpu_svm *svm)
55714cdd PB	426	{
c62e2e94	427	return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SMI);
55714cdd PB	428	}
55714cdd PB	429
fc6f7c03 PB	430	static inline bool nested_exit_on_intr(struct vcpu_svm *svm)
fc6f7c03 PB	431	{
c62e2e94	432	return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_INTR);
fc6f7c03 PB	433	}
fc6f7c03 PB	434
bbdad0b5 PB	435	static inline bool nested_exit_on_nmi(struct vcpu_svm *svm)
bbdad0b5 PB	436	{
c62e2e94	437	return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_NMI);
bbdad0b5 PB	438	}
bbdad0b5 PB	439
9e8f0fbf	440	int enter_svm_guest_mode(struct vcpu_svm svm, u64 vmcb_gpa, struct vmcb vmcb12);
c513f484	441	void svm_leave_nested(struct vcpu_svm *svm);
2fcf4876 ML	442	void svm_free_nested(struct vcpu_svm *svm);
2fcf4876 ML	443	int svm_allocate_nested(struct vcpu_svm *svm);
883b0a91 JR	444	int nested_svm_vmrun(struct vcpu_svm *svm);
	445	void nested_svm_vmloadsave(struct vmcb from_vmcb, struct vmcb to_vmcb);
	446	int nested_svm_vmexit(struct vcpu_svm *svm);
	447	int nested_svm_exit_handled(struct vcpu_svm *svm);
	448	int nested_svm_check_permissions(struct vcpu_svm *svm);
	449	int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
	450	bool has_error_code, u32 error_code);
883b0a91	451	int nested_svm_exit_special(struct vcpu_svm *svm);
9e8f0fbf	452	void nested_sync_control_from_vmcb02(struct vcpu_svm *svm);
4995a368 CA	453	void nested_vmcb02_compute_g_pat(struct vcpu_svm *svm);
4995a368 CA	454	void svm_switch_vmcb(struct vcpu_svm svm, struct kvm_vmcb_info target_vmcb);
883b0a91	455
33b22172 PB	456	extern struct kvm_x86_nested_ops svm_nested_ops;
33b22172 PB	457
ef0f6496 JR	458	/* avic.c */
	459
	460	#define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
	461	#define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31
	462	#define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
	463
	464	#define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
	465	#define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
	466	#define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
	467	#define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
	468
	469	#define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
	470
	471	extern int avic;
	472
	473	static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
	474	{
	475	svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
06e7852c	476	vmcb_mark_dirty(svm->vmcb, VMCB_AVIC);
ef0f6496 JR	477	}
	478
	479	static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
	480	{
	481	struct vcpu_svm *svm = to_svm(vcpu);
	482	u64 *entry = svm->avic_physical_id_cache;
	483
	484	if (!entry)
	485	return false;
	486
	487	return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
	488	}
	489
	490	int avic_ga_log_notifier(u32 ga_tag);
	491	void avic_vm_destroy(struct kvm *kvm);
	492	int avic_vm_init(struct kvm *kvm);
	493	void avic_init_vmcb(struct vcpu_svm *svm);
	494	void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate);
	495	int avic_incomplete_ipi_interception(struct vcpu_svm *svm);
	496	int avic_unaccelerated_access_interception(struct vcpu_svm *svm);
	497	int avic_init_vcpu(struct vcpu_svm *svm);
	498	void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
	499	void avic_vcpu_put(struct kvm_vcpu *vcpu);
	500	void avic_post_state_restore(struct kvm_vcpu *vcpu);
	501	void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
	502	void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu);
	503	bool svm_check_apicv_inhibit_reasons(ulong bit);
	504	void svm_pre_update_apicv_exec_ctrl(struct kvm *kvm, bool activate);
	505	void svm_load_eoi_exitmap(struct kvm_vcpu vcpu, u64 eoi_exit_bitmap);
	506	void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr);
	507	void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr);
	508	int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec);
	509	bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu);
	510	int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
	511	uint32_t guest_irq, bool set);
	512	void svm_vcpu_blocking(struct kvm_vcpu *vcpu);
	513	void svm_vcpu_unblocking(struct kvm_vcpu *vcpu);
	514
eaf78265 JR	515	/* sev.c */
eaf78265 JR	516
1edc1459 TL	517	#define GHCB_VERSION_MAX 1ULL
	518	#define GHCB_VERSION_MIN 1ULL
	519
291bd20d TL	520	#define GHCB_MSR_INFO_POS 0
	521	#define GHCB_MSR_INFO_MASK (BIT_ULL(12) - 1)
	522
1edc1459 TL	523	#define GHCB_MSR_SEV_INFO_RESP 0x001
	524	#define GHCB_MSR_SEV_INFO_REQ 0x002
	525	#define GHCB_MSR_VER_MAX_POS 48
	526	#define GHCB_MSR_VER_MAX_MASK 0xffff
	527	#define GHCB_MSR_VER_MIN_POS 32
	528	#define GHCB_MSR_VER_MIN_MASK 0xffff
	529	#define GHCB_MSR_CBIT_POS 24
	530	#define GHCB_MSR_CBIT_MASK 0xff
	531	#define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \
	532	((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) \| \
	533	(((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) \| \
	534	(((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) \| \
	535	GHCB_MSR_SEV_INFO_RESP)
	536
d3694667 TL	537	#define GHCB_MSR_CPUID_REQ 0x004
	538	#define GHCB_MSR_CPUID_RESP 0x005
	539	#define GHCB_MSR_CPUID_FUNC_POS 32
	540	#define GHCB_MSR_CPUID_FUNC_MASK 0xffffffff
	541	#define GHCB_MSR_CPUID_VALUE_POS 32
	542	#define GHCB_MSR_CPUID_VALUE_MASK 0xffffffff
	543	#define GHCB_MSR_CPUID_REG_POS 30
	544	#define GHCB_MSR_CPUID_REG_MASK 0x3
	545
e1d71116 TL	546	#define GHCB_MSR_TERM_REQ 0x100
	547	#define GHCB_MSR_TERM_REASON_SET_POS 12
	548	#define GHCB_MSR_TERM_REASON_SET_MASK 0xf
	549	#define GHCB_MSR_TERM_REASON_POS 16
	550	#define GHCB_MSR_TERM_REASON_MASK 0xff
	551
eaf78265 JR	552	extern unsigned int max_sev_asid;
eaf78265 JR	553
eaf78265 JR	554	static inline bool svm_sev_enabled(void)
	555	{
	556	return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
	557	}
	558
	559	void sev_vm_destroy(struct kvm *kvm);
	560	int svm_mem_enc_op(struct kvm kvm, void __user argp);
	561	int svm_register_enc_region(struct kvm *kvm,
	562	struct kvm_enc_region *range);
	563	int svm_unregister_enc_region(struct kvm *kvm,
	564	struct kvm_enc_region *range);
	565	void pre_sev_run(struct vcpu_svm *svm, int cpu);
916391a2	566	void __init sev_hardware_setup(void);
eaf78265	567	void sev_hardware_teardown(void);
add5e2f0	568	void sev_free_vcpu(struct kvm_vcpu *vcpu);
291bd20d	569	int sev_handle_vmgexit(struct vcpu_svm *svm);
7ed9abfe	570	int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in);
376c6d28 TL	571	void sev_es_init_vmcb(struct vcpu_svm *svm);
376c6d28 TL	572	void sev_es_create_vcpu(struct vcpu_svm *svm);
647daca2	573	void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector);
a7fc06dd	574	void sev_es_prepare_guest_switch(struct vcpu_svm *svm, unsigned int cpu);
eaf78265	575
16809ecd TL	576	/* vmenter.S */
	577
	578	void __svm_sev_es_vcpu_run(unsigned long vmcb_pa);
	579	void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
	580
883b0a91	581	#endif