[linux-block.git] / arch / x86 / kvm / svm / svm.h

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Kernel-based Virtual Machine driver for Linux
 *
 * AMD SVM support
 *
 * Copyright (C) 2006 Qumranet, Inc.
 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
 *
 * Authors:
 *   Yaniv Kamay  <yaniv@qumranet.com>
 *   Avi Kivity   <avi@qumranet.com>
 */

#ifndef __SVM_SVM_H
#define __SVM_SVM_H

#include <linux/kvm_types.h>
#include <linux/kvm_host.h>

#include <asm/svm.h>

static const u32 host_save_user_msrs[] = {
#ifdef CONFIG_X86_64
	MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
	MSR_FS_BASE,
#endif
	MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
	MSR_TSC_AUX,
};

#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)

#define MSRPM_OFFSETS	16
extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
extern bool npt_enabled;

enum {
	VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
			    pause filter count */
	VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
	VMCB_ASID,	 /* ASID */
	VMCB_INTR,	 /* int_ctl, int_vector */
	VMCB_NPT,        /* npt_en, nCR3, gPAT */
	VMCB_CR,	 /* CR0, CR3, CR4, EFER */
	VMCB_DR,         /* DR6, DR7 */
	VMCB_DT,         /* GDT, IDT */
	VMCB_SEG,        /* CS, DS, SS, ES, CPL */
	VMCB_CR2,        /* CR2 only */
	VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
	VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
			  * AVIC PHYSICAL_TABLE pointer,
			  * AVIC LOGICAL_TABLE pointer
			  */
	VMCB_DIRTY_MAX,
};

/* TPR and CR2 are always written before VMRUN */
#define VMCB_ALWAYS_DIRTY_MASK	((1U << VMCB_INTR) | (1U << VMCB_CR2))

struct kvm_sev_info {
	bool active;		/* SEV enabled guest */
	unsigned int asid;	/* ASID used for this guest */
	unsigned int handle;	/* SEV firmware handle */
	int fd;			/* SEV device fd */
	unsigned long pages_locked; /* Number of pages locked */
	struct list_head regions_list;  /* List of registered regions */
};

struct kvm_svm {
	struct kvm kvm;

	/* Struct members for AVIC */
	u32 avic_vm_id;
	struct page *avic_logical_id_table_page;
	struct page *avic_physical_id_table_page;
	struct hlist_node hnode;

	struct kvm_sev_info sev_info;
};

struct kvm_vcpu;

struct svm_nested_state {
	struct vmcb *hsave;
	u64 hsave_msr;
	u64 vm_cr_msr;
	u64 vmcb;
	u32 host_intercept_exceptions;

	/* These are the merged vectors */
	u32 *msrpm;

	/* A VMRUN has started but has not yet been performed, so
	 * we cannot inject a nested vmexit yet.  */
	bool nested_run_pending;

	/* cache for control fields of the guest */
	struct vmcb_control_area ctl;
};

struct vcpu_svm {
	struct kvm_vcpu vcpu;
	struct vmcb *vmcb;
	unsigned long vmcb_pa;
	struct svm_cpu_data *svm_data;
	uint64_t asid_generation;
	uint64_t sysenter_esp;
	uint64_t sysenter_eip;
	uint64_t tsc_aux;

	u64 msr_decfg;

	u64 next_rip;

	u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
	struct {
		u16 fs;
		u16 gs;
		u16 ldt;
		u64 gs_base;
	} host;

	u64 spec_ctrl;
	/*
	 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
	 * translated into the appropriate L2_CFG bits on the host to
	 * perform speculative control.
	 */
	u64 virt_spec_ctrl;

	u32 *msrpm;

	ulong nmi_iret_rip;

	struct svm_nested_state nested;

	bool nmi_singlestep;
	u64 nmi_singlestep_guest_rflags;

	unsigned int3_injected;
	unsigned long int3_rip;

	/* cached guest cpuid flags for faster access */
	bool nrips_enabled	: 1;

	u32 ldr_reg;
	u32 dfr_reg;
	struct page *avic_backing_page;
	u64 *avic_physical_id_cache;
	bool avic_is_running;

	/*
	 * Per-vcpu list of struct amd_svm_iommu_ir:
	 * This is used mainly to store interrupt remapping information used
	 * when update the vcpu affinity. This avoids the need to scan for
	 * IRTE and try to match ga_tag in the IOMMU driver.
	 */
	struct list_head ir_list;
	spinlock_t ir_list_lock;
};

struct svm_cpu_data {
	int cpu;

	u64 asid_generation;
	u32 max_asid;
	u32 next_asid;
	u32 min_asid;
	struct kvm_ldttss_desc *tss_desc;

	struct page *save_area;
	struct vmcb *current_vmcb;

	/* index = sev_asid, value = vmcb pointer */
	struct vmcb **sev_vmcbs;
};

DECLARE_PER_CPU(struct svm_cpu_data *, svm_data);

void recalc_intercepts(struct vcpu_svm *svm);

static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
{
	return container_of(kvm, struct kvm_svm, kvm);
}

static inline void vmcb_mark_all_dirty(struct vmcb *vmcb)
{
	vmcb->control.clean = 0;
}

static inline void vmcb_mark_all_clean(struct vmcb *vmcb)
{
	vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
			       & ~VMCB_ALWAYS_DIRTY_MASK;
}

static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit)
{
	vmcb->control.clean &= ~(1 << bit);
}

static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
{
	return container_of(vcpu, struct vcpu_svm, vcpu);
}

static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
{
	if (is_guest_mode(&svm->vcpu))
		return svm->nested.hsave;
	else
		return svm->vmcb;
}

static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	vmcb->control.intercept_cr |= (1U << bit);

	recalc_intercepts(svm);
}

static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	vmcb->control.intercept_cr &= ~(1U << bit);

	recalc_intercepts(svm);
}

static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	return vmcb->control.intercept_cr & (1U << bit);
}

static inline void set_dr_intercepts(struct vcpu_svm *svm)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
		| (1 << INTERCEPT_DR1_READ)
		| (1 << INTERCEPT_DR2_READ)
		| (1 << INTERCEPT_DR3_READ)
		| (1 << INTERCEPT_DR4_READ)
		| (1 << INTERCEPT_DR5_READ)
		| (1 << INTERCEPT_DR6_READ)
		| (1 << INTERCEPT_DR7_READ)
		| (1 << INTERCEPT_DR0_WRITE)
		| (1 << INTERCEPT_DR1_WRITE)
		| (1 << INTERCEPT_DR2_WRITE)
		| (1 << INTERCEPT_DR3_WRITE)
		| (1 << INTERCEPT_DR4_WRITE)
		| (1 << INTERCEPT_DR5_WRITE)
		| (1 << INTERCEPT_DR6_WRITE)
		| (1 << INTERCEPT_DR7_WRITE);

	recalc_intercepts(svm);
}

static inline void clr_dr_intercepts(struct vcpu_svm *svm)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	vmcb->control.intercept_dr = 0;

	recalc_intercepts(svm);
}

static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	vmcb->control.intercept_exceptions |= (1U << bit);

	recalc_intercepts(svm);
}

static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	vmcb->control.intercept_exceptions &= ~(1U << bit);

	recalc_intercepts(svm);
}

static inline void set_intercept(struct vcpu_svm *svm, int bit)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	vmcb->control.intercept |= (1ULL << bit);

	recalc_intercepts(svm);
}

static inline void clr_intercept(struct vcpu_svm *svm, int bit)
{
	struct vmcb *vmcb = get_host_vmcb(svm);

	vmcb->control.intercept &= ~(1ULL << bit);

	recalc_intercepts(svm);
}

static inline bool is_intercept(struct vcpu_svm *svm, int bit)
{
	return (svm->vmcb->control.intercept & (1ULL << bit)) != 0;
}

static inline bool vgif_enabled(struct vcpu_svm *svm)
{
	return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
}

static inline void enable_gif(struct vcpu_svm *svm)
{
	if (vgif_enabled(svm))
		svm->vmcb->control.int_ctl |= V_GIF_MASK;
	else
		svm->vcpu.arch.hflags |= HF_GIF_MASK;
}

static inline void disable_gif(struct vcpu_svm *svm)
{
	if (vgif_enabled(svm))
		svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
	else
		svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
}

static inline bool gif_set(struct vcpu_svm *svm)
{
	if (vgif_enabled(svm))
		return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
	else
		return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
}

/* svm.c */
#define MSR_INVALID			0xffffffffU

u32 svm_msrpm_offset(u32 msr);
void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer);
void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
void svm_flush_tlb(struct kvm_vcpu *vcpu);
void disable_nmi_singlestep(struct vcpu_svm *svm);
bool svm_smi_blocked(struct kvm_vcpu *vcpu);
bool svm_nmi_blocked(struct kvm_vcpu *vcpu);
bool svm_interrupt_blocked(struct kvm_vcpu *vcpu);
void svm_set_gif(struct vcpu_svm *svm, bool value);

/* nested.c */

#define NESTED_EXIT_HOST	0	/* Exit handled on host level */
#define NESTED_EXIT_DONE	1	/* Exit caused nested vmexit  */
#define NESTED_EXIT_CONTINUE	2	/* Further checks needed      */

static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
{
	struct vcpu_svm *svm = to_svm(vcpu);

	return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK);
}

static inline bool nested_exit_on_smi(struct vcpu_svm *svm)
{
	return (svm->nested.ctl.intercept & (1ULL << INTERCEPT_SMI));
}

static inline bool nested_exit_on_intr(struct vcpu_svm *svm)
{
	return (svm->nested.ctl.intercept & (1ULL << INTERCEPT_INTR));
}

static inline bool nested_exit_on_nmi(struct vcpu_svm *svm)
{
	return (svm->nested.ctl.intercept & (1ULL << INTERCEPT_NMI));
}

void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
			  struct vmcb *nested_vmcb);
void svm_leave_nested(struct vcpu_svm *svm);
int nested_svm_vmrun(struct vcpu_svm *svm);
void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb);
int nested_svm_vmexit(struct vcpu_svm *svm);
int nested_svm_exit_handled(struct vcpu_svm *svm);
int nested_svm_check_permissions(struct vcpu_svm *svm);
int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
			       bool has_error_code, u32 error_code);
int nested_svm_exit_special(struct vcpu_svm *svm);
void sync_nested_vmcb_control(struct vcpu_svm *svm);

extern struct kvm_x86_nested_ops svm_nested_ops;

/* avic.c */

#define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK	(0xFF)
#define AVIC_LOGICAL_ID_ENTRY_VALID_BIT			31
#define AVIC_LOGICAL_ID_ENTRY_VALID_MASK		(1 << 31)

#define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK	(0xFFULL)
#define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK	(0xFFFFFFFFFFULL << 12)
#define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK		(1ULL << 62)
#define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK		(1ULL << 63)

#define VMCB_AVIC_APIC_BAR_MASK		0xFFFFFFFFFF000ULL

extern int avic;

static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
{
	svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
	vmcb_mark_dirty(svm->vmcb, VMCB_AVIC);
}

static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
{
	struct vcpu_svm *svm = to_svm(vcpu);
	u64 *entry = svm->avic_physical_id_cache;

	if (!entry)
		return false;

	return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
}

int avic_ga_log_notifier(u32 ga_tag);
void avic_vm_destroy(struct kvm *kvm);
int avic_vm_init(struct kvm *kvm);
void avic_init_vmcb(struct vcpu_svm *svm);
void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate);
int avic_incomplete_ipi_interception(struct vcpu_svm *svm);
int avic_unaccelerated_access_interception(struct vcpu_svm *svm);
int avic_init_vcpu(struct vcpu_svm *svm);
void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
void avic_vcpu_put(struct kvm_vcpu *vcpu);
void avic_post_state_restore(struct kvm_vcpu *vcpu);
void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu);
bool svm_check_apicv_inhibit_reasons(ulong bit);
void svm_pre_update_apicv_exec_ctrl(struct kvm *kvm, bool activate);
void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap);
void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr);
void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr);
int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec);
bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu);
int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
		       uint32_t guest_irq, bool set);
void svm_vcpu_blocking(struct kvm_vcpu *vcpu);
void svm_vcpu_unblocking(struct kvm_vcpu *vcpu);

/* sev.c */

extern unsigned int max_sev_asid;

static inline bool sev_guest(struct kvm *kvm)
{
#ifdef CONFIG_KVM_AMD_SEV
	struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;

	return sev->active;
#else
	return false;
#endif
}

static inline bool svm_sev_enabled(void)
{
	return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
}

void sev_vm_destroy(struct kvm *kvm);
int svm_mem_enc_op(struct kvm *kvm, void __user *argp);
int svm_register_enc_region(struct kvm *kvm,
			    struct kvm_enc_region *range);
int svm_unregister_enc_region(struct kvm *kvm,
			      struct kvm_enc_region *range);
void pre_sev_run(struct vcpu_svm *svm, int cpu);
int __init sev_hardware_setup(void);
void sev_hardware_teardown(void);

#endif
Commit	Line	Data
883b0a91 JR	1	// SPDX-License-Identifier: GPL-2.0-only
	2	/*
	3	* Kernel-based Virtual Machine driver for Linux
	4	*
	5	* AMD SVM support
	6	*
	7	* Copyright (C) 2006 Qumranet, Inc.
	8	* Copyright 2010 Red Hat, Inc. and/or its affiliates.
	9	*
	10	* Authors:
	11	* Yaniv Kamay <yaniv@qumranet.com>
	12	* Avi Kivity <avi@qumranet.com>
	13	*/
	14
	15	#ifndef __SVM_SVM_H
	16	#define __SVM_SVM_H
	17
	18	#include <linux/kvm_types.h>
	19	#include <linux/kvm_host.h>
	20
	21	#include <asm/svm.h>
	22
	23	static const u32 host_save_user_msrs[] = {
	24	#ifdef CONFIG_X86_64
	25	MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
	26	MSR_FS_BASE,
	27	#endif
	28	MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
	29	MSR_TSC_AUX,
	30	};
	31
	32	#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
	33
	34	#define MSRPM_OFFSETS 16
	35	extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
	36	extern bool npt_enabled;
	37
	38	enum {
	39	VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
	40	pause filter count */
	41	VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
	42	VMCB_ASID, /* ASID */
	43	VMCB_INTR, /* int_ctl, int_vector */
	44	VMCB_NPT, /* npt_en, nCR3, gPAT */
	45	VMCB_CR, /* CR0, CR3, CR4, EFER */
	46	VMCB_DR, /* DR6, DR7 */
	47	VMCB_DT, /* GDT, IDT */
	48	VMCB_SEG, /* CS, DS, SS, ES, CPL */
	49	VMCB_CR2, /* CR2 only */
	50	VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
	51	VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
	52	* AVIC PHYSICAL_TABLE pointer,
	53	* AVIC LOGICAL_TABLE pointer
	54	*/
	55	VMCB_DIRTY_MAX,
	56	};
	57
	58	/* TPR and CR2 are always written before VMRUN */
	59	#define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) \| (1U << VMCB_CR2))
	60
	61	struct kvm_sev_info {
	62	bool active; /* SEV enabled guest */
	63	unsigned int asid; /* ASID used for this guest */
	64	unsigned int handle; /* SEV firmware handle */
65	int fd; /* SEV device fd */
66	unsigned long pages_locked; /* Number of pages locked */
67	struct list_head regions_list; /* List of registered regions */
68	};
69
70	struct kvm_svm {
71	struct kvm kvm;
72
73	/* Struct members for AVIC */
74	u32 avic_vm_id;
75	struct page *avic_logical_id_table_page;
76	struct page *avic_physical_id_table_page;
77	struct hlist_node hnode;
78
79	struct kvm_sev_info sev_info;
80	};
81
82	struct kvm_vcpu;
83
7693b3eb	84	struct svm_nested_state {
883b0a91 JR	85	struct vmcb *hsave;
	86	u64 hsave_msr;
	87	u64 vm_cr_msr;
	88	u64 vmcb;
7c86663b	89	u32 host_intercept_exceptions;
883b0a91 JR	90
	91	/* These are the merged vectors */
	92	u32 *msrpm;
	93
f74f9414 PB	94	/* A VMRUN has started but has not yet been performed, so
	95	* we cannot inject a nested vmexit yet. */
	96	bool nested_run_pending;
	97
e670bf68 PB	98	/* cache for control fields of the guest */
e670bf68 PB	99	struct vmcb_control_area ctl;
883b0a91 JR	100	};
	101
	102	struct vcpu_svm {
	103	struct kvm_vcpu vcpu;
	104	struct vmcb *vmcb;
	105	unsigned long vmcb_pa;
	106	struct svm_cpu_data *svm_data;
	107	uint64_t asid_generation;
	108	uint64_t sysenter_esp;
	109	uint64_t sysenter_eip;
	110	uint64_t tsc_aux;
	111
	112	u64 msr_decfg;
	113
	114	u64 next_rip;
	115
	116	u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
	117	struct {
	118	u16 fs;
	119	u16 gs;
	120	u16 ldt;
	121	u64 gs_base;
	122	} host;
	123
	124	u64 spec_ctrl;
	125	/*
	126	* Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
	127	* translated into the appropriate L2_CFG bits on the host to
	128	* perform speculative control.
	129	*/
	130	u64 virt_spec_ctrl;
	131
	132	u32 *msrpm;
	133
	134	ulong nmi_iret_rip;
	135
7693b3eb	136	struct svm_nested_state nested;
883b0a91 JR	137
	138	bool nmi_singlestep;
	139	u64 nmi_singlestep_guest_rflags;
	140
	141	unsigned int3_injected;
	142	unsigned long int3_rip;
	143
	144	/* cached guest cpuid flags for faster access */
	145	bool nrips_enabled : 1;
	146
	147	u32 ldr_reg;
	148	u32 dfr_reg;
	149	struct page *avic_backing_page;
	150	u64 *avic_physical_id_cache;
	151	bool avic_is_running;
	152
	153	/*
	154	* Per-vcpu list of struct amd_svm_iommu_ir:
	155	* This is used mainly to store interrupt remapping information used
	156	* when update the vcpu affinity. This avoids the need to scan for
	157	* IRTE and try to match ga_tag in the IOMMU driver.
	158	*/
	159	struct list_head ir_list;
	160	spinlock_t ir_list_lock;
883b0a91 JR	161	};
883b0a91 JR	162
eaf78265 JR	163	struct svm_cpu_data {
	164	int cpu;
	165
	166	u64 asid_generation;
	167	u32 max_asid;
	168	u32 next_asid;
	169	u32 min_asid;
	170	struct kvm_ldttss_desc *tss_desc;
	171
	172	struct page *save_area;
	173	struct vmcb *current_vmcb;
	174
	175	/* index = sev_asid, value = vmcb pointer */
	176	struct vmcb **sev_vmcbs;
	177	};
	178
	179	DECLARE_PER_CPU(struct svm_cpu_data *, svm_data);
	180
883b0a91 JR	181	void recalc_intercepts(struct vcpu_svm *svm);
883b0a91 JR	182
ef0f6496 JR	183	static inline struct kvm_svm to_kvm_svm(struct kvm kvm)
	184	{
	185	return container_of(kvm, struct kvm_svm, kvm);
	186	}
	187
06e7852c	188	static inline void vmcb_mark_all_dirty(struct vmcb *vmcb)
883b0a91 JR	189	{
	190	vmcb->control.clean = 0;
	191	}
	192
06e7852c	193	static inline void vmcb_mark_all_clean(struct vmcb *vmcb)
883b0a91 JR	194	{
	195	vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
	196	& ~VMCB_ALWAYS_DIRTY_MASK;
	197	}
	198
06e7852c	199	static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit)
883b0a91 JR	200	{
	201	vmcb->control.clean &= ~(1 << bit);
	202	}
	203
	204	static inline struct vcpu_svm to_svm(struct kvm_vcpu vcpu)
	205	{
	206	return container_of(vcpu, struct vcpu_svm, vcpu);
	207	}
	208
	209	static inline struct vmcb get_host_vmcb(struct vcpu_svm svm)
	210	{
	211	if (is_guest_mode(&svm->vcpu))
	212	return svm->nested.hsave;
	213	else
	214	return svm->vmcb;
	215	}
	216
	217	static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
	218	{
	219	struct vmcb *vmcb = get_host_vmcb(svm);
	220
	221	vmcb->control.intercept_cr \|= (1U << bit);
	222
	223	recalc_intercepts(svm);
	224	}
	225
	226	static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
	227	{
	228	struct vmcb *vmcb = get_host_vmcb(svm);
	229
	230	vmcb->control.intercept_cr &= ~(1U << bit);
	231
	232	recalc_intercepts(svm);
	233	}
	234
	235	static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
	236	{
	237	struct vmcb *vmcb = get_host_vmcb(svm);
	238
	239	return vmcb->control.intercept_cr & (1U << bit);
	240	}
	241
	242	static inline void set_dr_intercepts(struct vcpu_svm *svm)
	243	{
	244	struct vmcb *vmcb = get_host_vmcb(svm);
	245
	246	vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
	247	\| (1 << INTERCEPT_DR1_READ)
	248	\| (1 << INTERCEPT_DR2_READ)
	249	\| (1 << INTERCEPT_DR3_READ)
	250	\| (1 << INTERCEPT_DR4_READ)
	251	\| (1 << INTERCEPT_DR5_READ)
	252	\| (1 << INTERCEPT_DR6_READ)
	253	\| (1 << INTERCEPT_DR7_READ)
	254	\| (1 << INTERCEPT_DR0_WRITE)
	255	\| (1 << INTERCEPT_DR1_WRITE)
	256	\| (1 << INTERCEPT_DR2_WRITE)
	257	\| (1 << INTERCEPT_DR3_WRITE)
	258	\| (1 << INTERCEPT_DR4_WRITE)
	259	\| (1 << INTERCEPT_DR5_WRITE)
	260	\| (1 << INTERCEPT_DR6_WRITE)
	261	\| (1 << INTERCEPT_DR7_WRITE);
	262
	263	recalc_intercepts(svm);
264	}
265
266	static inline void clr_dr_intercepts(struct vcpu_svm *svm)
267	{
268	struct vmcb *vmcb = get_host_vmcb(svm);
269
270	vmcb->control.intercept_dr = 0;
271
272	recalc_intercepts(svm);
273	}
274
275	static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
276	{
277	struct vmcb *vmcb = get_host_vmcb(svm);
278
279	vmcb->control.intercept_exceptions \|= (1U << bit);
280
281	recalc_intercepts(svm);
282	}
283
284	static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
285	{
286	struct vmcb *vmcb = get_host_vmcb(svm);
287
288	vmcb->control.intercept_exceptions &= ~(1U << bit);
289
290	recalc_intercepts(svm);
291	}
292
293	static inline void set_intercept(struct vcpu_svm *svm, int bit)
294	{
295	struct vmcb *vmcb = get_host_vmcb(svm);
296
297	vmcb->control.intercept \|= (1ULL << bit);
298
299	recalc_intercepts(svm);
300	}
301
302	static inline void clr_intercept(struct vcpu_svm *svm, int bit)
303	{
304	struct vmcb *vmcb = get_host_vmcb(svm);
305
306	vmcb->control.intercept &= ~(1ULL << bit);
307
308	recalc_intercepts(svm);
309	}
310
311	static inline bool is_intercept(struct vcpu_svm *svm, int bit)
312	{
313	return (svm->vmcb->control.intercept & (1ULL << bit)) != 0;
314	}
315
316	static inline bool vgif_enabled(struct vcpu_svm *svm)
317	{
318	return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
319	}
320
321	static inline void enable_gif(struct vcpu_svm *svm)
322	{
323	if (vgif_enabled(svm))
324	svm->vmcb->control.int_ctl \|= V_GIF_MASK;
325	else
326	svm->vcpu.arch.hflags \|= HF_GIF_MASK;
327	}
328
329	static inline void disable_gif(struct vcpu_svm *svm)
330	{
331	if (vgif_enabled(svm))
332	svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
333	else
334	svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
335	}
336
337	static inline bool gif_set(struct vcpu_svm *svm)
338	{
339	if (vgif_enabled(svm))
340	return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
341	else
342	return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
343	}
344
345	/* svm.c */
346	#define MSR_INVALID 0xffffffffU
347
348	u32 svm_msrpm_offset(u32 msr);
349	void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer);
350	void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
351	int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
f55ac304	352	void svm_flush_tlb(struct kvm_vcpu *vcpu);
883b0a91	353	void disable_nmi_singlestep(struct vcpu_svm *svm);
cae96af1 PB	354	bool svm_smi_blocked(struct kvm_vcpu *vcpu);
	355	bool svm_nmi_blocked(struct kvm_vcpu *vcpu);
	356	bool svm_interrupt_blocked(struct kvm_vcpu *vcpu);
ffdf7f9e	357	void svm_set_gif(struct vcpu_svm *svm, bool value);
883b0a91 JR	358
	359	/* nested.c */
	360
	361	#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
	362	#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
	363	#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
	364
883b0a91 JR	365	static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
883b0a91 JR	366	{
e9fd761a PB	367	struct vcpu_svm *svm = to_svm(vcpu);
	368
	369	return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK);
883b0a91 JR	370	}
883b0a91 JR	371
55714cdd PB	372	static inline bool nested_exit_on_smi(struct vcpu_svm *svm)
55714cdd PB	373	{
e670bf68	374	return (svm->nested.ctl.intercept & (1ULL << INTERCEPT_SMI));
55714cdd PB	375	}
55714cdd PB	376
fc6f7c03 PB	377	static inline bool nested_exit_on_intr(struct vcpu_svm *svm)
fc6f7c03 PB	378	{
e670bf68	379	return (svm->nested.ctl.intercept & (1ULL << INTERCEPT_INTR));
fc6f7c03 PB	380	}
fc6f7c03 PB	381
bbdad0b5 PB	382	static inline bool nested_exit_on_nmi(struct vcpu_svm *svm)
bbdad0b5 PB	383	{
e670bf68	384	return (svm->nested.ctl.intercept & (1ULL << INTERCEPT_NMI));
bbdad0b5 PB	385	}
bbdad0b5 PB	386
883b0a91	387	void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
69c9dfa2	388	struct vmcb *nested_vmcb);
c513f484	389	void svm_leave_nested(struct vcpu_svm *svm);
883b0a91 JR	390	int nested_svm_vmrun(struct vcpu_svm *svm);
	391	void nested_svm_vmloadsave(struct vmcb from_vmcb, struct vmcb to_vmcb);
	392	int nested_svm_vmexit(struct vcpu_svm *svm);
	393	int nested_svm_exit_handled(struct vcpu_svm *svm);
	394	int nested_svm_check_permissions(struct vcpu_svm *svm);
	395	int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
	396	bool has_error_code, u32 error_code);
883b0a91	397	int nested_svm_exit_special(struct vcpu_svm *svm);
2d8a42be	398	void sync_nested_vmcb_control(struct vcpu_svm *svm);
883b0a91	399
33b22172 PB	400	extern struct kvm_x86_nested_ops svm_nested_ops;
33b22172 PB	401
ef0f6496 JR	402	/* avic.c */
	403
	404	#define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
	405	#define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31
	406	#define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
	407
	408	#define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
	409	#define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
	410	#define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
	411	#define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
	412
	413	#define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
	414
	415	extern int avic;
	416
	417	static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
	418	{
	419	svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
06e7852c	420	vmcb_mark_dirty(svm->vmcb, VMCB_AVIC);
ef0f6496 JR	421	}
	422
	423	static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
	424	{
	425	struct vcpu_svm *svm = to_svm(vcpu);
	426	u64 *entry = svm->avic_physical_id_cache;
	427
	428	if (!entry)
	429	return false;
	430
	431	return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
	432	}
	433
	434	int avic_ga_log_notifier(u32 ga_tag);
	435	void avic_vm_destroy(struct kvm *kvm);
	436	int avic_vm_init(struct kvm *kvm);
	437	void avic_init_vmcb(struct vcpu_svm *svm);
	438	void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate);
	439	int avic_incomplete_ipi_interception(struct vcpu_svm *svm);
	440	int avic_unaccelerated_access_interception(struct vcpu_svm *svm);
	441	int avic_init_vcpu(struct vcpu_svm *svm);
	442	void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
	443	void avic_vcpu_put(struct kvm_vcpu *vcpu);
	444	void avic_post_state_restore(struct kvm_vcpu *vcpu);
	445	void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
	446	void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu);
	447	bool svm_check_apicv_inhibit_reasons(ulong bit);
	448	void svm_pre_update_apicv_exec_ctrl(struct kvm *kvm, bool activate);
	449	void svm_load_eoi_exitmap(struct kvm_vcpu vcpu, u64 eoi_exit_bitmap);
	450	void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr);
	451	void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr);
	452	int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec);
	453	bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu);
	454	int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
	455	uint32_t guest_irq, bool set);
	456	void svm_vcpu_blocking(struct kvm_vcpu *vcpu);
	457	void svm_vcpu_unblocking(struct kvm_vcpu *vcpu);
	458
eaf78265 JR	459	/* sev.c */
	460
	461	extern unsigned int max_sev_asid;
	462
	463	static inline bool sev_guest(struct kvm *kvm)
	464	{
	465	#ifdef CONFIG_KVM_AMD_SEV
	466	struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
	467
	468	return sev->active;
	469	#else
	470	return false;
	471	#endif
	472	}
	473
	474	static inline bool svm_sev_enabled(void)
	475	{
	476	return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
	477	}
	478
	479	void sev_vm_destroy(struct kvm *kvm);
	480	int svm_mem_enc_op(struct kvm kvm, void __user argp);
	481	int svm_register_enc_region(struct kvm *kvm,
	482	struct kvm_enc_region *range);
	483	int svm_unregister_enc_region(struct kvm *kvm,
	484	struct kvm_enc_region *range);
	485	void pre_sev_run(struct vcpu_svm *svm, int cpu);
	486	int __init sev_hardware_setup(void);
	487	void sev_hardware_teardown(void);
	488
883b0a91	489	#endif