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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
474a5bb9 WH |
2 | #ifndef __KVM_X86_PMU_H |
3 | #define __KVM_X86_PMU_H | |
4 | ||
13c5183a MP |
5 | #include <linux/nospec.h> |
6 | ||
6ebe4436 LX |
7 | #include <asm/cpu_device_id.h> |
8 | ||
474a5bb9 WH |
9 | #define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu) |
10 | #define pmu_to_vcpu(pmu) (container_of((pmu), struct kvm_vcpu, arch.pmu)) | |
11 | #define pmc_to_pmu(pmc) (&(pmc)->vcpu->arch.pmu) | |
12 | ||
25462f7f WH |
13 | /* retrieve the 4 bits for EN and PMI out of IA32_FIXED_CTR_CTRL */ |
14 | #define fixed_ctrl_field(ctrl_reg, idx) (((ctrl_reg) >> ((idx)*4)) & 0xf) | |
15 | ||
2d7921c4 AM |
16 | #define VMWARE_BACKDOOR_PMC_HOST_TSC 0x10000 |
17 | #define VMWARE_BACKDOOR_PMC_REAL_TIME 0x10001 | |
18 | #define VMWARE_BACKDOOR_PMC_APPARENT_TIME 0x10002 | |
19 | ||
6ebe4436 LX |
20 | static const struct x86_cpu_id vmx_icl_pebs_cpu[] = { |
21 | X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, NULL), | |
22 | X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, NULL), | |
23 | {} | |
24 | }; | |
25 | ||
474a5bb9 WH |
26 | struct kvm_event_hw_type_mapping { |
27 | u8 eventsel; | |
28 | u8 unit_mask; | |
29 | unsigned event_type; | |
30 | }; | |
31 | ||
25462f7f | 32 | struct kvm_pmu_ops { |
7c174f30 | 33 | unsigned int (*pmc_perf_hw_id)(struct kvm_pmc *pmc); |
25462f7f WH |
34 | bool (*pmc_is_enabled)(struct kvm_pmc *pmc); |
35 | struct kvm_pmc *(*pmc_idx_to_pmc)(struct kvm_pmu *pmu, int pmc_idx); | |
98ff80f5 LX |
36 | struct kvm_pmc *(*rdpmc_ecx_to_pmc)(struct kvm_vcpu *vcpu, |
37 | unsigned int idx, u64 *mask); | |
c900c156 | 38 | struct kvm_pmc *(*msr_idx_to_pmc)(struct kvm_vcpu *vcpu, u32 msr); |
e6cd31f1 | 39 | bool (*is_valid_rdpmc_ecx)(struct kvm_vcpu *vcpu, unsigned int idx); |
25462f7f | 40 | bool (*is_valid_msr)(struct kvm_vcpu *vcpu, u32 msr); |
cbd71758 | 41 | int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info); |
25462f7f WH |
42 | int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info); |
43 | void (*refresh)(struct kvm_vcpu *vcpu); | |
44 | void (*init)(struct kvm_vcpu *vcpu); | |
45 | void (*reset)(struct kvm_vcpu *vcpu); | |
e6209a3b | 46 | void (*deliver_pmi)(struct kvm_vcpu *vcpu); |
9aa4f622 | 47 | void (*cleanup)(struct kvm_vcpu *vcpu); |
25462f7f WH |
48 | }; |
49 | ||
8f969c0c LX |
50 | void kvm_pmu_ops_update(const struct kvm_pmu_ops *pmu_ops); |
51 | ||
25462f7f WH |
52 | static inline u64 pmc_bitmask(struct kvm_pmc *pmc) |
53 | { | |
54 | struct kvm_pmu *pmu = pmc_to_pmu(pmc); | |
55 | ||
56 | return pmu->counter_bitmask[pmc->type]; | |
57 | } | |
58 | ||
59 | static inline u64 pmc_read_counter(struct kvm_pmc *pmc) | |
60 | { | |
61 | u64 counter, enabled, running; | |
62 | ||
63 | counter = pmc->counter; | |
e79f49c3 | 64 | if (pmc->perf_event && !pmc->is_paused) |
25462f7f WH |
65 | counter += perf_event_read_value(pmc->perf_event, |
66 | &enabled, &running); | |
67 | /* FIXME: Scaling needed? */ | |
68 | return counter & pmc_bitmask(pmc); | |
69 | } | |
70 | ||
a6da0d77 | 71 | static inline void pmc_release_perf_event(struct kvm_pmc *pmc) |
25462f7f WH |
72 | { |
73 | if (pmc->perf_event) { | |
25462f7f WH |
74 | perf_event_release_kernel(pmc->perf_event); |
75 | pmc->perf_event = NULL; | |
a6da0d77 | 76 | pmc->current_config = 0; |
b35e5548 | 77 | pmc_to_pmu(pmc)->event_count--; |
a6da0d77 LX |
78 | } |
79 | } | |
80 | ||
81 | static inline void pmc_stop_counter(struct kvm_pmc *pmc) | |
82 | { | |
83 | if (pmc->perf_event) { | |
84 | pmc->counter = pmc_read_counter(pmc); | |
85 | pmc_release_perf_event(pmc); | |
25462f7f WH |
86 | } |
87 | } | |
88 | ||
89 | static inline bool pmc_is_gp(struct kvm_pmc *pmc) | |
90 | { | |
91 | return pmc->type == KVM_PMC_GP; | |
92 | } | |
93 | ||
94 | static inline bool pmc_is_fixed(struct kvm_pmc *pmc) | |
95 | { | |
96 | return pmc->type == KVM_PMC_FIXED; | |
97 | } | |
98 | ||
9477f444 OU |
99 | static inline bool kvm_valid_perf_global_ctrl(struct kvm_pmu *pmu, |
100 | u64 data) | |
101 | { | |
102 | return !(pmu->global_ctrl_mask & data); | |
103 | } | |
104 | ||
25462f7f WH |
105 | /* returns general purpose PMC with the specified MSR. Note that it can be |
106 | * used for both PERFCTRn and EVNTSELn; that is why it accepts base as a | |
d9f6e12f | 107 | * parameter to tell them apart. |
25462f7f WH |
108 | */ |
109 | static inline struct kvm_pmc *get_gp_pmc(struct kvm_pmu *pmu, u32 msr, | |
110 | u32 base) | |
111 | { | |
13c5183a MP |
112 | if (msr >= base && msr < base + pmu->nr_arch_gp_counters) { |
113 | u32 index = array_index_nospec(msr - base, | |
114 | pmu->nr_arch_gp_counters); | |
115 | ||
116 | return &pmu->gp_counters[index]; | |
117 | } | |
25462f7f WH |
118 | |
119 | return NULL; | |
120 | } | |
121 | ||
122 | /* returns fixed PMC with the specified MSR */ | |
123 | static inline struct kvm_pmc *get_fixed_pmc(struct kvm_pmu *pmu, u32 msr) | |
124 | { | |
125 | int base = MSR_CORE_PERF_FIXED_CTR0; | |
126 | ||
13c5183a MP |
127 | if (msr >= base && msr < base + pmu->nr_arch_fixed_counters) { |
128 | u32 index = array_index_nospec(msr - base, | |
129 | pmu->nr_arch_fixed_counters); | |
130 | ||
131 | return &pmu->fixed_counters[index]; | |
132 | } | |
25462f7f WH |
133 | |
134 | return NULL; | |
135 | } | |
136 | ||
168d918f EH |
137 | static inline u64 get_sample_period(struct kvm_pmc *pmc, u64 counter_value) |
138 | { | |
139 | u64 sample_period = (-counter_value) & pmc_bitmask(pmc); | |
140 | ||
141 | if (!sample_period) | |
142 | sample_period = pmc_bitmask(pmc) + 1; | |
143 | return sample_period; | |
144 | } | |
145 | ||
75189d1d LX |
146 | static inline void pmc_update_sample_period(struct kvm_pmc *pmc) |
147 | { | |
148 | if (!pmc->perf_event || pmc->is_paused) | |
149 | return; | |
150 | ||
151 | perf_event_period(pmc->perf_event, | |
152 | get_sample_period(pmc, pmc->counter)); | |
153 | } | |
154 | ||
63f21f32 LX |
155 | static inline bool pmc_speculative_in_use(struct kvm_pmc *pmc) |
156 | { | |
157 | struct kvm_pmu *pmu = pmc_to_pmu(pmc); | |
158 | ||
159 | if (pmc_is_fixed(pmc)) | |
160 | return fixed_ctrl_field(pmu->fixed_ctr_ctrl, | |
161 | pmc->idx - INTEL_PMC_IDX_FIXED) & 0x3; | |
162 | ||
163 | return pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE; | |
164 | } | |
165 | ||
25462f7f WH |
166 | void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel); |
167 | void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int fixed_idx); | |
168 | void reprogram_counter(struct kvm_pmu *pmu, int pmc_idx); | |
169 | ||
474a5bb9 WH |
170 | void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu); |
171 | void kvm_pmu_handle_event(struct kvm_vcpu *vcpu); | |
172 | int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); | |
e6cd31f1 | 173 | bool kvm_pmu_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx); |
474a5bb9 | 174 | bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr); |
cbd71758 | 175 | int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info); |
474a5bb9 WH |
176 | int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info); |
177 | void kvm_pmu_refresh(struct kvm_vcpu *vcpu); | |
178 | void kvm_pmu_reset(struct kvm_vcpu *vcpu); | |
179 | void kvm_pmu_init(struct kvm_vcpu *vcpu); | |
b35e5548 | 180 | void kvm_pmu_cleanup(struct kvm_vcpu *vcpu); |
474a5bb9 | 181 | void kvm_pmu_destroy(struct kvm_vcpu *vcpu); |
66bb8a06 | 182 | int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp); |
9cd803d4 | 183 | void kvm_pmu_trigger_event(struct kvm_vcpu *vcpu, u64 perf_hw_id); |
474a5bb9 | 184 | |
2d7921c4 AM |
185 | bool is_vmware_backdoor_pmc(u32 pmc_idx); |
186 | ||
25462f7f WH |
187 | extern struct kvm_pmu_ops intel_pmu_ops; |
188 | extern struct kvm_pmu_ops amd_pmu_ops; | |
474a5bb9 | 189 | #endif /* __KVM_X86_PMU_H */ |