[linux-block.git] / arch / x86 / kvm / pmu.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __KVM_X86_PMU_H
#define __KVM_X86_PMU_H

#include <linux/nospec.h>

#define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu)
#define pmu_to_vcpu(pmu)  (container_of((pmu), struct kvm_vcpu, arch.pmu))
#define pmc_to_pmu(pmc)   (&(pmc)->vcpu->arch.pmu)

#define MSR_IA32_MISC_ENABLE_PMU_RO_MASK (MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL |	\
					  MSR_IA32_MISC_ENABLE_BTS_UNAVAIL)

/* retrieve the 4 bits for EN and PMI out of IA32_FIXED_CTR_CTRL */
#define fixed_ctrl_field(ctrl_reg, idx) (((ctrl_reg) >> ((idx)*4)) & 0xf)

#define VMWARE_BACKDOOR_PMC_HOST_TSC		0x10000
#define VMWARE_BACKDOOR_PMC_REAL_TIME		0x10001
#define VMWARE_BACKDOOR_PMC_APPARENT_TIME	0x10002

struct kvm_pmu_ops {
	bool (*hw_event_available)(struct kvm_pmc *pmc);
	struct kvm_pmc *(*pmc_idx_to_pmc)(struct kvm_pmu *pmu, int pmc_idx);
	struct kvm_pmc *(*rdpmc_ecx_to_pmc)(struct kvm_vcpu *vcpu,
		unsigned int idx, u64 *mask);
	struct kvm_pmc *(*msr_idx_to_pmc)(struct kvm_vcpu *vcpu, u32 msr);
	bool (*is_valid_rdpmc_ecx)(struct kvm_vcpu *vcpu, unsigned int idx);
	bool (*is_valid_msr)(struct kvm_vcpu *vcpu, u32 msr);
	int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
	int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
	void (*refresh)(struct kvm_vcpu *vcpu);
	void (*init)(struct kvm_vcpu *vcpu);
	void (*reset)(struct kvm_vcpu *vcpu);
	void (*deliver_pmi)(struct kvm_vcpu *vcpu);
	void (*cleanup)(struct kvm_vcpu *vcpu);

	const u64 EVENTSEL_EVENT;
	const int MAX_NR_GP_COUNTERS;
	const int MIN_NR_GP_COUNTERS;
};

void kvm_pmu_ops_update(const struct kvm_pmu_ops *pmu_ops);

static inline bool kvm_pmu_has_perf_global_ctrl(struct kvm_pmu *pmu)
{
	/*
	 * Architecturally, Intel's SDM states that IA32_PERF_GLOBAL_CTRL is
	 * supported if "CPUID.0AH: EAX[7:0] > 0", i.e. if the PMU version is
	 * greater than zero.  However, KVM only exposes and emulates the MSR
	 * to/for the guest if the guest PMU supports at least "Architectural
	 * Performance Monitoring Version 2".
	 *
	 * AMD's version of PERF_GLOBAL_CTRL conveniently shows up with v2.
	 */
	return pmu->version > 1;
}

static inline u64 pmc_bitmask(struct kvm_pmc *pmc)
{
	struct kvm_pmu *pmu = pmc_to_pmu(pmc);

	return pmu->counter_bitmask[pmc->type];
}

static inline u64 pmc_read_counter(struct kvm_pmc *pmc)
{
	u64 counter, enabled, running;

	counter = pmc->counter;
	if (pmc->perf_event && !pmc->is_paused)
		counter += perf_event_read_value(pmc->perf_event,
						 &enabled, &running);
	/* FIXME: Scaling needed? */
	return counter & pmc_bitmask(pmc);
}

static inline void pmc_release_perf_event(struct kvm_pmc *pmc)
{
	if (pmc->perf_event) {
		perf_event_release_kernel(pmc->perf_event);
		pmc->perf_event = NULL;
		pmc->current_config = 0;
		pmc_to_pmu(pmc)->event_count--;
	}
}

static inline void pmc_stop_counter(struct kvm_pmc *pmc)
{
	if (pmc->perf_event) {
		pmc->counter = pmc_read_counter(pmc);
		pmc_release_perf_event(pmc);
	}
}

static inline bool pmc_is_gp(struct kvm_pmc *pmc)
{
	return pmc->type == KVM_PMC_GP;
}

static inline bool pmc_is_fixed(struct kvm_pmc *pmc)
{
	return pmc->type == KVM_PMC_FIXED;
}

static inline bool kvm_valid_perf_global_ctrl(struct kvm_pmu *pmu,
						 u64 data)
{
	return !(pmu->global_ctrl_mask & data);
}

/* returns general purpose PMC with the specified MSR. Note that it can be
 * used for both PERFCTRn and EVNTSELn; that is why it accepts base as a
 * parameter to tell them apart.
 */
static inline struct kvm_pmc *get_gp_pmc(struct kvm_pmu *pmu, u32 msr,
					 u32 base)
{
	if (msr >= base && msr < base + pmu->nr_arch_gp_counters) {
		u32 index = array_index_nospec(msr - base,
					       pmu->nr_arch_gp_counters);

		return &pmu->gp_counters[index];
	}

	return NULL;
}

/* returns fixed PMC with the specified MSR */
static inline struct kvm_pmc *get_fixed_pmc(struct kvm_pmu *pmu, u32 msr)
{
	int base = MSR_CORE_PERF_FIXED_CTR0;

	if (msr >= base && msr < base + pmu->nr_arch_fixed_counters) {
		u32 index = array_index_nospec(msr - base,
					       pmu->nr_arch_fixed_counters);

		return &pmu->fixed_counters[index];
	}

	return NULL;
}

static inline u64 get_sample_period(struct kvm_pmc *pmc, u64 counter_value)
{
	u64 sample_period = (-counter_value) & pmc_bitmask(pmc);

	if (!sample_period)
		sample_period = pmc_bitmask(pmc) + 1;
	return sample_period;
}

static inline void pmc_update_sample_period(struct kvm_pmc *pmc)
{
	if (!pmc->perf_event || pmc->is_paused ||
	    !is_sampling_event(pmc->perf_event))
		return;

	perf_event_period(pmc->perf_event,
			  get_sample_period(pmc, pmc->counter));
}

static inline bool pmc_speculative_in_use(struct kvm_pmc *pmc)
{
	struct kvm_pmu *pmu = pmc_to_pmu(pmc);

	if (pmc_is_fixed(pmc))
		return fixed_ctrl_field(pmu->fixed_ctr_ctrl,
					pmc->idx - INTEL_PMC_IDX_FIXED) & 0x3;

	return pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE;
}

extern struct x86_pmu_capability kvm_pmu_cap;

static inline void kvm_init_pmu_capability(const struct kvm_pmu_ops *pmu_ops)
{
	bool is_intel = boot_cpu_data.x86_vendor == X86_VENDOR_INTEL;
	int min_nr_gp_ctrs = pmu_ops->MIN_NR_GP_COUNTERS;

	/*
	 * Hybrid PMUs don't play nice with virtualization without careful
	 * configuration by userspace, and KVM's APIs for reporting supported
	 * vPMU features do not account for hybrid PMUs.  Disable vPMU support
	 * for hybrid PMUs until KVM gains a way to let userspace opt-in.
	 */
	if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
		enable_pmu = false;

	if (enable_pmu) {
		perf_get_x86_pmu_capability(&kvm_pmu_cap);

		/*
		 * WARN if perf did NOT disable hardware PMU if the number of
		 * architecturally required GP counters aren't present, i.e. if
		 * there are a non-zero number of counters, but fewer than what
		 * is architecturally required.
		 */
		if (!kvm_pmu_cap.num_counters_gp ||
		    WARN_ON_ONCE(kvm_pmu_cap.num_counters_gp < min_nr_gp_ctrs))
			enable_pmu = false;
		else if (is_intel && !kvm_pmu_cap.version)
			enable_pmu = false;
	}

	if (!enable_pmu) {
		memset(&kvm_pmu_cap, 0, sizeof(kvm_pmu_cap));
		return;
	}

	kvm_pmu_cap.version = min(kvm_pmu_cap.version, 2);
	kvm_pmu_cap.num_counters_gp = min(kvm_pmu_cap.num_counters_gp,
					  pmu_ops->MAX_NR_GP_COUNTERS);
	kvm_pmu_cap.num_counters_fixed = min(kvm_pmu_cap.num_counters_fixed,
					     KVM_PMC_MAX_FIXED);
}

static inline void kvm_pmu_request_counter_reprogram(struct kvm_pmc *pmc)
{
	set_bit(pmc->idx, pmc_to_pmu(pmc)->reprogram_pmi);
	kvm_make_request(KVM_REQ_PMU, pmc->vcpu);
}

static inline void reprogram_counters(struct kvm_pmu *pmu, u64 diff)
{
	int bit;

	if (!diff)
		return;

	for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX)
		set_bit(bit, pmu->reprogram_pmi);
	kvm_make_request(KVM_REQ_PMU, pmu_to_vcpu(pmu));
}

/*
 * Check if a PMC is enabled by comparing it against global_ctrl bits.
 *
 * If the vPMU doesn't have global_ctrl MSR, all vPMCs are enabled.
 */
static inline bool pmc_is_globally_enabled(struct kvm_pmc *pmc)
{
	struct kvm_pmu *pmu = pmc_to_pmu(pmc);

	if (!kvm_pmu_has_perf_global_ctrl(pmu))
		return true;

	return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl);
}

void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu);
void kvm_pmu_handle_event(struct kvm_vcpu *vcpu);
int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data);
bool kvm_pmu_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx);
bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr);
int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
void kvm_pmu_refresh(struct kvm_vcpu *vcpu);
void kvm_pmu_reset(struct kvm_vcpu *vcpu);
void kvm_pmu_init(struct kvm_vcpu *vcpu);
void kvm_pmu_cleanup(struct kvm_vcpu *vcpu);
void kvm_pmu_destroy(struct kvm_vcpu *vcpu);
int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp);
void kvm_pmu_trigger_event(struct kvm_vcpu *vcpu, u64 perf_hw_id);

bool is_vmware_backdoor_pmc(u32 pmc_idx);

extern struct kvm_pmu_ops intel_pmu_ops;
extern struct kvm_pmu_ops amd_pmu_ops;
#endif /* __KVM_X86_PMU_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
474a5bb9 WH	2	#ifndef __KVM_X86_PMU_H
	3	#define __KVM_X86_PMU_H
	4
13c5183a MP	5	#include <linux/nospec.h>
13c5183a MP	6
474a5bb9 WH	7	#define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu)
	8	#define pmu_to_vcpu(pmu) (container_of((pmu), struct kvm_vcpu, arch.pmu))
	9	#define pmc_to_pmu(pmc) (&(pmc)->vcpu->arch.pmu)
	10
b9181c8e LX	11	#define MSR_IA32_MISC_ENABLE_PMU_RO_MASK (MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL \| \
	12	MSR_IA32_MISC_ENABLE_BTS_UNAVAIL)
	13
25462f7f WH	14	/* retrieve the 4 bits for EN and PMI out of IA32_FIXED_CTR_CTRL */
	15	#define fixed_ctrl_field(ctrl_reg, idx) (((ctrl_reg) >> ((idx)*4)) & 0xf)
	16
2d7921c4 AM	17	#define VMWARE_BACKDOOR_PMC_HOST_TSC 0x10000
	18	#define VMWARE_BACKDOOR_PMC_REAL_TIME 0x10001
	19	#define VMWARE_BACKDOOR_PMC_APPARENT_TIME 0x10002
	20
25462f7f	21	struct kvm_pmu_ops {
7aadaa98	22	bool (hw_event_available)(struct kvm_pmc pmc);
25462f7f	23	struct kvm_pmc (pmc_idx_to_pmc)(struct kvm_pmu *pmu, int pmc_idx);
98ff80f5 LX	24	struct kvm_pmc (rdpmc_ecx_to_pmc)(struct kvm_vcpu *vcpu,
98ff80f5 LX	25	unsigned int idx, u64 *mask);
c900c156	26	struct kvm_pmc (msr_idx_to_pmc)(struct kvm_vcpu *vcpu, u32 msr);
e6cd31f1	27	bool (is_valid_rdpmc_ecx)(struct kvm_vcpu vcpu, unsigned int idx);
545feb96	28	bool (is_valid_msr)(struct kvm_vcpu vcpu, u32 msr);
cbd71758	29	int (get_msr)(struct kvm_vcpu vcpu, struct msr_data *msr_info);
25462f7f WH	30	int (set_msr)(struct kvm_vcpu vcpu, struct msr_data *msr_info);
	31	void (refresh)(struct kvm_vcpu vcpu);
	32	void (init)(struct kvm_vcpu vcpu);
	33	void (reset)(struct kvm_vcpu vcpu);
e6209a3b	34	void (deliver_pmi)(struct kvm_vcpu vcpu);
9aa4f622	35	void (cleanup)(struct kvm_vcpu vcpu);
6a5cba7b AL	36
6a5cba7b AL	37	const u64 EVENTSEL_EVENT;
8911ce66	38	const int MAX_NR_GP_COUNTERS;
6a08083f	39	const int MIN_NR_GP_COUNTERS;
25462f7f WH	40	};
25462f7f WH	41
8f969c0c LX	42	void kvm_pmu_ops_update(const struct kvm_pmu_ops *pmu_ops);
8f969c0c LX	43
c85cdc1c LX	44	static inline bool kvm_pmu_has_perf_global_ctrl(struct kvm_pmu *pmu)
	45	{
	46	/*
	47	* Architecturally, Intel's SDM states that IA32_PERF_GLOBAL_CTRL is
	48	* supported if "CPUID.0AH: EAX[7:0] > 0", i.e. if the PMU version is
	49	* greater than zero. However, KVM only exposes and emulates the MSR
	50	* to/for the guest if the guest PMU supports at least "Architectural
	51	* Performance Monitoring Version 2".
	52	*
	53	* AMD's version of PERF_GLOBAL_CTRL conveniently shows up with v2.
	54	*/
	55	return pmu->version > 1;
	56	}
	57
25462f7f WH	58	static inline u64 pmc_bitmask(struct kvm_pmc *pmc)
	59	{
	60	struct kvm_pmu *pmu = pmc_to_pmu(pmc);
	61
	62	return pmu->counter_bitmask[pmc->type];
	63	}
	64
	65	static inline u64 pmc_read_counter(struct kvm_pmc *pmc)
	66	{
	67	u64 counter, enabled, running;
	68
	69	counter = pmc->counter;
e79f49c3	70	if (pmc->perf_event && !pmc->is_paused)
25462f7f WH	71	counter += perf_event_read_value(pmc->perf_event,
	72	&enabled, &running);
	73	/* FIXME: Scaling needed? */
	74	return counter & pmc_bitmask(pmc);
	75	}
	76
a6da0d77	77	static inline void pmc_release_perf_event(struct kvm_pmc *pmc)
25462f7f WH	78	{
25462f7f WH	79	if (pmc->perf_event) {
25462f7f WH	80	perf_event_release_kernel(pmc->perf_event);
25462f7f WH	81	pmc->perf_event = NULL;
a6da0d77	82	pmc->current_config = 0;
b35e5548	83	pmc_to_pmu(pmc)->event_count--;
a6da0d77 LX	84	}
	85	}
	86
	87	static inline void pmc_stop_counter(struct kvm_pmc *pmc)
	88	{
	89	if (pmc->perf_event) {
	90	pmc->counter = pmc_read_counter(pmc);
	91	pmc_release_perf_event(pmc);
25462f7f WH	92	}
	93	}
	94
	95	static inline bool pmc_is_gp(struct kvm_pmc *pmc)
	96	{
	97	return pmc->type == KVM_PMC_GP;
	98	}
	99
	100	static inline bool pmc_is_fixed(struct kvm_pmc *pmc)
	101	{
	102	return pmc->type == KVM_PMC_FIXED;
	103	}
	104
9477f444 OU	105	static inline bool kvm_valid_perf_global_ctrl(struct kvm_pmu *pmu,
	106	u64 data)
	107	{
	108	return !(pmu->global_ctrl_mask & data);
	109	}
	110
25462f7f WH	111	/* returns general purpose PMC with the specified MSR. Note that it can be
25462f7f WH	112	* used for both PERFCTRn and EVNTSELn; that is why it accepts base as a
d9f6e12f	113	* parameter to tell them apart.
25462f7f WH	114	*/
	115	static inline struct kvm_pmc get_gp_pmc(struct kvm_pmu pmu, u32 msr,
	116	u32 base)
	117	{
13c5183a MP	118	if (msr >= base && msr < base + pmu->nr_arch_gp_counters) {
	119	u32 index = array_index_nospec(msr - base,
	120	pmu->nr_arch_gp_counters);
	121
	122	return &pmu->gp_counters[index];
	123	}
25462f7f WH	124
	125	return NULL;
	126	}
	127
	128	/* returns fixed PMC with the specified MSR */
	129	static inline struct kvm_pmc get_fixed_pmc(struct kvm_pmu pmu, u32 msr)
	130	{
	131	int base = MSR_CORE_PERF_FIXED_CTR0;
	132
13c5183a MP	133	if (msr >= base && msr < base + pmu->nr_arch_fixed_counters) {
	134	u32 index = array_index_nospec(msr - base,
	135	pmu->nr_arch_fixed_counters);
	136
	137	return &pmu->fixed_counters[index];
	138	}
25462f7f WH	139
	140	return NULL;
	141	}
	142
168d918f EH	143	static inline u64 get_sample_period(struct kvm_pmc *pmc, u64 counter_value)
	144	{
	145	u64 sample_period = (-counter_value) & pmc_bitmask(pmc);
	146
	147	if (!sample_period)
	148	sample_period = pmc_bitmask(pmc) + 1;
	149	return sample_period;
	150	}
	151
75189d1d LX	152	static inline void pmc_update_sample_period(struct kvm_pmc *pmc)
75189d1d LX	153	{
55c590ad LX	154	if (!pmc->perf_event \|\| pmc->is_paused \|\|
55c590ad LX	155	!is_sampling_event(pmc->perf_event))
75189d1d LX	156	return;
	157
	158	perf_event_period(pmc->perf_event,
	159	get_sample_period(pmc, pmc->counter));
	160	}
	161
63f21f32 LX	162	static inline bool pmc_speculative_in_use(struct kvm_pmc *pmc)
	163	{
	164	struct kvm_pmu *pmu = pmc_to_pmu(pmc);
	165
	166	if (pmc_is_fixed(pmc))
	167	return fixed_ctrl_field(pmu->fixed_ctr_ctrl,
	168	pmc->idx - INTEL_PMC_IDX_FIXED) & 0x3;
	169
	170	return pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE;
	171	}
	172
968635ab LX	173	extern struct x86_pmu_capability kvm_pmu_cap;
968635ab LX	174
8911ce66	175	static inline void kvm_init_pmu_capability(const struct kvm_pmu_ops *pmu_ops)
968635ab	176	{
d7808f73	177	bool is_intel = boot_cpu_data.x86_vendor == X86_VENDOR_INTEL;
6a08083f	178	int min_nr_gp_ctrs = pmu_ops->MIN_NR_GP_COUNTERS;
d7808f73	179
4d7404e5 SC	180	/*
	181	* Hybrid PMUs don't play nice with virtualization without careful
	182	* configuration by userspace, and KVM's APIs for reporting supported
	183	* vPMU features do not account for hybrid PMUs. Disable vPMU support
	184	* for hybrid PMUs until KVM gains a way to let userspace opt-in.
	185	*/
	186	if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
d7808f73	187	enable_pmu = false;
6ef25aa0	188
4d7404e5 SC	189	if (enable_pmu) {
	190	perf_get_x86_pmu_capability(&kvm_pmu_cap);
	191
	192	/*
6a08083f LX	193	* WARN if perf did NOT disable hardware PMU if the number of
	194	* architecturally required GP counters aren't present, i.e. if
	195	* there are a non-zero number of counters, but fewer than what
	196	* is architecturally required.
4d7404e5	197	*/
6a08083f LX	198	if (!kvm_pmu_cap.num_counters_gp \|\|
	199	WARN_ON_ONCE(kvm_pmu_cap.num_counters_gp < min_nr_gp_ctrs))
	200	enable_pmu = false;
	201	else if (is_intel && !kvm_pmu_cap.version)
4d7404e5 SC	202	enable_pmu = false;
	203	}
	204
6ef25aa0 LX	205	if (!enable_pmu) {
6ef25aa0 LX	206	memset(&kvm_pmu_cap, 0, sizeof(kvm_pmu_cap));
d7808f73 LX	207	return;
d7808f73 LX	208	}
968635ab LX	209
968635ab LX	210	kvm_pmu_cap.version = min(kvm_pmu_cap.version, 2);
8911ce66 SC	211	kvm_pmu_cap.num_counters_gp = min(kvm_pmu_cap.num_counters_gp,
8911ce66 SC	212	pmu_ops->MAX_NR_GP_COUNTERS);
968635ab LX	213	kvm_pmu_cap.num_counters_fixed = min(kvm_pmu_cap.num_counters_fixed,
	214	KVM_PMC_MAX_FIXED);
	215	}
	216
4fa5843d	217	static inline void kvm_pmu_request_counter_reprogram(struct kvm_pmc *pmc)
68fb4757 LX	218	{
	219	set_bit(pmc->idx, pmc_to_pmu(pmc)->reprogram_pmi);
	220	kvm_make_request(KVM_REQ_PMU, pmc->vcpu);
	221	}
25462f7f	222
8de18543 LX	223	static inline void reprogram_counters(struct kvm_pmu *pmu, u64 diff)
	224	{
	225	int bit;
	226
	227	if (!diff)
	228	return;
	229
	230	for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX)
	231	set_bit(bit, pmu->reprogram_pmi);
	232	kvm_make_request(KVM_REQ_PMU, pmu_to_vcpu(pmu));
	233	}
	234
13afa29a LX	235	/*
	236	* Check if a PMC is enabled by comparing it against global_ctrl bits.
	237	*
	238	* If the vPMU doesn't have global_ctrl MSR, all vPMCs are enabled.
	239	*/
	240	static inline bool pmc_is_globally_enabled(struct kvm_pmc *pmc)
	241	{
	242	struct kvm_pmu *pmu = pmc_to_pmu(pmc);
	243
	244	if (!kvm_pmu_has_perf_global_ctrl(pmu))
	245	return true;
	246
	247	return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl);
	248	}
	249
474a5bb9 WH	250	void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu);
	251	void kvm_pmu_handle_event(struct kvm_vcpu *vcpu);
	252	int kvm_pmu_rdpmc(struct kvm_vcpu vcpu, unsigned pmc, u64 data);
e6cd31f1	253	bool kvm_pmu_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx);
545feb96	254	bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr);
cbd71758	255	int kvm_pmu_get_msr(struct kvm_vcpu vcpu, struct msr_data msr_info);
474a5bb9 WH	256	int kvm_pmu_set_msr(struct kvm_vcpu vcpu, struct msr_data msr_info);
	257	void kvm_pmu_refresh(struct kvm_vcpu *vcpu);
	258	void kvm_pmu_reset(struct kvm_vcpu *vcpu);
	259	void kvm_pmu_init(struct kvm_vcpu *vcpu);
b35e5548	260	void kvm_pmu_cleanup(struct kvm_vcpu *vcpu);
474a5bb9	261	void kvm_pmu_destroy(struct kvm_vcpu *vcpu);
66bb8a06	262	int kvm_vm_ioctl_set_pmu_event_filter(struct kvm kvm, void __user argp);
9cd803d4	263	void kvm_pmu_trigger_event(struct kvm_vcpu *vcpu, u64 perf_hw_id);
474a5bb9	264
2d7921c4 AM	265	bool is_vmware_backdoor_pmc(u32 pmc_idx);
2d7921c4 AM	266
25462f7f WH	267	extern struct kvm_pmu_ops intel_pmu_ops;
25462f7f WH	268	extern struct kvm_pmu_ops amd_pmu_ops;
474a5bb9	269	#endif /* __KVM_X86_PMU_H */