Commit | Line | Data |
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20c8ccb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
6aa8b732 AK |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * This module enables machines with Intel VT-x extensions to run virtual | |
6 | * machines without emulation or binary translation. | |
7 | * | |
8 | * MMU support | |
9 | * | |
10 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 11 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
12 | * |
13 | * Authors: | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
15 | * Avi Kivity <avi@qumranet.com> | |
6aa8b732 AK |
16 | */ |
17 | ||
18 | /* | |
19 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
20 | * so the code in this file is compiled twice, once per pte size. | |
21 | */ | |
22 | ||
23 | #if PTTYPE == 64 | |
24 | #define pt_element_t u64 | |
25 | #define guest_walker guest_walker64 | |
26 | #define FNAME(name) paging##64_##name | |
27 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
28 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
29 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 30 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 31 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
d8089bac GN |
32 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT |
33 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
86407bcb | 34 | #define PT_HAVE_ACCESSED_DIRTY(mmu) true |
cea0f0e7 AK |
35 | #ifdef CONFIG_X86_64 |
36 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 37 | #define CMPXCHG cmpxchg |
cea0f0e7 | 38 | #else |
b3e4e63f | 39 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
40 | #define PT_MAX_FULL_LEVELS 2 |
41 | #endif | |
6aa8b732 AK |
42 | #elif PTTYPE == 32 |
43 | #define pt_element_t u32 | |
44 | #define guest_walker guest_walker32 | |
45 | #define FNAME(name) paging##32_##name | |
46 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
47 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
48 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 49 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 50 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 51 | #define PT_MAX_FULL_LEVELS 2 |
d8089bac GN |
52 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT |
53 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
86407bcb | 54 | #define PT_HAVE_ACCESSED_DIRTY(mmu) true |
b3e4e63f | 55 | #define CMPXCHG cmpxchg |
37406aaa NHE |
56 | #elif PTTYPE == PTTYPE_EPT |
57 | #define pt_element_t u64 | |
58 | #define guest_walker guest_walkerEPT | |
59 | #define FNAME(name) ept_##name | |
60 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
61 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) | |
62 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
63 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
64 | #define PT_LEVEL_BITS PT64_LEVEL_BITS | |
ae1e2d10 PB |
65 | #define PT_GUEST_DIRTY_SHIFT 9 |
66 | #define PT_GUEST_ACCESSED_SHIFT 8 | |
67 | #define PT_HAVE_ACCESSED_DIRTY(mmu) ((mmu)->ept_ad) | |
37406aaa NHE |
68 | #define CMPXCHG cmpxchg64 |
69 | #define PT_MAX_FULL_LEVELS 4 | |
6aa8b732 AK |
70 | #else |
71 | #error Invalid PTTYPE value | |
72 | #endif | |
73 | ||
ae1e2d10 PB |
74 | #define PT_GUEST_DIRTY_MASK (1 << PT_GUEST_DIRTY_SHIFT) |
75 | #define PT_GUEST_ACCESSED_MASK (1 << PT_GUEST_ACCESSED_SHIFT) | |
76 | ||
e04da980 JR |
77 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
78 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 79 | |
6aa8b732 AK |
80 | /* |
81 | * The guest_walker structure emulates the behavior of the hardware page | |
82 | * table walker. | |
83 | */ | |
84 | struct guest_walker { | |
85 | int level; | |
8cbc7069 | 86 | unsigned max_level; |
cea0f0e7 | 87 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 88 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 89 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 90 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
8cbc7069 | 91 | pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS]; |
ba6a3541 | 92 | bool pte_writable[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
93 | unsigned pt_access; |
94 | unsigned pte_access; | |
815af8d4 | 95 | gfn_t gfn; |
8c28d031 | 96 | struct x86_exception fault; |
6aa8b732 AK |
97 | }; |
98 | ||
e04da980 | 99 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 100 | { |
e04da980 | 101 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
102 | } |
103 | ||
86407bcb PB |
104 | static inline void FNAME(protect_clean_gpte)(struct kvm_mmu *mmu, unsigned *access, |
105 | unsigned gpte) | |
0ad805a0 NHE |
106 | { |
107 | unsigned mask; | |
108 | ||
61719a8f | 109 | /* dirty bit is not supported, so no need to track it */ |
86407bcb | 110 | if (!PT_HAVE_ACCESSED_DIRTY(mmu)) |
61719a8f GN |
111 | return; |
112 | ||
0ad805a0 NHE |
113 | BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK); |
114 | ||
115 | mask = (unsigned)~ACC_WRITE_MASK; | |
116 | /* Allow write access to dirty gptes */ | |
d8089bac GN |
117 | mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & |
118 | PT_WRITABLE_MASK; | |
0ad805a0 NHE |
119 | *access &= mask; |
120 | } | |
121 | ||
0ad805a0 NHE |
122 | static inline int FNAME(is_present_gpte)(unsigned long pte) |
123 | { | |
37406aaa | 124 | #if PTTYPE != PTTYPE_EPT |
812f30b2 | 125 | return pte & PT_PRESENT_MASK; |
37406aaa NHE |
126 | #else |
127 | return pte & 7; | |
128 | #endif | |
0ad805a0 NHE |
129 | } |
130 | ||
a78484c6 | 131 | static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
c8cfbb55 TY |
132 | pt_element_t __user *ptep_user, unsigned index, |
133 | pt_element_t orig_pte, pt_element_t new_pte) | |
b3e4e63f | 134 | { |
c8cfbb55 | 135 | int npages; |
b3e4e63f MT |
136 | pt_element_t ret; |
137 | pt_element_t *table; | |
138 | struct page *page; | |
139 | ||
73b0140b | 140 | npages = get_user_pages_fast((unsigned long)ptep_user, 1, FOLL_WRITE, &page); |
bd53cb35 FS |
141 | if (likely(npages == 1)) { |
142 | table = kmap_atomic(page); | |
143 | ret = CMPXCHG(&table[index], orig_pte, new_pte); | |
144 | kunmap_atomic(table); | |
145 | ||
146 | kvm_release_page_dirty(page); | |
147 | } else { | |
148 | struct vm_area_struct *vma; | |
149 | unsigned long vaddr = (unsigned long)ptep_user & PAGE_MASK; | |
150 | unsigned long pfn; | |
151 | unsigned long paddr; | |
152 | ||
153 | down_read(¤t->mm->mmap_sem); | |
154 | vma = find_vma_intersection(current->mm, vaddr, vaddr + PAGE_SIZE); | |
155 | if (!vma || !(vma->vm_flags & VM_PFNMAP)) { | |
156 | up_read(¤t->mm->mmap_sem); | |
157 | return -EFAULT; | |
158 | } | |
159 | pfn = ((vaddr - vma->vm_start) >> PAGE_SHIFT) + vma->vm_pgoff; | |
160 | paddr = pfn << PAGE_SHIFT; | |
161 | table = memremap(paddr, PAGE_SIZE, MEMREMAP_WB); | |
162 | if (!table) { | |
163 | up_read(¤t->mm->mmap_sem); | |
164 | return -EFAULT; | |
165 | } | |
166 | ret = CMPXCHG(&table[index], orig_pte, new_pte); | |
167 | memunmap(table); | |
168 | up_read(¤t->mm->mmap_sem); | |
169 | } | |
b3e4e63f MT |
170 | |
171 | return (ret != orig_pte); | |
172 | } | |
173 | ||
0ad805a0 NHE |
174 | static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu, |
175 | struct kvm_mmu_page *sp, u64 *spte, | |
176 | u64 gpte) | |
177 | { | |
44dd3ffa | 178 | if (is_rsvd_bits_set(vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) |
0ad805a0 NHE |
179 | goto no_present; |
180 | ||
181 | if (!FNAME(is_present_gpte)(gpte)) | |
182 | goto no_present; | |
183 | ||
61719a8f | 184 | /* if accessed bit is not supported prefetch non accessed gpte */ |
44dd3ffa VK |
185 | if (PT_HAVE_ACCESSED_DIRTY(vcpu->arch.mmu) && |
186 | !(gpte & PT_GUEST_ACCESSED_MASK)) | |
0ad805a0 NHE |
187 | goto no_present; |
188 | ||
189 | return false; | |
190 | ||
191 | no_present: | |
192 | drop_spte(vcpu->kvm, spte); | |
193 | return true; | |
194 | } | |
195 | ||
d95c5568 BD |
196 | /* |
197 | * For PTTYPE_EPT, a page table can be executable but not readable | |
198 | * on supported processors. Therefore, set_spte does not automatically | |
199 | * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK | |
200 | * to signify readability since it isn't used in the EPT case | |
201 | */ | |
42522d08 | 202 | static inline unsigned FNAME(gpte_access)(u64 gpte) |
0ad805a0 NHE |
203 | { |
204 | unsigned access; | |
37406aaa NHE |
205 | #if PTTYPE == PTTYPE_EPT |
206 | access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) | | |
207 | ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) | | |
d95c5568 | 208 | ((gpte & VMX_EPT_READABLE_MASK) ? ACC_USER_MASK : 0); |
37406aaa | 209 | #else |
bb9eadf0 PB |
210 | BUILD_BUG_ON(ACC_EXEC_MASK != PT_PRESENT_MASK); |
211 | BUILD_BUG_ON(ACC_EXEC_MASK != 1); | |
212 | access = gpte & (PT_WRITABLE_MASK | PT_USER_MASK | PT_PRESENT_MASK); | |
213 | /* Combine NX with P (which is set here) to get ACC_EXEC_MASK. */ | |
214 | access ^= (gpte >> PT64_NX_SHIFT); | |
37406aaa | 215 | #endif |
0ad805a0 NHE |
216 | |
217 | return access; | |
218 | } | |
219 | ||
8cbc7069 AK |
220 | static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu, |
221 | struct kvm_mmu *mmu, | |
222 | struct guest_walker *walker, | |
223 | int write_fault) | |
224 | { | |
225 | unsigned level, index; | |
226 | pt_element_t pte, orig_pte; | |
227 | pt_element_t __user *ptep_user; | |
228 | gfn_t table_gfn; | |
229 | int ret; | |
230 | ||
61719a8f | 231 | /* dirty/accessed bits are not supported, so no need to update them */ |
86407bcb | 232 | if (!PT_HAVE_ACCESSED_DIRTY(mmu)) |
61719a8f GN |
233 | return 0; |
234 | ||
8cbc7069 AK |
235 | for (level = walker->max_level; level >= walker->level; --level) { |
236 | pte = orig_pte = walker->ptes[level - 1]; | |
237 | table_gfn = walker->table_gfn[level - 1]; | |
238 | ptep_user = walker->ptep_user[level - 1]; | |
239 | index = offset_in_page(ptep_user) / sizeof(pt_element_t); | |
d8089bac | 240 | if (!(pte & PT_GUEST_ACCESSED_MASK)) { |
8cbc7069 | 241 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte)); |
d8089bac | 242 | pte |= PT_GUEST_ACCESSED_MASK; |
8cbc7069 | 243 | } |
0ad805a0 | 244 | if (level == walker->level && write_fault && |
d8089bac | 245 | !(pte & PT_GUEST_DIRTY_MASK)) { |
8cbc7069 | 246 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
bab4165e BD |
247 | #if PTTYPE == PTTYPE_EPT |
248 | if (kvm_arch_write_log_dirty(vcpu)) | |
249 | return -EINVAL; | |
250 | #endif | |
d8089bac | 251 | pte |= PT_GUEST_DIRTY_MASK; |
8cbc7069 AK |
252 | } |
253 | if (pte == orig_pte) | |
254 | continue; | |
255 | ||
ba6a3541 PB |
256 | /* |
257 | * If the slot is read-only, simply do not process the accessed | |
258 | * and dirty bits. This is the correct thing to do if the slot | |
259 | * is ROM, and page tables in read-as-ROM/write-as-MMIO slots | |
260 | * are only supported if the accessed and dirty bits are already | |
261 | * set in the ROM (so that MMIO writes are never needed). | |
262 | * | |
263 | * Note that NPT does not allow this at all and faults, since | |
264 | * it always wants nested page table entries for the guest | |
265 | * page tables to be writable. And EPT works but will simply | |
266 | * overwrite the read-only memory to set the accessed and dirty | |
267 | * bits. | |
268 | */ | |
269 | if (unlikely(!walker->pte_writable[level - 1])) | |
270 | continue; | |
271 | ||
8cbc7069 AK |
272 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte); |
273 | if (ret) | |
274 | return ret; | |
275 | ||
54bf36aa | 276 | kvm_vcpu_mark_page_dirty(vcpu, table_gfn); |
17e4bce0 | 277 | walker->ptes[level - 1] = pte; |
8cbc7069 AK |
278 | } |
279 | return 0; | |
280 | } | |
281 | ||
be94f6b7 HH |
282 | static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte) |
283 | { | |
284 | unsigned pkeys = 0; | |
285 | #if PTTYPE == 64 | |
286 | pte_t pte = {.pte = gpte}; | |
287 | ||
288 | pkeys = pte_flags_pkey(pte_flags(pte)); | |
289 | #endif | |
290 | return pkeys; | |
291 | } | |
292 | ||
ac79c978 AK |
293 | /* |
294 | * Fetch a guest pte for a guest virtual address | |
295 | */ | |
1e301feb JR |
296 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
297 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
33770780 | 298 | gva_t addr, u32 access) |
6aa8b732 | 299 | { |
8cbc7069 | 300 | int ret; |
42bf3f0a | 301 | pt_element_t pte; |
b7233635 | 302 | pt_element_t __user *uninitialized_var(ptep_user); |
cea0f0e7 | 303 | gfn_t table_gfn; |
0780516a PB |
304 | u64 pt_access, pte_access; |
305 | unsigned index, accessed_dirty, pte_pkey; | |
ae1e2d10 | 306 | unsigned nested_access; |
42bf3f0a | 307 | gpa_t pte_gpa; |
86407bcb | 308 | bool have_ad; |
134291bf | 309 | int offset; |
0780516a | 310 | u64 walk_nx_mask = 0; |
134291bf TY |
311 | const int write_fault = access & PFERR_WRITE_MASK; |
312 | const int user_fault = access & PFERR_USER_MASK; | |
313 | const int fetch_fault = access & PFERR_FETCH_MASK; | |
314 | u16 errcode = 0; | |
13d22b6a AK |
315 | gpa_t real_gpa; |
316 | gfn_t gfn; | |
6aa8b732 | 317 | |
6fbc2770 | 318 | trace_kvm_mmu_pagetable_walk(addr, access); |
92c1c1e8 | 319 | retry_walk: |
1e301feb JR |
320 | walker->level = mmu->root_level; |
321 | pte = mmu->get_cr3(vcpu); | |
86407bcb | 322 | have_ad = PT_HAVE_ACCESSED_DIRTY(mmu); |
1e301feb | 323 | |
1b0973bd | 324 | #if PTTYPE == 64 |
0780516a | 325 | walk_nx_mask = 1ULL << PT64_NX_SHIFT; |
1e301feb | 326 | if (walker->level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 327 | pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3); |
07420171 | 328 | trace_kvm_mmu_paging_element(pte, walker->level); |
0ad805a0 | 329 | if (!FNAME(is_present_gpte)(pte)) |
f59c1d2d | 330 | goto error; |
1b0973bd AK |
331 | --walker->level; |
332 | } | |
333 | #endif | |
8cbc7069 | 334 | walker->max_level = walker->level; |
1715d0dc | 335 | ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu))); |
6aa8b732 | 336 | |
ae1e2d10 PB |
337 | /* |
338 | * FIXME: on Intel processors, loads of the PDPTE registers for PAE paging | |
339 | * by the MOV to CR instruction are treated as reads and do not cause the | |
340 | * processor to set the dirty flag in any EPT paging-structure entry. | |
341 | */ | |
342 | nested_access = (have_ad ? PFERR_WRITE_MASK : 0) | PFERR_USER_MASK; | |
343 | ||
0780516a | 344 | pte_access = ~0; |
13d22b6a | 345 | ++walker->level; |
ac79c978 | 346 | |
13d22b6a | 347 | do { |
6e2ca7d1 TY |
348 | gfn_t real_gfn; |
349 | unsigned long host_addr; | |
350 | ||
0780516a | 351 | pt_access = pte_access; |
13d22b6a AK |
352 | --walker->level; |
353 | ||
42bf3f0a | 354 | index = PT_INDEX(addr, walker->level); |
5fb07ddb | 355 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
356 | offset = index * sizeof(pt_element_t); |
357 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
829ee279 LP |
358 | |
359 | BUG_ON(walker->level < 1); | |
42bf3f0a | 360 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 361 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 362 | |
6e2ca7d1 | 363 | real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn), |
ae1e2d10 | 364 | nested_access, |
54987b7a | 365 | &walker->fault); |
5e352519 PB |
366 | |
367 | /* | |
368 | * FIXME: This can happen if emulation (for of an INS/OUTS | |
369 | * instruction) triggers a nested page fault. The exit | |
370 | * qualification / exit info field will incorrectly have | |
371 | * "guest page access" as the nested page fault's cause, | |
372 | * instead of "guest page structure access". To fix this, | |
373 | * the x86_exception struct should be augmented with enough | |
374 | * information to fix the exit_qualification or exit_info_1 | |
375 | * fields. | |
376 | */ | |
134291bf | 377 | if (unlikely(real_gfn == UNMAPPED_GVA)) |
54987b7a | 378 | return 0; |
5e352519 | 379 | |
6e2ca7d1 TY |
380 | real_gfn = gpa_to_gfn(real_gfn); |
381 | ||
54bf36aa | 382 | host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, real_gfn, |
ba6a3541 | 383 | &walker->pte_writable[walker->level - 1]); |
134291bf TY |
384 | if (unlikely(kvm_is_error_hva(host_addr))) |
385 | goto error; | |
6e2ca7d1 TY |
386 | |
387 | ptep_user = (pt_element_t __user *)((void *)host_addr + offset); | |
134291bf TY |
388 | if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte)))) |
389 | goto error; | |
8cbc7069 | 390 | walker->ptep_user[walker->level - 1] = ptep_user; |
a6085fba | 391 | |
07420171 | 392 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 393 | |
0780516a PB |
394 | /* |
395 | * Inverting the NX it lets us AND it like other | |
396 | * permission bits. | |
397 | */ | |
398 | pte_access = pt_access & (pte ^ walk_nx_mask); | |
399 | ||
0ad805a0 | 400 | if (unlikely(!FNAME(is_present_gpte)(pte))) |
134291bf | 401 | goto error; |
7993ba43 | 402 | |
d2b0f981 | 403 | if (unlikely(is_rsvd_bits_set(mmu, pte, walker->level))) { |
7a98205d | 404 | errcode = PFERR_RSVD_MASK | PFERR_PRESENT_MASK; |
134291bf | 405 | goto error; |
f59c1d2d | 406 | } |
82725b20 | 407 | |
7819026e | 408 | walker->ptes[walker->level - 1] = pte; |
6fd01b71 | 409 | } while (!is_last_gpte(mmu, walker->level, pte)); |
42bf3f0a | 410 | |
be94f6b7 | 411 | pte_pkey = FNAME(gpte_pkeys)(vcpu, pte); |
0780516a PB |
412 | accessed_dirty = have_ad ? pte_access & PT_GUEST_ACCESSED_MASK : 0; |
413 | ||
414 | /* Convert to ACC_*_MASK flags for struct guest_walker. */ | |
42522d08 PX |
415 | walker->pt_access = FNAME(gpte_access)(pt_access ^ walk_nx_mask); |
416 | walker->pte_access = FNAME(gpte_access)(pte_access ^ walk_nx_mask); | |
0780516a | 417 | errcode = permission_fault(vcpu, mmu, walker->pte_access, pte_pkey, access); |
f13577e8 | 418 | if (unlikely(errcode)) |
f59c1d2d AK |
419 | goto error; |
420 | ||
13d22b6a AK |
421 | gfn = gpte_to_gfn_lvl(pte, walker->level); |
422 | gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT; | |
423 | ||
424 | if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36()) | |
425 | gfn += pse36_gfn_delta(pte); | |
426 | ||
54987b7a | 427 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault); |
13d22b6a AK |
428 | if (real_gpa == UNMAPPED_GVA) |
429 | return 0; | |
430 | ||
431 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
432 | ||
8ea667f2 | 433 | if (!write_fault) |
0780516a | 434 | FNAME(protect_clean_gpte)(mmu, &walker->pte_access, pte); |
908e7d79 GN |
435 | else |
436 | /* | |
61719a8f GN |
437 | * On a write fault, fold the dirty bit into accessed_dirty. |
438 | * For modes without A/D bits support accessed_dirty will be | |
439 | * always clear. | |
908e7d79 | 440 | */ |
d8089bac GN |
441 | accessed_dirty &= pte >> |
442 | (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT); | |
b514c30f AK |
443 | |
444 | if (unlikely(!accessed_dirty)) { | |
445 | ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault); | |
446 | if (unlikely(ret < 0)) | |
447 | goto error; | |
448 | else if (ret) | |
449 | goto retry_walk; | |
450 | } | |
42bf3f0a | 451 | |
fe135d2c | 452 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", |
0780516a | 453 | __func__, (u64)pte, walker->pte_access, walker->pt_access); |
7993ba43 AK |
454 | return 1; |
455 | ||
f59c1d2d | 456 | error: |
134291bf | 457 | errcode |= write_fault | user_fault; |
e57d4a35 YW |
458 | if (fetch_fault && (mmu->nx || |
459 | kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))) | |
134291bf | 460 | errcode |= PFERR_FETCH_MASK; |
8df25a32 | 461 | |
134291bf TY |
462 | walker->fault.vector = PF_VECTOR; |
463 | walker->fault.error_code_valid = true; | |
464 | walker->fault.error_code = errcode; | |
25d92081 YZ |
465 | |
466 | #if PTTYPE == PTTYPE_EPT | |
467 | /* | |
468 | * Use PFERR_RSVD_MASK in error_code to to tell if EPT | |
469 | * misconfiguration requires to be injected. The detection is | |
470 | * done by is_rsvd_bits_set() above. | |
471 | * | |
472 | * We set up the value of exit_qualification to inject: | |
ddd6f0e9 KA |
473 | * [2:0] - Derive from the access bits. The exit_qualification might be |
474 | * out of date if it is serving an EPT misconfiguration. | |
25d92081 YZ |
475 | * [5:3] - Calculated by the page walk of the guest EPT page tables |
476 | * [7:8] - Derived from [7:8] of real exit_qualification | |
477 | * | |
478 | * The other bits are set to 0. | |
479 | */ | |
480 | if (!(errcode & PFERR_RSVD_MASK)) { | |
ddd6f0e9 KA |
481 | vcpu->arch.exit_qualification &= 0x180; |
482 | if (write_fault) | |
483 | vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_WRITE; | |
484 | if (user_fault) | |
485 | vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_READ; | |
486 | if (fetch_fault) | |
487 | vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_INSTR; | |
0780516a | 488 | vcpu->arch.exit_qualification |= (pte_access & 0x7) << 3; |
25d92081 YZ |
489 | } |
490 | #endif | |
6389ee94 AK |
491 | walker->fault.address = addr; |
492 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 493 | |
8c28d031 | 494 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 495 | return 0; |
6aa8b732 AK |
496 | } |
497 | ||
1e301feb | 498 | static int FNAME(walk_addr)(struct guest_walker *walker, |
33770780 | 499 | struct kvm_vcpu *vcpu, gva_t addr, u32 access) |
1e301feb | 500 | { |
44dd3ffa | 501 | return FNAME(walk_addr_generic)(walker, vcpu, vcpu->arch.mmu, addr, |
33770780 | 502 | access); |
1e301feb JR |
503 | } |
504 | ||
37406aaa | 505 | #if PTTYPE != PTTYPE_EPT |
6539e738 JR |
506 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
507 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 508 | u32 access) |
6539e738 JR |
509 | { |
510 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 511 | addr, access); |
6539e738 | 512 | } |
37406aaa | 513 | #endif |
6539e738 | 514 | |
bd6360cc XG |
515 | static bool |
516 | FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
517 | u64 *spte, pt_element_t gpte, bool no_dirty_log) | |
0028425f | 518 | { |
41074d07 | 519 | unsigned pte_access; |
bd6360cc | 520 | gfn_t gfn; |
ba049e93 | 521 | kvm_pfn_t pfn; |
0028425f | 522 | |
0ad805a0 | 523 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
bd6360cc | 524 | return false; |
407c61c6 | 525 | |
b8688d51 | 526 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
bd6360cc XG |
527 | |
528 | gfn = gpte_to_gfn(gpte); | |
42522d08 | 529 | pte_access = sp->role.access & FNAME(gpte_access)(gpte); |
44dd3ffa | 530 | FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte); |
bd6360cc XG |
531 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, |
532 | no_dirty_log && (pte_access & ACC_WRITE_MASK)); | |
81c52c56 | 533 | if (is_error_pfn(pfn)) |
bd6360cc | 534 | return false; |
0f53b5b1 | 535 | |
1403283a | 536 | /* |
bd6360cc XG |
537 | * we call mmu_set_spte() with host_writable = true because |
538 | * pte_prefetch_gfn_to_pfn always gets a writable pfn. | |
1403283a | 539 | */ |
029499b4 TY |
540 | mmu_set_spte(vcpu, spte, pte_access, 0, PT_PAGE_TABLE_LEVEL, gfn, pfn, |
541 | true, true); | |
bd6360cc | 542 | |
43fdcda9 | 543 | kvm_release_pfn_clean(pfn); |
bd6360cc XG |
544 | return true; |
545 | } | |
546 | ||
547 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
548 | u64 *spte, const void *pte) | |
549 | { | |
550 | pt_element_t gpte = *(const pt_element_t *)pte; | |
551 | ||
552 | FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false); | |
0028425f AK |
553 | } |
554 | ||
39c8c672 AK |
555 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
556 | struct guest_walker *gw, int level) | |
557 | { | |
39c8c672 | 558 | pt_element_t curr_pte; |
189be38d XG |
559 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
560 | u64 mask; | |
561 | int r, index; | |
562 | ||
563 | if (level == PT_PAGE_TABLE_LEVEL) { | |
564 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
565 | base_gpa = pte_gpa & ~mask; | |
566 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
567 | ||
54bf36aa | 568 | r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa, |
189be38d XG |
569 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); |
570 | curr_pte = gw->prefetch_ptes[index]; | |
571 | } else | |
54bf36aa | 572 | r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, |
39c8c672 | 573 | &curr_pte, sizeof(curr_pte)); |
189be38d | 574 | |
39c8c672 AK |
575 | return r || curr_pte != gw->ptes[level - 1]; |
576 | } | |
577 | ||
189be38d XG |
578 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
579 | u64 *sptep) | |
957ed9ef XG |
580 | { |
581 | struct kvm_mmu_page *sp; | |
189be38d | 582 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 583 | u64 *spte; |
189be38d | 584 | int i; |
957ed9ef XG |
585 | |
586 | sp = page_header(__pa(sptep)); | |
587 | ||
588 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
589 | return; | |
590 | ||
591 | if (sp->role.direct) | |
592 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
593 | ||
594 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
595 | spte = sp->spt + i; |
596 | ||
597 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
957ed9ef XG |
598 | if (spte == sptep) |
599 | continue; | |
600 | ||
c3707958 | 601 | if (is_shadow_present_pte(*spte)) |
957ed9ef XG |
602 | continue; |
603 | ||
bd6360cc | 604 | if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true)) |
957ed9ef | 605 | break; |
957ed9ef XG |
606 | } |
607 | } | |
608 | ||
6aa8b732 AK |
609 | /* |
610 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
d4878f24 XG |
611 | * If the guest tries to write a write-protected page, we need to |
612 | * emulate this operation, return 1 to indicate this case. | |
6aa8b732 | 613 | */ |
d4878f24 | 614 | static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
e7a04c99 | 615 | struct guest_walker *gw, |
c2288505 | 616 | int write_fault, int hlevel, |
b8e8c830 PB |
617 | kvm_pfn_t pfn, bool map_writable, bool prefault, |
618 | bool lpage_disallowed) | |
6aa8b732 | 619 | { |
5991b332 | 620 | struct kvm_mmu_page *sp = NULL; |
24157aaf | 621 | struct kvm_shadow_walk_iterator it; |
d4878f24 | 622 | unsigned direct_access, access = gw->pt_access; |
9b8ebbdb | 623 | int top_level, ret; |
b8e8c830 | 624 | gfn_t gfn, base_gfn; |
abb9e0b8 | 625 | |
b36c7a7c | 626 | direct_access = gw->pte_access; |
84754cd8 | 627 | |
44dd3ffa | 628 | top_level = vcpu->arch.mmu->root_level; |
5991b332 AK |
629 | if (top_level == PT32E_ROOT_LEVEL) |
630 | top_level = PT32_ROOT_LEVEL; | |
631 | /* | |
632 | * Verify that the top-level gpte is still there. Since the page | |
633 | * is a root page, it is either write protected (and cannot be | |
634 | * changed from now on) or it is invalid (in which case, we don't | |
635 | * really care if it changes underneath us after this point). | |
636 | */ | |
637 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
638 | goto out_gpte_changed; | |
639 | ||
44dd3ffa | 640 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
37f6a4e2 MT |
641 | goto out_gpte_changed; |
642 | ||
24157aaf AK |
643 | for (shadow_walk_init(&it, vcpu, addr); |
644 | shadow_walk_okay(&it) && it.level > gw->level; | |
645 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
646 | gfn_t table_gfn; |
647 | ||
a30f47cb | 648 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 649 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 650 | |
5991b332 | 651 | sp = NULL; |
24157aaf AK |
652 | if (!is_shadow_present_pte(*it.sptep)) { |
653 | table_gfn = gw->table_gfn[it.level - 2]; | |
654 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
bb11c6c9 | 655 | false, access); |
5991b332 | 656 | } |
0b3c9333 AK |
657 | |
658 | /* | |
659 | * Verify that the gpte in the page we've just write | |
660 | * protected is still there. | |
661 | */ | |
24157aaf | 662 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 663 | goto out_gpte_changed; |
abb9e0b8 | 664 | |
5991b332 | 665 | if (sp) |
98bba238 | 666 | link_shadow_page(vcpu, it.sptep, sp); |
e7a04c99 | 667 | } |
050e6499 | 668 | |
b8e8c830 PB |
669 | /* |
670 | * FNAME(page_fault) might have clobbered the bottom bits of | |
671 | * gw->gfn, restore them from the virtual address. | |
672 | */ | |
673 | gfn = gw->gfn | ((addr & PT_LVL_OFFSET_MASK(gw->level)) >> PAGE_SHIFT); | |
674 | base_gfn = gfn; | |
0b3c9333 | 675 | |
335e192a PB |
676 | trace_kvm_mmu_spte_requested(addr, gw->level, pfn); |
677 | ||
3fcf2d1b | 678 | for (; shadow_walk_okay(&it); shadow_walk_next(&it)) { |
a30f47cb | 679 | clear_sp_write_flooding_count(it.sptep); |
b8e8c830 PB |
680 | |
681 | /* | |
682 | * We cannot overwrite existing page tables with an NX | |
683 | * large page, as the leaf could be executable. | |
684 | */ | |
685 | disallowed_hugepage_adjust(it, gfn, &pfn, &hlevel); | |
686 | ||
687 | base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); | |
3fcf2d1b PB |
688 | if (it.level == hlevel) |
689 | break; | |
690 | ||
24157aaf | 691 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 692 | |
24157aaf | 693 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 694 | |
3fcf2d1b PB |
695 | if (!is_shadow_present_pte(*it.sptep)) { |
696 | sp = kvm_mmu_get_page(vcpu, base_gfn, addr, | |
697 | it.level - 1, true, direct_access); | |
698 | link_shadow_page(vcpu, it.sptep, sp); | |
b8e8c830 PB |
699 | if (lpage_disallowed) |
700 | account_huge_nx_page(vcpu->kvm, sp); | |
3fcf2d1b | 701 | } |
0b3c9333 AK |
702 | } |
703 | ||
9b8ebbdb | 704 | ret = mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault, |
3fcf2d1b | 705 | it.level, base_gfn, pfn, prefault, map_writable); |
189be38d | 706 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
3fcf2d1b | 707 | ++vcpu->stat.pf_fixed; |
9b8ebbdb | 708 | return ret; |
0b3c9333 AK |
709 | |
710 | out_gpte_changed: | |
9b8ebbdb | 711 | return RET_PF_RETRY; |
6aa8b732 AK |
712 | } |
713 | ||
7751babd XG |
714 | /* |
715 | * To see whether the mapped gfn can write its page table in the current | |
716 | * mapping. | |
717 | * | |
718 | * It is the helper function of FNAME(page_fault). When guest uses large page | |
719 | * size to map the writable gfn which is used as current page table, we should | |
720 | * force kvm to use small page size to map it because new shadow page will be | |
721 | * created when kvm establishes shadow page table that stop kvm using large | |
722 | * page size. Do it early can avoid unnecessary #PF and emulation. | |
723 | * | |
93c05d3e XG |
724 | * @write_fault_to_shadow_pgtable will return true if the fault gfn is |
725 | * currently used as its page table. | |
726 | * | |
7751babd XG |
727 | * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok |
728 | * since the PDPT is always shadowed, that means, we can not use large page | |
729 | * size to map the gfn which is used as PDPT. | |
730 | */ | |
731 | static bool | |
732 | FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu, | |
93c05d3e XG |
733 | struct guest_walker *walker, int user_fault, |
734 | bool *write_fault_to_shadow_pgtable) | |
7751babd XG |
735 | { |
736 | int level; | |
737 | gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1); | |
93c05d3e | 738 | bool self_changed = false; |
7751babd XG |
739 | |
740 | if (!(walker->pte_access & ACC_WRITE_MASK || | |
741 | (!is_write_protection(vcpu) && !user_fault))) | |
742 | return false; | |
743 | ||
93c05d3e XG |
744 | for (level = walker->level; level <= walker->max_level; level++) { |
745 | gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1]; | |
746 | ||
747 | self_changed |= !(gfn & mask); | |
748 | *write_fault_to_shadow_pgtable |= !gfn; | |
749 | } | |
7751babd | 750 | |
93c05d3e | 751 | return self_changed; |
7751babd XG |
752 | } |
753 | ||
6aa8b732 AK |
754 | /* |
755 | * Page fault handler. There are several causes for a page fault: | |
756 | * - there is no shadow pte for the guest pte | |
757 | * - write access through a shadow pte marked read only so that we can set | |
758 | * the dirty bit | |
759 | * - write access to a shadow pte marked read only so we can update the page | |
760 | * dirty bitmap, when userspace requests it | |
761 | * - mmio access; in this case we will never install a present shadow pte | |
762 | * - normal guest page fault due to the guest pte marked not present, not | |
763 | * writable, or not executable | |
764 | * | |
e2dec939 AK |
765 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
766 | * a negative value on error. | |
6aa8b732 | 767 | */ |
56028d08 | 768 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code, |
78b2c54a | 769 | bool prefault) |
6aa8b732 AK |
770 | { |
771 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
772 | int user_fault = error_code & PFERR_USER_MASK; |
773 | struct guest_walker walker; | |
e2dec939 | 774 | int r; |
ba049e93 | 775 | kvm_pfn_t pfn; |
7e4e4056 | 776 | int level = PT_PAGE_TABLE_LEVEL; |
e930bffe | 777 | unsigned long mmu_seq; |
93c05d3e | 778 | bool map_writable, is_self_change_mapping; |
b8e8c830 PB |
779 | bool lpage_disallowed = (error_code & PFERR_FETCH_MASK) && |
780 | is_nx_huge_page_enabled(); | |
781 | bool force_pt_level = lpage_disallowed; | |
6aa8b732 | 782 | |
b8688d51 | 783 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 784 | |
e2dec939 AK |
785 | r = mmu_topup_memory_caches(vcpu); |
786 | if (r) | |
787 | return r; | |
714b93da | 788 | |
e9ee956e TY |
789 | /* |
790 | * If PFEC.RSVD is set, this is a shadow page fault. | |
791 | * The bit needs to be cleared before walking guest page tables. | |
792 | */ | |
793 | error_code &= ~PFERR_RSVD_MASK; | |
794 | ||
6aa8b732 | 795 | /* |
a8b876b1 | 796 | * Look up the guest pte for the faulting address. |
6aa8b732 | 797 | */ |
33770780 | 798 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
799 | |
800 | /* | |
801 | * The page is not mapped by the guest. Let the guest handle it. | |
802 | */ | |
7993ba43 | 803 | if (!r) { |
b8688d51 | 804 | pgprintk("%s: guest page fault\n", __func__); |
a30f47cb | 805 | if (!prefault) |
fb67e14f | 806 | inject_page_fault(vcpu, &walker.fault); |
a30f47cb | 807 | |
9b8ebbdb | 808 | return RET_PF_RETRY; |
6aa8b732 AK |
809 | } |
810 | ||
e5691a81 XG |
811 | if (page_fault_handle_page_track(vcpu, error_code, walker.gfn)) { |
812 | shadow_page_table_clear_flood(vcpu, addr); | |
9b8ebbdb | 813 | return RET_PF_EMULATE; |
e5691a81 | 814 | } |
3d0c27ad | 815 | |
93c05d3e XG |
816 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
817 | ||
818 | is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu, | |
819 | &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable); | |
820 | ||
5ed5c5c8 | 821 | if (walker.level >= PT_DIRECTORY_LEVEL && !is_self_change_mapping) { |
fd136902 TY |
822 | level = mapping_level(vcpu, walker.gfn, &force_pt_level); |
823 | if (likely(!force_pt_level)) { | |
824 | level = min(walker.level, level); | |
5ed5c5c8 TY |
825 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); |
826 | } | |
827 | } else | |
cd1872f0 | 828 | force_pt_level = true; |
7e4e4056 | 829 | |
e930bffe | 830 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 831 | smp_rmb(); |
af585b92 | 832 | |
78b2c54a | 833 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 834 | &map_writable)) |
9b8ebbdb | 835 | return RET_PF_RETRY; |
d7824fff | 836 | |
9034e6e8 | 837 | if (handle_abnormal_pfn(vcpu, addr, walker.gfn, pfn, walker.pte_access, &r)) |
d7c55201 XG |
838 | return r; |
839 | ||
c2288505 XG |
840 | /* |
841 | * Do not change pte_access if the pfn is a mmio page, otherwise | |
842 | * we will cache the incorrect access into mmio spte. | |
843 | */ | |
844 | if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) && | |
845 | !is_write_protection(vcpu) && !user_fault && | |
846 | !is_noslot_pfn(pfn)) { | |
847 | walker.pte_access |= ACC_WRITE_MASK; | |
848 | walker.pte_access &= ~ACC_USER_MASK; | |
849 | ||
850 | /* | |
851 | * If we converted a user page to a kernel page, | |
852 | * so that the kernel can write to it when cr0.wp=0, | |
853 | * then we should prevent the kernel from executing it | |
854 | * if SMEP is enabled. | |
855 | */ | |
856 | if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)) | |
857 | walker.pte_access &= ~ACC_EXEC_MASK; | |
858 | } | |
859 | ||
43fdcda9 | 860 | r = RET_PF_RETRY; |
aaee2c94 | 861 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 862 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 863 | goto out_unlock; |
bc32ce21 | 864 | |
0375f7fa | 865 | kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
26eeb53c WL |
866 | if (make_mmu_pages_available(vcpu) < 0) |
867 | goto out_unlock; | |
936a5fe6 | 868 | if (!force_pt_level) |
d679b326 | 869 | transparent_hugepage_adjust(vcpu, walker.gfn, &pfn, &level); |
c2288505 | 870 | r = FNAME(fetch)(vcpu, addr, &walker, write_fault, |
b8e8c830 | 871 | level, pfn, map_writable, prefault, lpage_disallowed); |
0375f7fa | 872 | kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
e930bffe AA |
873 | |
874 | out_unlock: | |
875 | spin_unlock(&vcpu->kvm->mmu_lock); | |
876 | kvm_release_pfn_clean(pfn); | |
43fdcda9 | 877 | return r; |
6aa8b732 AK |
878 | } |
879 | ||
505aef8f XG |
880 | static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp) |
881 | { | |
882 | int offset = 0; | |
883 | ||
f71fa31f | 884 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
505aef8f XG |
885 | |
886 | if (PTTYPE == 32) | |
887 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
888 | ||
889 | return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); | |
890 | } | |
891 | ||
7eb77e9f | 892 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa) |
a7052897 | 893 | { |
a461930b | 894 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 895 | struct kvm_mmu_page *sp; |
a461930b AK |
896 | int level; |
897 | u64 *sptep; | |
898 | ||
bebb106a XG |
899 | vcpu_clear_mmio_info(vcpu, gva); |
900 | ||
f57f2ef5 XG |
901 | /* |
902 | * No need to check return value here, rmap_can_add() can | |
903 | * help us to skip pte prefetch later. | |
904 | */ | |
905 | mmu_topup_memory_caches(vcpu); | |
a7052897 | 906 | |
7eb77e9f | 907 | if (!VALID_PAGE(root_hpa)) { |
37f6a4e2 MT |
908 | WARN_ON(1); |
909 | return; | |
910 | } | |
911 | ||
f57f2ef5 | 912 | spin_lock(&vcpu->kvm->mmu_lock); |
7eb77e9f | 913 | for_each_shadow_entry_using_root(vcpu, root_hpa, gva, iterator) { |
a461930b AK |
914 | level = iterator.level; |
915 | sptep = iterator.sptep; | |
ad218f85 | 916 | |
f78978aa | 917 | sp = page_header(__pa(sptep)); |
884a0ff0 | 918 | if (is_last_spte(*sptep, level)) { |
f57f2ef5 XG |
919 | pt_element_t gpte; |
920 | gpa_t pte_gpa; | |
921 | ||
f78978aa XG |
922 | if (!sp->unsync) |
923 | break; | |
924 | ||
505aef8f | 925 | pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
08e850c6 | 926 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b | 927 | |
505aef8f | 928 | if (mmu_page_zap_pte(vcpu->kvm, sp, sptep)) |
c3134ce2 LT |
929 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, |
930 | sp->gfn, KVM_PAGES_PER_HPAGE(sp->role.level)); | |
f57f2ef5 XG |
931 | |
932 | if (!rmap_can_add(vcpu)) | |
933 | break; | |
934 | ||
54bf36aa PB |
935 | if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte, |
936 | sizeof(pt_element_t))) | |
f57f2ef5 XG |
937 | break; |
938 | ||
939 | FNAME(update_pte)(vcpu, sp, sptep, &gpte); | |
87917239 | 940 | } |
a7052897 | 941 | |
f78978aa | 942 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
943 | break; |
944 | } | |
ad218f85 | 945 | spin_unlock(&vcpu->kvm->mmu_lock); |
a7052897 MT |
946 | } |
947 | ||
1871c602 | 948 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
ab9ae313 | 949 | struct x86_exception *exception) |
6aa8b732 AK |
950 | { |
951 | struct guest_walker walker; | |
e119d117 AK |
952 | gpa_t gpa = UNMAPPED_GVA; |
953 | int r; | |
6aa8b732 | 954 | |
33770780 | 955 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, access); |
6aa8b732 | 956 | |
e119d117 | 957 | if (r) { |
1755fbcc | 958 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 959 | gpa |= vaddr & ~PAGE_MASK; |
8c28d031 AK |
960 | } else if (exception) |
961 | *exception = walker.fault; | |
6aa8b732 AK |
962 | |
963 | return gpa; | |
964 | } | |
965 | ||
37406aaa | 966 | #if PTTYPE != PTTYPE_EPT |
6539e738 | 967 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
968 | u32 access, |
969 | struct x86_exception *exception) | |
6539e738 JR |
970 | { |
971 | struct guest_walker walker; | |
972 | gpa_t gpa = UNMAPPED_GVA; | |
973 | int r; | |
974 | ||
33770780 | 975 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
976 | |
977 | if (r) { | |
978 | gpa = gfn_to_gpa(walker.gfn); | |
979 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
980 | } else if (exception) |
981 | *exception = walker.fault; | |
6539e738 JR |
982 | |
983 | return gpa; | |
984 | } | |
37406aaa | 985 | #endif |
6539e738 | 986 | |
e8bc217a MT |
987 | /* |
988 | * Using the cached information from sp->gfns is safe because: | |
989 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
990 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
991 | * |
992 | * Note: | |
993 | * We should flush all tlbs if spte is dropped even though guest is | |
994 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
995 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
996 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
997 | * freed pages. | |
a086f6a1 | 998 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. |
e8bc217a | 999 | */ |
a4a8e6f7 | 1000 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a | 1001 | { |
505aef8f | 1002 | int i, nr_present = 0; |
9bdbba13 | 1003 | bool host_writable; |
51fb60d8 | 1004 | gpa_t first_pte_gpa; |
5ce4786f | 1005 | int set_spte_ret = 0; |
e8bc217a | 1006 | |
2032a93d LJ |
1007 | /* direct kvm_mmu_page can not be unsync. */ |
1008 | BUG_ON(sp->role.direct); | |
1009 | ||
505aef8f | 1010 | first_pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
51fb60d8 | 1011 | |
e8bc217a MT |
1012 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
1013 | unsigned pte_access; | |
1014 | pt_element_t gpte; | |
1015 | gpa_t pte_gpa; | |
f55c3f41 | 1016 | gfn_t gfn; |
e8bc217a | 1017 | |
ce88decf | 1018 | if (!sp->spt[i]) |
e8bc217a MT |
1019 | continue; |
1020 | ||
51fb60d8 | 1021 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a | 1022 | |
54bf36aa PB |
1023 | if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte, |
1024 | sizeof(pt_element_t))) | |
1f50f1b3 | 1025 | return 0; |
e8bc217a | 1026 | |
0ad805a0 | 1027 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { |
7bfdf217 LT |
1028 | /* |
1029 | * Update spte before increasing tlbs_dirty to make | |
1030 | * sure no tlb flush is lost after spte is zapped; see | |
1031 | * the comments in kvm_flush_remote_tlbs(). | |
1032 | */ | |
1033 | smp_wmb(); | |
a086f6a1 | 1034 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
1035 | continue; |
1036 | } | |
1037 | ||
ce88decf XG |
1038 | gfn = gpte_to_gfn(gpte); |
1039 | pte_access = sp->role.access; | |
42522d08 | 1040 | pte_access &= FNAME(gpte_access)(gpte); |
44dd3ffa | 1041 | FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte); |
ce88decf | 1042 | |
54bf36aa | 1043 | if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access, |
f2fd125d | 1044 | &nr_present)) |
ce88decf XG |
1045 | continue; |
1046 | ||
407c61c6 | 1047 | if (gfn != sp->gfns[i]) { |
c3707958 | 1048 | drop_spte(vcpu->kvm, &sp->spt[i]); |
7bfdf217 LT |
1049 | /* |
1050 | * The same as above where we are doing | |
1051 | * prefetch_invalid_gpte(). | |
1052 | */ | |
1053 | smp_wmb(); | |
a086f6a1 | 1054 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
1055 | continue; |
1056 | } | |
1057 | ||
1058 | nr_present++; | |
ce88decf | 1059 | |
f8e453b0 XG |
1060 | host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE; |
1061 | ||
5ce4786f JS |
1062 | set_spte_ret |= set_spte(vcpu, &sp->spt[i], |
1063 | pte_access, PT_PAGE_TABLE_LEVEL, | |
1064 | gfn, spte_to_pfn(sp->spt[i]), | |
1065 | true, false, host_writable); | |
e8bc217a MT |
1066 | } |
1067 | ||
5ce4786f JS |
1068 | if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH) |
1069 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1070 | ||
1f50f1b3 | 1071 | return nr_present; |
e8bc217a MT |
1072 | } |
1073 | ||
6aa8b732 AK |
1074 | #undef pt_element_t |
1075 | #undef guest_walker | |
1076 | #undef FNAME | |
1077 | #undef PT_BASE_ADDR_MASK | |
1078 | #undef PT_INDEX | |
e04da980 JR |
1079 | #undef PT_LVL_ADDR_MASK |
1080 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 1081 | #undef PT_LEVEL_BITS |
cea0f0e7 | 1082 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 1083 | #undef gpte_to_gfn |
e04da980 | 1084 | #undef gpte_to_gfn_lvl |
b3e4e63f | 1085 | #undef CMPXCHG |
d8089bac GN |
1086 | #undef PT_GUEST_ACCESSED_MASK |
1087 | #undef PT_GUEST_DIRTY_MASK | |
1088 | #undef PT_GUEST_DIRTY_SHIFT | |
1089 | #undef PT_GUEST_ACCESSED_SHIFT | |
86407bcb | 1090 | #undef PT_HAVE_ACCESSED_DIRTY |