Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
10 | * | |
11 | * Authors: | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * | |
15 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
16 | * the COPYING file in the top-level directory. | |
17 | * | |
18 | */ | |
19 | ||
20 | /* | |
21 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
22 | * so the code in this file is compiled twice, once per pte size. | |
23 | */ | |
24 | ||
25 | #if PTTYPE == 64 | |
26 | #define pt_element_t u64 | |
27 | #define guest_walker guest_walker64 | |
abb9e0b8 | 28 | #define shadow_walker shadow_walker64 |
6aa8b732 AK |
29 | #define FNAME(name) paging##64_##name |
30 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
31 | #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK | |
32 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
6aa8b732 | 33 | #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level) |
c7addb90 | 34 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
cea0f0e7 AK |
35 | #ifdef CONFIG_X86_64 |
36 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 37 | #define CMPXCHG cmpxchg |
cea0f0e7 | 38 | #else |
b3e4e63f | 39 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
40 | #define PT_MAX_FULL_LEVELS 2 |
41 | #endif | |
6aa8b732 AK |
42 | #elif PTTYPE == 32 |
43 | #define pt_element_t u32 | |
44 | #define guest_walker guest_walker32 | |
abb9e0b8 | 45 | #define shadow_walker shadow_walker32 |
6aa8b732 AK |
46 | #define FNAME(name) paging##32_##name |
47 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
48 | #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK | |
49 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) | |
6aa8b732 | 50 | #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level) |
c7addb90 | 51 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 52 | #define PT_MAX_FULL_LEVELS 2 |
b3e4e63f | 53 | #define CMPXCHG cmpxchg |
6aa8b732 AK |
54 | #else |
55 | #error Invalid PTTYPE value | |
56 | #endif | |
57 | ||
5fb07ddb AK |
58 | #define gpte_to_gfn FNAME(gpte_to_gfn) |
59 | #define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde) | |
60 | ||
6aa8b732 AK |
61 | /* |
62 | * The guest_walker structure emulates the behavior of the hardware page | |
63 | * table walker. | |
64 | */ | |
65 | struct guest_walker { | |
66 | int level; | |
cea0f0e7 | 67 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e MT |
68 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
69 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; | |
fe135d2c AK |
70 | unsigned pt_access; |
71 | unsigned pte_access; | |
815af8d4 | 72 | gfn_t gfn; |
7993ba43 | 73 | u32 error_code; |
6aa8b732 AK |
74 | }; |
75 | ||
abb9e0b8 AK |
76 | struct shadow_walker { |
77 | struct kvm_shadow_walk walker; | |
78 | struct guest_walker *guest_walker; | |
79 | int user_fault; | |
80 | int write_fault; | |
81 | int largepage; | |
82 | int *ptwrite; | |
83 | pfn_t pfn; | |
84 | u64 *sptep; | |
ad218f85 | 85 | gpa_t pte_gpa; |
abb9e0b8 AK |
86 | }; |
87 | ||
5fb07ddb AK |
88 | static gfn_t gpte_to_gfn(pt_element_t gpte) |
89 | { | |
90 | return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT; | |
91 | } | |
92 | ||
93 | static gfn_t gpte_to_gfn_pde(pt_element_t gpte) | |
94 | { | |
95 | return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT; | |
96 | } | |
97 | ||
b3e4e63f MT |
98 | static bool FNAME(cmpxchg_gpte)(struct kvm *kvm, |
99 | gfn_t table_gfn, unsigned index, | |
100 | pt_element_t orig_pte, pt_element_t new_pte) | |
101 | { | |
102 | pt_element_t ret; | |
103 | pt_element_t *table; | |
104 | struct page *page; | |
105 | ||
106 | page = gfn_to_page(kvm, table_gfn); | |
72dc67a6 | 107 | |
b3e4e63f | 108 | table = kmap_atomic(page, KM_USER0); |
b3e4e63f | 109 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
b3e4e63f MT |
110 | kunmap_atomic(table, KM_USER0); |
111 | ||
112 | kvm_release_page_dirty(page); | |
113 | ||
114 | return (ret != orig_pte); | |
115 | } | |
116 | ||
bedbe4ee AK |
117 | static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte) |
118 | { | |
119 | unsigned access; | |
120 | ||
121 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; | |
122 | #if PTTYPE == 64 | |
123 | if (is_nx(vcpu)) | |
124 | access &= ~(gpte >> PT64_NX_SHIFT); | |
125 | #endif | |
126 | return access; | |
127 | } | |
128 | ||
ac79c978 AK |
129 | /* |
130 | * Fetch a guest pte for a guest virtual address | |
131 | */ | |
7993ba43 AK |
132 | static int FNAME(walk_addr)(struct guest_walker *walker, |
133 | struct kvm_vcpu *vcpu, gva_t addr, | |
73b1087e | 134 | int write_fault, int user_fault, int fetch_fault) |
6aa8b732 | 135 | { |
42bf3f0a | 136 | pt_element_t pte; |
cea0f0e7 | 137 | gfn_t table_gfn; |
fe135d2c | 138 | unsigned index, pt_access, pte_access; |
42bf3f0a | 139 | gpa_t pte_gpa; |
6aa8b732 | 140 | |
b8688d51 | 141 | pgprintk("%s: addr %lx\n", __func__, addr); |
b3e4e63f | 142 | walk: |
ad312c7c ZX |
143 | walker->level = vcpu->arch.mmu.root_level; |
144 | pte = vcpu->arch.cr3; | |
1b0973bd AK |
145 | #if PTTYPE == 64 |
146 | if (!is_long_mode(vcpu)) { | |
ad312c7c | 147 | pte = vcpu->arch.pdptrs[(addr >> 30) & 3]; |
42bf3f0a | 148 | if (!is_present_pte(pte)) |
7993ba43 | 149 | goto not_present; |
1b0973bd AK |
150 | --walker->level; |
151 | } | |
152 | #endif | |
a9058ecd | 153 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
24993d53 | 154 | (vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 155 | |
fe135d2c | 156 | pt_access = ACC_ALL; |
ac79c978 AK |
157 | |
158 | for (;;) { | |
42bf3f0a | 159 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 160 | |
5fb07ddb | 161 | table_gfn = gpte_to_gfn(pte); |
1755fbcc | 162 | pte_gpa = gfn_to_gpa(table_gfn); |
ec8d4eae | 163 | pte_gpa += index * sizeof(pt_element_t); |
42bf3f0a | 164 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 165 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
b8688d51 | 166 | pgprintk("%s: table_gfn[%d] %lx\n", __func__, |
42bf3f0a AK |
167 | walker->level - 1, table_gfn); |
168 | ||
ec8d4eae | 169 | kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte)); |
42bf3f0a AK |
170 | |
171 | if (!is_present_pte(pte)) | |
7993ba43 AK |
172 | goto not_present; |
173 | ||
42bf3f0a | 174 | if (write_fault && !is_writeble_pte(pte)) |
7993ba43 AK |
175 | if (user_fault || is_write_protection(vcpu)) |
176 | goto access_error; | |
177 | ||
42bf3f0a | 178 | if (user_fault && !(pte & PT_USER_MASK)) |
7993ba43 AK |
179 | goto access_error; |
180 | ||
73b1087e | 181 | #if PTTYPE == 64 |
42bf3f0a | 182 | if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK)) |
73b1087e AK |
183 | goto access_error; |
184 | #endif | |
185 | ||
42bf3f0a | 186 | if (!(pte & PT_ACCESSED_MASK)) { |
bf3f8e86 | 187 | mark_page_dirty(vcpu->kvm, table_gfn); |
b3e4e63f MT |
188 | if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, |
189 | index, pte, pte|PT_ACCESSED_MASK)) | |
190 | goto walk; | |
42bf3f0a | 191 | pte |= PT_ACCESSED_MASK; |
bf3f8e86 | 192 | } |
815af8d4 | 193 | |
bedbe4ee | 194 | pte_access = pt_access & FNAME(gpte_access)(vcpu, pte); |
fe135d2c | 195 | |
7819026e MT |
196 | walker->ptes[walker->level - 1] = pte; |
197 | ||
815af8d4 | 198 | if (walker->level == PT_PAGE_TABLE_LEVEL) { |
5fb07ddb | 199 | walker->gfn = gpte_to_gfn(pte); |
815af8d4 AK |
200 | break; |
201 | } | |
202 | ||
203 | if (walker->level == PT_DIRECTORY_LEVEL | |
42bf3f0a | 204 | && (pte & PT_PAGE_SIZE_MASK) |
815af8d4 | 205 | && (PTTYPE == 64 || is_pse(vcpu))) { |
5fb07ddb | 206 | walker->gfn = gpte_to_gfn_pde(pte); |
815af8d4 | 207 | walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL); |
da928521 AK |
208 | if (PTTYPE == 32 && is_cpuid_PSE36()) |
209 | walker->gfn += pse36_gfn_delta(pte); | |
ac79c978 | 210 | break; |
815af8d4 | 211 | } |
ac79c978 | 212 | |
fe135d2c | 213 | pt_access = pte_access; |
ac79c978 AK |
214 | --walker->level; |
215 | } | |
42bf3f0a AK |
216 | |
217 | if (write_fault && !is_dirty_pte(pte)) { | |
b3e4e63f MT |
218 | bool ret; |
219 | ||
42bf3f0a | 220 | mark_page_dirty(vcpu->kvm, table_gfn); |
b3e4e63f MT |
221 | ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte, |
222 | pte|PT_DIRTY_MASK); | |
223 | if (ret) | |
224 | goto walk; | |
42bf3f0a | 225 | pte |= PT_DIRTY_MASK; |
ad218f85 | 226 | kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte), 0); |
7819026e | 227 | walker->ptes[walker->level - 1] = pte; |
42bf3f0a AK |
228 | } |
229 | ||
fe135d2c AK |
230 | walker->pt_access = pt_access; |
231 | walker->pte_access = pte_access; | |
232 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
b8688d51 | 233 | __func__, (u64)pte, pt_access, pte_access); |
7993ba43 AK |
234 | return 1; |
235 | ||
236 | not_present: | |
237 | walker->error_code = 0; | |
238 | goto err; | |
239 | ||
240 | access_error: | |
241 | walker->error_code = PFERR_PRESENT_MASK; | |
242 | ||
243 | err: | |
244 | if (write_fault) | |
245 | walker->error_code |= PFERR_WRITE_MASK; | |
246 | if (user_fault) | |
247 | walker->error_code |= PFERR_USER_MASK; | |
73b1087e AK |
248 | if (fetch_fault) |
249 | walker->error_code |= PFERR_FETCH_MASK; | |
fe551881 | 250 | return 0; |
6aa8b732 AK |
251 | } |
252 | ||
0028425f | 253 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page, |
489f1d65 | 254 | u64 *spte, const void *pte) |
0028425f AK |
255 | { |
256 | pt_element_t gpte; | |
41074d07 | 257 | unsigned pte_access; |
35149e21 | 258 | pfn_t pfn; |
05da4558 | 259 | int largepage = vcpu->arch.update_pte.largepage; |
0028425f | 260 | |
0028425f | 261 | gpte = *(const pt_element_t *)pte; |
c7addb90 | 262 | if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) { |
489f1d65 | 263 | if (!is_present_pte(gpte)) |
c7addb90 AK |
264 | set_shadow_pte(spte, shadow_notrap_nonpresent_pte); |
265 | return; | |
266 | } | |
b8688d51 | 267 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
41074d07 | 268 | pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte); |
d7824fff AK |
269 | if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn) |
270 | return; | |
35149e21 AL |
271 | pfn = vcpu->arch.update_pte.pfn; |
272 | if (is_error_pfn(pfn)) | |
d7824fff | 273 | return; |
e930bffe AA |
274 | if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq)) |
275 | return; | |
35149e21 | 276 | kvm_get_pfn(pfn); |
1c4f1fd6 | 277 | mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0, |
6cffe8ca MT |
278 | gpte & PT_DIRTY_MASK, NULL, largepage, |
279 | gpte & PT_GLOBAL_MASK, gpte_to_gfn(gpte), | |
35149e21 | 280 | pfn, true); |
0028425f AK |
281 | } |
282 | ||
6aa8b732 AK |
283 | /* |
284 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
285 | */ | |
abb9e0b8 | 286 | static int FNAME(shadow_walk_entry)(struct kvm_shadow_walk *_sw, |
d40a1ee4 | 287 | struct kvm_vcpu *vcpu, u64 addr, |
abb9e0b8 | 288 | u64 *sptep, int level) |
6aa8b732 | 289 | { |
abb9e0b8 AK |
290 | struct shadow_walker *sw = |
291 | container_of(_sw, struct shadow_walker, walker); | |
292 | struct guest_walker *gw = sw->guest_walker; | |
293 | unsigned access = gw->pt_access; | |
294 | struct kvm_mmu_page *shadow_page; | |
295 | u64 spte; | |
296 | int metaphysical; | |
297 | gfn_t table_gfn; | |
298 | int r; | |
299 | pt_element_t curr_pte; | |
300 | ||
301 | if (level == PT_PAGE_TABLE_LEVEL | |
302 | || (sw->largepage && level == PT_DIRECTORY_LEVEL)) { | |
303 | mmu_set_spte(vcpu, sptep, access, gw->pte_access & access, | |
304 | sw->user_fault, sw->write_fault, | |
305 | gw->ptes[gw->level-1] & PT_DIRTY_MASK, | |
6cffe8ca MT |
306 | sw->ptwrite, sw->largepage, |
307 | gw->ptes[gw->level-1] & PT_GLOBAL_MASK, | |
308 | gw->gfn, sw->pfn, false); | |
abb9e0b8 AK |
309 | sw->sptep = sptep; |
310 | return 1; | |
aef3d3fe | 311 | } |
6aa8b732 | 312 | |
abb9e0b8 AK |
313 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) |
314 | return 0; | |
6aa8b732 | 315 | |
93a423e7 MT |
316 | if (is_large_pte(*sptep)) { |
317 | set_shadow_pte(sptep, shadow_trap_nonpresent_pte); | |
318 | kvm_flush_remote_tlbs(vcpu->kvm); | |
abb9e0b8 | 319 | rmap_remove(vcpu->kvm, sptep); |
93a423e7 | 320 | } |
abb9e0b8 AK |
321 | |
322 | if (level == PT_DIRECTORY_LEVEL && gw->level == PT_DIRECTORY_LEVEL) { | |
323 | metaphysical = 1; | |
324 | if (!is_dirty_pte(gw->ptes[level - 1])) | |
325 | access &= ~ACC_WRITE_MASK; | |
326 | table_gfn = gpte_to_gfn(gw->ptes[level - 1]); | |
327 | } else { | |
328 | metaphysical = 0; | |
329 | table_gfn = gw->table_gfn[level - 2]; | |
330 | } | |
d40a1ee4 | 331 | shadow_page = kvm_mmu_get_page(vcpu, table_gfn, (gva_t)addr, level-1, |
abb9e0b8 AK |
332 | metaphysical, access, sptep); |
333 | if (!metaphysical) { | |
334 | r = kvm_read_guest_atomic(vcpu->kvm, gw->pte_gpa[level - 2], | |
335 | &curr_pte, sizeof(curr_pte)); | |
336 | if (r || curr_pte != gw->ptes[level - 2]) { | |
6c475352 | 337 | kvm_mmu_put_page(shadow_page, sptep); |
abb9e0b8 AK |
338 | kvm_release_pfn_clean(sw->pfn); |
339 | sw->sptep = NULL; | |
340 | return 1; | |
7819026e | 341 | } |
6aa8b732 | 342 | } |
ef0197e8 | 343 | |
abb9e0b8 AK |
344 | spte = __pa(shadow_page->spt) | PT_PRESENT_MASK | PT_ACCESSED_MASK |
345 | | PT_WRITABLE_MASK | PT_USER_MASK; | |
346 | *sptep = spte; | |
347 | return 0; | |
348 | } | |
349 | ||
350 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, | |
351 | struct guest_walker *guest_walker, | |
352 | int user_fault, int write_fault, int largepage, | |
353 | int *ptwrite, pfn_t pfn) | |
354 | { | |
355 | struct shadow_walker walker = { | |
356 | .walker = { .entry = FNAME(shadow_walk_entry), }, | |
357 | .guest_walker = guest_walker, | |
358 | .user_fault = user_fault, | |
359 | .write_fault = write_fault, | |
360 | .largepage = largepage, | |
361 | .ptwrite = ptwrite, | |
362 | .pfn = pfn, | |
363 | }; | |
364 | ||
365 | if (!is_present_pte(guest_walker->ptes[guest_walker->level - 1])) | |
366 | return NULL; | |
367 | ||
368 | walk_shadow(&walker.walker, vcpu, addr); | |
050e6499 | 369 | |
abb9e0b8 | 370 | return walker.sptep; |
6aa8b732 AK |
371 | } |
372 | ||
6aa8b732 AK |
373 | /* |
374 | * Page fault handler. There are several causes for a page fault: | |
375 | * - there is no shadow pte for the guest pte | |
376 | * - write access through a shadow pte marked read only so that we can set | |
377 | * the dirty bit | |
378 | * - write access to a shadow pte marked read only so we can update the page | |
379 | * dirty bitmap, when userspace requests it | |
380 | * - mmio access; in this case we will never install a present shadow pte | |
381 | * - normal guest page fault due to the guest pte marked not present, not | |
382 | * writable, or not executable | |
383 | * | |
e2dec939 AK |
384 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
385 | * a negative value on error. | |
6aa8b732 AK |
386 | */ |
387 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, | |
388 | u32 error_code) | |
389 | { | |
390 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 | 391 | int user_fault = error_code & PFERR_USER_MASK; |
73b1087e | 392 | int fetch_fault = error_code & PFERR_FETCH_MASK; |
6aa8b732 AK |
393 | struct guest_walker walker; |
394 | u64 *shadow_pte; | |
cea0f0e7 | 395 | int write_pt = 0; |
e2dec939 | 396 | int r; |
35149e21 | 397 | pfn_t pfn; |
05da4558 | 398 | int largepage = 0; |
e930bffe | 399 | unsigned long mmu_seq; |
6aa8b732 | 400 | |
b8688d51 | 401 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
37a7d8b0 | 402 | kvm_mmu_audit(vcpu, "pre page fault"); |
714b93da | 403 | |
e2dec939 AK |
404 | r = mmu_topup_memory_caches(vcpu); |
405 | if (r) | |
406 | return r; | |
714b93da | 407 | |
6aa8b732 AK |
408 | /* |
409 | * Look up the shadow pte for the faulting address. | |
410 | */ | |
73b1087e AK |
411 | r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault, |
412 | fetch_fault); | |
6aa8b732 AK |
413 | |
414 | /* | |
415 | * The page is not mapped by the guest. Let the guest handle it. | |
416 | */ | |
7993ba43 | 417 | if (!r) { |
b8688d51 | 418 | pgprintk("%s: guest page fault\n", __func__); |
7993ba43 | 419 | inject_page_fault(vcpu, addr, walker.error_code); |
ad312c7c | 420 | vcpu->arch.last_pt_write_count = 0; /* reset fork detector */ |
6aa8b732 AK |
421 | return 0; |
422 | } | |
423 | ||
05da4558 MT |
424 | if (walker.level == PT_DIRECTORY_LEVEL) { |
425 | gfn_t large_gfn; | |
426 | large_gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE-1); | |
427 | if (is_largepage_backed(vcpu, large_gfn)) { | |
428 | walker.gfn = large_gfn; | |
429 | largepage = 1; | |
430 | } | |
431 | } | |
e930bffe | 432 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 433 | smp_rmb(); |
35149e21 | 434 | pfn = gfn_to_pfn(vcpu->kvm, walker.gfn); |
d7824fff | 435 | |
d196e343 | 436 | /* mmio */ |
35149e21 | 437 | if (is_error_pfn(pfn)) { |
ebb0e626 | 438 | pgprintk("gfn %lx is mmio\n", walker.gfn); |
35149e21 | 439 | kvm_release_pfn_clean(pfn); |
d196e343 AK |
440 | return 1; |
441 | } | |
442 | ||
aaee2c94 | 443 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
444 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
445 | goto out_unlock; | |
eb787d10 | 446 | kvm_mmu_free_some_pages(vcpu); |
97a0a01e | 447 | shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault, |
35149e21 | 448 | largepage, &write_pt, pfn); |
05da4558 | 449 | |
b8688d51 | 450 | pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__, |
97a0a01e | 451 | shadow_pte, *shadow_pte, write_pt); |
cea0f0e7 | 452 | |
a25f7e1f | 453 | if (!write_pt) |
ad312c7c | 454 | vcpu->arch.last_pt_write_count = 0; /* reset fork detector */ |
a25f7e1f | 455 | |
1165f5fe | 456 | ++vcpu->stat.pf_fixed; |
37a7d8b0 | 457 | kvm_mmu_audit(vcpu, "post page fault (fixed)"); |
aaee2c94 | 458 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 459 | |
cea0f0e7 | 460 | return write_pt; |
e930bffe AA |
461 | |
462 | out_unlock: | |
463 | spin_unlock(&vcpu->kvm->mmu_lock); | |
464 | kvm_release_pfn_clean(pfn); | |
465 | return 0; | |
6aa8b732 AK |
466 | } |
467 | ||
a7052897 MT |
468 | static int FNAME(shadow_invlpg_entry)(struct kvm_shadow_walk *_sw, |
469 | struct kvm_vcpu *vcpu, u64 addr, | |
470 | u64 *sptep, int level) | |
471 | { | |
ad218f85 MT |
472 | struct shadow_walker *sw = |
473 | container_of(_sw, struct shadow_walker, walker); | |
a7052897 | 474 | |
87917239 MT |
475 | /* FIXME: properly handle invlpg on large guest pages */ |
476 | if (level == PT_PAGE_TABLE_LEVEL || | |
477 | ((level == PT_DIRECTORY_LEVEL) && is_large_pte(*sptep))) { | |
ad218f85 MT |
478 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); |
479 | ||
480 | sw->pte_gpa = (sp->gfn << PAGE_SHIFT); | |
481 | sw->pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); | |
482 | ||
87917239 | 483 | if (is_shadow_present_pte(*sptep)) { |
a7052897 | 484 | rmap_remove(vcpu->kvm, sptep); |
87917239 MT |
485 | if (is_large_pte(*sptep)) |
486 | --vcpu->kvm->stat.lpages; | |
487 | } | |
a7052897 MT |
488 | set_shadow_pte(sptep, shadow_trap_nonpresent_pte); |
489 | return 1; | |
490 | } | |
491 | if (!is_shadow_present_pte(*sptep)) | |
492 | return 1; | |
493 | return 0; | |
494 | } | |
495 | ||
496 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) | |
497 | { | |
ad218f85 | 498 | pt_element_t gpte; |
a7052897 MT |
499 | struct shadow_walker walker = { |
500 | .walker = { .entry = FNAME(shadow_invlpg_entry), }, | |
ad218f85 | 501 | .pte_gpa = -1, |
a7052897 MT |
502 | }; |
503 | ||
ad218f85 | 504 | spin_lock(&vcpu->kvm->mmu_lock); |
a7052897 | 505 | walk_shadow(&walker.walker, vcpu, gva); |
ad218f85 MT |
506 | spin_unlock(&vcpu->kvm->mmu_lock); |
507 | if (walker.pte_gpa == -1) | |
508 | return; | |
509 | if (kvm_read_guest_atomic(vcpu->kvm, walker.pte_gpa, &gpte, | |
510 | sizeof(pt_element_t))) | |
511 | return; | |
512 | if (is_present_pte(gpte) && (gpte & PT_ACCESSED_MASK)) { | |
513 | if (mmu_topup_memory_caches(vcpu)) | |
514 | return; | |
515 | kvm_mmu_pte_write(vcpu, walker.pte_gpa, (const u8 *)&gpte, | |
516 | sizeof(pt_element_t), 0); | |
517 | } | |
a7052897 MT |
518 | } |
519 | ||
6aa8b732 AK |
520 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr) |
521 | { | |
522 | struct guest_walker walker; | |
e119d117 AK |
523 | gpa_t gpa = UNMAPPED_GVA; |
524 | int r; | |
6aa8b732 | 525 | |
e119d117 | 526 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0); |
6aa8b732 | 527 | |
e119d117 | 528 | if (r) { |
1755fbcc | 529 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 530 | gpa |= vaddr & ~PAGE_MASK; |
6aa8b732 AK |
531 | } |
532 | ||
533 | return gpa; | |
534 | } | |
535 | ||
c7addb90 AK |
536 | static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu, |
537 | struct kvm_mmu_page *sp) | |
538 | { | |
eab9f71f AK |
539 | int i, j, offset, r; |
540 | pt_element_t pt[256 / sizeof(pt_element_t)]; | |
541 | gpa_t pte_gpa; | |
c7addb90 | 542 | |
e5a4c8ca AK |
543 | if (sp->role.metaphysical |
544 | || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) { | |
c7addb90 AK |
545 | nonpaging_prefetch_page(vcpu, sp); |
546 | return; | |
547 | } | |
548 | ||
eab9f71f AK |
549 | pte_gpa = gfn_to_gpa(sp->gfn); |
550 | if (PTTYPE == 32) { | |
e5a4c8ca | 551 | offset = sp->role.quadrant << PT64_LEVEL_BITS; |
eab9f71f AK |
552 | pte_gpa += offset * sizeof(pt_element_t); |
553 | } | |
7ec54588 | 554 | |
eab9f71f AK |
555 | for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) { |
556 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt); | |
557 | pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t); | |
558 | for (j = 0; j < ARRAY_SIZE(pt); ++j) | |
559 | if (r || is_present_pte(pt[j])) | |
560 | sp->spt[i+j] = shadow_trap_nonpresent_pte; | |
561 | else | |
562 | sp->spt[i+j] = shadow_notrap_nonpresent_pte; | |
7ec54588 | 563 | } |
c7addb90 AK |
564 | } |
565 | ||
e8bc217a MT |
566 | /* |
567 | * Using the cached information from sp->gfns is safe because: | |
568 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
569 | * can't change unless all sptes pointing to it are nuked first. | |
570 | * - Alias changes zap the entire shadow cache. | |
571 | */ | |
572 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) | |
573 | { | |
574 | int i, offset, nr_present; | |
575 | ||
576 | offset = nr_present = 0; | |
577 | ||
578 | if (PTTYPE == 32) | |
579 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
580 | ||
581 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { | |
582 | unsigned pte_access; | |
583 | pt_element_t gpte; | |
584 | gpa_t pte_gpa; | |
585 | gfn_t gfn = sp->gfns[i]; | |
586 | ||
587 | if (!is_shadow_present_pte(sp->spt[i])) | |
588 | continue; | |
589 | ||
590 | pte_gpa = gfn_to_gpa(sp->gfn); | |
591 | pte_gpa += (i+offset) * sizeof(pt_element_t); | |
592 | ||
593 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
594 | sizeof(pt_element_t))) | |
595 | return -EINVAL; | |
596 | ||
597 | if (gpte_to_gfn(gpte) != gfn || !is_present_pte(gpte) || | |
598 | !(gpte & PT_ACCESSED_MASK)) { | |
599 | u64 nonpresent; | |
600 | ||
601 | rmap_remove(vcpu->kvm, &sp->spt[i]); | |
602 | if (is_present_pte(gpte)) | |
603 | nonpresent = shadow_trap_nonpresent_pte; | |
604 | else | |
605 | nonpresent = shadow_notrap_nonpresent_pte; | |
606 | set_shadow_pte(&sp->spt[i], nonpresent); | |
607 | continue; | |
608 | } | |
609 | ||
610 | nr_present++; | |
611 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); | |
612 | set_spte(vcpu, &sp->spt[i], pte_access, 0, 0, | |
6cffe8ca | 613 | is_dirty_pte(gpte), 0, gpte & PT_GLOBAL_MASK, gfn, |
4731d4c7 | 614 | spte_to_pfn(sp->spt[i]), true, false); |
e8bc217a MT |
615 | } |
616 | ||
617 | return !nr_present; | |
618 | } | |
619 | ||
6aa8b732 AK |
620 | #undef pt_element_t |
621 | #undef guest_walker | |
abb9e0b8 | 622 | #undef shadow_walker |
6aa8b732 AK |
623 | #undef FNAME |
624 | #undef PT_BASE_ADDR_MASK | |
625 | #undef PT_INDEX | |
6aa8b732 | 626 | #undef PT_LEVEL_MASK |
6aa8b732 | 627 | #undef PT_DIR_BASE_ADDR_MASK |
c7addb90 | 628 | #undef PT_LEVEL_BITS |
cea0f0e7 | 629 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb AK |
630 | #undef gpte_to_gfn |
631 | #undef gpte_to_gfn_pde | |
b3e4e63f | 632 | #undef CMPXCHG |