[linux-2.6-block.git] / arch / x86 / kvm / paging_tmpl.h

/*
 * Kernel-based Virtual Machine driver for Linux
 *
 * This module enables machines with Intel VT-x extensions to run virtual
 * machines without emulation or binary translation.
 *
 * MMU support
 *
 * Copyright (C) 2006 Qumranet, Inc.
 *
 * Authors:
 *   Yaniv Kamay  <yaniv@qumranet.com>
 *   Avi Kivity   <avi@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 */

/*
 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
 * so the code in this file is compiled twice, once per pte size.
 */

#if PTTYPE == 64
	#define pt_element_t u64
	#define guest_walker guest_walker64
	#define FNAME(name) paging##64_##name
	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
	#define PT_LEVEL_BITS PT64_LEVEL_BITS
	#ifdef CONFIG_X86_64
	#define PT_MAX_FULL_LEVELS 4
	#define CMPXCHG cmpxchg
	#else
	#define CMPXCHG cmpxchg64
	#define PT_MAX_FULL_LEVELS 2
	#endif
#elif PTTYPE == 32
	#define pt_element_t u32
	#define guest_walker guest_walker32
	#define FNAME(name) paging##32_##name
	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
	#define PT_LEVEL_BITS PT32_LEVEL_BITS
	#define PT_MAX_FULL_LEVELS 2
	#define CMPXCHG cmpxchg
#else
	#error Invalid PTTYPE value
#endif

#define gpte_to_gfn FNAME(gpte_to_gfn)
#define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde)

/*
 * The guest_walker structure emulates the behavior of the hardware page
 * table walker.
 */
struct guest_walker {
	int level;
	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
	pt_element_t ptes[PT_MAX_FULL_LEVELS];
	gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
	unsigned pt_access;
	unsigned pte_access;
	gfn_t gfn;
	u32 error_code;
};

static gfn_t gpte_to_gfn(pt_element_t gpte)
{
	return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
}

static gfn_t gpte_to_gfn_pde(pt_element_t gpte)
{
	return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
}

static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
			 gfn_t table_gfn, unsigned index,
			 pt_element_t orig_pte, pt_element_t new_pte)
{
	pt_element_t ret;
	pt_element_t *table;
	struct page *page;

	page = gfn_to_page(kvm, table_gfn);
	table = kmap_atomic(page, KM_USER0);

	ret = CMPXCHG(&table[index], orig_pte, new_pte);

	kunmap_atomic(table, KM_USER0);

	kvm_release_page_dirty(page);

	return (ret != orig_pte);
}

static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
{
	unsigned access;

	access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
#if PTTYPE == 64
	if (is_nx(vcpu))
		access &= ~(gpte >> PT64_NX_SHIFT);
#endif
	return access;
}

/*
 * Fetch a guest pte for a guest virtual address
 */
static int FNAME(walk_addr)(struct guest_walker *walker,
			    struct kvm_vcpu *vcpu, gva_t addr,
			    int write_fault, int user_fault, int fetch_fault)
{
	pt_element_t pte;
	gfn_t table_gfn;
	unsigned index, pt_access, pte_access;
	gpa_t pte_gpa;

	pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
walk:
	walker->level = vcpu->arch.mmu.root_level;
	pte = vcpu->arch.cr3;
#if PTTYPE == 64
	if (!is_long_mode(vcpu)) {
		pte = vcpu->arch.pdptrs[(addr >> 30) & 3];
		if (!is_present_pte(pte))
			goto not_present;
		--walker->level;
	}
#endif
	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
	       (vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0);

	pt_access = ACC_ALL;

	for (;;) {
		index = PT_INDEX(addr, walker->level);

		table_gfn = gpte_to_gfn(pte);
		pte_gpa = gfn_to_gpa(table_gfn);
		pte_gpa += index * sizeof(pt_element_t);
		walker->table_gfn[walker->level - 1] = table_gfn;
		walker->pte_gpa[walker->level - 1] = pte_gpa;
		pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
			 walker->level - 1, table_gfn);

		kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));

		if (!is_present_pte(pte))
			goto not_present;

		if (write_fault && !is_writeble_pte(pte))
			if (user_fault || is_write_protection(vcpu))
				goto access_error;

		if (user_fault && !(pte & PT_USER_MASK))
			goto access_error;

#if PTTYPE == 64
		if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
			goto access_error;
#endif

		if (!(pte & PT_ACCESSED_MASK)) {
			mark_page_dirty(vcpu->kvm, table_gfn);
			if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
			    index, pte, pte|PT_ACCESSED_MASK))
				goto walk;
			pte |= PT_ACCESSED_MASK;
		}

		pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);

		walker->ptes[walker->level - 1] = pte;

		if (walker->level == PT_PAGE_TABLE_LEVEL) {
			walker->gfn = gpte_to_gfn(pte);
			break;
		}

		if (walker->level == PT_DIRECTORY_LEVEL
		    && (pte & PT_PAGE_SIZE_MASK)
		    && (PTTYPE == 64 || is_pse(vcpu))) {
			walker->gfn = gpte_to_gfn_pde(pte);
			walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
			if (PTTYPE == 32 && is_cpuid_PSE36())
				walker->gfn += pse36_gfn_delta(pte);
			break;
		}

		pt_access = pte_access;
		--walker->level;
	}

	if (write_fault && !is_dirty_pte(pte)) {
		bool ret;

		mark_page_dirty(vcpu->kvm, table_gfn);
		ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
			    pte|PT_DIRTY_MASK);
		if (ret)
			goto walk;
		pte |= PT_DIRTY_MASK;
		kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte));
		walker->ptes[walker->level - 1] = pte;
	}

	walker->pt_access = pt_access;
	walker->pte_access = pte_access;
	pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
		 __FUNCTION__, (u64)pte, pt_access, pte_access);
	return 1;

not_present:
	walker->error_code = 0;
	goto err;

access_error:
	walker->error_code = PFERR_PRESENT_MASK;

err:
	if (write_fault)
		walker->error_code |= PFERR_WRITE_MASK;
	if (user_fault)
		walker->error_code |= PFERR_USER_MASK;
	if (fetch_fault)
		walker->error_code |= PFERR_FETCH_MASK;
	return 0;
}

static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
			      u64 *spte, const void *pte, int bytes,
			      int offset_in_pte)
{
	pt_element_t gpte;
	unsigned pte_access;

	gpte = *(const pt_element_t *)pte;
	if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
		if (!offset_in_pte && !is_present_pte(gpte))
			set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
		return;
	}
	if (bytes < sizeof(pt_element_t))
		return;
	pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
	pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte);
	mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
		     gpte & PT_DIRTY_MASK, NULL, gpte_to_gfn(gpte));
}

/*
 * Fetch a shadow pte for a specific level in the paging hierarchy.
 */
static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
			 struct guest_walker *walker,
			 int user_fault, int write_fault, int *ptwrite)
{
	hpa_t shadow_addr;
	int level;
	u64 *shadow_ent;
	unsigned access = walker->pt_access;

	if (!is_present_pte(walker->ptes[walker->level - 1]))
		return NULL;

	shadow_addr = vcpu->arch.mmu.root_hpa;
	level = vcpu->arch.mmu.shadow_root_level;
	if (level == PT32E_ROOT_LEVEL) {
		shadow_addr = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
		shadow_addr &= PT64_BASE_ADDR_MASK;
		--level;
	}

	for (; ; level--) {
		u32 index = SHADOW_PT_INDEX(addr, level);
		struct kvm_mmu_page *shadow_page;
		u64 shadow_pte;
		int metaphysical;
		gfn_t table_gfn;
		bool new_page = 0;

		shadow_ent = ((u64 *)__va(shadow_addr)) + index;
		if (is_shadow_present_pte(*shadow_ent)) {
			if (level == PT_PAGE_TABLE_LEVEL)
				break;
			shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
			continue;
		}

		if (level == PT_PAGE_TABLE_LEVEL)
			break;

		if (level - 1 == PT_PAGE_TABLE_LEVEL
		    && walker->level == PT_DIRECTORY_LEVEL) {
			metaphysical = 1;
			if (!is_dirty_pte(walker->ptes[level - 1]))
				access &= ~ACC_WRITE_MASK;
			table_gfn = gpte_to_gfn(walker->ptes[level - 1]);
		} else {
			metaphysical = 0;
			table_gfn = walker->table_gfn[level - 2];
		}
		shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
					       metaphysical, access,
					       shadow_ent, &new_page);
		if (new_page && !metaphysical) {
			int r;
			pt_element_t curr_pte;
			r = kvm_read_guest_atomic(vcpu->kvm,
						  walker->pte_gpa[level - 2],
						  &curr_pte, sizeof(curr_pte));
			if (r || curr_pte != walker->ptes[level - 2])
				return NULL;
		}
		shadow_addr = __pa(shadow_page->spt);
		shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK
			| PT_WRITABLE_MASK | PT_USER_MASK;
		*shadow_ent = shadow_pte;
	}

	mmu_set_spte(vcpu, shadow_ent, access, walker->pte_access & access,
		     user_fault, write_fault,
		     walker->ptes[walker->level-1] & PT_DIRTY_MASK,
		     ptwrite, walker->gfn);

	return shadow_ent;
}

/*
 * Page fault handler.  There are several causes for a page fault:
 *   - there is no shadow pte for the guest pte
 *   - write access through a shadow pte marked read only so that we can set
 *     the dirty bit
 *   - write access to a shadow pte marked read only so we can update the page
 *     dirty bitmap, when userspace requests it
 *   - mmio access; in this case we will never install a present shadow pte
 *   - normal guest page fault due to the guest pte marked not present, not
 *     writable, or not executable
 *
 *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 *           a negative value on error.
 */
static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
			       u32 error_code)
{
	int write_fault = error_code & PFERR_WRITE_MASK;
	int user_fault = error_code & PFERR_USER_MASK;
	int fetch_fault = error_code & PFERR_FETCH_MASK;
	struct guest_walker walker;
	u64 *shadow_pte;
	int write_pt = 0;
	int r;

	pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
	kvm_mmu_audit(vcpu, "pre page fault");

	r = mmu_topup_memory_caches(vcpu);
	if (r)
		return r;

	down_read(&current->mm->mmap_sem);
	/*
	 * Look up the shadow pte for the faulting address.
	 */
	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
			     fetch_fault);
	up_read(&current->mm->mmap_sem);

	/*
	 * The page is not mapped by the guest.  Let the guest handle it.
	 */
	if (!r) {
		pgprintk("%s: guest page fault\n", __FUNCTION__);
		inject_page_fault(vcpu, addr, walker.error_code);
		vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
		return 0;
	}

	mutex_lock(&vcpu->kvm->lock);
	shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
				  &write_pt);
	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__,
		 shadow_pte, *shadow_pte, write_pt);

	if (!write_pt)
		vcpu->arch.last_pt_write_count = 0; /* reset fork detector */

	/*
	 * mmio: emulate if accessible, otherwise its a guest fault.
	 */
	if (shadow_pte && is_io_pte(*shadow_pte)) {
		mutex_unlock(&vcpu->kvm->lock);
		return 1;
	}

	++vcpu->stat.pf_fixed;
	kvm_mmu_audit(vcpu, "post page fault (fixed)");
	mutex_unlock(&vcpu->kvm->lock);

	return write_pt;
}

static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
{
	struct guest_walker walker;
	gpa_t gpa = UNMAPPED_GVA;
	int r;

	r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);

	if (r) {
		gpa = gfn_to_gpa(walker.gfn);
		gpa |= vaddr & ~PAGE_MASK;
	}

	return gpa;
}

static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
				 struct kvm_mmu_page *sp)
{
	int i, offset = 0, r = 0;
	pt_element_t pt;

	if (sp->role.metaphysical
	    || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
		nonpaging_prefetch_page(vcpu, sp);
		return;
	}

	if (PTTYPE == 32)
		offset = sp->role.quadrant << PT64_LEVEL_BITS;

	for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
		gpa_t pte_gpa = gfn_to_gpa(sp->gfn);
		pte_gpa += (i+offset) * sizeof(pt_element_t);

		r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &pt,
					  sizeof(pt_element_t));
		if (r || is_present_pte(pt))
			sp->spt[i] = shadow_trap_nonpresent_pte;
		else
			sp->spt[i] = shadow_notrap_nonpresent_pte;
	}
}

#undef pt_element_t
#undef guest_walker
#undef FNAME
#undef PT_BASE_ADDR_MASK
#undef PT_INDEX
#undef SHADOW_PT_INDEX
#undef PT_LEVEL_MASK
#undef PT_DIR_BASE_ADDR_MASK
#undef PT_LEVEL_BITS
#undef PT_MAX_FULL_LEVELS
#undef gpte_to_gfn
#undef gpte_to_gfn_pde
#undef CMPXCHG
Commit	Line	Data
6aa8b732 AK	1	/*
	2	* Kernel-based Virtual Machine driver for Linux
	3	*
	4	* This module enables machines with Intel VT-x extensions to run virtual
	5	* machines without emulation or binary translation.
	6	*
	7	* MMU support
	8	*
	9	* Copyright (C) 2006 Qumranet, Inc.
	10	*
	11	* Authors:
	12	* Yaniv Kamay <yaniv@qumranet.com>
	13	* Avi Kivity <avi@qumranet.com>
	14	*
	15	* This work is licensed under the terms of the GNU GPL, version 2. See
	16	* the COPYING file in the top-level directory.
	17	*
	18	*/
	19
	20	/*
	21	* We need the mmu code to access both 32-bit and 64-bit guest ptes,
	22	* so the code in this file is compiled twice, once per pte size.
	23	*/
	24
	25	#if PTTYPE == 64
	26	#define pt_element_t u64
	27	#define guest_walker guest_walker64
	28	#define FNAME(name) paging##64_##name
	29	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	30	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	31	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	32	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	33	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
c7addb90	34	#define PT_LEVEL_BITS PT64_LEVEL_BITS
cea0f0e7 AK	35	#ifdef CONFIG_X86_64
cea0f0e7 AK	36	#define PT_MAX_FULL_LEVELS 4
b3e4e63f	37	#define CMPXCHG cmpxchg
cea0f0e7	38	#else
b3e4e63f	39	#define CMPXCHG cmpxchg64
cea0f0e7 AK	40	#define PT_MAX_FULL_LEVELS 2
cea0f0e7 AK	41	#endif
6aa8b732 AK	42	#elif PTTYPE == 32
	43	#define pt_element_t u32
	44	#define guest_walker guest_walker32
	45	#define FNAME(name) paging##32_##name
	46	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	47	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	48	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	49	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	50	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
c7addb90	51	#define PT_LEVEL_BITS PT32_LEVEL_BITS
cea0f0e7	52	#define PT_MAX_FULL_LEVELS 2
b3e4e63f	53	#define CMPXCHG cmpxchg
6aa8b732 AK	54	#else
	55	#error Invalid PTTYPE value
	56	#endif
	57
5fb07ddb AK	58	#define gpte_to_gfn FNAME(gpte_to_gfn)
	59	#define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde)
	60
6aa8b732 AK	61	/*
	62	* The guest_walker structure emulates the behavior of the hardware page
	63	* table walker.
	64	*/
	65	struct guest_walker {
	66	int level;
cea0f0e7	67	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
7819026e MT	68	pt_element_t ptes[PT_MAX_FULL_LEVELS];
7819026e MT	69	gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
fe135d2c AK	70	unsigned pt_access;
fe135d2c AK	71	unsigned pte_access;
815af8d4	72	gfn_t gfn;
7993ba43	73	u32 error_code;
6aa8b732 AK	74	};
6aa8b732 AK	75
5fb07ddb AK	76	static gfn_t gpte_to_gfn(pt_element_t gpte)
	77	{
	78	return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
	79	}
	80
	81	static gfn_t gpte_to_gfn_pde(pt_element_t gpte)
	82	{
	83	return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
	84	}
	85
b3e4e63f MT	86	static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
	87	gfn_t table_gfn, unsigned index,
	88	pt_element_t orig_pte, pt_element_t new_pte)
	89	{
	90	pt_element_t ret;
	91	pt_element_t *table;
	92	struct page *page;
	93
	94	page = gfn_to_page(kvm, table_gfn);
	95	table = kmap_atomic(page, KM_USER0);
	96
	97	ret = CMPXCHG(&table[index], orig_pte, new_pte);
	98
	99	kunmap_atomic(table, KM_USER0);
	100
	101	kvm_release_page_dirty(page);
	102
	103	return (ret != orig_pte);
	104	}
	105
bedbe4ee AK	106	static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
	107	{
	108	unsigned access;
	109
	110	access = (gpte & (PT_WRITABLE_MASK \| PT_USER_MASK)) \| ACC_EXEC_MASK;
	111	#if PTTYPE == 64
	112	if (is_nx(vcpu))
	113	access &= ~(gpte >> PT64_NX_SHIFT);
	114	#endif
	115	return access;
	116	}
	117
ac79c978 AK	118	/*
	119	* Fetch a guest pte for a guest virtual address
	120	*/
7993ba43 AK	121	static int FNAME(walk_addr)(struct guest_walker *walker,
7993ba43 AK	122	struct kvm_vcpu *vcpu, gva_t addr,
73b1087e	123	int write_fault, int user_fault, int fetch_fault)
6aa8b732	124	{
42bf3f0a	125	pt_element_t pte;
cea0f0e7	126	gfn_t table_gfn;
fe135d2c	127	unsigned index, pt_access, pte_access;
42bf3f0a	128	gpa_t pte_gpa;
6aa8b732	129
cea0f0e7	130	pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
b3e4e63f	131	walk:
ad312c7c ZX	132	walker->level = vcpu->arch.mmu.root_level;
ad312c7c ZX	133	pte = vcpu->arch.cr3;
1b0973bd AK	134	#if PTTYPE == 64
1b0973bd AK	135	if (!is_long_mode(vcpu)) {
ad312c7c	136	pte = vcpu->arch.pdptrs[(addr >> 30) & 3];
42bf3f0a	137	if (!is_present_pte(pte))
7993ba43	138	goto not_present;
1b0973bd AK	139	--walker->level;
	140	}
	141	#endif
a9058ecd	142	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) \|\|
f802a307	143	(vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
6aa8b732	144
fe135d2c	145	pt_access = ACC_ALL;
ac79c978 AK	146
ac79c978 AK	147	for (;;) {
42bf3f0a	148	index = PT_INDEX(addr, walker->level);
ac79c978	149
5fb07ddb	150	table_gfn = gpte_to_gfn(pte);
1755fbcc	151	pte_gpa = gfn_to_gpa(table_gfn);
ec8d4eae	152	pte_gpa += index * sizeof(pt_element_t);
42bf3f0a	153	walker->table_gfn[walker->level - 1] = table_gfn;
7819026e	154	walker->pte_gpa[walker->level - 1] = pte_gpa;
42bf3f0a AK	155	pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
	156	walker->level - 1, table_gfn);
	157
ec8d4eae	158	kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
42bf3f0a AK	159
42bf3f0a AK	160	if (!is_present_pte(pte))
7993ba43 AK	161	goto not_present;
7993ba43 AK	162
42bf3f0a	163	if (write_fault && !is_writeble_pte(pte))
7993ba43 AK	164	if (user_fault \|\| is_write_protection(vcpu))
	165	goto access_error;
	166
42bf3f0a	167	if (user_fault && !(pte & PT_USER_MASK))
7993ba43 AK	168	goto access_error;
7993ba43 AK	169
73b1087e	170	#if PTTYPE == 64
42bf3f0a	171	if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
73b1087e AK	172	goto access_error;
	173	#endif
	174
42bf3f0a	175	if (!(pte & PT_ACCESSED_MASK)) {
bf3f8e86	176	mark_page_dirty(vcpu->kvm, table_gfn);
b3e4e63f MT	177	if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
	178	index, pte, pte\|PT_ACCESSED_MASK))
	179	goto walk;
42bf3f0a	180	pte \|= PT_ACCESSED_MASK;
bf3f8e86	181	}
815af8d4	182
bedbe4ee	183	pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
fe135d2c	184
7819026e MT	185	walker->ptes[walker->level - 1] = pte;
7819026e MT	186
815af8d4	187	if (walker->level == PT_PAGE_TABLE_LEVEL) {
5fb07ddb	188	walker->gfn = gpte_to_gfn(pte);
815af8d4 AK	189	break;
	190	}
	191
	192	if (walker->level == PT_DIRECTORY_LEVEL
42bf3f0a	193	&& (pte & PT_PAGE_SIZE_MASK)
815af8d4	194	&& (PTTYPE == 64 \|\| is_pse(vcpu))) {
5fb07ddb	195	walker->gfn = gpte_to_gfn_pde(pte);
815af8d4	196	walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
da928521 AK	197	if (PTTYPE == 32 && is_cpuid_PSE36())
da928521 AK	198	walker->gfn += pse36_gfn_delta(pte);
ac79c978	199	break;
815af8d4	200	}
ac79c978	201
fe135d2c	202	pt_access = pte_access;
ac79c978 AK	203	--walker->level;
ac79c978 AK	204	}
42bf3f0a AK	205
42bf3f0a AK	206	if (write_fault && !is_dirty_pte(pte)) {
b3e4e63f MT	207	bool ret;
b3e4e63f MT	208
42bf3f0a	209	mark_page_dirty(vcpu->kvm, table_gfn);
b3e4e63f MT	210	ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
	211	pte\|PT_DIRTY_MASK);
	212	if (ret)
	213	goto walk;
42bf3f0a	214	pte \|= PT_DIRTY_MASK;
42bf3f0a	215	kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte));
7819026e	216	walker->ptes[walker->level - 1] = pte;
42bf3f0a AK	217	}
42bf3f0a AK	218
fe135d2c AK	219	walker->pt_access = pt_access;
	220	walker->pte_access = pte_access;
	221	pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
	222	__FUNCTION__, (u64)pte, pt_access, pte_access);
7993ba43 AK	223	return 1;
	224
	225	not_present:
	226	walker->error_code = 0;
	227	goto err;
	228
	229	access_error:
	230	walker->error_code = PFERR_PRESENT_MASK;
	231
	232	err:
	233	if (write_fault)
	234	walker->error_code \|= PFERR_WRITE_MASK;
	235	if (user_fault)
	236	walker->error_code \|= PFERR_USER_MASK;
73b1087e AK	237	if (fetch_fault)
73b1087e AK	238	walker->error_code \|= PFERR_FETCH_MASK;
fe551881	239	return 0;
6aa8b732 AK	240	}
6aa8b732 AK	241
0028425f	242	static void FNAME(update_pte)(struct kvm_vcpu vcpu, struct kvm_mmu_page page,
c7addb90 AK	243	u64 spte, const void pte, int bytes,
c7addb90 AK	244	int offset_in_pte)
0028425f AK	245	{
0028425f AK	246	pt_element_t gpte;
41074d07	247	unsigned pte_access;
0028425f	248
0028425f	249	gpte = (const pt_element_t )pte;
c7addb90 AK	250	if (~gpte & (PT_PRESENT_MASK \| PT_ACCESSED_MASK)) {
	251	if (!offset_in_pte && !is_present_pte(gpte))
	252	set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
	253	return;
	254	}
	255	if (bytes < sizeof(pt_element_t))
0028425f AK	256	return;
0028425f AK	257	pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
41074d07	258	pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte);
1c4f1fd6 AK	259	mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
1c4f1fd6 AK	260	gpte & PT_DIRTY_MASK, NULL, gpte_to_gfn(gpte));
0028425f AK	261	}
0028425f AK	262
6aa8b732 AK	263	/*
	264	* Fetch a shadow pte for a specific level in the paging hierarchy.
	265	*/
	266	static u64 FNAME(fetch)(struct kvm_vcpu vcpu, gva_t addr,
97a0a01e AK	267	struct guest_walker *walker,
97a0a01e AK	268	int user_fault, int write_fault, int *ptwrite)
6aa8b732 AK	269	{
	270	hpa_t shadow_addr;
	271	int level;
ef0197e8	272	u64 *shadow_ent;
fe135d2c	273	unsigned access = walker->pt_access;
ac79c978	274
7819026e	275	if (!is_present_pte(walker->ptes[walker->level - 1]))
ac79c978	276	return NULL;
6aa8b732	277
ad312c7c ZX	278	shadow_addr = vcpu->arch.mmu.root_hpa;
ad312c7c ZX	279	level = vcpu->arch.mmu.shadow_root_level;
aef3d3fe	280	if (level == PT32E_ROOT_LEVEL) {
ad312c7c	281	shadow_addr = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
aef3d3fe AK	282	shadow_addr &= PT64_BASE_ADDR_MASK;
	283	--level;
	284	}
6aa8b732 AK	285
	286	for (; ; level--) {
	287	u32 index = SHADOW_PT_INDEX(addr, level);
25c0de2c	288	struct kvm_mmu_page *shadow_page;
8c7bb723	289	u64 shadow_pte;
cea0f0e7 AK	290	int metaphysical;
cea0f0e7 AK	291	gfn_t table_gfn;
7819026e	292	bool new_page = 0;
6aa8b732	293
ef0197e8	294	shadow_ent = ((u64 *)__va(shadow_addr)) + index;
c7addb90	295	if (is_shadow_present_pte(*shadow_ent)) {
6aa8b732	296	if (level == PT_PAGE_TABLE_LEVEL)
97a0a01e	297	break;
6aa8b732	298	shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
6aa8b732 AK	299	continue;
	300	}
	301
ef0197e8 AK	302	if (level == PT_PAGE_TABLE_LEVEL)
ef0197e8 AK	303	break;
6aa8b732	304
cea0f0e7 AK	305	if (level - 1 == PT_PAGE_TABLE_LEVEL
	306	&& walker->level == PT_DIRECTORY_LEVEL) {
	307	metaphysical = 1;
7819026e	308	if (!is_dirty_pte(walker->ptes[level - 1]))
fe135d2c	309	access &= ~ACC_WRITE_MASK;
7819026e	310	table_gfn = gpte_to_gfn(walker->ptes[level - 1]);
cea0f0e7 AK	311	} else {
	312	metaphysical = 0;
	313	table_gfn = walker->table_gfn[level - 2];
	314	}
	315	shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
fe135d2c	316	metaphysical, access,
7819026e MT	317	shadow_ent, &new_page);
7819026e MT	318	if (new_page && !metaphysical) {
7ec54588	319	int r;
7819026e	320	pt_element_t curr_pte;
7ec54588 MT	321	r = kvm_read_guest_atomic(vcpu->kvm,
	322	walker->pte_gpa[level - 2],
	323	&curr_pte, sizeof(curr_pte));
	324	if (r \|\| curr_pte != walker->ptes[level - 2])
7819026e MT	325	return NULL;
7819026e MT	326	}
47ad8e68	327	shadow_addr = __pa(shadow_page->spt);
aef3d3fe AK	328	shadow_pte = shadow_addr \| PT_PRESENT_MASK \| PT_ACCESSED_MASK
aef3d3fe AK	329	\| PT_WRITABLE_MASK \| PT_USER_MASK;
8c7bb723	330	*shadow_ent = shadow_pte;
6aa8b732	331	}
ef0197e8	332
1c4f1fd6	333	mmu_set_spte(vcpu, shadow_ent, access, walker->pte_access & access,
7819026e MT	334	user_fault, write_fault,
7819026e MT	335	walker->ptes[walker->level-1] & PT_DIRTY_MASK,
1c4f1fd6	336	ptwrite, walker->gfn);
050e6499	337
ef0197e8	338	return shadow_ent;
6aa8b732 AK	339	}
6aa8b732 AK	340
6aa8b732 AK	341	/*
	342	* Page fault handler. There are several causes for a page fault:
	343	* - there is no shadow pte for the guest pte
	344	* - write access through a shadow pte marked read only so that we can set
	345	* the dirty bit
	346	* - write access to a shadow pte marked read only so we can update the page
	347	* dirty bitmap, when userspace requests it
	348	* - mmio access; in this case we will never install a present shadow pte
	349	* - normal guest page fault due to the guest pte marked not present, not
	350	* writable, or not executable
	351	*
e2dec939 AK	352	* Returns: 1 if we need to emulate the instruction, 0 otherwise, or
e2dec939 AK	353	* a negative value on error.
6aa8b732 AK	354	*/
	355	static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
	356	u32 error_code)
	357	{
	358	int write_fault = error_code & PFERR_WRITE_MASK;
6aa8b732	359	int user_fault = error_code & PFERR_USER_MASK;
73b1087e	360	int fetch_fault = error_code & PFERR_FETCH_MASK;
6aa8b732 AK	361	struct guest_walker walker;
6aa8b732 AK	362	u64 *shadow_pte;
cea0f0e7	363	int write_pt = 0;
e2dec939	364	int r;
6aa8b732	365
cea0f0e7	366	pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
37a7d8b0	367	kvm_mmu_audit(vcpu, "pre page fault");
714b93da	368
e2dec939 AK	369	r = mmu_topup_memory_caches(vcpu);
	370	if (r)
	371	return r;
714b93da	372
10589a46	373	down_read(&current->mm->mmap_sem);
6aa8b732 AK	374	/*
	375	* Look up the shadow pte for the faulting address.
	376	*/
73b1087e AK	377	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
73b1087e AK	378	fetch_fault);
10589a46	379	up_read(&current->mm->mmap_sem);
6aa8b732 AK	380
	381	/*
	382	* The page is not mapped by the guest. Let the guest handle it.
	383	*/
7993ba43 AK	384	if (!r) {
	385	pgprintk("%s: guest page fault\n", __FUNCTION__);
	386	inject_page_fault(vcpu, addr, walker.error_code);
ad312c7c	387	vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
6aa8b732 AK	388	return 0;
	389	}
	390
10589a46	391	mutex_lock(&vcpu->kvm->lock);
97a0a01e AK	392	shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
	393	&write_pt);
	394	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__,
	395	shadow_pte, *shadow_pte, write_pt);
cea0f0e7	396
a25f7e1f	397	if (!write_pt)
ad312c7c	398	vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
a25f7e1f	399
6aa8b732 AK	400	/*
	401	* mmio: emulate if accessible, otherwise its a guest fault.
	402	*/
10589a46 MT	403	if (shadow_pte && is_io_pte(*shadow_pte)) {
10589a46 MT	404	mutex_unlock(&vcpu->kvm->lock);
7993ba43	405	return 1;
10589a46	406	}
6aa8b732	407
1165f5fe	408	++vcpu->stat.pf_fixed;
37a7d8b0	409	kvm_mmu_audit(vcpu, "post page fault (fixed)");
10589a46	410	mutex_unlock(&vcpu->kvm->lock);
6aa8b732	411
cea0f0e7	412	return write_pt;
6aa8b732 AK	413	}
	414
	415	static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
	416	{
	417	struct guest_walker walker;
e119d117 AK	418	gpa_t gpa = UNMAPPED_GVA;
e119d117 AK	419	int r;
6aa8b732	420
e119d117	421	r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
6aa8b732	422
e119d117	423	if (r) {
1755fbcc	424	gpa = gfn_to_gpa(walker.gfn);
e119d117	425	gpa \|= vaddr & ~PAGE_MASK;
6aa8b732 AK	426	}
	427
	428	return gpa;
	429	}
	430
c7addb90 AK	431	static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
	432	struct kvm_mmu_page *sp)
	433	{
7ec54588 MT	434	int i, offset = 0, r = 0;
7ec54588 MT	435	pt_element_t pt;
c7addb90	436
e5a4c8ca AK	437	if (sp->role.metaphysical
e5a4c8ca AK	438	\|\| (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
c7addb90 AK	439	nonpaging_prefetch_page(vcpu, sp);
	440	return;
	441	}
	442
e5a4c8ca AK	443	if (PTTYPE == 32)
e5a4c8ca AK	444	offset = sp->role.quadrant << PT64_LEVEL_BITS;
7ec54588 MT	445
	446	for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
	447	gpa_t pte_gpa = gfn_to_gpa(sp->gfn);
	448	pte_gpa += (i+offset) * sizeof(pt_element_t);
	449
	450	r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &pt,
	451	sizeof(pt_element_t));
	452	if (r \|\| is_present_pte(pt))
c7addb90 AK	453	sp->spt[i] = shadow_trap_nonpresent_pte;
	454	else
	455	sp->spt[i] = shadow_notrap_nonpresent_pte;
7ec54588	456	}
c7addb90 AK	457	}
c7addb90 AK	458
6aa8b732 AK	459	#undef pt_element_t
	460	#undef guest_walker
	461	#undef FNAME
	462	#undef PT_BASE_ADDR_MASK
	463	#undef PT_INDEX
	464	#undef SHADOW_PT_INDEX
	465	#undef PT_LEVEL_MASK
6aa8b732	466	#undef PT_DIR_BASE_ADDR_MASK
c7addb90	467	#undef PT_LEVEL_BITS
cea0f0e7	468	#undef PT_MAX_FULL_LEVELS
5fb07ddb AK	469	#undef gpte_to_gfn
5fb07ddb AK	470	#undef gpte_to_gfn_pde
b3e4e63f	471	#undef CMPXCHG