Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
37406aaa NHE |
26 | /* |
27 | * This is used to catch non optimized PT_GUEST_(DIRTY|ACCESS)_SHIFT macro | |
28 | * uses for EPT without A/D paging type. | |
29 | */ | |
30 | extern u64 __pure __using_nonexistent_pte_bit(void) | |
31 | __compiletime_error("wrong use of PT_GUEST_(DIRTY|ACCESS)_SHIFT"); | |
32 | ||
6aa8b732 AK |
33 | #if PTTYPE == 64 |
34 | #define pt_element_t u64 | |
35 | #define guest_walker guest_walker64 | |
36 | #define FNAME(name) paging##64_##name | |
37 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
38 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
39 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 40 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 41 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
d8089bac GN |
42 | #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK |
43 | #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK | |
44 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT | |
45 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
cea0f0e7 AK |
46 | #ifdef CONFIG_X86_64 |
47 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 48 | #define CMPXCHG cmpxchg |
cea0f0e7 | 49 | #else |
b3e4e63f | 50 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
51 | #define PT_MAX_FULL_LEVELS 2 |
52 | #endif | |
6aa8b732 AK |
53 | #elif PTTYPE == 32 |
54 | #define pt_element_t u32 | |
55 | #define guest_walker guest_walker32 | |
56 | #define FNAME(name) paging##32_##name | |
57 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
58 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
59 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 60 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 61 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 62 | #define PT_MAX_FULL_LEVELS 2 |
d8089bac GN |
63 | #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK |
64 | #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK | |
65 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT | |
66 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
b3e4e63f | 67 | #define CMPXCHG cmpxchg |
37406aaa NHE |
68 | #elif PTTYPE == PTTYPE_EPT |
69 | #define pt_element_t u64 | |
70 | #define guest_walker guest_walkerEPT | |
71 | #define FNAME(name) ept_##name | |
72 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
73 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) | |
74 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
75 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
76 | #define PT_LEVEL_BITS PT64_LEVEL_BITS | |
77 | #define PT_GUEST_ACCESSED_MASK 0 | |
78 | #define PT_GUEST_DIRTY_MASK 0 | |
79 | #define PT_GUEST_DIRTY_SHIFT __using_nonexistent_pte_bit() | |
80 | #define PT_GUEST_ACCESSED_SHIFT __using_nonexistent_pte_bit() | |
81 | #define CMPXCHG cmpxchg64 | |
82 | #define PT_MAX_FULL_LEVELS 4 | |
6aa8b732 AK |
83 | #else |
84 | #error Invalid PTTYPE value | |
85 | #endif | |
86 | ||
e04da980 JR |
87 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
88 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 89 | |
6aa8b732 AK |
90 | /* |
91 | * The guest_walker structure emulates the behavior of the hardware page | |
92 | * table walker. | |
93 | */ | |
94 | struct guest_walker { | |
95 | int level; | |
8cbc7069 | 96 | unsigned max_level; |
cea0f0e7 | 97 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 98 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 99 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 100 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
8cbc7069 | 101 | pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS]; |
ba6a3541 | 102 | bool pte_writable[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
103 | unsigned pt_access; |
104 | unsigned pte_access; | |
815af8d4 | 105 | gfn_t gfn; |
8c28d031 | 106 | struct x86_exception fault; |
6aa8b732 AK |
107 | }; |
108 | ||
e04da980 | 109 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 110 | { |
e04da980 | 111 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
112 | } |
113 | ||
0ad805a0 NHE |
114 | static inline void FNAME(protect_clean_gpte)(unsigned *access, unsigned gpte) |
115 | { | |
116 | unsigned mask; | |
117 | ||
61719a8f GN |
118 | /* dirty bit is not supported, so no need to track it */ |
119 | if (!PT_GUEST_DIRTY_MASK) | |
120 | return; | |
121 | ||
0ad805a0 NHE |
122 | BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK); |
123 | ||
124 | mask = (unsigned)~ACC_WRITE_MASK; | |
125 | /* Allow write access to dirty gptes */ | |
d8089bac GN |
126 | mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & |
127 | PT_WRITABLE_MASK; | |
0ad805a0 NHE |
128 | *access &= mask; |
129 | } | |
130 | ||
0ad805a0 NHE |
131 | static inline int FNAME(is_present_gpte)(unsigned long pte) |
132 | { | |
37406aaa | 133 | #if PTTYPE != PTTYPE_EPT |
812f30b2 | 134 | return pte & PT_PRESENT_MASK; |
37406aaa NHE |
135 | #else |
136 | return pte & 7; | |
137 | #endif | |
0ad805a0 NHE |
138 | } |
139 | ||
a78484c6 | 140 | static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
c8cfbb55 TY |
141 | pt_element_t __user *ptep_user, unsigned index, |
142 | pt_element_t orig_pte, pt_element_t new_pte) | |
b3e4e63f | 143 | { |
c8cfbb55 | 144 | int npages; |
b3e4e63f MT |
145 | pt_element_t ret; |
146 | pt_element_t *table; | |
147 | struct page *page; | |
148 | ||
c8cfbb55 TY |
149 | npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page); |
150 | /* Check if the user is doing something meaningless. */ | |
151 | if (unlikely(npages != 1)) | |
a78484c6 RJ |
152 | return -EFAULT; |
153 | ||
8fd75e12 | 154 | table = kmap_atomic(page); |
b3e4e63f | 155 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
8fd75e12 | 156 | kunmap_atomic(table); |
b3e4e63f MT |
157 | |
158 | kvm_release_page_dirty(page); | |
159 | ||
160 | return (ret != orig_pte); | |
161 | } | |
162 | ||
0ad805a0 NHE |
163 | static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu, |
164 | struct kvm_mmu_page *sp, u64 *spte, | |
165 | u64 gpte) | |
166 | { | |
d2b0f981 | 167 | if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) |
0ad805a0 NHE |
168 | goto no_present; |
169 | ||
170 | if (!FNAME(is_present_gpte)(gpte)) | |
171 | goto no_present; | |
172 | ||
61719a8f GN |
173 | /* if accessed bit is not supported prefetch non accessed gpte */ |
174 | if (PT_GUEST_ACCESSED_MASK && !(gpte & PT_GUEST_ACCESSED_MASK)) | |
0ad805a0 NHE |
175 | goto no_present; |
176 | ||
177 | return false; | |
178 | ||
179 | no_present: | |
180 | drop_spte(vcpu->kvm, spte); | |
181 | return true; | |
182 | } | |
183 | ||
d95c5568 BD |
184 | /* |
185 | * For PTTYPE_EPT, a page table can be executable but not readable | |
186 | * on supported processors. Therefore, set_spte does not automatically | |
187 | * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK | |
188 | * to signify readability since it isn't used in the EPT case | |
189 | */ | |
0ad805a0 NHE |
190 | static inline unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, u64 gpte) |
191 | { | |
192 | unsigned access; | |
37406aaa NHE |
193 | #if PTTYPE == PTTYPE_EPT |
194 | access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) | | |
195 | ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) | | |
d95c5568 | 196 | ((gpte & VMX_EPT_READABLE_MASK) ? ACC_USER_MASK : 0); |
37406aaa | 197 | #else |
bb9eadf0 PB |
198 | BUILD_BUG_ON(ACC_EXEC_MASK != PT_PRESENT_MASK); |
199 | BUILD_BUG_ON(ACC_EXEC_MASK != 1); | |
200 | access = gpte & (PT_WRITABLE_MASK | PT_USER_MASK | PT_PRESENT_MASK); | |
201 | /* Combine NX with P (which is set here) to get ACC_EXEC_MASK. */ | |
202 | access ^= (gpte >> PT64_NX_SHIFT); | |
37406aaa | 203 | #endif |
0ad805a0 NHE |
204 | |
205 | return access; | |
206 | } | |
207 | ||
8cbc7069 AK |
208 | static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu, |
209 | struct kvm_mmu *mmu, | |
210 | struct guest_walker *walker, | |
211 | int write_fault) | |
212 | { | |
213 | unsigned level, index; | |
214 | pt_element_t pte, orig_pte; | |
215 | pt_element_t __user *ptep_user; | |
216 | gfn_t table_gfn; | |
217 | int ret; | |
218 | ||
61719a8f GN |
219 | /* dirty/accessed bits are not supported, so no need to update them */ |
220 | if (!PT_GUEST_DIRTY_MASK) | |
221 | return 0; | |
222 | ||
8cbc7069 AK |
223 | for (level = walker->max_level; level >= walker->level; --level) { |
224 | pte = orig_pte = walker->ptes[level - 1]; | |
225 | table_gfn = walker->table_gfn[level - 1]; | |
226 | ptep_user = walker->ptep_user[level - 1]; | |
227 | index = offset_in_page(ptep_user) / sizeof(pt_element_t); | |
d8089bac | 228 | if (!(pte & PT_GUEST_ACCESSED_MASK)) { |
8cbc7069 | 229 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte)); |
d8089bac | 230 | pte |= PT_GUEST_ACCESSED_MASK; |
8cbc7069 | 231 | } |
0ad805a0 | 232 | if (level == walker->level && write_fault && |
d8089bac | 233 | !(pte & PT_GUEST_DIRTY_MASK)) { |
8cbc7069 | 234 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
d8089bac | 235 | pte |= PT_GUEST_DIRTY_MASK; |
8cbc7069 AK |
236 | } |
237 | if (pte == orig_pte) | |
238 | continue; | |
239 | ||
ba6a3541 PB |
240 | /* |
241 | * If the slot is read-only, simply do not process the accessed | |
242 | * and dirty bits. This is the correct thing to do if the slot | |
243 | * is ROM, and page tables in read-as-ROM/write-as-MMIO slots | |
244 | * are only supported if the accessed and dirty bits are already | |
245 | * set in the ROM (so that MMIO writes are never needed). | |
246 | * | |
247 | * Note that NPT does not allow this at all and faults, since | |
248 | * it always wants nested page table entries for the guest | |
249 | * page tables to be writable. And EPT works but will simply | |
250 | * overwrite the read-only memory to set the accessed and dirty | |
251 | * bits. | |
252 | */ | |
253 | if (unlikely(!walker->pte_writable[level - 1])) | |
254 | continue; | |
255 | ||
8cbc7069 AK |
256 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte); |
257 | if (ret) | |
258 | return ret; | |
259 | ||
54bf36aa | 260 | kvm_vcpu_mark_page_dirty(vcpu, table_gfn); |
17e4bce0 | 261 | walker->ptes[level - 1] = pte; |
8cbc7069 AK |
262 | } |
263 | return 0; | |
264 | } | |
265 | ||
be94f6b7 HH |
266 | static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte) |
267 | { | |
268 | unsigned pkeys = 0; | |
269 | #if PTTYPE == 64 | |
270 | pte_t pte = {.pte = gpte}; | |
271 | ||
272 | pkeys = pte_flags_pkey(pte_flags(pte)); | |
273 | #endif | |
274 | return pkeys; | |
275 | } | |
276 | ||
ac79c978 AK |
277 | /* |
278 | * Fetch a guest pte for a guest virtual address | |
279 | */ | |
1e301feb JR |
280 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
281 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
33770780 | 282 | gva_t addr, u32 access) |
6aa8b732 | 283 | { |
8cbc7069 | 284 | int ret; |
42bf3f0a | 285 | pt_element_t pte; |
b7233635 | 286 | pt_element_t __user *uninitialized_var(ptep_user); |
cea0f0e7 | 287 | gfn_t table_gfn; |
be94f6b7 | 288 | unsigned index, pt_access, pte_access, accessed_dirty, pte_pkey; |
42bf3f0a | 289 | gpa_t pte_gpa; |
134291bf TY |
290 | int offset; |
291 | const int write_fault = access & PFERR_WRITE_MASK; | |
292 | const int user_fault = access & PFERR_USER_MASK; | |
293 | const int fetch_fault = access & PFERR_FETCH_MASK; | |
294 | u16 errcode = 0; | |
13d22b6a AK |
295 | gpa_t real_gpa; |
296 | gfn_t gfn; | |
6aa8b732 | 297 | |
6fbc2770 | 298 | trace_kvm_mmu_pagetable_walk(addr, access); |
92c1c1e8 | 299 | retry_walk: |
1e301feb JR |
300 | walker->level = mmu->root_level; |
301 | pte = mmu->get_cr3(vcpu); | |
302 | ||
1b0973bd | 303 | #if PTTYPE == 64 |
1e301feb | 304 | if (walker->level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 305 | pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3); |
07420171 | 306 | trace_kvm_mmu_paging_element(pte, walker->level); |
0ad805a0 | 307 | if (!FNAME(is_present_gpte)(pte)) |
f59c1d2d | 308 | goto error; |
1b0973bd AK |
309 | --walker->level; |
310 | } | |
311 | #endif | |
8cbc7069 | 312 | walker->max_level = walker->level; |
1715d0dc | 313 | ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu))); |
6aa8b732 | 314 | |
d8089bac | 315 | accessed_dirty = PT_GUEST_ACCESSED_MASK; |
13d22b6a AK |
316 | pt_access = pte_access = ACC_ALL; |
317 | ++walker->level; | |
ac79c978 | 318 | |
13d22b6a | 319 | do { |
6e2ca7d1 TY |
320 | gfn_t real_gfn; |
321 | unsigned long host_addr; | |
322 | ||
13d22b6a AK |
323 | pt_access &= pte_access; |
324 | --walker->level; | |
325 | ||
42bf3f0a | 326 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 327 | |
5fb07ddb | 328 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
329 | offset = index * sizeof(pt_element_t); |
330 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
42bf3f0a | 331 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 332 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 333 | |
6e2ca7d1 | 334 | real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn), |
54987b7a PB |
335 | PFERR_USER_MASK|PFERR_WRITE_MASK, |
336 | &walker->fault); | |
5e352519 PB |
337 | |
338 | /* | |
339 | * FIXME: This can happen if emulation (for of an INS/OUTS | |
340 | * instruction) triggers a nested page fault. The exit | |
341 | * qualification / exit info field will incorrectly have | |
342 | * "guest page access" as the nested page fault's cause, | |
343 | * instead of "guest page structure access". To fix this, | |
344 | * the x86_exception struct should be augmented with enough | |
345 | * information to fix the exit_qualification or exit_info_1 | |
346 | * fields. | |
347 | */ | |
134291bf | 348 | if (unlikely(real_gfn == UNMAPPED_GVA)) |
54987b7a | 349 | return 0; |
5e352519 | 350 | |
6e2ca7d1 TY |
351 | real_gfn = gpa_to_gfn(real_gfn); |
352 | ||
54bf36aa | 353 | host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, real_gfn, |
ba6a3541 | 354 | &walker->pte_writable[walker->level - 1]); |
134291bf TY |
355 | if (unlikely(kvm_is_error_hva(host_addr))) |
356 | goto error; | |
6e2ca7d1 TY |
357 | |
358 | ptep_user = (pt_element_t __user *)((void *)host_addr + offset); | |
134291bf TY |
359 | if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte)))) |
360 | goto error; | |
8cbc7069 | 361 | walker->ptep_user[walker->level - 1] = ptep_user; |
a6085fba | 362 | |
07420171 | 363 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 364 | |
0ad805a0 | 365 | if (unlikely(!FNAME(is_present_gpte)(pte))) |
134291bf | 366 | goto error; |
7993ba43 | 367 | |
d2b0f981 | 368 | if (unlikely(is_rsvd_bits_set(mmu, pte, walker->level))) { |
7a98205d | 369 | errcode = PFERR_RSVD_MASK | PFERR_PRESENT_MASK; |
134291bf | 370 | goto error; |
f59c1d2d | 371 | } |
82725b20 | 372 | |
b514c30f | 373 | accessed_dirty &= pte; |
0ad805a0 | 374 | pte_access = pt_access & FNAME(gpte_access)(vcpu, pte); |
73b1087e | 375 | |
7819026e | 376 | walker->ptes[walker->level - 1] = pte; |
6fd01b71 | 377 | } while (!is_last_gpte(mmu, walker->level, pte)); |
42bf3f0a | 378 | |
be94f6b7 HH |
379 | pte_pkey = FNAME(gpte_pkeys)(vcpu, pte); |
380 | errcode = permission_fault(vcpu, mmu, pte_access, pte_pkey, access); | |
f13577e8 | 381 | if (unlikely(errcode)) |
f59c1d2d AK |
382 | goto error; |
383 | ||
13d22b6a AK |
384 | gfn = gpte_to_gfn_lvl(pte, walker->level); |
385 | gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT; | |
386 | ||
387 | if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36()) | |
388 | gfn += pse36_gfn_delta(pte); | |
389 | ||
54987b7a | 390 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault); |
13d22b6a AK |
391 | if (real_gpa == UNMAPPED_GVA) |
392 | return 0; | |
393 | ||
394 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
395 | ||
8ea667f2 | 396 | if (!write_fault) |
0ad805a0 | 397 | FNAME(protect_clean_gpte)(&pte_access, pte); |
908e7d79 GN |
398 | else |
399 | /* | |
61719a8f GN |
400 | * On a write fault, fold the dirty bit into accessed_dirty. |
401 | * For modes without A/D bits support accessed_dirty will be | |
402 | * always clear. | |
908e7d79 | 403 | */ |
d8089bac GN |
404 | accessed_dirty &= pte >> |
405 | (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT); | |
b514c30f AK |
406 | |
407 | if (unlikely(!accessed_dirty)) { | |
408 | ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault); | |
409 | if (unlikely(ret < 0)) | |
410 | goto error; | |
411 | else if (ret) | |
412 | goto retry_walk; | |
413 | } | |
42bf3f0a | 414 | |
fe135d2c AK |
415 | walker->pt_access = pt_access; |
416 | walker->pte_access = pte_access; | |
417 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
518c5a05 | 418 | __func__, (u64)pte, pte_access, pt_access); |
7993ba43 AK |
419 | return 1; |
420 | ||
f59c1d2d | 421 | error: |
134291bf | 422 | errcode |= write_fault | user_fault; |
e57d4a35 YW |
423 | if (fetch_fault && (mmu->nx || |
424 | kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))) | |
134291bf | 425 | errcode |= PFERR_FETCH_MASK; |
8df25a32 | 426 | |
134291bf TY |
427 | walker->fault.vector = PF_VECTOR; |
428 | walker->fault.error_code_valid = true; | |
429 | walker->fault.error_code = errcode; | |
25d92081 YZ |
430 | |
431 | #if PTTYPE == PTTYPE_EPT | |
432 | /* | |
433 | * Use PFERR_RSVD_MASK in error_code to to tell if EPT | |
434 | * misconfiguration requires to be injected. The detection is | |
435 | * done by is_rsvd_bits_set() above. | |
436 | * | |
437 | * We set up the value of exit_qualification to inject: | |
438 | * [2:0] - Derive from [2:0] of real exit_qualification at EPT violation | |
439 | * [5:3] - Calculated by the page walk of the guest EPT page tables | |
440 | * [7:8] - Derived from [7:8] of real exit_qualification | |
441 | * | |
442 | * The other bits are set to 0. | |
443 | */ | |
444 | if (!(errcode & PFERR_RSVD_MASK)) { | |
445 | vcpu->arch.exit_qualification &= 0x187; | |
446 | vcpu->arch.exit_qualification |= ((pt_access & pte) & 0x7) << 3; | |
447 | } | |
448 | #endif | |
6389ee94 AK |
449 | walker->fault.address = addr; |
450 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 451 | |
8c28d031 | 452 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 453 | return 0; |
6aa8b732 AK |
454 | } |
455 | ||
1e301feb | 456 | static int FNAME(walk_addr)(struct guest_walker *walker, |
33770780 | 457 | struct kvm_vcpu *vcpu, gva_t addr, u32 access) |
1e301feb JR |
458 | { |
459 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr, | |
33770780 | 460 | access); |
1e301feb JR |
461 | } |
462 | ||
37406aaa | 463 | #if PTTYPE != PTTYPE_EPT |
6539e738 JR |
464 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
465 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 466 | u32 access) |
6539e738 JR |
467 | { |
468 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 469 | addr, access); |
6539e738 | 470 | } |
37406aaa | 471 | #endif |
6539e738 | 472 | |
bd6360cc XG |
473 | static bool |
474 | FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
475 | u64 *spte, pt_element_t gpte, bool no_dirty_log) | |
0028425f | 476 | { |
41074d07 | 477 | unsigned pte_access; |
bd6360cc | 478 | gfn_t gfn; |
ba049e93 | 479 | kvm_pfn_t pfn; |
0028425f | 480 | |
0ad805a0 | 481 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
bd6360cc | 482 | return false; |
407c61c6 | 483 | |
b8688d51 | 484 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
bd6360cc XG |
485 | |
486 | gfn = gpte_to_gfn(gpte); | |
0ad805a0 NHE |
487 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); |
488 | FNAME(protect_clean_gpte)(&pte_access, gpte); | |
bd6360cc XG |
489 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, |
490 | no_dirty_log && (pte_access & ACC_WRITE_MASK)); | |
81c52c56 | 491 | if (is_error_pfn(pfn)) |
bd6360cc | 492 | return false; |
0f53b5b1 | 493 | |
1403283a | 494 | /* |
bd6360cc XG |
495 | * we call mmu_set_spte() with host_writable = true because |
496 | * pte_prefetch_gfn_to_pfn always gets a writable pfn. | |
1403283a | 497 | */ |
029499b4 TY |
498 | mmu_set_spte(vcpu, spte, pte_access, 0, PT_PAGE_TABLE_LEVEL, gfn, pfn, |
499 | true, true); | |
bd6360cc XG |
500 | |
501 | return true; | |
502 | } | |
503 | ||
504 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
505 | u64 *spte, const void *pte) | |
506 | { | |
507 | pt_element_t gpte = *(const pt_element_t *)pte; | |
508 | ||
509 | FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false); | |
0028425f AK |
510 | } |
511 | ||
39c8c672 AK |
512 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
513 | struct guest_walker *gw, int level) | |
514 | { | |
39c8c672 | 515 | pt_element_t curr_pte; |
189be38d XG |
516 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
517 | u64 mask; | |
518 | int r, index; | |
519 | ||
520 | if (level == PT_PAGE_TABLE_LEVEL) { | |
521 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
522 | base_gpa = pte_gpa & ~mask; | |
523 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
524 | ||
54bf36aa | 525 | r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa, |
189be38d XG |
526 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); |
527 | curr_pte = gw->prefetch_ptes[index]; | |
528 | } else | |
54bf36aa | 529 | r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, |
39c8c672 | 530 | &curr_pte, sizeof(curr_pte)); |
189be38d | 531 | |
39c8c672 AK |
532 | return r || curr_pte != gw->ptes[level - 1]; |
533 | } | |
534 | ||
189be38d XG |
535 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
536 | u64 *sptep) | |
957ed9ef XG |
537 | { |
538 | struct kvm_mmu_page *sp; | |
189be38d | 539 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 540 | u64 *spte; |
189be38d | 541 | int i; |
957ed9ef XG |
542 | |
543 | sp = page_header(__pa(sptep)); | |
544 | ||
545 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
546 | return; | |
547 | ||
548 | if (sp->role.direct) | |
549 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
550 | ||
551 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
552 | spte = sp->spt + i; |
553 | ||
554 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
957ed9ef XG |
555 | if (spte == sptep) |
556 | continue; | |
557 | ||
c3707958 | 558 | if (is_shadow_present_pte(*spte)) |
957ed9ef XG |
559 | continue; |
560 | ||
bd6360cc | 561 | if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true)) |
957ed9ef | 562 | break; |
957ed9ef XG |
563 | } |
564 | } | |
565 | ||
6aa8b732 AK |
566 | /* |
567 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
d4878f24 XG |
568 | * If the guest tries to write a write-protected page, we need to |
569 | * emulate this operation, return 1 to indicate this case. | |
6aa8b732 | 570 | */ |
d4878f24 | 571 | static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
e7a04c99 | 572 | struct guest_walker *gw, |
c2288505 | 573 | int write_fault, int hlevel, |
ba049e93 | 574 | kvm_pfn_t pfn, bool map_writable, bool prefault) |
6aa8b732 | 575 | { |
5991b332 | 576 | struct kvm_mmu_page *sp = NULL; |
24157aaf | 577 | struct kvm_shadow_walk_iterator it; |
d4878f24 | 578 | unsigned direct_access, access = gw->pt_access; |
029499b4 | 579 | int top_level, emulate; |
abb9e0b8 | 580 | |
b36c7a7c | 581 | direct_access = gw->pte_access; |
84754cd8 | 582 | |
5991b332 AK |
583 | top_level = vcpu->arch.mmu.root_level; |
584 | if (top_level == PT32E_ROOT_LEVEL) | |
585 | top_level = PT32_ROOT_LEVEL; | |
586 | /* | |
587 | * Verify that the top-level gpte is still there. Since the page | |
588 | * is a root page, it is either write protected (and cannot be | |
589 | * changed from now on) or it is invalid (in which case, we don't | |
590 | * really care if it changes underneath us after this point). | |
591 | */ | |
592 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
593 | goto out_gpte_changed; | |
594 | ||
37f6a4e2 MT |
595 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
596 | goto out_gpte_changed; | |
597 | ||
24157aaf AK |
598 | for (shadow_walk_init(&it, vcpu, addr); |
599 | shadow_walk_okay(&it) && it.level > gw->level; | |
600 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
601 | gfn_t table_gfn; |
602 | ||
a30f47cb | 603 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 604 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 605 | |
5991b332 | 606 | sp = NULL; |
24157aaf AK |
607 | if (!is_shadow_present_pte(*it.sptep)) { |
608 | table_gfn = gw->table_gfn[it.level - 2]; | |
609 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
bb11c6c9 | 610 | false, access); |
5991b332 | 611 | } |
0b3c9333 AK |
612 | |
613 | /* | |
614 | * Verify that the gpte in the page we've just write | |
615 | * protected is still there. | |
616 | */ | |
24157aaf | 617 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 618 | goto out_gpte_changed; |
abb9e0b8 | 619 | |
5991b332 | 620 | if (sp) |
98bba238 | 621 | link_shadow_page(vcpu, it.sptep, sp); |
e7a04c99 | 622 | } |
050e6499 | 623 | |
0b3c9333 | 624 | for (; |
24157aaf AK |
625 | shadow_walk_okay(&it) && it.level > hlevel; |
626 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
627 | gfn_t direct_gfn; |
628 | ||
a30f47cb | 629 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 630 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 631 | |
24157aaf | 632 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 633 | |
24157aaf | 634 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
635 | continue; |
636 | ||
24157aaf | 637 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 638 | |
24157aaf | 639 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
bb11c6c9 | 640 | true, direct_access); |
98bba238 | 641 | link_shadow_page(vcpu, it.sptep, sp); |
0b3c9333 AK |
642 | } |
643 | ||
a30f47cb | 644 | clear_sp_write_flooding_count(it.sptep); |
029499b4 TY |
645 | emulate = mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault, |
646 | it.level, gw->gfn, pfn, prefault, map_writable); | |
189be38d | 647 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
0b3c9333 | 648 | |
d4878f24 | 649 | return emulate; |
0b3c9333 AK |
650 | |
651 | out_gpte_changed: | |
0b3c9333 | 652 | kvm_release_pfn_clean(pfn); |
d4878f24 | 653 | return 0; |
6aa8b732 AK |
654 | } |
655 | ||
7751babd XG |
656 | /* |
657 | * To see whether the mapped gfn can write its page table in the current | |
658 | * mapping. | |
659 | * | |
660 | * It is the helper function of FNAME(page_fault). When guest uses large page | |
661 | * size to map the writable gfn which is used as current page table, we should | |
662 | * force kvm to use small page size to map it because new shadow page will be | |
663 | * created when kvm establishes shadow page table that stop kvm using large | |
664 | * page size. Do it early can avoid unnecessary #PF and emulation. | |
665 | * | |
93c05d3e XG |
666 | * @write_fault_to_shadow_pgtable will return true if the fault gfn is |
667 | * currently used as its page table. | |
668 | * | |
7751babd XG |
669 | * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok |
670 | * since the PDPT is always shadowed, that means, we can not use large page | |
671 | * size to map the gfn which is used as PDPT. | |
672 | */ | |
673 | static bool | |
674 | FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu, | |
93c05d3e XG |
675 | struct guest_walker *walker, int user_fault, |
676 | bool *write_fault_to_shadow_pgtable) | |
7751babd XG |
677 | { |
678 | int level; | |
679 | gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1); | |
93c05d3e | 680 | bool self_changed = false; |
7751babd XG |
681 | |
682 | if (!(walker->pte_access & ACC_WRITE_MASK || | |
683 | (!is_write_protection(vcpu) && !user_fault))) | |
684 | return false; | |
685 | ||
93c05d3e XG |
686 | for (level = walker->level; level <= walker->max_level; level++) { |
687 | gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1]; | |
688 | ||
689 | self_changed |= !(gfn & mask); | |
690 | *write_fault_to_shadow_pgtable |= !gfn; | |
691 | } | |
7751babd | 692 | |
93c05d3e | 693 | return self_changed; |
7751babd XG |
694 | } |
695 | ||
6aa8b732 AK |
696 | /* |
697 | * Page fault handler. There are several causes for a page fault: | |
698 | * - there is no shadow pte for the guest pte | |
699 | * - write access through a shadow pte marked read only so that we can set | |
700 | * the dirty bit | |
701 | * - write access to a shadow pte marked read only so we can update the page | |
702 | * dirty bitmap, when userspace requests it | |
703 | * - mmio access; in this case we will never install a present shadow pte | |
704 | * - normal guest page fault due to the guest pte marked not present, not | |
705 | * writable, or not executable | |
706 | * | |
e2dec939 AK |
707 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
708 | * a negative value on error. | |
6aa8b732 | 709 | */ |
56028d08 | 710 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code, |
78b2c54a | 711 | bool prefault) |
6aa8b732 AK |
712 | { |
713 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
714 | int user_fault = error_code & PFERR_USER_MASK; |
715 | struct guest_walker walker; | |
e2dec939 | 716 | int r; |
ba049e93 | 717 | kvm_pfn_t pfn; |
7e4e4056 | 718 | int level = PT_PAGE_TABLE_LEVEL; |
8c85ac1c | 719 | bool force_pt_level = false; |
e930bffe | 720 | unsigned long mmu_seq; |
93c05d3e | 721 | bool map_writable, is_self_change_mapping; |
6aa8b732 | 722 | |
b8688d51 | 723 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 724 | |
e2dec939 AK |
725 | r = mmu_topup_memory_caches(vcpu); |
726 | if (r) | |
727 | return r; | |
714b93da | 728 | |
e9ee956e TY |
729 | /* |
730 | * If PFEC.RSVD is set, this is a shadow page fault. | |
731 | * The bit needs to be cleared before walking guest page tables. | |
732 | */ | |
733 | error_code &= ~PFERR_RSVD_MASK; | |
734 | ||
6aa8b732 | 735 | /* |
a8b876b1 | 736 | * Look up the guest pte for the faulting address. |
6aa8b732 | 737 | */ |
33770780 | 738 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
739 | |
740 | /* | |
741 | * The page is not mapped by the guest. Let the guest handle it. | |
742 | */ | |
7993ba43 | 743 | if (!r) { |
b8688d51 | 744 | pgprintk("%s: guest page fault\n", __func__); |
a30f47cb | 745 | if (!prefault) |
fb67e14f | 746 | inject_page_fault(vcpu, &walker.fault); |
a30f47cb | 747 | |
6aa8b732 AK |
748 | return 0; |
749 | } | |
750 | ||
e5691a81 XG |
751 | if (page_fault_handle_page_track(vcpu, error_code, walker.gfn)) { |
752 | shadow_page_table_clear_flood(vcpu, addr); | |
3d0c27ad | 753 | return 1; |
e5691a81 | 754 | } |
3d0c27ad | 755 | |
93c05d3e XG |
756 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
757 | ||
758 | is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu, | |
759 | &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable); | |
760 | ||
5ed5c5c8 | 761 | if (walker.level >= PT_DIRECTORY_LEVEL && !is_self_change_mapping) { |
fd136902 TY |
762 | level = mapping_level(vcpu, walker.gfn, &force_pt_level); |
763 | if (likely(!force_pt_level)) { | |
764 | level = min(walker.level, level); | |
5ed5c5c8 TY |
765 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); |
766 | } | |
767 | } else | |
cd1872f0 | 768 | force_pt_level = true; |
7e4e4056 | 769 | |
e930bffe | 770 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 771 | smp_rmb(); |
af585b92 | 772 | |
78b2c54a | 773 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 774 | &map_writable)) |
af585b92 | 775 | return 0; |
d7824fff | 776 | |
d7c55201 XG |
777 | if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr, |
778 | walker.gfn, pfn, walker.pte_access, &r)) | |
779 | return r; | |
780 | ||
c2288505 XG |
781 | /* |
782 | * Do not change pte_access if the pfn is a mmio page, otherwise | |
783 | * we will cache the incorrect access into mmio spte. | |
784 | */ | |
785 | if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) && | |
786 | !is_write_protection(vcpu) && !user_fault && | |
787 | !is_noslot_pfn(pfn)) { | |
788 | walker.pte_access |= ACC_WRITE_MASK; | |
789 | walker.pte_access &= ~ACC_USER_MASK; | |
790 | ||
791 | /* | |
792 | * If we converted a user page to a kernel page, | |
793 | * so that the kernel can write to it when cr0.wp=0, | |
794 | * then we should prevent the kernel from executing it | |
795 | * if SMEP is enabled. | |
796 | */ | |
797 | if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)) | |
798 | walker.pte_access &= ~ACC_EXEC_MASK; | |
799 | } | |
800 | ||
aaee2c94 | 801 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 802 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 803 | goto out_unlock; |
bc32ce21 | 804 | |
0375f7fa | 805 | kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
450e0b41 | 806 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
807 | if (!force_pt_level) |
808 | transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level); | |
c2288505 | 809 | r = FNAME(fetch)(vcpu, addr, &walker, write_fault, |
d4878f24 | 810 | level, pfn, map_writable, prefault); |
1165f5fe | 811 | ++vcpu->stat.pf_fixed; |
0375f7fa | 812 | kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
aaee2c94 | 813 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 814 | |
d4878f24 | 815 | return r; |
e930bffe AA |
816 | |
817 | out_unlock: | |
818 | spin_unlock(&vcpu->kvm->mmu_lock); | |
819 | kvm_release_pfn_clean(pfn); | |
820 | return 0; | |
6aa8b732 AK |
821 | } |
822 | ||
505aef8f XG |
823 | static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp) |
824 | { | |
825 | int offset = 0; | |
826 | ||
f71fa31f | 827 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
505aef8f XG |
828 | |
829 | if (PTTYPE == 32) | |
830 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
831 | ||
832 | return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); | |
833 | } | |
834 | ||
a461930b | 835 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) |
a7052897 | 836 | { |
a461930b | 837 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 838 | struct kvm_mmu_page *sp; |
a461930b AK |
839 | int level; |
840 | u64 *sptep; | |
841 | ||
bebb106a XG |
842 | vcpu_clear_mmio_info(vcpu, gva); |
843 | ||
f57f2ef5 XG |
844 | /* |
845 | * No need to check return value here, rmap_can_add() can | |
846 | * help us to skip pte prefetch later. | |
847 | */ | |
848 | mmu_topup_memory_caches(vcpu); | |
a7052897 | 849 | |
37f6a4e2 MT |
850 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) { |
851 | WARN_ON(1); | |
852 | return; | |
853 | } | |
854 | ||
f57f2ef5 | 855 | spin_lock(&vcpu->kvm->mmu_lock); |
a461930b AK |
856 | for_each_shadow_entry(vcpu, gva, iterator) { |
857 | level = iterator.level; | |
858 | sptep = iterator.sptep; | |
ad218f85 | 859 | |
f78978aa | 860 | sp = page_header(__pa(sptep)); |
884a0ff0 | 861 | if (is_last_spte(*sptep, level)) { |
f57f2ef5 XG |
862 | pt_element_t gpte; |
863 | gpa_t pte_gpa; | |
864 | ||
f78978aa XG |
865 | if (!sp->unsync) |
866 | break; | |
867 | ||
505aef8f | 868 | pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
08e850c6 | 869 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b | 870 | |
505aef8f XG |
871 | if (mmu_page_zap_pte(vcpu->kvm, sp, sptep)) |
872 | kvm_flush_remote_tlbs(vcpu->kvm); | |
f57f2ef5 XG |
873 | |
874 | if (!rmap_can_add(vcpu)) | |
875 | break; | |
876 | ||
54bf36aa PB |
877 | if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte, |
878 | sizeof(pt_element_t))) | |
f57f2ef5 XG |
879 | break; |
880 | ||
881 | FNAME(update_pte)(vcpu, sp, sptep, &gpte); | |
87917239 | 882 | } |
a7052897 | 883 | |
f78978aa | 884 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
885 | break; |
886 | } | |
ad218f85 | 887 | spin_unlock(&vcpu->kvm->mmu_lock); |
a7052897 MT |
888 | } |
889 | ||
1871c602 | 890 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
ab9ae313 | 891 | struct x86_exception *exception) |
6aa8b732 AK |
892 | { |
893 | struct guest_walker walker; | |
e119d117 AK |
894 | gpa_t gpa = UNMAPPED_GVA; |
895 | int r; | |
6aa8b732 | 896 | |
33770780 | 897 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, access); |
6aa8b732 | 898 | |
e119d117 | 899 | if (r) { |
1755fbcc | 900 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 901 | gpa |= vaddr & ~PAGE_MASK; |
8c28d031 AK |
902 | } else if (exception) |
903 | *exception = walker.fault; | |
6aa8b732 AK |
904 | |
905 | return gpa; | |
906 | } | |
907 | ||
37406aaa | 908 | #if PTTYPE != PTTYPE_EPT |
6539e738 | 909 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
910 | u32 access, |
911 | struct x86_exception *exception) | |
6539e738 JR |
912 | { |
913 | struct guest_walker walker; | |
914 | gpa_t gpa = UNMAPPED_GVA; | |
915 | int r; | |
916 | ||
33770780 | 917 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
918 | |
919 | if (r) { | |
920 | gpa = gfn_to_gpa(walker.gfn); | |
921 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
922 | } else if (exception) |
923 | *exception = walker.fault; | |
6539e738 JR |
924 | |
925 | return gpa; | |
926 | } | |
37406aaa | 927 | #endif |
6539e738 | 928 | |
e8bc217a MT |
929 | /* |
930 | * Using the cached information from sp->gfns is safe because: | |
931 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
932 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
933 | * |
934 | * Note: | |
935 | * We should flush all tlbs if spte is dropped even though guest is | |
936 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
937 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
938 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
939 | * freed pages. | |
a086f6a1 | 940 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. |
e8bc217a | 941 | */ |
a4a8e6f7 | 942 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a | 943 | { |
505aef8f | 944 | int i, nr_present = 0; |
9bdbba13 | 945 | bool host_writable; |
51fb60d8 | 946 | gpa_t first_pte_gpa; |
e8bc217a | 947 | |
2032a93d LJ |
948 | /* direct kvm_mmu_page can not be unsync. */ |
949 | BUG_ON(sp->role.direct); | |
950 | ||
505aef8f | 951 | first_pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
51fb60d8 | 952 | |
e8bc217a MT |
953 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
954 | unsigned pte_access; | |
955 | pt_element_t gpte; | |
956 | gpa_t pte_gpa; | |
f55c3f41 | 957 | gfn_t gfn; |
e8bc217a | 958 | |
ce88decf | 959 | if (!sp->spt[i]) |
e8bc217a MT |
960 | continue; |
961 | ||
51fb60d8 | 962 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a | 963 | |
54bf36aa PB |
964 | if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte, |
965 | sizeof(pt_element_t))) | |
1f50f1b3 | 966 | return 0; |
e8bc217a | 967 | |
0ad805a0 | 968 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { |
7bfdf217 LT |
969 | /* |
970 | * Update spte before increasing tlbs_dirty to make | |
971 | * sure no tlb flush is lost after spte is zapped; see | |
972 | * the comments in kvm_flush_remote_tlbs(). | |
973 | */ | |
974 | smp_wmb(); | |
a086f6a1 | 975 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
976 | continue; |
977 | } | |
978 | ||
ce88decf XG |
979 | gfn = gpte_to_gfn(gpte); |
980 | pte_access = sp->role.access; | |
0ad805a0 NHE |
981 | pte_access &= FNAME(gpte_access)(vcpu, gpte); |
982 | FNAME(protect_clean_gpte)(&pte_access, gpte); | |
ce88decf | 983 | |
54bf36aa | 984 | if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access, |
f2fd125d | 985 | &nr_present)) |
ce88decf XG |
986 | continue; |
987 | ||
407c61c6 | 988 | if (gfn != sp->gfns[i]) { |
c3707958 | 989 | drop_spte(vcpu->kvm, &sp->spt[i]); |
7bfdf217 LT |
990 | /* |
991 | * The same as above where we are doing | |
992 | * prefetch_invalid_gpte(). | |
993 | */ | |
994 | smp_wmb(); | |
a086f6a1 | 995 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
996 | continue; |
997 | } | |
998 | ||
999 | nr_present++; | |
ce88decf | 1000 | |
f8e453b0 XG |
1001 | host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE; |
1002 | ||
c2288505 | 1003 | set_spte(vcpu, &sp->spt[i], pte_access, |
640d9b0d | 1004 | PT_PAGE_TABLE_LEVEL, gfn, |
1403283a | 1005 | spte_to_pfn(sp->spt[i]), true, false, |
9bdbba13 | 1006 | host_writable); |
e8bc217a MT |
1007 | } |
1008 | ||
1f50f1b3 | 1009 | return nr_present; |
e8bc217a MT |
1010 | } |
1011 | ||
6aa8b732 AK |
1012 | #undef pt_element_t |
1013 | #undef guest_walker | |
1014 | #undef FNAME | |
1015 | #undef PT_BASE_ADDR_MASK | |
1016 | #undef PT_INDEX | |
e04da980 JR |
1017 | #undef PT_LVL_ADDR_MASK |
1018 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 1019 | #undef PT_LEVEL_BITS |
cea0f0e7 | 1020 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 1021 | #undef gpte_to_gfn |
e04da980 | 1022 | #undef gpte_to_gfn_lvl |
b3e4e63f | 1023 | #undef CMPXCHG |
d8089bac GN |
1024 | #undef PT_GUEST_ACCESSED_MASK |
1025 | #undef PT_GUEST_DIRTY_MASK | |
1026 | #undef PT_GUEST_DIRTY_SHIFT | |
1027 | #undef PT_GUEST_ACCESSED_SHIFT |