Commit | Line | Data |
---|---|---|
6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
e495606d | 25 | |
edf88417 | 26 | #include <linux/kvm_host.h> |
6aa8b732 AK |
27 | #include <linux/types.h> |
28 | #include <linux/string.h> | |
6aa8b732 AK |
29 | #include <linux/mm.h> |
30 | #include <linux/highmem.h> | |
31 | #include <linux/module.h> | |
448353ca | 32 | #include <linux/swap.h> |
05da4558 | 33 | #include <linux/hugetlb.h> |
2f333bcb | 34 | #include <linux/compiler.h> |
bc6678a3 | 35 | #include <linux/srcu.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
bf998156 | 37 | #include <linux/uaccess.h> |
6aa8b732 | 38 | |
e495606d AK |
39 | #include <asm/page.h> |
40 | #include <asm/cmpxchg.h> | |
4e542370 | 41 | #include <asm/io.h> |
13673a90 | 42 | #include <asm/vmx.h> |
6aa8b732 | 43 | |
18552672 JR |
44 | /* |
45 | * When setting this variable to true it enables Two-Dimensional-Paging | |
46 | * where the hardware walks 2 page tables: | |
47 | * 1. the guest-virtual to guest-physical | |
48 | * 2. while doing 1. it walks guest-physical to host-physical | |
49 | * If the hardware supports that we don't need to do shadow paging. | |
50 | */ | |
2f333bcb | 51 | bool tdp_enabled = false; |
18552672 | 52 | |
8b1fe17c XG |
53 | enum { |
54 | AUDIT_PRE_PAGE_FAULT, | |
55 | AUDIT_POST_PAGE_FAULT, | |
56 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
57 | AUDIT_POST_PTE_WRITE, |
58 | AUDIT_PRE_SYNC, | |
59 | AUDIT_POST_SYNC | |
8b1fe17c | 60 | }; |
37a7d8b0 | 61 | |
8b1fe17c | 62 | #undef MMU_DEBUG |
37a7d8b0 AK |
63 | |
64 | #ifdef MMU_DEBUG | |
65 | ||
66 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
67 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
68 | ||
69 | #else | |
70 | ||
71 | #define pgprintk(x...) do { } while (0) | |
72 | #define rmap_printk(x...) do { } while (0) | |
73 | ||
74 | #endif | |
75 | ||
8b1fe17c | 76 | #ifdef MMU_DEBUG |
476bc001 | 77 | static bool dbg = 0; |
6ada8cca | 78 | module_param(dbg, bool, 0644); |
37a7d8b0 | 79 | #endif |
6aa8b732 | 80 | |
d6c69ee9 YD |
81 | #ifndef MMU_DEBUG |
82 | #define ASSERT(x) do { } while (0) | |
83 | #else | |
6aa8b732 AK |
84 | #define ASSERT(x) \ |
85 | if (!(x)) { \ | |
86 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
87 | __FILE__, __LINE__, #x); \ | |
88 | } | |
d6c69ee9 | 89 | #endif |
6aa8b732 | 90 | |
957ed9ef XG |
91 | #define PTE_PREFETCH_NUM 8 |
92 | ||
00763e41 | 93 | #define PT_FIRST_AVAIL_BITS_SHIFT 10 |
6aa8b732 AK |
94 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 |
95 | ||
6aa8b732 AK |
96 | #define PT64_LEVEL_BITS 9 |
97 | ||
98 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 99 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 100 | |
6aa8b732 AK |
101 | #define PT64_INDEX(address, level)\ |
102 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
103 | ||
104 | ||
105 | #define PT32_LEVEL_BITS 10 | |
106 | ||
107 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 108 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 109 | |
e04da980 JR |
110 | #define PT32_LVL_OFFSET_MASK(level) \ |
111 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
112 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
113 | |
114 | #define PT32_INDEX(address, level)\ | |
115 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
116 | ||
117 | ||
27aba766 | 118 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
119 | #define PT64_DIR_BASE_ADDR_MASK \ |
120 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
121 | #define PT64_LVL_ADDR_MASK(level) \ |
122 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
123 | * PT64_LEVEL_BITS))) - 1)) | |
124 | #define PT64_LVL_OFFSET_MASK(level) \ | |
125 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
126 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
127 | |
128 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
129 | #define PT32_DIR_BASE_ADDR_MASK \ | |
130 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
131 | #define PT32_LVL_ADDR_MASK(level) \ |
132 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
133 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 134 | |
79539cec AK |
135 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
136 | | PT64_NX_MASK) | |
6aa8b732 | 137 | |
fe135d2c AK |
138 | #define ACC_EXEC_MASK 1 |
139 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
140 | #define ACC_USER_MASK PT_USER_MASK | |
141 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
142 | ||
90bb6fc5 AK |
143 | #include <trace/events/kvm.h> |
144 | ||
07420171 AK |
145 | #define CREATE_TRACE_POINTS |
146 | #include "mmutrace.h" | |
147 | ||
49fde340 XG |
148 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
149 | #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1)) | |
1403283a | 150 | |
135f8c2b AK |
151 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
152 | ||
220f773a TY |
153 | /* make pte_list_desc fit well in cache line */ |
154 | #define PTE_LIST_EXT 3 | |
155 | ||
53c07b18 XG |
156 | struct pte_list_desc { |
157 | u64 *sptes[PTE_LIST_EXT]; | |
158 | struct pte_list_desc *more; | |
cd4a4e53 AK |
159 | }; |
160 | ||
2d11123a AK |
161 | struct kvm_shadow_walk_iterator { |
162 | u64 addr; | |
163 | hpa_t shadow_addr; | |
2d11123a | 164 | u64 *sptep; |
dd3bfd59 | 165 | int level; |
2d11123a AK |
166 | unsigned index; |
167 | }; | |
168 | ||
169 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
170 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
171 | shadow_walk_okay(&(_walker)); \ | |
172 | shadow_walk_next(&(_walker))) | |
173 | ||
c2a2ac2b XG |
174 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
175 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
176 | shadow_walk_okay(&(_walker)) && \ | |
177 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
178 | __shadow_walk_next(&(_walker), spte)) | |
179 | ||
53c07b18 | 180 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 181 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 182 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 183 | |
7b52345e SY |
184 | static u64 __read_mostly shadow_nx_mask; |
185 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
186 | static u64 __read_mostly shadow_user_mask; | |
187 | static u64 __read_mostly shadow_accessed_mask; | |
188 | static u64 __read_mostly shadow_dirty_mask; | |
ce88decf XG |
189 | static u64 __read_mostly shadow_mmio_mask; |
190 | ||
191 | static void mmu_spte_set(u64 *sptep, u64 spte); | |
e676505a | 192 | static void mmu_free_roots(struct kvm_vcpu *vcpu); |
ce88decf XG |
193 | |
194 | void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask) | |
195 | { | |
196 | shadow_mmio_mask = mmio_mask; | |
197 | } | |
198 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); | |
199 | ||
f2fd125d XG |
200 | /* |
201 | * spte bits of bit 3 ~ bit 11 are used as low 9 bits of generation number, | |
202 | * the bits of bits 52 ~ bit 61 are used as high 10 bits of generation | |
203 | * number. | |
204 | */ | |
205 | #define MMIO_SPTE_GEN_LOW_SHIFT 3 | |
206 | #define MMIO_SPTE_GEN_HIGH_SHIFT 52 | |
207 | ||
f8f55942 | 208 | #define MMIO_GEN_SHIFT 19 |
f2fd125d XG |
209 | #define MMIO_GEN_LOW_SHIFT 9 |
210 | #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 1) | |
f8f55942 XG |
211 | #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1) |
212 | #define MMIO_MAX_GEN ((1 << MMIO_GEN_SHIFT) - 1) | |
f2fd125d XG |
213 | |
214 | static u64 generation_mmio_spte_mask(unsigned int gen) | |
215 | { | |
216 | u64 mask; | |
217 | ||
218 | WARN_ON(gen > MMIO_MAX_GEN); | |
219 | ||
220 | mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT; | |
221 | mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT; | |
222 | return mask; | |
223 | } | |
224 | ||
225 | static unsigned int get_mmio_spte_generation(u64 spte) | |
226 | { | |
227 | unsigned int gen; | |
228 | ||
229 | spte &= ~shadow_mmio_mask; | |
230 | ||
231 | gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK; | |
232 | gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT; | |
233 | return gen; | |
234 | } | |
235 | ||
f8f55942 XG |
236 | static unsigned int kvm_current_mmio_generation(struct kvm *kvm) |
237 | { | |
238 | return kvm_memslots(kvm)->generation & MMIO_GEN_MASK; | |
239 | } | |
240 | ||
f2fd125d XG |
241 | static void mark_mmio_spte(struct kvm *kvm, u64 *sptep, u64 gfn, |
242 | unsigned access) | |
ce88decf | 243 | { |
95b0430d | 244 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); |
f8f55942 XG |
245 | unsigned int gen = kvm_current_mmio_generation(kvm); |
246 | u64 mask = generation_mmio_spte_mask(gen); | |
95b0430d | 247 | |
ce88decf | 248 | access &= ACC_WRITE_MASK | ACC_USER_MASK; |
f2fd125d | 249 | mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT; |
95b0430d | 250 | sp->mmio_cached = true; |
f2fd125d | 251 | |
f8f55942 | 252 | trace_mark_mmio_spte(sptep, gfn, access, gen); |
f2fd125d | 253 | mmu_spte_set(sptep, mask); |
ce88decf XG |
254 | } |
255 | ||
256 | static bool is_mmio_spte(u64 spte) | |
257 | { | |
258 | return (spte & shadow_mmio_mask) == shadow_mmio_mask; | |
259 | } | |
260 | ||
261 | static gfn_t get_mmio_spte_gfn(u64 spte) | |
262 | { | |
f2fd125d XG |
263 | u64 mask = generation_mmio_spte_mask(MMIO_MAX_GEN) | shadow_mmio_mask; |
264 | return (spte & ~mask) >> PAGE_SHIFT; | |
ce88decf XG |
265 | } |
266 | ||
267 | static unsigned get_mmio_spte_access(u64 spte) | |
268 | { | |
f2fd125d XG |
269 | u64 mask = generation_mmio_spte_mask(MMIO_MAX_GEN) | shadow_mmio_mask; |
270 | return (spte & ~mask) & ~PAGE_MASK; | |
ce88decf XG |
271 | } |
272 | ||
f2fd125d XG |
273 | static bool set_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn, |
274 | pfn_t pfn, unsigned access) | |
ce88decf XG |
275 | { |
276 | if (unlikely(is_noslot_pfn(pfn))) { | |
f2fd125d | 277 | mark_mmio_spte(kvm, sptep, gfn, access); |
ce88decf XG |
278 | return true; |
279 | } | |
280 | ||
281 | return false; | |
282 | } | |
c7addb90 | 283 | |
f8f55942 XG |
284 | static bool check_mmio_spte(struct kvm *kvm, u64 spte) |
285 | { | |
286 | return likely(get_mmio_spte_generation(spte) == | |
287 | kvm_current_mmio_generation(kvm)); | |
288 | } | |
289 | ||
82725b20 DE |
290 | static inline u64 rsvd_bits(int s, int e) |
291 | { | |
292 | return ((1ULL << (e - s + 1)) - 1) << s; | |
293 | } | |
294 | ||
7b52345e | 295 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 296 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
297 | { |
298 | shadow_user_mask = user_mask; | |
299 | shadow_accessed_mask = accessed_mask; | |
300 | shadow_dirty_mask = dirty_mask; | |
301 | shadow_nx_mask = nx_mask; | |
302 | shadow_x_mask = x_mask; | |
303 | } | |
304 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
305 | ||
6aa8b732 AK |
306 | static int is_cpuid_PSE36(void) |
307 | { | |
308 | return 1; | |
309 | } | |
310 | ||
73b1087e AK |
311 | static int is_nx(struct kvm_vcpu *vcpu) |
312 | { | |
f6801dff | 313 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
314 | } |
315 | ||
c7addb90 AK |
316 | static int is_shadow_present_pte(u64 pte) |
317 | { | |
ce88decf | 318 | return pte & PT_PRESENT_MASK && !is_mmio_spte(pte); |
c7addb90 AK |
319 | } |
320 | ||
05da4558 MT |
321 | static int is_large_pte(u64 pte) |
322 | { | |
323 | return pte & PT_PAGE_SIZE_MASK; | |
324 | } | |
325 | ||
43a3795a | 326 | static int is_dirty_gpte(unsigned long pte) |
e3c5e7ec | 327 | { |
439e218a | 328 | return pte & PT_DIRTY_MASK; |
e3c5e7ec AK |
329 | } |
330 | ||
43a3795a | 331 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 332 | { |
4b1a80fa | 333 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
334 | } |
335 | ||
776e6633 MT |
336 | static int is_last_spte(u64 pte, int level) |
337 | { | |
338 | if (level == PT_PAGE_TABLE_LEVEL) | |
339 | return 1; | |
852e3c19 | 340 | if (is_large_pte(pte)) |
776e6633 MT |
341 | return 1; |
342 | return 0; | |
343 | } | |
344 | ||
35149e21 | 345 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 346 | { |
35149e21 | 347 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
348 | } |
349 | ||
da928521 AK |
350 | static gfn_t pse36_gfn_delta(u32 gpte) |
351 | { | |
352 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
353 | ||
354 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
355 | } | |
356 | ||
603e0651 | 357 | #ifdef CONFIG_X86_64 |
d555c333 | 358 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 359 | { |
603e0651 | 360 | *sptep = spte; |
e663ee64 AK |
361 | } |
362 | ||
603e0651 | 363 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 364 | { |
603e0651 XG |
365 | *sptep = spte; |
366 | } | |
367 | ||
368 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
369 | { | |
370 | return xchg(sptep, spte); | |
371 | } | |
c2a2ac2b XG |
372 | |
373 | static u64 __get_spte_lockless(u64 *sptep) | |
374 | { | |
375 | return ACCESS_ONCE(*sptep); | |
376 | } | |
ce88decf XG |
377 | |
378 | static bool __check_direct_spte_mmio_pf(u64 spte) | |
379 | { | |
380 | /* It is valid if the spte is zapped. */ | |
381 | return spte == 0ull; | |
382 | } | |
a9221dd5 | 383 | #else |
603e0651 XG |
384 | union split_spte { |
385 | struct { | |
386 | u32 spte_low; | |
387 | u32 spte_high; | |
388 | }; | |
389 | u64 spte; | |
390 | }; | |
a9221dd5 | 391 | |
c2a2ac2b XG |
392 | static void count_spte_clear(u64 *sptep, u64 spte) |
393 | { | |
394 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
395 | ||
396 | if (is_shadow_present_pte(spte)) | |
397 | return; | |
398 | ||
399 | /* Ensure the spte is completely set before we increase the count */ | |
400 | smp_wmb(); | |
401 | sp->clear_spte_count++; | |
402 | } | |
403 | ||
603e0651 XG |
404 | static void __set_spte(u64 *sptep, u64 spte) |
405 | { | |
406 | union split_spte *ssptep, sspte; | |
a9221dd5 | 407 | |
603e0651 XG |
408 | ssptep = (union split_spte *)sptep; |
409 | sspte = (union split_spte)spte; | |
410 | ||
411 | ssptep->spte_high = sspte.spte_high; | |
412 | ||
413 | /* | |
414 | * If we map the spte from nonpresent to present, We should store | |
415 | * the high bits firstly, then set present bit, so cpu can not | |
416 | * fetch this spte while we are setting the spte. | |
417 | */ | |
418 | smp_wmb(); | |
419 | ||
420 | ssptep->spte_low = sspte.spte_low; | |
a9221dd5 AK |
421 | } |
422 | ||
603e0651 XG |
423 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
424 | { | |
425 | union split_spte *ssptep, sspte; | |
426 | ||
427 | ssptep = (union split_spte *)sptep; | |
428 | sspte = (union split_spte)spte; | |
429 | ||
430 | ssptep->spte_low = sspte.spte_low; | |
431 | ||
432 | /* | |
433 | * If we map the spte from present to nonpresent, we should clear | |
434 | * present bit firstly to avoid vcpu fetch the old high bits. | |
435 | */ | |
436 | smp_wmb(); | |
437 | ||
438 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 439 | count_spte_clear(sptep, spte); |
603e0651 XG |
440 | } |
441 | ||
442 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
443 | { | |
444 | union split_spte *ssptep, sspte, orig; | |
445 | ||
446 | ssptep = (union split_spte *)sptep; | |
447 | sspte = (union split_spte)spte; | |
448 | ||
449 | /* xchg acts as a barrier before the setting of the high bits */ | |
450 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
451 | orig.spte_high = ssptep->spte_high; |
452 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 453 | count_spte_clear(sptep, spte); |
603e0651 XG |
454 | |
455 | return orig.spte; | |
456 | } | |
c2a2ac2b XG |
457 | |
458 | /* | |
459 | * The idea using the light way get the spte on x86_32 guest is from | |
460 | * gup_get_pte(arch/x86/mm/gup.c). | |
461 | * The difference is we can not catch the spte tlb flush if we leave | |
462 | * guest mode, so we emulate it by increase clear_spte_count when spte | |
463 | * is cleared. | |
464 | */ | |
465 | static u64 __get_spte_lockless(u64 *sptep) | |
466 | { | |
467 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
468 | union split_spte spte, *orig = (union split_spte *)sptep; | |
469 | int count; | |
470 | ||
471 | retry: | |
472 | count = sp->clear_spte_count; | |
473 | smp_rmb(); | |
474 | ||
475 | spte.spte_low = orig->spte_low; | |
476 | smp_rmb(); | |
477 | ||
478 | spte.spte_high = orig->spte_high; | |
479 | smp_rmb(); | |
480 | ||
481 | if (unlikely(spte.spte_low != orig->spte_low || | |
482 | count != sp->clear_spte_count)) | |
483 | goto retry; | |
484 | ||
485 | return spte.spte; | |
486 | } | |
ce88decf XG |
487 | |
488 | static bool __check_direct_spte_mmio_pf(u64 spte) | |
489 | { | |
490 | union split_spte sspte = (union split_spte)spte; | |
491 | u32 high_mmio_mask = shadow_mmio_mask >> 32; | |
492 | ||
493 | /* It is valid if the spte is zapped. */ | |
494 | if (spte == 0ull) | |
495 | return true; | |
496 | ||
497 | /* It is valid if the spte is being zapped. */ | |
498 | if (sspte.spte_low == 0ull && | |
499 | (sspte.spte_high & high_mmio_mask) == high_mmio_mask) | |
500 | return true; | |
501 | ||
502 | return false; | |
503 | } | |
603e0651 XG |
504 | #endif |
505 | ||
c7ba5b48 XG |
506 | static bool spte_is_locklessly_modifiable(u64 spte) |
507 | { | |
feb3eb70 GN |
508 | return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) == |
509 | (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE); | |
c7ba5b48 XG |
510 | } |
511 | ||
8672b721 XG |
512 | static bool spte_has_volatile_bits(u64 spte) |
513 | { | |
c7ba5b48 XG |
514 | /* |
515 | * Always atomicly update spte if it can be updated | |
516 | * out of mmu-lock, it can ensure dirty bit is not lost, | |
517 | * also, it can help us to get a stable is_writable_pte() | |
518 | * to ensure tlb flush is not missed. | |
519 | */ | |
520 | if (spte_is_locklessly_modifiable(spte)) | |
521 | return true; | |
522 | ||
8672b721 XG |
523 | if (!shadow_accessed_mask) |
524 | return false; | |
525 | ||
526 | if (!is_shadow_present_pte(spte)) | |
527 | return false; | |
528 | ||
4132779b XG |
529 | if ((spte & shadow_accessed_mask) && |
530 | (!is_writable_pte(spte) || (spte & shadow_dirty_mask))) | |
8672b721 XG |
531 | return false; |
532 | ||
533 | return true; | |
534 | } | |
535 | ||
4132779b XG |
536 | static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask) |
537 | { | |
538 | return (old_spte & bit_mask) && !(new_spte & bit_mask); | |
539 | } | |
540 | ||
1df9f2dc XG |
541 | /* Rules for using mmu_spte_set: |
542 | * Set the sptep from nonpresent to present. | |
543 | * Note: the sptep being assigned *must* be either not present | |
544 | * or in a state where the hardware will not attempt to update | |
545 | * the spte. | |
546 | */ | |
547 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
548 | { | |
549 | WARN_ON(is_shadow_present_pte(*sptep)); | |
550 | __set_spte(sptep, new_spte); | |
551 | } | |
552 | ||
553 | /* Rules for using mmu_spte_update: | |
554 | * Update the state bits, it means the mapped pfn is not changged. | |
6e7d0354 XG |
555 | * |
556 | * Whenever we overwrite a writable spte with a read-only one we | |
557 | * should flush remote TLBs. Otherwise rmap_write_protect | |
558 | * will find a read-only spte, even though the writable spte | |
559 | * might be cached on a CPU's TLB, the return value indicates this | |
560 | * case. | |
1df9f2dc | 561 | */ |
6e7d0354 | 562 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) |
b79b93f9 | 563 | { |
c7ba5b48 | 564 | u64 old_spte = *sptep; |
6e7d0354 | 565 | bool ret = false; |
4132779b XG |
566 | |
567 | WARN_ON(!is_rmap_spte(new_spte)); | |
b79b93f9 | 568 | |
6e7d0354 XG |
569 | if (!is_shadow_present_pte(old_spte)) { |
570 | mmu_spte_set(sptep, new_spte); | |
571 | return ret; | |
572 | } | |
4132779b | 573 | |
c7ba5b48 | 574 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 575 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 576 | else |
603e0651 | 577 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 578 | |
c7ba5b48 XG |
579 | /* |
580 | * For the spte updated out of mmu-lock is safe, since | |
581 | * we always atomicly update it, see the comments in | |
582 | * spte_has_volatile_bits(). | |
583 | */ | |
6e7d0354 XG |
584 | if (is_writable_pte(old_spte) && !is_writable_pte(new_spte)) |
585 | ret = true; | |
586 | ||
4132779b | 587 | if (!shadow_accessed_mask) |
6e7d0354 | 588 | return ret; |
4132779b XG |
589 | |
590 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask)) | |
591 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); | |
592 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask)) | |
593 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); | |
6e7d0354 XG |
594 | |
595 | return ret; | |
b79b93f9 AK |
596 | } |
597 | ||
1df9f2dc XG |
598 | /* |
599 | * Rules for using mmu_spte_clear_track_bits: | |
600 | * It sets the sptep from present to nonpresent, and track the | |
601 | * state bits, it is used to clear the last level sptep. | |
602 | */ | |
603 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
604 | { | |
605 | pfn_t pfn; | |
606 | u64 old_spte = *sptep; | |
607 | ||
608 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 609 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 610 | else |
603e0651 | 611 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc XG |
612 | |
613 | if (!is_rmap_spte(old_spte)) | |
614 | return 0; | |
615 | ||
616 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
617 | |
618 | /* | |
619 | * KVM does not hold the refcount of the page used by | |
620 | * kvm mmu, before reclaiming the page, we should | |
621 | * unmap it from mmu first. | |
622 | */ | |
623 | WARN_ON(!kvm_is_mmio_pfn(pfn) && !page_count(pfn_to_page(pfn))); | |
624 | ||
1df9f2dc XG |
625 | if (!shadow_accessed_mask || old_spte & shadow_accessed_mask) |
626 | kvm_set_pfn_accessed(pfn); | |
627 | if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask)) | |
628 | kvm_set_pfn_dirty(pfn); | |
629 | return 1; | |
630 | } | |
631 | ||
632 | /* | |
633 | * Rules for using mmu_spte_clear_no_track: | |
634 | * Directly clear spte without caring the state bits of sptep, | |
635 | * it is used to set the upper level spte. | |
636 | */ | |
637 | static void mmu_spte_clear_no_track(u64 *sptep) | |
638 | { | |
603e0651 | 639 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
640 | } |
641 | ||
c2a2ac2b XG |
642 | static u64 mmu_spte_get_lockless(u64 *sptep) |
643 | { | |
644 | return __get_spte_lockless(sptep); | |
645 | } | |
646 | ||
647 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) | |
648 | { | |
c142786c AK |
649 | /* |
650 | * Prevent page table teardown by making any free-er wait during | |
651 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
652 | */ | |
653 | local_irq_disable(); | |
654 | vcpu->mode = READING_SHADOW_PAGE_TABLES; | |
655 | /* | |
656 | * Make sure a following spte read is not reordered ahead of the write | |
657 | * to vcpu->mode. | |
658 | */ | |
659 | smp_mb(); | |
c2a2ac2b XG |
660 | } |
661 | ||
662 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
663 | { | |
c142786c AK |
664 | /* |
665 | * Make sure the write to vcpu->mode is not reordered in front of | |
666 | * reads to sptes. If it does, kvm_commit_zap_page() can see us | |
667 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. | |
668 | */ | |
669 | smp_mb(); | |
670 | vcpu->mode = OUTSIDE_GUEST_MODE; | |
671 | local_irq_enable(); | |
c2a2ac2b XG |
672 | } |
673 | ||
e2dec939 | 674 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 675 | struct kmem_cache *base_cache, int min) |
714b93da AK |
676 | { |
677 | void *obj; | |
678 | ||
679 | if (cache->nobjs >= min) | |
e2dec939 | 680 | return 0; |
714b93da | 681 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 682 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 683 | if (!obj) |
e2dec939 | 684 | return -ENOMEM; |
714b93da AK |
685 | cache->objects[cache->nobjs++] = obj; |
686 | } | |
e2dec939 | 687 | return 0; |
714b93da AK |
688 | } |
689 | ||
f759e2b4 XG |
690 | static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache) |
691 | { | |
692 | return cache->nobjs; | |
693 | } | |
694 | ||
e8ad9a70 XG |
695 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
696 | struct kmem_cache *cache) | |
714b93da AK |
697 | { |
698 | while (mc->nobjs) | |
e8ad9a70 | 699 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
700 | } |
701 | ||
c1158e63 | 702 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 703 | int min) |
c1158e63 | 704 | { |
842f22ed | 705 | void *page; |
c1158e63 AK |
706 | |
707 | if (cache->nobjs >= min) | |
708 | return 0; | |
709 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
842f22ed | 710 | page = (void *)__get_free_page(GFP_KERNEL); |
c1158e63 AK |
711 | if (!page) |
712 | return -ENOMEM; | |
842f22ed | 713 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
714 | } |
715 | return 0; | |
716 | } | |
717 | ||
718 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
719 | { | |
720 | while (mc->nobjs) | |
c4d198d5 | 721 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
722 | } |
723 | ||
2e3e5882 | 724 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 725 | { |
e2dec939 AK |
726 | int r; |
727 | ||
53c07b18 | 728 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 729 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
730 | if (r) |
731 | goto out; | |
ad312c7c | 732 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
733 | if (r) |
734 | goto out; | |
ad312c7c | 735 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 736 | mmu_page_header_cache, 4); |
e2dec939 AK |
737 | out: |
738 | return r; | |
714b93da AK |
739 | } |
740 | ||
741 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
742 | { | |
53c07b18 XG |
743 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
744 | pte_list_desc_cache); | |
ad312c7c | 745 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
746 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
747 | mmu_page_header_cache); | |
714b93da AK |
748 | } |
749 | ||
80feb89a | 750 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) |
714b93da AK |
751 | { |
752 | void *p; | |
753 | ||
754 | BUG_ON(!mc->nobjs); | |
755 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
756 | return p; |
757 | } | |
758 | ||
53c07b18 | 759 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 760 | { |
80feb89a | 761 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
762 | } |
763 | ||
53c07b18 | 764 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 765 | { |
53c07b18 | 766 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
767 | } |
768 | ||
2032a93d LJ |
769 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
770 | { | |
771 | if (!sp->role.direct) | |
772 | return sp->gfns[index]; | |
773 | ||
774 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
775 | } | |
776 | ||
777 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
778 | { | |
779 | if (sp->role.direct) | |
780 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
781 | else | |
782 | sp->gfns[index] = gfn; | |
783 | } | |
784 | ||
05da4558 | 785 | /* |
d4dbf470 TY |
786 | * Return the pointer to the large page information for a given gfn, |
787 | * handling slots that are not large page aligned. | |
05da4558 | 788 | */ |
d4dbf470 TY |
789 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
790 | struct kvm_memory_slot *slot, | |
791 | int level) | |
05da4558 MT |
792 | { |
793 | unsigned long idx; | |
794 | ||
fb03cb6f | 795 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 796 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
797 | } |
798 | ||
799 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
800 | { | |
d25797b2 | 801 | struct kvm_memory_slot *slot; |
d4dbf470 | 802 | struct kvm_lpage_info *linfo; |
d25797b2 | 803 | int i; |
05da4558 | 804 | |
a1f4d395 | 805 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
806 | for (i = PT_DIRECTORY_LEVEL; |
807 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
808 | linfo = lpage_info_slot(gfn, slot, i); |
809 | linfo->write_count += 1; | |
d25797b2 | 810 | } |
332b207d | 811 | kvm->arch.indirect_shadow_pages++; |
05da4558 MT |
812 | } |
813 | ||
814 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
815 | { | |
d25797b2 | 816 | struct kvm_memory_slot *slot; |
d4dbf470 | 817 | struct kvm_lpage_info *linfo; |
d25797b2 | 818 | int i; |
05da4558 | 819 | |
a1f4d395 | 820 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
821 | for (i = PT_DIRECTORY_LEVEL; |
822 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
823 | linfo = lpage_info_slot(gfn, slot, i); |
824 | linfo->write_count -= 1; | |
825 | WARN_ON(linfo->write_count < 0); | |
d25797b2 | 826 | } |
332b207d | 827 | kvm->arch.indirect_shadow_pages--; |
05da4558 MT |
828 | } |
829 | ||
d25797b2 JR |
830 | static int has_wrprotected_page(struct kvm *kvm, |
831 | gfn_t gfn, | |
832 | int level) | |
05da4558 | 833 | { |
2843099f | 834 | struct kvm_memory_slot *slot; |
d4dbf470 | 835 | struct kvm_lpage_info *linfo; |
05da4558 | 836 | |
a1f4d395 | 837 | slot = gfn_to_memslot(kvm, gfn); |
05da4558 | 838 | if (slot) { |
d4dbf470 TY |
839 | linfo = lpage_info_slot(gfn, slot, level); |
840 | return linfo->write_count; | |
05da4558 MT |
841 | } |
842 | ||
843 | return 1; | |
844 | } | |
845 | ||
d25797b2 | 846 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 847 | { |
8f0b1ab6 | 848 | unsigned long page_size; |
d25797b2 | 849 | int i, ret = 0; |
05da4558 | 850 | |
8f0b1ab6 | 851 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 852 | |
d25797b2 JR |
853 | for (i = PT_PAGE_TABLE_LEVEL; |
854 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
855 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
856 | ret = i; | |
857 | else | |
858 | break; | |
859 | } | |
860 | ||
4c2155ce | 861 | return ret; |
05da4558 MT |
862 | } |
863 | ||
5d163b1c XG |
864 | static struct kvm_memory_slot * |
865 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
866 | bool no_dirty_log) | |
05da4558 MT |
867 | { |
868 | struct kvm_memory_slot *slot; | |
5d163b1c XG |
869 | |
870 | slot = gfn_to_memslot(vcpu->kvm, gfn); | |
871 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID || | |
872 | (no_dirty_log && slot->dirty_bitmap)) | |
873 | slot = NULL; | |
874 | ||
875 | return slot; | |
876 | } | |
877 | ||
878 | static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
879 | { | |
a0a8eaba | 880 | return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true); |
936a5fe6 AA |
881 | } |
882 | ||
883 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
884 | { | |
885 | int host_level, level, max_level; | |
05da4558 | 886 | |
d25797b2 JR |
887 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
888 | ||
889 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
890 | return host_level; | |
891 | ||
55dd98c3 | 892 | max_level = min(kvm_x86_ops->get_lpage_level(), host_level); |
878403b7 SY |
893 | |
894 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
895 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
896 | break; | |
d25797b2 JR |
897 | |
898 | return level - 1; | |
05da4558 MT |
899 | } |
900 | ||
290fc38d | 901 | /* |
53c07b18 | 902 | * Pte mapping structures: |
cd4a4e53 | 903 | * |
53c07b18 | 904 | * If pte_list bit zero is zero, then pte_list point to the spte. |
cd4a4e53 | 905 | * |
53c07b18 XG |
906 | * If pte_list bit zero is one, (then pte_list & ~1) points to a struct |
907 | * pte_list_desc containing more mappings. | |
53a27b39 | 908 | * |
53c07b18 | 909 | * Returns the number of pte entries before the spte was added or zero if |
53a27b39 MT |
910 | * the spte was not added. |
911 | * | |
cd4a4e53 | 912 | */ |
53c07b18 XG |
913 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
914 | unsigned long *pte_list) | |
cd4a4e53 | 915 | { |
53c07b18 | 916 | struct pte_list_desc *desc; |
53a27b39 | 917 | int i, count = 0; |
cd4a4e53 | 918 | |
53c07b18 XG |
919 | if (!*pte_list) { |
920 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); | |
921 | *pte_list = (unsigned long)spte; | |
922 | } else if (!(*pte_list & 1)) { | |
923 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); | |
924 | desc = mmu_alloc_pte_list_desc(vcpu); | |
925 | desc->sptes[0] = (u64 *)*pte_list; | |
d555c333 | 926 | desc->sptes[1] = spte; |
53c07b18 | 927 | *pte_list = (unsigned long)desc | 1; |
cb16a7b3 | 928 | ++count; |
cd4a4e53 | 929 | } else { |
53c07b18 XG |
930 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
931 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
932 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { | |
cd4a4e53 | 933 | desc = desc->more; |
53c07b18 | 934 | count += PTE_LIST_EXT; |
53a27b39 | 935 | } |
53c07b18 XG |
936 | if (desc->sptes[PTE_LIST_EXT-1]) { |
937 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
938 | desc = desc->more; |
939 | } | |
d555c333 | 940 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 941 | ++count; |
d555c333 | 942 | desc->sptes[i] = spte; |
cd4a4e53 | 943 | } |
53a27b39 | 944 | return count; |
cd4a4e53 AK |
945 | } |
946 | ||
53c07b18 XG |
947 | static void |
948 | pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc, | |
949 | int i, struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
950 | { |
951 | int j; | |
952 | ||
53c07b18 | 953 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 954 | ; |
d555c333 AK |
955 | desc->sptes[i] = desc->sptes[j]; |
956 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
957 | if (j != 0) |
958 | return; | |
959 | if (!prev_desc && !desc->more) | |
53c07b18 | 960 | *pte_list = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
961 | else |
962 | if (prev_desc) | |
963 | prev_desc->more = desc->more; | |
964 | else | |
53c07b18 XG |
965 | *pte_list = (unsigned long)desc->more | 1; |
966 | mmu_free_pte_list_desc(desc); | |
cd4a4e53 AK |
967 | } |
968 | ||
53c07b18 | 969 | static void pte_list_remove(u64 *spte, unsigned long *pte_list) |
cd4a4e53 | 970 | { |
53c07b18 XG |
971 | struct pte_list_desc *desc; |
972 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
973 | int i; |
974 | ||
53c07b18 XG |
975 | if (!*pte_list) { |
976 | printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte); | |
cd4a4e53 | 977 | BUG(); |
53c07b18 XG |
978 | } else if (!(*pte_list & 1)) { |
979 | rmap_printk("pte_list_remove: %p 1->0\n", spte); | |
980 | if ((u64 *)*pte_list != spte) { | |
981 | printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte); | |
cd4a4e53 AK |
982 | BUG(); |
983 | } | |
53c07b18 | 984 | *pte_list = 0; |
cd4a4e53 | 985 | } else { |
53c07b18 XG |
986 | rmap_printk("pte_list_remove: %p many->many\n", spte); |
987 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
cd4a4e53 AK |
988 | prev_desc = NULL; |
989 | while (desc) { | |
53c07b18 | 990 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) |
d555c333 | 991 | if (desc->sptes[i] == spte) { |
53c07b18 | 992 | pte_list_desc_remove_entry(pte_list, |
714b93da | 993 | desc, i, |
cd4a4e53 AK |
994 | prev_desc); |
995 | return; | |
996 | } | |
997 | prev_desc = desc; | |
998 | desc = desc->more; | |
999 | } | |
53c07b18 | 1000 | pr_err("pte_list_remove: %p many->many\n", spte); |
cd4a4e53 AK |
1001 | BUG(); |
1002 | } | |
1003 | } | |
1004 | ||
67052b35 XG |
1005 | typedef void (*pte_list_walk_fn) (u64 *spte); |
1006 | static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn) | |
1007 | { | |
1008 | struct pte_list_desc *desc; | |
1009 | int i; | |
1010 | ||
1011 | if (!*pte_list) | |
1012 | return; | |
1013 | ||
1014 | if (!(*pte_list & 1)) | |
1015 | return fn((u64 *)*pte_list); | |
1016 | ||
1017 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
1018 | while (desc) { | |
1019 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) | |
1020 | fn(desc->sptes[i]); | |
1021 | desc = desc->more; | |
1022 | } | |
1023 | } | |
1024 | ||
9373e2c0 | 1025 | static unsigned long *__gfn_to_rmap(gfn_t gfn, int level, |
9b9b1492 | 1026 | struct kvm_memory_slot *slot) |
53c07b18 | 1027 | { |
77d11309 | 1028 | unsigned long idx; |
53c07b18 | 1029 | |
77d11309 | 1030 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
d89cc617 | 1031 | return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx]; |
53c07b18 XG |
1032 | } |
1033 | ||
9b9b1492 TY |
1034 | /* |
1035 | * Take gfn and return the reverse mapping to it. | |
1036 | */ | |
1037 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) | |
1038 | { | |
1039 | struct kvm_memory_slot *slot; | |
1040 | ||
1041 | slot = gfn_to_memslot(kvm, gfn); | |
9373e2c0 | 1042 | return __gfn_to_rmap(gfn, level, slot); |
9b9b1492 TY |
1043 | } |
1044 | ||
f759e2b4 XG |
1045 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
1046 | { | |
1047 | struct kvm_mmu_memory_cache *cache; | |
1048 | ||
1049 | cache = &vcpu->arch.mmu_pte_list_desc_cache; | |
1050 | return mmu_memory_cache_free_objects(cache); | |
1051 | } | |
1052 | ||
53c07b18 XG |
1053 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
1054 | { | |
1055 | struct kvm_mmu_page *sp; | |
1056 | unsigned long *rmapp; | |
1057 | ||
53c07b18 XG |
1058 | sp = page_header(__pa(spte)); |
1059 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
1060 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); | |
1061 | return pte_list_add(vcpu, spte, rmapp); | |
1062 | } | |
1063 | ||
53c07b18 XG |
1064 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
1065 | { | |
1066 | struct kvm_mmu_page *sp; | |
1067 | gfn_t gfn; | |
1068 | unsigned long *rmapp; | |
1069 | ||
1070 | sp = page_header(__pa(spte)); | |
1071 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
1072 | rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); | |
1073 | pte_list_remove(spte, rmapp); | |
1074 | } | |
1075 | ||
1e3f42f0 TY |
1076 | /* |
1077 | * Used by the following functions to iterate through the sptes linked by a | |
1078 | * rmap. All fields are private and not assumed to be used outside. | |
1079 | */ | |
1080 | struct rmap_iterator { | |
1081 | /* private fields */ | |
1082 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1083 | int pos; /* index of the sptep */ | |
1084 | }; | |
1085 | ||
1086 | /* | |
1087 | * Iteration must be started by this function. This should also be used after | |
1088 | * removing/dropping sptes from the rmap link because in such cases the | |
1089 | * information in the itererator may not be valid. | |
1090 | * | |
1091 | * Returns sptep if found, NULL otherwise. | |
1092 | */ | |
1093 | static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter) | |
1094 | { | |
1095 | if (!rmap) | |
1096 | return NULL; | |
1097 | ||
1098 | if (!(rmap & 1)) { | |
1099 | iter->desc = NULL; | |
1100 | return (u64 *)rmap; | |
1101 | } | |
1102 | ||
1103 | iter->desc = (struct pte_list_desc *)(rmap & ~1ul); | |
1104 | iter->pos = 0; | |
1105 | return iter->desc->sptes[iter->pos]; | |
1106 | } | |
1107 | ||
1108 | /* | |
1109 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1110 | * | |
1111 | * Returns sptep if found, NULL otherwise. | |
1112 | */ | |
1113 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1114 | { | |
1115 | if (iter->desc) { | |
1116 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1117 | u64 *sptep; | |
1118 | ||
1119 | ++iter->pos; | |
1120 | sptep = iter->desc->sptes[iter->pos]; | |
1121 | if (sptep) | |
1122 | return sptep; | |
1123 | } | |
1124 | ||
1125 | iter->desc = iter->desc->more; | |
1126 | ||
1127 | if (iter->desc) { | |
1128 | iter->pos = 0; | |
1129 | /* desc->sptes[0] cannot be NULL */ | |
1130 | return iter->desc->sptes[iter->pos]; | |
1131 | } | |
1132 | } | |
1133 | ||
1134 | return NULL; | |
1135 | } | |
1136 | ||
c3707958 | 1137 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1138 | { |
1df9f2dc | 1139 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1140 | rmap_remove(kvm, sptep); |
be38d276 AK |
1141 | } |
1142 | ||
8e22f955 XG |
1143 | |
1144 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1145 | { | |
1146 | if (is_large_pte(*sptep)) { | |
1147 | WARN_ON(page_header(__pa(sptep))->role.level == | |
1148 | PT_PAGE_TABLE_LEVEL); | |
1149 | drop_spte(kvm, sptep); | |
1150 | --kvm->stat.lpages; | |
1151 | return true; | |
1152 | } | |
1153 | ||
1154 | return false; | |
1155 | } | |
1156 | ||
1157 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1158 | { | |
1159 | if (__drop_large_spte(vcpu->kvm, sptep)) | |
1160 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1161 | } | |
1162 | ||
1163 | /* | |
49fde340 | 1164 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
6b73a960 MT |
1165 | * spte writ-protection is caused by protecting shadow page table. |
1166 | * @flush indicates whether tlb need be flushed. | |
49fde340 XG |
1167 | * |
1168 | * Note: write protection is difference between drity logging and spte | |
1169 | * protection: | |
1170 | * - for dirty logging, the spte can be set to writable at anytime if | |
1171 | * its dirty bitmap is properly set. | |
1172 | * - for spte protection, the spte can be writable only after unsync-ing | |
1173 | * shadow page. | |
8e22f955 | 1174 | * |
6b73a960 | 1175 | * Return true if the spte is dropped. |
8e22f955 | 1176 | */ |
6b73a960 MT |
1177 | static bool |
1178 | spte_write_protect(struct kvm *kvm, u64 *sptep, bool *flush, bool pt_protect) | |
d13bc5b5 XG |
1179 | { |
1180 | u64 spte = *sptep; | |
1181 | ||
49fde340 XG |
1182 | if (!is_writable_pte(spte) && |
1183 | !(pt_protect && spte_is_locklessly_modifiable(spte))) | |
d13bc5b5 XG |
1184 | return false; |
1185 | ||
1186 | rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); | |
1187 | ||
6b73a960 MT |
1188 | if (__drop_large_spte(kvm, sptep)) { |
1189 | *flush |= true; | |
1190 | return true; | |
1191 | } | |
1192 | ||
49fde340 XG |
1193 | if (pt_protect) |
1194 | spte &= ~SPTE_MMU_WRITEABLE; | |
d13bc5b5 | 1195 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1196 | |
6b73a960 MT |
1197 | *flush |= mmu_spte_update(sptep, spte); |
1198 | return false; | |
d13bc5b5 XG |
1199 | } |
1200 | ||
49fde340 | 1201 | static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp, |
245c3912 | 1202 | bool pt_protect) |
98348e95 | 1203 | { |
1e3f42f0 TY |
1204 | u64 *sptep; |
1205 | struct rmap_iterator iter; | |
d13bc5b5 | 1206 | bool flush = false; |
374cbac0 | 1207 | |
1e3f42f0 TY |
1208 | for (sptep = rmap_get_first(*rmapp, &iter); sptep;) { |
1209 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
6b73a960 MT |
1210 | if (spte_write_protect(kvm, sptep, &flush, pt_protect)) { |
1211 | sptep = rmap_get_first(*rmapp, &iter); | |
1212 | continue; | |
1213 | } | |
a0ed4607 | 1214 | |
d13bc5b5 | 1215 | sptep = rmap_get_next(&iter); |
374cbac0 | 1216 | } |
855149aa | 1217 | |
d13bc5b5 | 1218 | return flush; |
a0ed4607 TY |
1219 | } |
1220 | ||
5dc99b23 TY |
1221 | /** |
1222 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages | |
1223 | * @kvm: kvm instance | |
1224 | * @slot: slot to protect | |
1225 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1226 | * @mask: indicates which pages we should protect | |
1227 | * | |
1228 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1229 | * logging we do not have any such mappings. | |
1230 | */ | |
1231 | void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, | |
1232 | struct kvm_memory_slot *slot, | |
1233 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 TY |
1234 | { |
1235 | unsigned long *rmapp; | |
a0ed4607 | 1236 | |
5dc99b23 | 1237 | while (mask) { |
65fbe37c TY |
1238 | rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1239 | PT_PAGE_TABLE_LEVEL, slot); | |
245c3912 | 1240 | __rmap_write_protect(kvm, rmapp, false); |
05da4558 | 1241 | |
5dc99b23 TY |
1242 | /* clear the first set bit */ |
1243 | mask &= mask - 1; | |
1244 | } | |
374cbac0 AK |
1245 | } |
1246 | ||
2f84569f | 1247 | static bool rmap_write_protect(struct kvm *kvm, u64 gfn) |
95d4c16c TY |
1248 | { |
1249 | struct kvm_memory_slot *slot; | |
5dc99b23 TY |
1250 | unsigned long *rmapp; |
1251 | int i; | |
2f84569f | 1252 | bool write_protected = false; |
95d4c16c TY |
1253 | |
1254 | slot = gfn_to_memslot(kvm, gfn); | |
5dc99b23 TY |
1255 | |
1256 | for (i = PT_PAGE_TABLE_LEVEL; | |
1257 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
1258 | rmapp = __gfn_to_rmap(gfn, i, slot); | |
245c3912 | 1259 | write_protected |= __rmap_write_protect(kvm, rmapp, true); |
5dc99b23 TY |
1260 | } |
1261 | ||
1262 | return write_protected; | |
95d4c16c TY |
1263 | } |
1264 | ||
8a8365c5 | 1265 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1266 | struct kvm_memory_slot *slot, unsigned long data) |
e930bffe | 1267 | { |
1e3f42f0 TY |
1268 | u64 *sptep; |
1269 | struct rmap_iterator iter; | |
e930bffe AA |
1270 | int need_tlb_flush = 0; |
1271 | ||
1e3f42f0 TY |
1272 | while ((sptep = rmap_get_first(*rmapp, &iter))) { |
1273 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
1274 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep); | |
1275 | ||
1276 | drop_spte(kvm, sptep); | |
e930bffe AA |
1277 | need_tlb_flush = 1; |
1278 | } | |
1e3f42f0 | 1279 | |
e930bffe AA |
1280 | return need_tlb_flush; |
1281 | } | |
1282 | ||
8a8365c5 | 1283 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1284 | struct kvm_memory_slot *slot, unsigned long data) |
3da0dd43 | 1285 | { |
1e3f42f0 TY |
1286 | u64 *sptep; |
1287 | struct rmap_iterator iter; | |
3da0dd43 | 1288 | int need_flush = 0; |
1e3f42f0 | 1289 | u64 new_spte; |
3da0dd43 IE |
1290 | pte_t *ptep = (pte_t *)data; |
1291 | pfn_t new_pfn; | |
1292 | ||
1293 | WARN_ON(pte_huge(*ptep)); | |
1294 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 TY |
1295 | |
1296 | for (sptep = rmap_get_first(*rmapp, &iter); sptep;) { | |
1297 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1298 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep); | |
1299 | ||
3da0dd43 | 1300 | need_flush = 1; |
1e3f42f0 | 1301 | |
3da0dd43 | 1302 | if (pte_write(*ptep)) { |
1e3f42f0 TY |
1303 | drop_spte(kvm, sptep); |
1304 | sptep = rmap_get_first(*rmapp, &iter); | |
3da0dd43 | 1305 | } else { |
1e3f42f0 | 1306 | new_spte = *sptep & ~PT64_BASE_ADDR_MASK; |
3da0dd43 IE |
1307 | new_spte |= (u64)new_pfn << PAGE_SHIFT; |
1308 | ||
1309 | new_spte &= ~PT_WRITABLE_MASK; | |
1310 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 1311 | new_spte &= ~shadow_accessed_mask; |
1e3f42f0 TY |
1312 | |
1313 | mmu_spte_clear_track_bits(sptep); | |
1314 | mmu_spte_set(sptep, new_spte); | |
1315 | sptep = rmap_get_next(&iter); | |
3da0dd43 IE |
1316 | } |
1317 | } | |
1e3f42f0 | 1318 | |
3da0dd43 IE |
1319 | if (need_flush) |
1320 | kvm_flush_remote_tlbs(kvm); | |
1321 | ||
1322 | return 0; | |
1323 | } | |
1324 | ||
84504ef3 TY |
1325 | static int kvm_handle_hva_range(struct kvm *kvm, |
1326 | unsigned long start, | |
1327 | unsigned long end, | |
1328 | unsigned long data, | |
1329 | int (*handler)(struct kvm *kvm, | |
1330 | unsigned long *rmapp, | |
048212d0 | 1331 | struct kvm_memory_slot *slot, |
84504ef3 | 1332 | unsigned long data)) |
e930bffe | 1333 | { |
be6ba0f0 | 1334 | int j; |
f395302e | 1335 | int ret = 0; |
bc6678a3 | 1336 | struct kvm_memslots *slots; |
be6ba0f0 | 1337 | struct kvm_memory_slot *memslot; |
bc6678a3 | 1338 | |
90d83dc3 | 1339 | slots = kvm_memslots(kvm); |
e930bffe | 1340 | |
be6ba0f0 | 1341 | kvm_for_each_memslot(memslot, slots) { |
84504ef3 | 1342 | unsigned long hva_start, hva_end; |
bcd3ef58 | 1343 | gfn_t gfn_start, gfn_end; |
e930bffe | 1344 | |
84504ef3 TY |
1345 | hva_start = max(start, memslot->userspace_addr); |
1346 | hva_end = min(end, memslot->userspace_addr + | |
1347 | (memslot->npages << PAGE_SHIFT)); | |
1348 | if (hva_start >= hva_end) | |
1349 | continue; | |
1350 | /* | |
1351 | * {gfn(page) | page intersects with [hva_start, hva_end)} = | |
bcd3ef58 | 1352 | * {gfn_start, gfn_start+1, ..., gfn_end-1}. |
84504ef3 | 1353 | */ |
bcd3ef58 | 1354 | gfn_start = hva_to_gfn_memslot(hva_start, memslot); |
84504ef3 | 1355 | gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); |
852e3c19 | 1356 | |
bcd3ef58 TY |
1357 | for (j = PT_PAGE_TABLE_LEVEL; |
1358 | j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) { | |
1359 | unsigned long idx, idx_end; | |
1360 | unsigned long *rmapp; | |
d4dbf470 | 1361 | |
bcd3ef58 TY |
1362 | /* |
1363 | * {idx(page_j) | page_j intersects with | |
1364 | * [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}. | |
1365 | */ | |
1366 | idx = gfn_to_index(gfn_start, memslot->base_gfn, j); | |
1367 | idx_end = gfn_to_index(gfn_end - 1, memslot->base_gfn, j); | |
852e3c19 | 1368 | |
bcd3ef58 | 1369 | rmapp = __gfn_to_rmap(gfn_start, j, memslot); |
d4dbf470 | 1370 | |
bcd3ef58 TY |
1371 | for (; idx <= idx_end; ++idx) |
1372 | ret |= handler(kvm, rmapp++, memslot, data); | |
e930bffe AA |
1373 | } |
1374 | } | |
1375 | ||
f395302e | 1376 | return ret; |
e930bffe AA |
1377 | } |
1378 | ||
84504ef3 TY |
1379 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1380 | unsigned long data, | |
1381 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, | |
048212d0 | 1382 | struct kvm_memory_slot *slot, |
84504ef3 TY |
1383 | unsigned long data)) |
1384 | { | |
1385 | return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler); | |
e930bffe AA |
1386 | } |
1387 | ||
1388 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
1389 | { | |
3da0dd43 IE |
1390 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
1391 | } | |
1392 | ||
b3ae2096 TY |
1393 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end) |
1394 | { | |
1395 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp); | |
1396 | } | |
1397 | ||
3da0dd43 IE |
1398 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
1399 | { | |
8a8365c5 | 1400 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1401 | } |
1402 | ||
8a8365c5 | 1403 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1404 | struct kvm_memory_slot *slot, unsigned long data) |
e930bffe | 1405 | { |
1e3f42f0 | 1406 | u64 *sptep; |
79f702a6 | 1407 | struct rmap_iterator uninitialized_var(iter); |
e930bffe AA |
1408 | int young = 0; |
1409 | ||
6316e1c8 | 1410 | /* |
3f6d8c8a XH |
1411 | * In case of absence of EPT Access and Dirty Bits supports, |
1412 | * emulate the accessed bit for EPT, by checking if this page has | |
6316e1c8 RR |
1413 | * an EPT mapping, and clearing it if it does. On the next access, |
1414 | * a new EPT mapping will be established. | |
1415 | * This has some overhead, but not as much as the cost of swapping | |
1416 | * out actively used pages or breaking up actively used hugepages. | |
1417 | */ | |
f395302e TY |
1418 | if (!shadow_accessed_mask) { |
1419 | young = kvm_unmap_rmapp(kvm, rmapp, slot, data); | |
1420 | goto out; | |
1421 | } | |
534e38b4 | 1422 | |
1e3f42f0 TY |
1423 | for (sptep = rmap_get_first(*rmapp, &iter); sptep; |
1424 | sptep = rmap_get_next(&iter)) { | |
3f6d8c8a | 1425 | BUG_ON(!is_shadow_present_pte(*sptep)); |
1e3f42f0 | 1426 | |
3f6d8c8a | 1427 | if (*sptep & shadow_accessed_mask) { |
e930bffe | 1428 | young = 1; |
3f6d8c8a XH |
1429 | clear_bit((ffs(shadow_accessed_mask) - 1), |
1430 | (unsigned long *)sptep); | |
e930bffe | 1431 | } |
e930bffe | 1432 | } |
f395302e TY |
1433 | out: |
1434 | /* @data has hva passed to kvm_age_hva(). */ | |
1435 | trace_kvm_age_page(data, slot, young); | |
e930bffe AA |
1436 | return young; |
1437 | } | |
1438 | ||
8ee53820 | 1439 | static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1440 | struct kvm_memory_slot *slot, unsigned long data) |
8ee53820 | 1441 | { |
1e3f42f0 TY |
1442 | u64 *sptep; |
1443 | struct rmap_iterator iter; | |
8ee53820 AA |
1444 | int young = 0; |
1445 | ||
1446 | /* | |
1447 | * If there's no access bit in the secondary pte set by the | |
1448 | * hardware it's up to gup-fast/gup to set the access bit in | |
1449 | * the primary pte or in the page structure. | |
1450 | */ | |
1451 | if (!shadow_accessed_mask) | |
1452 | goto out; | |
1453 | ||
1e3f42f0 TY |
1454 | for (sptep = rmap_get_first(*rmapp, &iter); sptep; |
1455 | sptep = rmap_get_next(&iter)) { | |
3f6d8c8a | 1456 | BUG_ON(!is_shadow_present_pte(*sptep)); |
1e3f42f0 | 1457 | |
3f6d8c8a | 1458 | if (*sptep & shadow_accessed_mask) { |
8ee53820 AA |
1459 | young = 1; |
1460 | break; | |
1461 | } | |
8ee53820 AA |
1462 | } |
1463 | out: | |
1464 | return young; | |
1465 | } | |
1466 | ||
53a27b39 MT |
1467 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1468 | ||
852e3c19 | 1469 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
1470 | { |
1471 | unsigned long *rmapp; | |
852e3c19 JR |
1472 | struct kvm_mmu_page *sp; |
1473 | ||
1474 | sp = page_header(__pa(spte)); | |
53a27b39 | 1475 | |
852e3c19 | 1476 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 1477 | |
048212d0 | 1478 | kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, 0); |
53a27b39 MT |
1479 | kvm_flush_remote_tlbs(vcpu->kvm); |
1480 | } | |
1481 | ||
e930bffe AA |
1482 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
1483 | { | |
f395302e | 1484 | return kvm_handle_hva(kvm, hva, hva, kvm_age_rmapp); |
e930bffe AA |
1485 | } |
1486 | ||
8ee53820 AA |
1487 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1488 | { | |
1489 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1490 | } | |
1491 | ||
d6c69ee9 | 1492 | #ifdef MMU_DEBUG |
47ad8e68 | 1493 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1494 | { |
139bdb2d AK |
1495 | u64 *pos; |
1496 | u64 *end; | |
1497 | ||
47ad8e68 | 1498 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1499 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1500 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1501 | pos, *pos); |
6aa8b732 | 1502 | return 0; |
139bdb2d | 1503 | } |
6aa8b732 AK |
1504 | return 1; |
1505 | } | |
d6c69ee9 | 1506 | #endif |
6aa8b732 | 1507 | |
45221ab6 DH |
1508 | /* |
1509 | * This value is the sum of all of the kvm instances's | |
1510 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1511 | * aggregate version in order to make the slab shrinker | |
1512 | * faster | |
1513 | */ | |
1514 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
1515 | { | |
1516 | kvm->arch.n_used_mmu_pages += nr; | |
1517 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1518 | } | |
1519 | ||
834be0d8 | 1520 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 1521 | { |
4db35314 | 1522 | ASSERT(is_empty_shadow_page(sp->spt)); |
7775834a | 1523 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
1524 | list_del(&sp->link); |
1525 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
1526 | if (!sp->role.direct) |
1527 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 1528 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1529 | } |
1530 | ||
cea0f0e7 AK |
1531 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1532 | { | |
1ae0a13d | 1533 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
1534 | } |
1535 | ||
714b93da | 1536 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1537 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1538 | { |
cea0f0e7 AK |
1539 | if (!parent_pte) |
1540 | return; | |
cea0f0e7 | 1541 | |
67052b35 | 1542 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1543 | } |
1544 | ||
4db35314 | 1545 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1546 | u64 *parent_pte) |
1547 | { | |
67052b35 | 1548 | pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1549 | } |
1550 | ||
bcdd9a93 XG |
1551 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1552 | u64 *parent_pte) | |
1553 | { | |
1554 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1555 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1556 | } |
1557 | ||
67052b35 XG |
1558 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
1559 | u64 *parent_pte, int direct) | |
ad8cfbe3 | 1560 | { |
67052b35 | 1561 | struct kvm_mmu_page *sp; |
7ddca7e4 | 1562 | |
80feb89a TY |
1563 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
1564 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); | |
67052b35 | 1565 | if (!direct) |
80feb89a | 1566 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); |
67052b35 | 1567 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
5304b8d3 XG |
1568 | |
1569 | /* | |
1570 | * The active_mmu_pages list is the FIFO list, do not move the | |
1571 | * page until it is zapped. kvm_zap_obsolete_pages depends on | |
1572 | * this feature. See the comments in kvm_zap_obsolete_pages(). | |
1573 | */ | |
67052b35 | 1574 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
67052b35 XG |
1575 | sp->parent_ptes = 0; |
1576 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); | |
1577 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); | |
1578 | return sp; | |
ad8cfbe3 MT |
1579 | } |
1580 | ||
67052b35 | 1581 | static void mark_unsync(u64 *spte); |
1047df1f | 1582 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1583 | { |
67052b35 | 1584 | pte_list_walk(&sp->parent_ptes, mark_unsync); |
0074ff63 MT |
1585 | } |
1586 | ||
67052b35 | 1587 | static void mark_unsync(u64 *spte) |
0074ff63 | 1588 | { |
67052b35 | 1589 | struct kvm_mmu_page *sp; |
1047df1f | 1590 | unsigned int index; |
0074ff63 | 1591 | |
67052b35 | 1592 | sp = page_header(__pa(spte)); |
1047df1f XG |
1593 | index = spte - sp->spt; |
1594 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1595 | return; |
1047df1f | 1596 | if (sp->unsync_children++) |
0074ff63 | 1597 | return; |
1047df1f | 1598 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1599 | } |
1600 | ||
e8bc217a | 1601 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1602 | struct kvm_mmu_page *sp) |
e8bc217a MT |
1603 | { |
1604 | return 1; | |
1605 | } | |
1606 | ||
a7052897 MT |
1607 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1608 | { | |
1609 | } | |
1610 | ||
0f53b5b1 XG |
1611 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1612 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 1613 | const void *pte) |
0f53b5b1 XG |
1614 | { |
1615 | WARN_ON(1); | |
1616 | } | |
1617 | ||
60c8aec6 MT |
1618 | #define KVM_PAGE_ARRAY_NR 16 |
1619 | ||
1620 | struct kvm_mmu_pages { | |
1621 | struct mmu_page_and_offset { | |
1622 | struct kvm_mmu_page *sp; | |
1623 | unsigned int idx; | |
1624 | } page[KVM_PAGE_ARRAY_NR]; | |
1625 | unsigned int nr; | |
1626 | }; | |
1627 | ||
cded19f3 HE |
1628 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1629 | int idx) | |
4731d4c7 | 1630 | { |
60c8aec6 | 1631 | int i; |
4731d4c7 | 1632 | |
60c8aec6 MT |
1633 | if (sp->unsync) |
1634 | for (i=0; i < pvec->nr; i++) | |
1635 | if (pvec->page[i].sp == sp) | |
1636 | return 0; | |
1637 | ||
1638 | pvec->page[pvec->nr].sp = sp; | |
1639 | pvec->page[pvec->nr].idx = idx; | |
1640 | pvec->nr++; | |
1641 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1642 | } | |
1643 | ||
1644 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1645 | struct kvm_mmu_pages *pvec) | |
1646 | { | |
1647 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1648 | |
37178b8b | 1649 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 1650 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1651 | u64 ent = sp->spt[i]; |
1652 | ||
7a8f1a74 XG |
1653 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) |
1654 | goto clear_child_bitmap; | |
1655 | ||
1656 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1657 | ||
1658 | if (child->unsync_children) { | |
1659 | if (mmu_pages_add(pvec, child, i)) | |
1660 | return -ENOSPC; | |
1661 | ||
1662 | ret = __mmu_unsync_walk(child, pvec); | |
1663 | if (!ret) | |
1664 | goto clear_child_bitmap; | |
1665 | else if (ret > 0) | |
1666 | nr_unsync_leaf += ret; | |
1667 | else | |
1668 | return ret; | |
1669 | } else if (child->unsync) { | |
1670 | nr_unsync_leaf++; | |
1671 | if (mmu_pages_add(pvec, child, i)) | |
1672 | return -ENOSPC; | |
1673 | } else | |
1674 | goto clear_child_bitmap; | |
1675 | ||
1676 | continue; | |
1677 | ||
1678 | clear_child_bitmap: | |
1679 | __clear_bit(i, sp->unsync_child_bitmap); | |
1680 | sp->unsync_children--; | |
1681 | WARN_ON((int)sp->unsync_children < 0); | |
4731d4c7 MT |
1682 | } |
1683 | ||
4731d4c7 | 1684 | |
60c8aec6 MT |
1685 | return nr_unsync_leaf; |
1686 | } | |
1687 | ||
1688 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1689 | struct kvm_mmu_pages *pvec) | |
1690 | { | |
1691 | if (!sp->unsync_children) | |
1692 | return 0; | |
1693 | ||
1694 | mmu_pages_add(pvec, sp, 0); | |
1695 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1696 | } |
1697 | ||
4731d4c7 MT |
1698 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1699 | { | |
1700 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1701 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1702 | sp->unsync = 0; |
1703 | --kvm->stat.mmu_unsync; | |
1704 | } | |
1705 | ||
7775834a XG |
1706 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1707 | struct list_head *invalid_list); | |
1708 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1709 | struct list_head *invalid_list); | |
4731d4c7 | 1710 | |
f34d251d XG |
1711 | /* |
1712 | * NOTE: we should pay more attention on the zapped-obsolete page | |
1713 | * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk | |
1714 | * since it has been deleted from active_mmu_pages but still can be found | |
1715 | * at hast list. | |
1716 | * | |
1717 | * for_each_gfn_indirect_valid_sp has skipped that kind of page and | |
1718 | * kvm_mmu_get_page(), the only user of for_each_gfn_sp(), has skipped | |
1719 | * all the obsolete pages. | |
1720 | */ | |
1044b030 TY |
1721 | #define for_each_gfn_sp(_kvm, _sp, _gfn) \ |
1722 | hlist_for_each_entry(_sp, \ | |
1723 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \ | |
1724 | if ((_sp)->gfn != (_gfn)) {} else | |
1725 | ||
1726 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
1727 | for_each_gfn_sp(_kvm, _sp, _gfn) \ | |
1728 | if ((_sp)->role.direct || (_sp)->role.invalid) {} else | |
7ae680eb | 1729 | |
f918b443 | 1730 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1731 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1732 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1733 | { |
5b7e0102 | 1734 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1735 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1736 | return 1; |
1737 | } | |
1738 | ||
f918b443 | 1739 | if (clear_unsync) |
1d9dc7e0 | 1740 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1741 | |
a4a8e6f7 | 1742 | if (vcpu->arch.mmu.sync_page(vcpu, sp)) { |
d98ba053 | 1743 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1744 | return 1; |
1745 | } | |
1746 | ||
1747 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1748 | return 0; |
1749 | } | |
1750 | ||
1d9dc7e0 XG |
1751 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1752 | struct kvm_mmu_page *sp) | |
1753 | { | |
d98ba053 | 1754 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1755 | int ret; |
1756 | ||
d98ba053 | 1757 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1758 | if (ret) |
d98ba053 XG |
1759 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1760 | ||
1d9dc7e0 XG |
1761 | return ret; |
1762 | } | |
1763 | ||
e37fa785 XG |
1764 | #ifdef CONFIG_KVM_MMU_AUDIT |
1765 | #include "mmu_audit.c" | |
1766 | #else | |
1767 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
1768 | static void mmu_audit_disable(void) { } | |
1769 | #endif | |
1770 | ||
d98ba053 XG |
1771 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1772 | struct list_head *invalid_list) | |
1d9dc7e0 | 1773 | { |
d98ba053 | 1774 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1775 | } |
1776 | ||
9f1a122f XG |
1777 | /* @gfn should be write-protected at the call site */ |
1778 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1779 | { | |
9f1a122f | 1780 | struct kvm_mmu_page *s; |
d98ba053 | 1781 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1782 | bool flush = false; |
1783 | ||
b67bfe0d | 1784 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 1785 | if (!s->unsync) |
9f1a122f XG |
1786 | continue; |
1787 | ||
1788 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
a4a8e6f7 | 1789 | kvm_unlink_unsync_page(vcpu->kvm, s); |
9f1a122f | 1790 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || |
a4a8e6f7 | 1791 | (vcpu->arch.mmu.sync_page(vcpu, s))) { |
d98ba053 | 1792 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1793 | continue; |
1794 | } | |
9f1a122f XG |
1795 | flush = true; |
1796 | } | |
1797 | ||
d98ba053 | 1798 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f XG |
1799 | if (flush) |
1800 | kvm_mmu_flush_tlb(vcpu); | |
1801 | } | |
1802 | ||
60c8aec6 MT |
1803 | struct mmu_page_path { |
1804 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1805 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1806 | }; |
1807 | ||
60c8aec6 MT |
1808 | #define for_each_sp(pvec, sp, parents, i) \ |
1809 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1810 | sp = pvec.page[i].sp; \ | |
1811 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1812 | i = mmu_pages_next(&pvec, &parents, i)) | |
1813 | ||
cded19f3 HE |
1814 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1815 | struct mmu_page_path *parents, | |
1816 | int i) | |
60c8aec6 MT |
1817 | { |
1818 | int n; | |
1819 | ||
1820 | for (n = i+1; n < pvec->nr; n++) { | |
1821 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1822 | ||
1823 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1824 | parents->idx[0] = pvec->page[n].idx; | |
1825 | return n; | |
1826 | } | |
1827 | ||
1828 | parents->parent[sp->role.level-2] = sp; | |
1829 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1830 | } | |
1831 | ||
1832 | return n; | |
1833 | } | |
1834 | ||
cded19f3 | 1835 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1836 | { |
60c8aec6 MT |
1837 | struct kvm_mmu_page *sp; |
1838 | unsigned int level = 0; | |
1839 | ||
1840 | do { | |
1841 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1842 | |
60c8aec6 MT |
1843 | sp = parents->parent[level]; |
1844 | if (!sp) | |
1845 | return; | |
1846 | ||
1847 | --sp->unsync_children; | |
1848 | WARN_ON((int)sp->unsync_children < 0); | |
1849 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1850 | level++; | |
1851 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1852 | } |
1853 | ||
60c8aec6 MT |
1854 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1855 | struct mmu_page_path *parents, | |
1856 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1857 | { |
60c8aec6 MT |
1858 | parents->parent[parent->role.level-1] = NULL; |
1859 | pvec->nr = 0; | |
1860 | } | |
4731d4c7 | 1861 | |
60c8aec6 MT |
1862 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1863 | struct kvm_mmu_page *parent) | |
1864 | { | |
1865 | int i; | |
1866 | struct kvm_mmu_page *sp; | |
1867 | struct mmu_page_path parents; | |
1868 | struct kvm_mmu_pages pages; | |
d98ba053 | 1869 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
1870 | |
1871 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1872 | while (mmu_unsync_walk(parent, &pages)) { | |
2f84569f | 1873 | bool protected = false; |
b1a36821 MT |
1874 | |
1875 | for_each_sp(pages, sp, parents, i) | |
1876 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1877 | ||
1878 | if (protected) | |
1879 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1880 | ||
60c8aec6 | 1881 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 1882 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1883 | mmu_pages_clear_parents(&parents); |
1884 | } | |
d98ba053 | 1885 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 1886 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1887 | kvm_mmu_pages_init(parent, &parents, &pages); |
1888 | } | |
4731d4c7 MT |
1889 | } |
1890 | ||
c3707958 XG |
1891 | static void init_shadow_page_table(struct kvm_mmu_page *sp) |
1892 | { | |
1893 | int i; | |
1894 | ||
1895 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1896 | sp->spt[i] = 0ull; | |
1897 | } | |
1898 | ||
a30f47cb XG |
1899 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
1900 | { | |
1901 | sp->write_flooding_count = 0; | |
1902 | } | |
1903 | ||
1904 | static void clear_sp_write_flooding_count(u64 *spte) | |
1905 | { | |
1906 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
1907 | ||
1908 | __clear_sp_write_flooding_count(sp); | |
1909 | } | |
1910 | ||
5304b8d3 XG |
1911 | static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) |
1912 | { | |
1913 | return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); | |
1914 | } | |
1915 | ||
cea0f0e7 AK |
1916 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1917 | gfn_t gfn, | |
1918 | gva_t gaddr, | |
1919 | unsigned level, | |
f6e2c02b | 1920 | int direct, |
41074d07 | 1921 | unsigned access, |
f7d9c7b7 | 1922 | u64 *parent_pte) |
cea0f0e7 AK |
1923 | { |
1924 | union kvm_mmu_page_role role; | |
cea0f0e7 | 1925 | unsigned quadrant; |
9f1a122f | 1926 | struct kvm_mmu_page *sp; |
9f1a122f | 1927 | bool need_sync = false; |
cea0f0e7 | 1928 | |
a770f6f2 | 1929 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1930 | role.level = level; |
f6e2c02b | 1931 | role.direct = direct; |
84b0c8c6 | 1932 | if (role.direct) |
5b7e0102 | 1933 | role.cr4_pae = 0; |
41074d07 | 1934 | role.access = access; |
c5a78f2b JR |
1935 | if (!vcpu->arch.mmu.direct_map |
1936 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
1937 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1938 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1939 | role.quadrant = quadrant; | |
1940 | } | |
b67bfe0d | 1941 | for_each_gfn_sp(vcpu->kvm, sp, gfn) { |
7f52af74 XG |
1942 | if (is_obsolete_sp(vcpu->kvm, sp)) |
1943 | continue; | |
1944 | ||
7ae680eb XG |
1945 | if (!need_sync && sp->unsync) |
1946 | need_sync = true; | |
4731d4c7 | 1947 | |
7ae680eb XG |
1948 | if (sp->role.word != role.word) |
1949 | continue; | |
4731d4c7 | 1950 | |
7ae680eb XG |
1951 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
1952 | break; | |
e02aa901 | 1953 | |
7ae680eb XG |
1954 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
1955 | if (sp->unsync_children) { | |
a8eeb04a | 1956 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
7ae680eb XG |
1957 | kvm_mmu_mark_parents_unsync(sp); |
1958 | } else if (sp->unsync) | |
1959 | kvm_mmu_mark_parents_unsync(sp); | |
e02aa901 | 1960 | |
a30f47cb | 1961 | __clear_sp_write_flooding_count(sp); |
7ae680eb XG |
1962 | trace_kvm_mmu_get_page(sp, false); |
1963 | return sp; | |
1964 | } | |
dfc5aa00 | 1965 | ++vcpu->kvm->stat.mmu_cache_miss; |
2032a93d | 1966 | sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct); |
4db35314 AK |
1967 | if (!sp) |
1968 | return sp; | |
4db35314 AK |
1969 | sp->gfn = gfn; |
1970 | sp->role = role; | |
7ae680eb XG |
1971 | hlist_add_head(&sp->hash_link, |
1972 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 1973 | if (!direct) { |
b1a36821 MT |
1974 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1975 | kvm_flush_remote_tlbs(vcpu->kvm); | |
9f1a122f XG |
1976 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
1977 | kvm_sync_pages(vcpu, gfn); | |
1978 | ||
4731d4c7 MT |
1979 | account_shadowed(vcpu->kvm, gfn); |
1980 | } | |
5304b8d3 | 1981 | sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen; |
c3707958 | 1982 | init_shadow_page_table(sp); |
f691fe1d | 1983 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1984 | return sp; |
cea0f0e7 AK |
1985 | } |
1986 | ||
2d11123a AK |
1987 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1988 | struct kvm_vcpu *vcpu, u64 addr) | |
1989 | { | |
1990 | iterator->addr = addr; | |
1991 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1992 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 JR |
1993 | |
1994 | if (iterator->level == PT64_ROOT_LEVEL && | |
1995 | vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL && | |
1996 | !vcpu->arch.mmu.direct_map) | |
1997 | --iterator->level; | |
1998 | ||
2d11123a AK |
1999 | if (iterator->level == PT32E_ROOT_LEVEL) { |
2000 | iterator->shadow_addr | |
2001 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
2002 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
2003 | --iterator->level; | |
2004 | if (!iterator->shadow_addr) | |
2005 | iterator->level = 0; | |
2006 | } | |
2007 | } | |
2008 | ||
2009 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
2010 | { | |
2011 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
2012 | return false; | |
4d88954d | 2013 | |
2d11123a AK |
2014 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
2015 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
2016 | return true; | |
2017 | } | |
2018 | ||
c2a2ac2b XG |
2019 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
2020 | u64 spte) | |
2d11123a | 2021 | { |
c2a2ac2b | 2022 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
2023 | iterator->level = 0; |
2024 | return; | |
2025 | } | |
2026 | ||
c2a2ac2b | 2027 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
2028 | --iterator->level; |
2029 | } | |
2030 | ||
c2a2ac2b XG |
2031 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
2032 | { | |
2033 | return __shadow_walk_next(iterator, *iterator->sptep); | |
2034 | } | |
2035 | ||
32ef26a3 AK |
2036 | static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp) |
2037 | { | |
2038 | u64 spte; | |
2039 | ||
24db2734 XG |
2040 | spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
2041 | shadow_user_mask | shadow_x_mask | shadow_accessed_mask; | |
2042 | ||
1df9f2dc | 2043 | mmu_spte_set(sptep, spte); |
32ef26a3 AK |
2044 | } |
2045 | ||
a357bd22 AK |
2046 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2047 | unsigned direct_access) | |
2048 | { | |
2049 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
2050 | struct kvm_mmu_page *child; | |
2051 | ||
2052 | /* | |
2053 | * For the direct sp, if the guest pte's dirty bit | |
2054 | * changed form clean to dirty, it will corrupt the | |
2055 | * sp's access: allow writable in the read-only sp, | |
2056 | * so we should update the spte at this point to get | |
2057 | * a new sp with the correct access. | |
2058 | */ | |
2059 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
2060 | if (child->role.access == direct_access) | |
2061 | return; | |
2062 | ||
bcdd9a93 | 2063 | drop_parent_pte(child, sptep); |
a357bd22 AK |
2064 | kvm_flush_remote_tlbs(vcpu->kvm); |
2065 | } | |
2066 | } | |
2067 | ||
505aef8f | 2068 | static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
38e3b2b2 XG |
2069 | u64 *spte) |
2070 | { | |
2071 | u64 pte; | |
2072 | struct kvm_mmu_page *child; | |
2073 | ||
2074 | pte = *spte; | |
2075 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2076 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2077 | drop_spte(kvm, spte); |
505aef8f XG |
2078 | if (is_large_pte(pte)) |
2079 | --kvm->stat.lpages; | |
2080 | } else { | |
38e3b2b2 | 2081 | child = page_header(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2082 | drop_parent_pte(child, spte); |
38e3b2b2 | 2083 | } |
505aef8f XG |
2084 | return true; |
2085 | } | |
2086 | ||
2087 | if (is_mmio_spte(pte)) | |
ce88decf | 2088 | mmu_spte_clear_no_track(spte); |
c3707958 | 2089 | |
505aef8f | 2090 | return false; |
38e3b2b2 XG |
2091 | } |
2092 | ||
90cb0529 | 2093 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 2094 | struct kvm_mmu_page *sp) |
a436036b | 2095 | { |
697fe2e2 | 2096 | unsigned i; |
697fe2e2 | 2097 | |
38e3b2b2 XG |
2098 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2099 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
2100 | } |
2101 | ||
4db35314 | 2102 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 2103 | { |
4db35314 | 2104 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
2105 | } |
2106 | ||
31aa2b44 | 2107 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2108 | { |
1e3f42f0 TY |
2109 | u64 *sptep; |
2110 | struct rmap_iterator iter; | |
a436036b | 2111 | |
1e3f42f0 TY |
2112 | while ((sptep = rmap_get_first(sp->parent_ptes, &iter))) |
2113 | drop_parent_pte(sp, sptep); | |
31aa2b44 AK |
2114 | } |
2115 | ||
60c8aec6 | 2116 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2117 | struct kvm_mmu_page *parent, |
2118 | struct list_head *invalid_list) | |
4731d4c7 | 2119 | { |
60c8aec6 MT |
2120 | int i, zapped = 0; |
2121 | struct mmu_page_path parents; | |
2122 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2123 | |
60c8aec6 | 2124 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2125 | return 0; |
60c8aec6 MT |
2126 | |
2127 | kvm_mmu_pages_init(parent, &parents, &pages); | |
2128 | while (mmu_unsync_walk(parent, &pages)) { | |
2129 | struct kvm_mmu_page *sp; | |
2130 | ||
2131 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2132 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2133 | mmu_pages_clear_parents(&parents); |
77662e00 | 2134 | zapped++; |
60c8aec6 | 2135 | } |
60c8aec6 MT |
2136 | kvm_mmu_pages_init(parent, &parents, &pages); |
2137 | } | |
2138 | ||
2139 | return zapped; | |
4731d4c7 MT |
2140 | } |
2141 | ||
7775834a XG |
2142 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2143 | struct list_head *invalid_list) | |
31aa2b44 | 2144 | { |
4731d4c7 | 2145 | int ret; |
f691fe1d | 2146 | |
7775834a | 2147 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2148 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 2149 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 2150 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 2151 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2152 | |
f6e2c02b | 2153 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 2154 | unaccount_shadowed(kvm, sp->gfn); |
5304b8d3 | 2155 | |
4731d4c7 MT |
2156 | if (sp->unsync) |
2157 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2158 | if (!sp->root_count) { |
54a4f023 GJ |
2159 | /* Count self */ |
2160 | ret++; | |
7775834a | 2161 | list_move(&sp->link, invalid_list); |
aa6bd187 | 2162 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2163 | } else { |
5b5c6a5a | 2164 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
05988d72 GN |
2165 | |
2166 | /* | |
2167 | * The obsolete pages can not be used on any vcpus. | |
2168 | * See the comments in kvm_mmu_invalidate_zap_all_pages(). | |
2169 | */ | |
2170 | if (!sp->role.invalid && !is_obsolete_sp(kvm, sp)) | |
2171 | kvm_reload_remote_mmus(kvm); | |
2e53d63a | 2172 | } |
7775834a XG |
2173 | |
2174 | sp->role.invalid = 1; | |
4731d4c7 | 2175 | return ret; |
a436036b AK |
2176 | } |
2177 | ||
7775834a XG |
2178 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2179 | struct list_head *invalid_list) | |
2180 | { | |
945315b9 | 2181 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2182 | |
2183 | if (list_empty(invalid_list)) | |
2184 | return; | |
2185 | ||
c142786c AK |
2186 | /* |
2187 | * wmb: make sure everyone sees our modifications to the page tables | |
2188 | * rmb: make sure we see changes to vcpu->mode | |
2189 | */ | |
2190 | smp_mb(); | |
4f022648 | 2191 | |
c142786c AK |
2192 | /* |
2193 | * Wait for all vcpus to exit guest mode and/or lockless shadow | |
2194 | * page table walks. | |
2195 | */ | |
2196 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2197 | |
945315b9 | 2198 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2199 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2200 | kvm_mmu_free_page(sp); |
945315b9 | 2201 | } |
7775834a XG |
2202 | } |
2203 | ||
5da59607 TY |
2204 | static bool prepare_zap_oldest_mmu_page(struct kvm *kvm, |
2205 | struct list_head *invalid_list) | |
2206 | { | |
2207 | struct kvm_mmu_page *sp; | |
2208 | ||
2209 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
2210 | return false; | |
2211 | ||
2212 | sp = list_entry(kvm->arch.active_mmu_pages.prev, | |
2213 | struct kvm_mmu_page, link); | |
2214 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); | |
2215 | ||
2216 | return true; | |
2217 | } | |
2218 | ||
82ce2c96 IE |
2219 | /* |
2220 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2221 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2222 | */ |
49d5ca26 | 2223 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 2224 | { |
d98ba053 | 2225 | LIST_HEAD(invalid_list); |
82ce2c96 | 2226 | |
b34cb590 TY |
2227 | spin_lock(&kvm->mmu_lock); |
2228 | ||
49d5ca26 | 2229 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
5da59607 TY |
2230 | /* Need to free some mmu pages to achieve the goal. */ |
2231 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) | |
2232 | if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list)) | |
2233 | break; | |
82ce2c96 | 2234 | |
aa6bd187 | 2235 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 2236 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2237 | } |
82ce2c96 | 2238 | |
49d5ca26 | 2239 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 TY |
2240 | |
2241 | spin_unlock(&kvm->mmu_lock); | |
82ce2c96 IE |
2242 | } |
2243 | ||
1cb3f3ae | 2244 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2245 | { |
4db35314 | 2246 | struct kvm_mmu_page *sp; |
d98ba053 | 2247 | LIST_HEAD(invalid_list); |
a436036b AK |
2248 | int r; |
2249 | ||
9ad17b10 | 2250 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2251 | r = 0; |
1cb3f3ae | 2252 | spin_lock(&kvm->mmu_lock); |
b67bfe0d | 2253 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2254 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2255 | sp->role.word); |
2256 | r = 1; | |
f41d335a | 2257 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2258 | } |
d98ba053 | 2259 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2260 | spin_unlock(&kvm->mmu_lock); |
2261 | ||
a436036b | 2262 | return r; |
cea0f0e7 | 2263 | } |
1cb3f3ae | 2264 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2265 | |
74be52e3 SY |
2266 | /* |
2267 | * The function is based on mtrr_type_lookup() in | |
2268 | * arch/x86/kernel/cpu/mtrr/generic.c | |
2269 | */ | |
2270 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
2271 | u64 start, u64 end) | |
2272 | { | |
2273 | int i; | |
2274 | u64 base, mask; | |
2275 | u8 prev_match, curr_match; | |
2276 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
2277 | ||
2278 | if (!mtrr_state->enabled) | |
2279 | return 0xFF; | |
2280 | ||
2281 | /* Make end inclusive end, instead of exclusive */ | |
2282 | end--; | |
2283 | ||
2284 | /* Look in fixed ranges. Just return the type as per start */ | |
2285 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
2286 | int idx; | |
2287 | ||
2288 | if (start < 0x80000) { | |
2289 | idx = 0; | |
2290 | idx += (start >> 16); | |
2291 | return mtrr_state->fixed_ranges[idx]; | |
2292 | } else if (start < 0xC0000) { | |
2293 | idx = 1 * 8; | |
2294 | idx += ((start - 0x80000) >> 14); | |
2295 | return mtrr_state->fixed_ranges[idx]; | |
2296 | } else if (start < 0x1000000) { | |
2297 | idx = 3 * 8; | |
2298 | idx += ((start - 0xC0000) >> 12); | |
2299 | return mtrr_state->fixed_ranges[idx]; | |
2300 | } | |
2301 | } | |
2302 | ||
2303 | /* | |
2304 | * Look in variable ranges | |
2305 | * Look of multiple ranges matching this address and pick type | |
2306 | * as per MTRR precedence | |
2307 | */ | |
2308 | if (!(mtrr_state->enabled & 2)) | |
2309 | return mtrr_state->def_type; | |
2310 | ||
2311 | prev_match = 0xFF; | |
2312 | for (i = 0; i < num_var_ranges; ++i) { | |
2313 | unsigned short start_state, end_state; | |
2314 | ||
2315 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
2316 | continue; | |
2317 | ||
2318 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
2319 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
2320 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
2321 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
2322 | ||
2323 | start_state = ((start & mask) == (base & mask)); | |
2324 | end_state = ((end & mask) == (base & mask)); | |
2325 | if (start_state != end_state) | |
2326 | return 0xFE; | |
2327 | ||
2328 | if ((start & mask) != (base & mask)) | |
2329 | continue; | |
2330 | ||
2331 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
2332 | if (prev_match == 0xFF) { | |
2333 | prev_match = curr_match; | |
2334 | continue; | |
2335 | } | |
2336 | ||
2337 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
2338 | curr_match == MTRR_TYPE_UNCACHABLE) | |
2339 | return MTRR_TYPE_UNCACHABLE; | |
2340 | ||
2341 | if ((prev_match == MTRR_TYPE_WRBACK && | |
2342 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
2343 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
2344 | curr_match == MTRR_TYPE_WRBACK)) { | |
2345 | prev_match = MTRR_TYPE_WRTHROUGH; | |
2346 | curr_match = MTRR_TYPE_WRTHROUGH; | |
2347 | } | |
2348 | ||
2349 | if (prev_match != curr_match) | |
2350 | return MTRR_TYPE_UNCACHABLE; | |
2351 | } | |
2352 | ||
2353 | if (prev_match != 0xFF) | |
2354 | return prev_match; | |
2355 | ||
2356 | return mtrr_state->def_type; | |
2357 | } | |
2358 | ||
4b12f0de | 2359 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
2360 | { |
2361 | u8 mtrr; | |
2362 | ||
2363 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
2364 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
2365 | if (mtrr == 0xfe || mtrr == 0xff) | |
2366 | mtrr = MTRR_TYPE_WRBACK; | |
2367 | return mtrr; | |
2368 | } | |
4b12f0de | 2369 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 2370 | |
9cf5cf5a XG |
2371 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
2372 | { | |
2373 | trace_kvm_mmu_unsync_page(sp); | |
2374 | ++vcpu->kvm->stat.mmu_unsync; | |
2375 | sp->unsync = 1; | |
2376 | ||
2377 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2378 | } |
2379 | ||
2380 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 2381 | { |
4731d4c7 | 2382 | struct kvm_mmu_page *s; |
9cf5cf5a | 2383 | |
b67bfe0d | 2384 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 2385 | if (s->unsync) |
4731d4c7 | 2386 | continue; |
9cf5cf5a XG |
2387 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
2388 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 2389 | } |
4731d4c7 MT |
2390 | } |
2391 | ||
2392 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
2393 | bool can_unsync) | |
2394 | { | |
9cf5cf5a | 2395 | struct kvm_mmu_page *s; |
9cf5cf5a XG |
2396 | bool need_unsync = false; |
2397 | ||
b67bfe0d | 2398 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
36a2e677 XG |
2399 | if (!can_unsync) |
2400 | return 1; | |
2401 | ||
9cf5cf5a | 2402 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2403 | return 1; |
9cf5cf5a | 2404 | |
9bb4f6b1 | 2405 | if (!s->unsync) |
9cf5cf5a | 2406 | need_unsync = true; |
4731d4c7 | 2407 | } |
9cf5cf5a XG |
2408 | if (need_unsync) |
2409 | kvm_unsync_pages(vcpu, gfn); | |
4731d4c7 MT |
2410 | return 0; |
2411 | } | |
2412 | ||
d555c333 | 2413 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
c2288505 | 2414 | unsigned pte_access, int level, |
c2d0ee46 | 2415 | gfn_t gfn, pfn_t pfn, bool speculative, |
9bdbba13 | 2416 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2417 | { |
6e7d0354 | 2418 | u64 spte; |
1e73f9dd | 2419 | int ret = 0; |
64d4d521 | 2420 | |
f2fd125d | 2421 | if (set_mmio_spte(vcpu->kvm, sptep, gfn, pfn, pte_access)) |
ce88decf XG |
2422 | return 0; |
2423 | ||
982c2565 | 2424 | spte = PT_PRESENT_MASK; |
947da538 | 2425 | if (!speculative) |
3201b5d9 | 2426 | spte |= shadow_accessed_mask; |
640d9b0d | 2427 | |
7b52345e SY |
2428 | if (pte_access & ACC_EXEC_MASK) |
2429 | spte |= shadow_x_mask; | |
2430 | else | |
2431 | spte |= shadow_nx_mask; | |
49fde340 | 2432 | |
1c4f1fd6 | 2433 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2434 | spte |= shadow_user_mask; |
49fde340 | 2435 | |
852e3c19 | 2436 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2437 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2438 | if (tdp_enabled) |
4b12f0de SY |
2439 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
2440 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 2441 | |
9bdbba13 | 2442 | if (host_writable) |
1403283a | 2443 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2444 | else |
2445 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2446 | |
35149e21 | 2447 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 | 2448 | |
c2288505 | 2449 | if (pte_access & ACC_WRITE_MASK) { |
1c4f1fd6 | 2450 | |
c2193463 | 2451 | /* |
7751babd XG |
2452 | * Other vcpu creates new sp in the window between |
2453 | * mapping_level() and acquiring mmu-lock. We can | |
2454 | * allow guest to retry the access, the mapping can | |
2455 | * be fixed if guest refault. | |
c2193463 | 2456 | */ |
852e3c19 | 2457 | if (level > PT_PAGE_TABLE_LEVEL && |
c2193463 | 2458 | has_wrprotected_page(vcpu->kvm, gfn, level)) |
be38d276 | 2459 | goto done; |
38187c83 | 2460 | |
49fde340 | 2461 | spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE; |
1c4f1fd6 | 2462 | |
ecc5589f MT |
2463 | /* |
2464 | * Optimization: for pte sync, if spte was writable the hash | |
2465 | * lookup is unnecessary (and expensive). Write protection | |
2466 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2467 | * Same reasoning can be applied to dirty page accounting. | |
2468 | */ | |
8dae4445 | 2469 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2470 | goto set_pte; |
2471 | ||
4731d4c7 | 2472 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2473 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2474 | __func__, gfn); |
1e73f9dd | 2475 | ret = 1; |
1c4f1fd6 | 2476 | pte_access &= ~ACC_WRITE_MASK; |
49fde340 | 2477 | spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE); |
1c4f1fd6 AK |
2478 | } |
2479 | } | |
2480 | ||
1c4f1fd6 AK |
2481 | if (pte_access & ACC_WRITE_MASK) |
2482 | mark_page_dirty(vcpu->kvm, gfn); | |
2483 | ||
38187c83 | 2484 | set_pte: |
6e7d0354 | 2485 | if (mmu_spte_update(sptep, spte)) |
b330aa0c | 2486 | kvm_flush_remote_tlbs(vcpu->kvm); |
be38d276 | 2487 | done: |
1e73f9dd MT |
2488 | return ret; |
2489 | } | |
2490 | ||
d555c333 | 2491 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
f7616203 XG |
2492 | unsigned pte_access, int write_fault, int *emulate, |
2493 | int level, gfn_t gfn, pfn_t pfn, bool speculative, | |
2494 | bool host_writable) | |
1e73f9dd MT |
2495 | { |
2496 | int was_rmapped = 0; | |
53a27b39 | 2497 | int rmap_count; |
1e73f9dd | 2498 | |
f7616203 XG |
2499 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
2500 | *sptep, write_fault, gfn); | |
1e73f9dd | 2501 | |
d555c333 | 2502 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
2503 | /* |
2504 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2505 | * the parent of the now unreachable PTE. | |
2506 | */ | |
852e3c19 JR |
2507 | if (level > PT_PAGE_TABLE_LEVEL && |
2508 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2509 | struct kvm_mmu_page *child; |
d555c333 | 2510 | u64 pte = *sptep; |
1e73f9dd MT |
2511 | |
2512 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 2513 | drop_parent_pte(child, sptep); |
3be2264b | 2514 | kvm_flush_remote_tlbs(vcpu->kvm); |
d555c333 | 2515 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2516 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2517 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2518 | drop_spte(vcpu->kvm, sptep); |
91546356 | 2519 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2520 | } else |
2521 | was_rmapped = 1; | |
1e73f9dd | 2522 | } |
852e3c19 | 2523 | |
c2288505 XG |
2524 | if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative, |
2525 | true, host_writable)) { | |
1e73f9dd | 2526 | if (write_fault) |
b90a0e6c | 2527 | *emulate = 1; |
5304efde | 2528 | kvm_mmu_flush_tlb(vcpu); |
a378b4e6 | 2529 | } |
1e73f9dd | 2530 | |
ce88decf XG |
2531 | if (unlikely(is_mmio_spte(*sptep) && emulate)) |
2532 | *emulate = 1; | |
2533 | ||
d555c333 | 2534 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2535 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2536 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
2537 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
2538 | *sptep, sptep); | |
d555c333 | 2539 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2540 | ++vcpu->kvm->stat.lpages; |
2541 | ||
ffb61bb3 | 2542 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
2543 | if (!was_rmapped) { |
2544 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2545 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2546 | rmap_recycle(vcpu, sptep, gfn); | |
2547 | } | |
1c4f1fd6 | 2548 | } |
cb9aaa30 | 2549 | |
f3ac1a4b | 2550 | kvm_release_pfn_clean(pfn); |
1c4f1fd6 AK |
2551 | } |
2552 | ||
6aa8b732 AK |
2553 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
2554 | { | |
e676505a | 2555 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2556 | } |
2557 | ||
a052b42b XG |
2558 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) |
2559 | { | |
2560 | int bit7; | |
2561 | ||
2562 | bit7 = (gpte >> 7) & 1; | |
2563 | return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0; | |
2564 | } | |
2565 | ||
957ed9ef XG |
2566 | static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
2567 | bool no_dirty_log) | |
2568 | { | |
2569 | struct kvm_memory_slot *slot; | |
957ed9ef | 2570 | |
5d163b1c | 2571 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 2572 | if (!slot) |
6c8ee57b | 2573 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 2574 | |
037d92dc | 2575 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
2576 | } |
2577 | ||
a052b42b XG |
2578 | static bool prefetch_invalid_gpte(struct kvm_vcpu *vcpu, |
2579 | struct kvm_mmu_page *sp, u64 *spte, | |
2580 | u64 gpte) | |
2581 | { | |
2582 | if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) | |
2583 | goto no_present; | |
2584 | ||
2585 | if (!is_present_gpte(gpte)) | |
2586 | goto no_present; | |
2587 | ||
2588 | if (!(gpte & PT_ACCESSED_MASK)) | |
2589 | goto no_present; | |
2590 | ||
2591 | return false; | |
2592 | ||
2593 | no_present: | |
2594 | drop_spte(vcpu->kvm, spte); | |
2595 | return true; | |
2596 | } | |
2597 | ||
957ed9ef XG |
2598 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, |
2599 | struct kvm_mmu_page *sp, | |
2600 | u64 *start, u64 *end) | |
2601 | { | |
2602 | struct page *pages[PTE_PREFETCH_NUM]; | |
2603 | unsigned access = sp->role.access; | |
2604 | int i, ret; | |
2605 | gfn_t gfn; | |
2606 | ||
2607 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
5d163b1c | 2608 | if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK)) |
957ed9ef XG |
2609 | return -1; |
2610 | ||
2611 | ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start); | |
2612 | if (ret <= 0) | |
2613 | return -1; | |
2614 | ||
2615 | for (i = 0; i < ret; i++, gfn++, start++) | |
f7616203 | 2616 | mmu_set_spte(vcpu, start, access, 0, NULL, |
c2288505 XG |
2617 | sp->role.level, gfn, page_to_pfn(pages[i]), |
2618 | true, true); | |
957ed9ef XG |
2619 | |
2620 | return 0; | |
2621 | } | |
2622 | ||
2623 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2624 | struct kvm_mmu_page *sp, u64 *sptep) | |
2625 | { | |
2626 | u64 *spte, *start = NULL; | |
2627 | int i; | |
2628 | ||
2629 | WARN_ON(!sp->role.direct); | |
2630 | ||
2631 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2632 | spte = sp->spt + i; | |
2633 | ||
2634 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2635 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2636 | if (!start) |
2637 | continue; | |
2638 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2639 | break; | |
2640 | start = NULL; | |
2641 | } else if (!start) | |
2642 | start = spte; | |
2643 | } | |
2644 | } | |
2645 | ||
2646 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2647 | { | |
2648 | struct kvm_mmu_page *sp; | |
2649 | ||
2650 | /* | |
2651 | * Since it's no accessed bit on EPT, it's no way to | |
2652 | * distinguish between actually accessed translations | |
2653 | * and prefetched, so disable pte prefetch if EPT is | |
2654 | * enabled. | |
2655 | */ | |
2656 | if (!shadow_accessed_mask) | |
2657 | return; | |
2658 | ||
2659 | sp = page_header(__pa(sptep)); | |
2660 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2661 | return; | |
2662 | ||
2663 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2664 | } | |
2665 | ||
9f652d21 | 2666 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
2ec4739d XG |
2667 | int map_writable, int level, gfn_t gfn, pfn_t pfn, |
2668 | bool prefault) | |
140754bc | 2669 | { |
9f652d21 | 2670 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2671 | struct kvm_mmu_page *sp; |
b90a0e6c | 2672 | int emulate = 0; |
140754bc | 2673 | gfn_t pseudo_gfn; |
6aa8b732 | 2674 | |
9f652d21 | 2675 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2676 | if (iterator.level == level) { |
f7616203 | 2677 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, |
c2288505 XG |
2678 | write, &emulate, level, gfn, pfn, |
2679 | prefault, map_writable); | |
957ed9ef | 2680 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2681 | ++vcpu->stat.pf_fixed; |
2682 | break; | |
6aa8b732 AK |
2683 | } |
2684 | ||
c3707958 | 2685 | if (!is_shadow_present_pte(*iterator.sptep)) { |
c9fa0b3b LJ |
2686 | u64 base_addr = iterator.addr; |
2687 | ||
2688 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2689 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 AK |
2690 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
2691 | iterator.level - 1, | |
2692 | 1, ACC_ALL, iterator.sptep); | |
140754bc | 2693 | |
24db2734 | 2694 | link_shadow_page(iterator.sptep, sp); |
9f652d21 AK |
2695 | } |
2696 | } | |
b90a0e6c | 2697 | return emulate; |
6aa8b732 AK |
2698 | } |
2699 | ||
77db5cbd | 2700 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2701 | { |
77db5cbd HY |
2702 | siginfo_t info; |
2703 | ||
2704 | info.si_signo = SIGBUS; | |
2705 | info.si_errno = 0; | |
2706 | info.si_code = BUS_MCEERR_AR; | |
2707 | info.si_addr = (void __user *)address; | |
2708 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 2709 | |
77db5cbd | 2710 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
2711 | } |
2712 | ||
d7c55201 | 2713 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn) |
bf998156 | 2714 | { |
4d8b81ab XG |
2715 | /* |
2716 | * Do not cache the mmio info caused by writing the readonly gfn | |
2717 | * into the spte otherwise read access on readonly gfn also can | |
2718 | * caused mmio page fault and treat it as mmio access. | |
2719 | * Return 1 to tell kvm to emulate it. | |
2720 | */ | |
2721 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
2722 | return 1; | |
2723 | ||
e6c1502b | 2724 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
bebb106a | 2725 | kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current); |
bf998156 | 2726 | return 0; |
d7c55201 | 2727 | } |
edba23e5 | 2728 | |
d7c55201 | 2729 | return -EFAULT; |
bf998156 HY |
2730 | } |
2731 | ||
936a5fe6 AA |
2732 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
2733 | gfn_t *gfnp, pfn_t *pfnp, int *levelp) | |
2734 | { | |
2735 | pfn_t pfn = *pfnp; | |
2736 | gfn_t gfn = *gfnp; | |
2737 | int level = *levelp; | |
2738 | ||
2739 | /* | |
2740 | * Check if it's a transparent hugepage. If this would be an | |
2741 | * hugetlbfs page, level wouldn't be set to | |
2742 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
2743 | * here. | |
2744 | */ | |
81c52c56 | 2745 | if (!is_error_noslot_pfn(pfn) && !kvm_is_mmio_pfn(pfn) && |
936a5fe6 AA |
2746 | level == PT_PAGE_TABLE_LEVEL && |
2747 | PageTransCompound(pfn_to_page(pfn)) && | |
2748 | !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) { | |
2749 | unsigned long mask; | |
2750 | /* | |
2751 | * mmu_notifier_retry was successful and we hold the | |
2752 | * mmu_lock here, so the pmd can't become splitting | |
2753 | * from under us, and in turn | |
2754 | * __split_huge_page_refcount() can't run from under | |
2755 | * us and we can safely transfer the refcount from | |
2756 | * PG_tail to PG_head as we switch the pfn to tail to | |
2757 | * head. | |
2758 | */ | |
2759 | *levelp = level = PT_DIRECTORY_LEVEL; | |
2760 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
2761 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2762 | if (pfn & mask) { | |
2763 | gfn &= ~mask; | |
2764 | *gfnp = gfn; | |
2765 | kvm_release_pfn_clean(pfn); | |
2766 | pfn &= ~mask; | |
c3586667 | 2767 | kvm_get_pfn(pfn); |
936a5fe6 AA |
2768 | *pfnp = pfn; |
2769 | } | |
2770 | } | |
2771 | } | |
2772 | ||
d7c55201 XG |
2773 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
2774 | pfn_t pfn, unsigned access, int *ret_val) | |
2775 | { | |
2776 | bool ret = true; | |
2777 | ||
2778 | /* The pfn is invalid, report the error! */ | |
81c52c56 | 2779 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 XG |
2780 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
2781 | goto exit; | |
2782 | } | |
2783 | ||
ce88decf | 2784 | if (unlikely(is_noslot_pfn(pfn))) |
d7c55201 | 2785 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); |
d7c55201 XG |
2786 | |
2787 | ret = false; | |
2788 | exit: | |
2789 | return ret; | |
2790 | } | |
2791 | ||
c7ba5b48 XG |
2792 | static bool page_fault_can_be_fast(struct kvm_vcpu *vcpu, u32 error_code) |
2793 | { | |
2794 | /* | |
2795 | * #PF can be fast only if the shadow page table is present and it | |
2796 | * is caused by write-protect, that means we just need change the | |
2797 | * W bit of the spte which can be done out of mmu-lock. | |
2798 | */ | |
2799 | if (!(error_code & PFERR_PRESENT_MASK) || | |
2800 | !(error_code & PFERR_WRITE_MASK)) | |
2801 | return false; | |
2802 | ||
2803 | return true; | |
2804 | } | |
2805 | ||
2806 | static bool | |
2807 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 spte) | |
2808 | { | |
2809 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
2810 | gfn_t gfn; | |
2811 | ||
2812 | WARN_ON(!sp->role.direct); | |
2813 | ||
2814 | /* | |
2815 | * The gfn of direct spte is stable since it is calculated | |
2816 | * by sp->gfn. | |
2817 | */ | |
2818 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
2819 | ||
2820 | if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte) | |
2821 | mark_page_dirty(vcpu->kvm, gfn); | |
2822 | ||
2823 | return true; | |
2824 | } | |
2825 | ||
2826 | /* | |
2827 | * Return value: | |
2828 | * - true: let the vcpu to access on the same address again. | |
2829 | * - false: let the real page fault path to fix it. | |
2830 | */ | |
2831 | static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, | |
2832 | u32 error_code) | |
2833 | { | |
2834 | struct kvm_shadow_walk_iterator iterator; | |
2835 | bool ret = false; | |
2836 | u64 spte = 0ull; | |
2837 | ||
2838 | if (!page_fault_can_be_fast(vcpu, error_code)) | |
2839 | return false; | |
2840 | ||
2841 | walk_shadow_page_lockless_begin(vcpu); | |
2842 | for_each_shadow_entry_lockless(vcpu, gva, iterator, spte) | |
2843 | if (!is_shadow_present_pte(spte) || iterator.level < level) | |
2844 | break; | |
2845 | ||
2846 | /* | |
2847 | * If the mapping has been changed, let the vcpu fault on the | |
2848 | * same address again. | |
2849 | */ | |
2850 | if (!is_rmap_spte(spte)) { | |
2851 | ret = true; | |
2852 | goto exit; | |
2853 | } | |
2854 | ||
2855 | if (!is_last_spte(spte, level)) | |
2856 | goto exit; | |
2857 | ||
2858 | /* | |
2859 | * Check if it is a spurious fault caused by TLB lazily flushed. | |
2860 | * | |
2861 | * Need not check the access of upper level table entries since | |
2862 | * they are always ACC_ALL. | |
2863 | */ | |
2864 | if (is_writable_pte(spte)) { | |
2865 | ret = true; | |
2866 | goto exit; | |
2867 | } | |
2868 | ||
2869 | /* | |
2870 | * Currently, to simplify the code, only the spte write-protected | |
2871 | * by dirty-log can be fast fixed. | |
2872 | */ | |
2873 | if (!spte_is_locklessly_modifiable(spte)) | |
2874 | goto exit; | |
2875 | ||
2876 | /* | |
2877 | * Currently, fast page fault only works for direct mapping since | |
2878 | * the gfn is not stable for indirect shadow page. | |
2879 | * See Documentation/virtual/kvm/locking.txt to get more detail. | |
2880 | */ | |
2881 | ret = fast_pf_fix_direct_spte(vcpu, iterator.sptep, spte); | |
2882 | exit: | |
a72faf25 XG |
2883 | trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep, |
2884 | spte, ret); | |
c7ba5b48 XG |
2885 | walk_shadow_page_lockless_end(vcpu); |
2886 | ||
2887 | return ret; | |
2888 | } | |
2889 | ||
78b2c54a | 2890 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
060c2abe | 2891 | gva_t gva, pfn_t *pfn, bool write, bool *writable); |
450e0b41 | 2892 | static void make_mmu_pages_available(struct kvm_vcpu *vcpu); |
060c2abe | 2893 | |
c7ba5b48 XG |
2894 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code, |
2895 | gfn_t gfn, bool prefault) | |
10589a46 MT |
2896 | { |
2897 | int r; | |
852e3c19 | 2898 | int level; |
936a5fe6 | 2899 | int force_pt_level; |
35149e21 | 2900 | pfn_t pfn; |
e930bffe | 2901 | unsigned long mmu_seq; |
c7ba5b48 | 2902 | bool map_writable, write = error_code & PFERR_WRITE_MASK; |
aaee2c94 | 2903 | |
936a5fe6 AA |
2904 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
2905 | if (likely(!force_pt_level)) { | |
2906 | level = mapping_level(vcpu, gfn); | |
2907 | /* | |
2908 | * This path builds a PAE pagetable - so we can map | |
2909 | * 2mb pages at maximum. Therefore check if the level | |
2910 | * is larger than that. | |
2911 | */ | |
2912 | if (level > PT_DIRECTORY_LEVEL) | |
2913 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 2914 | |
936a5fe6 AA |
2915 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
2916 | } else | |
2917 | level = PT_PAGE_TABLE_LEVEL; | |
05da4558 | 2918 | |
c7ba5b48 XG |
2919 | if (fast_page_fault(vcpu, v, level, error_code)) |
2920 | return 0; | |
2921 | ||
e930bffe | 2922 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2923 | smp_rmb(); |
060c2abe | 2924 | |
78b2c54a | 2925 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
060c2abe | 2926 | return 0; |
aaee2c94 | 2927 | |
d7c55201 XG |
2928 | if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r)) |
2929 | return r; | |
d196e343 | 2930 | |
aaee2c94 | 2931 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 2932 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 2933 | goto out_unlock; |
450e0b41 | 2934 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
2935 | if (likely(!force_pt_level)) |
2936 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
2ec4739d XG |
2937 | r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn, |
2938 | prefault); | |
aaee2c94 MT |
2939 | spin_unlock(&vcpu->kvm->mmu_lock); |
2940 | ||
aaee2c94 | 2941 | |
10589a46 | 2942 | return r; |
e930bffe AA |
2943 | |
2944 | out_unlock: | |
2945 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2946 | kvm_release_pfn_clean(pfn); | |
2947 | return 0; | |
10589a46 MT |
2948 | } |
2949 | ||
2950 | ||
17ac10ad AK |
2951 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
2952 | { | |
2953 | int i; | |
4db35314 | 2954 | struct kvm_mmu_page *sp; |
d98ba053 | 2955 | LIST_HEAD(invalid_list); |
17ac10ad | 2956 | |
ad312c7c | 2957 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 2958 | return; |
35af577a | 2959 | |
81407ca5 JR |
2960 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL && |
2961 | (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL || | |
2962 | vcpu->arch.mmu.direct_map)) { | |
ad312c7c | 2963 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 2964 | |
35af577a | 2965 | spin_lock(&vcpu->kvm->mmu_lock); |
4db35314 AK |
2966 | sp = page_header(root); |
2967 | --sp->root_count; | |
d98ba053 XG |
2968 | if (!sp->root_count && sp->role.invalid) { |
2969 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
2970 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
2971 | } | |
aaee2c94 | 2972 | spin_unlock(&vcpu->kvm->mmu_lock); |
35af577a | 2973 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2974 | return; |
2975 | } | |
35af577a GN |
2976 | |
2977 | spin_lock(&vcpu->kvm->mmu_lock); | |
17ac10ad | 2978 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2979 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2980 | |
417726a3 | 2981 | if (root) { |
417726a3 | 2982 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2983 | sp = page_header(root); |
2984 | --sp->root_count; | |
2e53d63a | 2985 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
2986 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2987 | &invalid_list); | |
417726a3 | 2988 | } |
ad312c7c | 2989 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2990 | } |
d98ba053 | 2991 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 2992 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2993 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2994 | } |
2995 | ||
8986ecc0 MT |
2996 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2997 | { | |
2998 | int ret = 0; | |
2999 | ||
3000 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 3001 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
3002 | ret = 1; |
3003 | } | |
3004 | ||
3005 | return ret; | |
3006 | } | |
3007 | ||
651dd37a JR |
3008 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
3009 | { | |
3010 | struct kvm_mmu_page *sp; | |
7ebaf15e | 3011 | unsigned i; |
651dd37a JR |
3012 | |
3013 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3014 | spin_lock(&vcpu->kvm->mmu_lock); | |
450e0b41 | 3015 | make_mmu_pages_available(vcpu); |
651dd37a JR |
3016 | sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, |
3017 | 1, ACC_ALL, NULL); | |
3018 | ++sp->root_count; | |
3019 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3020 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
3021 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
3022 | for (i = 0; i < 4; ++i) { | |
3023 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3024 | ||
3025 | ASSERT(!VALID_PAGE(root)); | |
3026 | spin_lock(&vcpu->kvm->mmu_lock); | |
450e0b41 | 3027 | make_mmu_pages_available(vcpu); |
649497d1 AK |
3028 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
3029 | i << 30, | |
651dd37a JR |
3030 | PT32_ROOT_LEVEL, 1, ACC_ALL, |
3031 | NULL); | |
3032 | root = __pa(sp->spt); | |
3033 | ++sp->root_count; | |
3034 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3035 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 3036 | } |
6292757f | 3037 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
3038 | } else |
3039 | BUG(); | |
3040 | ||
3041 | return 0; | |
3042 | } | |
3043 | ||
3044 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 3045 | { |
4db35314 | 3046 | struct kvm_mmu_page *sp; |
81407ca5 JR |
3047 | u64 pdptr, pm_mask; |
3048 | gfn_t root_gfn; | |
3049 | int i; | |
3bb65a22 | 3050 | |
5777ed34 | 3051 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 3052 | |
651dd37a JR |
3053 | if (mmu_check_root(vcpu, root_gfn)) |
3054 | return 1; | |
3055 | ||
3056 | /* | |
3057 | * Do we shadow a long mode page table? If so we need to | |
3058 | * write-protect the guests page table root. | |
3059 | */ | |
3060 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { | |
ad312c7c | 3061 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad AK |
3062 | |
3063 | ASSERT(!VALID_PAGE(root)); | |
651dd37a | 3064 | |
8facbbff | 3065 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3066 | make_mmu_pages_available(vcpu); |
651dd37a JR |
3067 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, |
3068 | 0, ACC_ALL, NULL); | |
4db35314 AK |
3069 | root = __pa(sp->spt); |
3070 | ++sp->root_count; | |
8facbbff | 3071 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 3072 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 3073 | return 0; |
17ac10ad | 3074 | } |
f87f9288 | 3075 | |
651dd37a JR |
3076 | /* |
3077 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3078 | * or a PAE 3-level page table. In either case we need to be aware that |
3079 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3080 | */ |
81407ca5 JR |
3081 | pm_mask = PT_PRESENT_MASK; |
3082 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) | |
3083 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; | |
3084 | ||
17ac10ad | 3085 | for (i = 0; i < 4; ++i) { |
ad312c7c | 3086 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
3087 | |
3088 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 3089 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 3090 | pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i); |
43a3795a | 3091 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 3092 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
3093 | continue; |
3094 | } | |
6de4f3ad | 3095 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
3096 | if (mmu_check_root(vcpu, root_gfn)) |
3097 | return 1; | |
5a7388c2 | 3098 | } |
8facbbff | 3099 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3100 | make_mmu_pages_available(vcpu); |
4db35314 | 3101 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
651dd37a | 3102 | PT32_ROOT_LEVEL, 0, |
f7d9c7b7 | 3103 | ACC_ALL, NULL); |
4db35314 AK |
3104 | root = __pa(sp->spt); |
3105 | ++sp->root_count; | |
8facbbff AK |
3106 | spin_unlock(&vcpu->kvm->mmu_lock); |
3107 | ||
81407ca5 | 3108 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 3109 | } |
6292757f | 3110 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3111 | |
3112 | /* | |
3113 | * If we shadow a 32 bit page table with a long mode page | |
3114 | * table we enter this path. | |
3115 | */ | |
3116 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3117 | if (vcpu->arch.mmu.lm_root == NULL) { | |
3118 | /* | |
3119 | * The additional page necessary for this is only | |
3120 | * allocated on demand. | |
3121 | */ | |
3122 | ||
3123 | u64 *lm_root; | |
3124 | ||
3125 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
3126 | if (lm_root == NULL) | |
3127 | return 1; | |
3128 | ||
3129 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
3130 | ||
3131 | vcpu->arch.mmu.lm_root = lm_root; | |
3132 | } | |
3133 | ||
3134 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
3135 | } | |
3136 | ||
8986ecc0 | 3137 | return 0; |
17ac10ad AK |
3138 | } |
3139 | ||
651dd37a JR |
3140 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
3141 | { | |
3142 | if (vcpu->arch.mmu.direct_map) | |
3143 | return mmu_alloc_direct_roots(vcpu); | |
3144 | else | |
3145 | return mmu_alloc_shadow_roots(vcpu); | |
3146 | } | |
3147 | ||
0ba73cda MT |
3148 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
3149 | { | |
3150 | int i; | |
3151 | struct kvm_mmu_page *sp; | |
3152 | ||
81407ca5 JR |
3153 | if (vcpu->arch.mmu.direct_map) |
3154 | return; | |
3155 | ||
0ba73cda MT |
3156 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3157 | return; | |
6903074c | 3158 | |
bebb106a | 3159 | vcpu_clear_mmio_info(vcpu, ~0ul); |
0375f7fa | 3160 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
81407ca5 | 3161 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { |
0ba73cda MT |
3162 | hpa_t root = vcpu->arch.mmu.root_hpa; |
3163 | sp = page_header(root); | |
3164 | mmu_sync_children(vcpu, sp); | |
0375f7fa | 3165 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3166 | return; |
3167 | } | |
3168 | for (i = 0; i < 4; ++i) { | |
3169 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3170 | ||
8986ecc0 | 3171 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
3172 | root &= PT64_BASE_ADDR_MASK; |
3173 | sp = page_header(root); | |
3174 | mmu_sync_children(vcpu, sp); | |
3175 | } | |
3176 | } | |
0375f7fa | 3177 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3178 | } |
3179 | ||
3180 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
3181 | { | |
3182 | spin_lock(&vcpu->kvm->mmu_lock); | |
3183 | mmu_sync_roots(vcpu); | |
6cffe8ca | 3184 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3185 | } |
3186 | ||
1871c602 | 3187 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 3188 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3189 | { |
ab9ae313 AK |
3190 | if (exception) |
3191 | exception->error_code = 0; | |
6aa8b732 AK |
3192 | return vaddr; |
3193 | } | |
3194 | ||
6539e738 | 3195 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
3196 | u32 access, |
3197 | struct x86_exception *exception) | |
6539e738 | 3198 | { |
ab9ae313 AK |
3199 | if (exception) |
3200 | exception->error_code = 0; | |
6539e738 JR |
3201 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access); |
3202 | } | |
3203 | ||
ce88decf XG |
3204 | static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
3205 | { | |
3206 | if (direct) | |
3207 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3208 | ||
3209 | return vcpu_match_mmio_gva(vcpu, addr); | |
3210 | } | |
3211 | ||
3212 | ||
3213 | /* | |
3214 | * On direct hosts, the last spte is only allows two states | |
3215 | * for mmio page fault: | |
3216 | * - It is the mmio spte | |
3217 | * - It is zapped or it is being zapped. | |
3218 | * | |
3219 | * This function completely checks the spte when the last spte | |
3220 | * is not the mmio spte. | |
3221 | */ | |
3222 | static bool check_direct_spte_mmio_pf(u64 spte) | |
3223 | { | |
3224 | return __check_direct_spte_mmio_pf(spte); | |
3225 | } | |
3226 | ||
3227 | static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr) | |
3228 | { | |
3229 | struct kvm_shadow_walk_iterator iterator; | |
3230 | u64 spte = 0ull; | |
3231 | ||
3232 | walk_shadow_page_lockless_begin(vcpu); | |
3233 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) | |
3234 | if (!is_shadow_present_pte(spte)) | |
3235 | break; | |
3236 | walk_shadow_page_lockless_end(vcpu); | |
3237 | ||
3238 | return spte; | |
3239 | } | |
3240 | ||
ce88decf XG |
3241 | int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
3242 | { | |
3243 | u64 spte; | |
3244 | ||
3245 | if (quickly_check_mmio_pf(vcpu, addr, direct)) | |
b37fbea6 | 3246 | return RET_MMIO_PF_EMULATE; |
ce88decf XG |
3247 | |
3248 | spte = walk_shadow_page_get_mmio_spte(vcpu, addr); | |
3249 | ||
3250 | if (is_mmio_spte(spte)) { | |
3251 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
3252 | unsigned access = get_mmio_spte_access(spte); | |
3253 | ||
f8f55942 XG |
3254 | if (!check_mmio_spte(vcpu->kvm, spte)) |
3255 | return RET_MMIO_PF_INVALID; | |
3256 | ||
ce88decf XG |
3257 | if (direct) |
3258 | addr = 0; | |
4f022648 XG |
3259 | |
3260 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf | 3261 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
b37fbea6 | 3262 | return RET_MMIO_PF_EMULATE; |
ce88decf XG |
3263 | } |
3264 | ||
3265 | /* | |
3266 | * It's ok if the gva is remapped by other cpus on shadow guest, | |
3267 | * it's a BUG if the gfn is not a mmio page. | |
3268 | */ | |
3269 | if (direct && !check_direct_spte_mmio_pf(spte)) | |
b37fbea6 | 3270 | return RET_MMIO_PF_BUG; |
ce88decf XG |
3271 | |
3272 | /* | |
3273 | * If the page table is zapped by other cpus, let CPU fault again on | |
3274 | * the address. | |
3275 | */ | |
b37fbea6 | 3276 | return RET_MMIO_PF_RETRY; |
ce88decf XG |
3277 | } |
3278 | EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common); | |
3279 | ||
3280 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, | |
3281 | u32 error_code, bool direct) | |
3282 | { | |
3283 | int ret; | |
3284 | ||
3285 | ret = handle_mmio_page_fault_common(vcpu, addr, direct); | |
b37fbea6 | 3286 | WARN_ON(ret == RET_MMIO_PF_BUG); |
ce88decf XG |
3287 | return ret; |
3288 | } | |
3289 | ||
6aa8b732 | 3290 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 3291 | u32 error_code, bool prefault) |
6aa8b732 | 3292 | { |
e833240f | 3293 | gfn_t gfn; |
e2dec939 | 3294 | int r; |
6aa8b732 | 3295 | |
b8688d51 | 3296 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
ce88decf | 3297 | |
f8f55942 XG |
3298 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
3299 | r = handle_mmio_page_fault(vcpu, gva, error_code, true); | |
3300 | ||
3301 | if (likely(r != RET_MMIO_PF_INVALID)) | |
3302 | return r; | |
3303 | } | |
ce88decf | 3304 | |
e2dec939 AK |
3305 | r = mmu_topup_memory_caches(vcpu); |
3306 | if (r) | |
3307 | return r; | |
714b93da | 3308 | |
6aa8b732 | 3309 | ASSERT(vcpu); |
ad312c7c | 3310 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3311 | |
e833240f | 3312 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 3313 | |
e833240f | 3314 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
c7ba5b48 | 3315 | error_code, gfn, prefault); |
6aa8b732 AK |
3316 | } |
3317 | ||
7e1fbeac | 3318 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
3319 | { |
3320 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3321 | |
7c90705b | 3322 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3323 | arch.gfn = gfn; |
c4806acd | 3324 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 3325 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 GN |
3326 | |
3327 | return kvm_setup_async_pf(vcpu, gva, gfn, &arch); | |
3328 | } | |
3329 | ||
3330 | static bool can_do_async_pf(struct kvm_vcpu *vcpu) | |
3331 | { | |
3332 | if (unlikely(!irqchip_in_kernel(vcpu->kvm) || | |
3333 | kvm_event_needs_reinjection(vcpu))) | |
3334 | return false; | |
3335 | ||
3336 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
3337 | } | |
3338 | ||
78b2c54a | 3339 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
612819c3 | 3340 | gva_t gva, pfn_t *pfn, bool write, bool *writable) |
af585b92 GN |
3341 | { |
3342 | bool async; | |
3343 | ||
612819c3 | 3344 | *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable); |
af585b92 GN |
3345 | |
3346 | if (!async) | |
3347 | return false; /* *pfn has correct page already */ | |
3348 | ||
78b2c54a | 3349 | if (!prefault && can_do_async_pf(vcpu)) { |
c9b263d2 | 3350 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
3351 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
3352 | trace_kvm_async_pf_doublefault(gva, gfn); | |
3353 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
3354 | return true; | |
3355 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
3356 | return true; | |
3357 | } | |
3358 | ||
612819c3 | 3359 | *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable); |
af585b92 GN |
3360 | |
3361 | return false; | |
3362 | } | |
3363 | ||
56028d08 | 3364 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 3365 | bool prefault) |
fb72d167 | 3366 | { |
35149e21 | 3367 | pfn_t pfn; |
fb72d167 | 3368 | int r; |
852e3c19 | 3369 | int level; |
936a5fe6 | 3370 | int force_pt_level; |
05da4558 | 3371 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 3372 | unsigned long mmu_seq; |
612819c3 MT |
3373 | int write = error_code & PFERR_WRITE_MASK; |
3374 | bool map_writable; | |
fb72d167 JR |
3375 | |
3376 | ASSERT(vcpu); | |
3377 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
3378 | ||
f8f55942 XG |
3379 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
3380 | r = handle_mmio_page_fault(vcpu, gpa, error_code, true); | |
3381 | ||
3382 | if (likely(r != RET_MMIO_PF_INVALID)) | |
3383 | return r; | |
3384 | } | |
ce88decf | 3385 | |
fb72d167 JR |
3386 | r = mmu_topup_memory_caches(vcpu); |
3387 | if (r) | |
3388 | return r; | |
3389 | ||
936a5fe6 AA |
3390 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
3391 | if (likely(!force_pt_level)) { | |
3392 | level = mapping_level(vcpu, gfn); | |
3393 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
3394 | } else | |
3395 | level = PT_PAGE_TABLE_LEVEL; | |
852e3c19 | 3396 | |
c7ba5b48 XG |
3397 | if (fast_page_fault(vcpu, gpa, level, error_code)) |
3398 | return 0; | |
3399 | ||
e930bffe | 3400 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3401 | smp_rmb(); |
af585b92 | 3402 | |
78b2c54a | 3403 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
af585b92 GN |
3404 | return 0; |
3405 | ||
d7c55201 XG |
3406 | if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r)) |
3407 | return r; | |
3408 | ||
fb72d167 | 3409 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3410 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3411 | goto out_unlock; |
450e0b41 | 3412 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
3413 | if (likely(!force_pt_level)) |
3414 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
612819c3 | 3415 | r = __direct_map(vcpu, gpa, write, map_writable, |
2ec4739d | 3416 | level, gfn, pfn, prefault); |
fb72d167 | 3417 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
3418 | |
3419 | return r; | |
e930bffe AA |
3420 | |
3421 | out_unlock: | |
3422 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3423 | kvm_release_pfn_clean(pfn); | |
3424 | return 0; | |
fb72d167 JR |
3425 | } |
3426 | ||
6aa8b732 AK |
3427 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
3428 | { | |
17ac10ad | 3429 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3430 | } |
3431 | ||
52fde8df JR |
3432 | static int nonpaging_init_context(struct kvm_vcpu *vcpu, |
3433 | struct kvm_mmu *context) | |
6aa8b732 | 3434 | { |
6aa8b732 AK |
3435 | context->new_cr3 = nonpaging_new_cr3; |
3436 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
3437 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
3438 | context->free = nonpaging_free; | |
e8bc217a | 3439 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3440 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3441 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 3442 | context->root_level = 0; |
6aa8b732 | 3443 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3444 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3445 | context->direct_map = true; |
2d48a985 | 3446 | context->nx = false; |
6aa8b732 AK |
3447 | return 0; |
3448 | } | |
3449 | ||
d835dfec | 3450 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 3451 | { |
1165f5fe | 3452 | ++vcpu->stat.tlb_flush; |
a8eeb04a | 3453 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
6aa8b732 AK |
3454 | } |
3455 | ||
3456 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
3457 | { | |
9f8fe504 | 3458 | pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu)); |
cea0f0e7 | 3459 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3460 | } |
3461 | ||
5777ed34 JR |
3462 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
3463 | { | |
9f8fe504 | 3464 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
3465 | } |
3466 | ||
6389ee94 AK |
3467 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
3468 | struct x86_exception *fault) | |
6aa8b732 | 3469 | { |
6389ee94 | 3470 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
3471 | } |
3472 | ||
6aa8b732 AK |
3473 | static void paging_free(struct kvm_vcpu *vcpu) |
3474 | { | |
3475 | nonpaging_free(vcpu); | |
3476 | } | |
3477 | ||
8ea667f2 AK |
3478 | static inline void protect_clean_gpte(unsigned *access, unsigned gpte) |
3479 | { | |
3480 | unsigned mask; | |
3481 | ||
3482 | BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK); | |
3483 | ||
3484 | mask = (unsigned)~ACC_WRITE_MASK; | |
3485 | /* Allow write access to dirty gptes */ | |
3486 | mask |= (gpte >> (PT_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & PT_WRITABLE_MASK; | |
3487 | *access &= mask; | |
3488 | } | |
3489 | ||
f2fd125d XG |
3490 | static bool sync_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn, |
3491 | unsigned access, int *nr_present) | |
ce88decf XG |
3492 | { |
3493 | if (unlikely(is_mmio_spte(*sptep))) { | |
3494 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
3495 | mmu_spte_clear_no_track(sptep); | |
3496 | return true; | |
3497 | } | |
3498 | ||
3499 | (*nr_present)++; | |
f2fd125d | 3500 | mark_mmio_spte(kvm, sptep, gfn, access); |
ce88decf XG |
3501 | return true; |
3502 | } | |
3503 | ||
3504 | return false; | |
3505 | } | |
3506 | ||
3d34adec AK |
3507 | static inline unsigned gpte_access(struct kvm_vcpu *vcpu, u64 gpte) |
3508 | { | |
3509 | unsigned access; | |
3510 | ||
3511 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; | |
3512 | access &= ~(gpte >> PT64_NX_SHIFT); | |
3513 | ||
3514 | return access; | |
3515 | } | |
3516 | ||
6fd01b71 AK |
3517 | static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte) |
3518 | { | |
3519 | unsigned index; | |
3520 | ||
3521 | index = level - 1; | |
3522 | index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2); | |
3523 | return mmu->last_pte_bitmap & (1 << index); | |
3524 | } | |
3525 | ||
6aa8b732 AK |
3526 | #define PTTYPE 64 |
3527 | #include "paging_tmpl.h" | |
3528 | #undef PTTYPE | |
3529 | ||
3530 | #define PTTYPE 32 | |
3531 | #include "paging_tmpl.h" | |
3532 | #undef PTTYPE | |
3533 | ||
52fde8df | 3534 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4d6931c3 | 3535 | struct kvm_mmu *context) |
82725b20 | 3536 | { |
82725b20 DE |
3537 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
3538 | u64 exb_bit_rsvd = 0; | |
3539 | ||
2d48a985 | 3540 | if (!context->nx) |
82725b20 | 3541 | exb_bit_rsvd = rsvd_bits(63, 63); |
4d6931c3 | 3542 | switch (context->root_level) { |
82725b20 DE |
3543 | case PT32_ROOT_LEVEL: |
3544 | /* no rsvd bits for 2 level 4K page table entries */ | |
3545 | context->rsvd_bits_mask[0][1] = 0; | |
3546 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
3547 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
3548 | ||
3549 | if (!is_pse(vcpu)) { | |
3550 | context->rsvd_bits_mask[1][1] = 0; | |
3551 | break; | |
3552 | } | |
3553 | ||
82725b20 DE |
3554 | if (is_cpuid_PSE36()) |
3555 | /* 36bits PSE 4MB page */ | |
3556 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
3557 | else | |
3558 | /* 32 bits PSE 4MB page */ | |
3559 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
3560 | break; |
3561 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
3562 | context->rsvd_bits_mask[0][2] = |
3563 | rsvd_bits(maxphyaddr, 63) | | |
3564 | rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ | |
82725b20 | 3565 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 3566 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
3567 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
3568 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
3569 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
3570 | rsvd_bits(maxphyaddr, 62) | | |
3571 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 3572 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
3573 | break; |
3574 | case PT64_ROOT_LEVEL: | |
3575 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
3576 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
3577 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | | |
3578 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
3579 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | | |
4c26b4cd | 3580 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
3581 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
3582 | rsvd_bits(maxphyaddr, 51); | |
3583 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 JR |
3584 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
3585 | rsvd_bits(maxphyaddr, 51) | | |
3586 | rsvd_bits(13, 29); | |
82725b20 | 3587 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
3588 | rsvd_bits(maxphyaddr, 51) | |
3589 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 3590 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
3591 | break; |
3592 | } | |
3593 | } | |
3594 | ||
97d64b78 AK |
3595 | static void update_permission_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
3596 | { | |
3597 | unsigned bit, byte, pfec; | |
3598 | u8 map; | |
3599 | bool fault, x, w, u, wf, uf, ff, smep; | |
3600 | ||
3601 | smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); | |
3602 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { | |
3603 | pfec = byte << 1; | |
3604 | map = 0; | |
3605 | wf = pfec & PFERR_WRITE_MASK; | |
3606 | uf = pfec & PFERR_USER_MASK; | |
3607 | ff = pfec & PFERR_FETCH_MASK; | |
3608 | for (bit = 0; bit < 8; ++bit) { | |
3609 | x = bit & ACC_EXEC_MASK; | |
3610 | w = bit & ACC_WRITE_MASK; | |
3611 | u = bit & ACC_USER_MASK; | |
3612 | ||
3613 | /* Not really needed: !nx will cause pte.nx to fault */ | |
3614 | x |= !mmu->nx; | |
3615 | /* Allow supervisor writes if !cr0.wp */ | |
3616 | w |= !is_write_protection(vcpu) && !uf; | |
3617 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
3618 | x &= !(smep && u && !uf); | |
3619 | ||
3620 | fault = (ff && !x) || (uf && !u) || (wf && !w); | |
3621 | map |= fault << bit; | |
3622 | } | |
3623 | mmu->permissions[byte] = map; | |
3624 | } | |
3625 | } | |
3626 | ||
6fd01b71 AK |
3627 | static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
3628 | { | |
3629 | u8 map; | |
3630 | unsigned level, root_level = mmu->root_level; | |
3631 | const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */ | |
3632 | ||
3633 | if (root_level == PT32E_ROOT_LEVEL) | |
3634 | --root_level; | |
3635 | /* PT_PAGE_TABLE_LEVEL always terminates */ | |
3636 | map = 1 | (1 << ps_set_index); | |
3637 | for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) { | |
3638 | if (level <= PT_PDPE_LEVEL | |
3639 | && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu))) | |
3640 | map |= 1 << (ps_set_index | (level - 1)); | |
3641 | } | |
3642 | mmu->last_pte_bitmap = map; | |
3643 | } | |
3644 | ||
52fde8df JR |
3645 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, |
3646 | struct kvm_mmu *context, | |
3647 | int level) | |
6aa8b732 | 3648 | { |
2d48a985 | 3649 | context->nx = is_nx(vcpu); |
4d6931c3 | 3650 | context->root_level = level; |
2d48a985 | 3651 | |
4d6931c3 | 3652 | reset_rsvds_bits_mask(vcpu, context); |
97d64b78 | 3653 | update_permission_bitmask(vcpu, context); |
6fd01b71 | 3654 | update_last_pte_bitmap(vcpu, context); |
6aa8b732 AK |
3655 | |
3656 | ASSERT(is_pae(vcpu)); | |
3657 | context->new_cr3 = paging_new_cr3; | |
3658 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 3659 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 3660 | context->sync_page = paging64_sync_page; |
a7052897 | 3661 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 3662 | context->update_pte = paging64_update_pte; |
6aa8b732 | 3663 | context->free = paging_free; |
17ac10ad | 3664 | context->shadow_root_level = level; |
17c3ba9d | 3665 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3666 | context->direct_map = false; |
6aa8b732 AK |
3667 | return 0; |
3668 | } | |
3669 | ||
52fde8df JR |
3670 | static int paging64_init_context(struct kvm_vcpu *vcpu, |
3671 | struct kvm_mmu *context) | |
17ac10ad | 3672 | { |
52fde8df | 3673 | return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
3674 | } |
3675 | ||
52fde8df JR |
3676 | static int paging32_init_context(struct kvm_vcpu *vcpu, |
3677 | struct kvm_mmu *context) | |
6aa8b732 | 3678 | { |
2d48a985 | 3679 | context->nx = false; |
4d6931c3 | 3680 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 3681 | |
4d6931c3 | 3682 | reset_rsvds_bits_mask(vcpu, context); |
97d64b78 | 3683 | update_permission_bitmask(vcpu, context); |
6fd01b71 | 3684 | update_last_pte_bitmap(vcpu, context); |
6aa8b732 AK |
3685 | |
3686 | context->new_cr3 = paging_new_cr3; | |
3687 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
3688 | context->gva_to_gpa = paging32_gva_to_gpa; |
3689 | context->free = paging_free; | |
e8bc217a | 3690 | context->sync_page = paging32_sync_page; |
a7052897 | 3691 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 3692 | context->update_pte = paging32_update_pte; |
6aa8b732 | 3693 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3694 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3695 | context->direct_map = false; |
6aa8b732 AK |
3696 | return 0; |
3697 | } | |
3698 | ||
52fde8df JR |
3699 | static int paging32E_init_context(struct kvm_vcpu *vcpu, |
3700 | struct kvm_mmu *context) | |
6aa8b732 | 3701 | { |
52fde8df | 3702 | return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
3703 | } |
3704 | ||
fb72d167 JR |
3705 | static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
3706 | { | |
14dfe855 | 3707 | struct kvm_mmu *context = vcpu->arch.walk_mmu; |
fb72d167 | 3708 | |
c445f8ef | 3709 | context->base_role.word = 0; |
fb72d167 JR |
3710 | context->new_cr3 = nonpaging_new_cr3; |
3711 | context->page_fault = tdp_page_fault; | |
3712 | context->free = nonpaging_free; | |
e8bc217a | 3713 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3714 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3715 | context->update_pte = nonpaging_update_pte; |
67253af5 | 3716 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 3717 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3718 | context->direct_map = true; |
1c97f0a0 | 3719 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 3720 | context->get_cr3 = get_cr3; |
e4e517b4 | 3721 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 3722 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
3723 | |
3724 | if (!is_paging(vcpu)) { | |
2d48a985 | 3725 | context->nx = false; |
fb72d167 JR |
3726 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
3727 | context->root_level = 0; | |
3728 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3729 | context->nx = is_nx(vcpu); |
fb72d167 | 3730 | context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 DB |
3731 | reset_rsvds_bits_mask(vcpu, context); |
3732 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 3733 | } else if (is_pae(vcpu)) { |
2d48a985 | 3734 | context->nx = is_nx(vcpu); |
fb72d167 | 3735 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
3736 | reset_rsvds_bits_mask(vcpu, context); |
3737 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 3738 | } else { |
2d48a985 | 3739 | context->nx = false; |
fb72d167 | 3740 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
3741 | reset_rsvds_bits_mask(vcpu, context); |
3742 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
3743 | } |
3744 | ||
97d64b78 | 3745 | update_permission_bitmask(vcpu, context); |
6fd01b71 | 3746 | update_last_pte_bitmap(vcpu, context); |
97d64b78 | 3747 | |
fb72d167 JR |
3748 | return 0; |
3749 | } | |
3750 | ||
52fde8df | 3751 | int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context) |
6aa8b732 | 3752 | { |
a770f6f2 | 3753 | int r; |
411c588d | 3754 | bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
6aa8b732 | 3755 | ASSERT(vcpu); |
ad312c7c | 3756 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
3757 | |
3758 | if (!is_paging(vcpu)) | |
52fde8df | 3759 | r = nonpaging_init_context(vcpu, context); |
a9058ecd | 3760 | else if (is_long_mode(vcpu)) |
52fde8df | 3761 | r = paging64_init_context(vcpu, context); |
6aa8b732 | 3762 | else if (is_pae(vcpu)) |
52fde8df | 3763 | r = paging32E_init_context(vcpu, context); |
6aa8b732 | 3764 | else |
52fde8df | 3765 | r = paging32_init_context(vcpu, context); |
a770f6f2 | 3766 | |
2c9afa52 | 3767 | vcpu->arch.mmu.base_role.nxe = is_nx(vcpu); |
5b7e0102 | 3768 | vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu); |
f43addd4 | 3769 | vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu); |
411c588d AK |
3770 | vcpu->arch.mmu.base_role.smep_andnot_wp |
3771 | = smep && !is_write_protection(vcpu); | |
52fde8df JR |
3772 | |
3773 | return r; | |
3774 | } | |
3775 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
3776 | ||
3777 | static int init_kvm_softmmu(struct kvm_vcpu *vcpu) | |
3778 | { | |
14dfe855 | 3779 | int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu); |
52fde8df | 3780 | |
14dfe855 JR |
3781 | vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3; |
3782 | vcpu->arch.walk_mmu->get_cr3 = get_cr3; | |
e4e517b4 | 3783 | vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read; |
14dfe855 | 3784 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; |
a770f6f2 AK |
3785 | |
3786 | return r; | |
6aa8b732 AK |
3787 | } |
3788 | ||
02f59dc9 JR |
3789 | static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
3790 | { | |
3791 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
3792 | ||
3793 | g_context->get_cr3 = get_cr3; | |
e4e517b4 | 3794 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
3795 | g_context->inject_page_fault = kvm_inject_page_fault; |
3796 | ||
3797 | /* | |
3798 | * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The | |
3799 | * translation of l2_gpa to l1_gpa addresses is done using the | |
3800 | * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa | |
3801 | * functions between mmu and nested_mmu are swapped. | |
3802 | */ | |
3803 | if (!is_paging(vcpu)) { | |
2d48a985 | 3804 | g_context->nx = false; |
02f59dc9 JR |
3805 | g_context->root_level = 0; |
3806 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
3807 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3808 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 3809 | g_context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 | 3810 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3811 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
3812 | } else if (is_pae(vcpu)) { | |
2d48a985 | 3813 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 3814 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 3815 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3816 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
3817 | } else { | |
2d48a985 | 3818 | g_context->nx = false; |
02f59dc9 | 3819 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 3820 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3821 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
3822 | } | |
3823 | ||
97d64b78 | 3824 | update_permission_bitmask(vcpu, g_context); |
6fd01b71 | 3825 | update_last_pte_bitmap(vcpu, g_context); |
97d64b78 | 3826 | |
02f59dc9 JR |
3827 | return 0; |
3828 | } | |
3829 | ||
fb72d167 JR |
3830 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) |
3831 | { | |
02f59dc9 JR |
3832 | if (mmu_is_nested(vcpu)) |
3833 | return init_kvm_nested_mmu(vcpu); | |
3834 | else if (tdp_enabled) | |
fb72d167 JR |
3835 | return init_kvm_tdp_mmu(vcpu); |
3836 | else | |
3837 | return init_kvm_softmmu(vcpu); | |
3838 | } | |
3839 | ||
6aa8b732 AK |
3840 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) |
3841 | { | |
3842 | ASSERT(vcpu); | |
62ad0755 SY |
3843 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3844 | /* mmu.free() should set root_hpa = INVALID_PAGE */ | |
ad312c7c | 3845 | vcpu->arch.mmu.free(vcpu); |
6aa8b732 AK |
3846 | } |
3847 | ||
3848 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
3849 | { |
3850 | destroy_kvm_mmu(vcpu); | |
f8f7e5ee | 3851 | return init_kvm_mmu(vcpu); |
17c3ba9d | 3852 | } |
8668a3c4 | 3853 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
3854 | |
3855 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 3856 | { |
714b93da AK |
3857 | int r; |
3858 | ||
e2dec939 | 3859 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
3860 | if (r) |
3861 | goto out; | |
8986ecc0 | 3862 | r = mmu_alloc_roots(vcpu); |
e2858b4a | 3863 | kvm_mmu_sync_roots(vcpu); |
8986ecc0 MT |
3864 | if (r) |
3865 | goto out; | |
3662cb1c | 3866 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 3867 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
3868 | out: |
3869 | return r; | |
6aa8b732 | 3870 | } |
17c3ba9d AK |
3871 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
3872 | ||
3873 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
3874 | { | |
3875 | mmu_free_roots(vcpu); | |
3876 | } | |
4b16184c | 3877 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 3878 | |
0028425f | 3879 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
3880 | struct kvm_mmu_page *sp, u64 *spte, |
3881 | const void *new) | |
0028425f | 3882 | { |
30945387 | 3883 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
3884 | ++vcpu->kvm->stat.mmu_pde_zapped; |
3885 | return; | |
30945387 | 3886 | } |
0028425f | 3887 | |
4cee5764 | 3888 | ++vcpu->kvm->stat.mmu_pte_updated; |
7c562522 | 3889 | vcpu->arch.mmu.update_pte(vcpu, sp, spte, new); |
0028425f AK |
3890 | } |
3891 | ||
79539cec AK |
3892 | static bool need_remote_flush(u64 old, u64 new) |
3893 | { | |
3894 | if (!is_shadow_present_pte(old)) | |
3895 | return false; | |
3896 | if (!is_shadow_present_pte(new)) | |
3897 | return true; | |
3898 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
3899 | return true; | |
3900 | old ^= PT64_NX_MASK; | |
3901 | new ^= PT64_NX_MASK; | |
3902 | return (old & ~new & PT64_PERM_MASK) != 0; | |
3903 | } | |
3904 | ||
0671a8e7 XG |
3905 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
3906 | bool remote_flush, bool local_flush) | |
79539cec | 3907 | { |
0671a8e7 XG |
3908 | if (zap_page) |
3909 | return; | |
3910 | ||
3911 | if (remote_flush) | |
79539cec | 3912 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 3913 | else if (local_flush) |
79539cec AK |
3914 | kvm_mmu_flush_tlb(vcpu); |
3915 | } | |
3916 | ||
889e5cbc XG |
3917 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
3918 | const u8 *new, int *bytes) | |
da4a00f0 | 3919 | { |
889e5cbc XG |
3920 | u64 gentry; |
3921 | int r; | |
72016f3a | 3922 | |
72016f3a AK |
3923 | /* |
3924 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
3925 | * as the current vcpu paging mode since we update the sptes only |
3926 | * when they have the same mode. | |
72016f3a | 3927 | */ |
889e5cbc | 3928 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 3929 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
3930 | *gpa &= ~(gpa_t)7; |
3931 | *bytes = 8; | |
116eb3d3 | 3932 | r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, 8); |
72016f3a AK |
3933 | if (r) |
3934 | gentry = 0; | |
08e850c6 AK |
3935 | new = (const u8 *)&gentry; |
3936 | } | |
3937 | ||
889e5cbc | 3938 | switch (*bytes) { |
08e850c6 AK |
3939 | case 4: |
3940 | gentry = *(const u32 *)new; | |
3941 | break; | |
3942 | case 8: | |
3943 | gentry = *(const u64 *)new; | |
3944 | break; | |
3945 | default: | |
3946 | gentry = 0; | |
3947 | break; | |
72016f3a AK |
3948 | } |
3949 | ||
889e5cbc XG |
3950 | return gentry; |
3951 | } | |
3952 | ||
3953 | /* | |
3954 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
3955 | * or we may be forking, in which case it is better to unmap the page. | |
3956 | */ | |
a138fe75 | 3957 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 3958 | { |
a30f47cb XG |
3959 | /* |
3960 | * Skip write-flooding detected for the sp whose level is 1, because | |
3961 | * it can become unsync, then the guest page is not write-protected. | |
3962 | */ | |
f71fa31f | 3963 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) |
a30f47cb | 3964 | return false; |
3246af0e | 3965 | |
a30f47cb | 3966 | return ++sp->write_flooding_count >= 3; |
889e5cbc XG |
3967 | } |
3968 | ||
3969 | /* | |
3970 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
3971 | * indicate a page is not used as a page table. | |
3972 | */ | |
3973 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
3974 | int bytes) | |
3975 | { | |
3976 | unsigned offset, pte_size, misaligned; | |
3977 | ||
3978 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
3979 | gpa, bytes, sp->role.word); | |
3980 | ||
3981 | offset = offset_in_page(gpa); | |
3982 | pte_size = sp->role.cr4_pae ? 8 : 4; | |
5d9ca30e XG |
3983 | |
3984 | /* | |
3985 | * Sometimes, the OS only writes the last one bytes to update status | |
3986 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
3987 | */ | |
3988 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
3989 | return false; | |
3990 | ||
889e5cbc XG |
3991 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
3992 | misaligned |= bytes < 4; | |
3993 | ||
3994 | return misaligned; | |
3995 | } | |
3996 | ||
3997 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
3998 | { | |
3999 | unsigned page_offset, quadrant; | |
4000 | u64 *spte; | |
4001 | int level; | |
4002 | ||
4003 | page_offset = offset_in_page(gpa); | |
4004 | level = sp->role.level; | |
4005 | *nspte = 1; | |
4006 | if (!sp->role.cr4_pae) { | |
4007 | page_offset <<= 1; /* 32->64 */ | |
4008 | /* | |
4009 | * A 32-bit pde maps 4MB while the shadow pdes map | |
4010 | * only 2MB. So we need to double the offset again | |
4011 | * and zap two pdes instead of one. | |
4012 | */ | |
4013 | if (level == PT32_ROOT_LEVEL) { | |
4014 | page_offset &= ~7; /* kill rounding error */ | |
4015 | page_offset <<= 1; | |
4016 | *nspte = 2; | |
4017 | } | |
4018 | quadrant = page_offset >> PAGE_SHIFT; | |
4019 | page_offset &= ~PAGE_MASK; | |
4020 | if (quadrant != sp->role.quadrant) | |
4021 | return NULL; | |
4022 | } | |
4023 | ||
4024 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
4025 | return spte; | |
4026 | } | |
4027 | ||
4028 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4029 | const u8 *new, int bytes) | |
4030 | { | |
4031 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
4032 | union kvm_mmu_page_role mask = { .word = 0 }; | |
4033 | struct kvm_mmu_page *sp; | |
889e5cbc XG |
4034 | LIST_HEAD(invalid_list); |
4035 | u64 entry, gentry, *spte; | |
4036 | int npte; | |
a30f47cb | 4037 | bool remote_flush, local_flush, zap_page; |
889e5cbc XG |
4038 | |
4039 | /* | |
4040 | * If we don't have indirect shadow pages, it means no page is | |
4041 | * write-protected, so we can exit simply. | |
4042 | */ | |
4043 | if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) | |
4044 | return; | |
4045 | ||
4046 | zap_page = remote_flush = local_flush = false; | |
4047 | ||
4048 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
4049 | ||
4050 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes); | |
4051 | ||
4052 | /* | |
4053 | * No need to care whether allocation memory is successful | |
4054 | * or not since pte prefetch is skiped if it does not have | |
4055 | * enough objects in the cache. | |
4056 | */ | |
4057 | mmu_topup_memory_caches(vcpu); | |
4058 | ||
4059 | spin_lock(&vcpu->kvm->mmu_lock); | |
4060 | ++vcpu->kvm->stat.mmu_pte_write; | |
0375f7fa | 4061 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 4062 | |
fa1de2bf | 4063 | mask.cr0_wp = mask.cr4_pae = mask.nxe = 1; |
b67bfe0d | 4064 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 4065 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 4066 | detect_write_flooding(sp)) { |
0671a8e7 | 4067 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 4068 | &invalid_list); |
4cee5764 | 4069 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
4070 | continue; |
4071 | } | |
889e5cbc XG |
4072 | |
4073 | spte = get_written_sptes(sp, gpa, &npte); | |
4074 | if (!spte) | |
4075 | continue; | |
4076 | ||
0671a8e7 | 4077 | local_flush = true; |
ac1b714e | 4078 | while (npte--) { |
79539cec | 4079 | entry = *spte; |
38e3b2b2 | 4080 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf XG |
4081 | if (gentry && |
4082 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
f759e2b4 | 4083 | & mask.word) && rmap_can_add(vcpu)) |
7c562522 | 4084 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
9bb4f6b1 | 4085 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 4086 | remote_flush = true; |
ac1b714e | 4087 | ++spte; |
9b7a0325 | 4088 | } |
9b7a0325 | 4089 | } |
0671a8e7 | 4090 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 4091 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
0375f7fa | 4092 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 4093 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
4094 | } |
4095 | ||
a436036b AK |
4096 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
4097 | { | |
10589a46 MT |
4098 | gpa_t gpa; |
4099 | int r; | |
a436036b | 4100 | |
c5a78f2b | 4101 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
4102 | return 0; |
4103 | ||
1871c602 | 4104 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 4105 | |
10589a46 | 4106 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 4107 | |
10589a46 | 4108 | return r; |
a436036b | 4109 | } |
577bdc49 | 4110 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 4111 | |
81f4f76b | 4112 | static void make_mmu_pages_available(struct kvm_vcpu *vcpu) |
ebeace86 | 4113 | { |
d98ba053 | 4114 | LIST_HEAD(invalid_list); |
103ad25a | 4115 | |
81f4f76b TY |
4116 | if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES)) |
4117 | return; | |
4118 | ||
5da59607 TY |
4119 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) { |
4120 | if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list)) | |
4121 | break; | |
ebeace86 | 4122 | |
4cee5764 | 4123 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 4124 | } |
aa6bd187 | 4125 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
ebeace86 | 4126 | } |
ebeace86 | 4127 | |
1cb3f3ae XG |
4128 | static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr) |
4129 | { | |
4130 | if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu)) | |
4131 | return vcpu_match_mmio_gpa(vcpu, addr); | |
4132 | ||
4133 | return vcpu_match_mmio_gva(vcpu, addr); | |
4134 | } | |
4135 | ||
dc25e89e AP |
4136 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code, |
4137 | void *insn, int insn_len) | |
3067714c | 4138 | { |
1cb3f3ae | 4139 | int r, emulation_type = EMULTYPE_RETRY; |
3067714c AK |
4140 | enum emulation_result er; |
4141 | ||
56028d08 | 4142 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false); |
3067714c AK |
4143 | if (r < 0) |
4144 | goto out; | |
4145 | ||
4146 | if (!r) { | |
4147 | r = 1; | |
4148 | goto out; | |
4149 | } | |
4150 | ||
1cb3f3ae XG |
4151 | if (is_mmio_page_fault(vcpu, cr2)) |
4152 | emulation_type = 0; | |
4153 | ||
4154 | er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len); | |
3067714c AK |
4155 | |
4156 | switch (er) { | |
4157 | case EMULATE_DONE: | |
4158 | return 1; | |
4159 | case EMULATE_DO_MMIO: | |
4160 | ++vcpu->stat.mmio_exits; | |
6d77dbfc | 4161 | /* fall through */ |
3067714c | 4162 | case EMULATE_FAIL: |
3f5d18a9 | 4163 | return 0; |
3067714c AK |
4164 | default: |
4165 | BUG(); | |
4166 | } | |
4167 | out: | |
3067714c AK |
4168 | return r; |
4169 | } | |
4170 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
4171 | ||
a7052897 MT |
4172 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
4173 | { | |
a7052897 | 4174 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
4175 | kvm_mmu_flush_tlb(vcpu); |
4176 | ++vcpu->stat.invlpg; | |
4177 | } | |
4178 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
4179 | ||
18552672 JR |
4180 | void kvm_enable_tdp(void) |
4181 | { | |
4182 | tdp_enabled = true; | |
4183 | } | |
4184 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
4185 | ||
5f4cb662 JR |
4186 | void kvm_disable_tdp(void) |
4187 | { | |
4188 | tdp_enabled = false; | |
4189 | } | |
4190 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
4191 | ||
6aa8b732 AK |
4192 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
4193 | { | |
ad312c7c | 4194 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
81407ca5 JR |
4195 | if (vcpu->arch.mmu.lm_root != NULL) |
4196 | free_page((unsigned long)vcpu->arch.mmu.lm_root); | |
6aa8b732 AK |
4197 | } |
4198 | ||
4199 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
4200 | { | |
17ac10ad | 4201 | struct page *page; |
6aa8b732 AK |
4202 | int i; |
4203 | ||
4204 | ASSERT(vcpu); | |
4205 | ||
17ac10ad AK |
4206 | /* |
4207 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
4208 | * Therefore we need to allocate shadow page tables in the first | |
4209 | * 4GB of memory, which happens to fit the DMA32 zone. | |
4210 | */ | |
4211 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
4212 | if (!page) | |
d7fa6ab2 WY |
4213 | return -ENOMEM; |
4214 | ||
ad312c7c | 4215 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 4216 | for (i = 0; i < 4; ++i) |
ad312c7c | 4217 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 4218 | |
6aa8b732 | 4219 | return 0; |
6aa8b732 AK |
4220 | } |
4221 | ||
8018c27b | 4222 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 4223 | { |
6aa8b732 | 4224 | ASSERT(vcpu); |
e459e322 XG |
4225 | |
4226 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
4227 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; | |
4228 | vcpu->arch.mmu.translate_gpa = translate_gpa; | |
4229 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; | |
6aa8b732 | 4230 | |
8018c27b IM |
4231 | return alloc_mmu_pages(vcpu); |
4232 | } | |
6aa8b732 | 4233 | |
8018c27b IM |
4234 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
4235 | { | |
4236 | ASSERT(vcpu); | |
ad312c7c | 4237 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 4238 | |
8018c27b | 4239 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
4240 | } |
4241 | ||
90cb0529 | 4242 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 4243 | { |
b99db1d3 TY |
4244 | struct kvm_memory_slot *memslot; |
4245 | gfn_t last_gfn; | |
4246 | int i; | |
6aa8b732 | 4247 | |
b99db1d3 TY |
4248 | memslot = id_to_memslot(kvm->memslots, slot); |
4249 | last_gfn = memslot->base_gfn + memslot->npages - 1; | |
6aa8b732 | 4250 | |
9d1beefb TY |
4251 | spin_lock(&kvm->mmu_lock); |
4252 | ||
b99db1d3 TY |
4253 | for (i = PT_PAGE_TABLE_LEVEL; |
4254 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
4255 | unsigned long *rmapp; | |
4256 | unsigned long last_index, index; | |
6aa8b732 | 4257 | |
b99db1d3 TY |
4258 | rmapp = memslot->arch.rmap[i - PT_PAGE_TABLE_LEVEL]; |
4259 | last_index = gfn_to_index(last_gfn, memslot->base_gfn, i); | |
da8dc75f | 4260 | |
b99db1d3 TY |
4261 | for (index = 0; index <= last_index; ++index, ++rmapp) { |
4262 | if (*rmapp) | |
4263 | __rmap_write_protect(kvm, rmapp, false); | |
6b81b05e TY |
4264 | |
4265 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { | |
4266 | kvm_flush_remote_tlbs(kvm); | |
4267 | cond_resched_lock(&kvm->mmu_lock); | |
4268 | } | |
8234b22e | 4269 | } |
6aa8b732 | 4270 | } |
b99db1d3 | 4271 | |
171d595d | 4272 | kvm_flush_remote_tlbs(kvm); |
9d1beefb | 4273 | spin_unlock(&kvm->mmu_lock); |
6aa8b732 | 4274 | } |
37a7d8b0 | 4275 | |
e7d11c7a | 4276 | #define BATCH_ZAP_PAGES 10 |
5304b8d3 XG |
4277 | static void kvm_zap_obsolete_pages(struct kvm *kvm) |
4278 | { | |
4279 | struct kvm_mmu_page *sp, *node; | |
e7d11c7a | 4280 | int batch = 0; |
5304b8d3 XG |
4281 | |
4282 | restart: | |
4283 | list_for_each_entry_safe_reverse(sp, node, | |
4284 | &kvm->arch.active_mmu_pages, link) { | |
e7d11c7a XG |
4285 | int ret; |
4286 | ||
5304b8d3 XG |
4287 | /* |
4288 | * No obsolete page exists before new created page since | |
4289 | * active_mmu_pages is the FIFO list. | |
4290 | */ | |
4291 | if (!is_obsolete_sp(kvm, sp)) | |
4292 | break; | |
4293 | ||
4294 | /* | |
5304b8d3 XG |
4295 | * Since we are reversely walking the list and the invalid |
4296 | * list will be moved to the head, skip the invalid page | |
4297 | * can help us to avoid the infinity list walking. | |
4298 | */ | |
4299 | if (sp->role.invalid) | |
4300 | continue; | |
4301 | ||
f34d251d XG |
4302 | /* |
4303 | * Need not flush tlb since we only zap the sp with invalid | |
4304 | * generation number. | |
4305 | */ | |
e7d11c7a | 4306 | if (batch >= BATCH_ZAP_PAGES && |
f34d251d | 4307 | cond_resched_lock(&kvm->mmu_lock)) { |
e7d11c7a | 4308 | batch = 0; |
5304b8d3 XG |
4309 | goto restart; |
4310 | } | |
4311 | ||
365c8868 XG |
4312 | ret = kvm_mmu_prepare_zap_page(kvm, sp, |
4313 | &kvm->arch.zapped_obsolete_pages); | |
e7d11c7a XG |
4314 | batch += ret; |
4315 | ||
4316 | if (ret) | |
5304b8d3 XG |
4317 | goto restart; |
4318 | } | |
4319 | ||
f34d251d XG |
4320 | /* |
4321 | * Should flush tlb before free page tables since lockless-walking | |
4322 | * may use the pages. | |
4323 | */ | |
365c8868 | 4324 | kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages); |
5304b8d3 XG |
4325 | } |
4326 | ||
4327 | /* | |
4328 | * Fast invalidate all shadow pages and use lock-break technique | |
4329 | * to zap obsolete pages. | |
4330 | * | |
4331 | * It's required when memslot is being deleted or VM is being | |
4332 | * destroyed, in these cases, we should ensure that KVM MMU does | |
4333 | * not use any resource of the being-deleted slot or all slots | |
4334 | * after calling the function. | |
4335 | */ | |
4336 | void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm) | |
4337 | { | |
4338 | spin_lock(&kvm->mmu_lock); | |
35006126 | 4339 | trace_kvm_mmu_invalidate_zap_all_pages(kvm); |
5304b8d3 XG |
4340 | kvm->arch.mmu_valid_gen++; |
4341 | ||
f34d251d XG |
4342 | /* |
4343 | * Notify all vcpus to reload its shadow page table | |
4344 | * and flush TLB. Then all vcpus will switch to new | |
4345 | * shadow page table with the new mmu_valid_gen. | |
4346 | * | |
4347 | * Note: we should do this under the protection of | |
4348 | * mmu-lock, otherwise, vcpu would purge shadow page | |
4349 | * but miss tlb flush. | |
4350 | */ | |
4351 | kvm_reload_remote_mmus(kvm); | |
4352 | ||
5304b8d3 XG |
4353 | kvm_zap_obsolete_pages(kvm); |
4354 | spin_unlock(&kvm->mmu_lock); | |
4355 | } | |
4356 | ||
f8f55942 | 4357 | static void kvm_mmu_zap_mmio_sptes(struct kvm *kvm) |
982b3394 TY |
4358 | { |
4359 | struct kvm_mmu_page *sp, *node; | |
4360 | LIST_HEAD(invalid_list); | |
4361 | ||
4362 | spin_lock(&kvm->mmu_lock); | |
4363 | restart: | |
4364 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) { | |
4365 | if (!sp->mmio_cached) | |
4366 | continue; | |
4367 | if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list)) | |
4368 | goto restart; | |
4369 | } | |
4370 | ||
4371 | kvm_mmu_commit_zap_page(kvm, &invalid_list); | |
4372 | spin_unlock(&kvm->mmu_lock); | |
4373 | } | |
4374 | ||
365c8868 XG |
4375 | static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm) |
4376 | { | |
4377 | return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages)); | |
4378 | } | |
4379 | ||
f8f55942 XG |
4380 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm) |
4381 | { | |
4382 | /* | |
4383 | * The very rare case: if the generation-number is round, | |
4384 | * zap all shadow pages. | |
4385 | * | |
4386 | * The max value is MMIO_MAX_GEN - 1 since it is not called | |
4387 | * when mark memslot invalid. | |
4388 | */ | |
4389 | if (unlikely(kvm_current_mmio_generation(kvm) >= (MMIO_MAX_GEN - 1))) | |
4390 | kvm_mmu_zap_mmio_sptes(kvm); | |
4391 | } | |
4392 | ||
1495f230 | 4393 | static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc) |
3ee16c81 IE |
4394 | { |
4395 | struct kvm *kvm; | |
1495f230 | 4396 | int nr_to_scan = sc->nr_to_scan; |
45221ab6 DH |
4397 | |
4398 | if (nr_to_scan == 0) | |
4399 | goto out; | |
3ee16c81 | 4400 | |
e935b837 | 4401 | raw_spin_lock(&kvm_lock); |
3ee16c81 IE |
4402 | |
4403 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 4404 | int idx; |
d98ba053 | 4405 | LIST_HEAD(invalid_list); |
3ee16c81 | 4406 | |
35f2d16b TY |
4407 | /* |
4408 | * Never scan more than sc->nr_to_scan VM instances. | |
4409 | * Will not hit this condition practically since we do not try | |
4410 | * to shrink more than one VM and it is very unlikely to see | |
4411 | * !n_used_mmu_pages so many times. | |
4412 | */ | |
4413 | if (!nr_to_scan--) | |
4414 | break; | |
19526396 GN |
4415 | /* |
4416 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
4417 | * here. We may skip a VM instance errorneosly, but we do not | |
4418 | * want to shrink a VM that only started to populate its MMU | |
4419 | * anyway. | |
4420 | */ | |
365c8868 XG |
4421 | if (!kvm->arch.n_used_mmu_pages && |
4422 | !kvm_has_zapped_obsolete_pages(kvm)) | |
19526396 | 4423 | continue; |
19526396 | 4424 | |
f656ce01 | 4425 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 4426 | spin_lock(&kvm->mmu_lock); |
3ee16c81 | 4427 | |
365c8868 XG |
4428 | if (kvm_has_zapped_obsolete_pages(kvm)) { |
4429 | kvm_mmu_commit_zap_page(kvm, | |
4430 | &kvm->arch.zapped_obsolete_pages); | |
4431 | goto unlock; | |
4432 | } | |
4433 | ||
5da59607 | 4434 | prepare_zap_oldest_mmu_page(kvm, &invalid_list); |
d98ba053 | 4435 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
19526396 | 4436 | |
365c8868 | 4437 | unlock: |
3ee16c81 | 4438 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 4439 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 GN |
4440 | |
4441 | list_move_tail(&kvm->vm_list, &vm_list); | |
4442 | break; | |
3ee16c81 | 4443 | } |
3ee16c81 | 4444 | |
e935b837 | 4445 | raw_spin_unlock(&kvm_lock); |
3ee16c81 | 4446 | |
45221ab6 DH |
4447 | out: |
4448 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); | |
3ee16c81 IE |
4449 | } |
4450 | ||
4451 | static struct shrinker mmu_shrinker = { | |
4452 | .shrink = mmu_shrink, | |
4453 | .seeks = DEFAULT_SEEKS * 10, | |
4454 | }; | |
4455 | ||
2ddfd20e | 4456 | static void mmu_destroy_caches(void) |
b5a33a75 | 4457 | { |
53c07b18 XG |
4458 | if (pte_list_desc_cache) |
4459 | kmem_cache_destroy(pte_list_desc_cache); | |
d3d25b04 AK |
4460 | if (mmu_page_header_cache) |
4461 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
4462 | } |
4463 | ||
4464 | int kvm_mmu_module_init(void) | |
4465 | { | |
53c07b18 XG |
4466 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
4467 | sizeof(struct pte_list_desc), | |
20c2df83 | 4468 | 0, 0, NULL); |
53c07b18 | 4469 | if (!pte_list_desc_cache) |
b5a33a75 AK |
4470 | goto nomem; |
4471 | ||
d3d25b04 AK |
4472 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
4473 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 4474 | 0, 0, NULL); |
d3d25b04 AK |
4475 | if (!mmu_page_header_cache) |
4476 | goto nomem; | |
4477 | ||
45bf21a8 WY |
4478 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0)) |
4479 | goto nomem; | |
4480 | ||
3ee16c81 IE |
4481 | register_shrinker(&mmu_shrinker); |
4482 | ||
b5a33a75 AK |
4483 | return 0; |
4484 | ||
4485 | nomem: | |
3ee16c81 | 4486 | mmu_destroy_caches(); |
b5a33a75 AK |
4487 | return -ENOMEM; |
4488 | } | |
4489 | ||
3ad82a7e ZX |
4490 | /* |
4491 | * Caculate mmu pages needed for kvm. | |
4492 | */ | |
4493 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
4494 | { | |
3ad82a7e ZX |
4495 | unsigned int nr_mmu_pages; |
4496 | unsigned int nr_pages = 0; | |
bc6678a3 | 4497 | struct kvm_memslots *slots; |
be6ba0f0 | 4498 | struct kvm_memory_slot *memslot; |
3ad82a7e | 4499 | |
90d83dc3 LJ |
4500 | slots = kvm_memslots(kvm); |
4501 | ||
be6ba0f0 XG |
4502 | kvm_for_each_memslot(memslot, slots) |
4503 | nr_pages += memslot->npages; | |
3ad82a7e ZX |
4504 | |
4505 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
4506 | nr_mmu_pages = max(nr_mmu_pages, | |
4507 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
4508 | ||
4509 | return nr_mmu_pages; | |
4510 | } | |
4511 | ||
94d8b056 MT |
4512 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
4513 | { | |
4514 | struct kvm_shadow_walk_iterator iterator; | |
c2a2ac2b | 4515 | u64 spte; |
94d8b056 MT |
4516 | int nr_sptes = 0; |
4517 | ||
c2a2ac2b XG |
4518 | walk_shadow_page_lockless_begin(vcpu); |
4519 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
4520 | sptes[iterator.level-1] = spte; | |
94d8b056 | 4521 | nr_sptes++; |
c2a2ac2b | 4522 | if (!is_shadow_present_pte(spte)) |
94d8b056 MT |
4523 | break; |
4524 | } | |
c2a2ac2b | 4525 | walk_shadow_page_lockless_end(vcpu); |
94d8b056 MT |
4526 | |
4527 | return nr_sptes; | |
4528 | } | |
4529 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
4530 | ||
c42fffe3 XG |
4531 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
4532 | { | |
4533 | ASSERT(vcpu); | |
4534 | ||
4535 | destroy_kvm_mmu(vcpu); | |
4536 | free_mmu_pages(vcpu); | |
4537 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
4538 | } |
4539 | ||
b034cf01 XG |
4540 | void kvm_mmu_module_exit(void) |
4541 | { | |
4542 | mmu_destroy_caches(); | |
4543 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
4544 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
4545 | mmu_audit_disable(); |
4546 | } |