Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
e495606d | 25 | |
edf88417 | 26 | #include <linux/kvm_host.h> |
6aa8b732 AK |
27 | #include <linux/types.h> |
28 | #include <linux/string.h> | |
6aa8b732 AK |
29 | #include <linux/mm.h> |
30 | #include <linux/highmem.h> | |
31 | #include <linux/module.h> | |
448353ca | 32 | #include <linux/swap.h> |
05da4558 | 33 | #include <linux/hugetlb.h> |
2f333bcb | 34 | #include <linux/compiler.h> |
bc6678a3 | 35 | #include <linux/srcu.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
bf998156 | 37 | #include <linux/uaccess.h> |
6aa8b732 | 38 | |
e495606d AK |
39 | #include <asm/page.h> |
40 | #include <asm/cmpxchg.h> | |
4e542370 | 41 | #include <asm/io.h> |
13673a90 | 42 | #include <asm/vmx.h> |
6aa8b732 | 43 | |
18552672 JR |
44 | /* |
45 | * When setting this variable to true it enables Two-Dimensional-Paging | |
46 | * where the hardware walks 2 page tables: | |
47 | * 1. the guest-virtual to guest-physical | |
48 | * 2. while doing 1. it walks guest-physical to host-physical | |
49 | * If the hardware supports that we don't need to do shadow paging. | |
50 | */ | |
2f333bcb | 51 | bool tdp_enabled = false; |
18552672 | 52 | |
8b1fe17c XG |
53 | enum { |
54 | AUDIT_PRE_PAGE_FAULT, | |
55 | AUDIT_POST_PAGE_FAULT, | |
56 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
57 | AUDIT_POST_PTE_WRITE, |
58 | AUDIT_PRE_SYNC, | |
59 | AUDIT_POST_SYNC | |
8b1fe17c | 60 | }; |
37a7d8b0 | 61 | |
8b1fe17c | 62 | #undef MMU_DEBUG |
37a7d8b0 AK |
63 | |
64 | #ifdef MMU_DEBUG | |
65 | ||
66 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
67 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
68 | ||
69 | #else | |
70 | ||
71 | #define pgprintk(x...) do { } while (0) | |
72 | #define rmap_printk(x...) do { } while (0) | |
73 | ||
74 | #endif | |
75 | ||
8b1fe17c | 76 | #ifdef MMU_DEBUG |
476bc001 | 77 | static bool dbg = 0; |
6ada8cca | 78 | module_param(dbg, bool, 0644); |
37a7d8b0 | 79 | #endif |
6aa8b732 | 80 | |
d6c69ee9 YD |
81 | #ifndef MMU_DEBUG |
82 | #define ASSERT(x) do { } while (0) | |
83 | #else | |
6aa8b732 AK |
84 | #define ASSERT(x) \ |
85 | if (!(x)) { \ | |
86 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
87 | __FILE__, __LINE__, #x); \ | |
88 | } | |
d6c69ee9 | 89 | #endif |
6aa8b732 | 90 | |
957ed9ef XG |
91 | #define PTE_PREFETCH_NUM 8 |
92 | ||
00763e41 | 93 | #define PT_FIRST_AVAIL_BITS_SHIFT 10 |
6aa8b732 AK |
94 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 |
95 | ||
6aa8b732 AK |
96 | #define PT64_LEVEL_BITS 9 |
97 | ||
98 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 99 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 100 | |
6aa8b732 AK |
101 | #define PT64_INDEX(address, level)\ |
102 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
103 | ||
104 | ||
105 | #define PT32_LEVEL_BITS 10 | |
106 | ||
107 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 108 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 109 | |
e04da980 JR |
110 | #define PT32_LVL_OFFSET_MASK(level) \ |
111 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
112 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
113 | |
114 | #define PT32_INDEX(address, level)\ | |
115 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
116 | ||
117 | ||
27aba766 | 118 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
119 | #define PT64_DIR_BASE_ADDR_MASK \ |
120 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
121 | #define PT64_LVL_ADDR_MASK(level) \ |
122 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
123 | * PT64_LEVEL_BITS))) - 1)) | |
124 | #define PT64_LVL_OFFSET_MASK(level) \ | |
125 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
126 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
127 | |
128 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
129 | #define PT32_DIR_BASE_ADDR_MASK \ | |
130 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
131 | #define PT32_LVL_ADDR_MASK(level) \ |
132 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
133 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 134 | |
79539cec AK |
135 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
136 | | PT64_NX_MASK) | |
6aa8b732 | 137 | |
fe135d2c AK |
138 | #define ACC_EXEC_MASK 1 |
139 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
140 | #define ACC_USER_MASK PT_USER_MASK | |
141 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
142 | ||
90bb6fc5 AK |
143 | #include <trace/events/kvm.h> |
144 | ||
07420171 AK |
145 | #define CREATE_TRACE_POINTS |
146 | #include "mmutrace.h" | |
147 | ||
49fde340 XG |
148 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
149 | #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1)) | |
1403283a | 150 | |
135f8c2b AK |
151 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
152 | ||
220f773a TY |
153 | /* make pte_list_desc fit well in cache line */ |
154 | #define PTE_LIST_EXT 3 | |
155 | ||
53c07b18 XG |
156 | struct pte_list_desc { |
157 | u64 *sptes[PTE_LIST_EXT]; | |
158 | struct pte_list_desc *more; | |
cd4a4e53 AK |
159 | }; |
160 | ||
2d11123a AK |
161 | struct kvm_shadow_walk_iterator { |
162 | u64 addr; | |
163 | hpa_t shadow_addr; | |
2d11123a | 164 | u64 *sptep; |
dd3bfd59 | 165 | int level; |
2d11123a AK |
166 | unsigned index; |
167 | }; | |
168 | ||
169 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
170 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
171 | shadow_walk_okay(&(_walker)); \ | |
172 | shadow_walk_next(&(_walker))) | |
173 | ||
c2a2ac2b XG |
174 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
175 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
176 | shadow_walk_okay(&(_walker)) && \ | |
177 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
178 | __shadow_walk_next(&(_walker), spte)) | |
179 | ||
53c07b18 | 180 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 181 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 182 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 183 | |
7b52345e SY |
184 | static u64 __read_mostly shadow_nx_mask; |
185 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
186 | static u64 __read_mostly shadow_user_mask; | |
187 | static u64 __read_mostly shadow_accessed_mask; | |
188 | static u64 __read_mostly shadow_dirty_mask; | |
ce88decf XG |
189 | static u64 __read_mostly shadow_mmio_mask; |
190 | ||
191 | static void mmu_spte_set(u64 *sptep, u64 spte); | |
e676505a | 192 | static void mmu_free_roots(struct kvm_vcpu *vcpu); |
ce88decf XG |
193 | |
194 | void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask) | |
195 | { | |
196 | shadow_mmio_mask = mmio_mask; | |
197 | } | |
198 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); | |
199 | ||
f2fd125d XG |
200 | /* |
201 | * spte bits of bit 3 ~ bit 11 are used as low 9 bits of generation number, | |
202 | * the bits of bits 52 ~ bit 61 are used as high 10 bits of generation | |
203 | * number. | |
204 | */ | |
205 | #define MMIO_SPTE_GEN_LOW_SHIFT 3 | |
206 | #define MMIO_SPTE_GEN_HIGH_SHIFT 52 | |
207 | ||
208 | #define MMIO_GEN_LOW_SHIFT 9 | |
209 | #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 1) | |
210 | #define MMIO_MAX_GEN ((1 << 19) - 1) | |
211 | ||
212 | static u64 generation_mmio_spte_mask(unsigned int gen) | |
213 | { | |
214 | u64 mask; | |
215 | ||
216 | WARN_ON(gen > MMIO_MAX_GEN); | |
217 | ||
218 | mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT; | |
219 | mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT; | |
220 | return mask; | |
221 | } | |
222 | ||
223 | static unsigned int get_mmio_spte_generation(u64 spte) | |
224 | { | |
225 | unsigned int gen; | |
226 | ||
227 | spte &= ~shadow_mmio_mask; | |
228 | ||
229 | gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK; | |
230 | gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT; | |
231 | return gen; | |
232 | } | |
233 | ||
234 | static void mark_mmio_spte(struct kvm *kvm, u64 *sptep, u64 gfn, | |
235 | unsigned access) | |
ce88decf | 236 | { |
95b0430d | 237 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); |
f2fd125d | 238 | u64 mask = generation_mmio_spte_mask(0); |
95b0430d | 239 | |
ce88decf | 240 | access &= ACC_WRITE_MASK | ACC_USER_MASK; |
f2fd125d | 241 | mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT; |
95b0430d | 242 | sp->mmio_cached = true; |
f2fd125d XG |
243 | |
244 | trace_mark_mmio_spte(sptep, gfn, access, 0); | |
245 | mmu_spte_set(sptep, mask); | |
ce88decf XG |
246 | } |
247 | ||
248 | static bool is_mmio_spte(u64 spte) | |
249 | { | |
250 | return (spte & shadow_mmio_mask) == shadow_mmio_mask; | |
251 | } | |
252 | ||
253 | static gfn_t get_mmio_spte_gfn(u64 spte) | |
254 | { | |
f2fd125d XG |
255 | u64 mask = generation_mmio_spte_mask(MMIO_MAX_GEN) | shadow_mmio_mask; |
256 | return (spte & ~mask) >> PAGE_SHIFT; | |
ce88decf XG |
257 | } |
258 | ||
259 | static unsigned get_mmio_spte_access(u64 spte) | |
260 | { | |
f2fd125d XG |
261 | u64 mask = generation_mmio_spte_mask(MMIO_MAX_GEN) | shadow_mmio_mask; |
262 | return (spte & ~mask) & ~PAGE_MASK; | |
ce88decf XG |
263 | } |
264 | ||
f2fd125d XG |
265 | static bool set_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn, |
266 | pfn_t pfn, unsigned access) | |
ce88decf XG |
267 | { |
268 | if (unlikely(is_noslot_pfn(pfn))) { | |
f2fd125d | 269 | mark_mmio_spte(kvm, sptep, gfn, access); |
ce88decf XG |
270 | return true; |
271 | } | |
272 | ||
273 | return false; | |
274 | } | |
c7addb90 | 275 | |
82725b20 DE |
276 | static inline u64 rsvd_bits(int s, int e) |
277 | { | |
278 | return ((1ULL << (e - s + 1)) - 1) << s; | |
279 | } | |
280 | ||
7b52345e | 281 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 282 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
283 | { |
284 | shadow_user_mask = user_mask; | |
285 | shadow_accessed_mask = accessed_mask; | |
286 | shadow_dirty_mask = dirty_mask; | |
287 | shadow_nx_mask = nx_mask; | |
288 | shadow_x_mask = x_mask; | |
289 | } | |
290 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
291 | ||
6aa8b732 AK |
292 | static int is_cpuid_PSE36(void) |
293 | { | |
294 | return 1; | |
295 | } | |
296 | ||
73b1087e AK |
297 | static int is_nx(struct kvm_vcpu *vcpu) |
298 | { | |
f6801dff | 299 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
300 | } |
301 | ||
c7addb90 AK |
302 | static int is_shadow_present_pte(u64 pte) |
303 | { | |
ce88decf | 304 | return pte & PT_PRESENT_MASK && !is_mmio_spte(pte); |
c7addb90 AK |
305 | } |
306 | ||
05da4558 MT |
307 | static int is_large_pte(u64 pte) |
308 | { | |
309 | return pte & PT_PAGE_SIZE_MASK; | |
310 | } | |
311 | ||
43a3795a | 312 | static int is_dirty_gpte(unsigned long pte) |
e3c5e7ec | 313 | { |
439e218a | 314 | return pte & PT_DIRTY_MASK; |
e3c5e7ec AK |
315 | } |
316 | ||
43a3795a | 317 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 318 | { |
4b1a80fa | 319 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
320 | } |
321 | ||
776e6633 MT |
322 | static int is_last_spte(u64 pte, int level) |
323 | { | |
324 | if (level == PT_PAGE_TABLE_LEVEL) | |
325 | return 1; | |
852e3c19 | 326 | if (is_large_pte(pte)) |
776e6633 MT |
327 | return 1; |
328 | return 0; | |
329 | } | |
330 | ||
35149e21 | 331 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 332 | { |
35149e21 | 333 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
334 | } |
335 | ||
da928521 AK |
336 | static gfn_t pse36_gfn_delta(u32 gpte) |
337 | { | |
338 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
339 | ||
340 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
341 | } | |
342 | ||
603e0651 | 343 | #ifdef CONFIG_X86_64 |
d555c333 | 344 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 345 | { |
603e0651 | 346 | *sptep = spte; |
e663ee64 AK |
347 | } |
348 | ||
603e0651 | 349 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 350 | { |
603e0651 XG |
351 | *sptep = spte; |
352 | } | |
353 | ||
354 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
355 | { | |
356 | return xchg(sptep, spte); | |
357 | } | |
c2a2ac2b XG |
358 | |
359 | static u64 __get_spte_lockless(u64 *sptep) | |
360 | { | |
361 | return ACCESS_ONCE(*sptep); | |
362 | } | |
ce88decf XG |
363 | |
364 | static bool __check_direct_spte_mmio_pf(u64 spte) | |
365 | { | |
366 | /* It is valid if the spte is zapped. */ | |
367 | return spte == 0ull; | |
368 | } | |
a9221dd5 | 369 | #else |
603e0651 XG |
370 | union split_spte { |
371 | struct { | |
372 | u32 spte_low; | |
373 | u32 spte_high; | |
374 | }; | |
375 | u64 spte; | |
376 | }; | |
a9221dd5 | 377 | |
c2a2ac2b XG |
378 | static void count_spte_clear(u64 *sptep, u64 spte) |
379 | { | |
380 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
381 | ||
382 | if (is_shadow_present_pte(spte)) | |
383 | return; | |
384 | ||
385 | /* Ensure the spte is completely set before we increase the count */ | |
386 | smp_wmb(); | |
387 | sp->clear_spte_count++; | |
388 | } | |
389 | ||
603e0651 XG |
390 | static void __set_spte(u64 *sptep, u64 spte) |
391 | { | |
392 | union split_spte *ssptep, sspte; | |
a9221dd5 | 393 | |
603e0651 XG |
394 | ssptep = (union split_spte *)sptep; |
395 | sspte = (union split_spte)spte; | |
396 | ||
397 | ssptep->spte_high = sspte.spte_high; | |
398 | ||
399 | /* | |
400 | * If we map the spte from nonpresent to present, We should store | |
401 | * the high bits firstly, then set present bit, so cpu can not | |
402 | * fetch this spte while we are setting the spte. | |
403 | */ | |
404 | smp_wmb(); | |
405 | ||
406 | ssptep->spte_low = sspte.spte_low; | |
a9221dd5 AK |
407 | } |
408 | ||
603e0651 XG |
409 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
410 | { | |
411 | union split_spte *ssptep, sspte; | |
412 | ||
413 | ssptep = (union split_spte *)sptep; | |
414 | sspte = (union split_spte)spte; | |
415 | ||
416 | ssptep->spte_low = sspte.spte_low; | |
417 | ||
418 | /* | |
419 | * If we map the spte from present to nonpresent, we should clear | |
420 | * present bit firstly to avoid vcpu fetch the old high bits. | |
421 | */ | |
422 | smp_wmb(); | |
423 | ||
424 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 425 | count_spte_clear(sptep, spte); |
603e0651 XG |
426 | } |
427 | ||
428 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
429 | { | |
430 | union split_spte *ssptep, sspte, orig; | |
431 | ||
432 | ssptep = (union split_spte *)sptep; | |
433 | sspte = (union split_spte)spte; | |
434 | ||
435 | /* xchg acts as a barrier before the setting of the high bits */ | |
436 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
437 | orig.spte_high = ssptep->spte_high; |
438 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 439 | count_spte_clear(sptep, spte); |
603e0651 XG |
440 | |
441 | return orig.spte; | |
442 | } | |
c2a2ac2b XG |
443 | |
444 | /* | |
445 | * The idea using the light way get the spte on x86_32 guest is from | |
446 | * gup_get_pte(arch/x86/mm/gup.c). | |
447 | * The difference is we can not catch the spte tlb flush if we leave | |
448 | * guest mode, so we emulate it by increase clear_spte_count when spte | |
449 | * is cleared. | |
450 | */ | |
451 | static u64 __get_spte_lockless(u64 *sptep) | |
452 | { | |
453 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
454 | union split_spte spte, *orig = (union split_spte *)sptep; | |
455 | int count; | |
456 | ||
457 | retry: | |
458 | count = sp->clear_spte_count; | |
459 | smp_rmb(); | |
460 | ||
461 | spte.spte_low = orig->spte_low; | |
462 | smp_rmb(); | |
463 | ||
464 | spte.spte_high = orig->spte_high; | |
465 | smp_rmb(); | |
466 | ||
467 | if (unlikely(spte.spte_low != orig->spte_low || | |
468 | count != sp->clear_spte_count)) | |
469 | goto retry; | |
470 | ||
471 | return spte.spte; | |
472 | } | |
ce88decf XG |
473 | |
474 | static bool __check_direct_spte_mmio_pf(u64 spte) | |
475 | { | |
476 | union split_spte sspte = (union split_spte)spte; | |
477 | u32 high_mmio_mask = shadow_mmio_mask >> 32; | |
478 | ||
479 | /* It is valid if the spte is zapped. */ | |
480 | if (spte == 0ull) | |
481 | return true; | |
482 | ||
483 | /* It is valid if the spte is being zapped. */ | |
484 | if (sspte.spte_low == 0ull && | |
485 | (sspte.spte_high & high_mmio_mask) == high_mmio_mask) | |
486 | return true; | |
487 | ||
488 | return false; | |
489 | } | |
603e0651 XG |
490 | #endif |
491 | ||
c7ba5b48 XG |
492 | static bool spte_is_locklessly_modifiable(u64 spte) |
493 | { | |
feb3eb70 GN |
494 | return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) == |
495 | (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE); | |
c7ba5b48 XG |
496 | } |
497 | ||
8672b721 XG |
498 | static bool spte_has_volatile_bits(u64 spte) |
499 | { | |
c7ba5b48 XG |
500 | /* |
501 | * Always atomicly update spte if it can be updated | |
502 | * out of mmu-lock, it can ensure dirty bit is not lost, | |
503 | * also, it can help us to get a stable is_writable_pte() | |
504 | * to ensure tlb flush is not missed. | |
505 | */ | |
506 | if (spte_is_locklessly_modifiable(spte)) | |
507 | return true; | |
508 | ||
8672b721 XG |
509 | if (!shadow_accessed_mask) |
510 | return false; | |
511 | ||
512 | if (!is_shadow_present_pte(spte)) | |
513 | return false; | |
514 | ||
4132779b XG |
515 | if ((spte & shadow_accessed_mask) && |
516 | (!is_writable_pte(spte) || (spte & shadow_dirty_mask))) | |
8672b721 XG |
517 | return false; |
518 | ||
519 | return true; | |
520 | } | |
521 | ||
4132779b XG |
522 | static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask) |
523 | { | |
524 | return (old_spte & bit_mask) && !(new_spte & bit_mask); | |
525 | } | |
526 | ||
1df9f2dc XG |
527 | /* Rules for using mmu_spte_set: |
528 | * Set the sptep from nonpresent to present. | |
529 | * Note: the sptep being assigned *must* be either not present | |
530 | * or in a state where the hardware will not attempt to update | |
531 | * the spte. | |
532 | */ | |
533 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
534 | { | |
535 | WARN_ON(is_shadow_present_pte(*sptep)); | |
536 | __set_spte(sptep, new_spte); | |
537 | } | |
538 | ||
539 | /* Rules for using mmu_spte_update: | |
540 | * Update the state bits, it means the mapped pfn is not changged. | |
6e7d0354 XG |
541 | * |
542 | * Whenever we overwrite a writable spte with a read-only one we | |
543 | * should flush remote TLBs. Otherwise rmap_write_protect | |
544 | * will find a read-only spte, even though the writable spte | |
545 | * might be cached on a CPU's TLB, the return value indicates this | |
546 | * case. | |
1df9f2dc | 547 | */ |
6e7d0354 | 548 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) |
b79b93f9 | 549 | { |
c7ba5b48 | 550 | u64 old_spte = *sptep; |
6e7d0354 | 551 | bool ret = false; |
4132779b XG |
552 | |
553 | WARN_ON(!is_rmap_spte(new_spte)); | |
b79b93f9 | 554 | |
6e7d0354 XG |
555 | if (!is_shadow_present_pte(old_spte)) { |
556 | mmu_spte_set(sptep, new_spte); | |
557 | return ret; | |
558 | } | |
4132779b | 559 | |
c7ba5b48 | 560 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 561 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 562 | else |
603e0651 | 563 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 564 | |
c7ba5b48 XG |
565 | /* |
566 | * For the spte updated out of mmu-lock is safe, since | |
567 | * we always atomicly update it, see the comments in | |
568 | * spte_has_volatile_bits(). | |
569 | */ | |
6e7d0354 XG |
570 | if (is_writable_pte(old_spte) && !is_writable_pte(new_spte)) |
571 | ret = true; | |
572 | ||
4132779b | 573 | if (!shadow_accessed_mask) |
6e7d0354 | 574 | return ret; |
4132779b XG |
575 | |
576 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask)) | |
577 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); | |
578 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask)) | |
579 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); | |
6e7d0354 XG |
580 | |
581 | return ret; | |
b79b93f9 AK |
582 | } |
583 | ||
1df9f2dc XG |
584 | /* |
585 | * Rules for using mmu_spte_clear_track_bits: | |
586 | * It sets the sptep from present to nonpresent, and track the | |
587 | * state bits, it is used to clear the last level sptep. | |
588 | */ | |
589 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
590 | { | |
591 | pfn_t pfn; | |
592 | u64 old_spte = *sptep; | |
593 | ||
594 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 595 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 596 | else |
603e0651 | 597 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc XG |
598 | |
599 | if (!is_rmap_spte(old_spte)) | |
600 | return 0; | |
601 | ||
602 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
603 | |
604 | /* | |
605 | * KVM does not hold the refcount of the page used by | |
606 | * kvm mmu, before reclaiming the page, we should | |
607 | * unmap it from mmu first. | |
608 | */ | |
609 | WARN_ON(!kvm_is_mmio_pfn(pfn) && !page_count(pfn_to_page(pfn))); | |
610 | ||
1df9f2dc XG |
611 | if (!shadow_accessed_mask || old_spte & shadow_accessed_mask) |
612 | kvm_set_pfn_accessed(pfn); | |
613 | if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask)) | |
614 | kvm_set_pfn_dirty(pfn); | |
615 | return 1; | |
616 | } | |
617 | ||
618 | /* | |
619 | * Rules for using mmu_spte_clear_no_track: | |
620 | * Directly clear spte without caring the state bits of sptep, | |
621 | * it is used to set the upper level spte. | |
622 | */ | |
623 | static void mmu_spte_clear_no_track(u64 *sptep) | |
624 | { | |
603e0651 | 625 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
626 | } |
627 | ||
c2a2ac2b XG |
628 | static u64 mmu_spte_get_lockless(u64 *sptep) |
629 | { | |
630 | return __get_spte_lockless(sptep); | |
631 | } | |
632 | ||
633 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) | |
634 | { | |
c142786c AK |
635 | /* |
636 | * Prevent page table teardown by making any free-er wait during | |
637 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
638 | */ | |
639 | local_irq_disable(); | |
640 | vcpu->mode = READING_SHADOW_PAGE_TABLES; | |
641 | /* | |
642 | * Make sure a following spte read is not reordered ahead of the write | |
643 | * to vcpu->mode. | |
644 | */ | |
645 | smp_mb(); | |
c2a2ac2b XG |
646 | } |
647 | ||
648 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
649 | { | |
c142786c AK |
650 | /* |
651 | * Make sure the write to vcpu->mode is not reordered in front of | |
652 | * reads to sptes. If it does, kvm_commit_zap_page() can see us | |
653 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. | |
654 | */ | |
655 | smp_mb(); | |
656 | vcpu->mode = OUTSIDE_GUEST_MODE; | |
657 | local_irq_enable(); | |
c2a2ac2b XG |
658 | } |
659 | ||
e2dec939 | 660 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 661 | struct kmem_cache *base_cache, int min) |
714b93da AK |
662 | { |
663 | void *obj; | |
664 | ||
665 | if (cache->nobjs >= min) | |
e2dec939 | 666 | return 0; |
714b93da | 667 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 668 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 669 | if (!obj) |
e2dec939 | 670 | return -ENOMEM; |
714b93da AK |
671 | cache->objects[cache->nobjs++] = obj; |
672 | } | |
e2dec939 | 673 | return 0; |
714b93da AK |
674 | } |
675 | ||
f759e2b4 XG |
676 | static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache) |
677 | { | |
678 | return cache->nobjs; | |
679 | } | |
680 | ||
e8ad9a70 XG |
681 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
682 | struct kmem_cache *cache) | |
714b93da AK |
683 | { |
684 | while (mc->nobjs) | |
e8ad9a70 | 685 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
686 | } |
687 | ||
c1158e63 | 688 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 689 | int min) |
c1158e63 | 690 | { |
842f22ed | 691 | void *page; |
c1158e63 AK |
692 | |
693 | if (cache->nobjs >= min) | |
694 | return 0; | |
695 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
842f22ed | 696 | page = (void *)__get_free_page(GFP_KERNEL); |
c1158e63 AK |
697 | if (!page) |
698 | return -ENOMEM; | |
842f22ed | 699 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
700 | } |
701 | return 0; | |
702 | } | |
703 | ||
704 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
705 | { | |
706 | while (mc->nobjs) | |
c4d198d5 | 707 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
708 | } |
709 | ||
2e3e5882 | 710 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 711 | { |
e2dec939 AK |
712 | int r; |
713 | ||
53c07b18 | 714 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 715 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
716 | if (r) |
717 | goto out; | |
ad312c7c | 718 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
719 | if (r) |
720 | goto out; | |
ad312c7c | 721 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 722 | mmu_page_header_cache, 4); |
e2dec939 AK |
723 | out: |
724 | return r; | |
714b93da AK |
725 | } |
726 | ||
727 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
728 | { | |
53c07b18 XG |
729 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
730 | pte_list_desc_cache); | |
ad312c7c | 731 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
732 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
733 | mmu_page_header_cache); | |
714b93da AK |
734 | } |
735 | ||
80feb89a | 736 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) |
714b93da AK |
737 | { |
738 | void *p; | |
739 | ||
740 | BUG_ON(!mc->nobjs); | |
741 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
742 | return p; |
743 | } | |
744 | ||
53c07b18 | 745 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 746 | { |
80feb89a | 747 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
748 | } |
749 | ||
53c07b18 | 750 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 751 | { |
53c07b18 | 752 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
753 | } |
754 | ||
2032a93d LJ |
755 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
756 | { | |
757 | if (!sp->role.direct) | |
758 | return sp->gfns[index]; | |
759 | ||
760 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
761 | } | |
762 | ||
763 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
764 | { | |
765 | if (sp->role.direct) | |
766 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
767 | else | |
768 | sp->gfns[index] = gfn; | |
769 | } | |
770 | ||
05da4558 | 771 | /* |
d4dbf470 TY |
772 | * Return the pointer to the large page information for a given gfn, |
773 | * handling slots that are not large page aligned. | |
05da4558 | 774 | */ |
d4dbf470 TY |
775 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
776 | struct kvm_memory_slot *slot, | |
777 | int level) | |
05da4558 MT |
778 | { |
779 | unsigned long idx; | |
780 | ||
fb03cb6f | 781 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 782 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
783 | } |
784 | ||
785 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
786 | { | |
d25797b2 | 787 | struct kvm_memory_slot *slot; |
d4dbf470 | 788 | struct kvm_lpage_info *linfo; |
d25797b2 | 789 | int i; |
05da4558 | 790 | |
a1f4d395 | 791 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
792 | for (i = PT_DIRECTORY_LEVEL; |
793 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
794 | linfo = lpage_info_slot(gfn, slot, i); |
795 | linfo->write_count += 1; | |
d25797b2 | 796 | } |
332b207d | 797 | kvm->arch.indirect_shadow_pages++; |
05da4558 MT |
798 | } |
799 | ||
800 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
801 | { | |
d25797b2 | 802 | struct kvm_memory_slot *slot; |
d4dbf470 | 803 | struct kvm_lpage_info *linfo; |
d25797b2 | 804 | int i; |
05da4558 | 805 | |
a1f4d395 | 806 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
807 | for (i = PT_DIRECTORY_LEVEL; |
808 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
809 | linfo = lpage_info_slot(gfn, slot, i); |
810 | linfo->write_count -= 1; | |
811 | WARN_ON(linfo->write_count < 0); | |
d25797b2 | 812 | } |
332b207d | 813 | kvm->arch.indirect_shadow_pages--; |
05da4558 MT |
814 | } |
815 | ||
d25797b2 JR |
816 | static int has_wrprotected_page(struct kvm *kvm, |
817 | gfn_t gfn, | |
818 | int level) | |
05da4558 | 819 | { |
2843099f | 820 | struct kvm_memory_slot *slot; |
d4dbf470 | 821 | struct kvm_lpage_info *linfo; |
05da4558 | 822 | |
a1f4d395 | 823 | slot = gfn_to_memslot(kvm, gfn); |
05da4558 | 824 | if (slot) { |
d4dbf470 TY |
825 | linfo = lpage_info_slot(gfn, slot, level); |
826 | return linfo->write_count; | |
05da4558 MT |
827 | } |
828 | ||
829 | return 1; | |
830 | } | |
831 | ||
d25797b2 | 832 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 833 | { |
8f0b1ab6 | 834 | unsigned long page_size; |
d25797b2 | 835 | int i, ret = 0; |
05da4558 | 836 | |
8f0b1ab6 | 837 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 838 | |
d25797b2 JR |
839 | for (i = PT_PAGE_TABLE_LEVEL; |
840 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
841 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
842 | ret = i; | |
843 | else | |
844 | break; | |
845 | } | |
846 | ||
4c2155ce | 847 | return ret; |
05da4558 MT |
848 | } |
849 | ||
5d163b1c XG |
850 | static struct kvm_memory_slot * |
851 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
852 | bool no_dirty_log) | |
05da4558 MT |
853 | { |
854 | struct kvm_memory_slot *slot; | |
5d163b1c XG |
855 | |
856 | slot = gfn_to_memslot(vcpu->kvm, gfn); | |
857 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID || | |
858 | (no_dirty_log && slot->dirty_bitmap)) | |
859 | slot = NULL; | |
860 | ||
861 | return slot; | |
862 | } | |
863 | ||
864 | static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
865 | { | |
a0a8eaba | 866 | return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true); |
936a5fe6 AA |
867 | } |
868 | ||
869 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
870 | { | |
871 | int host_level, level, max_level; | |
05da4558 | 872 | |
d25797b2 JR |
873 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
874 | ||
875 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
876 | return host_level; | |
877 | ||
55dd98c3 | 878 | max_level = min(kvm_x86_ops->get_lpage_level(), host_level); |
878403b7 SY |
879 | |
880 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
881 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
882 | break; | |
d25797b2 JR |
883 | |
884 | return level - 1; | |
05da4558 MT |
885 | } |
886 | ||
290fc38d | 887 | /* |
53c07b18 | 888 | * Pte mapping structures: |
cd4a4e53 | 889 | * |
53c07b18 | 890 | * If pte_list bit zero is zero, then pte_list point to the spte. |
cd4a4e53 | 891 | * |
53c07b18 XG |
892 | * If pte_list bit zero is one, (then pte_list & ~1) points to a struct |
893 | * pte_list_desc containing more mappings. | |
53a27b39 | 894 | * |
53c07b18 | 895 | * Returns the number of pte entries before the spte was added or zero if |
53a27b39 MT |
896 | * the spte was not added. |
897 | * | |
cd4a4e53 | 898 | */ |
53c07b18 XG |
899 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
900 | unsigned long *pte_list) | |
cd4a4e53 | 901 | { |
53c07b18 | 902 | struct pte_list_desc *desc; |
53a27b39 | 903 | int i, count = 0; |
cd4a4e53 | 904 | |
53c07b18 XG |
905 | if (!*pte_list) { |
906 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); | |
907 | *pte_list = (unsigned long)spte; | |
908 | } else if (!(*pte_list & 1)) { | |
909 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); | |
910 | desc = mmu_alloc_pte_list_desc(vcpu); | |
911 | desc->sptes[0] = (u64 *)*pte_list; | |
d555c333 | 912 | desc->sptes[1] = spte; |
53c07b18 | 913 | *pte_list = (unsigned long)desc | 1; |
cb16a7b3 | 914 | ++count; |
cd4a4e53 | 915 | } else { |
53c07b18 XG |
916 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
917 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
918 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { | |
cd4a4e53 | 919 | desc = desc->more; |
53c07b18 | 920 | count += PTE_LIST_EXT; |
53a27b39 | 921 | } |
53c07b18 XG |
922 | if (desc->sptes[PTE_LIST_EXT-1]) { |
923 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
924 | desc = desc->more; |
925 | } | |
d555c333 | 926 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 927 | ++count; |
d555c333 | 928 | desc->sptes[i] = spte; |
cd4a4e53 | 929 | } |
53a27b39 | 930 | return count; |
cd4a4e53 AK |
931 | } |
932 | ||
53c07b18 XG |
933 | static void |
934 | pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc, | |
935 | int i, struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
936 | { |
937 | int j; | |
938 | ||
53c07b18 | 939 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 940 | ; |
d555c333 AK |
941 | desc->sptes[i] = desc->sptes[j]; |
942 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
943 | if (j != 0) |
944 | return; | |
945 | if (!prev_desc && !desc->more) | |
53c07b18 | 946 | *pte_list = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
947 | else |
948 | if (prev_desc) | |
949 | prev_desc->more = desc->more; | |
950 | else | |
53c07b18 XG |
951 | *pte_list = (unsigned long)desc->more | 1; |
952 | mmu_free_pte_list_desc(desc); | |
cd4a4e53 AK |
953 | } |
954 | ||
53c07b18 | 955 | static void pte_list_remove(u64 *spte, unsigned long *pte_list) |
cd4a4e53 | 956 | { |
53c07b18 XG |
957 | struct pte_list_desc *desc; |
958 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
959 | int i; |
960 | ||
53c07b18 XG |
961 | if (!*pte_list) { |
962 | printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte); | |
cd4a4e53 | 963 | BUG(); |
53c07b18 XG |
964 | } else if (!(*pte_list & 1)) { |
965 | rmap_printk("pte_list_remove: %p 1->0\n", spte); | |
966 | if ((u64 *)*pte_list != spte) { | |
967 | printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte); | |
cd4a4e53 AK |
968 | BUG(); |
969 | } | |
53c07b18 | 970 | *pte_list = 0; |
cd4a4e53 | 971 | } else { |
53c07b18 XG |
972 | rmap_printk("pte_list_remove: %p many->many\n", spte); |
973 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
cd4a4e53 AK |
974 | prev_desc = NULL; |
975 | while (desc) { | |
53c07b18 | 976 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) |
d555c333 | 977 | if (desc->sptes[i] == spte) { |
53c07b18 | 978 | pte_list_desc_remove_entry(pte_list, |
714b93da | 979 | desc, i, |
cd4a4e53 AK |
980 | prev_desc); |
981 | return; | |
982 | } | |
983 | prev_desc = desc; | |
984 | desc = desc->more; | |
985 | } | |
53c07b18 | 986 | pr_err("pte_list_remove: %p many->many\n", spte); |
cd4a4e53 AK |
987 | BUG(); |
988 | } | |
989 | } | |
990 | ||
67052b35 XG |
991 | typedef void (*pte_list_walk_fn) (u64 *spte); |
992 | static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn) | |
993 | { | |
994 | struct pte_list_desc *desc; | |
995 | int i; | |
996 | ||
997 | if (!*pte_list) | |
998 | return; | |
999 | ||
1000 | if (!(*pte_list & 1)) | |
1001 | return fn((u64 *)*pte_list); | |
1002 | ||
1003 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
1004 | while (desc) { | |
1005 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) | |
1006 | fn(desc->sptes[i]); | |
1007 | desc = desc->more; | |
1008 | } | |
1009 | } | |
1010 | ||
9373e2c0 | 1011 | static unsigned long *__gfn_to_rmap(gfn_t gfn, int level, |
9b9b1492 | 1012 | struct kvm_memory_slot *slot) |
53c07b18 | 1013 | { |
77d11309 | 1014 | unsigned long idx; |
53c07b18 | 1015 | |
77d11309 | 1016 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
d89cc617 | 1017 | return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx]; |
53c07b18 XG |
1018 | } |
1019 | ||
9b9b1492 TY |
1020 | /* |
1021 | * Take gfn and return the reverse mapping to it. | |
1022 | */ | |
1023 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) | |
1024 | { | |
1025 | struct kvm_memory_slot *slot; | |
1026 | ||
1027 | slot = gfn_to_memslot(kvm, gfn); | |
9373e2c0 | 1028 | return __gfn_to_rmap(gfn, level, slot); |
9b9b1492 TY |
1029 | } |
1030 | ||
f759e2b4 XG |
1031 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
1032 | { | |
1033 | struct kvm_mmu_memory_cache *cache; | |
1034 | ||
1035 | cache = &vcpu->arch.mmu_pte_list_desc_cache; | |
1036 | return mmu_memory_cache_free_objects(cache); | |
1037 | } | |
1038 | ||
53c07b18 XG |
1039 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
1040 | { | |
1041 | struct kvm_mmu_page *sp; | |
1042 | unsigned long *rmapp; | |
1043 | ||
53c07b18 XG |
1044 | sp = page_header(__pa(spte)); |
1045 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
1046 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); | |
1047 | return pte_list_add(vcpu, spte, rmapp); | |
1048 | } | |
1049 | ||
53c07b18 XG |
1050 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
1051 | { | |
1052 | struct kvm_mmu_page *sp; | |
1053 | gfn_t gfn; | |
1054 | unsigned long *rmapp; | |
1055 | ||
1056 | sp = page_header(__pa(spte)); | |
1057 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
1058 | rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); | |
1059 | pte_list_remove(spte, rmapp); | |
1060 | } | |
1061 | ||
1e3f42f0 TY |
1062 | /* |
1063 | * Used by the following functions to iterate through the sptes linked by a | |
1064 | * rmap. All fields are private and not assumed to be used outside. | |
1065 | */ | |
1066 | struct rmap_iterator { | |
1067 | /* private fields */ | |
1068 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1069 | int pos; /* index of the sptep */ | |
1070 | }; | |
1071 | ||
1072 | /* | |
1073 | * Iteration must be started by this function. This should also be used after | |
1074 | * removing/dropping sptes from the rmap link because in such cases the | |
1075 | * information in the itererator may not be valid. | |
1076 | * | |
1077 | * Returns sptep if found, NULL otherwise. | |
1078 | */ | |
1079 | static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter) | |
1080 | { | |
1081 | if (!rmap) | |
1082 | return NULL; | |
1083 | ||
1084 | if (!(rmap & 1)) { | |
1085 | iter->desc = NULL; | |
1086 | return (u64 *)rmap; | |
1087 | } | |
1088 | ||
1089 | iter->desc = (struct pte_list_desc *)(rmap & ~1ul); | |
1090 | iter->pos = 0; | |
1091 | return iter->desc->sptes[iter->pos]; | |
1092 | } | |
1093 | ||
1094 | /* | |
1095 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1096 | * | |
1097 | * Returns sptep if found, NULL otherwise. | |
1098 | */ | |
1099 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1100 | { | |
1101 | if (iter->desc) { | |
1102 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1103 | u64 *sptep; | |
1104 | ||
1105 | ++iter->pos; | |
1106 | sptep = iter->desc->sptes[iter->pos]; | |
1107 | if (sptep) | |
1108 | return sptep; | |
1109 | } | |
1110 | ||
1111 | iter->desc = iter->desc->more; | |
1112 | ||
1113 | if (iter->desc) { | |
1114 | iter->pos = 0; | |
1115 | /* desc->sptes[0] cannot be NULL */ | |
1116 | return iter->desc->sptes[iter->pos]; | |
1117 | } | |
1118 | } | |
1119 | ||
1120 | return NULL; | |
1121 | } | |
1122 | ||
c3707958 | 1123 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1124 | { |
1df9f2dc | 1125 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1126 | rmap_remove(kvm, sptep); |
be38d276 AK |
1127 | } |
1128 | ||
8e22f955 XG |
1129 | |
1130 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1131 | { | |
1132 | if (is_large_pte(*sptep)) { | |
1133 | WARN_ON(page_header(__pa(sptep))->role.level == | |
1134 | PT_PAGE_TABLE_LEVEL); | |
1135 | drop_spte(kvm, sptep); | |
1136 | --kvm->stat.lpages; | |
1137 | return true; | |
1138 | } | |
1139 | ||
1140 | return false; | |
1141 | } | |
1142 | ||
1143 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1144 | { | |
1145 | if (__drop_large_spte(vcpu->kvm, sptep)) | |
1146 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1147 | } | |
1148 | ||
1149 | /* | |
49fde340 | 1150 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
6b73a960 MT |
1151 | * spte writ-protection is caused by protecting shadow page table. |
1152 | * @flush indicates whether tlb need be flushed. | |
49fde340 XG |
1153 | * |
1154 | * Note: write protection is difference between drity logging and spte | |
1155 | * protection: | |
1156 | * - for dirty logging, the spte can be set to writable at anytime if | |
1157 | * its dirty bitmap is properly set. | |
1158 | * - for spte protection, the spte can be writable only after unsync-ing | |
1159 | * shadow page. | |
8e22f955 | 1160 | * |
6b73a960 | 1161 | * Return true if the spte is dropped. |
8e22f955 | 1162 | */ |
6b73a960 MT |
1163 | static bool |
1164 | spte_write_protect(struct kvm *kvm, u64 *sptep, bool *flush, bool pt_protect) | |
d13bc5b5 XG |
1165 | { |
1166 | u64 spte = *sptep; | |
1167 | ||
49fde340 XG |
1168 | if (!is_writable_pte(spte) && |
1169 | !(pt_protect && spte_is_locklessly_modifiable(spte))) | |
d13bc5b5 XG |
1170 | return false; |
1171 | ||
1172 | rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); | |
1173 | ||
6b73a960 MT |
1174 | if (__drop_large_spte(kvm, sptep)) { |
1175 | *flush |= true; | |
1176 | return true; | |
1177 | } | |
1178 | ||
49fde340 XG |
1179 | if (pt_protect) |
1180 | spte &= ~SPTE_MMU_WRITEABLE; | |
d13bc5b5 | 1181 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1182 | |
6b73a960 MT |
1183 | *flush |= mmu_spte_update(sptep, spte); |
1184 | return false; | |
d13bc5b5 XG |
1185 | } |
1186 | ||
49fde340 | 1187 | static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp, |
245c3912 | 1188 | bool pt_protect) |
98348e95 | 1189 | { |
1e3f42f0 TY |
1190 | u64 *sptep; |
1191 | struct rmap_iterator iter; | |
d13bc5b5 | 1192 | bool flush = false; |
374cbac0 | 1193 | |
1e3f42f0 TY |
1194 | for (sptep = rmap_get_first(*rmapp, &iter); sptep;) { |
1195 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
6b73a960 MT |
1196 | if (spte_write_protect(kvm, sptep, &flush, pt_protect)) { |
1197 | sptep = rmap_get_first(*rmapp, &iter); | |
1198 | continue; | |
1199 | } | |
a0ed4607 | 1200 | |
d13bc5b5 | 1201 | sptep = rmap_get_next(&iter); |
374cbac0 | 1202 | } |
855149aa | 1203 | |
d13bc5b5 | 1204 | return flush; |
a0ed4607 TY |
1205 | } |
1206 | ||
5dc99b23 TY |
1207 | /** |
1208 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages | |
1209 | * @kvm: kvm instance | |
1210 | * @slot: slot to protect | |
1211 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1212 | * @mask: indicates which pages we should protect | |
1213 | * | |
1214 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1215 | * logging we do not have any such mappings. | |
1216 | */ | |
1217 | void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, | |
1218 | struct kvm_memory_slot *slot, | |
1219 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 TY |
1220 | { |
1221 | unsigned long *rmapp; | |
a0ed4607 | 1222 | |
5dc99b23 | 1223 | while (mask) { |
65fbe37c TY |
1224 | rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1225 | PT_PAGE_TABLE_LEVEL, slot); | |
245c3912 | 1226 | __rmap_write_protect(kvm, rmapp, false); |
05da4558 | 1227 | |
5dc99b23 TY |
1228 | /* clear the first set bit */ |
1229 | mask &= mask - 1; | |
1230 | } | |
374cbac0 AK |
1231 | } |
1232 | ||
2f84569f | 1233 | static bool rmap_write_protect(struct kvm *kvm, u64 gfn) |
95d4c16c TY |
1234 | { |
1235 | struct kvm_memory_slot *slot; | |
5dc99b23 TY |
1236 | unsigned long *rmapp; |
1237 | int i; | |
2f84569f | 1238 | bool write_protected = false; |
95d4c16c TY |
1239 | |
1240 | slot = gfn_to_memslot(kvm, gfn); | |
5dc99b23 TY |
1241 | |
1242 | for (i = PT_PAGE_TABLE_LEVEL; | |
1243 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
1244 | rmapp = __gfn_to_rmap(gfn, i, slot); | |
245c3912 | 1245 | write_protected |= __rmap_write_protect(kvm, rmapp, true); |
5dc99b23 TY |
1246 | } |
1247 | ||
1248 | return write_protected; | |
95d4c16c TY |
1249 | } |
1250 | ||
8a8365c5 | 1251 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1252 | struct kvm_memory_slot *slot, unsigned long data) |
e930bffe | 1253 | { |
1e3f42f0 TY |
1254 | u64 *sptep; |
1255 | struct rmap_iterator iter; | |
e930bffe AA |
1256 | int need_tlb_flush = 0; |
1257 | ||
1e3f42f0 TY |
1258 | while ((sptep = rmap_get_first(*rmapp, &iter))) { |
1259 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
1260 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep); | |
1261 | ||
1262 | drop_spte(kvm, sptep); | |
e930bffe AA |
1263 | need_tlb_flush = 1; |
1264 | } | |
1e3f42f0 | 1265 | |
e930bffe AA |
1266 | return need_tlb_flush; |
1267 | } | |
1268 | ||
8a8365c5 | 1269 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1270 | struct kvm_memory_slot *slot, unsigned long data) |
3da0dd43 | 1271 | { |
1e3f42f0 TY |
1272 | u64 *sptep; |
1273 | struct rmap_iterator iter; | |
3da0dd43 | 1274 | int need_flush = 0; |
1e3f42f0 | 1275 | u64 new_spte; |
3da0dd43 IE |
1276 | pte_t *ptep = (pte_t *)data; |
1277 | pfn_t new_pfn; | |
1278 | ||
1279 | WARN_ON(pte_huge(*ptep)); | |
1280 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 TY |
1281 | |
1282 | for (sptep = rmap_get_first(*rmapp, &iter); sptep;) { | |
1283 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1284 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep); | |
1285 | ||
3da0dd43 | 1286 | need_flush = 1; |
1e3f42f0 | 1287 | |
3da0dd43 | 1288 | if (pte_write(*ptep)) { |
1e3f42f0 TY |
1289 | drop_spte(kvm, sptep); |
1290 | sptep = rmap_get_first(*rmapp, &iter); | |
3da0dd43 | 1291 | } else { |
1e3f42f0 | 1292 | new_spte = *sptep & ~PT64_BASE_ADDR_MASK; |
3da0dd43 IE |
1293 | new_spte |= (u64)new_pfn << PAGE_SHIFT; |
1294 | ||
1295 | new_spte &= ~PT_WRITABLE_MASK; | |
1296 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 1297 | new_spte &= ~shadow_accessed_mask; |
1e3f42f0 TY |
1298 | |
1299 | mmu_spte_clear_track_bits(sptep); | |
1300 | mmu_spte_set(sptep, new_spte); | |
1301 | sptep = rmap_get_next(&iter); | |
3da0dd43 IE |
1302 | } |
1303 | } | |
1e3f42f0 | 1304 | |
3da0dd43 IE |
1305 | if (need_flush) |
1306 | kvm_flush_remote_tlbs(kvm); | |
1307 | ||
1308 | return 0; | |
1309 | } | |
1310 | ||
84504ef3 TY |
1311 | static int kvm_handle_hva_range(struct kvm *kvm, |
1312 | unsigned long start, | |
1313 | unsigned long end, | |
1314 | unsigned long data, | |
1315 | int (*handler)(struct kvm *kvm, | |
1316 | unsigned long *rmapp, | |
048212d0 | 1317 | struct kvm_memory_slot *slot, |
84504ef3 | 1318 | unsigned long data)) |
e930bffe | 1319 | { |
be6ba0f0 | 1320 | int j; |
f395302e | 1321 | int ret = 0; |
bc6678a3 | 1322 | struct kvm_memslots *slots; |
be6ba0f0 | 1323 | struct kvm_memory_slot *memslot; |
bc6678a3 | 1324 | |
90d83dc3 | 1325 | slots = kvm_memslots(kvm); |
e930bffe | 1326 | |
be6ba0f0 | 1327 | kvm_for_each_memslot(memslot, slots) { |
84504ef3 | 1328 | unsigned long hva_start, hva_end; |
bcd3ef58 | 1329 | gfn_t gfn_start, gfn_end; |
e930bffe | 1330 | |
84504ef3 TY |
1331 | hva_start = max(start, memslot->userspace_addr); |
1332 | hva_end = min(end, memslot->userspace_addr + | |
1333 | (memslot->npages << PAGE_SHIFT)); | |
1334 | if (hva_start >= hva_end) | |
1335 | continue; | |
1336 | /* | |
1337 | * {gfn(page) | page intersects with [hva_start, hva_end)} = | |
bcd3ef58 | 1338 | * {gfn_start, gfn_start+1, ..., gfn_end-1}. |
84504ef3 | 1339 | */ |
bcd3ef58 | 1340 | gfn_start = hva_to_gfn_memslot(hva_start, memslot); |
84504ef3 | 1341 | gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); |
852e3c19 | 1342 | |
bcd3ef58 TY |
1343 | for (j = PT_PAGE_TABLE_LEVEL; |
1344 | j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) { | |
1345 | unsigned long idx, idx_end; | |
1346 | unsigned long *rmapp; | |
d4dbf470 | 1347 | |
bcd3ef58 TY |
1348 | /* |
1349 | * {idx(page_j) | page_j intersects with | |
1350 | * [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}. | |
1351 | */ | |
1352 | idx = gfn_to_index(gfn_start, memslot->base_gfn, j); | |
1353 | idx_end = gfn_to_index(gfn_end - 1, memslot->base_gfn, j); | |
852e3c19 | 1354 | |
bcd3ef58 | 1355 | rmapp = __gfn_to_rmap(gfn_start, j, memslot); |
d4dbf470 | 1356 | |
bcd3ef58 TY |
1357 | for (; idx <= idx_end; ++idx) |
1358 | ret |= handler(kvm, rmapp++, memslot, data); | |
e930bffe AA |
1359 | } |
1360 | } | |
1361 | ||
f395302e | 1362 | return ret; |
e930bffe AA |
1363 | } |
1364 | ||
84504ef3 TY |
1365 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1366 | unsigned long data, | |
1367 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, | |
048212d0 | 1368 | struct kvm_memory_slot *slot, |
84504ef3 TY |
1369 | unsigned long data)) |
1370 | { | |
1371 | return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler); | |
e930bffe AA |
1372 | } |
1373 | ||
1374 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
1375 | { | |
3da0dd43 IE |
1376 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
1377 | } | |
1378 | ||
b3ae2096 TY |
1379 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end) |
1380 | { | |
1381 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp); | |
1382 | } | |
1383 | ||
3da0dd43 IE |
1384 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
1385 | { | |
8a8365c5 | 1386 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1387 | } |
1388 | ||
8a8365c5 | 1389 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1390 | struct kvm_memory_slot *slot, unsigned long data) |
e930bffe | 1391 | { |
1e3f42f0 | 1392 | u64 *sptep; |
79f702a6 | 1393 | struct rmap_iterator uninitialized_var(iter); |
e930bffe AA |
1394 | int young = 0; |
1395 | ||
6316e1c8 | 1396 | /* |
3f6d8c8a XH |
1397 | * In case of absence of EPT Access and Dirty Bits supports, |
1398 | * emulate the accessed bit for EPT, by checking if this page has | |
6316e1c8 RR |
1399 | * an EPT mapping, and clearing it if it does. On the next access, |
1400 | * a new EPT mapping will be established. | |
1401 | * This has some overhead, but not as much as the cost of swapping | |
1402 | * out actively used pages or breaking up actively used hugepages. | |
1403 | */ | |
f395302e TY |
1404 | if (!shadow_accessed_mask) { |
1405 | young = kvm_unmap_rmapp(kvm, rmapp, slot, data); | |
1406 | goto out; | |
1407 | } | |
534e38b4 | 1408 | |
1e3f42f0 TY |
1409 | for (sptep = rmap_get_first(*rmapp, &iter); sptep; |
1410 | sptep = rmap_get_next(&iter)) { | |
3f6d8c8a | 1411 | BUG_ON(!is_shadow_present_pte(*sptep)); |
1e3f42f0 | 1412 | |
3f6d8c8a | 1413 | if (*sptep & shadow_accessed_mask) { |
e930bffe | 1414 | young = 1; |
3f6d8c8a XH |
1415 | clear_bit((ffs(shadow_accessed_mask) - 1), |
1416 | (unsigned long *)sptep); | |
e930bffe | 1417 | } |
e930bffe | 1418 | } |
f395302e TY |
1419 | out: |
1420 | /* @data has hva passed to kvm_age_hva(). */ | |
1421 | trace_kvm_age_page(data, slot, young); | |
e930bffe AA |
1422 | return young; |
1423 | } | |
1424 | ||
8ee53820 | 1425 | static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1426 | struct kvm_memory_slot *slot, unsigned long data) |
8ee53820 | 1427 | { |
1e3f42f0 TY |
1428 | u64 *sptep; |
1429 | struct rmap_iterator iter; | |
8ee53820 AA |
1430 | int young = 0; |
1431 | ||
1432 | /* | |
1433 | * If there's no access bit in the secondary pte set by the | |
1434 | * hardware it's up to gup-fast/gup to set the access bit in | |
1435 | * the primary pte or in the page structure. | |
1436 | */ | |
1437 | if (!shadow_accessed_mask) | |
1438 | goto out; | |
1439 | ||
1e3f42f0 TY |
1440 | for (sptep = rmap_get_first(*rmapp, &iter); sptep; |
1441 | sptep = rmap_get_next(&iter)) { | |
3f6d8c8a | 1442 | BUG_ON(!is_shadow_present_pte(*sptep)); |
1e3f42f0 | 1443 | |
3f6d8c8a | 1444 | if (*sptep & shadow_accessed_mask) { |
8ee53820 AA |
1445 | young = 1; |
1446 | break; | |
1447 | } | |
8ee53820 AA |
1448 | } |
1449 | out: | |
1450 | return young; | |
1451 | } | |
1452 | ||
53a27b39 MT |
1453 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1454 | ||
852e3c19 | 1455 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
1456 | { |
1457 | unsigned long *rmapp; | |
852e3c19 JR |
1458 | struct kvm_mmu_page *sp; |
1459 | ||
1460 | sp = page_header(__pa(spte)); | |
53a27b39 | 1461 | |
852e3c19 | 1462 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 1463 | |
048212d0 | 1464 | kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, 0); |
53a27b39 MT |
1465 | kvm_flush_remote_tlbs(vcpu->kvm); |
1466 | } | |
1467 | ||
e930bffe AA |
1468 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
1469 | { | |
f395302e | 1470 | return kvm_handle_hva(kvm, hva, hva, kvm_age_rmapp); |
e930bffe AA |
1471 | } |
1472 | ||
8ee53820 AA |
1473 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1474 | { | |
1475 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1476 | } | |
1477 | ||
d6c69ee9 | 1478 | #ifdef MMU_DEBUG |
47ad8e68 | 1479 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1480 | { |
139bdb2d AK |
1481 | u64 *pos; |
1482 | u64 *end; | |
1483 | ||
47ad8e68 | 1484 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1485 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1486 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1487 | pos, *pos); |
6aa8b732 | 1488 | return 0; |
139bdb2d | 1489 | } |
6aa8b732 AK |
1490 | return 1; |
1491 | } | |
d6c69ee9 | 1492 | #endif |
6aa8b732 | 1493 | |
45221ab6 DH |
1494 | /* |
1495 | * This value is the sum of all of the kvm instances's | |
1496 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1497 | * aggregate version in order to make the slab shrinker | |
1498 | * faster | |
1499 | */ | |
1500 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
1501 | { | |
1502 | kvm->arch.n_used_mmu_pages += nr; | |
1503 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1504 | } | |
1505 | ||
834be0d8 | 1506 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 1507 | { |
4db35314 | 1508 | ASSERT(is_empty_shadow_page(sp->spt)); |
7775834a | 1509 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
1510 | list_del(&sp->link); |
1511 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
1512 | if (!sp->role.direct) |
1513 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 1514 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1515 | } |
1516 | ||
cea0f0e7 AK |
1517 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1518 | { | |
1ae0a13d | 1519 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
1520 | } |
1521 | ||
714b93da | 1522 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1523 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1524 | { |
cea0f0e7 AK |
1525 | if (!parent_pte) |
1526 | return; | |
cea0f0e7 | 1527 | |
67052b35 | 1528 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1529 | } |
1530 | ||
4db35314 | 1531 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1532 | u64 *parent_pte) |
1533 | { | |
67052b35 | 1534 | pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1535 | } |
1536 | ||
bcdd9a93 XG |
1537 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1538 | u64 *parent_pte) | |
1539 | { | |
1540 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1541 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1542 | } |
1543 | ||
67052b35 XG |
1544 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
1545 | u64 *parent_pte, int direct) | |
ad8cfbe3 | 1546 | { |
67052b35 | 1547 | struct kvm_mmu_page *sp; |
7ddca7e4 | 1548 | |
80feb89a TY |
1549 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
1550 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); | |
67052b35 | 1551 | if (!direct) |
80feb89a | 1552 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); |
67052b35 | 1553 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
5304b8d3 XG |
1554 | |
1555 | /* | |
1556 | * The active_mmu_pages list is the FIFO list, do not move the | |
1557 | * page until it is zapped. kvm_zap_obsolete_pages depends on | |
1558 | * this feature. See the comments in kvm_zap_obsolete_pages(). | |
1559 | */ | |
67052b35 | 1560 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
67052b35 XG |
1561 | sp->parent_ptes = 0; |
1562 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); | |
1563 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); | |
1564 | return sp; | |
ad8cfbe3 MT |
1565 | } |
1566 | ||
67052b35 | 1567 | static void mark_unsync(u64 *spte); |
1047df1f | 1568 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1569 | { |
67052b35 | 1570 | pte_list_walk(&sp->parent_ptes, mark_unsync); |
0074ff63 MT |
1571 | } |
1572 | ||
67052b35 | 1573 | static void mark_unsync(u64 *spte) |
0074ff63 | 1574 | { |
67052b35 | 1575 | struct kvm_mmu_page *sp; |
1047df1f | 1576 | unsigned int index; |
0074ff63 | 1577 | |
67052b35 | 1578 | sp = page_header(__pa(spte)); |
1047df1f XG |
1579 | index = spte - sp->spt; |
1580 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1581 | return; |
1047df1f | 1582 | if (sp->unsync_children++) |
0074ff63 | 1583 | return; |
1047df1f | 1584 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1585 | } |
1586 | ||
e8bc217a | 1587 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1588 | struct kvm_mmu_page *sp) |
e8bc217a MT |
1589 | { |
1590 | return 1; | |
1591 | } | |
1592 | ||
a7052897 MT |
1593 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1594 | { | |
1595 | } | |
1596 | ||
0f53b5b1 XG |
1597 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1598 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 1599 | const void *pte) |
0f53b5b1 XG |
1600 | { |
1601 | WARN_ON(1); | |
1602 | } | |
1603 | ||
60c8aec6 MT |
1604 | #define KVM_PAGE_ARRAY_NR 16 |
1605 | ||
1606 | struct kvm_mmu_pages { | |
1607 | struct mmu_page_and_offset { | |
1608 | struct kvm_mmu_page *sp; | |
1609 | unsigned int idx; | |
1610 | } page[KVM_PAGE_ARRAY_NR]; | |
1611 | unsigned int nr; | |
1612 | }; | |
1613 | ||
cded19f3 HE |
1614 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1615 | int idx) | |
4731d4c7 | 1616 | { |
60c8aec6 | 1617 | int i; |
4731d4c7 | 1618 | |
60c8aec6 MT |
1619 | if (sp->unsync) |
1620 | for (i=0; i < pvec->nr; i++) | |
1621 | if (pvec->page[i].sp == sp) | |
1622 | return 0; | |
1623 | ||
1624 | pvec->page[pvec->nr].sp = sp; | |
1625 | pvec->page[pvec->nr].idx = idx; | |
1626 | pvec->nr++; | |
1627 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1628 | } | |
1629 | ||
1630 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1631 | struct kvm_mmu_pages *pvec) | |
1632 | { | |
1633 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1634 | |
37178b8b | 1635 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 1636 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1637 | u64 ent = sp->spt[i]; |
1638 | ||
7a8f1a74 XG |
1639 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) |
1640 | goto clear_child_bitmap; | |
1641 | ||
1642 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1643 | ||
1644 | if (child->unsync_children) { | |
1645 | if (mmu_pages_add(pvec, child, i)) | |
1646 | return -ENOSPC; | |
1647 | ||
1648 | ret = __mmu_unsync_walk(child, pvec); | |
1649 | if (!ret) | |
1650 | goto clear_child_bitmap; | |
1651 | else if (ret > 0) | |
1652 | nr_unsync_leaf += ret; | |
1653 | else | |
1654 | return ret; | |
1655 | } else if (child->unsync) { | |
1656 | nr_unsync_leaf++; | |
1657 | if (mmu_pages_add(pvec, child, i)) | |
1658 | return -ENOSPC; | |
1659 | } else | |
1660 | goto clear_child_bitmap; | |
1661 | ||
1662 | continue; | |
1663 | ||
1664 | clear_child_bitmap: | |
1665 | __clear_bit(i, sp->unsync_child_bitmap); | |
1666 | sp->unsync_children--; | |
1667 | WARN_ON((int)sp->unsync_children < 0); | |
4731d4c7 MT |
1668 | } |
1669 | ||
4731d4c7 | 1670 | |
60c8aec6 MT |
1671 | return nr_unsync_leaf; |
1672 | } | |
1673 | ||
1674 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1675 | struct kvm_mmu_pages *pvec) | |
1676 | { | |
1677 | if (!sp->unsync_children) | |
1678 | return 0; | |
1679 | ||
1680 | mmu_pages_add(pvec, sp, 0); | |
1681 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1682 | } |
1683 | ||
4731d4c7 MT |
1684 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1685 | { | |
1686 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1687 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1688 | sp->unsync = 0; |
1689 | --kvm->stat.mmu_unsync; | |
1690 | } | |
1691 | ||
7775834a XG |
1692 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1693 | struct list_head *invalid_list); | |
1694 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1695 | struct list_head *invalid_list); | |
4731d4c7 | 1696 | |
f34d251d XG |
1697 | /* |
1698 | * NOTE: we should pay more attention on the zapped-obsolete page | |
1699 | * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk | |
1700 | * since it has been deleted from active_mmu_pages but still can be found | |
1701 | * at hast list. | |
1702 | * | |
1703 | * for_each_gfn_indirect_valid_sp has skipped that kind of page and | |
1704 | * kvm_mmu_get_page(), the only user of for_each_gfn_sp(), has skipped | |
1705 | * all the obsolete pages. | |
1706 | */ | |
1044b030 TY |
1707 | #define for_each_gfn_sp(_kvm, _sp, _gfn) \ |
1708 | hlist_for_each_entry(_sp, \ | |
1709 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \ | |
1710 | if ((_sp)->gfn != (_gfn)) {} else | |
1711 | ||
1712 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
1713 | for_each_gfn_sp(_kvm, _sp, _gfn) \ | |
1714 | if ((_sp)->role.direct || (_sp)->role.invalid) {} else | |
7ae680eb | 1715 | |
f918b443 | 1716 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1717 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1718 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1719 | { |
5b7e0102 | 1720 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1721 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1722 | return 1; |
1723 | } | |
1724 | ||
f918b443 | 1725 | if (clear_unsync) |
1d9dc7e0 | 1726 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1727 | |
a4a8e6f7 | 1728 | if (vcpu->arch.mmu.sync_page(vcpu, sp)) { |
d98ba053 | 1729 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1730 | return 1; |
1731 | } | |
1732 | ||
1733 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1734 | return 0; |
1735 | } | |
1736 | ||
1d9dc7e0 XG |
1737 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1738 | struct kvm_mmu_page *sp) | |
1739 | { | |
d98ba053 | 1740 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1741 | int ret; |
1742 | ||
d98ba053 | 1743 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1744 | if (ret) |
d98ba053 XG |
1745 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1746 | ||
1d9dc7e0 XG |
1747 | return ret; |
1748 | } | |
1749 | ||
e37fa785 XG |
1750 | #ifdef CONFIG_KVM_MMU_AUDIT |
1751 | #include "mmu_audit.c" | |
1752 | #else | |
1753 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
1754 | static void mmu_audit_disable(void) { } | |
1755 | #endif | |
1756 | ||
d98ba053 XG |
1757 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1758 | struct list_head *invalid_list) | |
1d9dc7e0 | 1759 | { |
d98ba053 | 1760 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1761 | } |
1762 | ||
9f1a122f XG |
1763 | /* @gfn should be write-protected at the call site */ |
1764 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1765 | { | |
9f1a122f | 1766 | struct kvm_mmu_page *s; |
d98ba053 | 1767 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1768 | bool flush = false; |
1769 | ||
b67bfe0d | 1770 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 1771 | if (!s->unsync) |
9f1a122f XG |
1772 | continue; |
1773 | ||
1774 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
a4a8e6f7 | 1775 | kvm_unlink_unsync_page(vcpu->kvm, s); |
9f1a122f | 1776 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || |
a4a8e6f7 | 1777 | (vcpu->arch.mmu.sync_page(vcpu, s))) { |
d98ba053 | 1778 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1779 | continue; |
1780 | } | |
9f1a122f XG |
1781 | flush = true; |
1782 | } | |
1783 | ||
d98ba053 | 1784 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f XG |
1785 | if (flush) |
1786 | kvm_mmu_flush_tlb(vcpu); | |
1787 | } | |
1788 | ||
60c8aec6 MT |
1789 | struct mmu_page_path { |
1790 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1791 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1792 | }; |
1793 | ||
60c8aec6 MT |
1794 | #define for_each_sp(pvec, sp, parents, i) \ |
1795 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1796 | sp = pvec.page[i].sp; \ | |
1797 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1798 | i = mmu_pages_next(&pvec, &parents, i)) | |
1799 | ||
cded19f3 HE |
1800 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1801 | struct mmu_page_path *parents, | |
1802 | int i) | |
60c8aec6 MT |
1803 | { |
1804 | int n; | |
1805 | ||
1806 | for (n = i+1; n < pvec->nr; n++) { | |
1807 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1808 | ||
1809 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1810 | parents->idx[0] = pvec->page[n].idx; | |
1811 | return n; | |
1812 | } | |
1813 | ||
1814 | parents->parent[sp->role.level-2] = sp; | |
1815 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1816 | } | |
1817 | ||
1818 | return n; | |
1819 | } | |
1820 | ||
cded19f3 | 1821 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1822 | { |
60c8aec6 MT |
1823 | struct kvm_mmu_page *sp; |
1824 | unsigned int level = 0; | |
1825 | ||
1826 | do { | |
1827 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1828 | |
60c8aec6 MT |
1829 | sp = parents->parent[level]; |
1830 | if (!sp) | |
1831 | return; | |
1832 | ||
1833 | --sp->unsync_children; | |
1834 | WARN_ON((int)sp->unsync_children < 0); | |
1835 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1836 | level++; | |
1837 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1838 | } |
1839 | ||
60c8aec6 MT |
1840 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1841 | struct mmu_page_path *parents, | |
1842 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1843 | { |
60c8aec6 MT |
1844 | parents->parent[parent->role.level-1] = NULL; |
1845 | pvec->nr = 0; | |
1846 | } | |
4731d4c7 | 1847 | |
60c8aec6 MT |
1848 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1849 | struct kvm_mmu_page *parent) | |
1850 | { | |
1851 | int i; | |
1852 | struct kvm_mmu_page *sp; | |
1853 | struct mmu_page_path parents; | |
1854 | struct kvm_mmu_pages pages; | |
d98ba053 | 1855 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
1856 | |
1857 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1858 | while (mmu_unsync_walk(parent, &pages)) { | |
2f84569f | 1859 | bool protected = false; |
b1a36821 MT |
1860 | |
1861 | for_each_sp(pages, sp, parents, i) | |
1862 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1863 | ||
1864 | if (protected) | |
1865 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1866 | ||
60c8aec6 | 1867 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 1868 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1869 | mmu_pages_clear_parents(&parents); |
1870 | } | |
d98ba053 | 1871 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 1872 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1873 | kvm_mmu_pages_init(parent, &parents, &pages); |
1874 | } | |
4731d4c7 MT |
1875 | } |
1876 | ||
c3707958 XG |
1877 | static void init_shadow_page_table(struct kvm_mmu_page *sp) |
1878 | { | |
1879 | int i; | |
1880 | ||
1881 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1882 | sp->spt[i] = 0ull; | |
1883 | } | |
1884 | ||
a30f47cb XG |
1885 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
1886 | { | |
1887 | sp->write_flooding_count = 0; | |
1888 | } | |
1889 | ||
1890 | static void clear_sp_write_flooding_count(u64 *spte) | |
1891 | { | |
1892 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
1893 | ||
1894 | __clear_sp_write_flooding_count(sp); | |
1895 | } | |
1896 | ||
5304b8d3 XG |
1897 | static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) |
1898 | { | |
1899 | return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); | |
1900 | } | |
1901 | ||
cea0f0e7 AK |
1902 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1903 | gfn_t gfn, | |
1904 | gva_t gaddr, | |
1905 | unsigned level, | |
f6e2c02b | 1906 | int direct, |
41074d07 | 1907 | unsigned access, |
f7d9c7b7 | 1908 | u64 *parent_pte) |
cea0f0e7 AK |
1909 | { |
1910 | union kvm_mmu_page_role role; | |
cea0f0e7 | 1911 | unsigned quadrant; |
9f1a122f | 1912 | struct kvm_mmu_page *sp; |
9f1a122f | 1913 | bool need_sync = false; |
cea0f0e7 | 1914 | |
a770f6f2 | 1915 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1916 | role.level = level; |
f6e2c02b | 1917 | role.direct = direct; |
84b0c8c6 | 1918 | if (role.direct) |
5b7e0102 | 1919 | role.cr4_pae = 0; |
41074d07 | 1920 | role.access = access; |
c5a78f2b JR |
1921 | if (!vcpu->arch.mmu.direct_map |
1922 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
1923 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1924 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1925 | role.quadrant = quadrant; | |
1926 | } | |
b67bfe0d | 1927 | for_each_gfn_sp(vcpu->kvm, sp, gfn) { |
7f52af74 XG |
1928 | if (is_obsolete_sp(vcpu->kvm, sp)) |
1929 | continue; | |
1930 | ||
7ae680eb XG |
1931 | if (!need_sync && sp->unsync) |
1932 | need_sync = true; | |
4731d4c7 | 1933 | |
7ae680eb XG |
1934 | if (sp->role.word != role.word) |
1935 | continue; | |
4731d4c7 | 1936 | |
7ae680eb XG |
1937 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
1938 | break; | |
e02aa901 | 1939 | |
7ae680eb XG |
1940 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
1941 | if (sp->unsync_children) { | |
a8eeb04a | 1942 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
7ae680eb XG |
1943 | kvm_mmu_mark_parents_unsync(sp); |
1944 | } else if (sp->unsync) | |
1945 | kvm_mmu_mark_parents_unsync(sp); | |
e02aa901 | 1946 | |
a30f47cb | 1947 | __clear_sp_write_flooding_count(sp); |
7ae680eb XG |
1948 | trace_kvm_mmu_get_page(sp, false); |
1949 | return sp; | |
1950 | } | |
dfc5aa00 | 1951 | ++vcpu->kvm->stat.mmu_cache_miss; |
2032a93d | 1952 | sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct); |
4db35314 AK |
1953 | if (!sp) |
1954 | return sp; | |
4db35314 AK |
1955 | sp->gfn = gfn; |
1956 | sp->role = role; | |
7ae680eb XG |
1957 | hlist_add_head(&sp->hash_link, |
1958 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 1959 | if (!direct) { |
b1a36821 MT |
1960 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1961 | kvm_flush_remote_tlbs(vcpu->kvm); | |
9f1a122f XG |
1962 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
1963 | kvm_sync_pages(vcpu, gfn); | |
1964 | ||
4731d4c7 MT |
1965 | account_shadowed(vcpu->kvm, gfn); |
1966 | } | |
5304b8d3 | 1967 | sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen; |
c3707958 | 1968 | init_shadow_page_table(sp); |
f691fe1d | 1969 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1970 | return sp; |
cea0f0e7 AK |
1971 | } |
1972 | ||
2d11123a AK |
1973 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1974 | struct kvm_vcpu *vcpu, u64 addr) | |
1975 | { | |
1976 | iterator->addr = addr; | |
1977 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1978 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 JR |
1979 | |
1980 | if (iterator->level == PT64_ROOT_LEVEL && | |
1981 | vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL && | |
1982 | !vcpu->arch.mmu.direct_map) | |
1983 | --iterator->level; | |
1984 | ||
2d11123a AK |
1985 | if (iterator->level == PT32E_ROOT_LEVEL) { |
1986 | iterator->shadow_addr | |
1987 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
1988 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
1989 | --iterator->level; | |
1990 | if (!iterator->shadow_addr) | |
1991 | iterator->level = 0; | |
1992 | } | |
1993 | } | |
1994 | ||
1995 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
1996 | { | |
1997 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
1998 | return false; | |
4d88954d | 1999 | |
2d11123a AK |
2000 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
2001 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
2002 | return true; | |
2003 | } | |
2004 | ||
c2a2ac2b XG |
2005 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
2006 | u64 spte) | |
2d11123a | 2007 | { |
c2a2ac2b | 2008 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
2009 | iterator->level = 0; |
2010 | return; | |
2011 | } | |
2012 | ||
c2a2ac2b | 2013 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
2014 | --iterator->level; |
2015 | } | |
2016 | ||
c2a2ac2b XG |
2017 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
2018 | { | |
2019 | return __shadow_walk_next(iterator, *iterator->sptep); | |
2020 | } | |
2021 | ||
32ef26a3 AK |
2022 | static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp) |
2023 | { | |
2024 | u64 spte; | |
2025 | ||
24db2734 XG |
2026 | spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
2027 | shadow_user_mask | shadow_x_mask | shadow_accessed_mask; | |
2028 | ||
1df9f2dc | 2029 | mmu_spte_set(sptep, spte); |
32ef26a3 AK |
2030 | } |
2031 | ||
a357bd22 AK |
2032 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2033 | unsigned direct_access) | |
2034 | { | |
2035 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
2036 | struct kvm_mmu_page *child; | |
2037 | ||
2038 | /* | |
2039 | * For the direct sp, if the guest pte's dirty bit | |
2040 | * changed form clean to dirty, it will corrupt the | |
2041 | * sp's access: allow writable in the read-only sp, | |
2042 | * so we should update the spte at this point to get | |
2043 | * a new sp with the correct access. | |
2044 | */ | |
2045 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
2046 | if (child->role.access == direct_access) | |
2047 | return; | |
2048 | ||
bcdd9a93 | 2049 | drop_parent_pte(child, sptep); |
a357bd22 AK |
2050 | kvm_flush_remote_tlbs(vcpu->kvm); |
2051 | } | |
2052 | } | |
2053 | ||
505aef8f | 2054 | static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
38e3b2b2 XG |
2055 | u64 *spte) |
2056 | { | |
2057 | u64 pte; | |
2058 | struct kvm_mmu_page *child; | |
2059 | ||
2060 | pte = *spte; | |
2061 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2062 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2063 | drop_spte(kvm, spte); |
505aef8f XG |
2064 | if (is_large_pte(pte)) |
2065 | --kvm->stat.lpages; | |
2066 | } else { | |
38e3b2b2 | 2067 | child = page_header(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2068 | drop_parent_pte(child, spte); |
38e3b2b2 | 2069 | } |
505aef8f XG |
2070 | return true; |
2071 | } | |
2072 | ||
2073 | if (is_mmio_spte(pte)) | |
ce88decf | 2074 | mmu_spte_clear_no_track(spte); |
c3707958 | 2075 | |
505aef8f | 2076 | return false; |
38e3b2b2 XG |
2077 | } |
2078 | ||
90cb0529 | 2079 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 2080 | struct kvm_mmu_page *sp) |
a436036b | 2081 | { |
697fe2e2 | 2082 | unsigned i; |
697fe2e2 | 2083 | |
38e3b2b2 XG |
2084 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2085 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
2086 | } |
2087 | ||
4db35314 | 2088 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 2089 | { |
4db35314 | 2090 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
2091 | } |
2092 | ||
31aa2b44 | 2093 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2094 | { |
1e3f42f0 TY |
2095 | u64 *sptep; |
2096 | struct rmap_iterator iter; | |
a436036b | 2097 | |
1e3f42f0 TY |
2098 | while ((sptep = rmap_get_first(sp->parent_ptes, &iter))) |
2099 | drop_parent_pte(sp, sptep); | |
31aa2b44 AK |
2100 | } |
2101 | ||
60c8aec6 | 2102 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2103 | struct kvm_mmu_page *parent, |
2104 | struct list_head *invalid_list) | |
4731d4c7 | 2105 | { |
60c8aec6 MT |
2106 | int i, zapped = 0; |
2107 | struct mmu_page_path parents; | |
2108 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2109 | |
60c8aec6 | 2110 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2111 | return 0; |
60c8aec6 MT |
2112 | |
2113 | kvm_mmu_pages_init(parent, &parents, &pages); | |
2114 | while (mmu_unsync_walk(parent, &pages)) { | |
2115 | struct kvm_mmu_page *sp; | |
2116 | ||
2117 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2118 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2119 | mmu_pages_clear_parents(&parents); |
77662e00 | 2120 | zapped++; |
60c8aec6 | 2121 | } |
60c8aec6 MT |
2122 | kvm_mmu_pages_init(parent, &parents, &pages); |
2123 | } | |
2124 | ||
2125 | return zapped; | |
4731d4c7 MT |
2126 | } |
2127 | ||
7775834a XG |
2128 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2129 | struct list_head *invalid_list) | |
31aa2b44 | 2130 | { |
4731d4c7 | 2131 | int ret; |
f691fe1d | 2132 | |
7775834a | 2133 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2134 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 2135 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 2136 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 2137 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2138 | |
f6e2c02b | 2139 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 2140 | unaccount_shadowed(kvm, sp->gfn); |
5304b8d3 | 2141 | |
4731d4c7 MT |
2142 | if (sp->unsync) |
2143 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2144 | if (!sp->root_count) { |
54a4f023 GJ |
2145 | /* Count self */ |
2146 | ret++; | |
7775834a | 2147 | list_move(&sp->link, invalid_list); |
aa6bd187 | 2148 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2149 | } else { |
5b5c6a5a | 2150 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
05988d72 GN |
2151 | |
2152 | /* | |
2153 | * The obsolete pages can not be used on any vcpus. | |
2154 | * See the comments in kvm_mmu_invalidate_zap_all_pages(). | |
2155 | */ | |
2156 | if (!sp->role.invalid && !is_obsolete_sp(kvm, sp)) | |
2157 | kvm_reload_remote_mmus(kvm); | |
2e53d63a | 2158 | } |
7775834a XG |
2159 | |
2160 | sp->role.invalid = 1; | |
4731d4c7 | 2161 | return ret; |
a436036b AK |
2162 | } |
2163 | ||
7775834a XG |
2164 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2165 | struct list_head *invalid_list) | |
2166 | { | |
945315b9 | 2167 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2168 | |
2169 | if (list_empty(invalid_list)) | |
2170 | return; | |
2171 | ||
c142786c AK |
2172 | /* |
2173 | * wmb: make sure everyone sees our modifications to the page tables | |
2174 | * rmb: make sure we see changes to vcpu->mode | |
2175 | */ | |
2176 | smp_mb(); | |
4f022648 | 2177 | |
c142786c AK |
2178 | /* |
2179 | * Wait for all vcpus to exit guest mode and/or lockless shadow | |
2180 | * page table walks. | |
2181 | */ | |
2182 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2183 | |
945315b9 | 2184 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2185 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2186 | kvm_mmu_free_page(sp); |
945315b9 | 2187 | } |
7775834a XG |
2188 | } |
2189 | ||
5da59607 TY |
2190 | static bool prepare_zap_oldest_mmu_page(struct kvm *kvm, |
2191 | struct list_head *invalid_list) | |
2192 | { | |
2193 | struct kvm_mmu_page *sp; | |
2194 | ||
2195 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
2196 | return false; | |
2197 | ||
2198 | sp = list_entry(kvm->arch.active_mmu_pages.prev, | |
2199 | struct kvm_mmu_page, link); | |
2200 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); | |
2201 | ||
2202 | return true; | |
2203 | } | |
2204 | ||
82ce2c96 IE |
2205 | /* |
2206 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2207 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2208 | */ |
49d5ca26 | 2209 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 2210 | { |
d98ba053 | 2211 | LIST_HEAD(invalid_list); |
82ce2c96 | 2212 | |
b34cb590 TY |
2213 | spin_lock(&kvm->mmu_lock); |
2214 | ||
49d5ca26 | 2215 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
5da59607 TY |
2216 | /* Need to free some mmu pages to achieve the goal. */ |
2217 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) | |
2218 | if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list)) | |
2219 | break; | |
82ce2c96 | 2220 | |
aa6bd187 | 2221 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 2222 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2223 | } |
82ce2c96 | 2224 | |
49d5ca26 | 2225 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 TY |
2226 | |
2227 | spin_unlock(&kvm->mmu_lock); | |
82ce2c96 IE |
2228 | } |
2229 | ||
1cb3f3ae | 2230 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2231 | { |
4db35314 | 2232 | struct kvm_mmu_page *sp; |
d98ba053 | 2233 | LIST_HEAD(invalid_list); |
a436036b AK |
2234 | int r; |
2235 | ||
9ad17b10 | 2236 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2237 | r = 0; |
1cb3f3ae | 2238 | spin_lock(&kvm->mmu_lock); |
b67bfe0d | 2239 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2240 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2241 | sp->role.word); |
2242 | r = 1; | |
f41d335a | 2243 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2244 | } |
d98ba053 | 2245 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2246 | spin_unlock(&kvm->mmu_lock); |
2247 | ||
a436036b | 2248 | return r; |
cea0f0e7 | 2249 | } |
1cb3f3ae | 2250 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2251 | |
74be52e3 SY |
2252 | /* |
2253 | * The function is based on mtrr_type_lookup() in | |
2254 | * arch/x86/kernel/cpu/mtrr/generic.c | |
2255 | */ | |
2256 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
2257 | u64 start, u64 end) | |
2258 | { | |
2259 | int i; | |
2260 | u64 base, mask; | |
2261 | u8 prev_match, curr_match; | |
2262 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
2263 | ||
2264 | if (!mtrr_state->enabled) | |
2265 | return 0xFF; | |
2266 | ||
2267 | /* Make end inclusive end, instead of exclusive */ | |
2268 | end--; | |
2269 | ||
2270 | /* Look in fixed ranges. Just return the type as per start */ | |
2271 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
2272 | int idx; | |
2273 | ||
2274 | if (start < 0x80000) { | |
2275 | idx = 0; | |
2276 | idx += (start >> 16); | |
2277 | return mtrr_state->fixed_ranges[idx]; | |
2278 | } else if (start < 0xC0000) { | |
2279 | idx = 1 * 8; | |
2280 | idx += ((start - 0x80000) >> 14); | |
2281 | return mtrr_state->fixed_ranges[idx]; | |
2282 | } else if (start < 0x1000000) { | |
2283 | idx = 3 * 8; | |
2284 | idx += ((start - 0xC0000) >> 12); | |
2285 | return mtrr_state->fixed_ranges[idx]; | |
2286 | } | |
2287 | } | |
2288 | ||
2289 | /* | |
2290 | * Look in variable ranges | |
2291 | * Look of multiple ranges matching this address and pick type | |
2292 | * as per MTRR precedence | |
2293 | */ | |
2294 | if (!(mtrr_state->enabled & 2)) | |
2295 | return mtrr_state->def_type; | |
2296 | ||
2297 | prev_match = 0xFF; | |
2298 | for (i = 0; i < num_var_ranges; ++i) { | |
2299 | unsigned short start_state, end_state; | |
2300 | ||
2301 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
2302 | continue; | |
2303 | ||
2304 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
2305 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
2306 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
2307 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
2308 | ||
2309 | start_state = ((start & mask) == (base & mask)); | |
2310 | end_state = ((end & mask) == (base & mask)); | |
2311 | if (start_state != end_state) | |
2312 | return 0xFE; | |
2313 | ||
2314 | if ((start & mask) != (base & mask)) | |
2315 | continue; | |
2316 | ||
2317 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
2318 | if (prev_match == 0xFF) { | |
2319 | prev_match = curr_match; | |
2320 | continue; | |
2321 | } | |
2322 | ||
2323 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
2324 | curr_match == MTRR_TYPE_UNCACHABLE) | |
2325 | return MTRR_TYPE_UNCACHABLE; | |
2326 | ||
2327 | if ((prev_match == MTRR_TYPE_WRBACK && | |
2328 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
2329 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
2330 | curr_match == MTRR_TYPE_WRBACK)) { | |
2331 | prev_match = MTRR_TYPE_WRTHROUGH; | |
2332 | curr_match = MTRR_TYPE_WRTHROUGH; | |
2333 | } | |
2334 | ||
2335 | if (prev_match != curr_match) | |
2336 | return MTRR_TYPE_UNCACHABLE; | |
2337 | } | |
2338 | ||
2339 | if (prev_match != 0xFF) | |
2340 | return prev_match; | |
2341 | ||
2342 | return mtrr_state->def_type; | |
2343 | } | |
2344 | ||
4b12f0de | 2345 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
2346 | { |
2347 | u8 mtrr; | |
2348 | ||
2349 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
2350 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
2351 | if (mtrr == 0xfe || mtrr == 0xff) | |
2352 | mtrr = MTRR_TYPE_WRBACK; | |
2353 | return mtrr; | |
2354 | } | |
4b12f0de | 2355 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 2356 | |
9cf5cf5a XG |
2357 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
2358 | { | |
2359 | trace_kvm_mmu_unsync_page(sp); | |
2360 | ++vcpu->kvm->stat.mmu_unsync; | |
2361 | sp->unsync = 1; | |
2362 | ||
2363 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2364 | } |
2365 | ||
2366 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 2367 | { |
4731d4c7 | 2368 | struct kvm_mmu_page *s; |
9cf5cf5a | 2369 | |
b67bfe0d | 2370 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 2371 | if (s->unsync) |
4731d4c7 | 2372 | continue; |
9cf5cf5a XG |
2373 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
2374 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 2375 | } |
4731d4c7 MT |
2376 | } |
2377 | ||
2378 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
2379 | bool can_unsync) | |
2380 | { | |
9cf5cf5a | 2381 | struct kvm_mmu_page *s; |
9cf5cf5a XG |
2382 | bool need_unsync = false; |
2383 | ||
b67bfe0d | 2384 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
36a2e677 XG |
2385 | if (!can_unsync) |
2386 | return 1; | |
2387 | ||
9cf5cf5a | 2388 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2389 | return 1; |
9cf5cf5a | 2390 | |
9bb4f6b1 | 2391 | if (!s->unsync) |
9cf5cf5a | 2392 | need_unsync = true; |
4731d4c7 | 2393 | } |
9cf5cf5a XG |
2394 | if (need_unsync) |
2395 | kvm_unsync_pages(vcpu, gfn); | |
4731d4c7 MT |
2396 | return 0; |
2397 | } | |
2398 | ||
d555c333 | 2399 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
c2288505 | 2400 | unsigned pte_access, int level, |
c2d0ee46 | 2401 | gfn_t gfn, pfn_t pfn, bool speculative, |
9bdbba13 | 2402 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2403 | { |
6e7d0354 | 2404 | u64 spte; |
1e73f9dd | 2405 | int ret = 0; |
64d4d521 | 2406 | |
f2fd125d | 2407 | if (set_mmio_spte(vcpu->kvm, sptep, gfn, pfn, pte_access)) |
ce88decf XG |
2408 | return 0; |
2409 | ||
982c2565 | 2410 | spte = PT_PRESENT_MASK; |
947da538 | 2411 | if (!speculative) |
3201b5d9 | 2412 | spte |= shadow_accessed_mask; |
640d9b0d | 2413 | |
7b52345e SY |
2414 | if (pte_access & ACC_EXEC_MASK) |
2415 | spte |= shadow_x_mask; | |
2416 | else | |
2417 | spte |= shadow_nx_mask; | |
49fde340 | 2418 | |
1c4f1fd6 | 2419 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2420 | spte |= shadow_user_mask; |
49fde340 | 2421 | |
852e3c19 | 2422 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2423 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2424 | if (tdp_enabled) |
4b12f0de SY |
2425 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
2426 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 2427 | |
9bdbba13 | 2428 | if (host_writable) |
1403283a | 2429 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2430 | else |
2431 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2432 | |
35149e21 | 2433 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 | 2434 | |
c2288505 | 2435 | if (pte_access & ACC_WRITE_MASK) { |
1c4f1fd6 | 2436 | |
c2193463 | 2437 | /* |
7751babd XG |
2438 | * Other vcpu creates new sp in the window between |
2439 | * mapping_level() and acquiring mmu-lock. We can | |
2440 | * allow guest to retry the access, the mapping can | |
2441 | * be fixed if guest refault. | |
c2193463 | 2442 | */ |
852e3c19 | 2443 | if (level > PT_PAGE_TABLE_LEVEL && |
c2193463 | 2444 | has_wrprotected_page(vcpu->kvm, gfn, level)) |
be38d276 | 2445 | goto done; |
38187c83 | 2446 | |
49fde340 | 2447 | spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE; |
1c4f1fd6 | 2448 | |
ecc5589f MT |
2449 | /* |
2450 | * Optimization: for pte sync, if spte was writable the hash | |
2451 | * lookup is unnecessary (and expensive). Write protection | |
2452 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2453 | * Same reasoning can be applied to dirty page accounting. | |
2454 | */ | |
8dae4445 | 2455 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2456 | goto set_pte; |
2457 | ||
4731d4c7 | 2458 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2459 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2460 | __func__, gfn); |
1e73f9dd | 2461 | ret = 1; |
1c4f1fd6 | 2462 | pte_access &= ~ACC_WRITE_MASK; |
49fde340 | 2463 | spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE); |
1c4f1fd6 AK |
2464 | } |
2465 | } | |
2466 | ||
1c4f1fd6 AK |
2467 | if (pte_access & ACC_WRITE_MASK) |
2468 | mark_page_dirty(vcpu->kvm, gfn); | |
2469 | ||
38187c83 | 2470 | set_pte: |
6e7d0354 | 2471 | if (mmu_spte_update(sptep, spte)) |
b330aa0c | 2472 | kvm_flush_remote_tlbs(vcpu->kvm); |
be38d276 | 2473 | done: |
1e73f9dd MT |
2474 | return ret; |
2475 | } | |
2476 | ||
d555c333 | 2477 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
f7616203 XG |
2478 | unsigned pte_access, int write_fault, int *emulate, |
2479 | int level, gfn_t gfn, pfn_t pfn, bool speculative, | |
2480 | bool host_writable) | |
1e73f9dd MT |
2481 | { |
2482 | int was_rmapped = 0; | |
53a27b39 | 2483 | int rmap_count; |
1e73f9dd | 2484 | |
f7616203 XG |
2485 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
2486 | *sptep, write_fault, gfn); | |
1e73f9dd | 2487 | |
d555c333 | 2488 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
2489 | /* |
2490 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2491 | * the parent of the now unreachable PTE. | |
2492 | */ | |
852e3c19 JR |
2493 | if (level > PT_PAGE_TABLE_LEVEL && |
2494 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2495 | struct kvm_mmu_page *child; |
d555c333 | 2496 | u64 pte = *sptep; |
1e73f9dd MT |
2497 | |
2498 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 2499 | drop_parent_pte(child, sptep); |
3be2264b | 2500 | kvm_flush_remote_tlbs(vcpu->kvm); |
d555c333 | 2501 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2502 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2503 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2504 | drop_spte(vcpu->kvm, sptep); |
91546356 | 2505 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2506 | } else |
2507 | was_rmapped = 1; | |
1e73f9dd | 2508 | } |
852e3c19 | 2509 | |
c2288505 XG |
2510 | if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative, |
2511 | true, host_writable)) { | |
1e73f9dd | 2512 | if (write_fault) |
b90a0e6c | 2513 | *emulate = 1; |
5304efde | 2514 | kvm_mmu_flush_tlb(vcpu); |
a378b4e6 | 2515 | } |
1e73f9dd | 2516 | |
ce88decf XG |
2517 | if (unlikely(is_mmio_spte(*sptep) && emulate)) |
2518 | *emulate = 1; | |
2519 | ||
d555c333 | 2520 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2521 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2522 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
2523 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
2524 | *sptep, sptep); | |
d555c333 | 2525 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2526 | ++vcpu->kvm->stat.lpages; |
2527 | ||
ffb61bb3 | 2528 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
2529 | if (!was_rmapped) { |
2530 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2531 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2532 | rmap_recycle(vcpu, sptep, gfn); | |
2533 | } | |
1c4f1fd6 | 2534 | } |
cb9aaa30 | 2535 | |
f3ac1a4b | 2536 | kvm_release_pfn_clean(pfn); |
1c4f1fd6 AK |
2537 | } |
2538 | ||
6aa8b732 AK |
2539 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
2540 | { | |
e676505a | 2541 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2542 | } |
2543 | ||
a052b42b XG |
2544 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) |
2545 | { | |
2546 | int bit7; | |
2547 | ||
2548 | bit7 = (gpte >> 7) & 1; | |
2549 | return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0; | |
2550 | } | |
2551 | ||
957ed9ef XG |
2552 | static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
2553 | bool no_dirty_log) | |
2554 | { | |
2555 | struct kvm_memory_slot *slot; | |
957ed9ef | 2556 | |
5d163b1c | 2557 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 2558 | if (!slot) |
6c8ee57b | 2559 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 2560 | |
037d92dc | 2561 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
2562 | } |
2563 | ||
a052b42b XG |
2564 | static bool prefetch_invalid_gpte(struct kvm_vcpu *vcpu, |
2565 | struct kvm_mmu_page *sp, u64 *spte, | |
2566 | u64 gpte) | |
2567 | { | |
2568 | if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) | |
2569 | goto no_present; | |
2570 | ||
2571 | if (!is_present_gpte(gpte)) | |
2572 | goto no_present; | |
2573 | ||
2574 | if (!(gpte & PT_ACCESSED_MASK)) | |
2575 | goto no_present; | |
2576 | ||
2577 | return false; | |
2578 | ||
2579 | no_present: | |
2580 | drop_spte(vcpu->kvm, spte); | |
2581 | return true; | |
2582 | } | |
2583 | ||
957ed9ef XG |
2584 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, |
2585 | struct kvm_mmu_page *sp, | |
2586 | u64 *start, u64 *end) | |
2587 | { | |
2588 | struct page *pages[PTE_PREFETCH_NUM]; | |
2589 | unsigned access = sp->role.access; | |
2590 | int i, ret; | |
2591 | gfn_t gfn; | |
2592 | ||
2593 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
5d163b1c | 2594 | if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK)) |
957ed9ef XG |
2595 | return -1; |
2596 | ||
2597 | ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start); | |
2598 | if (ret <= 0) | |
2599 | return -1; | |
2600 | ||
2601 | for (i = 0; i < ret; i++, gfn++, start++) | |
f7616203 | 2602 | mmu_set_spte(vcpu, start, access, 0, NULL, |
c2288505 XG |
2603 | sp->role.level, gfn, page_to_pfn(pages[i]), |
2604 | true, true); | |
957ed9ef XG |
2605 | |
2606 | return 0; | |
2607 | } | |
2608 | ||
2609 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2610 | struct kvm_mmu_page *sp, u64 *sptep) | |
2611 | { | |
2612 | u64 *spte, *start = NULL; | |
2613 | int i; | |
2614 | ||
2615 | WARN_ON(!sp->role.direct); | |
2616 | ||
2617 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2618 | spte = sp->spt + i; | |
2619 | ||
2620 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2621 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2622 | if (!start) |
2623 | continue; | |
2624 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2625 | break; | |
2626 | start = NULL; | |
2627 | } else if (!start) | |
2628 | start = spte; | |
2629 | } | |
2630 | } | |
2631 | ||
2632 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2633 | { | |
2634 | struct kvm_mmu_page *sp; | |
2635 | ||
2636 | /* | |
2637 | * Since it's no accessed bit on EPT, it's no way to | |
2638 | * distinguish between actually accessed translations | |
2639 | * and prefetched, so disable pte prefetch if EPT is | |
2640 | * enabled. | |
2641 | */ | |
2642 | if (!shadow_accessed_mask) | |
2643 | return; | |
2644 | ||
2645 | sp = page_header(__pa(sptep)); | |
2646 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2647 | return; | |
2648 | ||
2649 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2650 | } | |
2651 | ||
9f652d21 | 2652 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
2ec4739d XG |
2653 | int map_writable, int level, gfn_t gfn, pfn_t pfn, |
2654 | bool prefault) | |
140754bc | 2655 | { |
9f652d21 | 2656 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2657 | struct kvm_mmu_page *sp; |
b90a0e6c | 2658 | int emulate = 0; |
140754bc | 2659 | gfn_t pseudo_gfn; |
6aa8b732 | 2660 | |
9f652d21 | 2661 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2662 | if (iterator.level == level) { |
f7616203 | 2663 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, |
c2288505 XG |
2664 | write, &emulate, level, gfn, pfn, |
2665 | prefault, map_writable); | |
957ed9ef | 2666 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2667 | ++vcpu->stat.pf_fixed; |
2668 | break; | |
6aa8b732 AK |
2669 | } |
2670 | ||
c3707958 | 2671 | if (!is_shadow_present_pte(*iterator.sptep)) { |
c9fa0b3b LJ |
2672 | u64 base_addr = iterator.addr; |
2673 | ||
2674 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2675 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 AK |
2676 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
2677 | iterator.level - 1, | |
2678 | 1, ACC_ALL, iterator.sptep); | |
140754bc | 2679 | |
24db2734 | 2680 | link_shadow_page(iterator.sptep, sp); |
9f652d21 AK |
2681 | } |
2682 | } | |
b90a0e6c | 2683 | return emulate; |
6aa8b732 AK |
2684 | } |
2685 | ||
77db5cbd | 2686 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2687 | { |
77db5cbd HY |
2688 | siginfo_t info; |
2689 | ||
2690 | info.si_signo = SIGBUS; | |
2691 | info.si_errno = 0; | |
2692 | info.si_code = BUS_MCEERR_AR; | |
2693 | info.si_addr = (void __user *)address; | |
2694 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 2695 | |
77db5cbd | 2696 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
2697 | } |
2698 | ||
d7c55201 | 2699 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn) |
bf998156 | 2700 | { |
4d8b81ab XG |
2701 | /* |
2702 | * Do not cache the mmio info caused by writing the readonly gfn | |
2703 | * into the spte otherwise read access on readonly gfn also can | |
2704 | * caused mmio page fault and treat it as mmio access. | |
2705 | * Return 1 to tell kvm to emulate it. | |
2706 | */ | |
2707 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
2708 | return 1; | |
2709 | ||
e6c1502b | 2710 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
bebb106a | 2711 | kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current); |
bf998156 | 2712 | return 0; |
d7c55201 | 2713 | } |
edba23e5 | 2714 | |
d7c55201 | 2715 | return -EFAULT; |
bf998156 HY |
2716 | } |
2717 | ||
936a5fe6 AA |
2718 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
2719 | gfn_t *gfnp, pfn_t *pfnp, int *levelp) | |
2720 | { | |
2721 | pfn_t pfn = *pfnp; | |
2722 | gfn_t gfn = *gfnp; | |
2723 | int level = *levelp; | |
2724 | ||
2725 | /* | |
2726 | * Check if it's a transparent hugepage. If this would be an | |
2727 | * hugetlbfs page, level wouldn't be set to | |
2728 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
2729 | * here. | |
2730 | */ | |
81c52c56 | 2731 | if (!is_error_noslot_pfn(pfn) && !kvm_is_mmio_pfn(pfn) && |
936a5fe6 AA |
2732 | level == PT_PAGE_TABLE_LEVEL && |
2733 | PageTransCompound(pfn_to_page(pfn)) && | |
2734 | !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) { | |
2735 | unsigned long mask; | |
2736 | /* | |
2737 | * mmu_notifier_retry was successful and we hold the | |
2738 | * mmu_lock here, so the pmd can't become splitting | |
2739 | * from under us, and in turn | |
2740 | * __split_huge_page_refcount() can't run from under | |
2741 | * us and we can safely transfer the refcount from | |
2742 | * PG_tail to PG_head as we switch the pfn to tail to | |
2743 | * head. | |
2744 | */ | |
2745 | *levelp = level = PT_DIRECTORY_LEVEL; | |
2746 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
2747 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2748 | if (pfn & mask) { | |
2749 | gfn &= ~mask; | |
2750 | *gfnp = gfn; | |
2751 | kvm_release_pfn_clean(pfn); | |
2752 | pfn &= ~mask; | |
c3586667 | 2753 | kvm_get_pfn(pfn); |
936a5fe6 AA |
2754 | *pfnp = pfn; |
2755 | } | |
2756 | } | |
2757 | } | |
2758 | ||
d7c55201 XG |
2759 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
2760 | pfn_t pfn, unsigned access, int *ret_val) | |
2761 | { | |
2762 | bool ret = true; | |
2763 | ||
2764 | /* The pfn is invalid, report the error! */ | |
81c52c56 | 2765 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 XG |
2766 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
2767 | goto exit; | |
2768 | } | |
2769 | ||
ce88decf | 2770 | if (unlikely(is_noslot_pfn(pfn))) |
d7c55201 | 2771 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); |
d7c55201 XG |
2772 | |
2773 | ret = false; | |
2774 | exit: | |
2775 | return ret; | |
2776 | } | |
2777 | ||
c7ba5b48 XG |
2778 | static bool page_fault_can_be_fast(struct kvm_vcpu *vcpu, u32 error_code) |
2779 | { | |
2780 | /* | |
2781 | * #PF can be fast only if the shadow page table is present and it | |
2782 | * is caused by write-protect, that means we just need change the | |
2783 | * W bit of the spte which can be done out of mmu-lock. | |
2784 | */ | |
2785 | if (!(error_code & PFERR_PRESENT_MASK) || | |
2786 | !(error_code & PFERR_WRITE_MASK)) | |
2787 | return false; | |
2788 | ||
2789 | return true; | |
2790 | } | |
2791 | ||
2792 | static bool | |
2793 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 spte) | |
2794 | { | |
2795 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
2796 | gfn_t gfn; | |
2797 | ||
2798 | WARN_ON(!sp->role.direct); | |
2799 | ||
2800 | /* | |
2801 | * The gfn of direct spte is stable since it is calculated | |
2802 | * by sp->gfn. | |
2803 | */ | |
2804 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
2805 | ||
2806 | if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte) | |
2807 | mark_page_dirty(vcpu->kvm, gfn); | |
2808 | ||
2809 | return true; | |
2810 | } | |
2811 | ||
2812 | /* | |
2813 | * Return value: | |
2814 | * - true: let the vcpu to access on the same address again. | |
2815 | * - false: let the real page fault path to fix it. | |
2816 | */ | |
2817 | static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, | |
2818 | u32 error_code) | |
2819 | { | |
2820 | struct kvm_shadow_walk_iterator iterator; | |
2821 | bool ret = false; | |
2822 | u64 spte = 0ull; | |
2823 | ||
2824 | if (!page_fault_can_be_fast(vcpu, error_code)) | |
2825 | return false; | |
2826 | ||
2827 | walk_shadow_page_lockless_begin(vcpu); | |
2828 | for_each_shadow_entry_lockless(vcpu, gva, iterator, spte) | |
2829 | if (!is_shadow_present_pte(spte) || iterator.level < level) | |
2830 | break; | |
2831 | ||
2832 | /* | |
2833 | * If the mapping has been changed, let the vcpu fault on the | |
2834 | * same address again. | |
2835 | */ | |
2836 | if (!is_rmap_spte(spte)) { | |
2837 | ret = true; | |
2838 | goto exit; | |
2839 | } | |
2840 | ||
2841 | if (!is_last_spte(spte, level)) | |
2842 | goto exit; | |
2843 | ||
2844 | /* | |
2845 | * Check if it is a spurious fault caused by TLB lazily flushed. | |
2846 | * | |
2847 | * Need not check the access of upper level table entries since | |
2848 | * they are always ACC_ALL. | |
2849 | */ | |
2850 | if (is_writable_pte(spte)) { | |
2851 | ret = true; | |
2852 | goto exit; | |
2853 | } | |
2854 | ||
2855 | /* | |
2856 | * Currently, to simplify the code, only the spte write-protected | |
2857 | * by dirty-log can be fast fixed. | |
2858 | */ | |
2859 | if (!spte_is_locklessly_modifiable(spte)) | |
2860 | goto exit; | |
2861 | ||
2862 | /* | |
2863 | * Currently, fast page fault only works for direct mapping since | |
2864 | * the gfn is not stable for indirect shadow page. | |
2865 | * See Documentation/virtual/kvm/locking.txt to get more detail. | |
2866 | */ | |
2867 | ret = fast_pf_fix_direct_spte(vcpu, iterator.sptep, spte); | |
2868 | exit: | |
a72faf25 XG |
2869 | trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep, |
2870 | spte, ret); | |
c7ba5b48 XG |
2871 | walk_shadow_page_lockless_end(vcpu); |
2872 | ||
2873 | return ret; | |
2874 | } | |
2875 | ||
78b2c54a | 2876 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
060c2abe | 2877 | gva_t gva, pfn_t *pfn, bool write, bool *writable); |
450e0b41 | 2878 | static void make_mmu_pages_available(struct kvm_vcpu *vcpu); |
060c2abe | 2879 | |
c7ba5b48 XG |
2880 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code, |
2881 | gfn_t gfn, bool prefault) | |
10589a46 MT |
2882 | { |
2883 | int r; | |
852e3c19 | 2884 | int level; |
936a5fe6 | 2885 | int force_pt_level; |
35149e21 | 2886 | pfn_t pfn; |
e930bffe | 2887 | unsigned long mmu_seq; |
c7ba5b48 | 2888 | bool map_writable, write = error_code & PFERR_WRITE_MASK; |
aaee2c94 | 2889 | |
936a5fe6 AA |
2890 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
2891 | if (likely(!force_pt_level)) { | |
2892 | level = mapping_level(vcpu, gfn); | |
2893 | /* | |
2894 | * This path builds a PAE pagetable - so we can map | |
2895 | * 2mb pages at maximum. Therefore check if the level | |
2896 | * is larger than that. | |
2897 | */ | |
2898 | if (level > PT_DIRECTORY_LEVEL) | |
2899 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 2900 | |
936a5fe6 AA |
2901 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
2902 | } else | |
2903 | level = PT_PAGE_TABLE_LEVEL; | |
05da4558 | 2904 | |
c7ba5b48 XG |
2905 | if (fast_page_fault(vcpu, v, level, error_code)) |
2906 | return 0; | |
2907 | ||
e930bffe | 2908 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2909 | smp_rmb(); |
060c2abe | 2910 | |
78b2c54a | 2911 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
060c2abe | 2912 | return 0; |
aaee2c94 | 2913 | |
d7c55201 XG |
2914 | if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r)) |
2915 | return r; | |
d196e343 | 2916 | |
aaee2c94 | 2917 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 2918 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 2919 | goto out_unlock; |
450e0b41 | 2920 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
2921 | if (likely(!force_pt_level)) |
2922 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
2ec4739d XG |
2923 | r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn, |
2924 | prefault); | |
aaee2c94 MT |
2925 | spin_unlock(&vcpu->kvm->mmu_lock); |
2926 | ||
aaee2c94 | 2927 | |
10589a46 | 2928 | return r; |
e930bffe AA |
2929 | |
2930 | out_unlock: | |
2931 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2932 | kvm_release_pfn_clean(pfn); | |
2933 | return 0; | |
10589a46 MT |
2934 | } |
2935 | ||
2936 | ||
17ac10ad AK |
2937 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
2938 | { | |
2939 | int i; | |
4db35314 | 2940 | struct kvm_mmu_page *sp; |
d98ba053 | 2941 | LIST_HEAD(invalid_list); |
17ac10ad | 2942 | |
ad312c7c | 2943 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 2944 | return; |
35af577a | 2945 | |
81407ca5 JR |
2946 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL && |
2947 | (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL || | |
2948 | vcpu->arch.mmu.direct_map)) { | |
ad312c7c | 2949 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 2950 | |
35af577a | 2951 | spin_lock(&vcpu->kvm->mmu_lock); |
4db35314 AK |
2952 | sp = page_header(root); |
2953 | --sp->root_count; | |
d98ba053 XG |
2954 | if (!sp->root_count && sp->role.invalid) { |
2955 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
2956 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
2957 | } | |
aaee2c94 | 2958 | spin_unlock(&vcpu->kvm->mmu_lock); |
35af577a | 2959 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2960 | return; |
2961 | } | |
35af577a GN |
2962 | |
2963 | spin_lock(&vcpu->kvm->mmu_lock); | |
17ac10ad | 2964 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2965 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2966 | |
417726a3 | 2967 | if (root) { |
417726a3 | 2968 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2969 | sp = page_header(root); |
2970 | --sp->root_count; | |
2e53d63a | 2971 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
2972 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2973 | &invalid_list); | |
417726a3 | 2974 | } |
ad312c7c | 2975 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2976 | } |
d98ba053 | 2977 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 2978 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2979 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2980 | } |
2981 | ||
8986ecc0 MT |
2982 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2983 | { | |
2984 | int ret = 0; | |
2985 | ||
2986 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 2987 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
2988 | ret = 1; |
2989 | } | |
2990 | ||
2991 | return ret; | |
2992 | } | |
2993 | ||
651dd37a JR |
2994 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
2995 | { | |
2996 | struct kvm_mmu_page *sp; | |
7ebaf15e | 2997 | unsigned i; |
651dd37a JR |
2998 | |
2999 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3000 | spin_lock(&vcpu->kvm->mmu_lock); | |
450e0b41 | 3001 | make_mmu_pages_available(vcpu); |
651dd37a JR |
3002 | sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, |
3003 | 1, ACC_ALL, NULL); | |
3004 | ++sp->root_count; | |
3005 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3006 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
3007 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
3008 | for (i = 0; i < 4; ++i) { | |
3009 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3010 | ||
3011 | ASSERT(!VALID_PAGE(root)); | |
3012 | spin_lock(&vcpu->kvm->mmu_lock); | |
450e0b41 | 3013 | make_mmu_pages_available(vcpu); |
649497d1 AK |
3014 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
3015 | i << 30, | |
651dd37a JR |
3016 | PT32_ROOT_LEVEL, 1, ACC_ALL, |
3017 | NULL); | |
3018 | root = __pa(sp->spt); | |
3019 | ++sp->root_count; | |
3020 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3021 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 3022 | } |
6292757f | 3023 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
3024 | } else |
3025 | BUG(); | |
3026 | ||
3027 | return 0; | |
3028 | } | |
3029 | ||
3030 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 3031 | { |
4db35314 | 3032 | struct kvm_mmu_page *sp; |
81407ca5 JR |
3033 | u64 pdptr, pm_mask; |
3034 | gfn_t root_gfn; | |
3035 | int i; | |
3bb65a22 | 3036 | |
5777ed34 | 3037 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 3038 | |
651dd37a JR |
3039 | if (mmu_check_root(vcpu, root_gfn)) |
3040 | return 1; | |
3041 | ||
3042 | /* | |
3043 | * Do we shadow a long mode page table? If so we need to | |
3044 | * write-protect the guests page table root. | |
3045 | */ | |
3046 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { | |
ad312c7c | 3047 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad AK |
3048 | |
3049 | ASSERT(!VALID_PAGE(root)); | |
651dd37a | 3050 | |
8facbbff | 3051 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3052 | make_mmu_pages_available(vcpu); |
651dd37a JR |
3053 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, |
3054 | 0, ACC_ALL, NULL); | |
4db35314 AK |
3055 | root = __pa(sp->spt); |
3056 | ++sp->root_count; | |
8facbbff | 3057 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 3058 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 3059 | return 0; |
17ac10ad | 3060 | } |
f87f9288 | 3061 | |
651dd37a JR |
3062 | /* |
3063 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3064 | * or a PAE 3-level page table. In either case we need to be aware that |
3065 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3066 | */ |
81407ca5 JR |
3067 | pm_mask = PT_PRESENT_MASK; |
3068 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) | |
3069 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; | |
3070 | ||
17ac10ad | 3071 | for (i = 0; i < 4; ++i) { |
ad312c7c | 3072 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
3073 | |
3074 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 3075 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 3076 | pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i); |
43a3795a | 3077 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 3078 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
3079 | continue; |
3080 | } | |
6de4f3ad | 3081 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
3082 | if (mmu_check_root(vcpu, root_gfn)) |
3083 | return 1; | |
5a7388c2 | 3084 | } |
8facbbff | 3085 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3086 | make_mmu_pages_available(vcpu); |
4db35314 | 3087 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
651dd37a | 3088 | PT32_ROOT_LEVEL, 0, |
f7d9c7b7 | 3089 | ACC_ALL, NULL); |
4db35314 AK |
3090 | root = __pa(sp->spt); |
3091 | ++sp->root_count; | |
8facbbff AK |
3092 | spin_unlock(&vcpu->kvm->mmu_lock); |
3093 | ||
81407ca5 | 3094 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 3095 | } |
6292757f | 3096 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3097 | |
3098 | /* | |
3099 | * If we shadow a 32 bit page table with a long mode page | |
3100 | * table we enter this path. | |
3101 | */ | |
3102 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3103 | if (vcpu->arch.mmu.lm_root == NULL) { | |
3104 | /* | |
3105 | * The additional page necessary for this is only | |
3106 | * allocated on demand. | |
3107 | */ | |
3108 | ||
3109 | u64 *lm_root; | |
3110 | ||
3111 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
3112 | if (lm_root == NULL) | |
3113 | return 1; | |
3114 | ||
3115 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
3116 | ||
3117 | vcpu->arch.mmu.lm_root = lm_root; | |
3118 | } | |
3119 | ||
3120 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
3121 | } | |
3122 | ||
8986ecc0 | 3123 | return 0; |
17ac10ad AK |
3124 | } |
3125 | ||
651dd37a JR |
3126 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
3127 | { | |
3128 | if (vcpu->arch.mmu.direct_map) | |
3129 | return mmu_alloc_direct_roots(vcpu); | |
3130 | else | |
3131 | return mmu_alloc_shadow_roots(vcpu); | |
3132 | } | |
3133 | ||
0ba73cda MT |
3134 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
3135 | { | |
3136 | int i; | |
3137 | struct kvm_mmu_page *sp; | |
3138 | ||
81407ca5 JR |
3139 | if (vcpu->arch.mmu.direct_map) |
3140 | return; | |
3141 | ||
0ba73cda MT |
3142 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3143 | return; | |
6903074c | 3144 | |
bebb106a | 3145 | vcpu_clear_mmio_info(vcpu, ~0ul); |
0375f7fa | 3146 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
81407ca5 | 3147 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { |
0ba73cda MT |
3148 | hpa_t root = vcpu->arch.mmu.root_hpa; |
3149 | sp = page_header(root); | |
3150 | mmu_sync_children(vcpu, sp); | |
0375f7fa | 3151 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3152 | return; |
3153 | } | |
3154 | for (i = 0; i < 4; ++i) { | |
3155 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3156 | ||
8986ecc0 | 3157 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
3158 | root &= PT64_BASE_ADDR_MASK; |
3159 | sp = page_header(root); | |
3160 | mmu_sync_children(vcpu, sp); | |
3161 | } | |
3162 | } | |
0375f7fa | 3163 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3164 | } |
3165 | ||
3166 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
3167 | { | |
3168 | spin_lock(&vcpu->kvm->mmu_lock); | |
3169 | mmu_sync_roots(vcpu); | |
6cffe8ca | 3170 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3171 | } |
3172 | ||
1871c602 | 3173 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 3174 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3175 | { |
ab9ae313 AK |
3176 | if (exception) |
3177 | exception->error_code = 0; | |
6aa8b732 AK |
3178 | return vaddr; |
3179 | } | |
3180 | ||
6539e738 | 3181 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
3182 | u32 access, |
3183 | struct x86_exception *exception) | |
6539e738 | 3184 | { |
ab9ae313 AK |
3185 | if (exception) |
3186 | exception->error_code = 0; | |
6539e738 JR |
3187 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access); |
3188 | } | |
3189 | ||
ce88decf XG |
3190 | static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
3191 | { | |
3192 | if (direct) | |
3193 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3194 | ||
3195 | return vcpu_match_mmio_gva(vcpu, addr); | |
3196 | } | |
3197 | ||
3198 | ||
3199 | /* | |
3200 | * On direct hosts, the last spte is only allows two states | |
3201 | * for mmio page fault: | |
3202 | * - It is the mmio spte | |
3203 | * - It is zapped or it is being zapped. | |
3204 | * | |
3205 | * This function completely checks the spte when the last spte | |
3206 | * is not the mmio spte. | |
3207 | */ | |
3208 | static bool check_direct_spte_mmio_pf(u64 spte) | |
3209 | { | |
3210 | return __check_direct_spte_mmio_pf(spte); | |
3211 | } | |
3212 | ||
3213 | static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr) | |
3214 | { | |
3215 | struct kvm_shadow_walk_iterator iterator; | |
3216 | u64 spte = 0ull; | |
3217 | ||
3218 | walk_shadow_page_lockless_begin(vcpu); | |
3219 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) | |
3220 | if (!is_shadow_present_pte(spte)) | |
3221 | break; | |
3222 | walk_shadow_page_lockless_end(vcpu); | |
3223 | ||
3224 | return spte; | |
3225 | } | |
3226 | ||
3227 | /* | |
3228 | * If it is a real mmio page fault, return 1 and emulat the instruction | |
3229 | * directly, return 0 to let CPU fault again on the address, -1 is | |
3230 | * returned if bug is detected. | |
3231 | */ | |
3232 | int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct) | |
3233 | { | |
3234 | u64 spte; | |
3235 | ||
3236 | if (quickly_check_mmio_pf(vcpu, addr, direct)) | |
3237 | return 1; | |
3238 | ||
3239 | spte = walk_shadow_page_get_mmio_spte(vcpu, addr); | |
3240 | ||
3241 | if (is_mmio_spte(spte)) { | |
3242 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
3243 | unsigned access = get_mmio_spte_access(spte); | |
3244 | ||
3245 | if (direct) | |
3246 | addr = 0; | |
4f022648 XG |
3247 | |
3248 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf XG |
3249 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
3250 | return 1; | |
3251 | } | |
3252 | ||
3253 | /* | |
3254 | * It's ok if the gva is remapped by other cpus on shadow guest, | |
3255 | * it's a BUG if the gfn is not a mmio page. | |
3256 | */ | |
3257 | if (direct && !check_direct_spte_mmio_pf(spte)) | |
3258 | return -1; | |
3259 | ||
3260 | /* | |
3261 | * If the page table is zapped by other cpus, let CPU fault again on | |
3262 | * the address. | |
3263 | */ | |
3264 | return 0; | |
3265 | } | |
3266 | EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common); | |
3267 | ||
3268 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, | |
3269 | u32 error_code, bool direct) | |
3270 | { | |
3271 | int ret; | |
3272 | ||
3273 | ret = handle_mmio_page_fault_common(vcpu, addr, direct); | |
3274 | WARN_ON(ret < 0); | |
3275 | return ret; | |
3276 | } | |
3277 | ||
6aa8b732 | 3278 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 3279 | u32 error_code, bool prefault) |
6aa8b732 | 3280 | { |
e833240f | 3281 | gfn_t gfn; |
e2dec939 | 3282 | int r; |
6aa8b732 | 3283 | |
b8688d51 | 3284 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
ce88decf XG |
3285 | |
3286 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3287 | return handle_mmio_page_fault(vcpu, gva, error_code, true); | |
3288 | ||
e2dec939 AK |
3289 | r = mmu_topup_memory_caches(vcpu); |
3290 | if (r) | |
3291 | return r; | |
714b93da | 3292 | |
6aa8b732 | 3293 | ASSERT(vcpu); |
ad312c7c | 3294 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3295 | |
e833240f | 3296 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 3297 | |
e833240f | 3298 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
c7ba5b48 | 3299 | error_code, gfn, prefault); |
6aa8b732 AK |
3300 | } |
3301 | ||
7e1fbeac | 3302 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
3303 | { |
3304 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3305 | |
7c90705b | 3306 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3307 | arch.gfn = gfn; |
c4806acd | 3308 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 3309 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 GN |
3310 | |
3311 | return kvm_setup_async_pf(vcpu, gva, gfn, &arch); | |
3312 | } | |
3313 | ||
3314 | static bool can_do_async_pf(struct kvm_vcpu *vcpu) | |
3315 | { | |
3316 | if (unlikely(!irqchip_in_kernel(vcpu->kvm) || | |
3317 | kvm_event_needs_reinjection(vcpu))) | |
3318 | return false; | |
3319 | ||
3320 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
3321 | } | |
3322 | ||
78b2c54a | 3323 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
612819c3 | 3324 | gva_t gva, pfn_t *pfn, bool write, bool *writable) |
af585b92 GN |
3325 | { |
3326 | bool async; | |
3327 | ||
612819c3 | 3328 | *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable); |
af585b92 GN |
3329 | |
3330 | if (!async) | |
3331 | return false; /* *pfn has correct page already */ | |
3332 | ||
78b2c54a | 3333 | if (!prefault && can_do_async_pf(vcpu)) { |
c9b263d2 | 3334 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
3335 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
3336 | trace_kvm_async_pf_doublefault(gva, gfn); | |
3337 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
3338 | return true; | |
3339 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
3340 | return true; | |
3341 | } | |
3342 | ||
612819c3 | 3343 | *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable); |
af585b92 GN |
3344 | |
3345 | return false; | |
3346 | } | |
3347 | ||
56028d08 | 3348 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 3349 | bool prefault) |
fb72d167 | 3350 | { |
35149e21 | 3351 | pfn_t pfn; |
fb72d167 | 3352 | int r; |
852e3c19 | 3353 | int level; |
936a5fe6 | 3354 | int force_pt_level; |
05da4558 | 3355 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 3356 | unsigned long mmu_seq; |
612819c3 MT |
3357 | int write = error_code & PFERR_WRITE_MASK; |
3358 | bool map_writable; | |
fb72d167 JR |
3359 | |
3360 | ASSERT(vcpu); | |
3361 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
3362 | ||
ce88decf XG |
3363 | if (unlikely(error_code & PFERR_RSVD_MASK)) |
3364 | return handle_mmio_page_fault(vcpu, gpa, error_code, true); | |
3365 | ||
fb72d167 JR |
3366 | r = mmu_topup_memory_caches(vcpu); |
3367 | if (r) | |
3368 | return r; | |
3369 | ||
936a5fe6 AA |
3370 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
3371 | if (likely(!force_pt_level)) { | |
3372 | level = mapping_level(vcpu, gfn); | |
3373 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
3374 | } else | |
3375 | level = PT_PAGE_TABLE_LEVEL; | |
852e3c19 | 3376 | |
c7ba5b48 XG |
3377 | if (fast_page_fault(vcpu, gpa, level, error_code)) |
3378 | return 0; | |
3379 | ||
e930bffe | 3380 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3381 | smp_rmb(); |
af585b92 | 3382 | |
78b2c54a | 3383 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
af585b92 GN |
3384 | return 0; |
3385 | ||
d7c55201 XG |
3386 | if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r)) |
3387 | return r; | |
3388 | ||
fb72d167 | 3389 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3390 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3391 | goto out_unlock; |
450e0b41 | 3392 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
3393 | if (likely(!force_pt_level)) |
3394 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
612819c3 | 3395 | r = __direct_map(vcpu, gpa, write, map_writable, |
2ec4739d | 3396 | level, gfn, pfn, prefault); |
fb72d167 | 3397 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
3398 | |
3399 | return r; | |
e930bffe AA |
3400 | |
3401 | out_unlock: | |
3402 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3403 | kvm_release_pfn_clean(pfn); | |
3404 | return 0; | |
fb72d167 JR |
3405 | } |
3406 | ||
6aa8b732 AK |
3407 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
3408 | { | |
17ac10ad | 3409 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3410 | } |
3411 | ||
52fde8df JR |
3412 | static int nonpaging_init_context(struct kvm_vcpu *vcpu, |
3413 | struct kvm_mmu *context) | |
6aa8b732 | 3414 | { |
6aa8b732 AK |
3415 | context->new_cr3 = nonpaging_new_cr3; |
3416 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
3417 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
3418 | context->free = nonpaging_free; | |
e8bc217a | 3419 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3420 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3421 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 3422 | context->root_level = 0; |
6aa8b732 | 3423 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3424 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3425 | context->direct_map = true; |
2d48a985 | 3426 | context->nx = false; |
6aa8b732 AK |
3427 | return 0; |
3428 | } | |
3429 | ||
d835dfec | 3430 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 3431 | { |
1165f5fe | 3432 | ++vcpu->stat.tlb_flush; |
a8eeb04a | 3433 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
6aa8b732 AK |
3434 | } |
3435 | ||
3436 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
3437 | { | |
9f8fe504 | 3438 | pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu)); |
cea0f0e7 | 3439 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3440 | } |
3441 | ||
5777ed34 JR |
3442 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
3443 | { | |
9f8fe504 | 3444 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
3445 | } |
3446 | ||
6389ee94 AK |
3447 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
3448 | struct x86_exception *fault) | |
6aa8b732 | 3449 | { |
6389ee94 | 3450 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
3451 | } |
3452 | ||
6aa8b732 AK |
3453 | static void paging_free(struct kvm_vcpu *vcpu) |
3454 | { | |
3455 | nonpaging_free(vcpu); | |
3456 | } | |
3457 | ||
8ea667f2 AK |
3458 | static inline void protect_clean_gpte(unsigned *access, unsigned gpte) |
3459 | { | |
3460 | unsigned mask; | |
3461 | ||
3462 | BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK); | |
3463 | ||
3464 | mask = (unsigned)~ACC_WRITE_MASK; | |
3465 | /* Allow write access to dirty gptes */ | |
3466 | mask |= (gpte >> (PT_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & PT_WRITABLE_MASK; | |
3467 | *access &= mask; | |
3468 | } | |
3469 | ||
f2fd125d XG |
3470 | static bool sync_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn, |
3471 | unsigned access, int *nr_present) | |
ce88decf XG |
3472 | { |
3473 | if (unlikely(is_mmio_spte(*sptep))) { | |
3474 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
3475 | mmu_spte_clear_no_track(sptep); | |
3476 | return true; | |
3477 | } | |
3478 | ||
3479 | (*nr_present)++; | |
f2fd125d | 3480 | mark_mmio_spte(kvm, sptep, gfn, access); |
ce88decf XG |
3481 | return true; |
3482 | } | |
3483 | ||
3484 | return false; | |
3485 | } | |
3486 | ||
3d34adec AK |
3487 | static inline unsigned gpte_access(struct kvm_vcpu *vcpu, u64 gpte) |
3488 | { | |
3489 | unsigned access; | |
3490 | ||
3491 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; | |
3492 | access &= ~(gpte >> PT64_NX_SHIFT); | |
3493 | ||
3494 | return access; | |
3495 | } | |
3496 | ||
6fd01b71 AK |
3497 | static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte) |
3498 | { | |
3499 | unsigned index; | |
3500 | ||
3501 | index = level - 1; | |
3502 | index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2); | |
3503 | return mmu->last_pte_bitmap & (1 << index); | |
3504 | } | |
3505 | ||
6aa8b732 AK |
3506 | #define PTTYPE 64 |
3507 | #include "paging_tmpl.h" | |
3508 | #undef PTTYPE | |
3509 | ||
3510 | #define PTTYPE 32 | |
3511 | #include "paging_tmpl.h" | |
3512 | #undef PTTYPE | |
3513 | ||
52fde8df | 3514 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4d6931c3 | 3515 | struct kvm_mmu *context) |
82725b20 | 3516 | { |
82725b20 DE |
3517 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
3518 | u64 exb_bit_rsvd = 0; | |
3519 | ||
2d48a985 | 3520 | if (!context->nx) |
82725b20 | 3521 | exb_bit_rsvd = rsvd_bits(63, 63); |
4d6931c3 | 3522 | switch (context->root_level) { |
82725b20 DE |
3523 | case PT32_ROOT_LEVEL: |
3524 | /* no rsvd bits for 2 level 4K page table entries */ | |
3525 | context->rsvd_bits_mask[0][1] = 0; | |
3526 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
3527 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
3528 | ||
3529 | if (!is_pse(vcpu)) { | |
3530 | context->rsvd_bits_mask[1][1] = 0; | |
3531 | break; | |
3532 | } | |
3533 | ||
82725b20 DE |
3534 | if (is_cpuid_PSE36()) |
3535 | /* 36bits PSE 4MB page */ | |
3536 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
3537 | else | |
3538 | /* 32 bits PSE 4MB page */ | |
3539 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
3540 | break; |
3541 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
3542 | context->rsvd_bits_mask[0][2] = |
3543 | rsvd_bits(maxphyaddr, 63) | | |
3544 | rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ | |
82725b20 | 3545 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 3546 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
3547 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
3548 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
3549 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
3550 | rsvd_bits(maxphyaddr, 62) | | |
3551 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 3552 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
3553 | break; |
3554 | case PT64_ROOT_LEVEL: | |
3555 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
3556 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
3557 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | | |
3558 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
3559 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | | |
4c26b4cd | 3560 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
3561 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
3562 | rsvd_bits(maxphyaddr, 51); | |
3563 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 JR |
3564 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
3565 | rsvd_bits(maxphyaddr, 51) | | |
3566 | rsvd_bits(13, 29); | |
82725b20 | 3567 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
3568 | rsvd_bits(maxphyaddr, 51) | |
3569 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 3570 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
3571 | break; |
3572 | } | |
3573 | } | |
3574 | ||
97d64b78 AK |
3575 | static void update_permission_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
3576 | { | |
3577 | unsigned bit, byte, pfec; | |
3578 | u8 map; | |
3579 | bool fault, x, w, u, wf, uf, ff, smep; | |
3580 | ||
3581 | smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); | |
3582 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { | |
3583 | pfec = byte << 1; | |
3584 | map = 0; | |
3585 | wf = pfec & PFERR_WRITE_MASK; | |
3586 | uf = pfec & PFERR_USER_MASK; | |
3587 | ff = pfec & PFERR_FETCH_MASK; | |
3588 | for (bit = 0; bit < 8; ++bit) { | |
3589 | x = bit & ACC_EXEC_MASK; | |
3590 | w = bit & ACC_WRITE_MASK; | |
3591 | u = bit & ACC_USER_MASK; | |
3592 | ||
3593 | /* Not really needed: !nx will cause pte.nx to fault */ | |
3594 | x |= !mmu->nx; | |
3595 | /* Allow supervisor writes if !cr0.wp */ | |
3596 | w |= !is_write_protection(vcpu) && !uf; | |
3597 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
3598 | x &= !(smep && u && !uf); | |
3599 | ||
3600 | fault = (ff && !x) || (uf && !u) || (wf && !w); | |
3601 | map |= fault << bit; | |
3602 | } | |
3603 | mmu->permissions[byte] = map; | |
3604 | } | |
3605 | } | |
3606 | ||
6fd01b71 AK |
3607 | static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
3608 | { | |
3609 | u8 map; | |
3610 | unsigned level, root_level = mmu->root_level; | |
3611 | const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */ | |
3612 | ||
3613 | if (root_level == PT32E_ROOT_LEVEL) | |
3614 | --root_level; | |
3615 | /* PT_PAGE_TABLE_LEVEL always terminates */ | |
3616 | map = 1 | (1 << ps_set_index); | |
3617 | for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) { | |
3618 | if (level <= PT_PDPE_LEVEL | |
3619 | && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu))) | |
3620 | map |= 1 << (ps_set_index | (level - 1)); | |
3621 | } | |
3622 | mmu->last_pte_bitmap = map; | |
3623 | } | |
3624 | ||
52fde8df JR |
3625 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, |
3626 | struct kvm_mmu *context, | |
3627 | int level) | |
6aa8b732 | 3628 | { |
2d48a985 | 3629 | context->nx = is_nx(vcpu); |
4d6931c3 | 3630 | context->root_level = level; |
2d48a985 | 3631 | |
4d6931c3 | 3632 | reset_rsvds_bits_mask(vcpu, context); |
97d64b78 | 3633 | update_permission_bitmask(vcpu, context); |
6fd01b71 | 3634 | update_last_pte_bitmap(vcpu, context); |
6aa8b732 AK |
3635 | |
3636 | ASSERT(is_pae(vcpu)); | |
3637 | context->new_cr3 = paging_new_cr3; | |
3638 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 3639 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 3640 | context->sync_page = paging64_sync_page; |
a7052897 | 3641 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 3642 | context->update_pte = paging64_update_pte; |
6aa8b732 | 3643 | context->free = paging_free; |
17ac10ad | 3644 | context->shadow_root_level = level; |
17c3ba9d | 3645 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3646 | context->direct_map = false; |
6aa8b732 AK |
3647 | return 0; |
3648 | } | |
3649 | ||
52fde8df JR |
3650 | static int paging64_init_context(struct kvm_vcpu *vcpu, |
3651 | struct kvm_mmu *context) | |
17ac10ad | 3652 | { |
52fde8df | 3653 | return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
3654 | } |
3655 | ||
52fde8df JR |
3656 | static int paging32_init_context(struct kvm_vcpu *vcpu, |
3657 | struct kvm_mmu *context) | |
6aa8b732 | 3658 | { |
2d48a985 | 3659 | context->nx = false; |
4d6931c3 | 3660 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 3661 | |
4d6931c3 | 3662 | reset_rsvds_bits_mask(vcpu, context); |
97d64b78 | 3663 | update_permission_bitmask(vcpu, context); |
6fd01b71 | 3664 | update_last_pte_bitmap(vcpu, context); |
6aa8b732 AK |
3665 | |
3666 | context->new_cr3 = paging_new_cr3; | |
3667 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
3668 | context->gva_to_gpa = paging32_gva_to_gpa; |
3669 | context->free = paging_free; | |
e8bc217a | 3670 | context->sync_page = paging32_sync_page; |
a7052897 | 3671 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 3672 | context->update_pte = paging32_update_pte; |
6aa8b732 | 3673 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3674 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3675 | context->direct_map = false; |
6aa8b732 AK |
3676 | return 0; |
3677 | } | |
3678 | ||
52fde8df JR |
3679 | static int paging32E_init_context(struct kvm_vcpu *vcpu, |
3680 | struct kvm_mmu *context) | |
6aa8b732 | 3681 | { |
52fde8df | 3682 | return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
3683 | } |
3684 | ||
fb72d167 JR |
3685 | static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
3686 | { | |
14dfe855 | 3687 | struct kvm_mmu *context = vcpu->arch.walk_mmu; |
fb72d167 | 3688 | |
c445f8ef | 3689 | context->base_role.word = 0; |
fb72d167 JR |
3690 | context->new_cr3 = nonpaging_new_cr3; |
3691 | context->page_fault = tdp_page_fault; | |
3692 | context->free = nonpaging_free; | |
e8bc217a | 3693 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3694 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3695 | context->update_pte = nonpaging_update_pte; |
67253af5 | 3696 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 3697 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3698 | context->direct_map = true; |
1c97f0a0 | 3699 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 3700 | context->get_cr3 = get_cr3; |
e4e517b4 | 3701 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 3702 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
3703 | |
3704 | if (!is_paging(vcpu)) { | |
2d48a985 | 3705 | context->nx = false; |
fb72d167 JR |
3706 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
3707 | context->root_level = 0; | |
3708 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3709 | context->nx = is_nx(vcpu); |
fb72d167 | 3710 | context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 DB |
3711 | reset_rsvds_bits_mask(vcpu, context); |
3712 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 3713 | } else if (is_pae(vcpu)) { |
2d48a985 | 3714 | context->nx = is_nx(vcpu); |
fb72d167 | 3715 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
3716 | reset_rsvds_bits_mask(vcpu, context); |
3717 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 3718 | } else { |
2d48a985 | 3719 | context->nx = false; |
fb72d167 | 3720 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
3721 | reset_rsvds_bits_mask(vcpu, context); |
3722 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
3723 | } |
3724 | ||
97d64b78 | 3725 | update_permission_bitmask(vcpu, context); |
6fd01b71 | 3726 | update_last_pte_bitmap(vcpu, context); |
97d64b78 | 3727 | |
fb72d167 JR |
3728 | return 0; |
3729 | } | |
3730 | ||
52fde8df | 3731 | int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context) |
6aa8b732 | 3732 | { |
a770f6f2 | 3733 | int r; |
411c588d | 3734 | bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
6aa8b732 | 3735 | ASSERT(vcpu); |
ad312c7c | 3736 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
3737 | |
3738 | if (!is_paging(vcpu)) | |
52fde8df | 3739 | r = nonpaging_init_context(vcpu, context); |
a9058ecd | 3740 | else if (is_long_mode(vcpu)) |
52fde8df | 3741 | r = paging64_init_context(vcpu, context); |
6aa8b732 | 3742 | else if (is_pae(vcpu)) |
52fde8df | 3743 | r = paging32E_init_context(vcpu, context); |
6aa8b732 | 3744 | else |
52fde8df | 3745 | r = paging32_init_context(vcpu, context); |
a770f6f2 | 3746 | |
2c9afa52 | 3747 | vcpu->arch.mmu.base_role.nxe = is_nx(vcpu); |
5b7e0102 | 3748 | vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu); |
f43addd4 | 3749 | vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu); |
411c588d AK |
3750 | vcpu->arch.mmu.base_role.smep_andnot_wp |
3751 | = smep && !is_write_protection(vcpu); | |
52fde8df JR |
3752 | |
3753 | return r; | |
3754 | } | |
3755 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
3756 | ||
3757 | static int init_kvm_softmmu(struct kvm_vcpu *vcpu) | |
3758 | { | |
14dfe855 | 3759 | int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu); |
52fde8df | 3760 | |
14dfe855 JR |
3761 | vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3; |
3762 | vcpu->arch.walk_mmu->get_cr3 = get_cr3; | |
e4e517b4 | 3763 | vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read; |
14dfe855 | 3764 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; |
a770f6f2 AK |
3765 | |
3766 | return r; | |
6aa8b732 AK |
3767 | } |
3768 | ||
02f59dc9 JR |
3769 | static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
3770 | { | |
3771 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
3772 | ||
3773 | g_context->get_cr3 = get_cr3; | |
e4e517b4 | 3774 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
3775 | g_context->inject_page_fault = kvm_inject_page_fault; |
3776 | ||
3777 | /* | |
3778 | * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The | |
3779 | * translation of l2_gpa to l1_gpa addresses is done using the | |
3780 | * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa | |
3781 | * functions between mmu and nested_mmu are swapped. | |
3782 | */ | |
3783 | if (!is_paging(vcpu)) { | |
2d48a985 | 3784 | g_context->nx = false; |
02f59dc9 JR |
3785 | g_context->root_level = 0; |
3786 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
3787 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3788 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 3789 | g_context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 | 3790 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3791 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
3792 | } else if (is_pae(vcpu)) { | |
2d48a985 | 3793 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 3794 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 3795 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3796 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
3797 | } else { | |
2d48a985 | 3798 | g_context->nx = false; |
02f59dc9 | 3799 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 3800 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3801 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
3802 | } | |
3803 | ||
97d64b78 | 3804 | update_permission_bitmask(vcpu, g_context); |
6fd01b71 | 3805 | update_last_pte_bitmap(vcpu, g_context); |
97d64b78 | 3806 | |
02f59dc9 JR |
3807 | return 0; |
3808 | } | |
3809 | ||
fb72d167 JR |
3810 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) |
3811 | { | |
02f59dc9 JR |
3812 | if (mmu_is_nested(vcpu)) |
3813 | return init_kvm_nested_mmu(vcpu); | |
3814 | else if (tdp_enabled) | |
fb72d167 JR |
3815 | return init_kvm_tdp_mmu(vcpu); |
3816 | else | |
3817 | return init_kvm_softmmu(vcpu); | |
3818 | } | |
3819 | ||
6aa8b732 AK |
3820 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) |
3821 | { | |
3822 | ASSERT(vcpu); | |
62ad0755 SY |
3823 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3824 | /* mmu.free() should set root_hpa = INVALID_PAGE */ | |
ad312c7c | 3825 | vcpu->arch.mmu.free(vcpu); |
6aa8b732 AK |
3826 | } |
3827 | ||
3828 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
3829 | { |
3830 | destroy_kvm_mmu(vcpu); | |
f8f7e5ee | 3831 | return init_kvm_mmu(vcpu); |
17c3ba9d | 3832 | } |
8668a3c4 | 3833 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
3834 | |
3835 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 3836 | { |
714b93da AK |
3837 | int r; |
3838 | ||
e2dec939 | 3839 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
3840 | if (r) |
3841 | goto out; | |
8986ecc0 | 3842 | r = mmu_alloc_roots(vcpu); |
e2858b4a | 3843 | kvm_mmu_sync_roots(vcpu); |
8986ecc0 MT |
3844 | if (r) |
3845 | goto out; | |
3662cb1c | 3846 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 3847 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
3848 | out: |
3849 | return r; | |
6aa8b732 | 3850 | } |
17c3ba9d AK |
3851 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
3852 | ||
3853 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
3854 | { | |
3855 | mmu_free_roots(vcpu); | |
3856 | } | |
4b16184c | 3857 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 3858 | |
0028425f | 3859 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
3860 | struct kvm_mmu_page *sp, u64 *spte, |
3861 | const void *new) | |
0028425f | 3862 | { |
30945387 | 3863 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
3864 | ++vcpu->kvm->stat.mmu_pde_zapped; |
3865 | return; | |
30945387 | 3866 | } |
0028425f | 3867 | |
4cee5764 | 3868 | ++vcpu->kvm->stat.mmu_pte_updated; |
7c562522 | 3869 | vcpu->arch.mmu.update_pte(vcpu, sp, spte, new); |
0028425f AK |
3870 | } |
3871 | ||
79539cec AK |
3872 | static bool need_remote_flush(u64 old, u64 new) |
3873 | { | |
3874 | if (!is_shadow_present_pte(old)) | |
3875 | return false; | |
3876 | if (!is_shadow_present_pte(new)) | |
3877 | return true; | |
3878 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
3879 | return true; | |
3880 | old ^= PT64_NX_MASK; | |
3881 | new ^= PT64_NX_MASK; | |
3882 | return (old & ~new & PT64_PERM_MASK) != 0; | |
3883 | } | |
3884 | ||
0671a8e7 XG |
3885 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
3886 | bool remote_flush, bool local_flush) | |
79539cec | 3887 | { |
0671a8e7 XG |
3888 | if (zap_page) |
3889 | return; | |
3890 | ||
3891 | if (remote_flush) | |
79539cec | 3892 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 3893 | else if (local_flush) |
79539cec AK |
3894 | kvm_mmu_flush_tlb(vcpu); |
3895 | } | |
3896 | ||
889e5cbc XG |
3897 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
3898 | const u8 *new, int *bytes) | |
da4a00f0 | 3899 | { |
889e5cbc XG |
3900 | u64 gentry; |
3901 | int r; | |
72016f3a | 3902 | |
72016f3a AK |
3903 | /* |
3904 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
3905 | * as the current vcpu paging mode since we update the sptes only |
3906 | * when they have the same mode. | |
72016f3a | 3907 | */ |
889e5cbc | 3908 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 3909 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
3910 | *gpa &= ~(gpa_t)7; |
3911 | *bytes = 8; | |
116eb3d3 | 3912 | r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, 8); |
72016f3a AK |
3913 | if (r) |
3914 | gentry = 0; | |
08e850c6 AK |
3915 | new = (const u8 *)&gentry; |
3916 | } | |
3917 | ||
889e5cbc | 3918 | switch (*bytes) { |
08e850c6 AK |
3919 | case 4: |
3920 | gentry = *(const u32 *)new; | |
3921 | break; | |
3922 | case 8: | |
3923 | gentry = *(const u64 *)new; | |
3924 | break; | |
3925 | default: | |
3926 | gentry = 0; | |
3927 | break; | |
72016f3a AK |
3928 | } |
3929 | ||
889e5cbc XG |
3930 | return gentry; |
3931 | } | |
3932 | ||
3933 | /* | |
3934 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
3935 | * or we may be forking, in which case it is better to unmap the page. | |
3936 | */ | |
a138fe75 | 3937 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 3938 | { |
a30f47cb XG |
3939 | /* |
3940 | * Skip write-flooding detected for the sp whose level is 1, because | |
3941 | * it can become unsync, then the guest page is not write-protected. | |
3942 | */ | |
f71fa31f | 3943 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) |
a30f47cb | 3944 | return false; |
3246af0e | 3945 | |
a30f47cb | 3946 | return ++sp->write_flooding_count >= 3; |
889e5cbc XG |
3947 | } |
3948 | ||
3949 | /* | |
3950 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
3951 | * indicate a page is not used as a page table. | |
3952 | */ | |
3953 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
3954 | int bytes) | |
3955 | { | |
3956 | unsigned offset, pte_size, misaligned; | |
3957 | ||
3958 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
3959 | gpa, bytes, sp->role.word); | |
3960 | ||
3961 | offset = offset_in_page(gpa); | |
3962 | pte_size = sp->role.cr4_pae ? 8 : 4; | |
5d9ca30e XG |
3963 | |
3964 | /* | |
3965 | * Sometimes, the OS only writes the last one bytes to update status | |
3966 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
3967 | */ | |
3968 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
3969 | return false; | |
3970 | ||
889e5cbc XG |
3971 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
3972 | misaligned |= bytes < 4; | |
3973 | ||
3974 | return misaligned; | |
3975 | } | |
3976 | ||
3977 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
3978 | { | |
3979 | unsigned page_offset, quadrant; | |
3980 | u64 *spte; | |
3981 | int level; | |
3982 | ||
3983 | page_offset = offset_in_page(gpa); | |
3984 | level = sp->role.level; | |
3985 | *nspte = 1; | |
3986 | if (!sp->role.cr4_pae) { | |
3987 | page_offset <<= 1; /* 32->64 */ | |
3988 | /* | |
3989 | * A 32-bit pde maps 4MB while the shadow pdes map | |
3990 | * only 2MB. So we need to double the offset again | |
3991 | * and zap two pdes instead of one. | |
3992 | */ | |
3993 | if (level == PT32_ROOT_LEVEL) { | |
3994 | page_offset &= ~7; /* kill rounding error */ | |
3995 | page_offset <<= 1; | |
3996 | *nspte = 2; | |
3997 | } | |
3998 | quadrant = page_offset >> PAGE_SHIFT; | |
3999 | page_offset &= ~PAGE_MASK; | |
4000 | if (quadrant != sp->role.quadrant) | |
4001 | return NULL; | |
4002 | } | |
4003 | ||
4004 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
4005 | return spte; | |
4006 | } | |
4007 | ||
4008 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4009 | const u8 *new, int bytes) | |
4010 | { | |
4011 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
4012 | union kvm_mmu_page_role mask = { .word = 0 }; | |
4013 | struct kvm_mmu_page *sp; | |
889e5cbc XG |
4014 | LIST_HEAD(invalid_list); |
4015 | u64 entry, gentry, *spte; | |
4016 | int npte; | |
a30f47cb | 4017 | bool remote_flush, local_flush, zap_page; |
889e5cbc XG |
4018 | |
4019 | /* | |
4020 | * If we don't have indirect shadow pages, it means no page is | |
4021 | * write-protected, so we can exit simply. | |
4022 | */ | |
4023 | if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) | |
4024 | return; | |
4025 | ||
4026 | zap_page = remote_flush = local_flush = false; | |
4027 | ||
4028 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
4029 | ||
4030 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes); | |
4031 | ||
4032 | /* | |
4033 | * No need to care whether allocation memory is successful | |
4034 | * or not since pte prefetch is skiped if it does not have | |
4035 | * enough objects in the cache. | |
4036 | */ | |
4037 | mmu_topup_memory_caches(vcpu); | |
4038 | ||
4039 | spin_lock(&vcpu->kvm->mmu_lock); | |
4040 | ++vcpu->kvm->stat.mmu_pte_write; | |
0375f7fa | 4041 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 4042 | |
fa1de2bf | 4043 | mask.cr0_wp = mask.cr4_pae = mask.nxe = 1; |
b67bfe0d | 4044 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 4045 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 4046 | detect_write_flooding(sp)) { |
0671a8e7 | 4047 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 4048 | &invalid_list); |
4cee5764 | 4049 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
4050 | continue; |
4051 | } | |
889e5cbc XG |
4052 | |
4053 | spte = get_written_sptes(sp, gpa, &npte); | |
4054 | if (!spte) | |
4055 | continue; | |
4056 | ||
0671a8e7 | 4057 | local_flush = true; |
ac1b714e | 4058 | while (npte--) { |
79539cec | 4059 | entry = *spte; |
38e3b2b2 | 4060 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf XG |
4061 | if (gentry && |
4062 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
f759e2b4 | 4063 | & mask.word) && rmap_can_add(vcpu)) |
7c562522 | 4064 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
9bb4f6b1 | 4065 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 4066 | remote_flush = true; |
ac1b714e | 4067 | ++spte; |
9b7a0325 | 4068 | } |
9b7a0325 | 4069 | } |
0671a8e7 | 4070 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 4071 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
0375f7fa | 4072 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 4073 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
4074 | } |
4075 | ||
a436036b AK |
4076 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
4077 | { | |
10589a46 MT |
4078 | gpa_t gpa; |
4079 | int r; | |
a436036b | 4080 | |
c5a78f2b | 4081 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
4082 | return 0; |
4083 | ||
1871c602 | 4084 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 4085 | |
10589a46 | 4086 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 4087 | |
10589a46 | 4088 | return r; |
a436036b | 4089 | } |
577bdc49 | 4090 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 4091 | |
81f4f76b | 4092 | static void make_mmu_pages_available(struct kvm_vcpu *vcpu) |
ebeace86 | 4093 | { |
d98ba053 | 4094 | LIST_HEAD(invalid_list); |
103ad25a | 4095 | |
81f4f76b TY |
4096 | if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES)) |
4097 | return; | |
4098 | ||
5da59607 TY |
4099 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) { |
4100 | if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list)) | |
4101 | break; | |
ebeace86 | 4102 | |
4cee5764 | 4103 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 4104 | } |
aa6bd187 | 4105 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
ebeace86 | 4106 | } |
ebeace86 | 4107 | |
1cb3f3ae XG |
4108 | static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr) |
4109 | { | |
4110 | if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu)) | |
4111 | return vcpu_match_mmio_gpa(vcpu, addr); | |
4112 | ||
4113 | return vcpu_match_mmio_gva(vcpu, addr); | |
4114 | } | |
4115 | ||
dc25e89e AP |
4116 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code, |
4117 | void *insn, int insn_len) | |
3067714c | 4118 | { |
1cb3f3ae | 4119 | int r, emulation_type = EMULTYPE_RETRY; |
3067714c AK |
4120 | enum emulation_result er; |
4121 | ||
56028d08 | 4122 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false); |
3067714c AK |
4123 | if (r < 0) |
4124 | goto out; | |
4125 | ||
4126 | if (!r) { | |
4127 | r = 1; | |
4128 | goto out; | |
4129 | } | |
4130 | ||
1cb3f3ae XG |
4131 | if (is_mmio_page_fault(vcpu, cr2)) |
4132 | emulation_type = 0; | |
4133 | ||
4134 | er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len); | |
3067714c AK |
4135 | |
4136 | switch (er) { | |
4137 | case EMULATE_DONE: | |
4138 | return 1; | |
4139 | case EMULATE_DO_MMIO: | |
4140 | ++vcpu->stat.mmio_exits; | |
6d77dbfc | 4141 | /* fall through */ |
3067714c | 4142 | case EMULATE_FAIL: |
3f5d18a9 | 4143 | return 0; |
3067714c AK |
4144 | default: |
4145 | BUG(); | |
4146 | } | |
4147 | out: | |
3067714c AK |
4148 | return r; |
4149 | } | |
4150 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
4151 | ||
a7052897 MT |
4152 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
4153 | { | |
a7052897 | 4154 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
4155 | kvm_mmu_flush_tlb(vcpu); |
4156 | ++vcpu->stat.invlpg; | |
4157 | } | |
4158 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
4159 | ||
18552672 JR |
4160 | void kvm_enable_tdp(void) |
4161 | { | |
4162 | tdp_enabled = true; | |
4163 | } | |
4164 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
4165 | ||
5f4cb662 JR |
4166 | void kvm_disable_tdp(void) |
4167 | { | |
4168 | tdp_enabled = false; | |
4169 | } | |
4170 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
4171 | ||
6aa8b732 AK |
4172 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
4173 | { | |
ad312c7c | 4174 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
81407ca5 JR |
4175 | if (vcpu->arch.mmu.lm_root != NULL) |
4176 | free_page((unsigned long)vcpu->arch.mmu.lm_root); | |
6aa8b732 AK |
4177 | } |
4178 | ||
4179 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
4180 | { | |
17ac10ad | 4181 | struct page *page; |
6aa8b732 AK |
4182 | int i; |
4183 | ||
4184 | ASSERT(vcpu); | |
4185 | ||
17ac10ad AK |
4186 | /* |
4187 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
4188 | * Therefore we need to allocate shadow page tables in the first | |
4189 | * 4GB of memory, which happens to fit the DMA32 zone. | |
4190 | */ | |
4191 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
4192 | if (!page) | |
d7fa6ab2 WY |
4193 | return -ENOMEM; |
4194 | ||
ad312c7c | 4195 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 4196 | for (i = 0; i < 4; ++i) |
ad312c7c | 4197 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 4198 | |
6aa8b732 | 4199 | return 0; |
6aa8b732 AK |
4200 | } |
4201 | ||
8018c27b | 4202 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 4203 | { |
6aa8b732 | 4204 | ASSERT(vcpu); |
e459e322 XG |
4205 | |
4206 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
4207 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; | |
4208 | vcpu->arch.mmu.translate_gpa = translate_gpa; | |
4209 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; | |
6aa8b732 | 4210 | |
8018c27b IM |
4211 | return alloc_mmu_pages(vcpu); |
4212 | } | |
6aa8b732 | 4213 | |
8018c27b IM |
4214 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
4215 | { | |
4216 | ASSERT(vcpu); | |
ad312c7c | 4217 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 4218 | |
8018c27b | 4219 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
4220 | } |
4221 | ||
90cb0529 | 4222 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 4223 | { |
b99db1d3 TY |
4224 | struct kvm_memory_slot *memslot; |
4225 | gfn_t last_gfn; | |
4226 | int i; | |
6aa8b732 | 4227 | |
b99db1d3 TY |
4228 | memslot = id_to_memslot(kvm->memslots, slot); |
4229 | last_gfn = memslot->base_gfn + memslot->npages - 1; | |
6aa8b732 | 4230 | |
9d1beefb TY |
4231 | spin_lock(&kvm->mmu_lock); |
4232 | ||
b99db1d3 TY |
4233 | for (i = PT_PAGE_TABLE_LEVEL; |
4234 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
4235 | unsigned long *rmapp; | |
4236 | unsigned long last_index, index; | |
6aa8b732 | 4237 | |
b99db1d3 TY |
4238 | rmapp = memslot->arch.rmap[i - PT_PAGE_TABLE_LEVEL]; |
4239 | last_index = gfn_to_index(last_gfn, memslot->base_gfn, i); | |
da8dc75f | 4240 | |
b99db1d3 TY |
4241 | for (index = 0; index <= last_index; ++index, ++rmapp) { |
4242 | if (*rmapp) | |
4243 | __rmap_write_protect(kvm, rmapp, false); | |
6b81b05e TY |
4244 | |
4245 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { | |
4246 | kvm_flush_remote_tlbs(kvm); | |
4247 | cond_resched_lock(&kvm->mmu_lock); | |
4248 | } | |
8234b22e | 4249 | } |
6aa8b732 | 4250 | } |
b99db1d3 | 4251 | |
171d595d | 4252 | kvm_flush_remote_tlbs(kvm); |
9d1beefb | 4253 | spin_unlock(&kvm->mmu_lock); |
6aa8b732 | 4254 | } |
37a7d8b0 | 4255 | |
e7d11c7a | 4256 | #define BATCH_ZAP_PAGES 10 |
5304b8d3 XG |
4257 | static void kvm_zap_obsolete_pages(struct kvm *kvm) |
4258 | { | |
4259 | struct kvm_mmu_page *sp, *node; | |
e7d11c7a | 4260 | int batch = 0; |
5304b8d3 XG |
4261 | |
4262 | restart: | |
4263 | list_for_each_entry_safe_reverse(sp, node, | |
4264 | &kvm->arch.active_mmu_pages, link) { | |
e7d11c7a XG |
4265 | int ret; |
4266 | ||
5304b8d3 XG |
4267 | /* |
4268 | * No obsolete page exists before new created page since | |
4269 | * active_mmu_pages is the FIFO list. | |
4270 | */ | |
4271 | if (!is_obsolete_sp(kvm, sp)) | |
4272 | break; | |
4273 | ||
4274 | /* | |
5304b8d3 XG |
4275 | * Since we are reversely walking the list and the invalid |
4276 | * list will be moved to the head, skip the invalid page | |
4277 | * can help us to avoid the infinity list walking. | |
4278 | */ | |
4279 | if (sp->role.invalid) | |
4280 | continue; | |
4281 | ||
f34d251d XG |
4282 | /* |
4283 | * Need not flush tlb since we only zap the sp with invalid | |
4284 | * generation number. | |
4285 | */ | |
e7d11c7a | 4286 | if (batch >= BATCH_ZAP_PAGES && |
f34d251d | 4287 | cond_resched_lock(&kvm->mmu_lock)) { |
e7d11c7a | 4288 | batch = 0; |
5304b8d3 XG |
4289 | goto restart; |
4290 | } | |
4291 | ||
365c8868 XG |
4292 | ret = kvm_mmu_prepare_zap_page(kvm, sp, |
4293 | &kvm->arch.zapped_obsolete_pages); | |
e7d11c7a XG |
4294 | batch += ret; |
4295 | ||
4296 | if (ret) | |
5304b8d3 XG |
4297 | goto restart; |
4298 | } | |
4299 | ||
f34d251d XG |
4300 | /* |
4301 | * Should flush tlb before free page tables since lockless-walking | |
4302 | * may use the pages. | |
4303 | */ | |
365c8868 | 4304 | kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages); |
5304b8d3 XG |
4305 | } |
4306 | ||
4307 | /* | |
4308 | * Fast invalidate all shadow pages and use lock-break technique | |
4309 | * to zap obsolete pages. | |
4310 | * | |
4311 | * It's required when memslot is being deleted or VM is being | |
4312 | * destroyed, in these cases, we should ensure that KVM MMU does | |
4313 | * not use any resource of the being-deleted slot or all slots | |
4314 | * after calling the function. | |
4315 | */ | |
4316 | void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm) | |
4317 | { | |
4318 | spin_lock(&kvm->mmu_lock); | |
35006126 | 4319 | trace_kvm_mmu_invalidate_zap_all_pages(kvm); |
5304b8d3 XG |
4320 | kvm->arch.mmu_valid_gen++; |
4321 | ||
f34d251d XG |
4322 | /* |
4323 | * Notify all vcpus to reload its shadow page table | |
4324 | * and flush TLB. Then all vcpus will switch to new | |
4325 | * shadow page table with the new mmu_valid_gen. | |
4326 | * | |
4327 | * Note: we should do this under the protection of | |
4328 | * mmu-lock, otherwise, vcpu would purge shadow page | |
4329 | * but miss tlb flush. | |
4330 | */ | |
4331 | kvm_reload_remote_mmus(kvm); | |
4332 | ||
5304b8d3 XG |
4333 | kvm_zap_obsolete_pages(kvm); |
4334 | spin_unlock(&kvm->mmu_lock); | |
4335 | } | |
4336 | ||
982b3394 TY |
4337 | void kvm_mmu_zap_mmio_sptes(struct kvm *kvm) |
4338 | { | |
4339 | struct kvm_mmu_page *sp, *node; | |
4340 | LIST_HEAD(invalid_list); | |
4341 | ||
4342 | spin_lock(&kvm->mmu_lock); | |
4343 | restart: | |
4344 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) { | |
4345 | if (!sp->mmio_cached) | |
4346 | continue; | |
4347 | if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list)) | |
4348 | goto restart; | |
4349 | } | |
4350 | ||
4351 | kvm_mmu_commit_zap_page(kvm, &invalid_list); | |
4352 | spin_unlock(&kvm->mmu_lock); | |
4353 | } | |
4354 | ||
365c8868 XG |
4355 | static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm) |
4356 | { | |
4357 | return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages)); | |
4358 | } | |
4359 | ||
1495f230 | 4360 | static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc) |
3ee16c81 IE |
4361 | { |
4362 | struct kvm *kvm; | |
1495f230 | 4363 | int nr_to_scan = sc->nr_to_scan; |
45221ab6 DH |
4364 | |
4365 | if (nr_to_scan == 0) | |
4366 | goto out; | |
3ee16c81 | 4367 | |
e935b837 | 4368 | raw_spin_lock(&kvm_lock); |
3ee16c81 IE |
4369 | |
4370 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 4371 | int idx; |
d98ba053 | 4372 | LIST_HEAD(invalid_list); |
3ee16c81 | 4373 | |
35f2d16b TY |
4374 | /* |
4375 | * Never scan more than sc->nr_to_scan VM instances. | |
4376 | * Will not hit this condition practically since we do not try | |
4377 | * to shrink more than one VM and it is very unlikely to see | |
4378 | * !n_used_mmu_pages so many times. | |
4379 | */ | |
4380 | if (!nr_to_scan--) | |
4381 | break; | |
19526396 GN |
4382 | /* |
4383 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
4384 | * here. We may skip a VM instance errorneosly, but we do not | |
4385 | * want to shrink a VM that only started to populate its MMU | |
4386 | * anyway. | |
4387 | */ | |
365c8868 XG |
4388 | if (!kvm->arch.n_used_mmu_pages && |
4389 | !kvm_has_zapped_obsolete_pages(kvm)) | |
19526396 | 4390 | continue; |
19526396 | 4391 | |
f656ce01 | 4392 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 4393 | spin_lock(&kvm->mmu_lock); |
3ee16c81 | 4394 | |
365c8868 XG |
4395 | if (kvm_has_zapped_obsolete_pages(kvm)) { |
4396 | kvm_mmu_commit_zap_page(kvm, | |
4397 | &kvm->arch.zapped_obsolete_pages); | |
4398 | goto unlock; | |
4399 | } | |
4400 | ||
5da59607 | 4401 | prepare_zap_oldest_mmu_page(kvm, &invalid_list); |
d98ba053 | 4402 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
19526396 | 4403 | |
365c8868 | 4404 | unlock: |
3ee16c81 | 4405 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 4406 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 GN |
4407 | |
4408 | list_move_tail(&kvm->vm_list, &vm_list); | |
4409 | break; | |
3ee16c81 | 4410 | } |
3ee16c81 | 4411 | |
e935b837 | 4412 | raw_spin_unlock(&kvm_lock); |
3ee16c81 | 4413 | |
45221ab6 DH |
4414 | out: |
4415 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); | |
3ee16c81 IE |
4416 | } |
4417 | ||
4418 | static struct shrinker mmu_shrinker = { | |
4419 | .shrink = mmu_shrink, | |
4420 | .seeks = DEFAULT_SEEKS * 10, | |
4421 | }; | |
4422 | ||
2ddfd20e | 4423 | static void mmu_destroy_caches(void) |
b5a33a75 | 4424 | { |
53c07b18 XG |
4425 | if (pte_list_desc_cache) |
4426 | kmem_cache_destroy(pte_list_desc_cache); | |
d3d25b04 AK |
4427 | if (mmu_page_header_cache) |
4428 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
4429 | } |
4430 | ||
4431 | int kvm_mmu_module_init(void) | |
4432 | { | |
53c07b18 XG |
4433 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
4434 | sizeof(struct pte_list_desc), | |
20c2df83 | 4435 | 0, 0, NULL); |
53c07b18 | 4436 | if (!pte_list_desc_cache) |
b5a33a75 AK |
4437 | goto nomem; |
4438 | ||
d3d25b04 AK |
4439 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
4440 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 4441 | 0, 0, NULL); |
d3d25b04 AK |
4442 | if (!mmu_page_header_cache) |
4443 | goto nomem; | |
4444 | ||
45bf21a8 WY |
4445 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0)) |
4446 | goto nomem; | |
4447 | ||
3ee16c81 IE |
4448 | register_shrinker(&mmu_shrinker); |
4449 | ||
b5a33a75 AK |
4450 | return 0; |
4451 | ||
4452 | nomem: | |
3ee16c81 | 4453 | mmu_destroy_caches(); |
b5a33a75 AK |
4454 | return -ENOMEM; |
4455 | } | |
4456 | ||
3ad82a7e ZX |
4457 | /* |
4458 | * Caculate mmu pages needed for kvm. | |
4459 | */ | |
4460 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
4461 | { | |
3ad82a7e ZX |
4462 | unsigned int nr_mmu_pages; |
4463 | unsigned int nr_pages = 0; | |
bc6678a3 | 4464 | struct kvm_memslots *slots; |
be6ba0f0 | 4465 | struct kvm_memory_slot *memslot; |
3ad82a7e | 4466 | |
90d83dc3 LJ |
4467 | slots = kvm_memslots(kvm); |
4468 | ||
be6ba0f0 XG |
4469 | kvm_for_each_memslot(memslot, slots) |
4470 | nr_pages += memslot->npages; | |
3ad82a7e ZX |
4471 | |
4472 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
4473 | nr_mmu_pages = max(nr_mmu_pages, | |
4474 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
4475 | ||
4476 | return nr_mmu_pages; | |
4477 | } | |
4478 | ||
94d8b056 MT |
4479 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
4480 | { | |
4481 | struct kvm_shadow_walk_iterator iterator; | |
c2a2ac2b | 4482 | u64 spte; |
94d8b056 MT |
4483 | int nr_sptes = 0; |
4484 | ||
c2a2ac2b XG |
4485 | walk_shadow_page_lockless_begin(vcpu); |
4486 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
4487 | sptes[iterator.level-1] = spte; | |
94d8b056 | 4488 | nr_sptes++; |
c2a2ac2b | 4489 | if (!is_shadow_present_pte(spte)) |
94d8b056 MT |
4490 | break; |
4491 | } | |
c2a2ac2b | 4492 | walk_shadow_page_lockless_end(vcpu); |
94d8b056 MT |
4493 | |
4494 | return nr_sptes; | |
4495 | } | |
4496 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
4497 | ||
c42fffe3 XG |
4498 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
4499 | { | |
4500 | ASSERT(vcpu); | |
4501 | ||
4502 | destroy_kvm_mmu(vcpu); | |
4503 | free_mmu_pages(vcpu); | |
4504 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
4505 | } |
4506 | ||
b034cf01 XG |
4507 | void kvm_mmu_module_exit(void) |
4508 | { | |
4509 | mmu_destroy_caches(); | |
4510 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
4511 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
4512 | mmu_audit_disable(); |
4513 | } |