Commit | Line | Data |
---|---|---|
6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
221d059d | 10 | * Copyright 2010 Red Hat, Inc. and/or its affilates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
1d737c8a | 21 | #include "mmu.h" |
836a1b3c | 22 | #include "x86.h" |
6de4f3ad | 23 | #include "kvm_cache_regs.h" |
e495606d | 24 | |
edf88417 | 25 | #include <linux/kvm_host.h> |
6aa8b732 AK |
26 | #include <linux/types.h> |
27 | #include <linux/string.h> | |
6aa8b732 AK |
28 | #include <linux/mm.h> |
29 | #include <linux/highmem.h> | |
30 | #include <linux/module.h> | |
448353ca | 31 | #include <linux/swap.h> |
05da4558 | 32 | #include <linux/hugetlb.h> |
2f333bcb | 33 | #include <linux/compiler.h> |
bc6678a3 | 34 | #include <linux/srcu.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
bf998156 | 36 | #include <linux/uaccess.h> |
6aa8b732 | 37 | |
e495606d AK |
38 | #include <asm/page.h> |
39 | #include <asm/cmpxchg.h> | |
4e542370 | 40 | #include <asm/io.h> |
13673a90 | 41 | #include <asm/vmx.h> |
6aa8b732 | 42 | |
18552672 JR |
43 | /* |
44 | * When setting this variable to true it enables Two-Dimensional-Paging | |
45 | * where the hardware walks 2 page tables: | |
46 | * 1. the guest-virtual to guest-physical | |
47 | * 2. while doing 1. it walks guest-physical to host-physical | |
48 | * If the hardware supports that we don't need to do shadow paging. | |
49 | */ | |
2f333bcb | 50 | bool tdp_enabled = false; |
18552672 | 51 | |
37a7d8b0 AK |
52 | #undef MMU_DEBUG |
53 | ||
54 | #undef AUDIT | |
55 | ||
56 | #ifdef AUDIT | |
57 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg); | |
58 | #else | |
59 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {} | |
60 | #endif | |
61 | ||
62 | #ifdef MMU_DEBUG | |
63 | ||
64 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
65 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
66 | ||
67 | #else | |
68 | ||
69 | #define pgprintk(x...) do { } while (0) | |
70 | #define rmap_printk(x...) do { } while (0) | |
71 | ||
72 | #endif | |
73 | ||
74 | #if defined(MMU_DEBUG) || defined(AUDIT) | |
6ada8cca AK |
75 | static int dbg = 0; |
76 | module_param(dbg, bool, 0644); | |
37a7d8b0 | 77 | #endif |
6aa8b732 | 78 | |
582801a9 MT |
79 | static int oos_shadow = 1; |
80 | module_param(oos_shadow, bool, 0644); | |
81 | ||
d6c69ee9 YD |
82 | #ifndef MMU_DEBUG |
83 | #define ASSERT(x) do { } while (0) | |
84 | #else | |
6aa8b732 AK |
85 | #define ASSERT(x) \ |
86 | if (!(x)) { \ | |
87 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
88 | __FILE__, __LINE__, #x); \ | |
89 | } | |
d6c69ee9 | 90 | #endif |
6aa8b732 | 91 | |
6aa8b732 AK |
92 | #define PT_FIRST_AVAIL_BITS_SHIFT 9 |
93 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 | |
94 | ||
6aa8b732 AK |
95 | #define PT64_LEVEL_BITS 9 |
96 | ||
97 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 98 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 AK |
99 | |
100 | #define PT64_LEVEL_MASK(level) \ | |
101 | (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level)) | |
102 | ||
103 | #define PT64_INDEX(address, level)\ | |
104 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
105 | ||
106 | ||
107 | #define PT32_LEVEL_BITS 10 | |
108 | ||
109 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 110 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 AK |
111 | |
112 | #define PT32_LEVEL_MASK(level) \ | |
113 | (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level)) | |
e04da980 JR |
114 | #define PT32_LVL_OFFSET_MASK(level) \ |
115 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
116 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
117 | |
118 | #define PT32_INDEX(address, level)\ | |
119 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
120 | ||
121 | ||
27aba766 | 122 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
123 | #define PT64_DIR_BASE_ADDR_MASK \ |
124 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
125 | #define PT64_LVL_ADDR_MASK(level) \ |
126 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
127 | * PT64_LEVEL_BITS))) - 1)) | |
128 | #define PT64_LVL_OFFSET_MASK(level) \ | |
129 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
130 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
131 | |
132 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
133 | #define PT32_DIR_BASE_ADDR_MASK \ | |
134 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
135 | #define PT32_LVL_ADDR_MASK(level) \ |
136 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
137 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 138 | |
79539cec AK |
139 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
140 | | PT64_NX_MASK) | |
6aa8b732 | 141 | |
cd4a4e53 AK |
142 | #define RMAP_EXT 4 |
143 | ||
fe135d2c AK |
144 | #define ACC_EXEC_MASK 1 |
145 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
146 | #define ACC_USER_MASK PT_USER_MASK | |
147 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
148 | ||
90bb6fc5 AK |
149 | #include <trace/events/kvm.h> |
150 | ||
07420171 AK |
151 | #define CREATE_TRACE_POINTS |
152 | #include "mmutrace.h" | |
153 | ||
1403283a IE |
154 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
155 | ||
135f8c2b AK |
156 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
157 | ||
cd4a4e53 | 158 | struct kvm_rmap_desc { |
d555c333 | 159 | u64 *sptes[RMAP_EXT]; |
cd4a4e53 AK |
160 | struct kvm_rmap_desc *more; |
161 | }; | |
162 | ||
2d11123a AK |
163 | struct kvm_shadow_walk_iterator { |
164 | u64 addr; | |
165 | hpa_t shadow_addr; | |
166 | int level; | |
167 | u64 *sptep; | |
168 | unsigned index; | |
169 | }; | |
170 | ||
171 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
172 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
173 | shadow_walk_okay(&(_walker)); \ | |
174 | shadow_walk_next(&(_walker))) | |
175 | ||
1047df1f | 176 | typedef void (*mmu_parent_walk_fn) (struct kvm_mmu_page *sp, u64 *spte); |
ad8cfbe3 | 177 | |
b5a33a75 AK |
178 | static struct kmem_cache *pte_chain_cache; |
179 | static struct kmem_cache *rmap_desc_cache; | |
d3d25b04 | 180 | static struct kmem_cache *mmu_page_header_cache; |
b5a33a75 | 181 | |
c7addb90 AK |
182 | static u64 __read_mostly shadow_trap_nonpresent_pte; |
183 | static u64 __read_mostly shadow_notrap_nonpresent_pte; | |
7b52345e SY |
184 | static u64 __read_mostly shadow_base_present_pte; |
185 | static u64 __read_mostly shadow_nx_mask; | |
186 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
187 | static u64 __read_mostly shadow_user_mask; | |
188 | static u64 __read_mostly shadow_accessed_mask; | |
189 | static u64 __read_mostly shadow_dirty_mask; | |
c7addb90 | 190 | |
82725b20 DE |
191 | static inline u64 rsvd_bits(int s, int e) |
192 | { | |
193 | return ((1ULL << (e - s + 1)) - 1) << s; | |
194 | } | |
195 | ||
c7addb90 AK |
196 | void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte) |
197 | { | |
198 | shadow_trap_nonpresent_pte = trap_pte; | |
199 | shadow_notrap_nonpresent_pte = notrap_pte; | |
200 | } | |
201 | EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes); | |
202 | ||
7b52345e SY |
203 | void kvm_mmu_set_base_ptes(u64 base_pte) |
204 | { | |
205 | shadow_base_present_pte = base_pte; | |
206 | } | |
207 | EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes); | |
208 | ||
209 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, | |
4b12f0de | 210 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
211 | { |
212 | shadow_user_mask = user_mask; | |
213 | shadow_accessed_mask = accessed_mask; | |
214 | shadow_dirty_mask = dirty_mask; | |
215 | shadow_nx_mask = nx_mask; | |
216 | shadow_x_mask = x_mask; | |
217 | } | |
218 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
219 | ||
3dbe1415 | 220 | static bool is_write_protection(struct kvm_vcpu *vcpu) |
6aa8b732 | 221 | { |
4d4ec087 | 222 | return kvm_read_cr0_bits(vcpu, X86_CR0_WP); |
6aa8b732 AK |
223 | } |
224 | ||
225 | static int is_cpuid_PSE36(void) | |
226 | { | |
227 | return 1; | |
228 | } | |
229 | ||
73b1087e AK |
230 | static int is_nx(struct kvm_vcpu *vcpu) |
231 | { | |
f6801dff | 232 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
233 | } |
234 | ||
c7addb90 AK |
235 | static int is_shadow_present_pte(u64 pte) |
236 | { | |
c7addb90 AK |
237 | return pte != shadow_trap_nonpresent_pte |
238 | && pte != shadow_notrap_nonpresent_pte; | |
239 | } | |
240 | ||
05da4558 MT |
241 | static int is_large_pte(u64 pte) |
242 | { | |
243 | return pte & PT_PAGE_SIZE_MASK; | |
244 | } | |
245 | ||
8dae4445 | 246 | static int is_writable_pte(unsigned long pte) |
6aa8b732 AK |
247 | { |
248 | return pte & PT_WRITABLE_MASK; | |
249 | } | |
250 | ||
43a3795a | 251 | static int is_dirty_gpte(unsigned long pte) |
e3c5e7ec | 252 | { |
439e218a | 253 | return pte & PT_DIRTY_MASK; |
e3c5e7ec AK |
254 | } |
255 | ||
43a3795a | 256 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 257 | { |
4b1a80fa | 258 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
259 | } |
260 | ||
776e6633 MT |
261 | static int is_last_spte(u64 pte, int level) |
262 | { | |
263 | if (level == PT_PAGE_TABLE_LEVEL) | |
264 | return 1; | |
852e3c19 | 265 | if (is_large_pte(pte)) |
776e6633 MT |
266 | return 1; |
267 | return 0; | |
268 | } | |
269 | ||
35149e21 | 270 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 271 | { |
35149e21 | 272 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
273 | } |
274 | ||
da928521 AK |
275 | static gfn_t pse36_gfn_delta(u32 gpte) |
276 | { | |
277 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
278 | ||
279 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
280 | } | |
281 | ||
d555c333 | 282 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 AK |
283 | { |
284 | #ifdef CONFIG_X86_64 | |
285 | set_64bit((unsigned long *)sptep, spte); | |
286 | #else | |
287 | set_64bit((unsigned long long *)sptep, spte); | |
288 | #endif | |
289 | } | |
290 | ||
e2dec939 | 291 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 292 | struct kmem_cache *base_cache, int min) |
714b93da AK |
293 | { |
294 | void *obj; | |
295 | ||
296 | if (cache->nobjs >= min) | |
e2dec939 | 297 | return 0; |
714b93da | 298 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 299 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 300 | if (!obj) |
e2dec939 | 301 | return -ENOMEM; |
714b93da AK |
302 | cache->objects[cache->nobjs++] = obj; |
303 | } | |
e2dec939 | 304 | return 0; |
714b93da AK |
305 | } |
306 | ||
e8ad9a70 XG |
307 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
308 | struct kmem_cache *cache) | |
714b93da AK |
309 | { |
310 | while (mc->nobjs) | |
e8ad9a70 | 311 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
312 | } |
313 | ||
c1158e63 | 314 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 315 | int min) |
c1158e63 AK |
316 | { |
317 | struct page *page; | |
318 | ||
319 | if (cache->nobjs >= min) | |
320 | return 0; | |
321 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
2e3e5882 | 322 | page = alloc_page(GFP_KERNEL); |
c1158e63 AK |
323 | if (!page) |
324 | return -ENOMEM; | |
c1158e63 AK |
325 | cache->objects[cache->nobjs++] = page_address(page); |
326 | } | |
327 | return 0; | |
328 | } | |
329 | ||
330 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
331 | { | |
332 | while (mc->nobjs) | |
c4d198d5 | 333 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
334 | } |
335 | ||
2e3e5882 | 336 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 337 | { |
e2dec939 AK |
338 | int r; |
339 | ||
ad312c7c | 340 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache, |
2e3e5882 | 341 | pte_chain_cache, 4); |
e2dec939 AK |
342 | if (r) |
343 | goto out; | |
ad312c7c | 344 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, |
c41ef344 | 345 | rmap_desc_cache, 4); |
d3d25b04 AK |
346 | if (r) |
347 | goto out; | |
ad312c7c | 348 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
349 | if (r) |
350 | goto out; | |
ad312c7c | 351 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 352 | mmu_page_header_cache, 4); |
e2dec939 AK |
353 | out: |
354 | return r; | |
714b93da AK |
355 | } |
356 | ||
357 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
358 | { | |
e8ad9a70 XG |
359 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache, pte_chain_cache); |
360 | mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, rmap_desc_cache); | |
ad312c7c | 361 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
362 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
363 | mmu_page_header_cache); | |
714b93da AK |
364 | } |
365 | ||
366 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc, | |
367 | size_t size) | |
368 | { | |
369 | void *p; | |
370 | ||
371 | BUG_ON(!mc->nobjs); | |
372 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
373 | return p; |
374 | } | |
375 | ||
714b93da AK |
376 | static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu) |
377 | { | |
ad312c7c | 378 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache, |
714b93da AK |
379 | sizeof(struct kvm_pte_chain)); |
380 | } | |
381 | ||
90cb0529 | 382 | static void mmu_free_pte_chain(struct kvm_pte_chain *pc) |
714b93da | 383 | { |
e8ad9a70 | 384 | kmem_cache_free(pte_chain_cache, pc); |
714b93da AK |
385 | } |
386 | ||
387 | static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu) | |
388 | { | |
ad312c7c | 389 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache, |
714b93da AK |
390 | sizeof(struct kvm_rmap_desc)); |
391 | } | |
392 | ||
90cb0529 | 393 | static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd) |
714b93da | 394 | { |
e8ad9a70 | 395 | kmem_cache_free(rmap_desc_cache, rd); |
714b93da AK |
396 | } |
397 | ||
2032a93d LJ |
398 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
399 | { | |
400 | if (!sp->role.direct) | |
401 | return sp->gfns[index]; | |
402 | ||
403 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
404 | } | |
405 | ||
406 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
407 | { | |
408 | if (sp->role.direct) | |
409 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
410 | else | |
411 | sp->gfns[index] = gfn; | |
412 | } | |
413 | ||
05da4558 MT |
414 | /* |
415 | * Return the pointer to the largepage write count for a given | |
416 | * gfn, handling slots that are not large page aligned. | |
417 | */ | |
d25797b2 JR |
418 | static int *slot_largepage_idx(gfn_t gfn, |
419 | struct kvm_memory_slot *slot, | |
420 | int level) | |
05da4558 MT |
421 | { |
422 | unsigned long idx; | |
423 | ||
82855413 JR |
424 | idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - |
425 | (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
d25797b2 | 426 | return &slot->lpage_info[level - 2][idx].write_count; |
05da4558 MT |
427 | } |
428 | ||
429 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
430 | { | |
d25797b2 | 431 | struct kvm_memory_slot *slot; |
05da4558 | 432 | int *write_count; |
d25797b2 | 433 | int i; |
05da4558 | 434 | |
a1f4d395 | 435 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
436 | for (i = PT_DIRECTORY_LEVEL; |
437 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
438 | write_count = slot_largepage_idx(gfn, slot, i); | |
439 | *write_count += 1; | |
440 | } | |
05da4558 MT |
441 | } |
442 | ||
443 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
444 | { | |
d25797b2 | 445 | struct kvm_memory_slot *slot; |
05da4558 | 446 | int *write_count; |
d25797b2 | 447 | int i; |
05da4558 | 448 | |
a1f4d395 | 449 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
450 | for (i = PT_DIRECTORY_LEVEL; |
451 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d25797b2 JR |
452 | write_count = slot_largepage_idx(gfn, slot, i); |
453 | *write_count -= 1; | |
454 | WARN_ON(*write_count < 0); | |
455 | } | |
05da4558 MT |
456 | } |
457 | ||
d25797b2 JR |
458 | static int has_wrprotected_page(struct kvm *kvm, |
459 | gfn_t gfn, | |
460 | int level) | |
05da4558 | 461 | { |
2843099f | 462 | struct kvm_memory_slot *slot; |
05da4558 MT |
463 | int *largepage_idx; |
464 | ||
a1f4d395 | 465 | slot = gfn_to_memslot(kvm, gfn); |
05da4558 | 466 | if (slot) { |
d25797b2 | 467 | largepage_idx = slot_largepage_idx(gfn, slot, level); |
05da4558 MT |
468 | return *largepage_idx; |
469 | } | |
470 | ||
471 | return 1; | |
472 | } | |
473 | ||
d25797b2 | 474 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 475 | { |
8f0b1ab6 | 476 | unsigned long page_size; |
d25797b2 | 477 | int i, ret = 0; |
05da4558 | 478 | |
8f0b1ab6 | 479 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 480 | |
d25797b2 JR |
481 | for (i = PT_PAGE_TABLE_LEVEL; |
482 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
483 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
484 | ret = i; | |
485 | else | |
486 | break; | |
487 | } | |
488 | ||
4c2155ce | 489 | return ret; |
05da4558 MT |
490 | } |
491 | ||
d25797b2 | 492 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) |
05da4558 MT |
493 | { |
494 | struct kvm_memory_slot *slot; | |
878403b7 | 495 | int host_level, level, max_level; |
05da4558 MT |
496 | |
497 | slot = gfn_to_memslot(vcpu->kvm, large_gfn); | |
498 | if (slot && slot->dirty_bitmap) | |
d25797b2 | 499 | return PT_PAGE_TABLE_LEVEL; |
05da4558 | 500 | |
d25797b2 JR |
501 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
502 | ||
503 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
504 | return host_level; | |
505 | ||
878403b7 SY |
506 | max_level = kvm_x86_ops->get_lpage_level() < host_level ? |
507 | kvm_x86_ops->get_lpage_level() : host_level; | |
508 | ||
509 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
510 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
511 | break; | |
d25797b2 JR |
512 | |
513 | return level - 1; | |
05da4558 MT |
514 | } |
515 | ||
290fc38d IE |
516 | /* |
517 | * Take gfn and return the reverse mapping to it. | |
290fc38d IE |
518 | */ |
519 | ||
44ad9944 | 520 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) |
290fc38d IE |
521 | { |
522 | struct kvm_memory_slot *slot; | |
05da4558 | 523 | unsigned long idx; |
290fc38d IE |
524 | |
525 | slot = gfn_to_memslot(kvm, gfn); | |
44ad9944 | 526 | if (likely(level == PT_PAGE_TABLE_LEVEL)) |
05da4558 MT |
527 | return &slot->rmap[gfn - slot->base_gfn]; |
528 | ||
82855413 JR |
529 | idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - |
530 | (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
05da4558 | 531 | |
44ad9944 | 532 | return &slot->lpage_info[level - 2][idx].rmap_pde; |
290fc38d IE |
533 | } |
534 | ||
cd4a4e53 AK |
535 | /* |
536 | * Reverse mapping data structures: | |
537 | * | |
290fc38d IE |
538 | * If rmapp bit zero is zero, then rmapp point to the shadw page table entry |
539 | * that points to page_address(page). | |
cd4a4e53 | 540 | * |
290fc38d IE |
541 | * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc |
542 | * containing more mappings. | |
53a27b39 MT |
543 | * |
544 | * Returns the number of rmap entries before the spte was added or zero if | |
545 | * the spte was not added. | |
546 | * | |
cd4a4e53 | 547 | */ |
44ad9944 | 548 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
cd4a4e53 | 549 | { |
4db35314 | 550 | struct kvm_mmu_page *sp; |
cd4a4e53 | 551 | struct kvm_rmap_desc *desc; |
290fc38d | 552 | unsigned long *rmapp; |
53a27b39 | 553 | int i, count = 0; |
cd4a4e53 | 554 | |
43a3795a | 555 | if (!is_rmap_spte(*spte)) |
53a27b39 | 556 | return count; |
4db35314 | 557 | sp = page_header(__pa(spte)); |
2032a93d | 558 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); |
44ad9944 | 559 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
290fc38d | 560 | if (!*rmapp) { |
cd4a4e53 | 561 | rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte); |
290fc38d IE |
562 | *rmapp = (unsigned long)spte; |
563 | } else if (!(*rmapp & 1)) { | |
cd4a4e53 | 564 | rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte); |
714b93da | 565 | desc = mmu_alloc_rmap_desc(vcpu); |
d555c333 AK |
566 | desc->sptes[0] = (u64 *)*rmapp; |
567 | desc->sptes[1] = spte; | |
290fc38d | 568 | *rmapp = (unsigned long)desc | 1; |
cd4a4e53 AK |
569 | } else { |
570 | rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte); | |
290fc38d | 571 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
d555c333 | 572 | while (desc->sptes[RMAP_EXT-1] && desc->more) { |
cd4a4e53 | 573 | desc = desc->more; |
53a27b39 MT |
574 | count += RMAP_EXT; |
575 | } | |
d555c333 | 576 | if (desc->sptes[RMAP_EXT-1]) { |
714b93da | 577 | desc->more = mmu_alloc_rmap_desc(vcpu); |
cd4a4e53 AK |
578 | desc = desc->more; |
579 | } | |
d555c333 | 580 | for (i = 0; desc->sptes[i]; ++i) |
cd4a4e53 | 581 | ; |
d555c333 | 582 | desc->sptes[i] = spte; |
cd4a4e53 | 583 | } |
53a27b39 | 584 | return count; |
cd4a4e53 AK |
585 | } |
586 | ||
290fc38d | 587 | static void rmap_desc_remove_entry(unsigned long *rmapp, |
cd4a4e53 AK |
588 | struct kvm_rmap_desc *desc, |
589 | int i, | |
590 | struct kvm_rmap_desc *prev_desc) | |
591 | { | |
592 | int j; | |
593 | ||
d555c333 | 594 | for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 595 | ; |
d555c333 AK |
596 | desc->sptes[i] = desc->sptes[j]; |
597 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
598 | if (j != 0) |
599 | return; | |
600 | if (!prev_desc && !desc->more) | |
d555c333 | 601 | *rmapp = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
602 | else |
603 | if (prev_desc) | |
604 | prev_desc->more = desc->more; | |
605 | else | |
290fc38d | 606 | *rmapp = (unsigned long)desc->more | 1; |
90cb0529 | 607 | mmu_free_rmap_desc(desc); |
cd4a4e53 AK |
608 | } |
609 | ||
290fc38d | 610 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
cd4a4e53 | 611 | { |
cd4a4e53 AK |
612 | struct kvm_rmap_desc *desc; |
613 | struct kvm_rmap_desc *prev_desc; | |
4db35314 | 614 | struct kvm_mmu_page *sp; |
35149e21 | 615 | pfn_t pfn; |
2032a93d | 616 | gfn_t gfn; |
290fc38d | 617 | unsigned long *rmapp; |
cd4a4e53 AK |
618 | int i; |
619 | ||
43a3795a | 620 | if (!is_rmap_spte(*spte)) |
cd4a4e53 | 621 | return; |
4db35314 | 622 | sp = page_header(__pa(spte)); |
35149e21 | 623 | pfn = spte_to_pfn(*spte); |
7b52345e | 624 | if (*spte & shadow_accessed_mask) |
35149e21 | 625 | kvm_set_pfn_accessed(pfn); |
8dae4445 | 626 | if (is_writable_pte(*spte)) |
acb66dd0 | 627 | kvm_set_pfn_dirty(pfn); |
2032a93d LJ |
628 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); |
629 | rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); | |
290fc38d | 630 | if (!*rmapp) { |
cd4a4e53 AK |
631 | printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte); |
632 | BUG(); | |
290fc38d | 633 | } else if (!(*rmapp & 1)) { |
cd4a4e53 | 634 | rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte); |
290fc38d | 635 | if ((u64 *)*rmapp != spte) { |
cd4a4e53 AK |
636 | printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n", |
637 | spte, *spte); | |
638 | BUG(); | |
639 | } | |
290fc38d | 640 | *rmapp = 0; |
cd4a4e53 AK |
641 | } else { |
642 | rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte); | |
290fc38d | 643 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
cd4a4e53 AK |
644 | prev_desc = NULL; |
645 | while (desc) { | |
d555c333 AK |
646 | for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) |
647 | if (desc->sptes[i] == spte) { | |
290fc38d | 648 | rmap_desc_remove_entry(rmapp, |
714b93da | 649 | desc, i, |
cd4a4e53 AK |
650 | prev_desc); |
651 | return; | |
652 | } | |
653 | prev_desc = desc; | |
654 | desc = desc->more; | |
655 | } | |
186a3e52 | 656 | pr_err("rmap_remove: %p %llx many->many\n", spte, *spte); |
cd4a4e53 AK |
657 | BUG(); |
658 | } | |
659 | } | |
660 | ||
98348e95 | 661 | static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte) |
374cbac0 | 662 | { |
374cbac0 | 663 | struct kvm_rmap_desc *desc; |
98348e95 IE |
664 | u64 *prev_spte; |
665 | int i; | |
666 | ||
667 | if (!*rmapp) | |
668 | return NULL; | |
669 | else if (!(*rmapp & 1)) { | |
670 | if (!spte) | |
671 | return (u64 *)*rmapp; | |
672 | return NULL; | |
673 | } | |
674 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); | |
98348e95 IE |
675 | prev_spte = NULL; |
676 | while (desc) { | |
d555c333 | 677 | for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) { |
98348e95 | 678 | if (prev_spte == spte) |
d555c333 AK |
679 | return desc->sptes[i]; |
680 | prev_spte = desc->sptes[i]; | |
98348e95 IE |
681 | } |
682 | desc = desc->more; | |
683 | } | |
684 | return NULL; | |
685 | } | |
686 | ||
b1a36821 | 687 | static int rmap_write_protect(struct kvm *kvm, u64 gfn) |
98348e95 | 688 | { |
290fc38d | 689 | unsigned long *rmapp; |
374cbac0 | 690 | u64 *spte; |
44ad9944 | 691 | int i, write_protected = 0; |
374cbac0 | 692 | |
44ad9944 | 693 | rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL); |
374cbac0 | 694 | |
98348e95 IE |
695 | spte = rmap_next(kvm, rmapp, NULL); |
696 | while (spte) { | |
374cbac0 | 697 | BUG_ON(!spte); |
374cbac0 | 698 | BUG_ON(!(*spte & PT_PRESENT_MASK)); |
374cbac0 | 699 | rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte); |
8dae4445 | 700 | if (is_writable_pte(*spte)) { |
d555c333 | 701 | __set_spte(spte, *spte & ~PT_WRITABLE_MASK); |
caa5b8a5 ED |
702 | write_protected = 1; |
703 | } | |
9647c14c | 704 | spte = rmap_next(kvm, rmapp, spte); |
374cbac0 | 705 | } |
855149aa | 706 | if (write_protected) { |
35149e21 | 707 | pfn_t pfn; |
855149aa IE |
708 | |
709 | spte = rmap_next(kvm, rmapp, NULL); | |
35149e21 AL |
710 | pfn = spte_to_pfn(*spte); |
711 | kvm_set_pfn_dirty(pfn); | |
855149aa IE |
712 | } |
713 | ||
05da4558 | 714 | /* check for huge page mappings */ |
44ad9944 JR |
715 | for (i = PT_DIRECTORY_LEVEL; |
716 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
717 | rmapp = gfn_to_rmap(kvm, gfn, i); | |
718 | spte = rmap_next(kvm, rmapp, NULL); | |
719 | while (spte) { | |
720 | BUG_ON(!spte); | |
721 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
722 | BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)); | |
723 | pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn); | |
8dae4445 | 724 | if (is_writable_pte(*spte)) { |
44ad9944 JR |
725 | rmap_remove(kvm, spte); |
726 | --kvm->stat.lpages; | |
727 | __set_spte(spte, shadow_trap_nonpresent_pte); | |
728 | spte = NULL; | |
729 | write_protected = 1; | |
730 | } | |
731 | spte = rmap_next(kvm, rmapp, spte); | |
05da4558 | 732 | } |
05da4558 MT |
733 | } |
734 | ||
b1a36821 | 735 | return write_protected; |
374cbac0 AK |
736 | } |
737 | ||
8a8365c5 FD |
738 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
739 | unsigned long data) | |
e930bffe AA |
740 | { |
741 | u64 *spte; | |
742 | int need_tlb_flush = 0; | |
743 | ||
744 | while ((spte = rmap_next(kvm, rmapp, NULL))) { | |
745 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
746 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte); | |
747 | rmap_remove(kvm, spte); | |
d555c333 | 748 | __set_spte(spte, shadow_trap_nonpresent_pte); |
e930bffe AA |
749 | need_tlb_flush = 1; |
750 | } | |
751 | return need_tlb_flush; | |
752 | } | |
753 | ||
8a8365c5 FD |
754 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
755 | unsigned long data) | |
3da0dd43 IE |
756 | { |
757 | int need_flush = 0; | |
758 | u64 *spte, new_spte; | |
759 | pte_t *ptep = (pte_t *)data; | |
760 | pfn_t new_pfn; | |
761 | ||
762 | WARN_ON(pte_huge(*ptep)); | |
763 | new_pfn = pte_pfn(*ptep); | |
764 | spte = rmap_next(kvm, rmapp, NULL); | |
765 | while (spte) { | |
766 | BUG_ON(!is_shadow_present_pte(*spte)); | |
767 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte); | |
768 | need_flush = 1; | |
769 | if (pte_write(*ptep)) { | |
770 | rmap_remove(kvm, spte); | |
771 | __set_spte(spte, shadow_trap_nonpresent_pte); | |
772 | spte = rmap_next(kvm, rmapp, NULL); | |
773 | } else { | |
774 | new_spte = *spte &~ (PT64_BASE_ADDR_MASK); | |
775 | new_spte |= (u64)new_pfn << PAGE_SHIFT; | |
776 | ||
777 | new_spte &= ~PT_WRITABLE_MASK; | |
778 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
8dae4445 | 779 | if (is_writable_pte(*spte)) |
3da0dd43 IE |
780 | kvm_set_pfn_dirty(spte_to_pfn(*spte)); |
781 | __set_spte(spte, new_spte); | |
782 | spte = rmap_next(kvm, rmapp, spte); | |
783 | } | |
784 | } | |
785 | if (need_flush) | |
786 | kvm_flush_remote_tlbs(kvm); | |
787 | ||
788 | return 0; | |
789 | } | |
790 | ||
8a8365c5 FD |
791 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
792 | unsigned long data, | |
3da0dd43 | 793 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, |
8a8365c5 | 794 | unsigned long data)) |
e930bffe | 795 | { |
852e3c19 | 796 | int i, j; |
90bb6fc5 | 797 | int ret; |
e930bffe | 798 | int retval = 0; |
bc6678a3 MT |
799 | struct kvm_memslots *slots; |
800 | ||
90d83dc3 | 801 | slots = kvm_memslots(kvm); |
e930bffe | 802 | |
46a26bf5 MT |
803 | for (i = 0; i < slots->nmemslots; i++) { |
804 | struct kvm_memory_slot *memslot = &slots->memslots[i]; | |
e930bffe AA |
805 | unsigned long start = memslot->userspace_addr; |
806 | unsigned long end; | |
807 | ||
e930bffe AA |
808 | end = start + (memslot->npages << PAGE_SHIFT); |
809 | if (hva >= start && hva < end) { | |
810 | gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT; | |
852e3c19 | 811 | |
90bb6fc5 | 812 | ret = handler(kvm, &memslot->rmap[gfn_offset], data); |
852e3c19 JR |
813 | |
814 | for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) { | |
815 | int idx = gfn_offset; | |
816 | idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j); | |
90bb6fc5 | 817 | ret |= handler(kvm, |
3da0dd43 IE |
818 | &memslot->lpage_info[j][idx].rmap_pde, |
819 | data); | |
852e3c19 | 820 | } |
90bb6fc5 AK |
821 | trace_kvm_age_page(hva, memslot, ret); |
822 | retval |= ret; | |
e930bffe AA |
823 | } |
824 | } | |
825 | ||
826 | return retval; | |
827 | } | |
828 | ||
829 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
830 | { | |
3da0dd43 IE |
831 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
832 | } | |
833 | ||
834 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) | |
835 | { | |
8a8365c5 | 836 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
837 | } |
838 | ||
8a8365c5 FD |
839 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
840 | unsigned long data) | |
e930bffe AA |
841 | { |
842 | u64 *spte; | |
843 | int young = 0; | |
844 | ||
6316e1c8 RR |
845 | /* |
846 | * Emulate the accessed bit for EPT, by checking if this page has | |
847 | * an EPT mapping, and clearing it if it does. On the next access, | |
848 | * a new EPT mapping will be established. | |
849 | * This has some overhead, but not as much as the cost of swapping | |
850 | * out actively used pages or breaking up actively used hugepages. | |
851 | */ | |
534e38b4 | 852 | if (!shadow_accessed_mask) |
6316e1c8 | 853 | return kvm_unmap_rmapp(kvm, rmapp, data); |
534e38b4 | 854 | |
e930bffe AA |
855 | spte = rmap_next(kvm, rmapp, NULL); |
856 | while (spte) { | |
857 | int _young; | |
858 | u64 _spte = *spte; | |
859 | BUG_ON(!(_spte & PT_PRESENT_MASK)); | |
860 | _young = _spte & PT_ACCESSED_MASK; | |
861 | if (_young) { | |
862 | young = 1; | |
863 | clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
864 | } | |
865 | spte = rmap_next(kvm, rmapp, spte); | |
866 | } | |
867 | return young; | |
868 | } | |
869 | ||
53a27b39 MT |
870 | #define RMAP_RECYCLE_THRESHOLD 1000 |
871 | ||
852e3c19 | 872 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
873 | { |
874 | unsigned long *rmapp; | |
852e3c19 JR |
875 | struct kvm_mmu_page *sp; |
876 | ||
877 | sp = page_header(__pa(spte)); | |
53a27b39 | 878 | |
852e3c19 | 879 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 880 | |
3da0dd43 | 881 | kvm_unmap_rmapp(vcpu->kvm, rmapp, 0); |
53a27b39 MT |
882 | kvm_flush_remote_tlbs(vcpu->kvm); |
883 | } | |
884 | ||
e930bffe AA |
885 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
886 | { | |
3da0dd43 | 887 | return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp); |
e930bffe AA |
888 | } |
889 | ||
d6c69ee9 | 890 | #ifdef MMU_DEBUG |
47ad8e68 | 891 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 892 | { |
139bdb2d AK |
893 | u64 *pos; |
894 | u64 *end; | |
895 | ||
47ad8e68 | 896 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 897 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 898 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 899 | pos, *pos); |
6aa8b732 | 900 | return 0; |
139bdb2d | 901 | } |
6aa8b732 AK |
902 | return 1; |
903 | } | |
d6c69ee9 | 904 | #endif |
6aa8b732 | 905 | |
4db35314 | 906 | static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
260746c0 | 907 | { |
4db35314 | 908 | ASSERT(is_empty_shadow_page(sp->spt)); |
7775834a | 909 | hlist_del(&sp->hash_link); |
4db35314 AK |
910 | list_del(&sp->link); |
911 | __free_page(virt_to_page(sp->spt)); | |
2032a93d LJ |
912 | if (!sp->role.direct) |
913 | __free_page(virt_to_page(sp->gfns)); | |
e8ad9a70 | 914 | kmem_cache_free(mmu_page_header_cache, sp); |
f05e70ac | 915 | ++kvm->arch.n_free_mmu_pages; |
260746c0 AK |
916 | } |
917 | ||
cea0f0e7 AK |
918 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
919 | { | |
1ae0a13d | 920 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
921 | } |
922 | ||
25c0de2c | 923 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
2032a93d | 924 | u64 *parent_pte, int direct) |
6aa8b732 | 925 | { |
4db35314 | 926 | struct kvm_mmu_page *sp; |
6aa8b732 | 927 | |
ad312c7c ZX |
928 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp); |
929 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE); | |
2032a93d LJ |
930 | if (!direct) |
931 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, | |
932 | PAGE_SIZE); | |
4db35314 | 933 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
f05e70ac | 934 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
291f26bc | 935 | bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS); |
4db35314 AK |
936 | sp->multimapped = 0; |
937 | sp->parent_pte = parent_pte; | |
f05e70ac | 938 | --vcpu->kvm->arch.n_free_mmu_pages; |
4db35314 | 939 | return sp; |
6aa8b732 AK |
940 | } |
941 | ||
714b93da | 942 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 943 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 AK |
944 | { |
945 | struct kvm_pte_chain *pte_chain; | |
946 | struct hlist_node *node; | |
947 | int i; | |
948 | ||
949 | if (!parent_pte) | |
950 | return; | |
4db35314 AK |
951 | if (!sp->multimapped) { |
952 | u64 *old = sp->parent_pte; | |
cea0f0e7 AK |
953 | |
954 | if (!old) { | |
4db35314 | 955 | sp->parent_pte = parent_pte; |
cea0f0e7 AK |
956 | return; |
957 | } | |
4db35314 | 958 | sp->multimapped = 1; |
714b93da | 959 | pte_chain = mmu_alloc_pte_chain(vcpu); |
4db35314 AK |
960 | INIT_HLIST_HEAD(&sp->parent_ptes); |
961 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); | |
cea0f0e7 AK |
962 | pte_chain->parent_ptes[0] = old; |
963 | } | |
4db35314 | 964 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) { |
cea0f0e7 AK |
965 | if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1]) |
966 | continue; | |
967 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) | |
968 | if (!pte_chain->parent_ptes[i]) { | |
969 | pte_chain->parent_ptes[i] = parent_pte; | |
970 | return; | |
971 | } | |
972 | } | |
714b93da | 973 | pte_chain = mmu_alloc_pte_chain(vcpu); |
cea0f0e7 | 974 | BUG_ON(!pte_chain); |
4db35314 | 975 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); |
cea0f0e7 AK |
976 | pte_chain->parent_ptes[0] = parent_pte; |
977 | } | |
978 | ||
4db35314 | 979 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
980 | u64 *parent_pte) |
981 | { | |
982 | struct kvm_pte_chain *pte_chain; | |
983 | struct hlist_node *node; | |
984 | int i; | |
985 | ||
4db35314 AK |
986 | if (!sp->multimapped) { |
987 | BUG_ON(sp->parent_pte != parent_pte); | |
988 | sp->parent_pte = NULL; | |
cea0f0e7 AK |
989 | return; |
990 | } | |
4db35314 | 991 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) |
cea0f0e7 AK |
992 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { |
993 | if (!pte_chain->parent_ptes[i]) | |
994 | break; | |
995 | if (pte_chain->parent_ptes[i] != parent_pte) | |
996 | continue; | |
697fe2e2 AK |
997 | while (i + 1 < NR_PTE_CHAIN_ENTRIES |
998 | && pte_chain->parent_ptes[i + 1]) { | |
cea0f0e7 AK |
999 | pte_chain->parent_ptes[i] |
1000 | = pte_chain->parent_ptes[i + 1]; | |
1001 | ++i; | |
1002 | } | |
1003 | pte_chain->parent_ptes[i] = NULL; | |
697fe2e2 AK |
1004 | if (i == 0) { |
1005 | hlist_del(&pte_chain->link); | |
90cb0529 | 1006 | mmu_free_pte_chain(pte_chain); |
4db35314 AK |
1007 | if (hlist_empty(&sp->parent_ptes)) { |
1008 | sp->multimapped = 0; | |
1009 | sp->parent_pte = NULL; | |
697fe2e2 AK |
1010 | } |
1011 | } | |
cea0f0e7 AK |
1012 | return; |
1013 | } | |
1014 | BUG(); | |
1015 | } | |
1016 | ||
6b18493d | 1017 | static void mmu_parent_walk(struct kvm_mmu_page *sp, mmu_parent_walk_fn fn) |
ad8cfbe3 MT |
1018 | { |
1019 | struct kvm_pte_chain *pte_chain; | |
1020 | struct hlist_node *node; | |
1021 | struct kvm_mmu_page *parent_sp; | |
1022 | int i; | |
1023 | ||
1024 | if (!sp->multimapped && sp->parent_pte) { | |
1025 | parent_sp = page_header(__pa(sp->parent_pte)); | |
1047df1f | 1026 | fn(parent_sp, sp->parent_pte); |
ad8cfbe3 MT |
1027 | return; |
1028 | } | |
1047df1f | 1029 | |
ad8cfbe3 MT |
1030 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) |
1031 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { | |
1047df1f XG |
1032 | u64 *spte = pte_chain->parent_ptes[i]; |
1033 | ||
1034 | if (!spte) | |
ad8cfbe3 | 1035 | break; |
1047df1f XG |
1036 | parent_sp = page_header(__pa(spte)); |
1037 | fn(parent_sp, spte); | |
ad8cfbe3 MT |
1038 | } |
1039 | } | |
1040 | ||
1047df1f XG |
1041 | static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte); |
1042 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) | |
0074ff63 | 1043 | { |
1047df1f | 1044 | mmu_parent_walk(sp, mark_unsync); |
0074ff63 MT |
1045 | } |
1046 | ||
1047df1f | 1047 | static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte) |
0074ff63 | 1048 | { |
1047df1f | 1049 | unsigned int index; |
0074ff63 | 1050 | |
1047df1f XG |
1051 | index = spte - sp->spt; |
1052 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1053 | return; |
1047df1f | 1054 | if (sp->unsync_children++) |
0074ff63 | 1055 | return; |
1047df1f | 1056 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1057 | } |
1058 | ||
d761a501 AK |
1059 | static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu, |
1060 | struct kvm_mmu_page *sp) | |
1061 | { | |
1062 | int i; | |
1063 | ||
1064 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1065 | sp->spt[i] = shadow_trap_nonpresent_pte; | |
1066 | } | |
1067 | ||
e8bc217a | 1068 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
be71e061 | 1069 | struct kvm_mmu_page *sp, bool clear_unsync) |
e8bc217a MT |
1070 | { |
1071 | return 1; | |
1072 | } | |
1073 | ||
a7052897 MT |
1074 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1075 | { | |
1076 | } | |
1077 | ||
60c8aec6 MT |
1078 | #define KVM_PAGE_ARRAY_NR 16 |
1079 | ||
1080 | struct kvm_mmu_pages { | |
1081 | struct mmu_page_and_offset { | |
1082 | struct kvm_mmu_page *sp; | |
1083 | unsigned int idx; | |
1084 | } page[KVM_PAGE_ARRAY_NR]; | |
1085 | unsigned int nr; | |
1086 | }; | |
1087 | ||
0074ff63 MT |
1088 | #define for_each_unsync_children(bitmap, idx) \ |
1089 | for (idx = find_first_bit(bitmap, 512); \ | |
1090 | idx < 512; \ | |
1091 | idx = find_next_bit(bitmap, 512, idx+1)) | |
1092 | ||
cded19f3 HE |
1093 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1094 | int idx) | |
4731d4c7 | 1095 | { |
60c8aec6 | 1096 | int i; |
4731d4c7 | 1097 | |
60c8aec6 MT |
1098 | if (sp->unsync) |
1099 | for (i=0; i < pvec->nr; i++) | |
1100 | if (pvec->page[i].sp == sp) | |
1101 | return 0; | |
1102 | ||
1103 | pvec->page[pvec->nr].sp = sp; | |
1104 | pvec->page[pvec->nr].idx = idx; | |
1105 | pvec->nr++; | |
1106 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1107 | } | |
1108 | ||
1109 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1110 | struct kvm_mmu_pages *pvec) | |
1111 | { | |
1112 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1113 | |
0074ff63 | 1114 | for_each_unsync_children(sp->unsync_child_bitmap, i) { |
7a8f1a74 | 1115 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1116 | u64 ent = sp->spt[i]; |
1117 | ||
7a8f1a74 XG |
1118 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) |
1119 | goto clear_child_bitmap; | |
1120 | ||
1121 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1122 | ||
1123 | if (child->unsync_children) { | |
1124 | if (mmu_pages_add(pvec, child, i)) | |
1125 | return -ENOSPC; | |
1126 | ||
1127 | ret = __mmu_unsync_walk(child, pvec); | |
1128 | if (!ret) | |
1129 | goto clear_child_bitmap; | |
1130 | else if (ret > 0) | |
1131 | nr_unsync_leaf += ret; | |
1132 | else | |
1133 | return ret; | |
1134 | } else if (child->unsync) { | |
1135 | nr_unsync_leaf++; | |
1136 | if (mmu_pages_add(pvec, child, i)) | |
1137 | return -ENOSPC; | |
1138 | } else | |
1139 | goto clear_child_bitmap; | |
1140 | ||
1141 | continue; | |
1142 | ||
1143 | clear_child_bitmap: | |
1144 | __clear_bit(i, sp->unsync_child_bitmap); | |
1145 | sp->unsync_children--; | |
1146 | WARN_ON((int)sp->unsync_children < 0); | |
4731d4c7 MT |
1147 | } |
1148 | ||
4731d4c7 | 1149 | |
60c8aec6 MT |
1150 | return nr_unsync_leaf; |
1151 | } | |
1152 | ||
1153 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1154 | struct kvm_mmu_pages *pvec) | |
1155 | { | |
1156 | if (!sp->unsync_children) | |
1157 | return 0; | |
1158 | ||
1159 | mmu_pages_add(pvec, sp, 0); | |
1160 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1161 | } |
1162 | ||
4731d4c7 MT |
1163 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1164 | { | |
1165 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1166 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1167 | sp->unsync = 0; |
1168 | --kvm->stat.mmu_unsync; | |
1169 | } | |
1170 | ||
7775834a XG |
1171 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1172 | struct list_head *invalid_list); | |
1173 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1174 | struct list_head *invalid_list); | |
4731d4c7 | 1175 | |
f41d335a XG |
1176 | #define for_each_gfn_sp(kvm, sp, gfn, pos) \ |
1177 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1178 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1179 | if ((sp)->gfn != (gfn)) {} else | |
1180 | ||
f41d335a XG |
1181 | #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \ |
1182 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1183 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1184 | if ((sp)->gfn != (gfn) || (sp)->role.direct || \ | |
1185 | (sp)->role.invalid) {} else | |
1186 | ||
f918b443 | 1187 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1188 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1189 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1190 | { |
5b7e0102 | 1191 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1192 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1193 | return 1; |
1194 | } | |
1195 | ||
f918b443 | 1196 | if (clear_unsync) |
1d9dc7e0 | 1197 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1198 | |
be71e061 | 1199 | if (vcpu->arch.mmu.sync_page(vcpu, sp, clear_unsync)) { |
d98ba053 | 1200 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1201 | return 1; |
1202 | } | |
1203 | ||
1204 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1205 | return 0; |
1206 | } | |
1207 | ||
1d9dc7e0 XG |
1208 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1209 | struct kvm_mmu_page *sp) | |
1210 | { | |
d98ba053 | 1211 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1212 | int ret; |
1213 | ||
d98ba053 | 1214 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1215 | if (ret) |
d98ba053 XG |
1216 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1217 | ||
1d9dc7e0 XG |
1218 | return ret; |
1219 | } | |
1220 | ||
d98ba053 XG |
1221 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1222 | struct list_head *invalid_list) | |
1d9dc7e0 | 1223 | { |
d98ba053 | 1224 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1225 | } |
1226 | ||
9f1a122f XG |
1227 | /* @gfn should be write-protected at the call site */ |
1228 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1229 | { | |
9f1a122f | 1230 | struct kvm_mmu_page *s; |
f41d335a | 1231 | struct hlist_node *node; |
d98ba053 | 1232 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1233 | bool flush = false; |
1234 | ||
f41d335a | 1235 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1236 | if (!s->unsync) |
9f1a122f XG |
1237 | continue; |
1238 | ||
1239 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
1240 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || | |
be71e061 | 1241 | (vcpu->arch.mmu.sync_page(vcpu, s, true))) { |
d98ba053 | 1242 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1243 | continue; |
1244 | } | |
1245 | kvm_unlink_unsync_page(vcpu->kvm, s); | |
1246 | flush = true; | |
1247 | } | |
1248 | ||
d98ba053 | 1249 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f XG |
1250 | if (flush) |
1251 | kvm_mmu_flush_tlb(vcpu); | |
1252 | } | |
1253 | ||
60c8aec6 MT |
1254 | struct mmu_page_path { |
1255 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1256 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1257 | }; |
1258 | ||
60c8aec6 MT |
1259 | #define for_each_sp(pvec, sp, parents, i) \ |
1260 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1261 | sp = pvec.page[i].sp; \ | |
1262 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1263 | i = mmu_pages_next(&pvec, &parents, i)) | |
1264 | ||
cded19f3 HE |
1265 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1266 | struct mmu_page_path *parents, | |
1267 | int i) | |
60c8aec6 MT |
1268 | { |
1269 | int n; | |
1270 | ||
1271 | for (n = i+1; n < pvec->nr; n++) { | |
1272 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1273 | ||
1274 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1275 | parents->idx[0] = pvec->page[n].idx; | |
1276 | return n; | |
1277 | } | |
1278 | ||
1279 | parents->parent[sp->role.level-2] = sp; | |
1280 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1281 | } | |
1282 | ||
1283 | return n; | |
1284 | } | |
1285 | ||
cded19f3 | 1286 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1287 | { |
60c8aec6 MT |
1288 | struct kvm_mmu_page *sp; |
1289 | unsigned int level = 0; | |
1290 | ||
1291 | do { | |
1292 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1293 | |
60c8aec6 MT |
1294 | sp = parents->parent[level]; |
1295 | if (!sp) | |
1296 | return; | |
1297 | ||
1298 | --sp->unsync_children; | |
1299 | WARN_ON((int)sp->unsync_children < 0); | |
1300 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1301 | level++; | |
1302 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1303 | } |
1304 | ||
60c8aec6 MT |
1305 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1306 | struct mmu_page_path *parents, | |
1307 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1308 | { |
60c8aec6 MT |
1309 | parents->parent[parent->role.level-1] = NULL; |
1310 | pvec->nr = 0; | |
1311 | } | |
4731d4c7 | 1312 | |
60c8aec6 MT |
1313 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1314 | struct kvm_mmu_page *parent) | |
1315 | { | |
1316 | int i; | |
1317 | struct kvm_mmu_page *sp; | |
1318 | struct mmu_page_path parents; | |
1319 | struct kvm_mmu_pages pages; | |
d98ba053 | 1320 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
1321 | |
1322 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1323 | while (mmu_unsync_walk(parent, &pages)) { | |
b1a36821 MT |
1324 | int protected = 0; |
1325 | ||
1326 | for_each_sp(pages, sp, parents, i) | |
1327 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1328 | ||
1329 | if (protected) | |
1330 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1331 | ||
60c8aec6 | 1332 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 1333 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1334 | mmu_pages_clear_parents(&parents); |
1335 | } | |
d98ba053 | 1336 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 1337 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1338 | kvm_mmu_pages_init(parent, &parents, &pages); |
1339 | } | |
4731d4c7 MT |
1340 | } |
1341 | ||
cea0f0e7 AK |
1342 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1343 | gfn_t gfn, | |
1344 | gva_t gaddr, | |
1345 | unsigned level, | |
f6e2c02b | 1346 | int direct, |
41074d07 | 1347 | unsigned access, |
f7d9c7b7 | 1348 | u64 *parent_pte) |
cea0f0e7 AK |
1349 | { |
1350 | union kvm_mmu_page_role role; | |
cea0f0e7 | 1351 | unsigned quadrant; |
9f1a122f | 1352 | struct kvm_mmu_page *sp; |
f41d335a | 1353 | struct hlist_node *node; |
9f1a122f | 1354 | bool need_sync = false; |
cea0f0e7 | 1355 | |
a770f6f2 | 1356 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1357 | role.level = level; |
f6e2c02b | 1358 | role.direct = direct; |
84b0c8c6 | 1359 | if (role.direct) |
5b7e0102 | 1360 | role.cr4_pae = 0; |
41074d07 | 1361 | role.access = access; |
b66d8000 | 1362 | if (!tdp_enabled && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { |
cea0f0e7 AK |
1363 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1364 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1365 | role.quadrant = quadrant; | |
1366 | } | |
f41d335a | 1367 | for_each_gfn_sp(vcpu->kvm, sp, gfn, node) { |
7ae680eb XG |
1368 | if (!need_sync && sp->unsync) |
1369 | need_sync = true; | |
4731d4c7 | 1370 | |
7ae680eb XG |
1371 | if (sp->role.word != role.word) |
1372 | continue; | |
4731d4c7 | 1373 | |
7ae680eb XG |
1374 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
1375 | break; | |
e02aa901 | 1376 | |
7ae680eb XG |
1377 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
1378 | if (sp->unsync_children) { | |
a8eeb04a | 1379 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
7ae680eb XG |
1380 | kvm_mmu_mark_parents_unsync(sp); |
1381 | } else if (sp->unsync) | |
1382 | kvm_mmu_mark_parents_unsync(sp); | |
e02aa901 | 1383 | |
7ae680eb XG |
1384 | trace_kvm_mmu_get_page(sp, false); |
1385 | return sp; | |
1386 | } | |
dfc5aa00 | 1387 | ++vcpu->kvm->stat.mmu_cache_miss; |
2032a93d | 1388 | sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct); |
4db35314 AK |
1389 | if (!sp) |
1390 | return sp; | |
4db35314 AK |
1391 | sp->gfn = gfn; |
1392 | sp->role = role; | |
7ae680eb XG |
1393 | hlist_add_head(&sp->hash_link, |
1394 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 1395 | if (!direct) { |
b1a36821 MT |
1396 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1397 | kvm_flush_remote_tlbs(vcpu->kvm); | |
9f1a122f XG |
1398 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
1399 | kvm_sync_pages(vcpu, gfn); | |
1400 | ||
4731d4c7 MT |
1401 | account_shadowed(vcpu->kvm, gfn); |
1402 | } | |
131d8279 AK |
1403 | if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte) |
1404 | vcpu->arch.mmu.prefetch_page(vcpu, sp); | |
1405 | else | |
1406 | nonpaging_prefetch_page(vcpu, sp); | |
f691fe1d | 1407 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1408 | return sp; |
cea0f0e7 AK |
1409 | } |
1410 | ||
2d11123a AK |
1411 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1412 | struct kvm_vcpu *vcpu, u64 addr) | |
1413 | { | |
1414 | iterator->addr = addr; | |
1415 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1416 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
1417 | if (iterator->level == PT32E_ROOT_LEVEL) { | |
1418 | iterator->shadow_addr | |
1419 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
1420 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
1421 | --iterator->level; | |
1422 | if (!iterator->shadow_addr) | |
1423 | iterator->level = 0; | |
1424 | } | |
1425 | } | |
1426 | ||
1427 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
1428 | { | |
1429 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
1430 | return false; | |
4d88954d MT |
1431 | |
1432 | if (iterator->level == PT_PAGE_TABLE_LEVEL) | |
1433 | if (is_large_pte(*iterator->sptep)) | |
1434 | return false; | |
1435 | ||
2d11123a AK |
1436 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
1437 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
1438 | return true; | |
1439 | } | |
1440 | ||
1441 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) | |
1442 | { | |
1443 | iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK; | |
1444 | --iterator->level; | |
1445 | } | |
1446 | ||
90cb0529 | 1447 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 1448 | struct kvm_mmu_page *sp) |
a436036b | 1449 | { |
697fe2e2 AK |
1450 | unsigned i; |
1451 | u64 *pt; | |
1452 | u64 ent; | |
1453 | ||
4db35314 | 1454 | pt = sp->spt; |
697fe2e2 | 1455 | |
697fe2e2 AK |
1456 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { |
1457 | ent = pt[i]; | |
1458 | ||
05da4558 | 1459 | if (is_shadow_present_pte(ent)) { |
776e6633 | 1460 | if (!is_last_spte(ent, sp->role.level)) { |
05da4558 MT |
1461 | ent &= PT64_BASE_ADDR_MASK; |
1462 | mmu_page_remove_parent_pte(page_header(ent), | |
1463 | &pt[i]); | |
1464 | } else { | |
776e6633 MT |
1465 | if (is_large_pte(ent)) |
1466 | --kvm->stat.lpages; | |
05da4558 MT |
1467 | rmap_remove(kvm, &pt[i]); |
1468 | } | |
1469 | } | |
c7addb90 | 1470 | pt[i] = shadow_trap_nonpresent_pte; |
697fe2e2 | 1471 | } |
a436036b AK |
1472 | } |
1473 | ||
4db35314 | 1474 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1475 | { |
4db35314 | 1476 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
1477 | } |
1478 | ||
12b7d28f AK |
1479 | static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm) |
1480 | { | |
1481 | int i; | |
988a2cae | 1482 | struct kvm_vcpu *vcpu; |
12b7d28f | 1483 | |
988a2cae GN |
1484 | kvm_for_each_vcpu(i, vcpu, kvm) |
1485 | vcpu->arch.last_pte_updated = NULL; | |
12b7d28f AK |
1486 | } |
1487 | ||
31aa2b44 | 1488 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b AK |
1489 | { |
1490 | u64 *parent_pte; | |
1491 | ||
4db35314 AK |
1492 | while (sp->multimapped || sp->parent_pte) { |
1493 | if (!sp->multimapped) | |
1494 | parent_pte = sp->parent_pte; | |
a436036b AK |
1495 | else { |
1496 | struct kvm_pte_chain *chain; | |
1497 | ||
4db35314 | 1498 | chain = container_of(sp->parent_ptes.first, |
a436036b AK |
1499 | struct kvm_pte_chain, link); |
1500 | parent_pte = chain->parent_ptes[0]; | |
1501 | } | |
697fe2e2 | 1502 | BUG_ON(!parent_pte); |
4db35314 | 1503 | kvm_mmu_put_page(sp, parent_pte); |
d555c333 | 1504 | __set_spte(parent_pte, shadow_trap_nonpresent_pte); |
a436036b | 1505 | } |
31aa2b44 AK |
1506 | } |
1507 | ||
60c8aec6 | 1508 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
1509 | struct kvm_mmu_page *parent, |
1510 | struct list_head *invalid_list) | |
4731d4c7 | 1511 | { |
60c8aec6 MT |
1512 | int i, zapped = 0; |
1513 | struct mmu_page_path parents; | |
1514 | struct kvm_mmu_pages pages; | |
4731d4c7 | 1515 | |
60c8aec6 | 1516 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1517 | return 0; |
60c8aec6 MT |
1518 | |
1519 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1520 | while (mmu_unsync_walk(parent, &pages)) { | |
1521 | struct kvm_mmu_page *sp; | |
1522 | ||
1523 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 1524 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 1525 | mmu_pages_clear_parents(&parents); |
77662e00 | 1526 | zapped++; |
60c8aec6 | 1527 | } |
60c8aec6 MT |
1528 | kvm_mmu_pages_init(parent, &parents, &pages); |
1529 | } | |
1530 | ||
1531 | return zapped; | |
4731d4c7 MT |
1532 | } |
1533 | ||
7775834a XG |
1534 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1535 | struct list_head *invalid_list) | |
31aa2b44 | 1536 | { |
4731d4c7 | 1537 | int ret; |
f691fe1d | 1538 | |
7775834a | 1539 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 1540 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 1541 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 1542 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 1543 | kvm_mmu_unlink_parents(kvm, sp); |
f6e2c02b | 1544 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 1545 | unaccount_shadowed(kvm, sp->gfn); |
4731d4c7 MT |
1546 | if (sp->unsync) |
1547 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 1548 | if (!sp->root_count) { |
54a4f023 GJ |
1549 | /* Count self */ |
1550 | ret++; | |
7775834a | 1551 | list_move(&sp->link, invalid_list); |
2e53d63a | 1552 | } else { |
5b5c6a5a | 1553 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
2e53d63a MT |
1554 | kvm_reload_remote_mmus(kvm); |
1555 | } | |
7775834a XG |
1556 | |
1557 | sp->role.invalid = 1; | |
12b7d28f | 1558 | kvm_mmu_reset_last_pte_updated(kvm); |
4731d4c7 | 1559 | return ret; |
a436036b AK |
1560 | } |
1561 | ||
7775834a XG |
1562 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
1563 | struct list_head *invalid_list) | |
1564 | { | |
1565 | struct kvm_mmu_page *sp; | |
1566 | ||
1567 | if (list_empty(invalid_list)) | |
1568 | return; | |
1569 | ||
1570 | kvm_flush_remote_tlbs(kvm); | |
1571 | ||
1572 | do { | |
1573 | sp = list_first_entry(invalid_list, struct kvm_mmu_page, link); | |
1574 | WARN_ON(!sp->role.invalid || sp->root_count); | |
1575 | kvm_mmu_free_page(kvm, sp); | |
1576 | } while (!list_empty(invalid_list)); | |
1577 | ||
1578 | } | |
1579 | ||
82ce2c96 IE |
1580 | /* |
1581 | * Changing the number of mmu pages allocated to the vm | |
1582 | * Note: if kvm_nr_mmu_pages is too small, you will get dead lock | |
1583 | */ | |
1584 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages) | |
1585 | { | |
025dbbf3 | 1586 | int used_pages; |
d98ba053 | 1587 | LIST_HEAD(invalid_list); |
025dbbf3 MT |
1588 | |
1589 | used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages; | |
1590 | used_pages = max(0, used_pages); | |
1591 | ||
82ce2c96 IE |
1592 | /* |
1593 | * If we set the number of mmu pages to be smaller be than the | |
1594 | * number of actived pages , we must to free some mmu pages before we | |
1595 | * change the value | |
1596 | */ | |
1597 | ||
025dbbf3 | 1598 | if (used_pages > kvm_nr_mmu_pages) { |
77662e00 XG |
1599 | while (used_pages > kvm_nr_mmu_pages && |
1600 | !list_empty(&kvm->arch.active_mmu_pages)) { | |
82ce2c96 IE |
1601 | struct kvm_mmu_page *page; |
1602 | ||
f05e70ac | 1603 | page = container_of(kvm->arch.active_mmu_pages.prev, |
82ce2c96 | 1604 | struct kvm_mmu_page, link); |
d98ba053 XG |
1605 | used_pages -= kvm_mmu_prepare_zap_page(kvm, page, |
1606 | &invalid_list); | |
82ce2c96 | 1607 | } |
d98ba053 | 1608 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
77662e00 | 1609 | kvm_nr_mmu_pages = used_pages; |
f05e70ac | 1610 | kvm->arch.n_free_mmu_pages = 0; |
82ce2c96 IE |
1611 | } |
1612 | else | |
f05e70ac ZX |
1613 | kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages |
1614 | - kvm->arch.n_alloc_mmu_pages; | |
82ce2c96 | 1615 | |
f05e70ac | 1616 | kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages; |
82ce2c96 IE |
1617 | } |
1618 | ||
f67a46f4 | 1619 | static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 1620 | { |
4db35314 | 1621 | struct kvm_mmu_page *sp; |
f41d335a | 1622 | struct hlist_node *node; |
d98ba053 | 1623 | LIST_HEAD(invalid_list); |
a436036b AK |
1624 | int r; |
1625 | ||
b8688d51 | 1626 | pgprintk("%s: looking for gfn %lx\n", __func__, gfn); |
a436036b | 1627 | r = 0; |
f41d335a XG |
1628 | |
1629 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { | |
7ae680eb XG |
1630 | pgprintk("%s: gfn %lx role %x\n", __func__, gfn, |
1631 | sp->role.word); | |
1632 | r = 1; | |
f41d335a | 1633 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 1634 | } |
d98ba053 | 1635 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
a436036b | 1636 | return r; |
cea0f0e7 AK |
1637 | } |
1638 | ||
f67a46f4 | 1639 | static void mmu_unshadow(struct kvm *kvm, gfn_t gfn) |
97a0a01e | 1640 | { |
4db35314 | 1641 | struct kvm_mmu_page *sp; |
f41d335a | 1642 | struct hlist_node *node; |
d98ba053 | 1643 | LIST_HEAD(invalid_list); |
97a0a01e | 1644 | |
f41d335a | 1645 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { |
7ae680eb XG |
1646 | pgprintk("%s: zap %lx %x\n", |
1647 | __func__, gfn, sp->role.word); | |
f41d335a | 1648 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
97a0a01e | 1649 | } |
d98ba053 | 1650 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
97a0a01e AK |
1651 | } |
1652 | ||
38c335f1 | 1653 | static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn) |
6aa8b732 | 1654 | { |
bc6678a3 | 1655 | int slot = memslot_id(kvm, gfn); |
4db35314 | 1656 | struct kvm_mmu_page *sp = page_header(__pa(pte)); |
6aa8b732 | 1657 | |
291f26bc | 1658 | __set_bit(slot, sp->slot_bitmap); |
6aa8b732 AK |
1659 | } |
1660 | ||
6844dec6 MT |
1661 | static void mmu_convert_notrap(struct kvm_mmu_page *sp) |
1662 | { | |
1663 | int i; | |
1664 | u64 *pt = sp->spt; | |
1665 | ||
1666 | if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte) | |
1667 | return; | |
1668 | ||
1669 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
1670 | if (pt[i] == shadow_notrap_nonpresent_pte) | |
d555c333 | 1671 | __set_spte(&pt[i], shadow_trap_nonpresent_pte); |
6844dec6 MT |
1672 | } |
1673 | } | |
1674 | ||
74be52e3 SY |
1675 | /* |
1676 | * The function is based on mtrr_type_lookup() in | |
1677 | * arch/x86/kernel/cpu/mtrr/generic.c | |
1678 | */ | |
1679 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
1680 | u64 start, u64 end) | |
1681 | { | |
1682 | int i; | |
1683 | u64 base, mask; | |
1684 | u8 prev_match, curr_match; | |
1685 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
1686 | ||
1687 | if (!mtrr_state->enabled) | |
1688 | return 0xFF; | |
1689 | ||
1690 | /* Make end inclusive end, instead of exclusive */ | |
1691 | end--; | |
1692 | ||
1693 | /* Look in fixed ranges. Just return the type as per start */ | |
1694 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
1695 | int idx; | |
1696 | ||
1697 | if (start < 0x80000) { | |
1698 | idx = 0; | |
1699 | idx += (start >> 16); | |
1700 | return mtrr_state->fixed_ranges[idx]; | |
1701 | } else if (start < 0xC0000) { | |
1702 | idx = 1 * 8; | |
1703 | idx += ((start - 0x80000) >> 14); | |
1704 | return mtrr_state->fixed_ranges[idx]; | |
1705 | } else if (start < 0x1000000) { | |
1706 | idx = 3 * 8; | |
1707 | idx += ((start - 0xC0000) >> 12); | |
1708 | return mtrr_state->fixed_ranges[idx]; | |
1709 | } | |
1710 | } | |
1711 | ||
1712 | /* | |
1713 | * Look in variable ranges | |
1714 | * Look of multiple ranges matching this address and pick type | |
1715 | * as per MTRR precedence | |
1716 | */ | |
1717 | if (!(mtrr_state->enabled & 2)) | |
1718 | return mtrr_state->def_type; | |
1719 | ||
1720 | prev_match = 0xFF; | |
1721 | for (i = 0; i < num_var_ranges; ++i) { | |
1722 | unsigned short start_state, end_state; | |
1723 | ||
1724 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
1725 | continue; | |
1726 | ||
1727 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
1728 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
1729 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
1730 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
1731 | ||
1732 | start_state = ((start & mask) == (base & mask)); | |
1733 | end_state = ((end & mask) == (base & mask)); | |
1734 | if (start_state != end_state) | |
1735 | return 0xFE; | |
1736 | ||
1737 | if ((start & mask) != (base & mask)) | |
1738 | continue; | |
1739 | ||
1740 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
1741 | if (prev_match == 0xFF) { | |
1742 | prev_match = curr_match; | |
1743 | continue; | |
1744 | } | |
1745 | ||
1746 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
1747 | curr_match == MTRR_TYPE_UNCACHABLE) | |
1748 | return MTRR_TYPE_UNCACHABLE; | |
1749 | ||
1750 | if ((prev_match == MTRR_TYPE_WRBACK && | |
1751 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
1752 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
1753 | curr_match == MTRR_TYPE_WRBACK)) { | |
1754 | prev_match = MTRR_TYPE_WRTHROUGH; | |
1755 | curr_match = MTRR_TYPE_WRTHROUGH; | |
1756 | } | |
1757 | ||
1758 | if (prev_match != curr_match) | |
1759 | return MTRR_TYPE_UNCACHABLE; | |
1760 | } | |
1761 | ||
1762 | if (prev_match != 0xFF) | |
1763 | return prev_match; | |
1764 | ||
1765 | return mtrr_state->def_type; | |
1766 | } | |
1767 | ||
4b12f0de | 1768 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
1769 | { |
1770 | u8 mtrr; | |
1771 | ||
1772 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
1773 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
1774 | if (mtrr == 0xfe || mtrr == 0xff) | |
1775 | mtrr = MTRR_TYPE_WRBACK; | |
1776 | return mtrr; | |
1777 | } | |
4b12f0de | 1778 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 1779 | |
9cf5cf5a XG |
1780 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
1781 | { | |
1782 | trace_kvm_mmu_unsync_page(sp); | |
1783 | ++vcpu->kvm->stat.mmu_unsync; | |
1784 | sp->unsync = 1; | |
1785 | ||
1786 | kvm_mmu_mark_parents_unsync(sp); | |
1787 | mmu_convert_notrap(sp); | |
1788 | } | |
1789 | ||
1790 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 1791 | { |
4731d4c7 | 1792 | struct kvm_mmu_page *s; |
f41d335a | 1793 | struct hlist_node *node; |
9cf5cf5a | 1794 | |
f41d335a | 1795 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1796 | if (s->unsync) |
4731d4c7 | 1797 | continue; |
9cf5cf5a XG |
1798 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
1799 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 1800 | } |
4731d4c7 MT |
1801 | } |
1802 | ||
1803 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
1804 | bool can_unsync) | |
1805 | { | |
9cf5cf5a | 1806 | struct kvm_mmu_page *s; |
f41d335a | 1807 | struct hlist_node *node; |
9cf5cf5a XG |
1808 | bool need_unsync = false; |
1809 | ||
f41d335a | 1810 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
36a2e677 XG |
1811 | if (!can_unsync) |
1812 | return 1; | |
1813 | ||
9cf5cf5a | 1814 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1815 | return 1; |
9cf5cf5a XG |
1816 | |
1817 | if (!need_unsync && !s->unsync) { | |
36a2e677 | 1818 | if (!oos_shadow) |
9cf5cf5a XG |
1819 | return 1; |
1820 | need_unsync = true; | |
1821 | } | |
4731d4c7 | 1822 | } |
9cf5cf5a XG |
1823 | if (need_unsync) |
1824 | kvm_unsync_pages(vcpu, gfn); | |
4731d4c7 MT |
1825 | return 0; |
1826 | } | |
1827 | ||
d555c333 | 1828 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd | 1829 | unsigned pte_access, int user_fault, |
852e3c19 | 1830 | int write_fault, int dirty, int level, |
c2d0ee46 | 1831 | gfn_t gfn, pfn_t pfn, bool speculative, |
1403283a | 1832 | bool can_unsync, bool reset_host_protection) |
1c4f1fd6 AK |
1833 | { |
1834 | u64 spte; | |
1e73f9dd | 1835 | int ret = 0; |
64d4d521 | 1836 | |
1c4f1fd6 AK |
1837 | /* |
1838 | * We don't set the accessed bit, since we sometimes want to see | |
1839 | * whether the guest actually used the pte (in order to detect | |
1840 | * demand paging). | |
1841 | */ | |
7b52345e | 1842 | spte = shadow_base_present_pte | shadow_dirty_mask; |
947da538 | 1843 | if (!speculative) |
3201b5d9 | 1844 | spte |= shadow_accessed_mask; |
1c4f1fd6 AK |
1845 | if (!dirty) |
1846 | pte_access &= ~ACC_WRITE_MASK; | |
7b52345e SY |
1847 | if (pte_access & ACC_EXEC_MASK) |
1848 | spte |= shadow_x_mask; | |
1849 | else | |
1850 | spte |= shadow_nx_mask; | |
1c4f1fd6 | 1851 | if (pte_access & ACC_USER_MASK) |
7b52345e | 1852 | spte |= shadow_user_mask; |
852e3c19 | 1853 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 1854 | spte |= PT_PAGE_SIZE_MASK; |
4b12f0de SY |
1855 | if (tdp_enabled) |
1856 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, | |
1857 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 1858 | |
1403283a IE |
1859 | if (reset_host_protection) |
1860 | spte |= SPTE_HOST_WRITEABLE; | |
1861 | ||
35149e21 | 1862 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 AK |
1863 | |
1864 | if ((pte_access & ACC_WRITE_MASK) | |
8184dd38 AK |
1865 | || (!tdp_enabled && write_fault && !is_write_protection(vcpu) |
1866 | && !user_fault)) { | |
1c4f1fd6 | 1867 | |
852e3c19 JR |
1868 | if (level > PT_PAGE_TABLE_LEVEL && |
1869 | has_wrprotected_page(vcpu->kvm, gfn, level)) { | |
38187c83 | 1870 | ret = 1; |
6d74229f | 1871 | rmap_remove(vcpu->kvm, sptep); |
38187c83 MT |
1872 | spte = shadow_trap_nonpresent_pte; |
1873 | goto set_pte; | |
1874 | } | |
1875 | ||
1c4f1fd6 | 1876 | spte |= PT_WRITABLE_MASK; |
1c4f1fd6 | 1877 | |
69325a12 AK |
1878 | if (!tdp_enabled && !(pte_access & ACC_WRITE_MASK)) |
1879 | spte &= ~PT_USER_MASK; | |
1880 | ||
ecc5589f MT |
1881 | /* |
1882 | * Optimization: for pte sync, if spte was writable the hash | |
1883 | * lookup is unnecessary (and expensive). Write protection | |
1884 | * is responsibility of mmu_get_page / kvm_sync_page. | |
1885 | * Same reasoning can be applied to dirty page accounting. | |
1886 | */ | |
8dae4445 | 1887 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
1888 | goto set_pte; |
1889 | ||
4731d4c7 | 1890 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
1c4f1fd6 | 1891 | pgprintk("%s: found shadow page for %lx, marking ro\n", |
b8688d51 | 1892 | __func__, gfn); |
1e73f9dd | 1893 | ret = 1; |
1c4f1fd6 | 1894 | pte_access &= ~ACC_WRITE_MASK; |
8dae4445 | 1895 | if (is_writable_pte(spte)) |
1c4f1fd6 | 1896 | spte &= ~PT_WRITABLE_MASK; |
1c4f1fd6 AK |
1897 | } |
1898 | } | |
1899 | ||
1c4f1fd6 AK |
1900 | if (pte_access & ACC_WRITE_MASK) |
1901 | mark_page_dirty(vcpu->kvm, gfn); | |
1902 | ||
38187c83 | 1903 | set_pte: |
d555c333 | 1904 | __set_spte(sptep, spte); |
1e73f9dd MT |
1905 | return ret; |
1906 | } | |
1907 | ||
d555c333 | 1908 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd MT |
1909 | unsigned pt_access, unsigned pte_access, |
1910 | int user_fault, int write_fault, int dirty, | |
852e3c19 | 1911 | int *ptwrite, int level, gfn_t gfn, |
1403283a IE |
1912 | pfn_t pfn, bool speculative, |
1913 | bool reset_host_protection) | |
1e73f9dd MT |
1914 | { |
1915 | int was_rmapped = 0; | |
8dae4445 | 1916 | int was_writable = is_writable_pte(*sptep); |
53a27b39 | 1917 | int rmap_count; |
1e73f9dd MT |
1918 | |
1919 | pgprintk("%s: spte %llx access %x write_fault %d" | |
1920 | " user_fault %d gfn %lx\n", | |
d555c333 | 1921 | __func__, *sptep, pt_access, |
1e73f9dd MT |
1922 | write_fault, user_fault, gfn); |
1923 | ||
d555c333 | 1924 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
1925 | /* |
1926 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
1927 | * the parent of the now unreachable PTE. | |
1928 | */ | |
852e3c19 JR |
1929 | if (level > PT_PAGE_TABLE_LEVEL && |
1930 | !is_large_pte(*sptep)) { | |
1e73f9dd | 1931 | struct kvm_mmu_page *child; |
d555c333 | 1932 | u64 pte = *sptep; |
1e73f9dd MT |
1933 | |
1934 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
d555c333 | 1935 | mmu_page_remove_parent_pte(child, sptep); |
3be2264b MT |
1936 | __set_spte(sptep, shadow_trap_nonpresent_pte); |
1937 | kvm_flush_remote_tlbs(vcpu->kvm); | |
d555c333 | 1938 | } else if (pfn != spte_to_pfn(*sptep)) { |
1e73f9dd | 1939 | pgprintk("hfn old %lx new %lx\n", |
d555c333 AK |
1940 | spte_to_pfn(*sptep), pfn); |
1941 | rmap_remove(vcpu->kvm, sptep); | |
91546356 XG |
1942 | __set_spte(sptep, shadow_trap_nonpresent_pte); |
1943 | kvm_flush_remote_tlbs(vcpu->kvm); | |
6bed6b9e JR |
1944 | } else |
1945 | was_rmapped = 1; | |
1e73f9dd | 1946 | } |
852e3c19 | 1947 | |
d555c333 | 1948 | if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault, |
1403283a IE |
1949 | dirty, level, gfn, pfn, speculative, true, |
1950 | reset_host_protection)) { | |
1e73f9dd MT |
1951 | if (write_fault) |
1952 | *ptwrite = 1; | |
5304efde | 1953 | kvm_mmu_flush_tlb(vcpu); |
a378b4e6 | 1954 | } |
1e73f9dd | 1955 | |
d555c333 | 1956 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
1e73f9dd | 1957 | pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n", |
d555c333 | 1958 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
1959 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
1960 | *sptep, sptep); | |
d555c333 | 1961 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
1962 | ++vcpu->kvm->stat.lpages; |
1963 | ||
d555c333 | 1964 | page_header_update_slot(vcpu->kvm, sptep, gfn); |
1c4f1fd6 | 1965 | if (!was_rmapped) { |
44ad9944 | 1966 | rmap_count = rmap_add(vcpu, sptep, gfn); |
acb66dd0 | 1967 | kvm_release_pfn_clean(pfn); |
53a27b39 | 1968 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) |
852e3c19 | 1969 | rmap_recycle(vcpu, sptep, gfn); |
75e68e60 | 1970 | } else { |
8dae4445 | 1971 | if (was_writable) |
35149e21 | 1972 | kvm_release_pfn_dirty(pfn); |
75e68e60 | 1973 | else |
35149e21 | 1974 | kvm_release_pfn_clean(pfn); |
1c4f1fd6 | 1975 | } |
1b7fcd32 | 1976 | if (speculative) { |
d555c333 | 1977 | vcpu->arch.last_pte_updated = sptep; |
1b7fcd32 AK |
1978 | vcpu->arch.last_pte_gfn = gfn; |
1979 | } | |
1c4f1fd6 AK |
1980 | } |
1981 | ||
6aa8b732 AK |
1982 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
1983 | { | |
1984 | } | |
1985 | ||
9f652d21 | 1986 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
852e3c19 | 1987 | int level, gfn_t gfn, pfn_t pfn) |
140754bc | 1988 | { |
9f652d21 | 1989 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 1990 | struct kvm_mmu_page *sp; |
9f652d21 | 1991 | int pt_write = 0; |
140754bc | 1992 | gfn_t pseudo_gfn; |
6aa8b732 | 1993 | |
9f652d21 | 1994 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 1995 | if (iterator.level == level) { |
9f652d21 AK |
1996 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL, |
1997 | 0, write, 1, &pt_write, | |
1403283a | 1998 | level, gfn, pfn, false, true); |
9f652d21 AK |
1999 | ++vcpu->stat.pf_fixed; |
2000 | break; | |
6aa8b732 AK |
2001 | } |
2002 | ||
9f652d21 | 2003 | if (*iterator.sptep == shadow_trap_nonpresent_pte) { |
c9fa0b3b LJ |
2004 | u64 base_addr = iterator.addr; |
2005 | ||
2006 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2007 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 AK |
2008 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
2009 | iterator.level - 1, | |
2010 | 1, ACC_ALL, iterator.sptep); | |
2011 | if (!sp) { | |
2012 | pgprintk("nonpaging_map: ENOMEM\n"); | |
2013 | kvm_release_pfn_clean(pfn); | |
2014 | return -ENOMEM; | |
2015 | } | |
140754bc | 2016 | |
d555c333 AK |
2017 | __set_spte(iterator.sptep, |
2018 | __pa(sp->spt) | |
2019 | | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
2020 | | shadow_user_mask | shadow_x_mask); | |
9f652d21 AK |
2021 | } |
2022 | } | |
2023 | return pt_write; | |
6aa8b732 AK |
2024 | } |
2025 | ||
bf998156 HY |
2026 | static void kvm_send_hwpoison_signal(struct kvm *kvm, gfn_t gfn) |
2027 | { | |
2028 | char buf[1]; | |
2029 | void __user *hva; | |
2030 | int r; | |
2031 | ||
2032 | /* Touch the page, so send SIGBUS */ | |
2033 | hva = (void __user *)gfn_to_hva(kvm, gfn); | |
2034 | r = copy_from_user(buf, hva, 1); | |
2035 | } | |
2036 | ||
2037 | static int kvm_handle_bad_page(struct kvm *kvm, gfn_t gfn, pfn_t pfn) | |
2038 | { | |
2039 | kvm_release_pfn_clean(pfn); | |
2040 | if (is_hwpoison_pfn(pfn)) { | |
2041 | kvm_send_hwpoison_signal(kvm, gfn); | |
2042 | return 0; | |
2043 | } | |
2044 | return 1; | |
2045 | } | |
2046 | ||
10589a46 MT |
2047 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn) |
2048 | { | |
2049 | int r; | |
852e3c19 | 2050 | int level; |
35149e21 | 2051 | pfn_t pfn; |
e930bffe | 2052 | unsigned long mmu_seq; |
aaee2c94 | 2053 | |
852e3c19 JR |
2054 | level = mapping_level(vcpu, gfn); |
2055 | ||
2056 | /* | |
2057 | * This path builds a PAE pagetable - so we can map 2mb pages at | |
2058 | * maximum. Therefore check if the level is larger than that. | |
2059 | */ | |
2060 | if (level > PT_DIRECTORY_LEVEL) | |
2061 | level = PT_DIRECTORY_LEVEL; | |
2062 | ||
2063 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 2064 | |
e930bffe | 2065 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2066 | smp_rmb(); |
35149e21 | 2067 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
aaee2c94 | 2068 | |
d196e343 | 2069 | /* mmio */ |
bf998156 HY |
2070 | if (is_error_pfn(pfn)) |
2071 | return kvm_handle_bad_page(vcpu->kvm, gfn, pfn); | |
d196e343 | 2072 | |
aaee2c94 | 2073 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2074 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2075 | goto out_unlock; | |
eb787d10 | 2076 | kvm_mmu_free_some_pages(vcpu); |
852e3c19 | 2077 | r = __direct_map(vcpu, v, write, level, gfn, pfn); |
aaee2c94 MT |
2078 | spin_unlock(&vcpu->kvm->mmu_lock); |
2079 | ||
aaee2c94 | 2080 | |
10589a46 | 2081 | return r; |
e930bffe AA |
2082 | |
2083 | out_unlock: | |
2084 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2085 | kvm_release_pfn_clean(pfn); | |
2086 | return 0; | |
10589a46 MT |
2087 | } |
2088 | ||
2089 | ||
17ac10ad AK |
2090 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
2091 | { | |
2092 | int i; | |
4db35314 | 2093 | struct kvm_mmu_page *sp; |
d98ba053 | 2094 | LIST_HEAD(invalid_list); |
17ac10ad | 2095 | |
ad312c7c | 2096 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 2097 | return; |
aaee2c94 | 2098 | spin_lock(&vcpu->kvm->mmu_lock); |
ad312c7c ZX |
2099 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { |
2100 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
17ac10ad | 2101 | |
4db35314 AK |
2102 | sp = page_header(root); |
2103 | --sp->root_count; | |
d98ba053 XG |
2104 | if (!sp->root_count && sp->role.invalid) { |
2105 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
2106 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
2107 | } | |
ad312c7c | 2108 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
aaee2c94 | 2109 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad AK |
2110 | return; |
2111 | } | |
17ac10ad | 2112 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2113 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2114 | |
417726a3 | 2115 | if (root) { |
417726a3 | 2116 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2117 | sp = page_header(root); |
2118 | --sp->root_count; | |
2e53d63a | 2119 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
2120 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2121 | &invalid_list); | |
417726a3 | 2122 | } |
ad312c7c | 2123 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2124 | } |
d98ba053 | 2125 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 2126 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2127 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2128 | } |
2129 | ||
8986ecc0 MT |
2130 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2131 | { | |
2132 | int ret = 0; | |
2133 | ||
2134 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 2135 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
2136 | ret = 1; |
2137 | } | |
2138 | ||
2139 | return ret; | |
2140 | } | |
2141 | ||
2142 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) | |
17ac10ad AK |
2143 | { |
2144 | int i; | |
cea0f0e7 | 2145 | gfn_t root_gfn; |
4db35314 | 2146 | struct kvm_mmu_page *sp; |
f6e2c02b | 2147 | int direct = 0; |
6de4f3ad | 2148 | u64 pdptr; |
3bb65a22 | 2149 | |
ad312c7c | 2150 | root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT; |
17ac10ad | 2151 | |
ad312c7c ZX |
2152 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { |
2153 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
17ac10ad AK |
2154 | |
2155 | ASSERT(!VALID_PAGE(root)); | |
8986ecc0 MT |
2156 | if (mmu_check_root(vcpu, root_gfn)) |
2157 | return 1; | |
5a7388c2 EN |
2158 | if (tdp_enabled) { |
2159 | direct = 1; | |
2160 | root_gfn = 0; | |
2161 | } | |
8facbbff | 2162 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2163 | kvm_mmu_free_some_pages(vcpu); |
4db35314 | 2164 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, |
f6e2c02b | 2165 | PT64_ROOT_LEVEL, direct, |
fb72d167 | 2166 | ACC_ALL, NULL); |
4db35314 AK |
2167 | root = __pa(sp->spt); |
2168 | ++sp->root_count; | |
8facbbff | 2169 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2170 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 2171 | return 0; |
17ac10ad | 2172 | } |
f6e2c02b | 2173 | direct = !is_paging(vcpu); |
17ac10ad | 2174 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2175 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
2176 | |
2177 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 2178 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
6de4f3ad | 2179 | pdptr = kvm_pdptr_read(vcpu, i); |
43a3795a | 2180 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 2181 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
2182 | continue; |
2183 | } | |
6de4f3ad | 2184 | root_gfn = pdptr >> PAGE_SHIFT; |
ad312c7c | 2185 | } else if (vcpu->arch.mmu.root_level == 0) |
cea0f0e7 | 2186 | root_gfn = 0; |
8986ecc0 MT |
2187 | if (mmu_check_root(vcpu, root_gfn)) |
2188 | return 1; | |
5a7388c2 EN |
2189 | if (tdp_enabled) { |
2190 | direct = 1; | |
2191 | root_gfn = i << 30; | |
2192 | } | |
8facbbff | 2193 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2194 | kvm_mmu_free_some_pages(vcpu); |
4db35314 | 2195 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
f6e2c02b | 2196 | PT32_ROOT_LEVEL, direct, |
f7d9c7b7 | 2197 | ACC_ALL, NULL); |
4db35314 AK |
2198 | root = __pa(sp->spt); |
2199 | ++sp->root_count; | |
8facbbff AK |
2200 | spin_unlock(&vcpu->kvm->mmu_lock); |
2201 | ||
ad312c7c | 2202 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; |
17ac10ad | 2203 | } |
ad312c7c | 2204 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
8986ecc0 | 2205 | return 0; |
17ac10ad AK |
2206 | } |
2207 | ||
0ba73cda MT |
2208 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
2209 | { | |
2210 | int i; | |
2211 | struct kvm_mmu_page *sp; | |
2212 | ||
2213 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
2214 | return; | |
2215 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2216 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
2217 | sp = page_header(root); | |
2218 | mmu_sync_children(vcpu, sp); | |
2219 | return; | |
2220 | } | |
2221 | for (i = 0; i < 4; ++i) { | |
2222 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2223 | ||
8986ecc0 | 2224 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
2225 | root &= PT64_BASE_ADDR_MASK; |
2226 | sp = page_header(root); | |
2227 | mmu_sync_children(vcpu, sp); | |
2228 | } | |
2229 | } | |
2230 | } | |
2231 | ||
2232 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
2233 | { | |
2234 | spin_lock(&vcpu->kvm->mmu_lock); | |
2235 | mmu_sync_roots(vcpu); | |
6cffe8ca | 2236 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
2237 | } |
2238 | ||
1871c602 GN |
2239 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
2240 | u32 access, u32 *error) | |
6aa8b732 | 2241 | { |
1871c602 GN |
2242 | if (error) |
2243 | *error = 0; | |
6aa8b732 AK |
2244 | return vaddr; |
2245 | } | |
2246 | ||
2247 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, | |
3f3e7124 | 2248 | u32 error_code) |
6aa8b732 | 2249 | { |
e833240f | 2250 | gfn_t gfn; |
e2dec939 | 2251 | int r; |
6aa8b732 | 2252 | |
b8688d51 | 2253 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
e2dec939 AK |
2254 | r = mmu_topup_memory_caches(vcpu); |
2255 | if (r) | |
2256 | return r; | |
714b93da | 2257 | |
6aa8b732 | 2258 | ASSERT(vcpu); |
ad312c7c | 2259 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 2260 | |
e833240f | 2261 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 2262 | |
e833240f AK |
2263 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
2264 | error_code & PFERR_WRITE_MASK, gfn); | |
6aa8b732 AK |
2265 | } |
2266 | ||
fb72d167 JR |
2267 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, |
2268 | u32 error_code) | |
2269 | { | |
35149e21 | 2270 | pfn_t pfn; |
fb72d167 | 2271 | int r; |
852e3c19 | 2272 | int level; |
05da4558 | 2273 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 2274 | unsigned long mmu_seq; |
fb72d167 JR |
2275 | |
2276 | ASSERT(vcpu); | |
2277 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
2278 | ||
2279 | r = mmu_topup_memory_caches(vcpu); | |
2280 | if (r) | |
2281 | return r; | |
2282 | ||
852e3c19 JR |
2283 | level = mapping_level(vcpu, gfn); |
2284 | ||
2285 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
2286 | ||
e930bffe | 2287 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2288 | smp_rmb(); |
35149e21 | 2289 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
bf998156 HY |
2290 | if (is_error_pfn(pfn)) |
2291 | return kvm_handle_bad_page(vcpu->kvm, gfn, pfn); | |
fb72d167 | 2292 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2293 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2294 | goto out_unlock; | |
fb72d167 JR |
2295 | kvm_mmu_free_some_pages(vcpu); |
2296 | r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK, | |
852e3c19 | 2297 | level, gfn, pfn); |
fb72d167 | 2298 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
2299 | |
2300 | return r; | |
e930bffe AA |
2301 | |
2302 | out_unlock: | |
2303 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2304 | kvm_release_pfn_clean(pfn); | |
2305 | return 0; | |
fb72d167 JR |
2306 | } |
2307 | ||
6aa8b732 AK |
2308 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
2309 | { | |
17ac10ad | 2310 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2311 | } |
2312 | ||
2313 | static int nonpaging_init_context(struct kvm_vcpu *vcpu) | |
2314 | { | |
ad312c7c | 2315 | struct kvm_mmu *context = &vcpu->arch.mmu; |
6aa8b732 AK |
2316 | |
2317 | context->new_cr3 = nonpaging_new_cr3; | |
2318 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
2319 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
2320 | context->free = nonpaging_free; | |
c7addb90 | 2321 | context->prefetch_page = nonpaging_prefetch_page; |
e8bc217a | 2322 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2323 | context->invlpg = nonpaging_invlpg; |
cea0f0e7 | 2324 | context->root_level = 0; |
6aa8b732 | 2325 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 2326 | context->root_hpa = INVALID_PAGE; |
6aa8b732 AK |
2327 | return 0; |
2328 | } | |
2329 | ||
d835dfec | 2330 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 2331 | { |
1165f5fe | 2332 | ++vcpu->stat.tlb_flush; |
a8eeb04a | 2333 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
6aa8b732 AK |
2334 | } |
2335 | ||
2336 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
2337 | { | |
b8688d51 | 2338 | pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3); |
cea0f0e7 | 2339 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2340 | } |
2341 | ||
6aa8b732 AK |
2342 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
2343 | u64 addr, | |
2344 | u32 err_code) | |
2345 | { | |
c3c91fee | 2346 | kvm_inject_page_fault(vcpu, addr, err_code); |
6aa8b732 AK |
2347 | } |
2348 | ||
6aa8b732 AK |
2349 | static void paging_free(struct kvm_vcpu *vcpu) |
2350 | { | |
2351 | nonpaging_free(vcpu); | |
2352 | } | |
2353 | ||
82725b20 DE |
2354 | static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level) |
2355 | { | |
2356 | int bit7; | |
2357 | ||
2358 | bit7 = (gpte >> 7) & 1; | |
2359 | return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0; | |
2360 | } | |
2361 | ||
6aa8b732 AK |
2362 | #define PTTYPE 64 |
2363 | #include "paging_tmpl.h" | |
2364 | #undef PTTYPE | |
2365 | ||
2366 | #define PTTYPE 32 | |
2367 | #include "paging_tmpl.h" | |
2368 | #undef PTTYPE | |
2369 | ||
82725b20 DE |
2370 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level) |
2371 | { | |
2372 | struct kvm_mmu *context = &vcpu->arch.mmu; | |
2373 | int maxphyaddr = cpuid_maxphyaddr(vcpu); | |
2374 | u64 exb_bit_rsvd = 0; | |
2375 | ||
2376 | if (!is_nx(vcpu)) | |
2377 | exb_bit_rsvd = rsvd_bits(63, 63); | |
2378 | switch (level) { | |
2379 | case PT32_ROOT_LEVEL: | |
2380 | /* no rsvd bits for 2 level 4K page table entries */ | |
2381 | context->rsvd_bits_mask[0][1] = 0; | |
2382 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
2383 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
2384 | ||
2385 | if (!is_pse(vcpu)) { | |
2386 | context->rsvd_bits_mask[1][1] = 0; | |
2387 | break; | |
2388 | } | |
2389 | ||
82725b20 DE |
2390 | if (is_cpuid_PSE36()) |
2391 | /* 36bits PSE 4MB page */ | |
2392 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
2393 | else | |
2394 | /* 32 bits PSE 4MB page */ | |
2395 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
2396 | break; |
2397 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
2398 | context->rsvd_bits_mask[0][2] = |
2399 | rsvd_bits(maxphyaddr, 63) | | |
2400 | rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ | |
82725b20 | 2401 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 2402 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
2403 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2404 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
2405 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
2406 | rsvd_bits(maxphyaddr, 62) | | |
2407 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2408 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2409 | break; |
2410 | case PT64_ROOT_LEVEL: | |
2411 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
2412 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2413 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | | |
2414 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2415 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | | |
4c26b4cd | 2416 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
2417 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2418 | rsvd_bits(maxphyaddr, 51); | |
2419 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 JR |
2420 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
2421 | rsvd_bits(maxphyaddr, 51) | | |
2422 | rsvd_bits(13, 29); | |
82725b20 | 2423 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
2424 | rsvd_bits(maxphyaddr, 51) | |
2425 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2426 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2427 | break; |
2428 | } | |
2429 | } | |
2430 | ||
17ac10ad | 2431 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level) |
6aa8b732 | 2432 | { |
ad312c7c | 2433 | struct kvm_mmu *context = &vcpu->arch.mmu; |
6aa8b732 AK |
2434 | |
2435 | ASSERT(is_pae(vcpu)); | |
2436 | context->new_cr3 = paging_new_cr3; | |
2437 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 2438 | context->gva_to_gpa = paging64_gva_to_gpa; |
c7addb90 | 2439 | context->prefetch_page = paging64_prefetch_page; |
e8bc217a | 2440 | context->sync_page = paging64_sync_page; |
a7052897 | 2441 | context->invlpg = paging64_invlpg; |
6aa8b732 | 2442 | context->free = paging_free; |
17ac10ad AK |
2443 | context->root_level = level; |
2444 | context->shadow_root_level = level; | |
17c3ba9d | 2445 | context->root_hpa = INVALID_PAGE; |
6aa8b732 AK |
2446 | return 0; |
2447 | } | |
2448 | ||
17ac10ad AK |
2449 | static int paging64_init_context(struct kvm_vcpu *vcpu) |
2450 | { | |
82725b20 | 2451 | reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL); |
17ac10ad AK |
2452 | return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL); |
2453 | } | |
2454 | ||
6aa8b732 AK |
2455 | static int paging32_init_context(struct kvm_vcpu *vcpu) |
2456 | { | |
ad312c7c | 2457 | struct kvm_mmu *context = &vcpu->arch.mmu; |
6aa8b732 | 2458 | |
82725b20 | 2459 | reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL); |
6aa8b732 AK |
2460 | context->new_cr3 = paging_new_cr3; |
2461 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
2462 | context->gva_to_gpa = paging32_gva_to_gpa; |
2463 | context->free = paging_free; | |
c7addb90 | 2464 | context->prefetch_page = paging32_prefetch_page; |
e8bc217a | 2465 | context->sync_page = paging32_sync_page; |
a7052897 | 2466 | context->invlpg = paging32_invlpg; |
6aa8b732 AK |
2467 | context->root_level = PT32_ROOT_LEVEL; |
2468 | context->shadow_root_level = PT32E_ROOT_LEVEL; | |
17c3ba9d | 2469 | context->root_hpa = INVALID_PAGE; |
6aa8b732 AK |
2470 | return 0; |
2471 | } | |
2472 | ||
2473 | static int paging32E_init_context(struct kvm_vcpu *vcpu) | |
2474 | { | |
82725b20 | 2475 | reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL); |
17ac10ad | 2476 | return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
2477 | } |
2478 | ||
fb72d167 JR |
2479 | static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
2480 | { | |
2481 | struct kvm_mmu *context = &vcpu->arch.mmu; | |
2482 | ||
2483 | context->new_cr3 = nonpaging_new_cr3; | |
2484 | context->page_fault = tdp_page_fault; | |
2485 | context->free = nonpaging_free; | |
2486 | context->prefetch_page = nonpaging_prefetch_page; | |
e8bc217a | 2487 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2488 | context->invlpg = nonpaging_invlpg; |
67253af5 | 2489 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 JR |
2490 | context->root_hpa = INVALID_PAGE; |
2491 | ||
2492 | if (!is_paging(vcpu)) { | |
2493 | context->gva_to_gpa = nonpaging_gva_to_gpa; | |
2494 | context->root_level = 0; | |
2495 | } else if (is_long_mode(vcpu)) { | |
82725b20 | 2496 | reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL); |
fb72d167 JR |
2497 | context->gva_to_gpa = paging64_gva_to_gpa; |
2498 | context->root_level = PT64_ROOT_LEVEL; | |
2499 | } else if (is_pae(vcpu)) { | |
82725b20 | 2500 | reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL); |
fb72d167 JR |
2501 | context->gva_to_gpa = paging64_gva_to_gpa; |
2502 | context->root_level = PT32E_ROOT_LEVEL; | |
2503 | } else { | |
82725b20 | 2504 | reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL); |
fb72d167 JR |
2505 | context->gva_to_gpa = paging32_gva_to_gpa; |
2506 | context->root_level = PT32_ROOT_LEVEL; | |
2507 | } | |
2508 | ||
2509 | return 0; | |
2510 | } | |
2511 | ||
2512 | static int init_kvm_softmmu(struct kvm_vcpu *vcpu) | |
6aa8b732 | 2513 | { |
a770f6f2 AK |
2514 | int r; |
2515 | ||
6aa8b732 | 2516 | ASSERT(vcpu); |
ad312c7c | 2517 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
2518 | |
2519 | if (!is_paging(vcpu)) | |
a770f6f2 | 2520 | r = nonpaging_init_context(vcpu); |
a9058ecd | 2521 | else if (is_long_mode(vcpu)) |
a770f6f2 | 2522 | r = paging64_init_context(vcpu); |
6aa8b732 | 2523 | else if (is_pae(vcpu)) |
a770f6f2 | 2524 | r = paging32E_init_context(vcpu); |
6aa8b732 | 2525 | else |
a770f6f2 AK |
2526 | r = paging32_init_context(vcpu); |
2527 | ||
5b7e0102 | 2528 | vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu); |
3dbe1415 | 2529 | vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu); |
a770f6f2 AK |
2530 | |
2531 | return r; | |
6aa8b732 AK |
2532 | } |
2533 | ||
fb72d167 JR |
2534 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) |
2535 | { | |
35149e21 AL |
2536 | vcpu->arch.update_pte.pfn = bad_pfn; |
2537 | ||
fb72d167 JR |
2538 | if (tdp_enabled) |
2539 | return init_kvm_tdp_mmu(vcpu); | |
2540 | else | |
2541 | return init_kvm_softmmu(vcpu); | |
2542 | } | |
2543 | ||
6aa8b732 AK |
2544 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) |
2545 | { | |
2546 | ASSERT(vcpu); | |
62ad0755 SY |
2547 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2548 | /* mmu.free() should set root_hpa = INVALID_PAGE */ | |
ad312c7c | 2549 | vcpu->arch.mmu.free(vcpu); |
6aa8b732 AK |
2550 | } |
2551 | ||
2552 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
2553 | { |
2554 | destroy_kvm_mmu(vcpu); | |
2555 | return init_kvm_mmu(vcpu); | |
2556 | } | |
8668a3c4 | 2557 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
2558 | |
2559 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 2560 | { |
714b93da AK |
2561 | int r; |
2562 | ||
e2dec939 | 2563 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
2564 | if (r) |
2565 | goto out; | |
8986ecc0 | 2566 | r = mmu_alloc_roots(vcpu); |
8facbbff | 2567 | spin_lock(&vcpu->kvm->mmu_lock); |
0ba73cda | 2568 | mmu_sync_roots(vcpu); |
aaee2c94 | 2569 | spin_unlock(&vcpu->kvm->mmu_lock); |
8986ecc0 MT |
2570 | if (r) |
2571 | goto out; | |
3662cb1c | 2572 | /* set_cr3() should ensure TLB has been flushed */ |
ad312c7c | 2573 | kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
2574 | out: |
2575 | return r; | |
6aa8b732 | 2576 | } |
17c3ba9d AK |
2577 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
2578 | ||
2579 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
2580 | { | |
2581 | mmu_free_roots(vcpu); | |
2582 | } | |
6aa8b732 | 2583 | |
09072daf | 2584 | static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu, |
4db35314 | 2585 | struct kvm_mmu_page *sp, |
ac1b714e AK |
2586 | u64 *spte) |
2587 | { | |
2588 | u64 pte; | |
2589 | struct kvm_mmu_page *child; | |
2590 | ||
2591 | pte = *spte; | |
c7addb90 | 2592 | if (is_shadow_present_pte(pte)) { |
776e6633 | 2593 | if (is_last_spte(pte, sp->role.level)) |
290fc38d | 2594 | rmap_remove(vcpu->kvm, spte); |
ac1b714e AK |
2595 | else { |
2596 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
90cb0529 | 2597 | mmu_page_remove_parent_pte(child, spte); |
ac1b714e AK |
2598 | } |
2599 | } | |
d555c333 | 2600 | __set_spte(spte, shadow_trap_nonpresent_pte); |
05da4558 MT |
2601 | if (is_large_pte(pte)) |
2602 | --vcpu->kvm->stat.lpages; | |
ac1b714e AK |
2603 | } |
2604 | ||
0028425f | 2605 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
4db35314 | 2606 | struct kvm_mmu_page *sp, |
0028425f | 2607 | u64 *spte, |
489f1d65 | 2608 | const void *new) |
0028425f | 2609 | { |
30945387 | 2610 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
2611 | ++vcpu->kvm->stat.mmu_pde_zapped; |
2612 | return; | |
30945387 | 2613 | } |
0028425f | 2614 | |
4cee5764 | 2615 | ++vcpu->kvm->stat.mmu_pte_updated; |
5b7e0102 | 2616 | if (!sp->role.cr4_pae) |
489f1d65 | 2617 | paging32_update_pte(vcpu, sp, spte, new); |
0028425f | 2618 | else |
489f1d65 | 2619 | paging64_update_pte(vcpu, sp, spte, new); |
0028425f AK |
2620 | } |
2621 | ||
79539cec AK |
2622 | static bool need_remote_flush(u64 old, u64 new) |
2623 | { | |
2624 | if (!is_shadow_present_pte(old)) | |
2625 | return false; | |
2626 | if (!is_shadow_present_pte(new)) | |
2627 | return true; | |
2628 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
2629 | return true; | |
2630 | old ^= PT64_NX_MASK; | |
2631 | new ^= PT64_NX_MASK; | |
2632 | return (old & ~new & PT64_PERM_MASK) != 0; | |
2633 | } | |
2634 | ||
0671a8e7 XG |
2635 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
2636 | bool remote_flush, bool local_flush) | |
79539cec | 2637 | { |
0671a8e7 XG |
2638 | if (zap_page) |
2639 | return; | |
2640 | ||
2641 | if (remote_flush) | |
79539cec | 2642 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 2643 | else if (local_flush) |
79539cec AK |
2644 | kvm_mmu_flush_tlb(vcpu); |
2645 | } | |
2646 | ||
12b7d28f AK |
2647 | static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu) |
2648 | { | |
ad312c7c | 2649 | u64 *spte = vcpu->arch.last_pte_updated; |
12b7d28f | 2650 | |
7b52345e | 2651 | return !!(spte && (*spte & shadow_accessed_mask)); |
12b7d28f AK |
2652 | } |
2653 | ||
d7824fff | 2654 | static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
72016f3a | 2655 | u64 gpte) |
d7824fff AK |
2656 | { |
2657 | gfn_t gfn; | |
35149e21 | 2658 | pfn_t pfn; |
d7824fff | 2659 | |
43a3795a | 2660 | if (!is_present_gpte(gpte)) |
d7824fff AK |
2661 | return; |
2662 | gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; | |
72dc67a6 | 2663 | |
e930bffe | 2664 | vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2665 | smp_rmb(); |
35149e21 | 2666 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
72dc67a6 | 2667 | |
35149e21 AL |
2668 | if (is_error_pfn(pfn)) { |
2669 | kvm_release_pfn_clean(pfn); | |
d196e343 AK |
2670 | return; |
2671 | } | |
d7824fff | 2672 | vcpu->arch.update_pte.gfn = gfn; |
35149e21 | 2673 | vcpu->arch.update_pte.pfn = pfn; |
d7824fff AK |
2674 | } |
2675 | ||
1b7fcd32 AK |
2676 | static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn) |
2677 | { | |
2678 | u64 *spte = vcpu->arch.last_pte_updated; | |
2679 | ||
2680 | if (spte | |
2681 | && vcpu->arch.last_pte_gfn == gfn | |
2682 | && shadow_accessed_mask | |
2683 | && !(*spte & shadow_accessed_mask) | |
2684 | && is_shadow_present_pte(*spte)) | |
2685 | set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
2686 | } | |
2687 | ||
09072daf | 2688 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
ad218f85 MT |
2689 | const u8 *new, int bytes, |
2690 | bool guest_initiated) | |
da4a00f0 | 2691 | { |
9b7a0325 | 2692 | gfn_t gfn = gpa >> PAGE_SHIFT; |
4db35314 | 2693 | struct kvm_mmu_page *sp; |
f41d335a | 2694 | struct hlist_node *node; |
d98ba053 | 2695 | LIST_HEAD(invalid_list); |
489f1d65 | 2696 | u64 entry, gentry; |
9b7a0325 | 2697 | u64 *spte; |
9b7a0325 | 2698 | unsigned offset = offset_in_page(gpa); |
0e7bc4b9 | 2699 | unsigned pte_size; |
9b7a0325 | 2700 | unsigned page_offset; |
0e7bc4b9 | 2701 | unsigned misaligned; |
fce0657f | 2702 | unsigned quadrant; |
9b7a0325 | 2703 | int level; |
86a5ba02 | 2704 | int flooded = 0; |
ac1b714e | 2705 | int npte; |
489f1d65 | 2706 | int r; |
08e850c6 | 2707 | int invlpg_counter; |
0671a8e7 XG |
2708 | bool remote_flush, local_flush, zap_page; |
2709 | ||
2710 | zap_page = remote_flush = local_flush = false; | |
9b7a0325 | 2711 | |
b8688d51 | 2712 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); |
72016f3a | 2713 | |
08e850c6 | 2714 | invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter); |
72016f3a AK |
2715 | |
2716 | /* | |
2717 | * Assume that the pte write on a page table of the same type | |
2718 | * as the current vcpu paging mode. This is nearly always true | |
2719 | * (might be false while changing modes). Note it is verified later | |
2720 | * by update_pte(). | |
2721 | */ | |
08e850c6 | 2722 | if ((is_pae(vcpu) && bytes == 4) || !new) { |
72016f3a | 2723 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
08e850c6 AK |
2724 | if (is_pae(vcpu)) { |
2725 | gpa &= ~(gpa_t)7; | |
2726 | bytes = 8; | |
2727 | } | |
2728 | r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8)); | |
72016f3a AK |
2729 | if (r) |
2730 | gentry = 0; | |
08e850c6 AK |
2731 | new = (const u8 *)&gentry; |
2732 | } | |
2733 | ||
2734 | switch (bytes) { | |
2735 | case 4: | |
2736 | gentry = *(const u32 *)new; | |
2737 | break; | |
2738 | case 8: | |
2739 | gentry = *(const u64 *)new; | |
2740 | break; | |
2741 | default: | |
2742 | gentry = 0; | |
2743 | break; | |
72016f3a AK |
2744 | } |
2745 | ||
2746 | mmu_guess_page_from_pte_write(vcpu, gpa, gentry); | |
aaee2c94 | 2747 | spin_lock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
2748 | if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter) |
2749 | gentry = 0; | |
1b7fcd32 | 2750 | kvm_mmu_access_page(vcpu, gfn); |
eb787d10 | 2751 | kvm_mmu_free_some_pages(vcpu); |
4cee5764 | 2752 | ++vcpu->kvm->stat.mmu_pte_write; |
c7addb90 | 2753 | kvm_mmu_audit(vcpu, "pre pte write"); |
ad218f85 MT |
2754 | if (guest_initiated) { |
2755 | if (gfn == vcpu->arch.last_pt_write_gfn | |
2756 | && !last_updated_pte_accessed(vcpu)) { | |
2757 | ++vcpu->arch.last_pt_write_count; | |
2758 | if (vcpu->arch.last_pt_write_count >= 3) | |
2759 | flooded = 1; | |
2760 | } else { | |
2761 | vcpu->arch.last_pt_write_gfn = gfn; | |
2762 | vcpu->arch.last_pt_write_count = 1; | |
2763 | vcpu->arch.last_pte_updated = NULL; | |
2764 | } | |
86a5ba02 | 2765 | } |
3246af0e | 2766 | |
f41d335a | 2767 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) { |
5b7e0102 | 2768 | pte_size = sp->role.cr4_pae ? 8 : 4; |
0e7bc4b9 | 2769 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
e925c5ba | 2770 | misaligned |= bytes < 4; |
86a5ba02 | 2771 | if (misaligned || flooded) { |
0e7bc4b9 AK |
2772 | /* |
2773 | * Misaligned accesses are too much trouble to fix | |
2774 | * up; also, they usually indicate a page is not used | |
2775 | * as a page table. | |
86a5ba02 AK |
2776 | * |
2777 | * If we're seeing too many writes to a page, | |
2778 | * it may no longer be a page table, or we may be | |
2779 | * forking, in which case it is better to unmap the | |
2780 | * page. | |
0e7bc4b9 AK |
2781 | */ |
2782 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4db35314 | 2783 | gpa, bytes, sp->role.word); |
0671a8e7 | 2784 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 2785 | &invalid_list); |
4cee5764 | 2786 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
2787 | continue; |
2788 | } | |
9b7a0325 | 2789 | page_offset = offset; |
4db35314 | 2790 | level = sp->role.level; |
ac1b714e | 2791 | npte = 1; |
5b7e0102 | 2792 | if (!sp->role.cr4_pae) { |
ac1b714e AK |
2793 | page_offset <<= 1; /* 32->64 */ |
2794 | /* | |
2795 | * A 32-bit pde maps 4MB while the shadow pdes map | |
2796 | * only 2MB. So we need to double the offset again | |
2797 | * and zap two pdes instead of one. | |
2798 | */ | |
2799 | if (level == PT32_ROOT_LEVEL) { | |
6b8d0f9b | 2800 | page_offset &= ~7; /* kill rounding error */ |
ac1b714e AK |
2801 | page_offset <<= 1; |
2802 | npte = 2; | |
2803 | } | |
fce0657f | 2804 | quadrant = page_offset >> PAGE_SHIFT; |
9b7a0325 | 2805 | page_offset &= ~PAGE_MASK; |
4db35314 | 2806 | if (quadrant != sp->role.quadrant) |
fce0657f | 2807 | continue; |
9b7a0325 | 2808 | } |
0671a8e7 | 2809 | local_flush = true; |
4db35314 | 2810 | spte = &sp->spt[page_offset / sizeof(*spte)]; |
ac1b714e | 2811 | while (npte--) { |
79539cec | 2812 | entry = *spte; |
4db35314 | 2813 | mmu_pte_write_zap_pte(vcpu, sp, spte); |
72016f3a AK |
2814 | if (gentry) |
2815 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); | |
0671a8e7 XG |
2816 | if (!remote_flush && need_remote_flush(entry, *spte)) |
2817 | remote_flush = true; | |
ac1b714e | 2818 | ++spte; |
9b7a0325 | 2819 | } |
9b7a0325 | 2820 | } |
0671a8e7 | 2821 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 2822 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
c7addb90 | 2823 | kvm_mmu_audit(vcpu, "post pte write"); |
aaee2c94 | 2824 | spin_unlock(&vcpu->kvm->mmu_lock); |
35149e21 AL |
2825 | if (!is_error_pfn(vcpu->arch.update_pte.pfn)) { |
2826 | kvm_release_pfn_clean(vcpu->arch.update_pte.pfn); | |
2827 | vcpu->arch.update_pte.pfn = bad_pfn; | |
d7824fff | 2828 | } |
da4a00f0 AK |
2829 | } |
2830 | ||
a436036b AK |
2831 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
2832 | { | |
10589a46 MT |
2833 | gpa_t gpa; |
2834 | int r; | |
a436036b | 2835 | |
60f24784 AK |
2836 | if (tdp_enabled) |
2837 | return 0; | |
2838 | ||
1871c602 | 2839 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 2840 | |
aaee2c94 | 2841 | spin_lock(&vcpu->kvm->mmu_lock); |
10589a46 | 2842 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
aaee2c94 | 2843 | spin_unlock(&vcpu->kvm->mmu_lock); |
10589a46 | 2844 | return r; |
a436036b | 2845 | } |
577bdc49 | 2846 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 2847 | |
22d95b12 | 2848 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu) |
ebeace86 | 2849 | { |
103ad25a | 2850 | int free_pages; |
d98ba053 | 2851 | LIST_HEAD(invalid_list); |
103ad25a XG |
2852 | |
2853 | free_pages = vcpu->kvm->arch.n_free_mmu_pages; | |
2854 | while (free_pages < KVM_REFILL_PAGES && | |
3b80fffe | 2855 | !list_empty(&vcpu->kvm->arch.active_mmu_pages)) { |
4db35314 | 2856 | struct kvm_mmu_page *sp; |
ebeace86 | 2857 | |
f05e70ac | 2858 | sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev, |
4db35314 | 2859 | struct kvm_mmu_page, link); |
d98ba053 XG |
2860 | free_pages += kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2861 | &invalid_list); | |
4cee5764 | 2862 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 2863 | } |
d98ba053 | 2864 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
ebeace86 | 2865 | } |
ebeace86 | 2866 | |
3067714c AK |
2867 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code) |
2868 | { | |
2869 | int r; | |
2870 | enum emulation_result er; | |
2871 | ||
ad312c7c | 2872 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code); |
3067714c AK |
2873 | if (r < 0) |
2874 | goto out; | |
2875 | ||
2876 | if (!r) { | |
2877 | r = 1; | |
2878 | goto out; | |
2879 | } | |
2880 | ||
b733bfb5 AK |
2881 | r = mmu_topup_memory_caches(vcpu); |
2882 | if (r) | |
2883 | goto out; | |
2884 | ||
851ba692 | 2885 | er = emulate_instruction(vcpu, cr2, error_code, 0); |
3067714c AK |
2886 | |
2887 | switch (er) { | |
2888 | case EMULATE_DONE: | |
2889 | return 1; | |
2890 | case EMULATE_DO_MMIO: | |
2891 | ++vcpu->stat.mmio_exits; | |
6d77dbfc | 2892 | /* fall through */ |
3067714c | 2893 | case EMULATE_FAIL: |
3f5d18a9 | 2894 | return 0; |
3067714c AK |
2895 | default: |
2896 | BUG(); | |
2897 | } | |
2898 | out: | |
3067714c AK |
2899 | return r; |
2900 | } | |
2901 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
2902 | ||
a7052897 MT |
2903 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
2904 | { | |
a7052897 | 2905 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
2906 | kvm_mmu_flush_tlb(vcpu); |
2907 | ++vcpu->stat.invlpg; | |
2908 | } | |
2909 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
2910 | ||
18552672 JR |
2911 | void kvm_enable_tdp(void) |
2912 | { | |
2913 | tdp_enabled = true; | |
2914 | } | |
2915 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
2916 | ||
5f4cb662 JR |
2917 | void kvm_disable_tdp(void) |
2918 | { | |
2919 | tdp_enabled = false; | |
2920 | } | |
2921 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
2922 | ||
6aa8b732 AK |
2923 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
2924 | { | |
ad312c7c | 2925 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
6aa8b732 AK |
2926 | } |
2927 | ||
2928 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
2929 | { | |
17ac10ad | 2930 | struct page *page; |
6aa8b732 AK |
2931 | int i; |
2932 | ||
2933 | ASSERT(vcpu); | |
2934 | ||
17ac10ad AK |
2935 | /* |
2936 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
2937 | * Therefore we need to allocate shadow page tables in the first | |
2938 | * 4GB of memory, which happens to fit the DMA32 zone. | |
2939 | */ | |
2940 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
2941 | if (!page) | |
d7fa6ab2 WY |
2942 | return -ENOMEM; |
2943 | ||
ad312c7c | 2944 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 2945 | for (i = 0; i < 4; ++i) |
ad312c7c | 2946 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2947 | |
6aa8b732 | 2948 | return 0; |
6aa8b732 AK |
2949 | } |
2950 | ||
8018c27b | 2951 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 2952 | { |
6aa8b732 | 2953 | ASSERT(vcpu); |
ad312c7c | 2954 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 2955 | |
8018c27b IM |
2956 | return alloc_mmu_pages(vcpu); |
2957 | } | |
6aa8b732 | 2958 | |
8018c27b IM |
2959 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
2960 | { | |
2961 | ASSERT(vcpu); | |
ad312c7c | 2962 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 2963 | |
8018c27b | 2964 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
2965 | } |
2966 | ||
2967 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) | |
2968 | { | |
2969 | ASSERT(vcpu); | |
2970 | ||
2971 | destroy_kvm_mmu(vcpu); | |
2972 | free_mmu_pages(vcpu); | |
714b93da | 2973 | mmu_free_memory_caches(vcpu); |
6aa8b732 AK |
2974 | } |
2975 | ||
90cb0529 | 2976 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 2977 | { |
4db35314 | 2978 | struct kvm_mmu_page *sp; |
6aa8b732 | 2979 | |
f05e70ac | 2980 | list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) { |
6aa8b732 AK |
2981 | int i; |
2982 | u64 *pt; | |
2983 | ||
291f26bc | 2984 | if (!test_bit(slot, sp->slot_bitmap)) |
6aa8b732 AK |
2985 | continue; |
2986 | ||
4db35314 | 2987 | pt = sp->spt; |
6aa8b732 AK |
2988 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2989 | /* avoid RMW */ | |
01c168ac | 2990 | if (is_writable_pte(pt[i])) |
6aa8b732 | 2991 | pt[i] &= ~PT_WRITABLE_MASK; |
6aa8b732 | 2992 | } |
171d595d | 2993 | kvm_flush_remote_tlbs(kvm); |
6aa8b732 | 2994 | } |
37a7d8b0 | 2995 | |
90cb0529 | 2996 | void kvm_mmu_zap_all(struct kvm *kvm) |
e0fa826f | 2997 | { |
4db35314 | 2998 | struct kvm_mmu_page *sp, *node; |
d98ba053 | 2999 | LIST_HEAD(invalid_list); |
e0fa826f | 3000 | |
aaee2c94 | 3001 | spin_lock(&kvm->mmu_lock); |
3246af0e | 3002 | restart: |
f05e70ac | 3003 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) |
d98ba053 | 3004 | if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list)) |
3246af0e XG |
3005 | goto restart; |
3006 | ||
d98ba053 | 3007 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
aaee2c94 | 3008 | spin_unlock(&kvm->mmu_lock); |
e0fa826f DL |
3009 | } |
3010 | ||
d98ba053 XG |
3011 | static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm, |
3012 | struct list_head *invalid_list) | |
3ee16c81 IE |
3013 | { |
3014 | struct kvm_mmu_page *page; | |
3015 | ||
3016 | page = container_of(kvm->arch.active_mmu_pages.prev, | |
3017 | struct kvm_mmu_page, link); | |
d98ba053 | 3018 | return kvm_mmu_prepare_zap_page(kvm, page, invalid_list); |
3ee16c81 IE |
3019 | } |
3020 | ||
7f8275d0 | 3021 | static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
3ee16c81 IE |
3022 | { |
3023 | struct kvm *kvm; | |
3024 | struct kvm *kvm_freed = NULL; | |
3025 | int cache_count = 0; | |
3026 | ||
3027 | spin_lock(&kvm_lock); | |
3028 | ||
3029 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
d35b8dd9 | 3030 | int npages, idx, freed_pages; |
d98ba053 | 3031 | LIST_HEAD(invalid_list); |
3ee16c81 | 3032 | |
f656ce01 | 3033 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 IE |
3034 | spin_lock(&kvm->mmu_lock); |
3035 | npages = kvm->arch.n_alloc_mmu_pages - | |
3036 | kvm->arch.n_free_mmu_pages; | |
3037 | cache_count += npages; | |
3038 | if (!kvm_freed && nr_to_scan > 0 && npages > 0) { | |
d98ba053 XG |
3039 | freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm, |
3040 | &invalid_list); | |
d35b8dd9 | 3041 | cache_count -= freed_pages; |
3ee16c81 IE |
3042 | kvm_freed = kvm; |
3043 | } | |
3044 | nr_to_scan--; | |
3045 | ||
d98ba053 | 3046 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
3ee16c81 | 3047 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 3048 | srcu_read_unlock(&kvm->srcu, idx); |
3ee16c81 IE |
3049 | } |
3050 | if (kvm_freed) | |
3051 | list_move_tail(&kvm_freed->vm_list, &vm_list); | |
3052 | ||
3053 | spin_unlock(&kvm_lock); | |
3054 | ||
3055 | return cache_count; | |
3056 | } | |
3057 | ||
3058 | static struct shrinker mmu_shrinker = { | |
3059 | .shrink = mmu_shrink, | |
3060 | .seeks = DEFAULT_SEEKS * 10, | |
3061 | }; | |
3062 | ||
2ddfd20e | 3063 | static void mmu_destroy_caches(void) |
b5a33a75 AK |
3064 | { |
3065 | if (pte_chain_cache) | |
3066 | kmem_cache_destroy(pte_chain_cache); | |
3067 | if (rmap_desc_cache) | |
3068 | kmem_cache_destroy(rmap_desc_cache); | |
d3d25b04 AK |
3069 | if (mmu_page_header_cache) |
3070 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
3071 | } |
3072 | ||
3ee16c81 IE |
3073 | void kvm_mmu_module_exit(void) |
3074 | { | |
3075 | mmu_destroy_caches(); | |
3076 | unregister_shrinker(&mmu_shrinker); | |
3077 | } | |
3078 | ||
b5a33a75 AK |
3079 | int kvm_mmu_module_init(void) |
3080 | { | |
3081 | pte_chain_cache = kmem_cache_create("kvm_pte_chain", | |
3082 | sizeof(struct kvm_pte_chain), | |
20c2df83 | 3083 | 0, 0, NULL); |
b5a33a75 AK |
3084 | if (!pte_chain_cache) |
3085 | goto nomem; | |
3086 | rmap_desc_cache = kmem_cache_create("kvm_rmap_desc", | |
3087 | sizeof(struct kvm_rmap_desc), | |
20c2df83 | 3088 | 0, 0, NULL); |
b5a33a75 AK |
3089 | if (!rmap_desc_cache) |
3090 | goto nomem; | |
3091 | ||
d3d25b04 AK |
3092 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
3093 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 3094 | 0, 0, NULL); |
d3d25b04 AK |
3095 | if (!mmu_page_header_cache) |
3096 | goto nomem; | |
3097 | ||
3ee16c81 IE |
3098 | register_shrinker(&mmu_shrinker); |
3099 | ||
b5a33a75 AK |
3100 | return 0; |
3101 | ||
3102 | nomem: | |
3ee16c81 | 3103 | mmu_destroy_caches(); |
b5a33a75 AK |
3104 | return -ENOMEM; |
3105 | } | |
3106 | ||
3ad82a7e ZX |
3107 | /* |
3108 | * Caculate mmu pages needed for kvm. | |
3109 | */ | |
3110 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
3111 | { | |
3112 | int i; | |
3113 | unsigned int nr_mmu_pages; | |
3114 | unsigned int nr_pages = 0; | |
bc6678a3 | 3115 | struct kvm_memslots *slots; |
3ad82a7e | 3116 | |
90d83dc3 LJ |
3117 | slots = kvm_memslots(kvm); |
3118 | ||
bc6678a3 MT |
3119 | for (i = 0; i < slots->nmemslots; i++) |
3120 | nr_pages += slots->memslots[i].npages; | |
3ad82a7e ZX |
3121 | |
3122 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
3123 | nr_mmu_pages = max(nr_mmu_pages, | |
3124 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
3125 | ||
3126 | return nr_mmu_pages; | |
3127 | } | |
3128 | ||
2f333bcb MT |
3129 | static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer, |
3130 | unsigned len) | |
3131 | { | |
3132 | if (len > buffer->len) | |
3133 | return NULL; | |
3134 | return buffer->ptr; | |
3135 | } | |
3136 | ||
3137 | static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer, | |
3138 | unsigned len) | |
3139 | { | |
3140 | void *ret; | |
3141 | ||
3142 | ret = pv_mmu_peek_buffer(buffer, len); | |
3143 | if (!ret) | |
3144 | return ret; | |
3145 | buffer->ptr += len; | |
3146 | buffer->len -= len; | |
3147 | buffer->processed += len; | |
3148 | return ret; | |
3149 | } | |
3150 | ||
3151 | static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu, | |
3152 | gpa_t addr, gpa_t value) | |
3153 | { | |
3154 | int bytes = 8; | |
3155 | int r; | |
3156 | ||
3157 | if (!is_long_mode(vcpu) && !is_pae(vcpu)) | |
3158 | bytes = 4; | |
3159 | ||
3160 | r = mmu_topup_memory_caches(vcpu); | |
3161 | if (r) | |
3162 | return r; | |
3163 | ||
3200f405 | 3164 | if (!emulator_write_phys(vcpu, addr, &value, bytes)) |
2f333bcb MT |
3165 | return -EFAULT; |
3166 | ||
3167 | return 1; | |
3168 | } | |
3169 | ||
3170 | static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu) | |
3171 | { | |
2390218b | 3172 | (void)kvm_set_cr3(vcpu, vcpu->arch.cr3); |
2f333bcb MT |
3173 | return 1; |
3174 | } | |
3175 | ||
3176 | static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr) | |
3177 | { | |
3178 | spin_lock(&vcpu->kvm->mmu_lock); | |
3179 | mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT); | |
3180 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3181 | return 1; | |
3182 | } | |
3183 | ||
3184 | static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu, | |
3185 | struct kvm_pv_mmu_op_buffer *buffer) | |
3186 | { | |
3187 | struct kvm_mmu_op_header *header; | |
3188 | ||
3189 | header = pv_mmu_peek_buffer(buffer, sizeof *header); | |
3190 | if (!header) | |
3191 | return 0; | |
3192 | switch (header->op) { | |
3193 | case KVM_MMU_OP_WRITE_PTE: { | |
3194 | struct kvm_mmu_op_write_pte *wpte; | |
3195 | ||
3196 | wpte = pv_mmu_read_buffer(buffer, sizeof *wpte); | |
3197 | if (!wpte) | |
3198 | return 0; | |
3199 | return kvm_pv_mmu_write(vcpu, wpte->pte_phys, | |
3200 | wpte->pte_val); | |
3201 | } | |
3202 | case KVM_MMU_OP_FLUSH_TLB: { | |
3203 | struct kvm_mmu_op_flush_tlb *ftlb; | |
3204 | ||
3205 | ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb); | |
3206 | if (!ftlb) | |
3207 | return 0; | |
3208 | return kvm_pv_mmu_flush_tlb(vcpu); | |
3209 | } | |
3210 | case KVM_MMU_OP_RELEASE_PT: { | |
3211 | struct kvm_mmu_op_release_pt *rpt; | |
3212 | ||
3213 | rpt = pv_mmu_read_buffer(buffer, sizeof *rpt); | |
3214 | if (!rpt) | |
3215 | return 0; | |
3216 | return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys); | |
3217 | } | |
3218 | default: return 0; | |
3219 | } | |
3220 | } | |
3221 | ||
3222 | int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes, | |
3223 | gpa_t addr, unsigned long *ret) | |
3224 | { | |
3225 | int r; | |
6ad18fba | 3226 | struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer; |
2f333bcb | 3227 | |
6ad18fba DH |
3228 | buffer->ptr = buffer->buf; |
3229 | buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf); | |
3230 | buffer->processed = 0; | |
2f333bcb | 3231 | |
6ad18fba | 3232 | r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len); |
2f333bcb MT |
3233 | if (r) |
3234 | goto out; | |
3235 | ||
6ad18fba DH |
3236 | while (buffer->len) { |
3237 | r = kvm_pv_mmu_op_one(vcpu, buffer); | |
2f333bcb MT |
3238 | if (r < 0) |
3239 | goto out; | |
3240 | if (r == 0) | |
3241 | break; | |
3242 | } | |
3243 | ||
3244 | r = 1; | |
3245 | out: | |
6ad18fba | 3246 | *ret = buffer->processed; |
2f333bcb MT |
3247 | return r; |
3248 | } | |
3249 | ||
94d8b056 MT |
3250 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
3251 | { | |
3252 | struct kvm_shadow_walk_iterator iterator; | |
3253 | int nr_sptes = 0; | |
3254 | ||
3255 | spin_lock(&vcpu->kvm->mmu_lock); | |
3256 | for_each_shadow_entry(vcpu, addr, iterator) { | |
3257 | sptes[iterator.level-1] = *iterator.sptep; | |
3258 | nr_sptes++; | |
3259 | if (!is_shadow_present_pte(*iterator.sptep)) | |
3260 | break; | |
3261 | } | |
3262 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3263 | ||
3264 | return nr_sptes; | |
3265 | } | |
3266 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
3267 | ||
37a7d8b0 AK |
3268 | #ifdef AUDIT |
3269 | ||
3270 | static const char *audit_msg; | |
3271 | ||
3272 | static gva_t canonicalize(gva_t gva) | |
3273 | { | |
3274 | #ifdef CONFIG_X86_64 | |
3275 | gva = (long long)(gva << 16) >> 16; | |
3276 | #endif | |
3277 | return gva; | |
3278 | } | |
3279 | ||
08a3732b | 3280 | |
805d32de | 3281 | typedef void (*inspect_spte_fn) (struct kvm *kvm, u64 *sptep); |
08a3732b MT |
3282 | |
3283 | static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp, | |
3284 | inspect_spte_fn fn) | |
3285 | { | |
3286 | int i; | |
3287 | ||
3288 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
3289 | u64 ent = sp->spt[i]; | |
3290 | ||
3291 | if (is_shadow_present_pte(ent)) { | |
2920d728 | 3292 | if (!is_last_spte(ent, sp->role.level)) { |
08a3732b MT |
3293 | struct kvm_mmu_page *child; |
3294 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
3295 | __mmu_spte_walk(kvm, child, fn); | |
2920d728 | 3296 | } else |
805d32de | 3297 | fn(kvm, &sp->spt[i]); |
08a3732b MT |
3298 | } |
3299 | } | |
3300 | } | |
3301 | ||
3302 | static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn) | |
3303 | { | |
3304 | int i; | |
3305 | struct kvm_mmu_page *sp; | |
3306 | ||
3307 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
3308 | return; | |
3309 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3310 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
3311 | sp = page_header(root); | |
3312 | __mmu_spte_walk(vcpu->kvm, sp, fn); | |
3313 | return; | |
3314 | } | |
3315 | for (i = 0; i < 4; ++i) { | |
3316 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3317 | ||
3318 | if (root && VALID_PAGE(root)) { | |
3319 | root &= PT64_BASE_ADDR_MASK; | |
3320 | sp = page_header(root); | |
3321 | __mmu_spte_walk(vcpu->kvm, sp, fn); | |
3322 | } | |
3323 | } | |
3324 | return; | |
3325 | } | |
3326 | ||
37a7d8b0 AK |
3327 | static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte, |
3328 | gva_t va, int level) | |
3329 | { | |
3330 | u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK); | |
3331 | int i; | |
3332 | gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1)); | |
3333 | ||
3334 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) { | |
3335 | u64 ent = pt[i]; | |
3336 | ||
c7addb90 | 3337 | if (ent == shadow_trap_nonpresent_pte) |
37a7d8b0 AK |
3338 | continue; |
3339 | ||
3340 | va = canonicalize(va); | |
2920d728 MT |
3341 | if (is_shadow_present_pte(ent) && !is_last_spte(ent, level)) |
3342 | audit_mappings_page(vcpu, ent, va, level - 1); | |
3343 | else { | |
1871c602 | 3344 | gpa_t gpa = kvm_mmu_gva_to_gpa_read(vcpu, va, NULL); |
34382539 JK |
3345 | gfn_t gfn = gpa >> PAGE_SHIFT; |
3346 | pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn); | |
3347 | hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT; | |
37a7d8b0 | 3348 | |
2aaf65e8 MT |
3349 | if (is_error_pfn(pfn)) { |
3350 | kvm_release_pfn_clean(pfn); | |
3351 | continue; | |
3352 | } | |
3353 | ||
c7addb90 | 3354 | if (is_shadow_present_pte(ent) |
37a7d8b0 | 3355 | && (ent & PT64_BASE_ADDR_MASK) != hpa) |
c7addb90 AK |
3356 | printk(KERN_ERR "xx audit error: (%s) levels %d" |
3357 | " gva %lx gpa %llx hpa %llx ent %llx %d\n", | |
ad312c7c | 3358 | audit_msg, vcpu->arch.mmu.root_level, |
d77c26fc MD |
3359 | va, gpa, hpa, ent, |
3360 | is_shadow_present_pte(ent)); | |
c7addb90 AK |
3361 | else if (ent == shadow_notrap_nonpresent_pte |
3362 | && !is_error_hpa(hpa)) | |
3363 | printk(KERN_ERR "audit: (%s) notrap shadow," | |
3364 | " valid guest gva %lx\n", audit_msg, va); | |
35149e21 | 3365 | kvm_release_pfn_clean(pfn); |
c7addb90 | 3366 | |
37a7d8b0 AK |
3367 | } |
3368 | } | |
3369 | } | |
3370 | ||
3371 | static void audit_mappings(struct kvm_vcpu *vcpu) | |
3372 | { | |
1ea252af | 3373 | unsigned i; |
37a7d8b0 | 3374 | |
ad312c7c ZX |
3375 | if (vcpu->arch.mmu.root_level == 4) |
3376 | audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4); | |
37a7d8b0 AK |
3377 | else |
3378 | for (i = 0; i < 4; ++i) | |
ad312c7c | 3379 | if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK) |
37a7d8b0 | 3380 | audit_mappings_page(vcpu, |
ad312c7c | 3381 | vcpu->arch.mmu.pae_root[i], |
37a7d8b0 AK |
3382 | i << 30, |
3383 | 2); | |
3384 | } | |
3385 | ||
3386 | static int count_rmaps(struct kvm_vcpu *vcpu) | |
3387 | { | |
805d32de XG |
3388 | struct kvm *kvm = vcpu->kvm; |
3389 | struct kvm_memslots *slots; | |
37a7d8b0 | 3390 | int nmaps = 0; |
bc6678a3 | 3391 | int i, j, k, idx; |
37a7d8b0 | 3392 | |
bc6678a3 | 3393 | idx = srcu_read_lock(&kvm->srcu); |
90d83dc3 | 3394 | slots = kvm_memslots(kvm); |
37a7d8b0 | 3395 | for (i = 0; i < KVM_MEMORY_SLOTS; ++i) { |
bc6678a3 | 3396 | struct kvm_memory_slot *m = &slots->memslots[i]; |
37a7d8b0 AK |
3397 | struct kvm_rmap_desc *d; |
3398 | ||
3399 | for (j = 0; j < m->npages; ++j) { | |
290fc38d | 3400 | unsigned long *rmapp = &m->rmap[j]; |
37a7d8b0 | 3401 | |
290fc38d | 3402 | if (!*rmapp) |
37a7d8b0 | 3403 | continue; |
290fc38d | 3404 | if (!(*rmapp & 1)) { |
37a7d8b0 AK |
3405 | ++nmaps; |
3406 | continue; | |
3407 | } | |
290fc38d | 3408 | d = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
37a7d8b0 AK |
3409 | while (d) { |
3410 | for (k = 0; k < RMAP_EXT; ++k) | |
d555c333 | 3411 | if (d->sptes[k]) |
37a7d8b0 AK |
3412 | ++nmaps; |
3413 | else | |
3414 | break; | |
3415 | d = d->more; | |
3416 | } | |
3417 | } | |
3418 | } | |
bc6678a3 | 3419 | srcu_read_unlock(&kvm->srcu, idx); |
37a7d8b0 AK |
3420 | return nmaps; |
3421 | } | |
3422 | ||
805d32de | 3423 | void inspect_spte_has_rmap(struct kvm *kvm, u64 *sptep) |
08a3732b MT |
3424 | { |
3425 | unsigned long *rmapp; | |
3426 | struct kvm_mmu_page *rev_sp; | |
3427 | gfn_t gfn; | |
3428 | ||
01c168ac | 3429 | if (is_writable_pte(*sptep)) { |
08a3732b | 3430 | rev_sp = page_header(__pa(sptep)); |
2032a93d | 3431 | gfn = kvm_mmu_page_get_gfn(rev_sp, sptep - rev_sp->spt); |
08a3732b MT |
3432 | |
3433 | if (!gfn_to_memslot(kvm, gfn)) { | |
3434 | if (!printk_ratelimit()) | |
3435 | return; | |
3436 | printk(KERN_ERR "%s: no memslot for gfn %ld\n", | |
3437 | audit_msg, gfn); | |
3438 | printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n", | |
805d32de | 3439 | audit_msg, (long int)(sptep - rev_sp->spt), |
08a3732b MT |
3440 | rev_sp->gfn); |
3441 | dump_stack(); | |
3442 | return; | |
3443 | } | |
3444 | ||
2032a93d | 3445 | rmapp = gfn_to_rmap(kvm, gfn, rev_sp->role.level); |
08a3732b MT |
3446 | if (!*rmapp) { |
3447 | if (!printk_ratelimit()) | |
3448 | return; | |
3449 | printk(KERN_ERR "%s: no rmap for writable spte %llx\n", | |
3450 | audit_msg, *sptep); | |
3451 | dump_stack(); | |
3452 | } | |
3453 | } | |
3454 | ||
3455 | } | |
3456 | ||
3457 | void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu) | |
3458 | { | |
3459 | mmu_spte_walk(vcpu, inspect_spte_has_rmap); | |
3460 | } | |
3461 | ||
3462 | static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu) | |
37a7d8b0 | 3463 | { |
4db35314 | 3464 | struct kvm_mmu_page *sp; |
37a7d8b0 AK |
3465 | int i; |
3466 | ||
f05e70ac | 3467 | list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) { |
4db35314 | 3468 | u64 *pt = sp->spt; |
37a7d8b0 | 3469 | |
4db35314 | 3470 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) |
37a7d8b0 AK |
3471 | continue; |
3472 | ||
3473 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
3474 | u64 ent = pt[i]; | |
3475 | ||
3476 | if (!(ent & PT_PRESENT_MASK)) | |
3477 | continue; | |
01c168ac | 3478 | if (!is_writable_pte(ent)) |
37a7d8b0 | 3479 | continue; |
805d32de | 3480 | inspect_spte_has_rmap(vcpu->kvm, &pt[i]); |
37a7d8b0 AK |
3481 | } |
3482 | } | |
08a3732b | 3483 | return; |
37a7d8b0 AK |
3484 | } |
3485 | ||
3486 | static void audit_rmap(struct kvm_vcpu *vcpu) | |
3487 | { | |
08a3732b MT |
3488 | check_writable_mappings_rmap(vcpu); |
3489 | count_rmaps(vcpu); | |
37a7d8b0 AK |
3490 | } |
3491 | ||
3492 | static void audit_write_protection(struct kvm_vcpu *vcpu) | |
3493 | { | |
4db35314 | 3494 | struct kvm_mmu_page *sp; |
290fc38d IE |
3495 | struct kvm_memory_slot *slot; |
3496 | unsigned long *rmapp; | |
e58b0f9e | 3497 | u64 *spte; |
290fc38d | 3498 | gfn_t gfn; |
37a7d8b0 | 3499 | |
f05e70ac | 3500 | list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) { |
f6e2c02b | 3501 | if (sp->role.direct) |
37a7d8b0 | 3502 | continue; |
e58b0f9e MT |
3503 | if (sp->unsync) |
3504 | continue; | |
37a7d8b0 | 3505 | |
a1f4d395 | 3506 | slot = gfn_to_memslot(vcpu->kvm, sp->gfn); |
290fc38d | 3507 | rmapp = &slot->rmap[gfn - slot->base_gfn]; |
e58b0f9e MT |
3508 | |
3509 | spte = rmap_next(vcpu->kvm, rmapp, NULL); | |
3510 | while (spte) { | |
01c168ac | 3511 | if (is_writable_pte(*spte)) |
e58b0f9e MT |
3512 | printk(KERN_ERR "%s: (%s) shadow page has " |
3513 | "writable mappings: gfn %lx role %x\n", | |
b8688d51 | 3514 | __func__, audit_msg, sp->gfn, |
4db35314 | 3515 | sp->role.word); |
e58b0f9e MT |
3516 | spte = rmap_next(vcpu->kvm, rmapp, spte); |
3517 | } | |
37a7d8b0 AK |
3518 | } |
3519 | } | |
3520 | ||
3521 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) | |
3522 | { | |
3523 | int olddbg = dbg; | |
3524 | ||
3525 | dbg = 0; | |
3526 | audit_msg = msg; | |
3527 | audit_rmap(vcpu); | |
3528 | audit_write_protection(vcpu); | |
2aaf65e8 MT |
3529 | if (strcmp("pre pte write", audit_msg) != 0) |
3530 | audit_mappings(vcpu); | |
08a3732b | 3531 | audit_writable_sptes_have_rmaps(vcpu); |
37a7d8b0 AK |
3532 | dbg = olddbg; |
3533 | } | |
3534 | ||
3535 | #endif |