Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
5f7dde7b | 25 | #include "cpuid.h" |
e495606d | 26 | |
edf88417 | 27 | #include <linux/kvm_host.h> |
6aa8b732 AK |
28 | #include <linux/types.h> |
29 | #include <linux/string.h> | |
6aa8b732 AK |
30 | #include <linux/mm.h> |
31 | #include <linux/highmem.h> | |
32 | #include <linux/module.h> | |
448353ca | 33 | #include <linux/swap.h> |
05da4558 | 34 | #include <linux/hugetlb.h> |
2f333bcb | 35 | #include <linux/compiler.h> |
bc6678a3 | 36 | #include <linux/srcu.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
bf998156 | 38 | #include <linux/uaccess.h> |
6aa8b732 | 39 | |
e495606d AK |
40 | #include <asm/page.h> |
41 | #include <asm/cmpxchg.h> | |
4e542370 | 42 | #include <asm/io.h> |
13673a90 | 43 | #include <asm/vmx.h> |
6aa8b732 | 44 | |
18552672 JR |
45 | /* |
46 | * When setting this variable to true it enables Two-Dimensional-Paging | |
47 | * where the hardware walks 2 page tables: | |
48 | * 1. the guest-virtual to guest-physical | |
49 | * 2. while doing 1. it walks guest-physical to host-physical | |
50 | * If the hardware supports that we don't need to do shadow paging. | |
51 | */ | |
2f333bcb | 52 | bool tdp_enabled = false; |
18552672 | 53 | |
8b1fe17c XG |
54 | enum { |
55 | AUDIT_PRE_PAGE_FAULT, | |
56 | AUDIT_POST_PAGE_FAULT, | |
57 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
58 | AUDIT_POST_PTE_WRITE, |
59 | AUDIT_PRE_SYNC, | |
60 | AUDIT_POST_SYNC | |
8b1fe17c | 61 | }; |
37a7d8b0 | 62 | |
8b1fe17c | 63 | #undef MMU_DEBUG |
37a7d8b0 AK |
64 | |
65 | #ifdef MMU_DEBUG | |
fa4a2c08 PB |
66 | static bool dbg = 0; |
67 | module_param(dbg, bool, 0644); | |
37a7d8b0 AK |
68 | |
69 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
70 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
fa4a2c08 | 71 | #define MMU_WARN_ON(x) WARN_ON(x) |
37a7d8b0 | 72 | #else |
37a7d8b0 AK |
73 | #define pgprintk(x...) do { } while (0) |
74 | #define rmap_printk(x...) do { } while (0) | |
fa4a2c08 | 75 | #define MMU_WARN_ON(x) do { } while (0) |
d6c69ee9 | 76 | #endif |
6aa8b732 | 77 | |
957ed9ef XG |
78 | #define PTE_PREFETCH_NUM 8 |
79 | ||
00763e41 | 80 | #define PT_FIRST_AVAIL_BITS_SHIFT 10 |
6aa8b732 AK |
81 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 |
82 | ||
6aa8b732 AK |
83 | #define PT64_LEVEL_BITS 9 |
84 | ||
85 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 86 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 87 | |
6aa8b732 AK |
88 | #define PT64_INDEX(address, level)\ |
89 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
90 | ||
91 | ||
92 | #define PT32_LEVEL_BITS 10 | |
93 | ||
94 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 95 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 96 | |
e04da980 JR |
97 | #define PT32_LVL_OFFSET_MASK(level) \ |
98 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
99 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
100 | |
101 | #define PT32_INDEX(address, level)\ | |
102 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
103 | ||
104 | ||
27aba766 | 105 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
106 | #define PT64_DIR_BASE_ADDR_MASK \ |
107 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
108 | #define PT64_LVL_ADDR_MASK(level) \ |
109 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
110 | * PT64_LEVEL_BITS))) - 1)) | |
111 | #define PT64_LVL_OFFSET_MASK(level) \ | |
112 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
113 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
114 | |
115 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
116 | #define PT32_DIR_BASE_ADDR_MASK \ | |
117 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
118 | #define PT32_LVL_ADDR_MASK(level) \ |
119 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
120 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 121 | |
53166229 GN |
122 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \ |
123 | | shadow_x_mask | shadow_nx_mask) | |
6aa8b732 | 124 | |
fe135d2c AK |
125 | #define ACC_EXEC_MASK 1 |
126 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
127 | #define ACC_USER_MASK PT_USER_MASK | |
128 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
129 | ||
90bb6fc5 AK |
130 | #include <trace/events/kvm.h> |
131 | ||
07420171 AK |
132 | #define CREATE_TRACE_POINTS |
133 | #include "mmutrace.h" | |
134 | ||
49fde340 XG |
135 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
136 | #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1)) | |
1403283a | 137 | |
135f8c2b AK |
138 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
139 | ||
220f773a TY |
140 | /* make pte_list_desc fit well in cache line */ |
141 | #define PTE_LIST_EXT 3 | |
142 | ||
53c07b18 XG |
143 | struct pte_list_desc { |
144 | u64 *sptes[PTE_LIST_EXT]; | |
145 | struct pte_list_desc *more; | |
cd4a4e53 AK |
146 | }; |
147 | ||
2d11123a AK |
148 | struct kvm_shadow_walk_iterator { |
149 | u64 addr; | |
150 | hpa_t shadow_addr; | |
2d11123a | 151 | u64 *sptep; |
dd3bfd59 | 152 | int level; |
2d11123a AK |
153 | unsigned index; |
154 | }; | |
155 | ||
156 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
157 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
158 | shadow_walk_okay(&(_walker)); \ | |
159 | shadow_walk_next(&(_walker))) | |
160 | ||
c2a2ac2b XG |
161 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
162 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
163 | shadow_walk_okay(&(_walker)) && \ | |
164 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
165 | __shadow_walk_next(&(_walker), spte)) | |
166 | ||
53c07b18 | 167 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 168 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 169 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 170 | |
7b52345e SY |
171 | static u64 __read_mostly shadow_nx_mask; |
172 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
173 | static u64 __read_mostly shadow_user_mask; | |
174 | static u64 __read_mostly shadow_accessed_mask; | |
175 | static u64 __read_mostly shadow_dirty_mask; | |
ce88decf XG |
176 | static u64 __read_mostly shadow_mmio_mask; |
177 | ||
178 | static void mmu_spte_set(u64 *sptep, u64 spte); | |
e676505a | 179 | static void mmu_free_roots(struct kvm_vcpu *vcpu); |
ce88decf XG |
180 | |
181 | void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask) | |
182 | { | |
183 | shadow_mmio_mask = mmio_mask; | |
184 | } | |
185 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); | |
186 | ||
f2fd125d | 187 | /* |
ee3d1570 DM |
188 | * the low bit of the generation number is always presumed to be zero. |
189 | * This disables mmio caching during memslot updates. The concept is | |
190 | * similar to a seqcount but instead of retrying the access we just punt | |
191 | * and ignore the cache. | |
192 | * | |
193 | * spte bits 3-11 are used as bits 1-9 of the generation number, | |
194 | * the bits 52-61 are used as bits 10-19 of the generation number. | |
f2fd125d | 195 | */ |
ee3d1570 | 196 | #define MMIO_SPTE_GEN_LOW_SHIFT 2 |
f2fd125d XG |
197 | #define MMIO_SPTE_GEN_HIGH_SHIFT 52 |
198 | ||
ee3d1570 DM |
199 | #define MMIO_GEN_SHIFT 20 |
200 | #define MMIO_GEN_LOW_SHIFT 10 | |
201 | #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2) | |
f8f55942 | 202 | #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1) |
f2fd125d XG |
203 | |
204 | static u64 generation_mmio_spte_mask(unsigned int gen) | |
205 | { | |
206 | u64 mask; | |
207 | ||
842bb26a | 208 | WARN_ON(gen & ~MMIO_GEN_MASK); |
f2fd125d XG |
209 | |
210 | mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT; | |
211 | mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT; | |
212 | return mask; | |
213 | } | |
214 | ||
215 | static unsigned int get_mmio_spte_generation(u64 spte) | |
216 | { | |
217 | unsigned int gen; | |
218 | ||
219 | spte &= ~shadow_mmio_mask; | |
220 | ||
221 | gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK; | |
222 | gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT; | |
223 | return gen; | |
224 | } | |
225 | ||
f8f55942 XG |
226 | static unsigned int kvm_current_mmio_generation(struct kvm *kvm) |
227 | { | |
00f034a1 | 228 | return kvm_memslots(kvm)->generation & MMIO_GEN_MASK; |
f8f55942 XG |
229 | } |
230 | ||
f2fd125d XG |
231 | static void mark_mmio_spte(struct kvm *kvm, u64 *sptep, u64 gfn, |
232 | unsigned access) | |
ce88decf | 233 | { |
f8f55942 XG |
234 | unsigned int gen = kvm_current_mmio_generation(kvm); |
235 | u64 mask = generation_mmio_spte_mask(gen); | |
95b0430d | 236 | |
ce88decf | 237 | access &= ACC_WRITE_MASK | ACC_USER_MASK; |
f2fd125d | 238 | mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT; |
f2fd125d | 239 | |
f8f55942 | 240 | trace_mark_mmio_spte(sptep, gfn, access, gen); |
f2fd125d | 241 | mmu_spte_set(sptep, mask); |
ce88decf XG |
242 | } |
243 | ||
244 | static bool is_mmio_spte(u64 spte) | |
245 | { | |
246 | return (spte & shadow_mmio_mask) == shadow_mmio_mask; | |
247 | } | |
248 | ||
249 | static gfn_t get_mmio_spte_gfn(u64 spte) | |
250 | { | |
842bb26a | 251 | u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask; |
f2fd125d | 252 | return (spte & ~mask) >> PAGE_SHIFT; |
ce88decf XG |
253 | } |
254 | ||
255 | static unsigned get_mmio_spte_access(u64 spte) | |
256 | { | |
842bb26a | 257 | u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask; |
f2fd125d | 258 | return (spte & ~mask) & ~PAGE_MASK; |
ce88decf XG |
259 | } |
260 | ||
f2fd125d XG |
261 | static bool set_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn, |
262 | pfn_t pfn, unsigned access) | |
ce88decf XG |
263 | { |
264 | if (unlikely(is_noslot_pfn(pfn))) { | |
f2fd125d | 265 | mark_mmio_spte(kvm, sptep, gfn, access); |
ce88decf XG |
266 | return true; |
267 | } | |
268 | ||
269 | return false; | |
270 | } | |
c7addb90 | 271 | |
f8f55942 XG |
272 | static bool check_mmio_spte(struct kvm *kvm, u64 spte) |
273 | { | |
089504c0 XG |
274 | unsigned int kvm_gen, spte_gen; |
275 | ||
276 | kvm_gen = kvm_current_mmio_generation(kvm); | |
277 | spte_gen = get_mmio_spte_generation(spte); | |
278 | ||
279 | trace_check_mmio_spte(spte, kvm_gen, spte_gen); | |
280 | return likely(kvm_gen == spte_gen); | |
f8f55942 XG |
281 | } |
282 | ||
7b52345e | 283 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 284 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
285 | { |
286 | shadow_user_mask = user_mask; | |
287 | shadow_accessed_mask = accessed_mask; | |
288 | shadow_dirty_mask = dirty_mask; | |
289 | shadow_nx_mask = nx_mask; | |
290 | shadow_x_mask = x_mask; | |
291 | } | |
292 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
293 | ||
6aa8b732 AK |
294 | static int is_cpuid_PSE36(void) |
295 | { | |
296 | return 1; | |
297 | } | |
298 | ||
73b1087e AK |
299 | static int is_nx(struct kvm_vcpu *vcpu) |
300 | { | |
f6801dff | 301 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
302 | } |
303 | ||
c7addb90 AK |
304 | static int is_shadow_present_pte(u64 pte) |
305 | { | |
ce88decf | 306 | return pte & PT_PRESENT_MASK && !is_mmio_spte(pte); |
c7addb90 AK |
307 | } |
308 | ||
05da4558 MT |
309 | static int is_large_pte(u64 pte) |
310 | { | |
311 | return pte & PT_PAGE_SIZE_MASK; | |
312 | } | |
313 | ||
43a3795a | 314 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 315 | { |
4b1a80fa | 316 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
317 | } |
318 | ||
776e6633 MT |
319 | static int is_last_spte(u64 pte, int level) |
320 | { | |
321 | if (level == PT_PAGE_TABLE_LEVEL) | |
322 | return 1; | |
852e3c19 | 323 | if (is_large_pte(pte)) |
776e6633 MT |
324 | return 1; |
325 | return 0; | |
326 | } | |
327 | ||
35149e21 | 328 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 329 | { |
35149e21 | 330 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
331 | } |
332 | ||
da928521 AK |
333 | static gfn_t pse36_gfn_delta(u32 gpte) |
334 | { | |
335 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
336 | ||
337 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
338 | } | |
339 | ||
603e0651 | 340 | #ifdef CONFIG_X86_64 |
d555c333 | 341 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 342 | { |
603e0651 | 343 | *sptep = spte; |
e663ee64 AK |
344 | } |
345 | ||
603e0651 | 346 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 347 | { |
603e0651 XG |
348 | *sptep = spte; |
349 | } | |
350 | ||
351 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
352 | { | |
353 | return xchg(sptep, spte); | |
354 | } | |
c2a2ac2b XG |
355 | |
356 | static u64 __get_spte_lockless(u64 *sptep) | |
357 | { | |
358 | return ACCESS_ONCE(*sptep); | |
359 | } | |
ce88decf XG |
360 | |
361 | static bool __check_direct_spte_mmio_pf(u64 spte) | |
362 | { | |
363 | /* It is valid if the spte is zapped. */ | |
364 | return spte == 0ull; | |
365 | } | |
a9221dd5 | 366 | #else |
603e0651 XG |
367 | union split_spte { |
368 | struct { | |
369 | u32 spte_low; | |
370 | u32 spte_high; | |
371 | }; | |
372 | u64 spte; | |
373 | }; | |
a9221dd5 | 374 | |
c2a2ac2b XG |
375 | static void count_spte_clear(u64 *sptep, u64 spte) |
376 | { | |
377 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
378 | ||
379 | if (is_shadow_present_pte(spte)) | |
380 | return; | |
381 | ||
382 | /* Ensure the spte is completely set before we increase the count */ | |
383 | smp_wmb(); | |
384 | sp->clear_spte_count++; | |
385 | } | |
386 | ||
603e0651 XG |
387 | static void __set_spte(u64 *sptep, u64 spte) |
388 | { | |
389 | union split_spte *ssptep, sspte; | |
a9221dd5 | 390 | |
603e0651 XG |
391 | ssptep = (union split_spte *)sptep; |
392 | sspte = (union split_spte)spte; | |
393 | ||
394 | ssptep->spte_high = sspte.spte_high; | |
395 | ||
396 | /* | |
397 | * If we map the spte from nonpresent to present, We should store | |
398 | * the high bits firstly, then set present bit, so cpu can not | |
399 | * fetch this spte while we are setting the spte. | |
400 | */ | |
401 | smp_wmb(); | |
402 | ||
403 | ssptep->spte_low = sspte.spte_low; | |
a9221dd5 AK |
404 | } |
405 | ||
603e0651 XG |
406 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
407 | { | |
408 | union split_spte *ssptep, sspte; | |
409 | ||
410 | ssptep = (union split_spte *)sptep; | |
411 | sspte = (union split_spte)spte; | |
412 | ||
413 | ssptep->spte_low = sspte.spte_low; | |
414 | ||
415 | /* | |
416 | * If we map the spte from present to nonpresent, we should clear | |
417 | * present bit firstly to avoid vcpu fetch the old high bits. | |
418 | */ | |
419 | smp_wmb(); | |
420 | ||
421 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 422 | count_spte_clear(sptep, spte); |
603e0651 XG |
423 | } |
424 | ||
425 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
426 | { | |
427 | union split_spte *ssptep, sspte, orig; | |
428 | ||
429 | ssptep = (union split_spte *)sptep; | |
430 | sspte = (union split_spte)spte; | |
431 | ||
432 | /* xchg acts as a barrier before the setting of the high bits */ | |
433 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
434 | orig.spte_high = ssptep->spte_high; |
435 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 436 | count_spte_clear(sptep, spte); |
603e0651 XG |
437 | |
438 | return orig.spte; | |
439 | } | |
c2a2ac2b XG |
440 | |
441 | /* | |
442 | * The idea using the light way get the spte on x86_32 guest is from | |
443 | * gup_get_pte(arch/x86/mm/gup.c). | |
accaefe0 XG |
444 | * |
445 | * An spte tlb flush may be pending, because kvm_set_pte_rmapp | |
446 | * coalesces them and we are running out of the MMU lock. Therefore | |
447 | * we need to protect against in-progress updates of the spte. | |
448 | * | |
449 | * Reading the spte while an update is in progress may get the old value | |
450 | * for the high part of the spte. The race is fine for a present->non-present | |
451 | * change (because the high part of the spte is ignored for non-present spte), | |
452 | * but for a present->present change we must reread the spte. | |
453 | * | |
454 | * All such changes are done in two steps (present->non-present and | |
455 | * non-present->present), hence it is enough to count the number of | |
456 | * present->non-present updates: if it changed while reading the spte, | |
457 | * we might have hit the race. This is done using clear_spte_count. | |
c2a2ac2b XG |
458 | */ |
459 | static u64 __get_spte_lockless(u64 *sptep) | |
460 | { | |
461 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
462 | union split_spte spte, *orig = (union split_spte *)sptep; | |
463 | int count; | |
464 | ||
465 | retry: | |
466 | count = sp->clear_spte_count; | |
467 | smp_rmb(); | |
468 | ||
469 | spte.spte_low = orig->spte_low; | |
470 | smp_rmb(); | |
471 | ||
472 | spte.spte_high = orig->spte_high; | |
473 | smp_rmb(); | |
474 | ||
475 | if (unlikely(spte.spte_low != orig->spte_low || | |
476 | count != sp->clear_spte_count)) | |
477 | goto retry; | |
478 | ||
479 | return spte.spte; | |
480 | } | |
ce88decf XG |
481 | |
482 | static bool __check_direct_spte_mmio_pf(u64 spte) | |
483 | { | |
484 | union split_spte sspte = (union split_spte)spte; | |
485 | u32 high_mmio_mask = shadow_mmio_mask >> 32; | |
486 | ||
487 | /* It is valid if the spte is zapped. */ | |
488 | if (spte == 0ull) | |
489 | return true; | |
490 | ||
491 | /* It is valid if the spte is being zapped. */ | |
492 | if (sspte.spte_low == 0ull && | |
493 | (sspte.spte_high & high_mmio_mask) == high_mmio_mask) | |
494 | return true; | |
495 | ||
496 | return false; | |
497 | } | |
603e0651 XG |
498 | #endif |
499 | ||
c7ba5b48 XG |
500 | static bool spte_is_locklessly_modifiable(u64 spte) |
501 | { | |
feb3eb70 GN |
502 | return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) == |
503 | (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE); | |
c7ba5b48 XG |
504 | } |
505 | ||
8672b721 XG |
506 | static bool spte_has_volatile_bits(u64 spte) |
507 | { | |
c7ba5b48 XG |
508 | /* |
509 | * Always atomicly update spte if it can be updated | |
510 | * out of mmu-lock, it can ensure dirty bit is not lost, | |
511 | * also, it can help us to get a stable is_writable_pte() | |
512 | * to ensure tlb flush is not missed. | |
513 | */ | |
514 | if (spte_is_locklessly_modifiable(spte)) | |
515 | return true; | |
516 | ||
8672b721 XG |
517 | if (!shadow_accessed_mask) |
518 | return false; | |
519 | ||
520 | if (!is_shadow_present_pte(spte)) | |
521 | return false; | |
522 | ||
4132779b XG |
523 | if ((spte & shadow_accessed_mask) && |
524 | (!is_writable_pte(spte) || (spte & shadow_dirty_mask))) | |
8672b721 XG |
525 | return false; |
526 | ||
527 | return true; | |
528 | } | |
529 | ||
4132779b XG |
530 | static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask) |
531 | { | |
532 | return (old_spte & bit_mask) && !(new_spte & bit_mask); | |
533 | } | |
534 | ||
7e71a59b KH |
535 | static bool spte_is_bit_changed(u64 old_spte, u64 new_spte, u64 bit_mask) |
536 | { | |
537 | return (old_spte & bit_mask) != (new_spte & bit_mask); | |
538 | } | |
539 | ||
1df9f2dc XG |
540 | /* Rules for using mmu_spte_set: |
541 | * Set the sptep from nonpresent to present. | |
542 | * Note: the sptep being assigned *must* be either not present | |
543 | * or in a state where the hardware will not attempt to update | |
544 | * the spte. | |
545 | */ | |
546 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
547 | { | |
548 | WARN_ON(is_shadow_present_pte(*sptep)); | |
549 | __set_spte(sptep, new_spte); | |
550 | } | |
551 | ||
552 | /* Rules for using mmu_spte_update: | |
553 | * Update the state bits, it means the mapped pfn is not changged. | |
6e7d0354 XG |
554 | * |
555 | * Whenever we overwrite a writable spte with a read-only one we | |
556 | * should flush remote TLBs. Otherwise rmap_write_protect | |
557 | * will find a read-only spte, even though the writable spte | |
558 | * might be cached on a CPU's TLB, the return value indicates this | |
559 | * case. | |
1df9f2dc | 560 | */ |
6e7d0354 | 561 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) |
b79b93f9 | 562 | { |
c7ba5b48 | 563 | u64 old_spte = *sptep; |
6e7d0354 | 564 | bool ret = false; |
4132779b XG |
565 | |
566 | WARN_ON(!is_rmap_spte(new_spte)); | |
b79b93f9 | 567 | |
6e7d0354 XG |
568 | if (!is_shadow_present_pte(old_spte)) { |
569 | mmu_spte_set(sptep, new_spte); | |
570 | return ret; | |
571 | } | |
4132779b | 572 | |
c7ba5b48 | 573 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 574 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 575 | else |
603e0651 | 576 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 577 | |
c7ba5b48 XG |
578 | /* |
579 | * For the spte updated out of mmu-lock is safe, since | |
580 | * we always atomicly update it, see the comments in | |
581 | * spte_has_volatile_bits(). | |
582 | */ | |
7f31c959 XG |
583 | if (spte_is_locklessly_modifiable(old_spte) && |
584 | !is_writable_pte(new_spte)) | |
6e7d0354 XG |
585 | ret = true; |
586 | ||
4132779b | 587 | if (!shadow_accessed_mask) |
6e7d0354 | 588 | return ret; |
4132779b | 589 | |
7e71a59b KH |
590 | /* |
591 | * Flush TLB when accessed/dirty bits are changed in the page tables, | |
592 | * to guarantee consistency between TLB and page tables. | |
593 | */ | |
594 | if (spte_is_bit_changed(old_spte, new_spte, | |
595 | shadow_accessed_mask | shadow_dirty_mask)) | |
596 | ret = true; | |
597 | ||
4132779b XG |
598 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask)) |
599 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); | |
600 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask)) | |
601 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); | |
6e7d0354 XG |
602 | |
603 | return ret; | |
b79b93f9 AK |
604 | } |
605 | ||
1df9f2dc XG |
606 | /* |
607 | * Rules for using mmu_spte_clear_track_bits: | |
608 | * It sets the sptep from present to nonpresent, and track the | |
609 | * state bits, it is used to clear the last level sptep. | |
610 | */ | |
611 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
612 | { | |
613 | pfn_t pfn; | |
614 | u64 old_spte = *sptep; | |
615 | ||
616 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 617 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 618 | else |
603e0651 | 619 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc XG |
620 | |
621 | if (!is_rmap_spte(old_spte)) | |
622 | return 0; | |
623 | ||
624 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
625 | |
626 | /* | |
627 | * KVM does not hold the refcount of the page used by | |
628 | * kvm mmu, before reclaiming the page, we should | |
629 | * unmap it from mmu first. | |
630 | */ | |
bf4bea8e | 631 | WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn))); |
86fde74c | 632 | |
1df9f2dc XG |
633 | if (!shadow_accessed_mask || old_spte & shadow_accessed_mask) |
634 | kvm_set_pfn_accessed(pfn); | |
635 | if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask)) | |
636 | kvm_set_pfn_dirty(pfn); | |
637 | return 1; | |
638 | } | |
639 | ||
640 | /* | |
641 | * Rules for using mmu_spte_clear_no_track: | |
642 | * Directly clear spte without caring the state bits of sptep, | |
643 | * it is used to set the upper level spte. | |
644 | */ | |
645 | static void mmu_spte_clear_no_track(u64 *sptep) | |
646 | { | |
603e0651 | 647 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
648 | } |
649 | ||
c2a2ac2b XG |
650 | static u64 mmu_spte_get_lockless(u64 *sptep) |
651 | { | |
652 | return __get_spte_lockless(sptep); | |
653 | } | |
654 | ||
655 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) | |
656 | { | |
c142786c AK |
657 | /* |
658 | * Prevent page table teardown by making any free-er wait during | |
659 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
660 | */ | |
661 | local_irq_disable(); | |
662 | vcpu->mode = READING_SHADOW_PAGE_TABLES; | |
663 | /* | |
664 | * Make sure a following spte read is not reordered ahead of the write | |
665 | * to vcpu->mode. | |
666 | */ | |
667 | smp_mb(); | |
c2a2ac2b XG |
668 | } |
669 | ||
670 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
671 | { | |
c142786c AK |
672 | /* |
673 | * Make sure the write to vcpu->mode is not reordered in front of | |
674 | * reads to sptes. If it does, kvm_commit_zap_page() can see us | |
675 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. | |
676 | */ | |
677 | smp_mb(); | |
678 | vcpu->mode = OUTSIDE_GUEST_MODE; | |
679 | local_irq_enable(); | |
c2a2ac2b XG |
680 | } |
681 | ||
e2dec939 | 682 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 683 | struct kmem_cache *base_cache, int min) |
714b93da AK |
684 | { |
685 | void *obj; | |
686 | ||
687 | if (cache->nobjs >= min) | |
e2dec939 | 688 | return 0; |
714b93da | 689 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 690 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 691 | if (!obj) |
e2dec939 | 692 | return -ENOMEM; |
714b93da AK |
693 | cache->objects[cache->nobjs++] = obj; |
694 | } | |
e2dec939 | 695 | return 0; |
714b93da AK |
696 | } |
697 | ||
f759e2b4 XG |
698 | static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache) |
699 | { | |
700 | return cache->nobjs; | |
701 | } | |
702 | ||
e8ad9a70 XG |
703 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
704 | struct kmem_cache *cache) | |
714b93da AK |
705 | { |
706 | while (mc->nobjs) | |
e8ad9a70 | 707 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
708 | } |
709 | ||
c1158e63 | 710 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 711 | int min) |
c1158e63 | 712 | { |
842f22ed | 713 | void *page; |
c1158e63 AK |
714 | |
715 | if (cache->nobjs >= min) | |
716 | return 0; | |
717 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
842f22ed | 718 | page = (void *)__get_free_page(GFP_KERNEL); |
c1158e63 AK |
719 | if (!page) |
720 | return -ENOMEM; | |
842f22ed | 721 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
722 | } |
723 | return 0; | |
724 | } | |
725 | ||
726 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
727 | { | |
728 | while (mc->nobjs) | |
c4d198d5 | 729 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
730 | } |
731 | ||
2e3e5882 | 732 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 733 | { |
e2dec939 AK |
734 | int r; |
735 | ||
53c07b18 | 736 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 737 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
738 | if (r) |
739 | goto out; | |
ad312c7c | 740 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
741 | if (r) |
742 | goto out; | |
ad312c7c | 743 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 744 | mmu_page_header_cache, 4); |
e2dec939 AK |
745 | out: |
746 | return r; | |
714b93da AK |
747 | } |
748 | ||
749 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
750 | { | |
53c07b18 XG |
751 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
752 | pte_list_desc_cache); | |
ad312c7c | 753 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
754 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
755 | mmu_page_header_cache); | |
714b93da AK |
756 | } |
757 | ||
80feb89a | 758 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) |
714b93da AK |
759 | { |
760 | void *p; | |
761 | ||
762 | BUG_ON(!mc->nobjs); | |
763 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
764 | return p; |
765 | } | |
766 | ||
53c07b18 | 767 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 768 | { |
80feb89a | 769 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
770 | } |
771 | ||
53c07b18 | 772 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 773 | { |
53c07b18 | 774 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
775 | } |
776 | ||
2032a93d LJ |
777 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
778 | { | |
779 | if (!sp->role.direct) | |
780 | return sp->gfns[index]; | |
781 | ||
782 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
783 | } | |
784 | ||
785 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
786 | { | |
787 | if (sp->role.direct) | |
788 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
789 | else | |
790 | sp->gfns[index] = gfn; | |
791 | } | |
792 | ||
05da4558 | 793 | /* |
d4dbf470 TY |
794 | * Return the pointer to the large page information for a given gfn, |
795 | * handling slots that are not large page aligned. | |
05da4558 | 796 | */ |
d4dbf470 TY |
797 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
798 | struct kvm_memory_slot *slot, | |
799 | int level) | |
05da4558 MT |
800 | { |
801 | unsigned long idx; | |
802 | ||
fb03cb6f | 803 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 804 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
805 | } |
806 | ||
807 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
808 | { | |
d25797b2 | 809 | struct kvm_memory_slot *slot; |
d4dbf470 | 810 | struct kvm_lpage_info *linfo; |
d25797b2 | 811 | int i; |
05da4558 | 812 | |
a1f4d395 | 813 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
814 | for (i = PT_DIRECTORY_LEVEL; |
815 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
816 | linfo = lpage_info_slot(gfn, slot, i); |
817 | linfo->write_count += 1; | |
d25797b2 | 818 | } |
332b207d | 819 | kvm->arch.indirect_shadow_pages++; |
05da4558 MT |
820 | } |
821 | ||
822 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
823 | { | |
d25797b2 | 824 | struct kvm_memory_slot *slot; |
d4dbf470 | 825 | struct kvm_lpage_info *linfo; |
d25797b2 | 826 | int i; |
05da4558 | 827 | |
a1f4d395 | 828 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
829 | for (i = PT_DIRECTORY_LEVEL; |
830 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
831 | linfo = lpage_info_slot(gfn, slot, i); |
832 | linfo->write_count -= 1; | |
833 | WARN_ON(linfo->write_count < 0); | |
d25797b2 | 834 | } |
332b207d | 835 | kvm->arch.indirect_shadow_pages--; |
05da4558 MT |
836 | } |
837 | ||
d25797b2 JR |
838 | static int has_wrprotected_page(struct kvm *kvm, |
839 | gfn_t gfn, | |
840 | int level) | |
05da4558 | 841 | { |
2843099f | 842 | struct kvm_memory_slot *slot; |
d4dbf470 | 843 | struct kvm_lpage_info *linfo; |
05da4558 | 844 | |
a1f4d395 | 845 | slot = gfn_to_memslot(kvm, gfn); |
05da4558 | 846 | if (slot) { |
d4dbf470 TY |
847 | linfo = lpage_info_slot(gfn, slot, level); |
848 | return linfo->write_count; | |
05da4558 MT |
849 | } |
850 | ||
851 | return 1; | |
852 | } | |
853 | ||
d25797b2 | 854 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 855 | { |
8f0b1ab6 | 856 | unsigned long page_size; |
d25797b2 | 857 | int i, ret = 0; |
05da4558 | 858 | |
8f0b1ab6 | 859 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 860 | |
d25797b2 JR |
861 | for (i = PT_PAGE_TABLE_LEVEL; |
862 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
863 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
864 | ret = i; | |
865 | else | |
866 | break; | |
867 | } | |
868 | ||
4c2155ce | 869 | return ret; |
05da4558 MT |
870 | } |
871 | ||
5d163b1c XG |
872 | static struct kvm_memory_slot * |
873 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
874 | bool no_dirty_log) | |
05da4558 MT |
875 | { |
876 | struct kvm_memory_slot *slot; | |
5d163b1c XG |
877 | |
878 | slot = gfn_to_memslot(vcpu->kvm, gfn); | |
879 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID || | |
880 | (no_dirty_log && slot->dirty_bitmap)) | |
881 | slot = NULL; | |
882 | ||
883 | return slot; | |
884 | } | |
885 | ||
886 | static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
887 | { | |
a0a8eaba | 888 | return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true); |
936a5fe6 AA |
889 | } |
890 | ||
891 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
892 | { | |
893 | int host_level, level, max_level; | |
05da4558 | 894 | |
d25797b2 JR |
895 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
896 | ||
897 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
898 | return host_level; | |
899 | ||
55dd98c3 | 900 | max_level = min(kvm_x86_ops->get_lpage_level(), host_level); |
878403b7 SY |
901 | |
902 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
903 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
904 | break; | |
d25797b2 JR |
905 | |
906 | return level - 1; | |
05da4558 MT |
907 | } |
908 | ||
290fc38d | 909 | /* |
53c07b18 | 910 | * Pte mapping structures: |
cd4a4e53 | 911 | * |
53c07b18 | 912 | * If pte_list bit zero is zero, then pte_list point to the spte. |
cd4a4e53 | 913 | * |
53c07b18 XG |
914 | * If pte_list bit zero is one, (then pte_list & ~1) points to a struct |
915 | * pte_list_desc containing more mappings. | |
53a27b39 | 916 | * |
53c07b18 | 917 | * Returns the number of pte entries before the spte was added or zero if |
53a27b39 MT |
918 | * the spte was not added. |
919 | * | |
cd4a4e53 | 920 | */ |
53c07b18 XG |
921 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
922 | unsigned long *pte_list) | |
cd4a4e53 | 923 | { |
53c07b18 | 924 | struct pte_list_desc *desc; |
53a27b39 | 925 | int i, count = 0; |
cd4a4e53 | 926 | |
53c07b18 XG |
927 | if (!*pte_list) { |
928 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); | |
929 | *pte_list = (unsigned long)spte; | |
930 | } else if (!(*pte_list & 1)) { | |
931 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); | |
932 | desc = mmu_alloc_pte_list_desc(vcpu); | |
933 | desc->sptes[0] = (u64 *)*pte_list; | |
d555c333 | 934 | desc->sptes[1] = spte; |
53c07b18 | 935 | *pte_list = (unsigned long)desc | 1; |
cb16a7b3 | 936 | ++count; |
cd4a4e53 | 937 | } else { |
53c07b18 XG |
938 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
939 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
940 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { | |
cd4a4e53 | 941 | desc = desc->more; |
53c07b18 | 942 | count += PTE_LIST_EXT; |
53a27b39 | 943 | } |
53c07b18 XG |
944 | if (desc->sptes[PTE_LIST_EXT-1]) { |
945 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
946 | desc = desc->more; |
947 | } | |
d555c333 | 948 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 949 | ++count; |
d555c333 | 950 | desc->sptes[i] = spte; |
cd4a4e53 | 951 | } |
53a27b39 | 952 | return count; |
cd4a4e53 AK |
953 | } |
954 | ||
53c07b18 XG |
955 | static void |
956 | pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc, | |
957 | int i, struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
958 | { |
959 | int j; | |
960 | ||
53c07b18 | 961 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 962 | ; |
d555c333 AK |
963 | desc->sptes[i] = desc->sptes[j]; |
964 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
965 | if (j != 0) |
966 | return; | |
967 | if (!prev_desc && !desc->more) | |
53c07b18 | 968 | *pte_list = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
969 | else |
970 | if (prev_desc) | |
971 | prev_desc->more = desc->more; | |
972 | else | |
53c07b18 XG |
973 | *pte_list = (unsigned long)desc->more | 1; |
974 | mmu_free_pte_list_desc(desc); | |
cd4a4e53 AK |
975 | } |
976 | ||
53c07b18 | 977 | static void pte_list_remove(u64 *spte, unsigned long *pte_list) |
cd4a4e53 | 978 | { |
53c07b18 XG |
979 | struct pte_list_desc *desc; |
980 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
981 | int i; |
982 | ||
53c07b18 XG |
983 | if (!*pte_list) { |
984 | printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte); | |
cd4a4e53 | 985 | BUG(); |
53c07b18 XG |
986 | } else if (!(*pte_list & 1)) { |
987 | rmap_printk("pte_list_remove: %p 1->0\n", spte); | |
988 | if ((u64 *)*pte_list != spte) { | |
989 | printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte); | |
cd4a4e53 AK |
990 | BUG(); |
991 | } | |
53c07b18 | 992 | *pte_list = 0; |
cd4a4e53 | 993 | } else { |
53c07b18 XG |
994 | rmap_printk("pte_list_remove: %p many->many\n", spte); |
995 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
cd4a4e53 AK |
996 | prev_desc = NULL; |
997 | while (desc) { | |
53c07b18 | 998 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) |
d555c333 | 999 | if (desc->sptes[i] == spte) { |
53c07b18 | 1000 | pte_list_desc_remove_entry(pte_list, |
714b93da | 1001 | desc, i, |
cd4a4e53 AK |
1002 | prev_desc); |
1003 | return; | |
1004 | } | |
1005 | prev_desc = desc; | |
1006 | desc = desc->more; | |
1007 | } | |
53c07b18 | 1008 | pr_err("pte_list_remove: %p many->many\n", spte); |
cd4a4e53 AK |
1009 | BUG(); |
1010 | } | |
1011 | } | |
1012 | ||
67052b35 XG |
1013 | typedef void (*pte_list_walk_fn) (u64 *spte); |
1014 | static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn) | |
1015 | { | |
1016 | struct pte_list_desc *desc; | |
1017 | int i; | |
1018 | ||
1019 | if (!*pte_list) | |
1020 | return; | |
1021 | ||
1022 | if (!(*pte_list & 1)) | |
1023 | return fn((u64 *)*pte_list); | |
1024 | ||
1025 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
1026 | while (desc) { | |
1027 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) | |
1028 | fn(desc->sptes[i]); | |
1029 | desc = desc->more; | |
1030 | } | |
1031 | } | |
1032 | ||
9373e2c0 | 1033 | static unsigned long *__gfn_to_rmap(gfn_t gfn, int level, |
9b9b1492 | 1034 | struct kvm_memory_slot *slot) |
53c07b18 | 1035 | { |
77d11309 | 1036 | unsigned long idx; |
53c07b18 | 1037 | |
77d11309 | 1038 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
d89cc617 | 1039 | return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx]; |
53c07b18 XG |
1040 | } |
1041 | ||
9b9b1492 TY |
1042 | /* |
1043 | * Take gfn and return the reverse mapping to it. | |
1044 | */ | |
1045 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) | |
1046 | { | |
1047 | struct kvm_memory_slot *slot; | |
1048 | ||
1049 | slot = gfn_to_memslot(kvm, gfn); | |
9373e2c0 | 1050 | return __gfn_to_rmap(gfn, level, slot); |
9b9b1492 TY |
1051 | } |
1052 | ||
f759e2b4 XG |
1053 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
1054 | { | |
1055 | struct kvm_mmu_memory_cache *cache; | |
1056 | ||
1057 | cache = &vcpu->arch.mmu_pte_list_desc_cache; | |
1058 | return mmu_memory_cache_free_objects(cache); | |
1059 | } | |
1060 | ||
53c07b18 XG |
1061 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
1062 | { | |
1063 | struct kvm_mmu_page *sp; | |
1064 | unsigned long *rmapp; | |
1065 | ||
53c07b18 XG |
1066 | sp = page_header(__pa(spte)); |
1067 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
1068 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); | |
1069 | return pte_list_add(vcpu, spte, rmapp); | |
1070 | } | |
1071 | ||
53c07b18 XG |
1072 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
1073 | { | |
1074 | struct kvm_mmu_page *sp; | |
1075 | gfn_t gfn; | |
1076 | unsigned long *rmapp; | |
1077 | ||
1078 | sp = page_header(__pa(spte)); | |
1079 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
1080 | rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); | |
1081 | pte_list_remove(spte, rmapp); | |
1082 | } | |
1083 | ||
1e3f42f0 TY |
1084 | /* |
1085 | * Used by the following functions to iterate through the sptes linked by a | |
1086 | * rmap. All fields are private and not assumed to be used outside. | |
1087 | */ | |
1088 | struct rmap_iterator { | |
1089 | /* private fields */ | |
1090 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1091 | int pos; /* index of the sptep */ | |
1092 | }; | |
1093 | ||
1094 | /* | |
1095 | * Iteration must be started by this function. This should also be used after | |
1096 | * removing/dropping sptes from the rmap link because in such cases the | |
1097 | * information in the itererator may not be valid. | |
1098 | * | |
1099 | * Returns sptep if found, NULL otherwise. | |
1100 | */ | |
1101 | static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter) | |
1102 | { | |
1103 | if (!rmap) | |
1104 | return NULL; | |
1105 | ||
1106 | if (!(rmap & 1)) { | |
1107 | iter->desc = NULL; | |
1108 | return (u64 *)rmap; | |
1109 | } | |
1110 | ||
1111 | iter->desc = (struct pte_list_desc *)(rmap & ~1ul); | |
1112 | iter->pos = 0; | |
1113 | return iter->desc->sptes[iter->pos]; | |
1114 | } | |
1115 | ||
1116 | /* | |
1117 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1118 | * | |
1119 | * Returns sptep if found, NULL otherwise. | |
1120 | */ | |
1121 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1122 | { | |
1123 | if (iter->desc) { | |
1124 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1125 | u64 *sptep; | |
1126 | ||
1127 | ++iter->pos; | |
1128 | sptep = iter->desc->sptes[iter->pos]; | |
1129 | if (sptep) | |
1130 | return sptep; | |
1131 | } | |
1132 | ||
1133 | iter->desc = iter->desc->more; | |
1134 | ||
1135 | if (iter->desc) { | |
1136 | iter->pos = 0; | |
1137 | /* desc->sptes[0] cannot be NULL */ | |
1138 | return iter->desc->sptes[iter->pos]; | |
1139 | } | |
1140 | } | |
1141 | ||
1142 | return NULL; | |
1143 | } | |
1144 | ||
c3707958 | 1145 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1146 | { |
1df9f2dc | 1147 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1148 | rmap_remove(kvm, sptep); |
be38d276 AK |
1149 | } |
1150 | ||
8e22f955 XG |
1151 | |
1152 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1153 | { | |
1154 | if (is_large_pte(*sptep)) { | |
1155 | WARN_ON(page_header(__pa(sptep))->role.level == | |
1156 | PT_PAGE_TABLE_LEVEL); | |
1157 | drop_spte(kvm, sptep); | |
1158 | --kvm->stat.lpages; | |
1159 | return true; | |
1160 | } | |
1161 | ||
1162 | return false; | |
1163 | } | |
1164 | ||
1165 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1166 | { | |
1167 | if (__drop_large_spte(vcpu->kvm, sptep)) | |
1168 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1169 | } | |
1170 | ||
1171 | /* | |
49fde340 | 1172 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
c126d94f | 1173 | * spte write-protection is caused by protecting shadow page table. |
49fde340 | 1174 | * |
b4619660 | 1175 | * Note: write protection is difference between dirty logging and spte |
49fde340 XG |
1176 | * protection: |
1177 | * - for dirty logging, the spte can be set to writable at anytime if | |
1178 | * its dirty bitmap is properly set. | |
1179 | * - for spte protection, the spte can be writable only after unsync-ing | |
1180 | * shadow page. | |
8e22f955 | 1181 | * |
c126d94f | 1182 | * Return true if tlb need be flushed. |
8e22f955 | 1183 | */ |
c126d94f | 1184 | static bool spte_write_protect(struct kvm *kvm, u64 *sptep, bool pt_protect) |
d13bc5b5 XG |
1185 | { |
1186 | u64 spte = *sptep; | |
1187 | ||
49fde340 XG |
1188 | if (!is_writable_pte(spte) && |
1189 | !(pt_protect && spte_is_locklessly_modifiable(spte))) | |
d13bc5b5 XG |
1190 | return false; |
1191 | ||
1192 | rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); | |
1193 | ||
49fde340 XG |
1194 | if (pt_protect) |
1195 | spte &= ~SPTE_MMU_WRITEABLE; | |
d13bc5b5 | 1196 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1197 | |
c126d94f | 1198 | return mmu_spte_update(sptep, spte); |
d13bc5b5 XG |
1199 | } |
1200 | ||
49fde340 | 1201 | static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp, |
245c3912 | 1202 | bool pt_protect) |
98348e95 | 1203 | { |
1e3f42f0 TY |
1204 | u64 *sptep; |
1205 | struct rmap_iterator iter; | |
d13bc5b5 | 1206 | bool flush = false; |
374cbac0 | 1207 | |
1e3f42f0 TY |
1208 | for (sptep = rmap_get_first(*rmapp, &iter); sptep;) { |
1209 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
a0ed4607 | 1210 | |
c126d94f | 1211 | flush |= spte_write_protect(kvm, sptep, pt_protect); |
d13bc5b5 | 1212 | sptep = rmap_get_next(&iter); |
374cbac0 | 1213 | } |
855149aa | 1214 | |
d13bc5b5 | 1215 | return flush; |
a0ed4607 TY |
1216 | } |
1217 | ||
f4b4b180 KH |
1218 | static bool spte_clear_dirty(struct kvm *kvm, u64 *sptep) |
1219 | { | |
1220 | u64 spte = *sptep; | |
1221 | ||
1222 | rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep); | |
1223 | ||
1224 | spte &= ~shadow_dirty_mask; | |
1225 | ||
1226 | return mmu_spte_update(sptep, spte); | |
1227 | } | |
1228 | ||
1229 | static bool __rmap_clear_dirty(struct kvm *kvm, unsigned long *rmapp) | |
1230 | { | |
1231 | u64 *sptep; | |
1232 | struct rmap_iterator iter; | |
1233 | bool flush = false; | |
1234 | ||
1235 | for (sptep = rmap_get_first(*rmapp, &iter); sptep;) { | |
1236 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
1237 | ||
1238 | flush |= spte_clear_dirty(kvm, sptep); | |
1239 | sptep = rmap_get_next(&iter); | |
1240 | } | |
1241 | ||
1242 | return flush; | |
1243 | } | |
1244 | ||
1245 | static bool spte_set_dirty(struct kvm *kvm, u64 *sptep) | |
1246 | { | |
1247 | u64 spte = *sptep; | |
1248 | ||
1249 | rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep); | |
1250 | ||
1251 | spte |= shadow_dirty_mask; | |
1252 | ||
1253 | return mmu_spte_update(sptep, spte); | |
1254 | } | |
1255 | ||
1256 | static bool __rmap_set_dirty(struct kvm *kvm, unsigned long *rmapp) | |
1257 | { | |
1258 | u64 *sptep; | |
1259 | struct rmap_iterator iter; | |
1260 | bool flush = false; | |
1261 | ||
1262 | for (sptep = rmap_get_first(*rmapp, &iter); sptep;) { | |
1263 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
1264 | ||
1265 | flush |= spte_set_dirty(kvm, sptep); | |
1266 | sptep = rmap_get_next(&iter); | |
1267 | } | |
1268 | ||
1269 | return flush; | |
1270 | } | |
1271 | ||
5dc99b23 | 1272 | /** |
3b0f1d01 | 1273 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages |
5dc99b23 TY |
1274 | * @kvm: kvm instance |
1275 | * @slot: slot to protect | |
1276 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1277 | * @mask: indicates which pages we should protect | |
1278 | * | |
1279 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1280 | * logging we do not have any such mappings. | |
1281 | */ | |
3b0f1d01 | 1282 | static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
5dc99b23 TY |
1283 | struct kvm_memory_slot *slot, |
1284 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 TY |
1285 | { |
1286 | unsigned long *rmapp; | |
a0ed4607 | 1287 | |
5dc99b23 | 1288 | while (mask) { |
65fbe37c TY |
1289 | rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1290 | PT_PAGE_TABLE_LEVEL, slot); | |
245c3912 | 1291 | __rmap_write_protect(kvm, rmapp, false); |
05da4558 | 1292 | |
5dc99b23 TY |
1293 | /* clear the first set bit */ |
1294 | mask &= mask - 1; | |
1295 | } | |
374cbac0 AK |
1296 | } |
1297 | ||
f4b4b180 KH |
1298 | /** |
1299 | * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages | |
1300 | * @kvm: kvm instance | |
1301 | * @slot: slot to clear D-bit | |
1302 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1303 | * @mask: indicates which pages we should clear D-bit | |
1304 | * | |
1305 | * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap. | |
1306 | */ | |
1307 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
1308 | struct kvm_memory_slot *slot, | |
1309 | gfn_t gfn_offset, unsigned long mask) | |
1310 | { | |
1311 | unsigned long *rmapp; | |
1312 | ||
1313 | while (mask) { | |
1314 | rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), | |
1315 | PT_PAGE_TABLE_LEVEL, slot); | |
1316 | __rmap_clear_dirty(kvm, rmapp); | |
1317 | ||
1318 | /* clear the first set bit */ | |
1319 | mask &= mask - 1; | |
1320 | } | |
1321 | } | |
1322 | EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked); | |
1323 | ||
3b0f1d01 KH |
1324 | /** |
1325 | * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected | |
1326 | * PT level pages. | |
1327 | * | |
1328 | * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to | |
1329 | * enable dirty logging for them. | |
1330 | * | |
1331 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1332 | * logging we do not have any such mappings. | |
1333 | */ | |
1334 | void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, | |
1335 | struct kvm_memory_slot *slot, | |
1336 | gfn_t gfn_offset, unsigned long mask) | |
1337 | { | |
88178fd4 KH |
1338 | if (kvm_x86_ops->enable_log_dirty_pt_masked) |
1339 | kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset, | |
1340 | mask); | |
1341 | else | |
1342 | kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); | |
3b0f1d01 KH |
1343 | } |
1344 | ||
2f84569f | 1345 | static bool rmap_write_protect(struct kvm *kvm, u64 gfn) |
95d4c16c TY |
1346 | { |
1347 | struct kvm_memory_slot *slot; | |
5dc99b23 TY |
1348 | unsigned long *rmapp; |
1349 | int i; | |
2f84569f | 1350 | bool write_protected = false; |
95d4c16c TY |
1351 | |
1352 | slot = gfn_to_memslot(kvm, gfn); | |
5dc99b23 TY |
1353 | |
1354 | for (i = PT_PAGE_TABLE_LEVEL; | |
1355 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
1356 | rmapp = __gfn_to_rmap(gfn, i, slot); | |
245c3912 | 1357 | write_protected |= __rmap_write_protect(kvm, rmapp, true); |
5dc99b23 TY |
1358 | } |
1359 | ||
1360 | return write_protected; | |
95d4c16c TY |
1361 | } |
1362 | ||
8a8365c5 | 1363 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
8a9522d2 ALC |
1364 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1365 | unsigned long data) | |
e930bffe | 1366 | { |
1e3f42f0 TY |
1367 | u64 *sptep; |
1368 | struct rmap_iterator iter; | |
e930bffe AA |
1369 | int need_tlb_flush = 0; |
1370 | ||
1e3f42f0 TY |
1371 | while ((sptep = rmap_get_first(*rmapp, &iter))) { |
1372 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
8a9522d2 ALC |
1373 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx gfn %llx (%d)\n", |
1374 | sptep, *sptep, gfn, level); | |
1e3f42f0 TY |
1375 | |
1376 | drop_spte(kvm, sptep); | |
e930bffe AA |
1377 | need_tlb_flush = 1; |
1378 | } | |
1e3f42f0 | 1379 | |
e930bffe AA |
1380 | return need_tlb_flush; |
1381 | } | |
1382 | ||
8a8365c5 | 1383 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
8a9522d2 ALC |
1384 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1385 | unsigned long data) | |
3da0dd43 | 1386 | { |
1e3f42f0 TY |
1387 | u64 *sptep; |
1388 | struct rmap_iterator iter; | |
3da0dd43 | 1389 | int need_flush = 0; |
1e3f42f0 | 1390 | u64 new_spte; |
3da0dd43 IE |
1391 | pte_t *ptep = (pte_t *)data; |
1392 | pfn_t new_pfn; | |
1393 | ||
1394 | WARN_ON(pte_huge(*ptep)); | |
1395 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 TY |
1396 | |
1397 | for (sptep = rmap_get_first(*rmapp, &iter); sptep;) { | |
1398 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
8a9522d2 ALC |
1399 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n", |
1400 | sptep, *sptep, gfn, level); | |
1e3f42f0 | 1401 | |
3da0dd43 | 1402 | need_flush = 1; |
1e3f42f0 | 1403 | |
3da0dd43 | 1404 | if (pte_write(*ptep)) { |
1e3f42f0 TY |
1405 | drop_spte(kvm, sptep); |
1406 | sptep = rmap_get_first(*rmapp, &iter); | |
3da0dd43 | 1407 | } else { |
1e3f42f0 | 1408 | new_spte = *sptep & ~PT64_BASE_ADDR_MASK; |
3da0dd43 IE |
1409 | new_spte |= (u64)new_pfn << PAGE_SHIFT; |
1410 | ||
1411 | new_spte &= ~PT_WRITABLE_MASK; | |
1412 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 1413 | new_spte &= ~shadow_accessed_mask; |
1e3f42f0 TY |
1414 | |
1415 | mmu_spte_clear_track_bits(sptep); | |
1416 | mmu_spte_set(sptep, new_spte); | |
1417 | sptep = rmap_get_next(&iter); | |
3da0dd43 IE |
1418 | } |
1419 | } | |
1e3f42f0 | 1420 | |
3da0dd43 IE |
1421 | if (need_flush) |
1422 | kvm_flush_remote_tlbs(kvm); | |
1423 | ||
1424 | return 0; | |
1425 | } | |
1426 | ||
84504ef3 TY |
1427 | static int kvm_handle_hva_range(struct kvm *kvm, |
1428 | unsigned long start, | |
1429 | unsigned long end, | |
1430 | unsigned long data, | |
1431 | int (*handler)(struct kvm *kvm, | |
1432 | unsigned long *rmapp, | |
048212d0 | 1433 | struct kvm_memory_slot *slot, |
8a9522d2 ALC |
1434 | gfn_t gfn, |
1435 | int level, | |
84504ef3 | 1436 | unsigned long data)) |
e930bffe | 1437 | { |
be6ba0f0 | 1438 | int j; |
f395302e | 1439 | int ret = 0; |
bc6678a3 | 1440 | struct kvm_memslots *slots; |
be6ba0f0 | 1441 | struct kvm_memory_slot *memslot; |
bc6678a3 | 1442 | |
90d83dc3 | 1443 | slots = kvm_memslots(kvm); |
e930bffe | 1444 | |
be6ba0f0 | 1445 | kvm_for_each_memslot(memslot, slots) { |
84504ef3 | 1446 | unsigned long hva_start, hva_end; |
bcd3ef58 | 1447 | gfn_t gfn_start, gfn_end; |
e930bffe | 1448 | |
84504ef3 TY |
1449 | hva_start = max(start, memslot->userspace_addr); |
1450 | hva_end = min(end, memslot->userspace_addr + | |
1451 | (memslot->npages << PAGE_SHIFT)); | |
1452 | if (hva_start >= hva_end) | |
1453 | continue; | |
1454 | /* | |
1455 | * {gfn(page) | page intersects with [hva_start, hva_end)} = | |
bcd3ef58 | 1456 | * {gfn_start, gfn_start+1, ..., gfn_end-1}. |
84504ef3 | 1457 | */ |
bcd3ef58 | 1458 | gfn_start = hva_to_gfn_memslot(hva_start, memslot); |
84504ef3 | 1459 | gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); |
852e3c19 | 1460 | |
bcd3ef58 TY |
1461 | for (j = PT_PAGE_TABLE_LEVEL; |
1462 | j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) { | |
1463 | unsigned long idx, idx_end; | |
1464 | unsigned long *rmapp; | |
8a9522d2 | 1465 | gfn_t gfn = gfn_start; |
d4dbf470 | 1466 | |
bcd3ef58 TY |
1467 | /* |
1468 | * {idx(page_j) | page_j intersects with | |
1469 | * [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}. | |
1470 | */ | |
1471 | idx = gfn_to_index(gfn_start, memslot->base_gfn, j); | |
1472 | idx_end = gfn_to_index(gfn_end - 1, memslot->base_gfn, j); | |
852e3c19 | 1473 | |
bcd3ef58 | 1474 | rmapp = __gfn_to_rmap(gfn_start, j, memslot); |
d4dbf470 | 1475 | |
8a9522d2 ALC |
1476 | for (; idx <= idx_end; |
1477 | ++idx, gfn += (1UL << KVM_HPAGE_GFN_SHIFT(j))) | |
1478 | ret |= handler(kvm, rmapp++, memslot, | |
1479 | gfn, j, data); | |
e930bffe AA |
1480 | } |
1481 | } | |
1482 | ||
f395302e | 1483 | return ret; |
e930bffe AA |
1484 | } |
1485 | ||
84504ef3 TY |
1486 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1487 | unsigned long data, | |
1488 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, | |
048212d0 | 1489 | struct kvm_memory_slot *slot, |
8a9522d2 | 1490 | gfn_t gfn, int level, |
84504ef3 TY |
1491 | unsigned long data)) |
1492 | { | |
1493 | return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler); | |
e930bffe AA |
1494 | } |
1495 | ||
1496 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
1497 | { | |
3da0dd43 IE |
1498 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
1499 | } | |
1500 | ||
b3ae2096 TY |
1501 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end) |
1502 | { | |
1503 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp); | |
1504 | } | |
1505 | ||
3da0dd43 IE |
1506 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
1507 | { | |
8a8365c5 | 1508 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1509 | } |
1510 | ||
8a8365c5 | 1511 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
8a9522d2 ALC |
1512 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1513 | unsigned long data) | |
e930bffe | 1514 | { |
1e3f42f0 | 1515 | u64 *sptep; |
79f702a6 | 1516 | struct rmap_iterator uninitialized_var(iter); |
e930bffe AA |
1517 | int young = 0; |
1518 | ||
57128468 | 1519 | BUG_ON(!shadow_accessed_mask); |
534e38b4 | 1520 | |
1e3f42f0 TY |
1521 | for (sptep = rmap_get_first(*rmapp, &iter); sptep; |
1522 | sptep = rmap_get_next(&iter)) { | |
3f6d8c8a | 1523 | BUG_ON(!is_shadow_present_pte(*sptep)); |
1e3f42f0 | 1524 | |
3f6d8c8a | 1525 | if (*sptep & shadow_accessed_mask) { |
e930bffe | 1526 | young = 1; |
3f6d8c8a XH |
1527 | clear_bit((ffs(shadow_accessed_mask) - 1), |
1528 | (unsigned long *)sptep); | |
e930bffe | 1529 | } |
e930bffe | 1530 | } |
8a9522d2 | 1531 | trace_kvm_age_page(gfn, level, slot, young); |
e930bffe AA |
1532 | return young; |
1533 | } | |
1534 | ||
8ee53820 | 1535 | static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
8a9522d2 ALC |
1536 | struct kvm_memory_slot *slot, gfn_t gfn, |
1537 | int level, unsigned long data) | |
8ee53820 | 1538 | { |
1e3f42f0 TY |
1539 | u64 *sptep; |
1540 | struct rmap_iterator iter; | |
8ee53820 AA |
1541 | int young = 0; |
1542 | ||
1543 | /* | |
1544 | * If there's no access bit in the secondary pte set by the | |
1545 | * hardware it's up to gup-fast/gup to set the access bit in | |
1546 | * the primary pte or in the page structure. | |
1547 | */ | |
1548 | if (!shadow_accessed_mask) | |
1549 | goto out; | |
1550 | ||
1e3f42f0 TY |
1551 | for (sptep = rmap_get_first(*rmapp, &iter); sptep; |
1552 | sptep = rmap_get_next(&iter)) { | |
3f6d8c8a | 1553 | BUG_ON(!is_shadow_present_pte(*sptep)); |
1e3f42f0 | 1554 | |
3f6d8c8a | 1555 | if (*sptep & shadow_accessed_mask) { |
8ee53820 AA |
1556 | young = 1; |
1557 | break; | |
1558 | } | |
8ee53820 AA |
1559 | } |
1560 | out: | |
1561 | return young; | |
1562 | } | |
1563 | ||
53a27b39 MT |
1564 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1565 | ||
852e3c19 | 1566 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
1567 | { |
1568 | unsigned long *rmapp; | |
852e3c19 JR |
1569 | struct kvm_mmu_page *sp; |
1570 | ||
1571 | sp = page_header(__pa(spte)); | |
53a27b39 | 1572 | |
852e3c19 | 1573 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 1574 | |
8a9522d2 | 1575 | kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, gfn, sp->role.level, 0); |
53a27b39 MT |
1576 | kvm_flush_remote_tlbs(vcpu->kvm); |
1577 | } | |
1578 | ||
57128468 | 1579 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end) |
e930bffe | 1580 | { |
57128468 ALC |
1581 | /* |
1582 | * In case of absence of EPT Access and Dirty Bits supports, | |
1583 | * emulate the accessed bit for EPT, by checking if this page has | |
1584 | * an EPT mapping, and clearing it if it does. On the next access, | |
1585 | * a new EPT mapping will be established. | |
1586 | * This has some overhead, but not as much as the cost of swapping | |
1587 | * out actively used pages or breaking up actively used hugepages. | |
1588 | */ | |
1589 | if (!shadow_accessed_mask) { | |
1590 | /* | |
1591 | * We are holding the kvm->mmu_lock, and we are blowing up | |
1592 | * shadow PTEs. MMU notifier consumers need to be kept at bay. | |
1593 | * This is correct as long as we don't decouple the mmu_lock | |
1594 | * protected regions (like invalidate_range_start|end does). | |
1595 | */ | |
1596 | kvm->mmu_notifier_seq++; | |
1597 | return kvm_handle_hva_range(kvm, start, end, 0, | |
1598 | kvm_unmap_rmapp); | |
1599 | } | |
1600 | ||
1601 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp); | |
e930bffe AA |
1602 | } |
1603 | ||
8ee53820 AA |
1604 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1605 | { | |
1606 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1607 | } | |
1608 | ||
d6c69ee9 | 1609 | #ifdef MMU_DEBUG |
47ad8e68 | 1610 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1611 | { |
139bdb2d AK |
1612 | u64 *pos; |
1613 | u64 *end; | |
1614 | ||
47ad8e68 | 1615 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1616 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1617 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1618 | pos, *pos); |
6aa8b732 | 1619 | return 0; |
139bdb2d | 1620 | } |
6aa8b732 AK |
1621 | return 1; |
1622 | } | |
d6c69ee9 | 1623 | #endif |
6aa8b732 | 1624 | |
45221ab6 DH |
1625 | /* |
1626 | * This value is the sum of all of the kvm instances's | |
1627 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1628 | * aggregate version in order to make the slab shrinker | |
1629 | * faster | |
1630 | */ | |
1631 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
1632 | { | |
1633 | kvm->arch.n_used_mmu_pages += nr; | |
1634 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1635 | } | |
1636 | ||
834be0d8 | 1637 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 1638 | { |
fa4a2c08 | 1639 | MMU_WARN_ON(!is_empty_shadow_page(sp->spt)); |
7775834a | 1640 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
1641 | list_del(&sp->link); |
1642 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
1643 | if (!sp->role.direct) |
1644 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 1645 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1646 | } |
1647 | ||
cea0f0e7 AK |
1648 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1649 | { | |
1ae0a13d | 1650 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
1651 | } |
1652 | ||
714b93da | 1653 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1654 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1655 | { |
cea0f0e7 AK |
1656 | if (!parent_pte) |
1657 | return; | |
cea0f0e7 | 1658 | |
67052b35 | 1659 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1660 | } |
1661 | ||
4db35314 | 1662 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1663 | u64 *parent_pte) |
1664 | { | |
67052b35 | 1665 | pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1666 | } |
1667 | ||
bcdd9a93 XG |
1668 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1669 | u64 *parent_pte) | |
1670 | { | |
1671 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1672 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1673 | } |
1674 | ||
67052b35 XG |
1675 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
1676 | u64 *parent_pte, int direct) | |
ad8cfbe3 | 1677 | { |
67052b35 | 1678 | struct kvm_mmu_page *sp; |
7ddca7e4 | 1679 | |
80feb89a TY |
1680 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
1681 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); | |
67052b35 | 1682 | if (!direct) |
80feb89a | 1683 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); |
67052b35 | 1684 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
5304b8d3 XG |
1685 | |
1686 | /* | |
1687 | * The active_mmu_pages list is the FIFO list, do not move the | |
1688 | * page until it is zapped. kvm_zap_obsolete_pages depends on | |
1689 | * this feature. See the comments in kvm_zap_obsolete_pages(). | |
1690 | */ | |
67052b35 | 1691 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
67052b35 XG |
1692 | sp->parent_ptes = 0; |
1693 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); | |
1694 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); | |
1695 | return sp; | |
ad8cfbe3 MT |
1696 | } |
1697 | ||
67052b35 | 1698 | static void mark_unsync(u64 *spte); |
1047df1f | 1699 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1700 | { |
67052b35 | 1701 | pte_list_walk(&sp->parent_ptes, mark_unsync); |
0074ff63 MT |
1702 | } |
1703 | ||
67052b35 | 1704 | static void mark_unsync(u64 *spte) |
0074ff63 | 1705 | { |
67052b35 | 1706 | struct kvm_mmu_page *sp; |
1047df1f | 1707 | unsigned int index; |
0074ff63 | 1708 | |
67052b35 | 1709 | sp = page_header(__pa(spte)); |
1047df1f XG |
1710 | index = spte - sp->spt; |
1711 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1712 | return; |
1047df1f | 1713 | if (sp->unsync_children++) |
0074ff63 | 1714 | return; |
1047df1f | 1715 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1716 | } |
1717 | ||
e8bc217a | 1718 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1719 | struct kvm_mmu_page *sp) |
e8bc217a MT |
1720 | { |
1721 | return 1; | |
1722 | } | |
1723 | ||
a7052897 MT |
1724 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1725 | { | |
1726 | } | |
1727 | ||
0f53b5b1 XG |
1728 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1729 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 1730 | const void *pte) |
0f53b5b1 XG |
1731 | { |
1732 | WARN_ON(1); | |
1733 | } | |
1734 | ||
60c8aec6 MT |
1735 | #define KVM_PAGE_ARRAY_NR 16 |
1736 | ||
1737 | struct kvm_mmu_pages { | |
1738 | struct mmu_page_and_offset { | |
1739 | struct kvm_mmu_page *sp; | |
1740 | unsigned int idx; | |
1741 | } page[KVM_PAGE_ARRAY_NR]; | |
1742 | unsigned int nr; | |
1743 | }; | |
1744 | ||
cded19f3 HE |
1745 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1746 | int idx) | |
4731d4c7 | 1747 | { |
60c8aec6 | 1748 | int i; |
4731d4c7 | 1749 | |
60c8aec6 MT |
1750 | if (sp->unsync) |
1751 | for (i=0; i < pvec->nr; i++) | |
1752 | if (pvec->page[i].sp == sp) | |
1753 | return 0; | |
1754 | ||
1755 | pvec->page[pvec->nr].sp = sp; | |
1756 | pvec->page[pvec->nr].idx = idx; | |
1757 | pvec->nr++; | |
1758 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1759 | } | |
1760 | ||
1761 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1762 | struct kvm_mmu_pages *pvec) | |
1763 | { | |
1764 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1765 | |
37178b8b | 1766 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 1767 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1768 | u64 ent = sp->spt[i]; |
1769 | ||
7a8f1a74 XG |
1770 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) |
1771 | goto clear_child_bitmap; | |
1772 | ||
1773 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1774 | ||
1775 | if (child->unsync_children) { | |
1776 | if (mmu_pages_add(pvec, child, i)) | |
1777 | return -ENOSPC; | |
1778 | ||
1779 | ret = __mmu_unsync_walk(child, pvec); | |
1780 | if (!ret) | |
1781 | goto clear_child_bitmap; | |
1782 | else if (ret > 0) | |
1783 | nr_unsync_leaf += ret; | |
1784 | else | |
1785 | return ret; | |
1786 | } else if (child->unsync) { | |
1787 | nr_unsync_leaf++; | |
1788 | if (mmu_pages_add(pvec, child, i)) | |
1789 | return -ENOSPC; | |
1790 | } else | |
1791 | goto clear_child_bitmap; | |
1792 | ||
1793 | continue; | |
1794 | ||
1795 | clear_child_bitmap: | |
1796 | __clear_bit(i, sp->unsync_child_bitmap); | |
1797 | sp->unsync_children--; | |
1798 | WARN_ON((int)sp->unsync_children < 0); | |
4731d4c7 MT |
1799 | } |
1800 | ||
4731d4c7 | 1801 | |
60c8aec6 MT |
1802 | return nr_unsync_leaf; |
1803 | } | |
1804 | ||
1805 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1806 | struct kvm_mmu_pages *pvec) | |
1807 | { | |
1808 | if (!sp->unsync_children) | |
1809 | return 0; | |
1810 | ||
1811 | mmu_pages_add(pvec, sp, 0); | |
1812 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1813 | } |
1814 | ||
4731d4c7 MT |
1815 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1816 | { | |
1817 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1818 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1819 | sp->unsync = 0; |
1820 | --kvm->stat.mmu_unsync; | |
1821 | } | |
1822 | ||
7775834a XG |
1823 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1824 | struct list_head *invalid_list); | |
1825 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1826 | struct list_head *invalid_list); | |
4731d4c7 | 1827 | |
f34d251d XG |
1828 | /* |
1829 | * NOTE: we should pay more attention on the zapped-obsolete page | |
1830 | * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk | |
1831 | * since it has been deleted from active_mmu_pages but still can be found | |
1832 | * at hast list. | |
1833 | * | |
1834 | * for_each_gfn_indirect_valid_sp has skipped that kind of page and | |
1835 | * kvm_mmu_get_page(), the only user of for_each_gfn_sp(), has skipped | |
1836 | * all the obsolete pages. | |
1837 | */ | |
1044b030 TY |
1838 | #define for_each_gfn_sp(_kvm, _sp, _gfn) \ |
1839 | hlist_for_each_entry(_sp, \ | |
1840 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \ | |
1841 | if ((_sp)->gfn != (_gfn)) {} else | |
1842 | ||
1843 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
1844 | for_each_gfn_sp(_kvm, _sp, _gfn) \ | |
1845 | if ((_sp)->role.direct || (_sp)->role.invalid) {} else | |
7ae680eb | 1846 | |
f918b443 | 1847 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1848 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1849 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1850 | { |
5b7e0102 | 1851 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1852 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1853 | return 1; |
1854 | } | |
1855 | ||
f918b443 | 1856 | if (clear_unsync) |
1d9dc7e0 | 1857 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1858 | |
a4a8e6f7 | 1859 | if (vcpu->arch.mmu.sync_page(vcpu, sp)) { |
d98ba053 | 1860 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1861 | return 1; |
1862 | } | |
1863 | ||
77c3913b | 1864 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
4731d4c7 MT |
1865 | return 0; |
1866 | } | |
1867 | ||
1d9dc7e0 XG |
1868 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1869 | struct kvm_mmu_page *sp) | |
1870 | { | |
d98ba053 | 1871 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1872 | int ret; |
1873 | ||
d98ba053 | 1874 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1875 | if (ret) |
d98ba053 XG |
1876 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1877 | ||
1d9dc7e0 XG |
1878 | return ret; |
1879 | } | |
1880 | ||
e37fa785 XG |
1881 | #ifdef CONFIG_KVM_MMU_AUDIT |
1882 | #include "mmu_audit.c" | |
1883 | #else | |
1884 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
1885 | static void mmu_audit_disable(void) { } | |
1886 | #endif | |
1887 | ||
d98ba053 XG |
1888 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1889 | struct list_head *invalid_list) | |
1d9dc7e0 | 1890 | { |
d98ba053 | 1891 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1892 | } |
1893 | ||
9f1a122f XG |
1894 | /* @gfn should be write-protected at the call site */ |
1895 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1896 | { | |
9f1a122f | 1897 | struct kvm_mmu_page *s; |
d98ba053 | 1898 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1899 | bool flush = false; |
1900 | ||
b67bfe0d | 1901 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 1902 | if (!s->unsync) |
9f1a122f XG |
1903 | continue; |
1904 | ||
1905 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
a4a8e6f7 | 1906 | kvm_unlink_unsync_page(vcpu->kvm, s); |
9f1a122f | 1907 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || |
a4a8e6f7 | 1908 | (vcpu->arch.mmu.sync_page(vcpu, s))) { |
d98ba053 | 1909 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1910 | continue; |
1911 | } | |
9f1a122f XG |
1912 | flush = true; |
1913 | } | |
1914 | ||
d98ba053 | 1915 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f | 1916 | if (flush) |
77c3913b | 1917 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
9f1a122f XG |
1918 | } |
1919 | ||
60c8aec6 MT |
1920 | struct mmu_page_path { |
1921 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1922 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1923 | }; |
1924 | ||
60c8aec6 MT |
1925 | #define for_each_sp(pvec, sp, parents, i) \ |
1926 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1927 | sp = pvec.page[i].sp; \ | |
1928 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1929 | i = mmu_pages_next(&pvec, &parents, i)) | |
1930 | ||
cded19f3 HE |
1931 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1932 | struct mmu_page_path *parents, | |
1933 | int i) | |
60c8aec6 MT |
1934 | { |
1935 | int n; | |
1936 | ||
1937 | for (n = i+1; n < pvec->nr; n++) { | |
1938 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1939 | ||
1940 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1941 | parents->idx[0] = pvec->page[n].idx; | |
1942 | return n; | |
1943 | } | |
1944 | ||
1945 | parents->parent[sp->role.level-2] = sp; | |
1946 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1947 | } | |
1948 | ||
1949 | return n; | |
1950 | } | |
1951 | ||
cded19f3 | 1952 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1953 | { |
60c8aec6 MT |
1954 | struct kvm_mmu_page *sp; |
1955 | unsigned int level = 0; | |
1956 | ||
1957 | do { | |
1958 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1959 | |
60c8aec6 MT |
1960 | sp = parents->parent[level]; |
1961 | if (!sp) | |
1962 | return; | |
1963 | ||
1964 | --sp->unsync_children; | |
1965 | WARN_ON((int)sp->unsync_children < 0); | |
1966 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1967 | level++; | |
1968 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1969 | } |
1970 | ||
60c8aec6 MT |
1971 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1972 | struct mmu_page_path *parents, | |
1973 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1974 | { |
60c8aec6 MT |
1975 | parents->parent[parent->role.level-1] = NULL; |
1976 | pvec->nr = 0; | |
1977 | } | |
4731d4c7 | 1978 | |
60c8aec6 MT |
1979 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1980 | struct kvm_mmu_page *parent) | |
1981 | { | |
1982 | int i; | |
1983 | struct kvm_mmu_page *sp; | |
1984 | struct mmu_page_path parents; | |
1985 | struct kvm_mmu_pages pages; | |
d98ba053 | 1986 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
1987 | |
1988 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1989 | while (mmu_unsync_walk(parent, &pages)) { | |
2f84569f | 1990 | bool protected = false; |
b1a36821 MT |
1991 | |
1992 | for_each_sp(pages, sp, parents, i) | |
1993 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1994 | ||
1995 | if (protected) | |
1996 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1997 | ||
60c8aec6 | 1998 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 1999 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
2000 | mmu_pages_clear_parents(&parents); |
2001 | } | |
d98ba053 | 2002 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 2003 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
2004 | kvm_mmu_pages_init(parent, &parents, &pages); |
2005 | } | |
4731d4c7 MT |
2006 | } |
2007 | ||
c3707958 XG |
2008 | static void init_shadow_page_table(struct kvm_mmu_page *sp) |
2009 | { | |
2010 | int i; | |
2011 | ||
2012 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
2013 | sp->spt[i] = 0ull; | |
2014 | } | |
2015 | ||
a30f47cb XG |
2016 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
2017 | { | |
2018 | sp->write_flooding_count = 0; | |
2019 | } | |
2020 | ||
2021 | static void clear_sp_write_flooding_count(u64 *spte) | |
2022 | { | |
2023 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
2024 | ||
2025 | __clear_sp_write_flooding_count(sp); | |
2026 | } | |
2027 | ||
5304b8d3 XG |
2028 | static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) |
2029 | { | |
2030 | return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); | |
2031 | } | |
2032 | ||
cea0f0e7 AK |
2033 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
2034 | gfn_t gfn, | |
2035 | gva_t gaddr, | |
2036 | unsigned level, | |
f6e2c02b | 2037 | int direct, |
41074d07 | 2038 | unsigned access, |
f7d9c7b7 | 2039 | u64 *parent_pte) |
cea0f0e7 AK |
2040 | { |
2041 | union kvm_mmu_page_role role; | |
cea0f0e7 | 2042 | unsigned quadrant; |
9f1a122f | 2043 | struct kvm_mmu_page *sp; |
9f1a122f | 2044 | bool need_sync = false; |
cea0f0e7 | 2045 | |
a770f6f2 | 2046 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 2047 | role.level = level; |
f6e2c02b | 2048 | role.direct = direct; |
84b0c8c6 | 2049 | if (role.direct) |
5b7e0102 | 2050 | role.cr4_pae = 0; |
41074d07 | 2051 | role.access = access; |
c5a78f2b JR |
2052 | if (!vcpu->arch.mmu.direct_map |
2053 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
2054 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
2055 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
2056 | role.quadrant = quadrant; | |
2057 | } | |
b67bfe0d | 2058 | for_each_gfn_sp(vcpu->kvm, sp, gfn) { |
7f52af74 XG |
2059 | if (is_obsolete_sp(vcpu->kvm, sp)) |
2060 | continue; | |
2061 | ||
7ae680eb XG |
2062 | if (!need_sync && sp->unsync) |
2063 | need_sync = true; | |
4731d4c7 | 2064 | |
7ae680eb XG |
2065 | if (sp->role.word != role.word) |
2066 | continue; | |
4731d4c7 | 2067 | |
7ae680eb XG |
2068 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
2069 | break; | |
e02aa901 | 2070 | |
7ae680eb XG |
2071 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
2072 | if (sp->unsync_children) { | |
a8eeb04a | 2073 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
7ae680eb XG |
2074 | kvm_mmu_mark_parents_unsync(sp); |
2075 | } else if (sp->unsync) | |
2076 | kvm_mmu_mark_parents_unsync(sp); | |
e02aa901 | 2077 | |
a30f47cb | 2078 | __clear_sp_write_flooding_count(sp); |
7ae680eb XG |
2079 | trace_kvm_mmu_get_page(sp, false); |
2080 | return sp; | |
2081 | } | |
dfc5aa00 | 2082 | ++vcpu->kvm->stat.mmu_cache_miss; |
2032a93d | 2083 | sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct); |
4db35314 AK |
2084 | if (!sp) |
2085 | return sp; | |
4db35314 AK |
2086 | sp->gfn = gfn; |
2087 | sp->role = role; | |
7ae680eb XG |
2088 | hlist_add_head(&sp->hash_link, |
2089 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 2090 | if (!direct) { |
b1a36821 MT |
2091 | if (rmap_write_protect(vcpu->kvm, gfn)) |
2092 | kvm_flush_remote_tlbs(vcpu->kvm); | |
9f1a122f XG |
2093 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
2094 | kvm_sync_pages(vcpu, gfn); | |
2095 | ||
4731d4c7 MT |
2096 | account_shadowed(vcpu->kvm, gfn); |
2097 | } | |
5304b8d3 | 2098 | sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen; |
c3707958 | 2099 | init_shadow_page_table(sp); |
f691fe1d | 2100 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 2101 | return sp; |
cea0f0e7 AK |
2102 | } |
2103 | ||
2d11123a AK |
2104 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
2105 | struct kvm_vcpu *vcpu, u64 addr) | |
2106 | { | |
2107 | iterator->addr = addr; | |
2108 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
2109 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 JR |
2110 | |
2111 | if (iterator->level == PT64_ROOT_LEVEL && | |
2112 | vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL && | |
2113 | !vcpu->arch.mmu.direct_map) | |
2114 | --iterator->level; | |
2115 | ||
2d11123a AK |
2116 | if (iterator->level == PT32E_ROOT_LEVEL) { |
2117 | iterator->shadow_addr | |
2118 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
2119 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
2120 | --iterator->level; | |
2121 | if (!iterator->shadow_addr) | |
2122 | iterator->level = 0; | |
2123 | } | |
2124 | } | |
2125 | ||
2126 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
2127 | { | |
2128 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
2129 | return false; | |
4d88954d | 2130 | |
2d11123a AK |
2131 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
2132 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
2133 | return true; | |
2134 | } | |
2135 | ||
c2a2ac2b XG |
2136 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
2137 | u64 spte) | |
2d11123a | 2138 | { |
c2a2ac2b | 2139 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
2140 | iterator->level = 0; |
2141 | return; | |
2142 | } | |
2143 | ||
c2a2ac2b | 2144 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
2145 | --iterator->level; |
2146 | } | |
2147 | ||
c2a2ac2b XG |
2148 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
2149 | { | |
2150 | return __shadow_walk_next(iterator, *iterator->sptep); | |
2151 | } | |
2152 | ||
7a1638ce | 2153 | static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp, bool accessed) |
32ef26a3 AK |
2154 | { |
2155 | u64 spte; | |
2156 | ||
7a1638ce YZ |
2157 | BUILD_BUG_ON(VMX_EPT_READABLE_MASK != PT_PRESENT_MASK || |
2158 | VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK); | |
2159 | ||
24db2734 | 2160 | spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
7a1638ce YZ |
2161 | shadow_user_mask | shadow_x_mask; |
2162 | ||
2163 | if (accessed) | |
2164 | spte |= shadow_accessed_mask; | |
24db2734 | 2165 | |
1df9f2dc | 2166 | mmu_spte_set(sptep, spte); |
32ef26a3 AK |
2167 | } |
2168 | ||
a357bd22 AK |
2169 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2170 | unsigned direct_access) | |
2171 | { | |
2172 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
2173 | struct kvm_mmu_page *child; | |
2174 | ||
2175 | /* | |
2176 | * For the direct sp, if the guest pte's dirty bit | |
2177 | * changed form clean to dirty, it will corrupt the | |
2178 | * sp's access: allow writable in the read-only sp, | |
2179 | * so we should update the spte at this point to get | |
2180 | * a new sp with the correct access. | |
2181 | */ | |
2182 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
2183 | if (child->role.access == direct_access) | |
2184 | return; | |
2185 | ||
bcdd9a93 | 2186 | drop_parent_pte(child, sptep); |
a357bd22 AK |
2187 | kvm_flush_remote_tlbs(vcpu->kvm); |
2188 | } | |
2189 | } | |
2190 | ||
505aef8f | 2191 | static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
38e3b2b2 XG |
2192 | u64 *spte) |
2193 | { | |
2194 | u64 pte; | |
2195 | struct kvm_mmu_page *child; | |
2196 | ||
2197 | pte = *spte; | |
2198 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2199 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2200 | drop_spte(kvm, spte); |
505aef8f XG |
2201 | if (is_large_pte(pte)) |
2202 | --kvm->stat.lpages; | |
2203 | } else { | |
38e3b2b2 | 2204 | child = page_header(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2205 | drop_parent_pte(child, spte); |
38e3b2b2 | 2206 | } |
505aef8f XG |
2207 | return true; |
2208 | } | |
2209 | ||
2210 | if (is_mmio_spte(pte)) | |
ce88decf | 2211 | mmu_spte_clear_no_track(spte); |
c3707958 | 2212 | |
505aef8f | 2213 | return false; |
38e3b2b2 XG |
2214 | } |
2215 | ||
90cb0529 | 2216 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 2217 | struct kvm_mmu_page *sp) |
a436036b | 2218 | { |
697fe2e2 | 2219 | unsigned i; |
697fe2e2 | 2220 | |
38e3b2b2 XG |
2221 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2222 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
2223 | } |
2224 | ||
4db35314 | 2225 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 2226 | { |
4db35314 | 2227 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
2228 | } |
2229 | ||
31aa2b44 | 2230 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2231 | { |
1e3f42f0 TY |
2232 | u64 *sptep; |
2233 | struct rmap_iterator iter; | |
a436036b | 2234 | |
1e3f42f0 TY |
2235 | while ((sptep = rmap_get_first(sp->parent_ptes, &iter))) |
2236 | drop_parent_pte(sp, sptep); | |
31aa2b44 AK |
2237 | } |
2238 | ||
60c8aec6 | 2239 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2240 | struct kvm_mmu_page *parent, |
2241 | struct list_head *invalid_list) | |
4731d4c7 | 2242 | { |
60c8aec6 MT |
2243 | int i, zapped = 0; |
2244 | struct mmu_page_path parents; | |
2245 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2246 | |
60c8aec6 | 2247 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2248 | return 0; |
60c8aec6 MT |
2249 | |
2250 | kvm_mmu_pages_init(parent, &parents, &pages); | |
2251 | while (mmu_unsync_walk(parent, &pages)) { | |
2252 | struct kvm_mmu_page *sp; | |
2253 | ||
2254 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2255 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2256 | mmu_pages_clear_parents(&parents); |
77662e00 | 2257 | zapped++; |
60c8aec6 | 2258 | } |
60c8aec6 MT |
2259 | kvm_mmu_pages_init(parent, &parents, &pages); |
2260 | } | |
2261 | ||
2262 | return zapped; | |
4731d4c7 MT |
2263 | } |
2264 | ||
7775834a XG |
2265 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2266 | struct list_head *invalid_list) | |
31aa2b44 | 2267 | { |
4731d4c7 | 2268 | int ret; |
f691fe1d | 2269 | |
7775834a | 2270 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2271 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 2272 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 2273 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 2274 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2275 | |
f6e2c02b | 2276 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 2277 | unaccount_shadowed(kvm, sp->gfn); |
5304b8d3 | 2278 | |
4731d4c7 MT |
2279 | if (sp->unsync) |
2280 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2281 | if (!sp->root_count) { |
54a4f023 GJ |
2282 | /* Count self */ |
2283 | ret++; | |
7775834a | 2284 | list_move(&sp->link, invalid_list); |
aa6bd187 | 2285 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2286 | } else { |
5b5c6a5a | 2287 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
05988d72 GN |
2288 | |
2289 | /* | |
2290 | * The obsolete pages can not be used on any vcpus. | |
2291 | * See the comments in kvm_mmu_invalidate_zap_all_pages(). | |
2292 | */ | |
2293 | if (!sp->role.invalid && !is_obsolete_sp(kvm, sp)) | |
2294 | kvm_reload_remote_mmus(kvm); | |
2e53d63a | 2295 | } |
7775834a XG |
2296 | |
2297 | sp->role.invalid = 1; | |
4731d4c7 | 2298 | return ret; |
a436036b AK |
2299 | } |
2300 | ||
7775834a XG |
2301 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2302 | struct list_head *invalid_list) | |
2303 | { | |
945315b9 | 2304 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2305 | |
2306 | if (list_empty(invalid_list)) | |
2307 | return; | |
2308 | ||
c142786c AK |
2309 | /* |
2310 | * wmb: make sure everyone sees our modifications to the page tables | |
2311 | * rmb: make sure we see changes to vcpu->mode | |
2312 | */ | |
2313 | smp_mb(); | |
4f022648 | 2314 | |
c142786c AK |
2315 | /* |
2316 | * Wait for all vcpus to exit guest mode and/or lockless shadow | |
2317 | * page table walks. | |
2318 | */ | |
2319 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2320 | |
945315b9 | 2321 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2322 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2323 | kvm_mmu_free_page(sp); |
945315b9 | 2324 | } |
7775834a XG |
2325 | } |
2326 | ||
5da59607 TY |
2327 | static bool prepare_zap_oldest_mmu_page(struct kvm *kvm, |
2328 | struct list_head *invalid_list) | |
2329 | { | |
2330 | struct kvm_mmu_page *sp; | |
2331 | ||
2332 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
2333 | return false; | |
2334 | ||
2335 | sp = list_entry(kvm->arch.active_mmu_pages.prev, | |
2336 | struct kvm_mmu_page, link); | |
2337 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); | |
2338 | ||
2339 | return true; | |
2340 | } | |
2341 | ||
82ce2c96 IE |
2342 | /* |
2343 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2344 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2345 | */ |
49d5ca26 | 2346 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 2347 | { |
d98ba053 | 2348 | LIST_HEAD(invalid_list); |
82ce2c96 | 2349 | |
b34cb590 TY |
2350 | spin_lock(&kvm->mmu_lock); |
2351 | ||
49d5ca26 | 2352 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
5da59607 TY |
2353 | /* Need to free some mmu pages to achieve the goal. */ |
2354 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) | |
2355 | if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list)) | |
2356 | break; | |
82ce2c96 | 2357 | |
aa6bd187 | 2358 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 2359 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2360 | } |
82ce2c96 | 2361 | |
49d5ca26 | 2362 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 TY |
2363 | |
2364 | spin_unlock(&kvm->mmu_lock); | |
82ce2c96 IE |
2365 | } |
2366 | ||
1cb3f3ae | 2367 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2368 | { |
4db35314 | 2369 | struct kvm_mmu_page *sp; |
d98ba053 | 2370 | LIST_HEAD(invalid_list); |
a436036b AK |
2371 | int r; |
2372 | ||
9ad17b10 | 2373 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2374 | r = 0; |
1cb3f3ae | 2375 | spin_lock(&kvm->mmu_lock); |
b67bfe0d | 2376 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2377 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2378 | sp->role.word); |
2379 | r = 1; | |
f41d335a | 2380 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2381 | } |
d98ba053 | 2382 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2383 | spin_unlock(&kvm->mmu_lock); |
2384 | ||
a436036b | 2385 | return r; |
cea0f0e7 | 2386 | } |
1cb3f3ae | 2387 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2388 | |
74be52e3 SY |
2389 | /* |
2390 | * The function is based on mtrr_type_lookup() in | |
2391 | * arch/x86/kernel/cpu/mtrr/generic.c | |
2392 | */ | |
2393 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
2394 | u64 start, u64 end) | |
2395 | { | |
2396 | int i; | |
2397 | u64 base, mask; | |
2398 | u8 prev_match, curr_match; | |
2399 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
2400 | ||
2401 | if (!mtrr_state->enabled) | |
2402 | return 0xFF; | |
2403 | ||
2404 | /* Make end inclusive end, instead of exclusive */ | |
2405 | end--; | |
2406 | ||
2407 | /* Look in fixed ranges. Just return the type as per start */ | |
2408 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
2409 | int idx; | |
2410 | ||
2411 | if (start < 0x80000) { | |
2412 | idx = 0; | |
2413 | idx += (start >> 16); | |
2414 | return mtrr_state->fixed_ranges[idx]; | |
2415 | } else if (start < 0xC0000) { | |
2416 | idx = 1 * 8; | |
2417 | idx += ((start - 0x80000) >> 14); | |
2418 | return mtrr_state->fixed_ranges[idx]; | |
2419 | } else if (start < 0x1000000) { | |
2420 | idx = 3 * 8; | |
2421 | idx += ((start - 0xC0000) >> 12); | |
2422 | return mtrr_state->fixed_ranges[idx]; | |
2423 | } | |
2424 | } | |
2425 | ||
2426 | /* | |
2427 | * Look in variable ranges | |
2428 | * Look of multiple ranges matching this address and pick type | |
2429 | * as per MTRR precedence | |
2430 | */ | |
2431 | if (!(mtrr_state->enabled & 2)) | |
2432 | return mtrr_state->def_type; | |
2433 | ||
2434 | prev_match = 0xFF; | |
2435 | for (i = 0; i < num_var_ranges; ++i) { | |
2436 | unsigned short start_state, end_state; | |
2437 | ||
2438 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
2439 | continue; | |
2440 | ||
2441 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
2442 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
2443 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
2444 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
2445 | ||
2446 | start_state = ((start & mask) == (base & mask)); | |
2447 | end_state = ((end & mask) == (base & mask)); | |
2448 | if (start_state != end_state) | |
2449 | return 0xFE; | |
2450 | ||
2451 | if ((start & mask) != (base & mask)) | |
2452 | continue; | |
2453 | ||
2454 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
2455 | if (prev_match == 0xFF) { | |
2456 | prev_match = curr_match; | |
2457 | continue; | |
2458 | } | |
2459 | ||
2460 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
2461 | curr_match == MTRR_TYPE_UNCACHABLE) | |
2462 | return MTRR_TYPE_UNCACHABLE; | |
2463 | ||
2464 | if ((prev_match == MTRR_TYPE_WRBACK && | |
2465 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
2466 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
2467 | curr_match == MTRR_TYPE_WRBACK)) { | |
2468 | prev_match = MTRR_TYPE_WRTHROUGH; | |
2469 | curr_match = MTRR_TYPE_WRTHROUGH; | |
2470 | } | |
2471 | ||
2472 | if (prev_match != curr_match) | |
2473 | return MTRR_TYPE_UNCACHABLE; | |
2474 | } | |
2475 | ||
2476 | if (prev_match != 0xFF) | |
2477 | return prev_match; | |
2478 | ||
2479 | return mtrr_state->def_type; | |
2480 | } | |
2481 | ||
4b12f0de | 2482 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
2483 | { |
2484 | u8 mtrr; | |
2485 | ||
2486 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
2487 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
2488 | if (mtrr == 0xfe || mtrr == 0xff) | |
2489 | mtrr = MTRR_TYPE_WRBACK; | |
2490 | return mtrr; | |
2491 | } | |
4b12f0de | 2492 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 2493 | |
9cf5cf5a XG |
2494 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
2495 | { | |
2496 | trace_kvm_mmu_unsync_page(sp); | |
2497 | ++vcpu->kvm->stat.mmu_unsync; | |
2498 | sp->unsync = 1; | |
2499 | ||
2500 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2501 | } |
2502 | ||
2503 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 2504 | { |
4731d4c7 | 2505 | struct kvm_mmu_page *s; |
9cf5cf5a | 2506 | |
b67bfe0d | 2507 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 2508 | if (s->unsync) |
4731d4c7 | 2509 | continue; |
9cf5cf5a XG |
2510 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
2511 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 2512 | } |
4731d4c7 MT |
2513 | } |
2514 | ||
2515 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
2516 | bool can_unsync) | |
2517 | { | |
9cf5cf5a | 2518 | struct kvm_mmu_page *s; |
9cf5cf5a XG |
2519 | bool need_unsync = false; |
2520 | ||
b67bfe0d | 2521 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
36a2e677 XG |
2522 | if (!can_unsync) |
2523 | return 1; | |
2524 | ||
9cf5cf5a | 2525 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2526 | return 1; |
9cf5cf5a | 2527 | |
9bb4f6b1 | 2528 | if (!s->unsync) |
9cf5cf5a | 2529 | need_unsync = true; |
4731d4c7 | 2530 | } |
9cf5cf5a XG |
2531 | if (need_unsync) |
2532 | kvm_unsync_pages(vcpu, gfn); | |
4731d4c7 MT |
2533 | return 0; |
2534 | } | |
2535 | ||
d555c333 | 2536 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
c2288505 | 2537 | unsigned pte_access, int level, |
c2d0ee46 | 2538 | gfn_t gfn, pfn_t pfn, bool speculative, |
9bdbba13 | 2539 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2540 | { |
6e7d0354 | 2541 | u64 spte; |
1e73f9dd | 2542 | int ret = 0; |
64d4d521 | 2543 | |
f2fd125d | 2544 | if (set_mmio_spte(vcpu->kvm, sptep, gfn, pfn, pte_access)) |
ce88decf XG |
2545 | return 0; |
2546 | ||
982c2565 | 2547 | spte = PT_PRESENT_MASK; |
947da538 | 2548 | if (!speculative) |
3201b5d9 | 2549 | spte |= shadow_accessed_mask; |
640d9b0d | 2550 | |
7b52345e SY |
2551 | if (pte_access & ACC_EXEC_MASK) |
2552 | spte |= shadow_x_mask; | |
2553 | else | |
2554 | spte |= shadow_nx_mask; | |
49fde340 | 2555 | |
1c4f1fd6 | 2556 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2557 | spte |= shadow_user_mask; |
49fde340 | 2558 | |
852e3c19 | 2559 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2560 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2561 | if (tdp_enabled) |
4b12f0de | 2562 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
bf4bea8e | 2563 | kvm_is_reserved_pfn(pfn)); |
1c4f1fd6 | 2564 | |
9bdbba13 | 2565 | if (host_writable) |
1403283a | 2566 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2567 | else |
2568 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2569 | |
35149e21 | 2570 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 | 2571 | |
c2288505 | 2572 | if (pte_access & ACC_WRITE_MASK) { |
1c4f1fd6 | 2573 | |
c2193463 | 2574 | /* |
7751babd XG |
2575 | * Other vcpu creates new sp in the window between |
2576 | * mapping_level() and acquiring mmu-lock. We can | |
2577 | * allow guest to retry the access, the mapping can | |
2578 | * be fixed if guest refault. | |
c2193463 | 2579 | */ |
852e3c19 | 2580 | if (level > PT_PAGE_TABLE_LEVEL && |
c2193463 | 2581 | has_wrprotected_page(vcpu->kvm, gfn, level)) |
be38d276 | 2582 | goto done; |
38187c83 | 2583 | |
49fde340 | 2584 | spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE; |
1c4f1fd6 | 2585 | |
ecc5589f MT |
2586 | /* |
2587 | * Optimization: for pte sync, if spte was writable the hash | |
2588 | * lookup is unnecessary (and expensive). Write protection | |
2589 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2590 | * Same reasoning can be applied to dirty page accounting. | |
2591 | */ | |
8dae4445 | 2592 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2593 | goto set_pte; |
2594 | ||
4731d4c7 | 2595 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2596 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2597 | __func__, gfn); |
1e73f9dd | 2598 | ret = 1; |
1c4f1fd6 | 2599 | pte_access &= ~ACC_WRITE_MASK; |
49fde340 | 2600 | spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE); |
1c4f1fd6 AK |
2601 | } |
2602 | } | |
2603 | ||
9b51a630 | 2604 | if (pte_access & ACC_WRITE_MASK) { |
1c4f1fd6 | 2605 | mark_page_dirty(vcpu->kvm, gfn); |
9b51a630 KH |
2606 | spte |= shadow_dirty_mask; |
2607 | } | |
1c4f1fd6 | 2608 | |
38187c83 | 2609 | set_pte: |
6e7d0354 | 2610 | if (mmu_spte_update(sptep, spte)) |
b330aa0c | 2611 | kvm_flush_remote_tlbs(vcpu->kvm); |
be38d276 | 2612 | done: |
1e73f9dd MT |
2613 | return ret; |
2614 | } | |
2615 | ||
d555c333 | 2616 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
f7616203 XG |
2617 | unsigned pte_access, int write_fault, int *emulate, |
2618 | int level, gfn_t gfn, pfn_t pfn, bool speculative, | |
2619 | bool host_writable) | |
1e73f9dd MT |
2620 | { |
2621 | int was_rmapped = 0; | |
53a27b39 | 2622 | int rmap_count; |
1e73f9dd | 2623 | |
f7616203 XG |
2624 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
2625 | *sptep, write_fault, gfn); | |
1e73f9dd | 2626 | |
d555c333 | 2627 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
2628 | /* |
2629 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2630 | * the parent of the now unreachable PTE. | |
2631 | */ | |
852e3c19 JR |
2632 | if (level > PT_PAGE_TABLE_LEVEL && |
2633 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2634 | struct kvm_mmu_page *child; |
d555c333 | 2635 | u64 pte = *sptep; |
1e73f9dd MT |
2636 | |
2637 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 2638 | drop_parent_pte(child, sptep); |
3be2264b | 2639 | kvm_flush_remote_tlbs(vcpu->kvm); |
d555c333 | 2640 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2641 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2642 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2643 | drop_spte(vcpu->kvm, sptep); |
91546356 | 2644 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2645 | } else |
2646 | was_rmapped = 1; | |
1e73f9dd | 2647 | } |
852e3c19 | 2648 | |
c2288505 XG |
2649 | if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative, |
2650 | true, host_writable)) { | |
1e73f9dd | 2651 | if (write_fault) |
b90a0e6c | 2652 | *emulate = 1; |
77c3913b | 2653 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
a378b4e6 | 2654 | } |
1e73f9dd | 2655 | |
ce88decf XG |
2656 | if (unlikely(is_mmio_spte(*sptep) && emulate)) |
2657 | *emulate = 1; | |
2658 | ||
d555c333 | 2659 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2660 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2661 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
2662 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
2663 | *sptep, sptep); | |
d555c333 | 2664 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2665 | ++vcpu->kvm->stat.lpages; |
2666 | ||
ffb61bb3 | 2667 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
2668 | if (!was_rmapped) { |
2669 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2670 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2671 | rmap_recycle(vcpu, sptep, gfn); | |
2672 | } | |
1c4f1fd6 | 2673 | } |
cb9aaa30 | 2674 | |
f3ac1a4b | 2675 | kvm_release_pfn_clean(pfn); |
1c4f1fd6 AK |
2676 | } |
2677 | ||
957ed9ef XG |
2678 | static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
2679 | bool no_dirty_log) | |
2680 | { | |
2681 | struct kvm_memory_slot *slot; | |
957ed9ef | 2682 | |
5d163b1c | 2683 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 2684 | if (!slot) |
6c8ee57b | 2685 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 2686 | |
037d92dc | 2687 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
2688 | } |
2689 | ||
2690 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2691 | struct kvm_mmu_page *sp, | |
2692 | u64 *start, u64 *end) | |
2693 | { | |
2694 | struct page *pages[PTE_PREFETCH_NUM]; | |
2695 | unsigned access = sp->role.access; | |
2696 | int i, ret; | |
2697 | gfn_t gfn; | |
2698 | ||
2699 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
5d163b1c | 2700 | if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK)) |
957ed9ef XG |
2701 | return -1; |
2702 | ||
2703 | ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start); | |
2704 | if (ret <= 0) | |
2705 | return -1; | |
2706 | ||
2707 | for (i = 0; i < ret; i++, gfn++, start++) | |
f7616203 | 2708 | mmu_set_spte(vcpu, start, access, 0, NULL, |
c2288505 XG |
2709 | sp->role.level, gfn, page_to_pfn(pages[i]), |
2710 | true, true); | |
957ed9ef XG |
2711 | |
2712 | return 0; | |
2713 | } | |
2714 | ||
2715 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2716 | struct kvm_mmu_page *sp, u64 *sptep) | |
2717 | { | |
2718 | u64 *spte, *start = NULL; | |
2719 | int i; | |
2720 | ||
2721 | WARN_ON(!sp->role.direct); | |
2722 | ||
2723 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2724 | spte = sp->spt + i; | |
2725 | ||
2726 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2727 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2728 | if (!start) |
2729 | continue; | |
2730 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2731 | break; | |
2732 | start = NULL; | |
2733 | } else if (!start) | |
2734 | start = spte; | |
2735 | } | |
2736 | } | |
2737 | ||
2738 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2739 | { | |
2740 | struct kvm_mmu_page *sp; | |
2741 | ||
2742 | /* | |
2743 | * Since it's no accessed bit on EPT, it's no way to | |
2744 | * distinguish between actually accessed translations | |
2745 | * and prefetched, so disable pte prefetch if EPT is | |
2746 | * enabled. | |
2747 | */ | |
2748 | if (!shadow_accessed_mask) | |
2749 | return; | |
2750 | ||
2751 | sp = page_header(__pa(sptep)); | |
2752 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2753 | return; | |
2754 | ||
2755 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2756 | } | |
2757 | ||
9f652d21 | 2758 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
2ec4739d XG |
2759 | int map_writable, int level, gfn_t gfn, pfn_t pfn, |
2760 | bool prefault) | |
140754bc | 2761 | { |
9f652d21 | 2762 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2763 | struct kvm_mmu_page *sp; |
b90a0e6c | 2764 | int emulate = 0; |
140754bc | 2765 | gfn_t pseudo_gfn; |
6aa8b732 | 2766 | |
989c6b34 MT |
2767 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2768 | return 0; | |
2769 | ||
9f652d21 | 2770 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2771 | if (iterator.level == level) { |
f7616203 | 2772 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, |
c2288505 XG |
2773 | write, &emulate, level, gfn, pfn, |
2774 | prefault, map_writable); | |
957ed9ef | 2775 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2776 | ++vcpu->stat.pf_fixed; |
2777 | break; | |
6aa8b732 AK |
2778 | } |
2779 | ||
404381c5 | 2780 | drop_large_spte(vcpu, iterator.sptep); |
c3707958 | 2781 | if (!is_shadow_present_pte(*iterator.sptep)) { |
c9fa0b3b LJ |
2782 | u64 base_addr = iterator.addr; |
2783 | ||
2784 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2785 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 AK |
2786 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
2787 | iterator.level - 1, | |
2788 | 1, ACC_ALL, iterator.sptep); | |
140754bc | 2789 | |
7a1638ce | 2790 | link_shadow_page(iterator.sptep, sp, true); |
9f652d21 AK |
2791 | } |
2792 | } | |
b90a0e6c | 2793 | return emulate; |
6aa8b732 AK |
2794 | } |
2795 | ||
77db5cbd | 2796 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2797 | { |
77db5cbd HY |
2798 | siginfo_t info; |
2799 | ||
2800 | info.si_signo = SIGBUS; | |
2801 | info.si_errno = 0; | |
2802 | info.si_code = BUS_MCEERR_AR; | |
2803 | info.si_addr = (void __user *)address; | |
2804 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 2805 | |
77db5cbd | 2806 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
2807 | } |
2808 | ||
d7c55201 | 2809 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn) |
bf998156 | 2810 | { |
4d8b81ab XG |
2811 | /* |
2812 | * Do not cache the mmio info caused by writing the readonly gfn | |
2813 | * into the spte otherwise read access on readonly gfn also can | |
2814 | * caused mmio page fault and treat it as mmio access. | |
2815 | * Return 1 to tell kvm to emulate it. | |
2816 | */ | |
2817 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
2818 | return 1; | |
2819 | ||
e6c1502b | 2820 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
bebb106a | 2821 | kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current); |
bf998156 | 2822 | return 0; |
d7c55201 | 2823 | } |
edba23e5 | 2824 | |
d7c55201 | 2825 | return -EFAULT; |
bf998156 HY |
2826 | } |
2827 | ||
936a5fe6 AA |
2828 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
2829 | gfn_t *gfnp, pfn_t *pfnp, int *levelp) | |
2830 | { | |
2831 | pfn_t pfn = *pfnp; | |
2832 | gfn_t gfn = *gfnp; | |
2833 | int level = *levelp; | |
2834 | ||
2835 | /* | |
2836 | * Check if it's a transparent hugepage. If this would be an | |
2837 | * hugetlbfs page, level wouldn't be set to | |
2838 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
2839 | * here. | |
2840 | */ | |
bf4bea8e | 2841 | if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) && |
936a5fe6 AA |
2842 | level == PT_PAGE_TABLE_LEVEL && |
2843 | PageTransCompound(pfn_to_page(pfn)) && | |
2844 | !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) { | |
2845 | unsigned long mask; | |
2846 | /* | |
2847 | * mmu_notifier_retry was successful and we hold the | |
2848 | * mmu_lock here, so the pmd can't become splitting | |
2849 | * from under us, and in turn | |
2850 | * __split_huge_page_refcount() can't run from under | |
2851 | * us and we can safely transfer the refcount from | |
2852 | * PG_tail to PG_head as we switch the pfn to tail to | |
2853 | * head. | |
2854 | */ | |
2855 | *levelp = level = PT_DIRECTORY_LEVEL; | |
2856 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
2857 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2858 | if (pfn & mask) { | |
2859 | gfn &= ~mask; | |
2860 | *gfnp = gfn; | |
2861 | kvm_release_pfn_clean(pfn); | |
2862 | pfn &= ~mask; | |
c3586667 | 2863 | kvm_get_pfn(pfn); |
936a5fe6 AA |
2864 | *pfnp = pfn; |
2865 | } | |
2866 | } | |
2867 | } | |
2868 | ||
d7c55201 XG |
2869 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
2870 | pfn_t pfn, unsigned access, int *ret_val) | |
2871 | { | |
2872 | bool ret = true; | |
2873 | ||
2874 | /* The pfn is invalid, report the error! */ | |
81c52c56 | 2875 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 XG |
2876 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
2877 | goto exit; | |
2878 | } | |
2879 | ||
ce88decf | 2880 | if (unlikely(is_noslot_pfn(pfn))) |
d7c55201 | 2881 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); |
d7c55201 XG |
2882 | |
2883 | ret = false; | |
2884 | exit: | |
2885 | return ret; | |
2886 | } | |
2887 | ||
e5552fd2 | 2888 | static bool page_fault_can_be_fast(u32 error_code) |
c7ba5b48 | 2889 | { |
1c118b82 XG |
2890 | /* |
2891 | * Do not fix the mmio spte with invalid generation number which | |
2892 | * need to be updated by slow page fault path. | |
2893 | */ | |
2894 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
2895 | return false; | |
2896 | ||
c7ba5b48 XG |
2897 | /* |
2898 | * #PF can be fast only if the shadow page table is present and it | |
2899 | * is caused by write-protect, that means we just need change the | |
2900 | * W bit of the spte which can be done out of mmu-lock. | |
2901 | */ | |
2902 | if (!(error_code & PFERR_PRESENT_MASK) || | |
2903 | !(error_code & PFERR_WRITE_MASK)) | |
2904 | return false; | |
2905 | ||
2906 | return true; | |
2907 | } | |
2908 | ||
2909 | static bool | |
92a476cb XG |
2910 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
2911 | u64 *sptep, u64 spte) | |
c7ba5b48 | 2912 | { |
c7ba5b48 XG |
2913 | gfn_t gfn; |
2914 | ||
2915 | WARN_ON(!sp->role.direct); | |
2916 | ||
2917 | /* | |
2918 | * The gfn of direct spte is stable since it is calculated | |
2919 | * by sp->gfn. | |
2920 | */ | |
2921 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
2922 | ||
9b51a630 KH |
2923 | /* |
2924 | * Theoretically we could also set dirty bit (and flush TLB) here in | |
2925 | * order to eliminate unnecessary PML logging. See comments in | |
2926 | * set_spte. But fast_page_fault is very unlikely to happen with PML | |
2927 | * enabled, so we do not do this. This might result in the same GPA | |
2928 | * to be logged in PML buffer again when the write really happens, and | |
2929 | * eventually to be called by mark_page_dirty twice. But it's also no | |
2930 | * harm. This also avoids the TLB flush needed after setting dirty bit | |
2931 | * so non-PML cases won't be impacted. | |
2932 | * | |
2933 | * Compare with set_spte where instead shadow_dirty_mask is set. | |
2934 | */ | |
c7ba5b48 XG |
2935 | if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte) |
2936 | mark_page_dirty(vcpu->kvm, gfn); | |
2937 | ||
2938 | return true; | |
2939 | } | |
2940 | ||
2941 | /* | |
2942 | * Return value: | |
2943 | * - true: let the vcpu to access on the same address again. | |
2944 | * - false: let the real page fault path to fix it. | |
2945 | */ | |
2946 | static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, | |
2947 | u32 error_code) | |
2948 | { | |
2949 | struct kvm_shadow_walk_iterator iterator; | |
92a476cb | 2950 | struct kvm_mmu_page *sp; |
c7ba5b48 XG |
2951 | bool ret = false; |
2952 | u64 spte = 0ull; | |
2953 | ||
37f6a4e2 MT |
2954 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2955 | return false; | |
2956 | ||
e5552fd2 | 2957 | if (!page_fault_can_be_fast(error_code)) |
c7ba5b48 XG |
2958 | return false; |
2959 | ||
2960 | walk_shadow_page_lockless_begin(vcpu); | |
2961 | for_each_shadow_entry_lockless(vcpu, gva, iterator, spte) | |
2962 | if (!is_shadow_present_pte(spte) || iterator.level < level) | |
2963 | break; | |
2964 | ||
2965 | /* | |
2966 | * If the mapping has been changed, let the vcpu fault on the | |
2967 | * same address again. | |
2968 | */ | |
2969 | if (!is_rmap_spte(spte)) { | |
2970 | ret = true; | |
2971 | goto exit; | |
2972 | } | |
2973 | ||
92a476cb XG |
2974 | sp = page_header(__pa(iterator.sptep)); |
2975 | if (!is_last_spte(spte, sp->role.level)) | |
c7ba5b48 XG |
2976 | goto exit; |
2977 | ||
2978 | /* | |
2979 | * Check if it is a spurious fault caused by TLB lazily flushed. | |
2980 | * | |
2981 | * Need not check the access of upper level table entries since | |
2982 | * they are always ACC_ALL. | |
2983 | */ | |
2984 | if (is_writable_pte(spte)) { | |
2985 | ret = true; | |
2986 | goto exit; | |
2987 | } | |
2988 | ||
2989 | /* | |
2990 | * Currently, to simplify the code, only the spte write-protected | |
2991 | * by dirty-log can be fast fixed. | |
2992 | */ | |
2993 | if (!spte_is_locklessly_modifiable(spte)) | |
2994 | goto exit; | |
2995 | ||
c126d94f XG |
2996 | /* |
2997 | * Do not fix write-permission on the large spte since we only dirty | |
2998 | * the first page into the dirty-bitmap in fast_pf_fix_direct_spte() | |
2999 | * that means other pages are missed if its slot is dirty-logged. | |
3000 | * | |
3001 | * Instead, we let the slow page fault path create a normal spte to | |
3002 | * fix the access. | |
3003 | * | |
3004 | * See the comments in kvm_arch_commit_memory_region(). | |
3005 | */ | |
3006 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
3007 | goto exit; | |
3008 | ||
c7ba5b48 XG |
3009 | /* |
3010 | * Currently, fast page fault only works for direct mapping since | |
3011 | * the gfn is not stable for indirect shadow page. | |
3012 | * See Documentation/virtual/kvm/locking.txt to get more detail. | |
3013 | */ | |
92a476cb | 3014 | ret = fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte); |
c7ba5b48 | 3015 | exit: |
a72faf25 XG |
3016 | trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep, |
3017 | spte, ret); | |
c7ba5b48 XG |
3018 | walk_shadow_page_lockless_end(vcpu); |
3019 | ||
3020 | return ret; | |
3021 | } | |
3022 | ||
78b2c54a | 3023 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
060c2abe | 3024 | gva_t gva, pfn_t *pfn, bool write, bool *writable); |
450e0b41 | 3025 | static void make_mmu_pages_available(struct kvm_vcpu *vcpu); |
060c2abe | 3026 | |
c7ba5b48 XG |
3027 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code, |
3028 | gfn_t gfn, bool prefault) | |
10589a46 MT |
3029 | { |
3030 | int r; | |
852e3c19 | 3031 | int level; |
936a5fe6 | 3032 | int force_pt_level; |
35149e21 | 3033 | pfn_t pfn; |
e930bffe | 3034 | unsigned long mmu_seq; |
c7ba5b48 | 3035 | bool map_writable, write = error_code & PFERR_WRITE_MASK; |
aaee2c94 | 3036 | |
936a5fe6 AA |
3037 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
3038 | if (likely(!force_pt_level)) { | |
3039 | level = mapping_level(vcpu, gfn); | |
3040 | /* | |
3041 | * This path builds a PAE pagetable - so we can map | |
3042 | * 2mb pages at maximum. Therefore check if the level | |
3043 | * is larger than that. | |
3044 | */ | |
3045 | if (level > PT_DIRECTORY_LEVEL) | |
3046 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 3047 | |
936a5fe6 AA |
3048 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
3049 | } else | |
3050 | level = PT_PAGE_TABLE_LEVEL; | |
05da4558 | 3051 | |
c7ba5b48 XG |
3052 | if (fast_page_fault(vcpu, v, level, error_code)) |
3053 | return 0; | |
3054 | ||
e930bffe | 3055 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3056 | smp_rmb(); |
060c2abe | 3057 | |
78b2c54a | 3058 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
060c2abe | 3059 | return 0; |
aaee2c94 | 3060 | |
d7c55201 XG |
3061 | if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r)) |
3062 | return r; | |
d196e343 | 3063 | |
aaee2c94 | 3064 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3065 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3066 | goto out_unlock; |
450e0b41 | 3067 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
3068 | if (likely(!force_pt_level)) |
3069 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
2ec4739d XG |
3070 | r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn, |
3071 | prefault); | |
aaee2c94 MT |
3072 | spin_unlock(&vcpu->kvm->mmu_lock); |
3073 | ||
aaee2c94 | 3074 | |
10589a46 | 3075 | return r; |
e930bffe AA |
3076 | |
3077 | out_unlock: | |
3078 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3079 | kvm_release_pfn_clean(pfn); | |
3080 | return 0; | |
10589a46 MT |
3081 | } |
3082 | ||
3083 | ||
17ac10ad AK |
3084 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
3085 | { | |
3086 | int i; | |
4db35314 | 3087 | struct kvm_mmu_page *sp; |
d98ba053 | 3088 | LIST_HEAD(invalid_list); |
17ac10ad | 3089 | |
ad312c7c | 3090 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 3091 | return; |
35af577a | 3092 | |
81407ca5 JR |
3093 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL && |
3094 | (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL || | |
3095 | vcpu->arch.mmu.direct_map)) { | |
ad312c7c | 3096 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 3097 | |
35af577a | 3098 | spin_lock(&vcpu->kvm->mmu_lock); |
4db35314 AK |
3099 | sp = page_header(root); |
3100 | --sp->root_count; | |
d98ba053 XG |
3101 | if (!sp->root_count && sp->role.invalid) { |
3102 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
3103 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
3104 | } | |
aaee2c94 | 3105 | spin_unlock(&vcpu->kvm->mmu_lock); |
35af577a | 3106 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
3107 | return; |
3108 | } | |
35af577a GN |
3109 | |
3110 | spin_lock(&vcpu->kvm->mmu_lock); | |
17ac10ad | 3111 | for (i = 0; i < 4; ++i) { |
ad312c7c | 3112 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 3113 | |
417726a3 | 3114 | if (root) { |
417726a3 | 3115 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
3116 | sp = page_header(root); |
3117 | --sp->root_count; | |
2e53d63a | 3118 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
3119 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
3120 | &invalid_list); | |
417726a3 | 3121 | } |
ad312c7c | 3122 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 3123 | } |
d98ba053 | 3124 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 3125 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 3126 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
3127 | } |
3128 | ||
8986ecc0 MT |
3129 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
3130 | { | |
3131 | int ret = 0; | |
3132 | ||
3133 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 3134 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
3135 | ret = 1; |
3136 | } | |
3137 | ||
3138 | return ret; | |
3139 | } | |
3140 | ||
651dd37a JR |
3141 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
3142 | { | |
3143 | struct kvm_mmu_page *sp; | |
7ebaf15e | 3144 | unsigned i; |
651dd37a JR |
3145 | |
3146 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3147 | spin_lock(&vcpu->kvm->mmu_lock); | |
450e0b41 | 3148 | make_mmu_pages_available(vcpu); |
651dd37a JR |
3149 | sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, |
3150 | 1, ACC_ALL, NULL); | |
3151 | ++sp->root_count; | |
3152 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3153 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
3154 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
3155 | for (i = 0; i < 4; ++i) { | |
3156 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3157 | ||
fa4a2c08 | 3158 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3159 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3160 | make_mmu_pages_available(vcpu); |
649497d1 AK |
3161 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
3162 | i << 30, | |
651dd37a JR |
3163 | PT32_ROOT_LEVEL, 1, ACC_ALL, |
3164 | NULL); | |
3165 | root = __pa(sp->spt); | |
3166 | ++sp->root_count; | |
3167 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3168 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 3169 | } |
6292757f | 3170 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
3171 | } else |
3172 | BUG(); | |
3173 | ||
3174 | return 0; | |
3175 | } | |
3176 | ||
3177 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 3178 | { |
4db35314 | 3179 | struct kvm_mmu_page *sp; |
81407ca5 JR |
3180 | u64 pdptr, pm_mask; |
3181 | gfn_t root_gfn; | |
3182 | int i; | |
3bb65a22 | 3183 | |
5777ed34 | 3184 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 3185 | |
651dd37a JR |
3186 | if (mmu_check_root(vcpu, root_gfn)) |
3187 | return 1; | |
3188 | ||
3189 | /* | |
3190 | * Do we shadow a long mode page table? If so we need to | |
3191 | * write-protect the guests page table root. | |
3192 | */ | |
3193 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { | |
ad312c7c | 3194 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 3195 | |
fa4a2c08 | 3196 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3197 | |
8facbbff | 3198 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3199 | make_mmu_pages_available(vcpu); |
651dd37a JR |
3200 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, |
3201 | 0, ACC_ALL, NULL); | |
4db35314 AK |
3202 | root = __pa(sp->spt); |
3203 | ++sp->root_count; | |
8facbbff | 3204 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 3205 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 3206 | return 0; |
17ac10ad | 3207 | } |
f87f9288 | 3208 | |
651dd37a JR |
3209 | /* |
3210 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3211 | * or a PAE 3-level page table. In either case we need to be aware that |
3212 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3213 | */ |
81407ca5 JR |
3214 | pm_mask = PT_PRESENT_MASK; |
3215 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) | |
3216 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; | |
3217 | ||
17ac10ad | 3218 | for (i = 0; i < 4; ++i) { |
ad312c7c | 3219 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 3220 | |
fa4a2c08 | 3221 | MMU_WARN_ON(VALID_PAGE(root)); |
ad312c7c | 3222 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 3223 | pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i); |
43a3795a | 3224 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 3225 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
3226 | continue; |
3227 | } | |
6de4f3ad | 3228 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
3229 | if (mmu_check_root(vcpu, root_gfn)) |
3230 | return 1; | |
5a7388c2 | 3231 | } |
8facbbff | 3232 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3233 | make_mmu_pages_available(vcpu); |
4db35314 | 3234 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
651dd37a | 3235 | PT32_ROOT_LEVEL, 0, |
f7d9c7b7 | 3236 | ACC_ALL, NULL); |
4db35314 AK |
3237 | root = __pa(sp->spt); |
3238 | ++sp->root_count; | |
8facbbff AK |
3239 | spin_unlock(&vcpu->kvm->mmu_lock); |
3240 | ||
81407ca5 | 3241 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 3242 | } |
6292757f | 3243 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3244 | |
3245 | /* | |
3246 | * If we shadow a 32 bit page table with a long mode page | |
3247 | * table we enter this path. | |
3248 | */ | |
3249 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3250 | if (vcpu->arch.mmu.lm_root == NULL) { | |
3251 | /* | |
3252 | * The additional page necessary for this is only | |
3253 | * allocated on demand. | |
3254 | */ | |
3255 | ||
3256 | u64 *lm_root; | |
3257 | ||
3258 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
3259 | if (lm_root == NULL) | |
3260 | return 1; | |
3261 | ||
3262 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
3263 | ||
3264 | vcpu->arch.mmu.lm_root = lm_root; | |
3265 | } | |
3266 | ||
3267 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
3268 | } | |
3269 | ||
8986ecc0 | 3270 | return 0; |
17ac10ad AK |
3271 | } |
3272 | ||
651dd37a JR |
3273 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
3274 | { | |
3275 | if (vcpu->arch.mmu.direct_map) | |
3276 | return mmu_alloc_direct_roots(vcpu); | |
3277 | else | |
3278 | return mmu_alloc_shadow_roots(vcpu); | |
3279 | } | |
3280 | ||
0ba73cda MT |
3281 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
3282 | { | |
3283 | int i; | |
3284 | struct kvm_mmu_page *sp; | |
3285 | ||
81407ca5 JR |
3286 | if (vcpu->arch.mmu.direct_map) |
3287 | return; | |
3288 | ||
0ba73cda MT |
3289 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3290 | return; | |
6903074c | 3291 | |
56f17dd3 | 3292 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); |
0375f7fa | 3293 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
81407ca5 | 3294 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { |
0ba73cda MT |
3295 | hpa_t root = vcpu->arch.mmu.root_hpa; |
3296 | sp = page_header(root); | |
3297 | mmu_sync_children(vcpu, sp); | |
0375f7fa | 3298 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3299 | return; |
3300 | } | |
3301 | for (i = 0; i < 4; ++i) { | |
3302 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3303 | ||
8986ecc0 | 3304 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
3305 | root &= PT64_BASE_ADDR_MASK; |
3306 | sp = page_header(root); | |
3307 | mmu_sync_children(vcpu, sp); | |
3308 | } | |
3309 | } | |
0375f7fa | 3310 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3311 | } |
3312 | ||
3313 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
3314 | { | |
3315 | spin_lock(&vcpu->kvm->mmu_lock); | |
3316 | mmu_sync_roots(vcpu); | |
6cffe8ca | 3317 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3318 | } |
bfd0a56b | 3319 | EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots); |
0ba73cda | 3320 | |
1871c602 | 3321 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 3322 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3323 | { |
ab9ae313 AK |
3324 | if (exception) |
3325 | exception->error_code = 0; | |
6aa8b732 AK |
3326 | return vaddr; |
3327 | } | |
3328 | ||
6539e738 | 3329 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
3330 | u32 access, |
3331 | struct x86_exception *exception) | |
6539e738 | 3332 | { |
ab9ae313 AK |
3333 | if (exception) |
3334 | exception->error_code = 0; | |
54987b7a | 3335 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception); |
6539e738 JR |
3336 | } |
3337 | ||
ce88decf XG |
3338 | static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
3339 | { | |
3340 | if (direct) | |
3341 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3342 | ||
3343 | return vcpu_match_mmio_gva(vcpu, addr); | |
3344 | } | |
3345 | ||
3346 | ||
3347 | /* | |
3348 | * On direct hosts, the last spte is only allows two states | |
3349 | * for mmio page fault: | |
3350 | * - It is the mmio spte | |
3351 | * - It is zapped or it is being zapped. | |
3352 | * | |
3353 | * This function completely checks the spte when the last spte | |
3354 | * is not the mmio spte. | |
3355 | */ | |
3356 | static bool check_direct_spte_mmio_pf(u64 spte) | |
3357 | { | |
3358 | return __check_direct_spte_mmio_pf(spte); | |
3359 | } | |
3360 | ||
3361 | static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr) | |
3362 | { | |
3363 | struct kvm_shadow_walk_iterator iterator; | |
3364 | u64 spte = 0ull; | |
3365 | ||
37f6a4e2 MT |
3366 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3367 | return spte; | |
3368 | ||
ce88decf XG |
3369 | walk_shadow_page_lockless_begin(vcpu); |
3370 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) | |
3371 | if (!is_shadow_present_pte(spte)) | |
3372 | break; | |
3373 | walk_shadow_page_lockless_end(vcpu); | |
3374 | ||
3375 | return spte; | |
3376 | } | |
3377 | ||
ce88decf XG |
3378 | int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
3379 | { | |
3380 | u64 spte; | |
3381 | ||
3382 | if (quickly_check_mmio_pf(vcpu, addr, direct)) | |
b37fbea6 | 3383 | return RET_MMIO_PF_EMULATE; |
ce88decf XG |
3384 | |
3385 | spte = walk_shadow_page_get_mmio_spte(vcpu, addr); | |
3386 | ||
3387 | if (is_mmio_spte(spte)) { | |
3388 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
3389 | unsigned access = get_mmio_spte_access(spte); | |
3390 | ||
f8f55942 XG |
3391 | if (!check_mmio_spte(vcpu->kvm, spte)) |
3392 | return RET_MMIO_PF_INVALID; | |
3393 | ||
ce88decf XG |
3394 | if (direct) |
3395 | addr = 0; | |
4f022648 XG |
3396 | |
3397 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf | 3398 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
b37fbea6 | 3399 | return RET_MMIO_PF_EMULATE; |
ce88decf XG |
3400 | } |
3401 | ||
3402 | /* | |
3403 | * It's ok if the gva is remapped by other cpus on shadow guest, | |
3404 | * it's a BUG if the gfn is not a mmio page. | |
3405 | */ | |
3406 | if (direct && !check_direct_spte_mmio_pf(spte)) | |
b37fbea6 | 3407 | return RET_MMIO_PF_BUG; |
ce88decf XG |
3408 | |
3409 | /* | |
3410 | * If the page table is zapped by other cpus, let CPU fault again on | |
3411 | * the address. | |
3412 | */ | |
b37fbea6 | 3413 | return RET_MMIO_PF_RETRY; |
ce88decf XG |
3414 | } |
3415 | EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common); | |
3416 | ||
3417 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, | |
3418 | u32 error_code, bool direct) | |
3419 | { | |
3420 | int ret; | |
3421 | ||
3422 | ret = handle_mmio_page_fault_common(vcpu, addr, direct); | |
b37fbea6 | 3423 | WARN_ON(ret == RET_MMIO_PF_BUG); |
ce88decf XG |
3424 | return ret; |
3425 | } | |
3426 | ||
6aa8b732 | 3427 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 3428 | u32 error_code, bool prefault) |
6aa8b732 | 3429 | { |
e833240f | 3430 | gfn_t gfn; |
e2dec939 | 3431 | int r; |
6aa8b732 | 3432 | |
b8688d51 | 3433 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
ce88decf | 3434 | |
f8f55942 XG |
3435 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
3436 | r = handle_mmio_page_fault(vcpu, gva, error_code, true); | |
3437 | ||
3438 | if (likely(r != RET_MMIO_PF_INVALID)) | |
3439 | return r; | |
3440 | } | |
ce88decf | 3441 | |
e2dec939 AK |
3442 | r = mmu_topup_memory_caches(vcpu); |
3443 | if (r) | |
3444 | return r; | |
714b93da | 3445 | |
fa4a2c08 | 3446 | MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3447 | |
e833240f | 3448 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 3449 | |
e833240f | 3450 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
c7ba5b48 | 3451 | error_code, gfn, prefault); |
6aa8b732 AK |
3452 | } |
3453 | ||
7e1fbeac | 3454 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
3455 | { |
3456 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3457 | |
7c90705b | 3458 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3459 | arch.gfn = gfn; |
c4806acd | 3460 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 3461 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 | 3462 | |
e0ead41a | 3463 | return kvm_setup_async_pf(vcpu, gva, gfn_to_hva(vcpu->kvm, gfn), &arch); |
af585b92 GN |
3464 | } |
3465 | ||
3466 | static bool can_do_async_pf(struct kvm_vcpu *vcpu) | |
3467 | { | |
3468 | if (unlikely(!irqchip_in_kernel(vcpu->kvm) || | |
3469 | kvm_event_needs_reinjection(vcpu))) | |
3470 | return false; | |
3471 | ||
3472 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
3473 | } | |
3474 | ||
78b2c54a | 3475 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
612819c3 | 3476 | gva_t gva, pfn_t *pfn, bool write, bool *writable) |
af585b92 GN |
3477 | { |
3478 | bool async; | |
3479 | ||
612819c3 | 3480 | *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable); |
af585b92 GN |
3481 | |
3482 | if (!async) | |
3483 | return false; /* *pfn has correct page already */ | |
3484 | ||
78b2c54a | 3485 | if (!prefault && can_do_async_pf(vcpu)) { |
c9b263d2 | 3486 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
3487 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
3488 | trace_kvm_async_pf_doublefault(gva, gfn); | |
3489 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
3490 | return true; | |
3491 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
3492 | return true; | |
3493 | } | |
3494 | ||
612819c3 | 3495 | *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable); |
af585b92 GN |
3496 | |
3497 | return false; | |
3498 | } | |
3499 | ||
56028d08 | 3500 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 3501 | bool prefault) |
fb72d167 | 3502 | { |
35149e21 | 3503 | pfn_t pfn; |
fb72d167 | 3504 | int r; |
852e3c19 | 3505 | int level; |
936a5fe6 | 3506 | int force_pt_level; |
05da4558 | 3507 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 3508 | unsigned long mmu_seq; |
612819c3 MT |
3509 | int write = error_code & PFERR_WRITE_MASK; |
3510 | bool map_writable; | |
fb72d167 | 3511 | |
fa4a2c08 | 3512 | MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
fb72d167 | 3513 | |
f8f55942 XG |
3514 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
3515 | r = handle_mmio_page_fault(vcpu, gpa, error_code, true); | |
3516 | ||
3517 | if (likely(r != RET_MMIO_PF_INVALID)) | |
3518 | return r; | |
3519 | } | |
ce88decf | 3520 | |
fb72d167 JR |
3521 | r = mmu_topup_memory_caches(vcpu); |
3522 | if (r) | |
3523 | return r; | |
3524 | ||
936a5fe6 AA |
3525 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
3526 | if (likely(!force_pt_level)) { | |
3527 | level = mapping_level(vcpu, gfn); | |
3528 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
3529 | } else | |
3530 | level = PT_PAGE_TABLE_LEVEL; | |
852e3c19 | 3531 | |
c7ba5b48 XG |
3532 | if (fast_page_fault(vcpu, gpa, level, error_code)) |
3533 | return 0; | |
3534 | ||
e930bffe | 3535 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3536 | smp_rmb(); |
af585b92 | 3537 | |
78b2c54a | 3538 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
af585b92 GN |
3539 | return 0; |
3540 | ||
d7c55201 XG |
3541 | if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r)) |
3542 | return r; | |
3543 | ||
fb72d167 | 3544 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3545 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3546 | goto out_unlock; |
450e0b41 | 3547 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
3548 | if (likely(!force_pt_level)) |
3549 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
612819c3 | 3550 | r = __direct_map(vcpu, gpa, write, map_writable, |
2ec4739d | 3551 | level, gfn, pfn, prefault); |
fb72d167 | 3552 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
3553 | |
3554 | return r; | |
e930bffe AA |
3555 | |
3556 | out_unlock: | |
3557 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3558 | kvm_release_pfn_clean(pfn); | |
3559 | return 0; | |
fb72d167 JR |
3560 | } |
3561 | ||
8a3c1a33 PB |
3562 | static void nonpaging_init_context(struct kvm_vcpu *vcpu, |
3563 | struct kvm_mmu *context) | |
6aa8b732 | 3564 | { |
6aa8b732 | 3565 | context->page_fault = nonpaging_page_fault; |
6aa8b732 | 3566 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
e8bc217a | 3567 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3568 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3569 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 3570 | context->root_level = 0; |
6aa8b732 | 3571 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3572 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3573 | context->direct_map = true; |
2d48a985 | 3574 | context->nx = false; |
6aa8b732 AK |
3575 | } |
3576 | ||
d8d173da | 3577 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu) |
6aa8b732 | 3578 | { |
cea0f0e7 | 3579 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3580 | } |
3581 | ||
5777ed34 JR |
3582 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
3583 | { | |
9f8fe504 | 3584 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
3585 | } |
3586 | ||
6389ee94 AK |
3587 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
3588 | struct x86_exception *fault) | |
6aa8b732 | 3589 | { |
6389ee94 | 3590 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
3591 | } |
3592 | ||
f2fd125d XG |
3593 | static bool sync_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn, |
3594 | unsigned access, int *nr_present) | |
ce88decf XG |
3595 | { |
3596 | if (unlikely(is_mmio_spte(*sptep))) { | |
3597 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
3598 | mmu_spte_clear_no_track(sptep); | |
3599 | return true; | |
3600 | } | |
3601 | ||
3602 | (*nr_present)++; | |
f2fd125d | 3603 | mark_mmio_spte(kvm, sptep, gfn, access); |
ce88decf XG |
3604 | return true; |
3605 | } | |
3606 | ||
3607 | return false; | |
3608 | } | |
3609 | ||
6fd01b71 AK |
3610 | static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte) |
3611 | { | |
3612 | unsigned index; | |
3613 | ||
3614 | index = level - 1; | |
3615 | index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2); | |
3616 | return mmu->last_pte_bitmap & (1 << index); | |
3617 | } | |
3618 | ||
37406aaa NHE |
3619 | #define PTTYPE_EPT 18 /* arbitrary */ |
3620 | #define PTTYPE PTTYPE_EPT | |
3621 | #include "paging_tmpl.h" | |
3622 | #undef PTTYPE | |
3623 | ||
6aa8b732 AK |
3624 | #define PTTYPE 64 |
3625 | #include "paging_tmpl.h" | |
3626 | #undef PTTYPE | |
3627 | ||
3628 | #define PTTYPE 32 | |
3629 | #include "paging_tmpl.h" | |
3630 | #undef PTTYPE | |
3631 | ||
52fde8df | 3632 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4d6931c3 | 3633 | struct kvm_mmu *context) |
82725b20 | 3634 | { |
82725b20 DE |
3635 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
3636 | u64 exb_bit_rsvd = 0; | |
5f7dde7b | 3637 | u64 gbpages_bit_rsvd = 0; |
a0c0feb5 | 3638 | u64 nonleaf_bit8_rsvd = 0; |
82725b20 | 3639 | |
25d92081 YZ |
3640 | context->bad_mt_xwr = 0; |
3641 | ||
2d48a985 | 3642 | if (!context->nx) |
82725b20 | 3643 | exb_bit_rsvd = rsvd_bits(63, 63); |
5f7dde7b NA |
3644 | if (!guest_cpuid_has_gbpages(vcpu)) |
3645 | gbpages_bit_rsvd = rsvd_bits(7, 7); | |
a0c0feb5 PB |
3646 | |
3647 | /* | |
3648 | * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for | |
3649 | * leaf entries) on AMD CPUs only. | |
3650 | */ | |
3651 | if (guest_cpuid_is_amd(vcpu)) | |
3652 | nonleaf_bit8_rsvd = rsvd_bits(8, 8); | |
3653 | ||
4d6931c3 | 3654 | switch (context->root_level) { |
82725b20 DE |
3655 | case PT32_ROOT_LEVEL: |
3656 | /* no rsvd bits for 2 level 4K page table entries */ | |
3657 | context->rsvd_bits_mask[0][1] = 0; | |
3658 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
3659 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
3660 | ||
3661 | if (!is_pse(vcpu)) { | |
3662 | context->rsvd_bits_mask[1][1] = 0; | |
3663 | break; | |
3664 | } | |
3665 | ||
82725b20 DE |
3666 | if (is_cpuid_PSE36()) |
3667 | /* 36bits PSE 4MB page */ | |
3668 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
3669 | else | |
3670 | /* 32 bits PSE 4MB page */ | |
3671 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
3672 | break; |
3673 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
3674 | context->rsvd_bits_mask[0][2] = |
3675 | rsvd_bits(maxphyaddr, 63) | | |
cd9ae5fe | 3676 | rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */ |
82725b20 | 3677 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 3678 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
3679 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
3680 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
3681 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
3682 | rsvd_bits(maxphyaddr, 62) | | |
3683 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 3684 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
3685 | break; |
3686 | case PT64_ROOT_LEVEL: | |
3687 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
a0c0feb5 | 3688 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | rsvd_bits(maxphyaddr, 51); |
82725b20 | 3689 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | |
a0c0feb5 | 3690 | nonleaf_bit8_rsvd | gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51); |
82725b20 | 3691 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 3692 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
3693 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
3694 | rsvd_bits(maxphyaddr, 51); | |
3695 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 | 3696 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
5f7dde7b | 3697 | gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) | |
e04da980 | 3698 | rsvd_bits(13, 29); |
82725b20 | 3699 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
3700 | rsvd_bits(maxphyaddr, 51) | |
3701 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 3702 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
3703 | break; |
3704 | } | |
3705 | } | |
3706 | ||
25d92081 YZ |
3707 | static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, |
3708 | struct kvm_mmu *context, bool execonly) | |
3709 | { | |
3710 | int maxphyaddr = cpuid_maxphyaddr(vcpu); | |
3711 | int pte; | |
3712 | ||
3713 | context->rsvd_bits_mask[0][3] = | |
3714 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); | |
3715 | context->rsvd_bits_mask[0][2] = | |
3716 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); | |
3717 | context->rsvd_bits_mask[0][1] = | |
3718 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); | |
3719 | context->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51); | |
3720 | ||
3721 | /* large page */ | |
3722 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
3723 | context->rsvd_bits_mask[1][2] = | |
3724 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29); | |
3725 | context->rsvd_bits_mask[1][1] = | |
3726 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20); | |
3727 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; | |
3728 | ||
3729 | for (pte = 0; pte < 64; pte++) { | |
3730 | int rwx_bits = pte & 7; | |
3731 | int mt = pte >> 3; | |
3732 | if (mt == 0x2 || mt == 0x3 || mt == 0x7 || | |
3733 | rwx_bits == 0x2 || rwx_bits == 0x6 || | |
3734 | (rwx_bits == 0x4 && !execonly)) | |
3735 | context->bad_mt_xwr |= (1ull << pte); | |
3736 | } | |
3737 | } | |
3738 | ||
edc90b7d XG |
3739 | static void update_permission_bitmask(struct kvm_vcpu *vcpu, |
3740 | struct kvm_mmu *mmu, bool ept) | |
97d64b78 AK |
3741 | { |
3742 | unsigned bit, byte, pfec; | |
3743 | u8 map; | |
66386ade | 3744 | bool fault, x, w, u, wf, uf, ff, smapf, cr4_smap, cr4_smep, smap = 0; |
97d64b78 | 3745 | |
66386ade | 3746 | cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
97ec8c06 | 3747 | cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); |
97d64b78 AK |
3748 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { |
3749 | pfec = byte << 1; | |
3750 | map = 0; | |
3751 | wf = pfec & PFERR_WRITE_MASK; | |
3752 | uf = pfec & PFERR_USER_MASK; | |
3753 | ff = pfec & PFERR_FETCH_MASK; | |
97ec8c06 FW |
3754 | /* |
3755 | * PFERR_RSVD_MASK bit is set in PFEC if the access is not | |
3756 | * subject to SMAP restrictions, and cleared otherwise. The | |
3757 | * bit is only meaningful if the SMAP bit is set in CR4. | |
3758 | */ | |
3759 | smapf = !(pfec & PFERR_RSVD_MASK); | |
97d64b78 AK |
3760 | for (bit = 0; bit < 8; ++bit) { |
3761 | x = bit & ACC_EXEC_MASK; | |
3762 | w = bit & ACC_WRITE_MASK; | |
3763 | u = bit & ACC_USER_MASK; | |
3764 | ||
25d92081 YZ |
3765 | if (!ept) { |
3766 | /* Not really needed: !nx will cause pte.nx to fault */ | |
3767 | x |= !mmu->nx; | |
3768 | /* Allow supervisor writes if !cr0.wp */ | |
3769 | w |= !is_write_protection(vcpu) && !uf; | |
3770 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
66386ade | 3771 | x &= !(cr4_smep && u && !uf); |
97ec8c06 FW |
3772 | |
3773 | /* | |
3774 | * SMAP:kernel-mode data accesses from user-mode | |
3775 | * mappings should fault. A fault is considered | |
3776 | * as a SMAP violation if all of the following | |
3777 | * conditions are ture: | |
3778 | * - X86_CR4_SMAP is set in CR4 | |
3779 | * - An user page is accessed | |
3780 | * - Page fault in kernel mode | |
3781 | * - if CPL = 3 or X86_EFLAGS_AC is clear | |
3782 | * | |
3783 | * Here, we cover the first three conditions. | |
3784 | * The fourth is computed dynamically in | |
3785 | * permission_fault() and is in smapf. | |
3786 | * | |
3787 | * Also, SMAP does not affect instruction | |
3788 | * fetches, add the !ff check here to make it | |
3789 | * clearer. | |
3790 | */ | |
3791 | smap = cr4_smap && u && !uf && !ff; | |
25d92081 YZ |
3792 | } else |
3793 | /* Not really needed: no U/S accesses on ept */ | |
3794 | u = 1; | |
97d64b78 | 3795 | |
97ec8c06 FW |
3796 | fault = (ff && !x) || (uf && !u) || (wf && !w) || |
3797 | (smapf && smap); | |
97d64b78 AK |
3798 | map |= fault << bit; |
3799 | } | |
3800 | mmu->permissions[byte] = map; | |
3801 | } | |
3802 | } | |
3803 | ||
6fd01b71 AK |
3804 | static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
3805 | { | |
3806 | u8 map; | |
3807 | unsigned level, root_level = mmu->root_level; | |
3808 | const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */ | |
3809 | ||
3810 | if (root_level == PT32E_ROOT_LEVEL) | |
3811 | --root_level; | |
3812 | /* PT_PAGE_TABLE_LEVEL always terminates */ | |
3813 | map = 1 | (1 << ps_set_index); | |
3814 | for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) { | |
3815 | if (level <= PT_PDPE_LEVEL | |
3816 | && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu))) | |
3817 | map |= 1 << (ps_set_index | (level - 1)); | |
3818 | } | |
3819 | mmu->last_pte_bitmap = map; | |
3820 | } | |
3821 | ||
8a3c1a33 PB |
3822 | static void paging64_init_context_common(struct kvm_vcpu *vcpu, |
3823 | struct kvm_mmu *context, | |
3824 | int level) | |
6aa8b732 | 3825 | { |
2d48a985 | 3826 | context->nx = is_nx(vcpu); |
4d6931c3 | 3827 | context->root_level = level; |
2d48a985 | 3828 | |
4d6931c3 | 3829 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 3830 | update_permission_bitmask(vcpu, context, false); |
6fd01b71 | 3831 | update_last_pte_bitmap(vcpu, context); |
6aa8b732 | 3832 | |
fa4a2c08 | 3833 | MMU_WARN_ON(!is_pae(vcpu)); |
6aa8b732 | 3834 | context->page_fault = paging64_page_fault; |
6aa8b732 | 3835 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 3836 | context->sync_page = paging64_sync_page; |
a7052897 | 3837 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 3838 | context->update_pte = paging64_update_pte; |
17ac10ad | 3839 | context->shadow_root_level = level; |
17c3ba9d | 3840 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3841 | context->direct_map = false; |
6aa8b732 AK |
3842 | } |
3843 | ||
8a3c1a33 PB |
3844 | static void paging64_init_context(struct kvm_vcpu *vcpu, |
3845 | struct kvm_mmu *context) | |
17ac10ad | 3846 | { |
8a3c1a33 | 3847 | paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
3848 | } |
3849 | ||
8a3c1a33 PB |
3850 | static void paging32_init_context(struct kvm_vcpu *vcpu, |
3851 | struct kvm_mmu *context) | |
6aa8b732 | 3852 | { |
2d48a985 | 3853 | context->nx = false; |
4d6931c3 | 3854 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 3855 | |
4d6931c3 | 3856 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 3857 | update_permission_bitmask(vcpu, context, false); |
6fd01b71 | 3858 | update_last_pte_bitmap(vcpu, context); |
6aa8b732 | 3859 | |
6aa8b732 | 3860 | context->page_fault = paging32_page_fault; |
6aa8b732 | 3861 | context->gva_to_gpa = paging32_gva_to_gpa; |
e8bc217a | 3862 | context->sync_page = paging32_sync_page; |
a7052897 | 3863 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 3864 | context->update_pte = paging32_update_pte; |
6aa8b732 | 3865 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3866 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3867 | context->direct_map = false; |
6aa8b732 AK |
3868 | } |
3869 | ||
8a3c1a33 PB |
3870 | static void paging32E_init_context(struct kvm_vcpu *vcpu, |
3871 | struct kvm_mmu *context) | |
6aa8b732 | 3872 | { |
8a3c1a33 | 3873 | paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
3874 | } |
3875 | ||
8a3c1a33 | 3876 | static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 3877 | { |
ad896af0 | 3878 | struct kvm_mmu *context = &vcpu->arch.mmu; |
fb72d167 | 3879 | |
c445f8ef | 3880 | context->base_role.word = 0; |
fb72d167 | 3881 | context->page_fault = tdp_page_fault; |
e8bc217a | 3882 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3883 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3884 | context->update_pte = nonpaging_update_pte; |
67253af5 | 3885 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 3886 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3887 | context->direct_map = true; |
1c97f0a0 | 3888 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 3889 | context->get_cr3 = get_cr3; |
e4e517b4 | 3890 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 3891 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
3892 | |
3893 | if (!is_paging(vcpu)) { | |
2d48a985 | 3894 | context->nx = false; |
fb72d167 JR |
3895 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
3896 | context->root_level = 0; | |
3897 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3898 | context->nx = is_nx(vcpu); |
fb72d167 | 3899 | context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 DB |
3900 | reset_rsvds_bits_mask(vcpu, context); |
3901 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 3902 | } else if (is_pae(vcpu)) { |
2d48a985 | 3903 | context->nx = is_nx(vcpu); |
fb72d167 | 3904 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
3905 | reset_rsvds_bits_mask(vcpu, context); |
3906 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 3907 | } else { |
2d48a985 | 3908 | context->nx = false; |
fb72d167 | 3909 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
3910 | reset_rsvds_bits_mask(vcpu, context); |
3911 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
3912 | } |
3913 | ||
25d92081 | 3914 | update_permission_bitmask(vcpu, context, false); |
6fd01b71 | 3915 | update_last_pte_bitmap(vcpu, context); |
fb72d167 JR |
3916 | } |
3917 | ||
ad896af0 | 3918 | void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu) |
6aa8b732 | 3919 | { |
411c588d | 3920 | bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
edc90b7d | 3921 | bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); |
ad896af0 PB |
3922 | struct kvm_mmu *context = &vcpu->arch.mmu; |
3923 | ||
fa4a2c08 | 3924 | MMU_WARN_ON(VALID_PAGE(context->root_hpa)); |
6aa8b732 AK |
3925 | |
3926 | if (!is_paging(vcpu)) | |
8a3c1a33 | 3927 | nonpaging_init_context(vcpu, context); |
a9058ecd | 3928 | else if (is_long_mode(vcpu)) |
8a3c1a33 | 3929 | paging64_init_context(vcpu, context); |
6aa8b732 | 3930 | else if (is_pae(vcpu)) |
8a3c1a33 | 3931 | paging32E_init_context(vcpu, context); |
6aa8b732 | 3932 | else |
8a3c1a33 | 3933 | paging32_init_context(vcpu, context); |
a770f6f2 | 3934 | |
ad896af0 PB |
3935 | context->base_role.nxe = is_nx(vcpu); |
3936 | context->base_role.cr4_pae = !!is_pae(vcpu); | |
3937 | context->base_role.cr0_wp = is_write_protection(vcpu); | |
3938 | context->base_role.smep_andnot_wp | |
411c588d | 3939 | = smep && !is_write_protection(vcpu); |
edc90b7d XG |
3940 | context->base_role.smap_andnot_wp |
3941 | = smap && !is_write_protection(vcpu); | |
52fde8df JR |
3942 | } |
3943 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
3944 | ||
ad896af0 | 3945 | void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly) |
155a97a3 | 3946 | { |
ad896af0 PB |
3947 | struct kvm_mmu *context = &vcpu->arch.mmu; |
3948 | ||
fa4a2c08 | 3949 | MMU_WARN_ON(VALID_PAGE(context->root_hpa)); |
155a97a3 NHE |
3950 | |
3951 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); | |
3952 | ||
3953 | context->nx = true; | |
155a97a3 NHE |
3954 | context->page_fault = ept_page_fault; |
3955 | context->gva_to_gpa = ept_gva_to_gpa; | |
3956 | context->sync_page = ept_sync_page; | |
3957 | context->invlpg = ept_invlpg; | |
3958 | context->update_pte = ept_update_pte; | |
155a97a3 NHE |
3959 | context->root_level = context->shadow_root_level; |
3960 | context->root_hpa = INVALID_PAGE; | |
3961 | context->direct_map = false; | |
3962 | ||
3963 | update_permission_bitmask(vcpu, context, true); | |
3964 | reset_rsvds_bits_mask_ept(vcpu, context, execonly); | |
155a97a3 NHE |
3965 | } |
3966 | EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu); | |
3967 | ||
8a3c1a33 | 3968 | static void init_kvm_softmmu(struct kvm_vcpu *vcpu) |
52fde8df | 3969 | { |
ad896af0 PB |
3970 | struct kvm_mmu *context = &vcpu->arch.mmu; |
3971 | ||
3972 | kvm_init_shadow_mmu(vcpu); | |
3973 | context->set_cr3 = kvm_x86_ops->set_cr3; | |
3974 | context->get_cr3 = get_cr3; | |
3975 | context->get_pdptr = kvm_pdptr_read; | |
3976 | context->inject_page_fault = kvm_inject_page_fault; | |
6aa8b732 AK |
3977 | } |
3978 | ||
8a3c1a33 | 3979 | static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
02f59dc9 JR |
3980 | { |
3981 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
3982 | ||
3983 | g_context->get_cr3 = get_cr3; | |
e4e517b4 | 3984 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
3985 | g_context->inject_page_fault = kvm_inject_page_fault; |
3986 | ||
3987 | /* | |
3988 | * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The | |
3989 | * translation of l2_gpa to l1_gpa addresses is done using the | |
3990 | * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa | |
3991 | * functions between mmu and nested_mmu are swapped. | |
3992 | */ | |
3993 | if (!is_paging(vcpu)) { | |
2d48a985 | 3994 | g_context->nx = false; |
02f59dc9 JR |
3995 | g_context->root_level = 0; |
3996 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
3997 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3998 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 3999 | g_context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 | 4000 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4001 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4002 | } else if (is_pae(vcpu)) { | |
2d48a985 | 4003 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 4004 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 4005 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4006 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4007 | } else { | |
2d48a985 | 4008 | g_context->nx = false; |
02f59dc9 | 4009 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 4010 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4011 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
4012 | } | |
4013 | ||
25d92081 | 4014 | update_permission_bitmask(vcpu, g_context, false); |
6fd01b71 | 4015 | update_last_pte_bitmap(vcpu, g_context); |
02f59dc9 JR |
4016 | } |
4017 | ||
8a3c1a33 | 4018 | static void init_kvm_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4019 | { |
02f59dc9 | 4020 | if (mmu_is_nested(vcpu)) |
e0c6db3e | 4021 | init_kvm_nested_mmu(vcpu); |
02f59dc9 | 4022 | else if (tdp_enabled) |
e0c6db3e | 4023 | init_kvm_tdp_mmu(vcpu); |
fb72d167 | 4024 | else |
e0c6db3e | 4025 | init_kvm_softmmu(vcpu); |
fb72d167 JR |
4026 | } |
4027 | ||
8a3c1a33 | 4028 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu) |
6aa8b732 | 4029 | { |
95f93af4 | 4030 | kvm_mmu_unload(vcpu); |
8a3c1a33 | 4031 | init_kvm_mmu(vcpu); |
17c3ba9d | 4032 | } |
8668a3c4 | 4033 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
4034 | |
4035 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 4036 | { |
714b93da AK |
4037 | int r; |
4038 | ||
e2dec939 | 4039 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
4040 | if (r) |
4041 | goto out; | |
8986ecc0 | 4042 | r = mmu_alloc_roots(vcpu); |
e2858b4a | 4043 | kvm_mmu_sync_roots(vcpu); |
8986ecc0 MT |
4044 | if (r) |
4045 | goto out; | |
3662cb1c | 4046 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 4047 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
4048 | out: |
4049 | return r; | |
6aa8b732 | 4050 | } |
17c3ba9d AK |
4051 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
4052 | ||
4053 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
4054 | { | |
4055 | mmu_free_roots(vcpu); | |
95f93af4 | 4056 | WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
17c3ba9d | 4057 | } |
4b16184c | 4058 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 4059 | |
0028425f | 4060 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
4061 | struct kvm_mmu_page *sp, u64 *spte, |
4062 | const void *new) | |
0028425f | 4063 | { |
30945387 | 4064 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
4065 | ++vcpu->kvm->stat.mmu_pde_zapped; |
4066 | return; | |
30945387 | 4067 | } |
0028425f | 4068 | |
4cee5764 | 4069 | ++vcpu->kvm->stat.mmu_pte_updated; |
7c562522 | 4070 | vcpu->arch.mmu.update_pte(vcpu, sp, spte, new); |
0028425f AK |
4071 | } |
4072 | ||
79539cec AK |
4073 | static bool need_remote_flush(u64 old, u64 new) |
4074 | { | |
4075 | if (!is_shadow_present_pte(old)) | |
4076 | return false; | |
4077 | if (!is_shadow_present_pte(new)) | |
4078 | return true; | |
4079 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
4080 | return true; | |
53166229 GN |
4081 | old ^= shadow_nx_mask; |
4082 | new ^= shadow_nx_mask; | |
79539cec AK |
4083 | return (old & ~new & PT64_PERM_MASK) != 0; |
4084 | } | |
4085 | ||
0671a8e7 XG |
4086 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
4087 | bool remote_flush, bool local_flush) | |
79539cec | 4088 | { |
0671a8e7 XG |
4089 | if (zap_page) |
4090 | return; | |
4091 | ||
4092 | if (remote_flush) | |
79539cec | 4093 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 4094 | else if (local_flush) |
77c3913b | 4095 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
79539cec AK |
4096 | } |
4097 | ||
889e5cbc XG |
4098 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
4099 | const u8 *new, int *bytes) | |
da4a00f0 | 4100 | { |
889e5cbc XG |
4101 | u64 gentry; |
4102 | int r; | |
72016f3a | 4103 | |
72016f3a AK |
4104 | /* |
4105 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
4106 | * as the current vcpu paging mode since we update the sptes only |
4107 | * when they have the same mode. | |
72016f3a | 4108 | */ |
889e5cbc | 4109 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 4110 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
4111 | *gpa &= ~(gpa_t)7; |
4112 | *bytes = 8; | |
116eb3d3 | 4113 | r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, 8); |
72016f3a AK |
4114 | if (r) |
4115 | gentry = 0; | |
08e850c6 AK |
4116 | new = (const u8 *)&gentry; |
4117 | } | |
4118 | ||
889e5cbc | 4119 | switch (*bytes) { |
08e850c6 AK |
4120 | case 4: |
4121 | gentry = *(const u32 *)new; | |
4122 | break; | |
4123 | case 8: | |
4124 | gentry = *(const u64 *)new; | |
4125 | break; | |
4126 | default: | |
4127 | gentry = 0; | |
4128 | break; | |
72016f3a AK |
4129 | } |
4130 | ||
889e5cbc XG |
4131 | return gentry; |
4132 | } | |
4133 | ||
4134 | /* | |
4135 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
4136 | * or we may be forking, in which case it is better to unmap the page. | |
4137 | */ | |
a138fe75 | 4138 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 4139 | { |
a30f47cb XG |
4140 | /* |
4141 | * Skip write-flooding detected for the sp whose level is 1, because | |
4142 | * it can become unsync, then the guest page is not write-protected. | |
4143 | */ | |
f71fa31f | 4144 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) |
a30f47cb | 4145 | return false; |
3246af0e | 4146 | |
a30f47cb | 4147 | return ++sp->write_flooding_count >= 3; |
889e5cbc XG |
4148 | } |
4149 | ||
4150 | /* | |
4151 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
4152 | * indicate a page is not used as a page table. | |
4153 | */ | |
4154 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
4155 | int bytes) | |
4156 | { | |
4157 | unsigned offset, pte_size, misaligned; | |
4158 | ||
4159 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4160 | gpa, bytes, sp->role.word); | |
4161 | ||
4162 | offset = offset_in_page(gpa); | |
4163 | pte_size = sp->role.cr4_pae ? 8 : 4; | |
5d9ca30e XG |
4164 | |
4165 | /* | |
4166 | * Sometimes, the OS only writes the last one bytes to update status | |
4167 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
4168 | */ | |
4169 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
4170 | return false; | |
4171 | ||
889e5cbc XG |
4172 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
4173 | misaligned |= bytes < 4; | |
4174 | ||
4175 | return misaligned; | |
4176 | } | |
4177 | ||
4178 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
4179 | { | |
4180 | unsigned page_offset, quadrant; | |
4181 | u64 *spte; | |
4182 | int level; | |
4183 | ||
4184 | page_offset = offset_in_page(gpa); | |
4185 | level = sp->role.level; | |
4186 | *nspte = 1; | |
4187 | if (!sp->role.cr4_pae) { | |
4188 | page_offset <<= 1; /* 32->64 */ | |
4189 | /* | |
4190 | * A 32-bit pde maps 4MB while the shadow pdes map | |
4191 | * only 2MB. So we need to double the offset again | |
4192 | * and zap two pdes instead of one. | |
4193 | */ | |
4194 | if (level == PT32_ROOT_LEVEL) { | |
4195 | page_offset &= ~7; /* kill rounding error */ | |
4196 | page_offset <<= 1; | |
4197 | *nspte = 2; | |
4198 | } | |
4199 | quadrant = page_offset >> PAGE_SHIFT; | |
4200 | page_offset &= ~PAGE_MASK; | |
4201 | if (quadrant != sp->role.quadrant) | |
4202 | return NULL; | |
4203 | } | |
4204 | ||
4205 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
4206 | return spte; | |
4207 | } | |
4208 | ||
4209 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4210 | const u8 *new, int bytes) | |
4211 | { | |
4212 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
889e5cbc | 4213 | struct kvm_mmu_page *sp; |
889e5cbc XG |
4214 | LIST_HEAD(invalid_list); |
4215 | u64 entry, gentry, *spte; | |
4216 | int npte; | |
a30f47cb | 4217 | bool remote_flush, local_flush, zap_page; |
edc90b7d XG |
4218 | union kvm_mmu_page_role mask = (union kvm_mmu_page_role) { |
4219 | .cr0_wp = 1, | |
4220 | .cr4_pae = 1, | |
4221 | .nxe = 1, | |
4222 | .smep_andnot_wp = 1, | |
4223 | .smap_andnot_wp = 1, | |
4224 | }; | |
889e5cbc XG |
4225 | |
4226 | /* | |
4227 | * If we don't have indirect shadow pages, it means no page is | |
4228 | * write-protected, so we can exit simply. | |
4229 | */ | |
4230 | if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) | |
4231 | return; | |
4232 | ||
4233 | zap_page = remote_flush = local_flush = false; | |
4234 | ||
4235 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
4236 | ||
4237 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes); | |
4238 | ||
4239 | /* | |
4240 | * No need to care whether allocation memory is successful | |
4241 | * or not since pte prefetch is skiped if it does not have | |
4242 | * enough objects in the cache. | |
4243 | */ | |
4244 | mmu_topup_memory_caches(vcpu); | |
4245 | ||
4246 | spin_lock(&vcpu->kvm->mmu_lock); | |
4247 | ++vcpu->kvm->stat.mmu_pte_write; | |
0375f7fa | 4248 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 4249 | |
b67bfe0d | 4250 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 4251 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 4252 | detect_write_flooding(sp)) { |
0671a8e7 | 4253 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 4254 | &invalid_list); |
4cee5764 | 4255 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
4256 | continue; |
4257 | } | |
889e5cbc XG |
4258 | |
4259 | spte = get_written_sptes(sp, gpa, &npte); | |
4260 | if (!spte) | |
4261 | continue; | |
4262 | ||
0671a8e7 | 4263 | local_flush = true; |
ac1b714e | 4264 | while (npte--) { |
79539cec | 4265 | entry = *spte; |
38e3b2b2 | 4266 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf XG |
4267 | if (gentry && |
4268 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
f759e2b4 | 4269 | & mask.word) && rmap_can_add(vcpu)) |
7c562522 | 4270 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
9bb4f6b1 | 4271 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 4272 | remote_flush = true; |
ac1b714e | 4273 | ++spte; |
9b7a0325 | 4274 | } |
9b7a0325 | 4275 | } |
0671a8e7 | 4276 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 4277 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
0375f7fa | 4278 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 4279 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
4280 | } |
4281 | ||
a436036b AK |
4282 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
4283 | { | |
10589a46 MT |
4284 | gpa_t gpa; |
4285 | int r; | |
a436036b | 4286 | |
c5a78f2b | 4287 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
4288 | return 0; |
4289 | ||
1871c602 | 4290 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 4291 | |
10589a46 | 4292 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 4293 | |
10589a46 | 4294 | return r; |
a436036b | 4295 | } |
577bdc49 | 4296 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 4297 | |
81f4f76b | 4298 | static void make_mmu_pages_available(struct kvm_vcpu *vcpu) |
ebeace86 | 4299 | { |
d98ba053 | 4300 | LIST_HEAD(invalid_list); |
103ad25a | 4301 | |
81f4f76b TY |
4302 | if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES)) |
4303 | return; | |
4304 | ||
5da59607 TY |
4305 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) { |
4306 | if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list)) | |
4307 | break; | |
ebeace86 | 4308 | |
4cee5764 | 4309 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 4310 | } |
aa6bd187 | 4311 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
ebeace86 | 4312 | } |
ebeace86 | 4313 | |
1cb3f3ae XG |
4314 | static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr) |
4315 | { | |
4316 | if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu)) | |
4317 | return vcpu_match_mmio_gpa(vcpu, addr); | |
4318 | ||
4319 | return vcpu_match_mmio_gva(vcpu, addr); | |
4320 | } | |
4321 | ||
dc25e89e AP |
4322 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code, |
4323 | void *insn, int insn_len) | |
3067714c | 4324 | { |
1cb3f3ae | 4325 | int r, emulation_type = EMULTYPE_RETRY; |
3067714c AK |
4326 | enum emulation_result er; |
4327 | ||
56028d08 | 4328 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false); |
3067714c AK |
4329 | if (r < 0) |
4330 | goto out; | |
4331 | ||
4332 | if (!r) { | |
4333 | r = 1; | |
4334 | goto out; | |
4335 | } | |
4336 | ||
1cb3f3ae XG |
4337 | if (is_mmio_page_fault(vcpu, cr2)) |
4338 | emulation_type = 0; | |
4339 | ||
4340 | er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len); | |
3067714c AK |
4341 | |
4342 | switch (er) { | |
4343 | case EMULATE_DONE: | |
4344 | return 1; | |
ac0a48c3 | 4345 | case EMULATE_USER_EXIT: |
3067714c | 4346 | ++vcpu->stat.mmio_exits; |
6d77dbfc | 4347 | /* fall through */ |
3067714c | 4348 | case EMULATE_FAIL: |
3f5d18a9 | 4349 | return 0; |
3067714c AK |
4350 | default: |
4351 | BUG(); | |
4352 | } | |
4353 | out: | |
3067714c AK |
4354 | return r; |
4355 | } | |
4356 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
4357 | ||
a7052897 MT |
4358 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
4359 | { | |
a7052897 | 4360 | vcpu->arch.mmu.invlpg(vcpu, gva); |
77c3913b | 4361 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
a7052897 MT |
4362 | ++vcpu->stat.invlpg; |
4363 | } | |
4364 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
4365 | ||
18552672 JR |
4366 | void kvm_enable_tdp(void) |
4367 | { | |
4368 | tdp_enabled = true; | |
4369 | } | |
4370 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
4371 | ||
5f4cb662 JR |
4372 | void kvm_disable_tdp(void) |
4373 | { | |
4374 | tdp_enabled = false; | |
4375 | } | |
4376 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
4377 | ||
6aa8b732 AK |
4378 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
4379 | { | |
ad312c7c | 4380 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
81407ca5 JR |
4381 | if (vcpu->arch.mmu.lm_root != NULL) |
4382 | free_page((unsigned long)vcpu->arch.mmu.lm_root); | |
6aa8b732 AK |
4383 | } |
4384 | ||
4385 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
4386 | { | |
17ac10ad | 4387 | struct page *page; |
6aa8b732 AK |
4388 | int i; |
4389 | ||
17ac10ad AK |
4390 | /* |
4391 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
4392 | * Therefore we need to allocate shadow page tables in the first | |
4393 | * 4GB of memory, which happens to fit the DMA32 zone. | |
4394 | */ | |
4395 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
4396 | if (!page) | |
d7fa6ab2 WY |
4397 | return -ENOMEM; |
4398 | ||
ad312c7c | 4399 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 4400 | for (i = 0; i < 4; ++i) |
ad312c7c | 4401 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 4402 | |
6aa8b732 | 4403 | return 0; |
6aa8b732 AK |
4404 | } |
4405 | ||
8018c27b | 4406 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 4407 | { |
e459e322 XG |
4408 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; |
4409 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; | |
4410 | vcpu->arch.mmu.translate_gpa = translate_gpa; | |
4411 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; | |
6aa8b732 | 4412 | |
8018c27b IM |
4413 | return alloc_mmu_pages(vcpu); |
4414 | } | |
6aa8b732 | 4415 | |
8a3c1a33 | 4416 | void kvm_mmu_setup(struct kvm_vcpu *vcpu) |
8018c27b | 4417 | { |
fa4a2c08 | 4418 | MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 4419 | |
8a3c1a33 | 4420 | init_kvm_mmu(vcpu); |
6aa8b732 AK |
4421 | } |
4422 | ||
1c91cad4 KH |
4423 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
4424 | struct kvm_memory_slot *memslot) | |
6aa8b732 | 4425 | { |
b99db1d3 TY |
4426 | gfn_t last_gfn; |
4427 | int i; | |
d91ffee9 | 4428 | bool flush = false; |
6aa8b732 | 4429 | |
b99db1d3 | 4430 | last_gfn = memslot->base_gfn + memslot->npages - 1; |
6aa8b732 | 4431 | |
9d1beefb TY |
4432 | spin_lock(&kvm->mmu_lock); |
4433 | ||
b99db1d3 TY |
4434 | for (i = PT_PAGE_TABLE_LEVEL; |
4435 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
4436 | unsigned long *rmapp; | |
4437 | unsigned long last_index, index; | |
6aa8b732 | 4438 | |
b99db1d3 TY |
4439 | rmapp = memslot->arch.rmap[i - PT_PAGE_TABLE_LEVEL]; |
4440 | last_index = gfn_to_index(last_gfn, memslot->base_gfn, i); | |
da8dc75f | 4441 | |
b99db1d3 TY |
4442 | for (index = 0; index <= last_index; ++index, ++rmapp) { |
4443 | if (*rmapp) | |
d91ffee9 KH |
4444 | flush |= __rmap_write_protect(kvm, rmapp, |
4445 | false); | |
6b81b05e | 4446 | |
198c74f4 | 4447 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) |
6b81b05e | 4448 | cond_resched_lock(&kvm->mmu_lock); |
8234b22e | 4449 | } |
6aa8b732 | 4450 | } |
b99db1d3 | 4451 | |
9d1beefb | 4452 | spin_unlock(&kvm->mmu_lock); |
198c74f4 XG |
4453 | |
4454 | /* | |
4455 | * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log() | |
4456 | * which do tlb flush out of mmu-lock should be serialized by | |
4457 | * kvm->slots_lock otherwise tlb flush would be missed. | |
4458 | */ | |
4459 | lockdep_assert_held(&kvm->slots_lock); | |
4460 | ||
4461 | /* | |
4462 | * We can flush all the TLBs out of the mmu lock without TLB | |
4463 | * corruption since we just change the spte from writable to | |
4464 | * readonly so that we only need to care the case of changing | |
4465 | * spte from present to present (changing the spte from present | |
4466 | * to nonpresent will flush all the TLBs immediately), in other | |
4467 | * words, the only case we care is mmu_spte_update() where we | |
4468 | * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE | |
4469 | * instead of PT_WRITABLE_MASK, that means it does not depend | |
4470 | * on PT_WRITABLE_MASK anymore. | |
4471 | */ | |
d91ffee9 KH |
4472 | if (flush) |
4473 | kvm_flush_remote_tlbs(kvm); | |
6aa8b732 | 4474 | } |
37a7d8b0 | 4475 | |
3ea3b7fa WL |
4476 | static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm, |
4477 | unsigned long *rmapp) | |
4478 | { | |
4479 | u64 *sptep; | |
4480 | struct rmap_iterator iter; | |
4481 | int need_tlb_flush = 0; | |
4482 | pfn_t pfn; | |
4483 | struct kvm_mmu_page *sp; | |
4484 | ||
4485 | for (sptep = rmap_get_first(*rmapp, &iter); sptep;) { | |
4486 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
4487 | ||
4488 | sp = page_header(__pa(sptep)); | |
4489 | pfn = spte_to_pfn(*sptep); | |
4490 | ||
4491 | /* | |
decf6333 XG |
4492 | * We cannot do huge page mapping for indirect shadow pages, |
4493 | * which are found on the last rmap (level = 1) when not using | |
4494 | * tdp; such shadow pages are synced with the page table in | |
4495 | * the guest, and the guest page table is using 4K page size | |
4496 | * mapping if the indirect sp has level = 1. | |
3ea3b7fa WL |
4497 | */ |
4498 | if (sp->role.direct && | |
4499 | !kvm_is_reserved_pfn(pfn) && | |
4500 | PageTransCompound(pfn_to_page(pfn))) { | |
4501 | drop_spte(kvm, sptep); | |
4502 | sptep = rmap_get_first(*rmapp, &iter); | |
4503 | need_tlb_flush = 1; | |
4504 | } else | |
4505 | sptep = rmap_get_next(&iter); | |
4506 | } | |
4507 | ||
4508 | return need_tlb_flush; | |
4509 | } | |
4510 | ||
4511 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, | |
4512 | struct kvm_memory_slot *memslot) | |
4513 | { | |
4514 | bool flush = false; | |
4515 | unsigned long *rmapp; | |
4516 | unsigned long last_index, index; | |
3ea3b7fa WL |
4517 | |
4518 | spin_lock(&kvm->mmu_lock); | |
4519 | ||
3ea3b7fa | 4520 | rmapp = memslot->arch.rmap[0]; |
13000523 WL |
4521 | last_index = gfn_to_index(memslot->base_gfn + memslot->npages - 1, |
4522 | memslot->base_gfn, PT_PAGE_TABLE_LEVEL); | |
3ea3b7fa WL |
4523 | |
4524 | for (index = 0; index <= last_index; ++index, ++rmapp) { | |
4525 | if (*rmapp) | |
4526 | flush |= kvm_mmu_zap_collapsible_spte(kvm, rmapp); | |
4527 | ||
4528 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { | |
4529 | if (flush) { | |
4530 | kvm_flush_remote_tlbs(kvm); | |
4531 | flush = false; | |
4532 | } | |
4533 | cond_resched_lock(&kvm->mmu_lock); | |
4534 | } | |
4535 | } | |
4536 | ||
4537 | if (flush) | |
4538 | kvm_flush_remote_tlbs(kvm); | |
4539 | ||
3ea3b7fa WL |
4540 | spin_unlock(&kvm->mmu_lock); |
4541 | } | |
4542 | ||
f4b4b180 KH |
4543 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
4544 | struct kvm_memory_slot *memslot) | |
4545 | { | |
4546 | gfn_t last_gfn; | |
4547 | unsigned long *rmapp; | |
4548 | unsigned long last_index, index; | |
4549 | bool flush = false; | |
4550 | ||
4551 | last_gfn = memslot->base_gfn + memslot->npages - 1; | |
4552 | ||
4553 | spin_lock(&kvm->mmu_lock); | |
4554 | ||
4555 | rmapp = memslot->arch.rmap[PT_PAGE_TABLE_LEVEL - 1]; | |
4556 | last_index = gfn_to_index(last_gfn, memslot->base_gfn, | |
4557 | PT_PAGE_TABLE_LEVEL); | |
4558 | ||
4559 | for (index = 0; index <= last_index; ++index, ++rmapp) { | |
4560 | if (*rmapp) | |
4561 | flush |= __rmap_clear_dirty(kvm, rmapp); | |
4562 | ||
4563 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) | |
4564 | cond_resched_lock(&kvm->mmu_lock); | |
4565 | } | |
4566 | ||
4567 | spin_unlock(&kvm->mmu_lock); | |
4568 | ||
4569 | lockdep_assert_held(&kvm->slots_lock); | |
4570 | ||
4571 | /* | |
4572 | * It's also safe to flush TLBs out of mmu lock here as currently this | |
4573 | * function is only used for dirty logging, in which case flushing TLB | |
4574 | * out of mmu lock also guarantees no dirty pages will be lost in | |
4575 | * dirty_bitmap. | |
4576 | */ | |
4577 | if (flush) | |
4578 | kvm_flush_remote_tlbs(kvm); | |
4579 | } | |
4580 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty); | |
4581 | ||
4582 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
4583 | struct kvm_memory_slot *memslot) | |
4584 | { | |
4585 | gfn_t last_gfn; | |
4586 | int i; | |
4587 | bool flush = false; | |
4588 | ||
4589 | last_gfn = memslot->base_gfn + memslot->npages - 1; | |
4590 | ||
4591 | spin_lock(&kvm->mmu_lock); | |
4592 | ||
4593 | for (i = PT_PAGE_TABLE_LEVEL + 1; /* skip rmap for 4K page */ | |
4594 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
4595 | unsigned long *rmapp; | |
4596 | unsigned long last_index, index; | |
4597 | ||
4598 | rmapp = memslot->arch.rmap[i - PT_PAGE_TABLE_LEVEL]; | |
4599 | last_index = gfn_to_index(last_gfn, memslot->base_gfn, i); | |
4600 | ||
4601 | for (index = 0; index <= last_index; ++index, ++rmapp) { | |
4602 | if (*rmapp) | |
4603 | flush |= __rmap_write_protect(kvm, rmapp, | |
4604 | false); | |
4605 | ||
4606 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) | |
4607 | cond_resched_lock(&kvm->mmu_lock); | |
4608 | } | |
4609 | } | |
4610 | spin_unlock(&kvm->mmu_lock); | |
4611 | ||
4612 | /* see kvm_mmu_slot_remove_write_access */ | |
4613 | lockdep_assert_held(&kvm->slots_lock); | |
4614 | ||
4615 | if (flush) | |
4616 | kvm_flush_remote_tlbs(kvm); | |
4617 | } | |
4618 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access); | |
4619 | ||
4620 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
4621 | struct kvm_memory_slot *memslot) | |
4622 | { | |
4623 | gfn_t last_gfn; | |
4624 | int i; | |
4625 | bool flush = false; | |
4626 | ||
4627 | last_gfn = memslot->base_gfn + memslot->npages - 1; | |
4628 | ||
4629 | spin_lock(&kvm->mmu_lock); | |
4630 | ||
4631 | for (i = PT_PAGE_TABLE_LEVEL; | |
4632 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
4633 | unsigned long *rmapp; | |
4634 | unsigned long last_index, index; | |
4635 | ||
4636 | rmapp = memslot->arch.rmap[i - PT_PAGE_TABLE_LEVEL]; | |
4637 | last_index = gfn_to_index(last_gfn, memslot->base_gfn, i); | |
4638 | ||
4639 | for (index = 0; index <= last_index; ++index, ++rmapp) { | |
4640 | if (*rmapp) | |
4641 | flush |= __rmap_set_dirty(kvm, rmapp); | |
4642 | ||
4643 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) | |
4644 | cond_resched_lock(&kvm->mmu_lock); | |
4645 | } | |
4646 | } | |
4647 | ||
4648 | spin_unlock(&kvm->mmu_lock); | |
4649 | ||
4650 | lockdep_assert_held(&kvm->slots_lock); | |
4651 | ||
4652 | /* see kvm_mmu_slot_leaf_clear_dirty */ | |
4653 | if (flush) | |
4654 | kvm_flush_remote_tlbs(kvm); | |
4655 | } | |
4656 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty); | |
4657 | ||
e7d11c7a | 4658 | #define BATCH_ZAP_PAGES 10 |
5304b8d3 XG |
4659 | static void kvm_zap_obsolete_pages(struct kvm *kvm) |
4660 | { | |
4661 | struct kvm_mmu_page *sp, *node; | |
e7d11c7a | 4662 | int batch = 0; |
5304b8d3 XG |
4663 | |
4664 | restart: | |
4665 | list_for_each_entry_safe_reverse(sp, node, | |
4666 | &kvm->arch.active_mmu_pages, link) { | |
e7d11c7a XG |
4667 | int ret; |
4668 | ||
5304b8d3 XG |
4669 | /* |
4670 | * No obsolete page exists before new created page since | |
4671 | * active_mmu_pages is the FIFO list. | |
4672 | */ | |
4673 | if (!is_obsolete_sp(kvm, sp)) | |
4674 | break; | |
4675 | ||
4676 | /* | |
5304b8d3 XG |
4677 | * Since we are reversely walking the list and the invalid |
4678 | * list will be moved to the head, skip the invalid page | |
4679 | * can help us to avoid the infinity list walking. | |
4680 | */ | |
4681 | if (sp->role.invalid) | |
4682 | continue; | |
4683 | ||
f34d251d XG |
4684 | /* |
4685 | * Need not flush tlb since we only zap the sp with invalid | |
4686 | * generation number. | |
4687 | */ | |
e7d11c7a | 4688 | if (batch >= BATCH_ZAP_PAGES && |
f34d251d | 4689 | cond_resched_lock(&kvm->mmu_lock)) { |
e7d11c7a | 4690 | batch = 0; |
5304b8d3 XG |
4691 | goto restart; |
4692 | } | |
4693 | ||
365c8868 XG |
4694 | ret = kvm_mmu_prepare_zap_page(kvm, sp, |
4695 | &kvm->arch.zapped_obsolete_pages); | |
e7d11c7a XG |
4696 | batch += ret; |
4697 | ||
4698 | if (ret) | |
5304b8d3 XG |
4699 | goto restart; |
4700 | } | |
4701 | ||
f34d251d XG |
4702 | /* |
4703 | * Should flush tlb before free page tables since lockless-walking | |
4704 | * may use the pages. | |
4705 | */ | |
365c8868 | 4706 | kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages); |
5304b8d3 XG |
4707 | } |
4708 | ||
4709 | /* | |
4710 | * Fast invalidate all shadow pages and use lock-break technique | |
4711 | * to zap obsolete pages. | |
4712 | * | |
4713 | * It's required when memslot is being deleted or VM is being | |
4714 | * destroyed, in these cases, we should ensure that KVM MMU does | |
4715 | * not use any resource of the being-deleted slot or all slots | |
4716 | * after calling the function. | |
4717 | */ | |
4718 | void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm) | |
4719 | { | |
4720 | spin_lock(&kvm->mmu_lock); | |
35006126 | 4721 | trace_kvm_mmu_invalidate_zap_all_pages(kvm); |
5304b8d3 XG |
4722 | kvm->arch.mmu_valid_gen++; |
4723 | ||
f34d251d XG |
4724 | /* |
4725 | * Notify all vcpus to reload its shadow page table | |
4726 | * and flush TLB. Then all vcpus will switch to new | |
4727 | * shadow page table with the new mmu_valid_gen. | |
4728 | * | |
4729 | * Note: we should do this under the protection of | |
4730 | * mmu-lock, otherwise, vcpu would purge shadow page | |
4731 | * but miss tlb flush. | |
4732 | */ | |
4733 | kvm_reload_remote_mmus(kvm); | |
4734 | ||
5304b8d3 XG |
4735 | kvm_zap_obsolete_pages(kvm); |
4736 | spin_unlock(&kvm->mmu_lock); | |
4737 | } | |
4738 | ||
365c8868 XG |
4739 | static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm) |
4740 | { | |
4741 | return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages)); | |
4742 | } | |
4743 | ||
f8f55942 XG |
4744 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm) |
4745 | { | |
4746 | /* | |
4747 | * The very rare case: if the generation-number is round, | |
4748 | * zap all shadow pages. | |
f8f55942 | 4749 | */ |
ee3d1570 | 4750 | if (unlikely(kvm_current_mmio_generation(kvm) == 0)) { |
a629df7e | 4751 | printk_ratelimited(KERN_DEBUG "kvm: zapping shadow pages for mmio generation wraparound\n"); |
a8eca9dc | 4752 | kvm_mmu_invalidate_zap_all_pages(kvm); |
7a2e8aaf | 4753 | } |
f8f55942 XG |
4754 | } |
4755 | ||
70534a73 DC |
4756 | static unsigned long |
4757 | mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) | |
3ee16c81 IE |
4758 | { |
4759 | struct kvm *kvm; | |
1495f230 | 4760 | int nr_to_scan = sc->nr_to_scan; |
70534a73 | 4761 | unsigned long freed = 0; |
3ee16c81 | 4762 | |
2f303b74 | 4763 | spin_lock(&kvm_lock); |
3ee16c81 IE |
4764 | |
4765 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 4766 | int idx; |
d98ba053 | 4767 | LIST_HEAD(invalid_list); |
3ee16c81 | 4768 | |
35f2d16b TY |
4769 | /* |
4770 | * Never scan more than sc->nr_to_scan VM instances. | |
4771 | * Will not hit this condition practically since we do not try | |
4772 | * to shrink more than one VM and it is very unlikely to see | |
4773 | * !n_used_mmu_pages so many times. | |
4774 | */ | |
4775 | if (!nr_to_scan--) | |
4776 | break; | |
19526396 GN |
4777 | /* |
4778 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
4779 | * here. We may skip a VM instance errorneosly, but we do not | |
4780 | * want to shrink a VM that only started to populate its MMU | |
4781 | * anyway. | |
4782 | */ | |
365c8868 XG |
4783 | if (!kvm->arch.n_used_mmu_pages && |
4784 | !kvm_has_zapped_obsolete_pages(kvm)) | |
19526396 | 4785 | continue; |
19526396 | 4786 | |
f656ce01 | 4787 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 4788 | spin_lock(&kvm->mmu_lock); |
3ee16c81 | 4789 | |
365c8868 XG |
4790 | if (kvm_has_zapped_obsolete_pages(kvm)) { |
4791 | kvm_mmu_commit_zap_page(kvm, | |
4792 | &kvm->arch.zapped_obsolete_pages); | |
4793 | goto unlock; | |
4794 | } | |
4795 | ||
70534a73 DC |
4796 | if (prepare_zap_oldest_mmu_page(kvm, &invalid_list)) |
4797 | freed++; | |
d98ba053 | 4798 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
19526396 | 4799 | |
365c8868 | 4800 | unlock: |
3ee16c81 | 4801 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 4802 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 | 4803 | |
70534a73 DC |
4804 | /* |
4805 | * unfair on small ones | |
4806 | * per-vm shrinkers cry out | |
4807 | * sadness comes quickly | |
4808 | */ | |
19526396 GN |
4809 | list_move_tail(&kvm->vm_list, &vm_list); |
4810 | break; | |
3ee16c81 | 4811 | } |
3ee16c81 | 4812 | |
2f303b74 | 4813 | spin_unlock(&kvm_lock); |
70534a73 | 4814 | return freed; |
70534a73 DC |
4815 | } |
4816 | ||
4817 | static unsigned long | |
4818 | mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc) | |
4819 | { | |
45221ab6 | 4820 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
4821 | } |
4822 | ||
4823 | static struct shrinker mmu_shrinker = { | |
70534a73 DC |
4824 | .count_objects = mmu_shrink_count, |
4825 | .scan_objects = mmu_shrink_scan, | |
3ee16c81 IE |
4826 | .seeks = DEFAULT_SEEKS * 10, |
4827 | }; | |
4828 | ||
2ddfd20e | 4829 | static void mmu_destroy_caches(void) |
b5a33a75 | 4830 | { |
53c07b18 XG |
4831 | if (pte_list_desc_cache) |
4832 | kmem_cache_destroy(pte_list_desc_cache); | |
d3d25b04 AK |
4833 | if (mmu_page_header_cache) |
4834 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
4835 | } |
4836 | ||
4837 | int kvm_mmu_module_init(void) | |
4838 | { | |
53c07b18 XG |
4839 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
4840 | sizeof(struct pte_list_desc), | |
20c2df83 | 4841 | 0, 0, NULL); |
53c07b18 | 4842 | if (!pte_list_desc_cache) |
b5a33a75 AK |
4843 | goto nomem; |
4844 | ||
d3d25b04 AK |
4845 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
4846 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 4847 | 0, 0, NULL); |
d3d25b04 AK |
4848 | if (!mmu_page_header_cache) |
4849 | goto nomem; | |
4850 | ||
908c7f19 | 4851 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL)) |
45bf21a8 WY |
4852 | goto nomem; |
4853 | ||
3ee16c81 IE |
4854 | register_shrinker(&mmu_shrinker); |
4855 | ||
b5a33a75 AK |
4856 | return 0; |
4857 | ||
4858 | nomem: | |
3ee16c81 | 4859 | mmu_destroy_caches(); |
b5a33a75 AK |
4860 | return -ENOMEM; |
4861 | } | |
4862 | ||
3ad82a7e ZX |
4863 | /* |
4864 | * Caculate mmu pages needed for kvm. | |
4865 | */ | |
4866 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
4867 | { | |
3ad82a7e ZX |
4868 | unsigned int nr_mmu_pages; |
4869 | unsigned int nr_pages = 0; | |
bc6678a3 | 4870 | struct kvm_memslots *slots; |
be6ba0f0 | 4871 | struct kvm_memory_slot *memslot; |
3ad82a7e | 4872 | |
90d83dc3 LJ |
4873 | slots = kvm_memslots(kvm); |
4874 | ||
be6ba0f0 XG |
4875 | kvm_for_each_memslot(memslot, slots) |
4876 | nr_pages += memslot->npages; | |
3ad82a7e ZX |
4877 | |
4878 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
4879 | nr_mmu_pages = max(nr_mmu_pages, | |
4880 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
4881 | ||
4882 | return nr_mmu_pages; | |
4883 | } | |
4884 | ||
94d8b056 MT |
4885 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
4886 | { | |
4887 | struct kvm_shadow_walk_iterator iterator; | |
c2a2ac2b | 4888 | u64 spte; |
94d8b056 MT |
4889 | int nr_sptes = 0; |
4890 | ||
37f6a4e2 MT |
4891 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
4892 | return nr_sptes; | |
4893 | ||
c2a2ac2b XG |
4894 | walk_shadow_page_lockless_begin(vcpu); |
4895 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
4896 | sptes[iterator.level-1] = spte; | |
94d8b056 | 4897 | nr_sptes++; |
c2a2ac2b | 4898 | if (!is_shadow_present_pte(spte)) |
94d8b056 MT |
4899 | break; |
4900 | } | |
c2a2ac2b | 4901 | walk_shadow_page_lockless_end(vcpu); |
94d8b056 MT |
4902 | |
4903 | return nr_sptes; | |
4904 | } | |
4905 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
4906 | ||
c42fffe3 XG |
4907 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
4908 | { | |
95f93af4 | 4909 | kvm_mmu_unload(vcpu); |
c42fffe3 XG |
4910 | free_mmu_pages(vcpu); |
4911 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
4912 | } |
4913 | ||
b034cf01 XG |
4914 | void kvm_mmu_module_exit(void) |
4915 | { | |
4916 | mmu_destroy_caches(); | |
4917 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
4918 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
4919 | mmu_audit_disable(); |
4920 | } |