Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
af585b92 | 25 | #include "x86.h" |
e495606d | 26 | |
edf88417 | 27 | #include <linux/kvm_host.h> |
6aa8b732 AK |
28 | #include <linux/types.h> |
29 | #include <linux/string.h> | |
6aa8b732 AK |
30 | #include <linux/mm.h> |
31 | #include <linux/highmem.h> | |
32 | #include <linux/module.h> | |
448353ca | 33 | #include <linux/swap.h> |
05da4558 | 34 | #include <linux/hugetlb.h> |
2f333bcb | 35 | #include <linux/compiler.h> |
bc6678a3 | 36 | #include <linux/srcu.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
bf998156 | 38 | #include <linux/uaccess.h> |
6aa8b732 | 39 | |
e495606d AK |
40 | #include <asm/page.h> |
41 | #include <asm/cmpxchg.h> | |
4e542370 | 42 | #include <asm/io.h> |
13673a90 | 43 | #include <asm/vmx.h> |
6aa8b732 | 44 | |
18552672 JR |
45 | /* |
46 | * When setting this variable to true it enables Two-Dimensional-Paging | |
47 | * where the hardware walks 2 page tables: | |
48 | * 1. the guest-virtual to guest-physical | |
49 | * 2. while doing 1. it walks guest-physical to host-physical | |
50 | * If the hardware supports that we don't need to do shadow paging. | |
51 | */ | |
2f333bcb | 52 | bool tdp_enabled = false; |
18552672 | 53 | |
8b1fe17c XG |
54 | enum { |
55 | AUDIT_PRE_PAGE_FAULT, | |
56 | AUDIT_POST_PAGE_FAULT, | |
57 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
58 | AUDIT_POST_PTE_WRITE, |
59 | AUDIT_PRE_SYNC, | |
60 | AUDIT_POST_SYNC | |
8b1fe17c | 61 | }; |
37a7d8b0 | 62 | |
8b1fe17c XG |
63 | char *audit_point_name[] = { |
64 | "pre page fault", | |
65 | "post page fault", | |
66 | "pre pte write", | |
6903074c XG |
67 | "post pte write", |
68 | "pre sync", | |
69 | "post sync" | |
8b1fe17c | 70 | }; |
37a7d8b0 | 71 | |
8b1fe17c | 72 | #undef MMU_DEBUG |
37a7d8b0 AK |
73 | |
74 | #ifdef MMU_DEBUG | |
75 | ||
76 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
77 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
78 | ||
79 | #else | |
80 | ||
81 | #define pgprintk(x...) do { } while (0) | |
82 | #define rmap_printk(x...) do { } while (0) | |
83 | ||
84 | #endif | |
85 | ||
8b1fe17c | 86 | #ifdef MMU_DEBUG |
6ada8cca AK |
87 | static int dbg = 0; |
88 | module_param(dbg, bool, 0644); | |
37a7d8b0 | 89 | #endif |
6aa8b732 | 90 | |
582801a9 MT |
91 | static int oos_shadow = 1; |
92 | module_param(oos_shadow, bool, 0644); | |
93 | ||
d6c69ee9 YD |
94 | #ifndef MMU_DEBUG |
95 | #define ASSERT(x) do { } while (0) | |
96 | #else | |
6aa8b732 AK |
97 | #define ASSERT(x) \ |
98 | if (!(x)) { \ | |
99 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
100 | __FILE__, __LINE__, #x); \ | |
101 | } | |
d6c69ee9 | 102 | #endif |
6aa8b732 | 103 | |
957ed9ef XG |
104 | #define PTE_PREFETCH_NUM 8 |
105 | ||
6aa8b732 AK |
106 | #define PT_FIRST_AVAIL_BITS_SHIFT 9 |
107 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 | |
108 | ||
6aa8b732 AK |
109 | #define PT64_LEVEL_BITS 9 |
110 | ||
111 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 112 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 113 | |
6aa8b732 AK |
114 | #define PT64_INDEX(address, level)\ |
115 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
116 | ||
117 | ||
118 | #define PT32_LEVEL_BITS 10 | |
119 | ||
120 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 121 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 122 | |
e04da980 JR |
123 | #define PT32_LVL_OFFSET_MASK(level) \ |
124 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
125 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
126 | |
127 | #define PT32_INDEX(address, level)\ | |
128 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
129 | ||
130 | ||
27aba766 | 131 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
132 | #define PT64_DIR_BASE_ADDR_MASK \ |
133 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
134 | #define PT64_LVL_ADDR_MASK(level) \ |
135 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
136 | * PT64_LEVEL_BITS))) - 1)) | |
137 | #define PT64_LVL_OFFSET_MASK(level) \ | |
138 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
139 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
140 | |
141 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
142 | #define PT32_DIR_BASE_ADDR_MASK \ | |
143 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
144 | #define PT32_LVL_ADDR_MASK(level) \ |
145 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
146 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 147 | |
79539cec AK |
148 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
149 | | PT64_NX_MASK) | |
6aa8b732 | 150 | |
53c07b18 | 151 | #define PTE_LIST_EXT 4 |
cd4a4e53 | 152 | |
fe135d2c AK |
153 | #define ACC_EXEC_MASK 1 |
154 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
155 | #define ACC_USER_MASK PT_USER_MASK | |
156 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
157 | ||
90bb6fc5 AK |
158 | #include <trace/events/kvm.h> |
159 | ||
07420171 AK |
160 | #define CREATE_TRACE_POINTS |
161 | #include "mmutrace.h" | |
162 | ||
1403283a IE |
163 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
164 | ||
135f8c2b AK |
165 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
166 | ||
53c07b18 XG |
167 | struct pte_list_desc { |
168 | u64 *sptes[PTE_LIST_EXT]; | |
169 | struct pte_list_desc *more; | |
cd4a4e53 AK |
170 | }; |
171 | ||
2d11123a AK |
172 | struct kvm_shadow_walk_iterator { |
173 | u64 addr; | |
174 | hpa_t shadow_addr; | |
175 | int level; | |
176 | u64 *sptep; | |
177 | unsigned index; | |
178 | }; | |
179 | ||
180 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
181 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
182 | shadow_walk_okay(&(_walker)); \ | |
183 | shadow_walk_next(&(_walker))) | |
184 | ||
c2a2ac2b XG |
185 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
186 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
187 | shadow_walk_okay(&(_walker)) && \ | |
188 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
189 | __shadow_walk_next(&(_walker), spte)) | |
190 | ||
53c07b18 | 191 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 192 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 193 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 194 | |
7b52345e SY |
195 | static u64 __read_mostly shadow_nx_mask; |
196 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
197 | static u64 __read_mostly shadow_user_mask; | |
198 | static u64 __read_mostly shadow_accessed_mask; | |
199 | static u64 __read_mostly shadow_dirty_mask; | |
c7addb90 | 200 | |
82725b20 DE |
201 | static inline u64 rsvd_bits(int s, int e) |
202 | { | |
203 | return ((1ULL << (e - s + 1)) - 1) << s; | |
204 | } | |
205 | ||
7b52345e | 206 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 207 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
208 | { |
209 | shadow_user_mask = user_mask; | |
210 | shadow_accessed_mask = accessed_mask; | |
211 | shadow_dirty_mask = dirty_mask; | |
212 | shadow_nx_mask = nx_mask; | |
213 | shadow_x_mask = x_mask; | |
214 | } | |
215 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
216 | ||
6aa8b732 AK |
217 | static int is_cpuid_PSE36(void) |
218 | { | |
219 | return 1; | |
220 | } | |
221 | ||
73b1087e AK |
222 | static int is_nx(struct kvm_vcpu *vcpu) |
223 | { | |
f6801dff | 224 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
225 | } |
226 | ||
c7addb90 AK |
227 | static int is_shadow_present_pte(u64 pte) |
228 | { | |
c3707958 | 229 | return pte & PT_PRESENT_MASK; |
c7addb90 AK |
230 | } |
231 | ||
05da4558 MT |
232 | static int is_large_pte(u64 pte) |
233 | { | |
234 | return pte & PT_PAGE_SIZE_MASK; | |
235 | } | |
236 | ||
43a3795a | 237 | static int is_dirty_gpte(unsigned long pte) |
e3c5e7ec | 238 | { |
439e218a | 239 | return pte & PT_DIRTY_MASK; |
e3c5e7ec AK |
240 | } |
241 | ||
43a3795a | 242 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 243 | { |
4b1a80fa | 244 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
245 | } |
246 | ||
776e6633 MT |
247 | static int is_last_spte(u64 pte, int level) |
248 | { | |
249 | if (level == PT_PAGE_TABLE_LEVEL) | |
250 | return 1; | |
852e3c19 | 251 | if (is_large_pte(pte)) |
776e6633 MT |
252 | return 1; |
253 | return 0; | |
254 | } | |
255 | ||
35149e21 | 256 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 257 | { |
35149e21 | 258 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
259 | } |
260 | ||
da928521 AK |
261 | static gfn_t pse36_gfn_delta(u32 gpte) |
262 | { | |
263 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
264 | ||
265 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
266 | } | |
267 | ||
603e0651 | 268 | #ifdef CONFIG_X86_64 |
d555c333 | 269 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 270 | { |
603e0651 | 271 | *sptep = spte; |
e663ee64 AK |
272 | } |
273 | ||
603e0651 | 274 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 275 | { |
603e0651 XG |
276 | *sptep = spte; |
277 | } | |
278 | ||
279 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
280 | { | |
281 | return xchg(sptep, spte); | |
282 | } | |
c2a2ac2b XG |
283 | |
284 | static u64 __get_spte_lockless(u64 *sptep) | |
285 | { | |
286 | return ACCESS_ONCE(*sptep); | |
287 | } | |
a9221dd5 | 288 | #else |
603e0651 XG |
289 | union split_spte { |
290 | struct { | |
291 | u32 spte_low; | |
292 | u32 spte_high; | |
293 | }; | |
294 | u64 spte; | |
295 | }; | |
a9221dd5 | 296 | |
c2a2ac2b XG |
297 | static void count_spte_clear(u64 *sptep, u64 spte) |
298 | { | |
299 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
300 | ||
301 | if (is_shadow_present_pte(spte)) | |
302 | return; | |
303 | ||
304 | /* Ensure the spte is completely set before we increase the count */ | |
305 | smp_wmb(); | |
306 | sp->clear_spte_count++; | |
307 | } | |
308 | ||
603e0651 XG |
309 | static void __set_spte(u64 *sptep, u64 spte) |
310 | { | |
311 | union split_spte *ssptep, sspte; | |
a9221dd5 | 312 | |
603e0651 XG |
313 | ssptep = (union split_spte *)sptep; |
314 | sspte = (union split_spte)spte; | |
315 | ||
316 | ssptep->spte_high = sspte.spte_high; | |
317 | ||
318 | /* | |
319 | * If we map the spte from nonpresent to present, We should store | |
320 | * the high bits firstly, then set present bit, so cpu can not | |
321 | * fetch this spte while we are setting the spte. | |
322 | */ | |
323 | smp_wmb(); | |
324 | ||
325 | ssptep->spte_low = sspte.spte_low; | |
a9221dd5 AK |
326 | } |
327 | ||
603e0651 XG |
328 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
329 | { | |
330 | union split_spte *ssptep, sspte; | |
331 | ||
332 | ssptep = (union split_spte *)sptep; | |
333 | sspte = (union split_spte)spte; | |
334 | ||
335 | ssptep->spte_low = sspte.spte_low; | |
336 | ||
337 | /* | |
338 | * If we map the spte from present to nonpresent, we should clear | |
339 | * present bit firstly to avoid vcpu fetch the old high bits. | |
340 | */ | |
341 | smp_wmb(); | |
342 | ||
343 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 344 | count_spte_clear(sptep, spte); |
603e0651 XG |
345 | } |
346 | ||
347 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
348 | { | |
349 | union split_spte *ssptep, sspte, orig; | |
350 | ||
351 | ssptep = (union split_spte *)sptep; | |
352 | sspte = (union split_spte)spte; | |
353 | ||
354 | /* xchg acts as a barrier before the setting of the high bits */ | |
355 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
356 | orig.spte_high = ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 357 | count_spte_clear(sptep, spte); |
603e0651 XG |
358 | |
359 | return orig.spte; | |
360 | } | |
c2a2ac2b XG |
361 | |
362 | /* | |
363 | * The idea using the light way get the spte on x86_32 guest is from | |
364 | * gup_get_pte(arch/x86/mm/gup.c). | |
365 | * The difference is we can not catch the spte tlb flush if we leave | |
366 | * guest mode, so we emulate it by increase clear_spte_count when spte | |
367 | * is cleared. | |
368 | */ | |
369 | static u64 __get_spte_lockless(u64 *sptep) | |
370 | { | |
371 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
372 | union split_spte spte, *orig = (union split_spte *)sptep; | |
373 | int count; | |
374 | ||
375 | retry: | |
376 | count = sp->clear_spte_count; | |
377 | smp_rmb(); | |
378 | ||
379 | spte.spte_low = orig->spte_low; | |
380 | smp_rmb(); | |
381 | ||
382 | spte.spte_high = orig->spte_high; | |
383 | smp_rmb(); | |
384 | ||
385 | if (unlikely(spte.spte_low != orig->spte_low || | |
386 | count != sp->clear_spte_count)) | |
387 | goto retry; | |
388 | ||
389 | return spte.spte; | |
390 | } | |
603e0651 XG |
391 | #endif |
392 | ||
8672b721 XG |
393 | static bool spte_has_volatile_bits(u64 spte) |
394 | { | |
395 | if (!shadow_accessed_mask) | |
396 | return false; | |
397 | ||
398 | if (!is_shadow_present_pte(spte)) | |
399 | return false; | |
400 | ||
4132779b XG |
401 | if ((spte & shadow_accessed_mask) && |
402 | (!is_writable_pte(spte) || (spte & shadow_dirty_mask))) | |
8672b721 XG |
403 | return false; |
404 | ||
405 | return true; | |
406 | } | |
407 | ||
4132779b XG |
408 | static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask) |
409 | { | |
410 | return (old_spte & bit_mask) && !(new_spte & bit_mask); | |
411 | } | |
412 | ||
1df9f2dc XG |
413 | /* Rules for using mmu_spte_set: |
414 | * Set the sptep from nonpresent to present. | |
415 | * Note: the sptep being assigned *must* be either not present | |
416 | * or in a state where the hardware will not attempt to update | |
417 | * the spte. | |
418 | */ | |
419 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
420 | { | |
421 | WARN_ON(is_shadow_present_pte(*sptep)); | |
422 | __set_spte(sptep, new_spte); | |
423 | } | |
424 | ||
425 | /* Rules for using mmu_spte_update: | |
426 | * Update the state bits, it means the mapped pfn is not changged. | |
427 | */ | |
428 | static void mmu_spte_update(u64 *sptep, u64 new_spte) | |
b79b93f9 | 429 | { |
4132779b XG |
430 | u64 mask, old_spte = *sptep; |
431 | ||
432 | WARN_ON(!is_rmap_spte(new_spte)); | |
b79b93f9 | 433 | |
1df9f2dc XG |
434 | if (!is_shadow_present_pte(old_spte)) |
435 | return mmu_spte_set(sptep, new_spte); | |
436 | ||
4132779b XG |
437 | new_spte |= old_spte & shadow_dirty_mask; |
438 | ||
439 | mask = shadow_accessed_mask; | |
440 | if (is_writable_pte(old_spte)) | |
441 | mask |= shadow_dirty_mask; | |
442 | ||
443 | if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask) | |
603e0651 | 444 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 445 | else |
603e0651 | 446 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b XG |
447 | |
448 | if (!shadow_accessed_mask) | |
449 | return; | |
450 | ||
451 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask)) | |
452 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); | |
453 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask)) | |
454 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); | |
b79b93f9 AK |
455 | } |
456 | ||
1df9f2dc XG |
457 | /* |
458 | * Rules for using mmu_spte_clear_track_bits: | |
459 | * It sets the sptep from present to nonpresent, and track the | |
460 | * state bits, it is used to clear the last level sptep. | |
461 | */ | |
462 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
463 | { | |
464 | pfn_t pfn; | |
465 | u64 old_spte = *sptep; | |
466 | ||
467 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 468 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 469 | else |
603e0651 | 470 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc XG |
471 | |
472 | if (!is_rmap_spte(old_spte)) | |
473 | return 0; | |
474 | ||
475 | pfn = spte_to_pfn(old_spte); | |
476 | if (!shadow_accessed_mask || old_spte & shadow_accessed_mask) | |
477 | kvm_set_pfn_accessed(pfn); | |
478 | if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask)) | |
479 | kvm_set_pfn_dirty(pfn); | |
480 | return 1; | |
481 | } | |
482 | ||
483 | /* | |
484 | * Rules for using mmu_spte_clear_no_track: | |
485 | * Directly clear spte without caring the state bits of sptep, | |
486 | * it is used to set the upper level spte. | |
487 | */ | |
488 | static void mmu_spte_clear_no_track(u64 *sptep) | |
489 | { | |
603e0651 | 490 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
491 | } |
492 | ||
c2a2ac2b XG |
493 | static u64 mmu_spte_get_lockless(u64 *sptep) |
494 | { | |
495 | return __get_spte_lockless(sptep); | |
496 | } | |
497 | ||
498 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) | |
499 | { | |
500 | rcu_read_lock(); | |
501 | atomic_inc(&vcpu->kvm->arch.reader_counter); | |
502 | ||
503 | /* Increase the counter before walking shadow page table */ | |
504 | smp_mb__after_atomic_inc(); | |
505 | } | |
506 | ||
507 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
508 | { | |
509 | /* Decrease the counter after walking shadow page table finished */ | |
510 | smp_mb__before_atomic_dec(); | |
511 | atomic_dec(&vcpu->kvm->arch.reader_counter); | |
512 | rcu_read_unlock(); | |
513 | } | |
514 | ||
e2dec939 | 515 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 516 | struct kmem_cache *base_cache, int min) |
714b93da AK |
517 | { |
518 | void *obj; | |
519 | ||
520 | if (cache->nobjs >= min) | |
e2dec939 | 521 | return 0; |
714b93da | 522 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 523 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 524 | if (!obj) |
e2dec939 | 525 | return -ENOMEM; |
714b93da AK |
526 | cache->objects[cache->nobjs++] = obj; |
527 | } | |
e2dec939 | 528 | return 0; |
714b93da AK |
529 | } |
530 | ||
e8ad9a70 XG |
531 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
532 | struct kmem_cache *cache) | |
714b93da AK |
533 | { |
534 | while (mc->nobjs) | |
e8ad9a70 | 535 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
536 | } |
537 | ||
c1158e63 | 538 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 539 | int min) |
c1158e63 | 540 | { |
842f22ed | 541 | void *page; |
c1158e63 AK |
542 | |
543 | if (cache->nobjs >= min) | |
544 | return 0; | |
545 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
842f22ed | 546 | page = (void *)__get_free_page(GFP_KERNEL); |
c1158e63 AK |
547 | if (!page) |
548 | return -ENOMEM; | |
842f22ed | 549 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
550 | } |
551 | return 0; | |
552 | } | |
553 | ||
554 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
555 | { | |
556 | while (mc->nobjs) | |
c4d198d5 | 557 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
558 | } |
559 | ||
2e3e5882 | 560 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 561 | { |
e2dec939 AK |
562 | int r; |
563 | ||
53c07b18 | 564 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 565 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
566 | if (r) |
567 | goto out; | |
ad312c7c | 568 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
569 | if (r) |
570 | goto out; | |
ad312c7c | 571 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 572 | mmu_page_header_cache, 4); |
e2dec939 AK |
573 | out: |
574 | return r; | |
714b93da AK |
575 | } |
576 | ||
577 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
578 | { | |
53c07b18 XG |
579 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
580 | pte_list_desc_cache); | |
ad312c7c | 581 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
582 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
583 | mmu_page_header_cache); | |
714b93da AK |
584 | } |
585 | ||
586 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc, | |
587 | size_t size) | |
588 | { | |
589 | void *p; | |
590 | ||
591 | BUG_ON(!mc->nobjs); | |
592 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
593 | return p; |
594 | } | |
595 | ||
53c07b18 | 596 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 597 | { |
53c07b18 XG |
598 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache, |
599 | sizeof(struct pte_list_desc)); | |
714b93da AK |
600 | } |
601 | ||
53c07b18 | 602 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 603 | { |
53c07b18 | 604 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
605 | } |
606 | ||
2032a93d LJ |
607 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
608 | { | |
609 | if (!sp->role.direct) | |
610 | return sp->gfns[index]; | |
611 | ||
612 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
613 | } | |
614 | ||
615 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
616 | { | |
617 | if (sp->role.direct) | |
618 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
619 | else | |
620 | sp->gfns[index] = gfn; | |
621 | } | |
622 | ||
05da4558 | 623 | /* |
d4dbf470 TY |
624 | * Return the pointer to the large page information for a given gfn, |
625 | * handling slots that are not large page aligned. | |
05da4558 | 626 | */ |
d4dbf470 TY |
627 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
628 | struct kvm_memory_slot *slot, | |
629 | int level) | |
05da4558 MT |
630 | { |
631 | unsigned long idx; | |
632 | ||
82855413 JR |
633 | idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - |
634 | (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
d4dbf470 | 635 | return &slot->lpage_info[level - 2][idx]; |
05da4558 MT |
636 | } |
637 | ||
638 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
639 | { | |
d25797b2 | 640 | struct kvm_memory_slot *slot; |
d4dbf470 | 641 | struct kvm_lpage_info *linfo; |
d25797b2 | 642 | int i; |
05da4558 | 643 | |
a1f4d395 | 644 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
645 | for (i = PT_DIRECTORY_LEVEL; |
646 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
647 | linfo = lpage_info_slot(gfn, slot, i); |
648 | linfo->write_count += 1; | |
d25797b2 | 649 | } |
332b207d | 650 | kvm->arch.indirect_shadow_pages++; |
05da4558 MT |
651 | } |
652 | ||
653 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
654 | { | |
d25797b2 | 655 | struct kvm_memory_slot *slot; |
d4dbf470 | 656 | struct kvm_lpage_info *linfo; |
d25797b2 | 657 | int i; |
05da4558 | 658 | |
a1f4d395 | 659 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
660 | for (i = PT_DIRECTORY_LEVEL; |
661 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
662 | linfo = lpage_info_slot(gfn, slot, i); |
663 | linfo->write_count -= 1; | |
664 | WARN_ON(linfo->write_count < 0); | |
d25797b2 | 665 | } |
332b207d | 666 | kvm->arch.indirect_shadow_pages--; |
05da4558 MT |
667 | } |
668 | ||
d25797b2 JR |
669 | static int has_wrprotected_page(struct kvm *kvm, |
670 | gfn_t gfn, | |
671 | int level) | |
05da4558 | 672 | { |
2843099f | 673 | struct kvm_memory_slot *slot; |
d4dbf470 | 674 | struct kvm_lpage_info *linfo; |
05da4558 | 675 | |
a1f4d395 | 676 | slot = gfn_to_memslot(kvm, gfn); |
05da4558 | 677 | if (slot) { |
d4dbf470 TY |
678 | linfo = lpage_info_slot(gfn, slot, level); |
679 | return linfo->write_count; | |
05da4558 MT |
680 | } |
681 | ||
682 | return 1; | |
683 | } | |
684 | ||
d25797b2 | 685 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 686 | { |
8f0b1ab6 | 687 | unsigned long page_size; |
d25797b2 | 688 | int i, ret = 0; |
05da4558 | 689 | |
8f0b1ab6 | 690 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 691 | |
d25797b2 JR |
692 | for (i = PT_PAGE_TABLE_LEVEL; |
693 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
694 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
695 | ret = i; | |
696 | else | |
697 | break; | |
698 | } | |
699 | ||
4c2155ce | 700 | return ret; |
05da4558 MT |
701 | } |
702 | ||
5d163b1c XG |
703 | static struct kvm_memory_slot * |
704 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
705 | bool no_dirty_log) | |
05da4558 MT |
706 | { |
707 | struct kvm_memory_slot *slot; | |
5d163b1c XG |
708 | |
709 | slot = gfn_to_memslot(vcpu->kvm, gfn); | |
710 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID || | |
711 | (no_dirty_log && slot->dirty_bitmap)) | |
712 | slot = NULL; | |
713 | ||
714 | return slot; | |
715 | } | |
716 | ||
717 | static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
718 | { | |
a0a8eaba | 719 | return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true); |
936a5fe6 AA |
720 | } |
721 | ||
722 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
723 | { | |
724 | int host_level, level, max_level; | |
05da4558 | 725 | |
d25797b2 JR |
726 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
727 | ||
728 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
729 | return host_level; | |
730 | ||
878403b7 SY |
731 | max_level = kvm_x86_ops->get_lpage_level() < host_level ? |
732 | kvm_x86_ops->get_lpage_level() : host_level; | |
733 | ||
734 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
735 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
736 | break; | |
d25797b2 JR |
737 | |
738 | return level - 1; | |
05da4558 MT |
739 | } |
740 | ||
290fc38d | 741 | /* |
53c07b18 | 742 | * Pte mapping structures: |
cd4a4e53 | 743 | * |
53c07b18 | 744 | * If pte_list bit zero is zero, then pte_list point to the spte. |
cd4a4e53 | 745 | * |
53c07b18 XG |
746 | * If pte_list bit zero is one, (then pte_list & ~1) points to a struct |
747 | * pte_list_desc containing more mappings. | |
53a27b39 | 748 | * |
53c07b18 | 749 | * Returns the number of pte entries before the spte was added or zero if |
53a27b39 MT |
750 | * the spte was not added. |
751 | * | |
cd4a4e53 | 752 | */ |
53c07b18 XG |
753 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
754 | unsigned long *pte_list) | |
cd4a4e53 | 755 | { |
53c07b18 | 756 | struct pte_list_desc *desc; |
53a27b39 | 757 | int i, count = 0; |
cd4a4e53 | 758 | |
53c07b18 XG |
759 | if (!*pte_list) { |
760 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); | |
761 | *pte_list = (unsigned long)spte; | |
762 | } else if (!(*pte_list & 1)) { | |
763 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); | |
764 | desc = mmu_alloc_pte_list_desc(vcpu); | |
765 | desc->sptes[0] = (u64 *)*pte_list; | |
d555c333 | 766 | desc->sptes[1] = spte; |
53c07b18 | 767 | *pte_list = (unsigned long)desc | 1; |
cb16a7b3 | 768 | ++count; |
cd4a4e53 | 769 | } else { |
53c07b18 XG |
770 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
771 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
772 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { | |
cd4a4e53 | 773 | desc = desc->more; |
53c07b18 | 774 | count += PTE_LIST_EXT; |
53a27b39 | 775 | } |
53c07b18 XG |
776 | if (desc->sptes[PTE_LIST_EXT-1]) { |
777 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
778 | desc = desc->more; |
779 | } | |
d555c333 | 780 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 781 | ++count; |
d555c333 | 782 | desc->sptes[i] = spte; |
cd4a4e53 | 783 | } |
53a27b39 | 784 | return count; |
cd4a4e53 AK |
785 | } |
786 | ||
53c07b18 XG |
787 | static u64 *pte_list_next(unsigned long *pte_list, u64 *spte) |
788 | { | |
789 | struct pte_list_desc *desc; | |
790 | u64 *prev_spte; | |
791 | int i; | |
792 | ||
793 | if (!*pte_list) | |
794 | return NULL; | |
795 | else if (!(*pte_list & 1)) { | |
796 | if (!spte) | |
797 | return (u64 *)*pte_list; | |
798 | return NULL; | |
799 | } | |
800 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
801 | prev_spte = NULL; | |
802 | while (desc) { | |
803 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) { | |
804 | if (prev_spte == spte) | |
805 | return desc->sptes[i]; | |
806 | prev_spte = desc->sptes[i]; | |
807 | } | |
808 | desc = desc->more; | |
809 | } | |
810 | return NULL; | |
811 | } | |
812 | ||
813 | static void | |
814 | pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc, | |
815 | int i, struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
816 | { |
817 | int j; | |
818 | ||
53c07b18 | 819 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 820 | ; |
d555c333 AK |
821 | desc->sptes[i] = desc->sptes[j]; |
822 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
823 | if (j != 0) |
824 | return; | |
825 | if (!prev_desc && !desc->more) | |
53c07b18 | 826 | *pte_list = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
827 | else |
828 | if (prev_desc) | |
829 | prev_desc->more = desc->more; | |
830 | else | |
53c07b18 XG |
831 | *pte_list = (unsigned long)desc->more | 1; |
832 | mmu_free_pte_list_desc(desc); | |
cd4a4e53 AK |
833 | } |
834 | ||
53c07b18 | 835 | static void pte_list_remove(u64 *spte, unsigned long *pte_list) |
cd4a4e53 | 836 | { |
53c07b18 XG |
837 | struct pte_list_desc *desc; |
838 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
839 | int i; |
840 | ||
53c07b18 XG |
841 | if (!*pte_list) { |
842 | printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte); | |
cd4a4e53 | 843 | BUG(); |
53c07b18 XG |
844 | } else if (!(*pte_list & 1)) { |
845 | rmap_printk("pte_list_remove: %p 1->0\n", spte); | |
846 | if ((u64 *)*pte_list != spte) { | |
847 | printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte); | |
cd4a4e53 AK |
848 | BUG(); |
849 | } | |
53c07b18 | 850 | *pte_list = 0; |
cd4a4e53 | 851 | } else { |
53c07b18 XG |
852 | rmap_printk("pte_list_remove: %p many->many\n", spte); |
853 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
cd4a4e53 AK |
854 | prev_desc = NULL; |
855 | while (desc) { | |
53c07b18 | 856 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) |
d555c333 | 857 | if (desc->sptes[i] == spte) { |
53c07b18 | 858 | pte_list_desc_remove_entry(pte_list, |
714b93da | 859 | desc, i, |
cd4a4e53 AK |
860 | prev_desc); |
861 | return; | |
862 | } | |
863 | prev_desc = desc; | |
864 | desc = desc->more; | |
865 | } | |
53c07b18 | 866 | pr_err("pte_list_remove: %p many->many\n", spte); |
cd4a4e53 AK |
867 | BUG(); |
868 | } | |
869 | } | |
870 | ||
67052b35 XG |
871 | typedef void (*pte_list_walk_fn) (u64 *spte); |
872 | static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn) | |
873 | { | |
874 | struct pte_list_desc *desc; | |
875 | int i; | |
876 | ||
877 | if (!*pte_list) | |
878 | return; | |
879 | ||
880 | if (!(*pte_list & 1)) | |
881 | return fn((u64 *)*pte_list); | |
882 | ||
883 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
884 | while (desc) { | |
885 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) | |
886 | fn(desc->sptes[i]); | |
887 | desc = desc->more; | |
888 | } | |
889 | } | |
890 | ||
53c07b18 XG |
891 | /* |
892 | * Take gfn and return the reverse mapping to it. | |
893 | */ | |
894 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) | |
895 | { | |
896 | struct kvm_memory_slot *slot; | |
897 | struct kvm_lpage_info *linfo; | |
898 | ||
899 | slot = gfn_to_memslot(kvm, gfn); | |
900 | if (likely(level == PT_PAGE_TABLE_LEVEL)) | |
901 | return &slot->rmap[gfn - slot->base_gfn]; | |
902 | ||
903 | linfo = lpage_info_slot(gfn, slot, level); | |
904 | ||
905 | return &linfo->rmap_pde; | |
906 | } | |
907 | ||
908 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) | |
909 | { | |
910 | struct kvm_mmu_page *sp; | |
911 | unsigned long *rmapp; | |
912 | ||
53c07b18 XG |
913 | sp = page_header(__pa(spte)); |
914 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
915 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); | |
916 | return pte_list_add(vcpu, spte, rmapp); | |
917 | } | |
918 | ||
919 | static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte) | |
920 | { | |
921 | return pte_list_next(rmapp, spte); | |
922 | } | |
923 | ||
924 | static void rmap_remove(struct kvm *kvm, u64 *spte) | |
925 | { | |
926 | struct kvm_mmu_page *sp; | |
927 | gfn_t gfn; | |
928 | unsigned long *rmapp; | |
929 | ||
930 | sp = page_header(__pa(spte)); | |
931 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
932 | rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); | |
933 | pte_list_remove(spte, rmapp); | |
934 | } | |
935 | ||
c3707958 | 936 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 937 | { |
1df9f2dc | 938 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 939 | rmap_remove(kvm, sptep); |
be38d276 AK |
940 | } |
941 | ||
b1a36821 | 942 | static int rmap_write_protect(struct kvm *kvm, u64 gfn) |
98348e95 | 943 | { |
290fc38d | 944 | unsigned long *rmapp; |
374cbac0 | 945 | u64 *spte; |
44ad9944 | 946 | int i, write_protected = 0; |
374cbac0 | 947 | |
44ad9944 | 948 | rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL); |
374cbac0 | 949 | |
98348e95 IE |
950 | spte = rmap_next(kvm, rmapp, NULL); |
951 | while (spte) { | |
374cbac0 | 952 | BUG_ON(!spte); |
374cbac0 | 953 | BUG_ON(!(*spte & PT_PRESENT_MASK)); |
374cbac0 | 954 | rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte); |
8dae4445 | 955 | if (is_writable_pte(*spte)) { |
1df9f2dc | 956 | mmu_spte_update(spte, *spte & ~PT_WRITABLE_MASK); |
caa5b8a5 ED |
957 | write_protected = 1; |
958 | } | |
9647c14c | 959 | spte = rmap_next(kvm, rmapp, spte); |
374cbac0 | 960 | } |
855149aa | 961 | |
05da4558 | 962 | /* check for huge page mappings */ |
44ad9944 JR |
963 | for (i = PT_DIRECTORY_LEVEL; |
964 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
965 | rmapp = gfn_to_rmap(kvm, gfn, i); | |
966 | spte = rmap_next(kvm, rmapp, NULL); | |
967 | while (spte) { | |
968 | BUG_ON(!spte); | |
969 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
970 | BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)); | |
971 | pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn); | |
8dae4445 | 972 | if (is_writable_pte(*spte)) { |
c3707958 | 973 | drop_spte(kvm, spte); |
44ad9944 | 974 | --kvm->stat.lpages; |
44ad9944 JR |
975 | spte = NULL; |
976 | write_protected = 1; | |
977 | } | |
978 | spte = rmap_next(kvm, rmapp, spte); | |
05da4558 | 979 | } |
05da4558 MT |
980 | } |
981 | ||
b1a36821 | 982 | return write_protected; |
374cbac0 AK |
983 | } |
984 | ||
8a8365c5 FD |
985 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
986 | unsigned long data) | |
e930bffe AA |
987 | { |
988 | u64 *spte; | |
989 | int need_tlb_flush = 0; | |
990 | ||
991 | while ((spte = rmap_next(kvm, rmapp, NULL))) { | |
992 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
993 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte); | |
c3707958 | 994 | drop_spte(kvm, spte); |
e930bffe AA |
995 | need_tlb_flush = 1; |
996 | } | |
997 | return need_tlb_flush; | |
998 | } | |
999 | ||
8a8365c5 FD |
1000 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
1001 | unsigned long data) | |
3da0dd43 IE |
1002 | { |
1003 | int need_flush = 0; | |
e4b502ea | 1004 | u64 *spte, new_spte; |
3da0dd43 IE |
1005 | pte_t *ptep = (pte_t *)data; |
1006 | pfn_t new_pfn; | |
1007 | ||
1008 | WARN_ON(pte_huge(*ptep)); | |
1009 | new_pfn = pte_pfn(*ptep); | |
1010 | spte = rmap_next(kvm, rmapp, NULL); | |
1011 | while (spte) { | |
1012 | BUG_ON(!is_shadow_present_pte(*spte)); | |
1013 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte); | |
1014 | need_flush = 1; | |
1015 | if (pte_write(*ptep)) { | |
c3707958 | 1016 | drop_spte(kvm, spte); |
3da0dd43 IE |
1017 | spte = rmap_next(kvm, rmapp, NULL); |
1018 | } else { | |
1019 | new_spte = *spte &~ (PT64_BASE_ADDR_MASK); | |
1020 | new_spte |= (u64)new_pfn << PAGE_SHIFT; | |
1021 | ||
1022 | new_spte &= ~PT_WRITABLE_MASK; | |
1023 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 1024 | new_spte &= ~shadow_accessed_mask; |
1df9f2dc XG |
1025 | mmu_spte_clear_track_bits(spte); |
1026 | mmu_spte_set(spte, new_spte); | |
3da0dd43 IE |
1027 | spte = rmap_next(kvm, rmapp, spte); |
1028 | } | |
1029 | } | |
1030 | if (need_flush) | |
1031 | kvm_flush_remote_tlbs(kvm); | |
1032 | ||
1033 | return 0; | |
1034 | } | |
1035 | ||
8a8365c5 FD |
1036 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1037 | unsigned long data, | |
3da0dd43 | 1038 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, |
8a8365c5 | 1039 | unsigned long data)) |
e930bffe | 1040 | { |
852e3c19 | 1041 | int i, j; |
90bb6fc5 | 1042 | int ret; |
e930bffe | 1043 | int retval = 0; |
bc6678a3 MT |
1044 | struct kvm_memslots *slots; |
1045 | ||
90d83dc3 | 1046 | slots = kvm_memslots(kvm); |
e930bffe | 1047 | |
46a26bf5 MT |
1048 | for (i = 0; i < slots->nmemslots; i++) { |
1049 | struct kvm_memory_slot *memslot = &slots->memslots[i]; | |
e930bffe AA |
1050 | unsigned long start = memslot->userspace_addr; |
1051 | unsigned long end; | |
1052 | ||
e930bffe AA |
1053 | end = start + (memslot->npages << PAGE_SHIFT); |
1054 | if (hva >= start && hva < end) { | |
1055 | gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT; | |
d4dbf470 | 1056 | gfn_t gfn = memslot->base_gfn + gfn_offset; |
852e3c19 | 1057 | |
90bb6fc5 | 1058 | ret = handler(kvm, &memslot->rmap[gfn_offset], data); |
852e3c19 JR |
1059 | |
1060 | for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) { | |
d4dbf470 TY |
1061 | struct kvm_lpage_info *linfo; |
1062 | ||
1063 | linfo = lpage_info_slot(gfn, memslot, | |
1064 | PT_DIRECTORY_LEVEL + j); | |
1065 | ret |= handler(kvm, &linfo->rmap_pde, data); | |
852e3c19 | 1066 | } |
90bb6fc5 AK |
1067 | trace_kvm_age_page(hva, memslot, ret); |
1068 | retval |= ret; | |
e930bffe AA |
1069 | } |
1070 | } | |
1071 | ||
1072 | return retval; | |
1073 | } | |
1074 | ||
1075 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
1076 | { | |
3da0dd43 IE |
1077 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
1078 | } | |
1079 | ||
1080 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) | |
1081 | { | |
8a8365c5 | 1082 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1083 | } |
1084 | ||
8a8365c5 FD |
1085 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
1086 | unsigned long data) | |
e930bffe AA |
1087 | { |
1088 | u64 *spte; | |
1089 | int young = 0; | |
1090 | ||
6316e1c8 RR |
1091 | /* |
1092 | * Emulate the accessed bit for EPT, by checking if this page has | |
1093 | * an EPT mapping, and clearing it if it does. On the next access, | |
1094 | * a new EPT mapping will be established. | |
1095 | * This has some overhead, but not as much as the cost of swapping | |
1096 | * out actively used pages or breaking up actively used hugepages. | |
1097 | */ | |
534e38b4 | 1098 | if (!shadow_accessed_mask) |
6316e1c8 | 1099 | return kvm_unmap_rmapp(kvm, rmapp, data); |
534e38b4 | 1100 | |
e930bffe AA |
1101 | spte = rmap_next(kvm, rmapp, NULL); |
1102 | while (spte) { | |
1103 | int _young; | |
1104 | u64 _spte = *spte; | |
1105 | BUG_ON(!(_spte & PT_PRESENT_MASK)); | |
1106 | _young = _spte & PT_ACCESSED_MASK; | |
1107 | if (_young) { | |
1108 | young = 1; | |
1109 | clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
1110 | } | |
1111 | spte = rmap_next(kvm, rmapp, spte); | |
1112 | } | |
1113 | return young; | |
1114 | } | |
1115 | ||
8ee53820 AA |
1116 | static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
1117 | unsigned long data) | |
1118 | { | |
1119 | u64 *spte; | |
1120 | int young = 0; | |
1121 | ||
1122 | /* | |
1123 | * If there's no access bit in the secondary pte set by the | |
1124 | * hardware it's up to gup-fast/gup to set the access bit in | |
1125 | * the primary pte or in the page structure. | |
1126 | */ | |
1127 | if (!shadow_accessed_mask) | |
1128 | goto out; | |
1129 | ||
1130 | spte = rmap_next(kvm, rmapp, NULL); | |
1131 | while (spte) { | |
1132 | u64 _spte = *spte; | |
1133 | BUG_ON(!(_spte & PT_PRESENT_MASK)); | |
1134 | young = _spte & PT_ACCESSED_MASK; | |
1135 | if (young) { | |
1136 | young = 1; | |
1137 | break; | |
1138 | } | |
1139 | spte = rmap_next(kvm, rmapp, spte); | |
1140 | } | |
1141 | out: | |
1142 | return young; | |
1143 | } | |
1144 | ||
53a27b39 MT |
1145 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1146 | ||
852e3c19 | 1147 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
1148 | { |
1149 | unsigned long *rmapp; | |
852e3c19 JR |
1150 | struct kvm_mmu_page *sp; |
1151 | ||
1152 | sp = page_header(__pa(spte)); | |
53a27b39 | 1153 | |
852e3c19 | 1154 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 1155 | |
3da0dd43 | 1156 | kvm_unmap_rmapp(vcpu->kvm, rmapp, 0); |
53a27b39 MT |
1157 | kvm_flush_remote_tlbs(vcpu->kvm); |
1158 | } | |
1159 | ||
e930bffe AA |
1160 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
1161 | { | |
3da0dd43 | 1162 | return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp); |
e930bffe AA |
1163 | } |
1164 | ||
8ee53820 AA |
1165 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1166 | { | |
1167 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1168 | } | |
1169 | ||
d6c69ee9 | 1170 | #ifdef MMU_DEBUG |
47ad8e68 | 1171 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1172 | { |
139bdb2d AK |
1173 | u64 *pos; |
1174 | u64 *end; | |
1175 | ||
47ad8e68 | 1176 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1177 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1178 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1179 | pos, *pos); |
6aa8b732 | 1180 | return 0; |
139bdb2d | 1181 | } |
6aa8b732 AK |
1182 | return 1; |
1183 | } | |
d6c69ee9 | 1184 | #endif |
6aa8b732 | 1185 | |
45221ab6 DH |
1186 | /* |
1187 | * This value is the sum of all of the kvm instances's | |
1188 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1189 | * aggregate version in order to make the slab shrinker | |
1190 | * faster | |
1191 | */ | |
1192 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
1193 | { | |
1194 | kvm->arch.n_used_mmu_pages += nr; | |
1195 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1196 | } | |
1197 | ||
bd4c86ea XG |
1198 | /* |
1199 | * Remove the sp from shadow page cache, after call it, | |
1200 | * we can not find this sp from the cache, and the shadow | |
1201 | * page table is still valid. | |
1202 | * It should be under the protection of mmu lock. | |
1203 | */ | |
1204 | static void kvm_mmu_isolate_page(struct kvm_mmu_page *sp) | |
260746c0 | 1205 | { |
4db35314 | 1206 | ASSERT(is_empty_shadow_page(sp->spt)); |
7775834a | 1207 | hlist_del(&sp->hash_link); |
2032a93d | 1208 | if (!sp->role.direct) |
842f22ed | 1209 | free_page((unsigned long)sp->gfns); |
bd4c86ea XG |
1210 | } |
1211 | ||
1212 | /* | |
1213 | * Free the shadow page table and the sp, we can do it | |
1214 | * out of the protection of mmu lock. | |
1215 | */ | |
1216 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) | |
1217 | { | |
1218 | list_del(&sp->link); | |
1219 | free_page((unsigned long)sp->spt); | |
e8ad9a70 | 1220 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1221 | } |
1222 | ||
cea0f0e7 AK |
1223 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1224 | { | |
1ae0a13d | 1225 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
1226 | } |
1227 | ||
714b93da | 1228 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1229 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1230 | { |
cea0f0e7 AK |
1231 | if (!parent_pte) |
1232 | return; | |
cea0f0e7 | 1233 | |
67052b35 | 1234 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1235 | } |
1236 | ||
4db35314 | 1237 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1238 | u64 *parent_pte) |
1239 | { | |
67052b35 | 1240 | pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1241 | } |
1242 | ||
bcdd9a93 XG |
1243 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1244 | u64 *parent_pte) | |
1245 | { | |
1246 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1247 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1248 | } |
1249 | ||
67052b35 XG |
1250 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
1251 | u64 *parent_pte, int direct) | |
ad8cfbe3 | 1252 | { |
67052b35 XG |
1253 | struct kvm_mmu_page *sp; |
1254 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, | |
1255 | sizeof *sp); | |
1256 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE); | |
1257 | if (!direct) | |
1258 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, | |
1259 | PAGE_SIZE); | |
1260 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); | |
1261 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); | |
1262 | bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS); | |
1263 | sp->parent_ptes = 0; | |
1264 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); | |
1265 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); | |
1266 | return sp; | |
ad8cfbe3 MT |
1267 | } |
1268 | ||
67052b35 | 1269 | static void mark_unsync(u64 *spte); |
1047df1f | 1270 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1271 | { |
67052b35 | 1272 | pte_list_walk(&sp->parent_ptes, mark_unsync); |
0074ff63 MT |
1273 | } |
1274 | ||
67052b35 | 1275 | static void mark_unsync(u64 *spte) |
0074ff63 | 1276 | { |
67052b35 | 1277 | struct kvm_mmu_page *sp; |
1047df1f | 1278 | unsigned int index; |
0074ff63 | 1279 | |
67052b35 | 1280 | sp = page_header(__pa(spte)); |
1047df1f XG |
1281 | index = spte - sp->spt; |
1282 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1283 | return; |
1047df1f | 1284 | if (sp->unsync_children++) |
0074ff63 | 1285 | return; |
1047df1f | 1286 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1287 | } |
1288 | ||
e8bc217a | 1289 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1290 | struct kvm_mmu_page *sp) |
e8bc217a MT |
1291 | { |
1292 | return 1; | |
1293 | } | |
1294 | ||
a7052897 MT |
1295 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1296 | { | |
1297 | } | |
1298 | ||
0f53b5b1 XG |
1299 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1300 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 1301 | const void *pte) |
0f53b5b1 XG |
1302 | { |
1303 | WARN_ON(1); | |
1304 | } | |
1305 | ||
60c8aec6 MT |
1306 | #define KVM_PAGE_ARRAY_NR 16 |
1307 | ||
1308 | struct kvm_mmu_pages { | |
1309 | struct mmu_page_and_offset { | |
1310 | struct kvm_mmu_page *sp; | |
1311 | unsigned int idx; | |
1312 | } page[KVM_PAGE_ARRAY_NR]; | |
1313 | unsigned int nr; | |
1314 | }; | |
1315 | ||
0074ff63 MT |
1316 | #define for_each_unsync_children(bitmap, idx) \ |
1317 | for (idx = find_first_bit(bitmap, 512); \ | |
1318 | idx < 512; \ | |
1319 | idx = find_next_bit(bitmap, 512, idx+1)) | |
1320 | ||
cded19f3 HE |
1321 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1322 | int idx) | |
4731d4c7 | 1323 | { |
60c8aec6 | 1324 | int i; |
4731d4c7 | 1325 | |
60c8aec6 MT |
1326 | if (sp->unsync) |
1327 | for (i=0; i < pvec->nr; i++) | |
1328 | if (pvec->page[i].sp == sp) | |
1329 | return 0; | |
1330 | ||
1331 | pvec->page[pvec->nr].sp = sp; | |
1332 | pvec->page[pvec->nr].idx = idx; | |
1333 | pvec->nr++; | |
1334 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1335 | } | |
1336 | ||
1337 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1338 | struct kvm_mmu_pages *pvec) | |
1339 | { | |
1340 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1341 | |
0074ff63 | 1342 | for_each_unsync_children(sp->unsync_child_bitmap, i) { |
7a8f1a74 | 1343 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1344 | u64 ent = sp->spt[i]; |
1345 | ||
7a8f1a74 XG |
1346 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) |
1347 | goto clear_child_bitmap; | |
1348 | ||
1349 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1350 | ||
1351 | if (child->unsync_children) { | |
1352 | if (mmu_pages_add(pvec, child, i)) | |
1353 | return -ENOSPC; | |
1354 | ||
1355 | ret = __mmu_unsync_walk(child, pvec); | |
1356 | if (!ret) | |
1357 | goto clear_child_bitmap; | |
1358 | else if (ret > 0) | |
1359 | nr_unsync_leaf += ret; | |
1360 | else | |
1361 | return ret; | |
1362 | } else if (child->unsync) { | |
1363 | nr_unsync_leaf++; | |
1364 | if (mmu_pages_add(pvec, child, i)) | |
1365 | return -ENOSPC; | |
1366 | } else | |
1367 | goto clear_child_bitmap; | |
1368 | ||
1369 | continue; | |
1370 | ||
1371 | clear_child_bitmap: | |
1372 | __clear_bit(i, sp->unsync_child_bitmap); | |
1373 | sp->unsync_children--; | |
1374 | WARN_ON((int)sp->unsync_children < 0); | |
4731d4c7 MT |
1375 | } |
1376 | ||
4731d4c7 | 1377 | |
60c8aec6 MT |
1378 | return nr_unsync_leaf; |
1379 | } | |
1380 | ||
1381 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1382 | struct kvm_mmu_pages *pvec) | |
1383 | { | |
1384 | if (!sp->unsync_children) | |
1385 | return 0; | |
1386 | ||
1387 | mmu_pages_add(pvec, sp, 0); | |
1388 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1389 | } |
1390 | ||
4731d4c7 MT |
1391 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1392 | { | |
1393 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1394 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1395 | sp->unsync = 0; |
1396 | --kvm->stat.mmu_unsync; | |
1397 | } | |
1398 | ||
7775834a XG |
1399 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1400 | struct list_head *invalid_list); | |
1401 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1402 | struct list_head *invalid_list); | |
4731d4c7 | 1403 | |
f41d335a XG |
1404 | #define for_each_gfn_sp(kvm, sp, gfn, pos) \ |
1405 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1406 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1407 | if ((sp)->gfn != (gfn)) {} else | |
1408 | ||
f41d335a XG |
1409 | #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \ |
1410 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1411 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1412 | if ((sp)->gfn != (gfn) || (sp)->role.direct || \ | |
1413 | (sp)->role.invalid) {} else | |
1414 | ||
f918b443 | 1415 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1416 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1417 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1418 | { |
5b7e0102 | 1419 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1420 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1421 | return 1; |
1422 | } | |
1423 | ||
f918b443 | 1424 | if (clear_unsync) |
1d9dc7e0 | 1425 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1426 | |
a4a8e6f7 | 1427 | if (vcpu->arch.mmu.sync_page(vcpu, sp)) { |
d98ba053 | 1428 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1429 | return 1; |
1430 | } | |
1431 | ||
1432 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1433 | return 0; |
1434 | } | |
1435 | ||
1d9dc7e0 XG |
1436 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1437 | struct kvm_mmu_page *sp) | |
1438 | { | |
d98ba053 | 1439 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1440 | int ret; |
1441 | ||
d98ba053 | 1442 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1443 | if (ret) |
d98ba053 XG |
1444 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1445 | ||
1d9dc7e0 XG |
1446 | return ret; |
1447 | } | |
1448 | ||
d98ba053 XG |
1449 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1450 | struct list_head *invalid_list) | |
1d9dc7e0 | 1451 | { |
d98ba053 | 1452 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1453 | } |
1454 | ||
9f1a122f XG |
1455 | /* @gfn should be write-protected at the call site */ |
1456 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1457 | { | |
9f1a122f | 1458 | struct kvm_mmu_page *s; |
f41d335a | 1459 | struct hlist_node *node; |
d98ba053 | 1460 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1461 | bool flush = false; |
1462 | ||
f41d335a | 1463 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1464 | if (!s->unsync) |
9f1a122f XG |
1465 | continue; |
1466 | ||
1467 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
a4a8e6f7 | 1468 | kvm_unlink_unsync_page(vcpu->kvm, s); |
9f1a122f | 1469 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || |
a4a8e6f7 | 1470 | (vcpu->arch.mmu.sync_page(vcpu, s))) { |
d98ba053 | 1471 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1472 | continue; |
1473 | } | |
9f1a122f XG |
1474 | flush = true; |
1475 | } | |
1476 | ||
d98ba053 | 1477 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f XG |
1478 | if (flush) |
1479 | kvm_mmu_flush_tlb(vcpu); | |
1480 | } | |
1481 | ||
60c8aec6 MT |
1482 | struct mmu_page_path { |
1483 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1484 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1485 | }; |
1486 | ||
60c8aec6 MT |
1487 | #define for_each_sp(pvec, sp, parents, i) \ |
1488 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1489 | sp = pvec.page[i].sp; \ | |
1490 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1491 | i = mmu_pages_next(&pvec, &parents, i)) | |
1492 | ||
cded19f3 HE |
1493 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1494 | struct mmu_page_path *parents, | |
1495 | int i) | |
60c8aec6 MT |
1496 | { |
1497 | int n; | |
1498 | ||
1499 | for (n = i+1; n < pvec->nr; n++) { | |
1500 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1501 | ||
1502 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1503 | parents->idx[0] = pvec->page[n].idx; | |
1504 | return n; | |
1505 | } | |
1506 | ||
1507 | parents->parent[sp->role.level-2] = sp; | |
1508 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1509 | } | |
1510 | ||
1511 | return n; | |
1512 | } | |
1513 | ||
cded19f3 | 1514 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1515 | { |
60c8aec6 MT |
1516 | struct kvm_mmu_page *sp; |
1517 | unsigned int level = 0; | |
1518 | ||
1519 | do { | |
1520 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1521 | |
60c8aec6 MT |
1522 | sp = parents->parent[level]; |
1523 | if (!sp) | |
1524 | return; | |
1525 | ||
1526 | --sp->unsync_children; | |
1527 | WARN_ON((int)sp->unsync_children < 0); | |
1528 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1529 | level++; | |
1530 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1531 | } |
1532 | ||
60c8aec6 MT |
1533 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1534 | struct mmu_page_path *parents, | |
1535 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1536 | { |
60c8aec6 MT |
1537 | parents->parent[parent->role.level-1] = NULL; |
1538 | pvec->nr = 0; | |
1539 | } | |
4731d4c7 | 1540 | |
60c8aec6 MT |
1541 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1542 | struct kvm_mmu_page *parent) | |
1543 | { | |
1544 | int i; | |
1545 | struct kvm_mmu_page *sp; | |
1546 | struct mmu_page_path parents; | |
1547 | struct kvm_mmu_pages pages; | |
d98ba053 | 1548 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
1549 | |
1550 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1551 | while (mmu_unsync_walk(parent, &pages)) { | |
b1a36821 MT |
1552 | int protected = 0; |
1553 | ||
1554 | for_each_sp(pages, sp, parents, i) | |
1555 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1556 | ||
1557 | if (protected) | |
1558 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1559 | ||
60c8aec6 | 1560 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 1561 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1562 | mmu_pages_clear_parents(&parents); |
1563 | } | |
d98ba053 | 1564 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 1565 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1566 | kvm_mmu_pages_init(parent, &parents, &pages); |
1567 | } | |
4731d4c7 MT |
1568 | } |
1569 | ||
c3707958 XG |
1570 | static void init_shadow_page_table(struct kvm_mmu_page *sp) |
1571 | { | |
1572 | int i; | |
1573 | ||
1574 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1575 | sp->spt[i] = 0ull; | |
1576 | } | |
1577 | ||
cea0f0e7 AK |
1578 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1579 | gfn_t gfn, | |
1580 | gva_t gaddr, | |
1581 | unsigned level, | |
f6e2c02b | 1582 | int direct, |
41074d07 | 1583 | unsigned access, |
f7d9c7b7 | 1584 | u64 *parent_pte) |
cea0f0e7 AK |
1585 | { |
1586 | union kvm_mmu_page_role role; | |
cea0f0e7 | 1587 | unsigned quadrant; |
9f1a122f | 1588 | struct kvm_mmu_page *sp; |
f41d335a | 1589 | struct hlist_node *node; |
9f1a122f | 1590 | bool need_sync = false; |
cea0f0e7 | 1591 | |
a770f6f2 | 1592 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1593 | role.level = level; |
f6e2c02b | 1594 | role.direct = direct; |
84b0c8c6 | 1595 | if (role.direct) |
5b7e0102 | 1596 | role.cr4_pae = 0; |
41074d07 | 1597 | role.access = access; |
c5a78f2b JR |
1598 | if (!vcpu->arch.mmu.direct_map |
1599 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
1600 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1601 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1602 | role.quadrant = quadrant; | |
1603 | } | |
f41d335a | 1604 | for_each_gfn_sp(vcpu->kvm, sp, gfn, node) { |
7ae680eb XG |
1605 | if (!need_sync && sp->unsync) |
1606 | need_sync = true; | |
4731d4c7 | 1607 | |
7ae680eb XG |
1608 | if (sp->role.word != role.word) |
1609 | continue; | |
4731d4c7 | 1610 | |
7ae680eb XG |
1611 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
1612 | break; | |
e02aa901 | 1613 | |
7ae680eb XG |
1614 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
1615 | if (sp->unsync_children) { | |
a8eeb04a | 1616 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
7ae680eb XG |
1617 | kvm_mmu_mark_parents_unsync(sp); |
1618 | } else if (sp->unsync) | |
1619 | kvm_mmu_mark_parents_unsync(sp); | |
e02aa901 | 1620 | |
7ae680eb XG |
1621 | trace_kvm_mmu_get_page(sp, false); |
1622 | return sp; | |
1623 | } | |
dfc5aa00 | 1624 | ++vcpu->kvm->stat.mmu_cache_miss; |
2032a93d | 1625 | sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct); |
4db35314 AK |
1626 | if (!sp) |
1627 | return sp; | |
4db35314 AK |
1628 | sp->gfn = gfn; |
1629 | sp->role = role; | |
7ae680eb XG |
1630 | hlist_add_head(&sp->hash_link, |
1631 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 1632 | if (!direct) { |
b1a36821 MT |
1633 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1634 | kvm_flush_remote_tlbs(vcpu->kvm); | |
9f1a122f XG |
1635 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
1636 | kvm_sync_pages(vcpu, gfn); | |
1637 | ||
4731d4c7 MT |
1638 | account_shadowed(vcpu->kvm, gfn); |
1639 | } | |
c3707958 | 1640 | init_shadow_page_table(sp); |
f691fe1d | 1641 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1642 | return sp; |
cea0f0e7 AK |
1643 | } |
1644 | ||
2d11123a AK |
1645 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1646 | struct kvm_vcpu *vcpu, u64 addr) | |
1647 | { | |
1648 | iterator->addr = addr; | |
1649 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1650 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 JR |
1651 | |
1652 | if (iterator->level == PT64_ROOT_LEVEL && | |
1653 | vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL && | |
1654 | !vcpu->arch.mmu.direct_map) | |
1655 | --iterator->level; | |
1656 | ||
2d11123a AK |
1657 | if (iterator->level == PT32E_ROOT_LEVEL) { |
1658 | iterator->shadow_addr | |
1659 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
1660 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
1661 | --iterator->level; | |
1662 | if (!iterator->shadow_addr) | |
1663 | iterator->level = 0; | |
1664 | } | |
1665 | } | |
1666 | ||
1667 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
1668 | { | |
1669 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
1670 | return false; | |
4d88954d | 1671 | |
2d11123a AK |
1672 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
1673 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
1674 | return true; | |
1675 | } | |
1676 | ||
c2a2ac2b XG |
1677 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
1678 | u64 spte) | |
2d11123a | 1679 | { |
c2a2ac2b | 1680 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
1681 | iterator->level = 0; |
1682 | return; | |
1683 | } | |
1684 | ||
c2a2ac2b | 1685 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
1686 | --iterator->level; |
1687 | } | |
1688 | ||
c2a2ac2b XG |
1689 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
1690 | { | |
1691 | return __shadow_walk_next(iterator, *iterator->sptep); | |
1692 | } | |
1693 | ||
32ef26a3 AK |
1694 | static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp) |
1695 | { | |
1696 | u64 spte; | |
1697 | ||
1698 | spte = __pa(sp->spt) | |
1699 | | PT_PRESENT_MASK | PT_ACCESSED_MASK | |
1700 | | PT_WRITABLE_MASK | PT_USER_MASK; | |
1df9f2dc | 1701 | mmu_spte_set(sptep, spte); |
32ef26a3 AK |
1702 | } |
1703 | ||
a3aa51cf AK |
1704 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) |
1705 | { | |
1706 | if (is_large_pte(*sptep)) { | |
c3707958 | 1707 | drop_spte(vcpu->kvm, sptep); |
a3aa51cf AK |
1708 | kvm_flush_remote_tlbs(vcpu->kvm); |
1709 | } | |
1710 | } | |
1711 | ||
a357bd22 AK |
1712 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1713 | unsigned direct_access) | |
1714 | { | |
1715 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
1716 | struct kvm_mmu_page *child; | |
1717 | ||
1718 | /* | |
1719 | * For the direct sp, if the guest pte's dirty bit | |
1720 | * changed form clean to dirty, it will corrupt the | |
1721 | * sp's access: allow writable in the read-only sp, | |
1722 | * so we should update the spte at this point to get | |
1723 | * a new sp with the correct access. | |
1724 | */ | |
1725 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
1726 | if (child->role.access == direct_access) | |
1727 | return; | |
1728 | ||
bcdd9a93 | 1729 | drop_parent_pte(child, sptep); |
a357bd22 AK |
1730 | kvm_flush_remote_tlbs(vcpu->kvm); |
1731 | } | |
1732 | } | |
1733 | ||
38e3b2b2 XG |
1734 | static void mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
1735 | u64 *spte) | |
1736 | { | |
1737 | u64 pte; | |
1738 | struct kvm_mmu_page *child; | |
1739 | ||
1740 | pte = *spte; | |
1741 | if (is_shadow_present_pte(pte)) { | |
1742 | if (is_last_spte(pte, sp->role.level)) | |
c3707958 | 1743 | drop_spte(kvm, spte); |
38e3b2b2 XG |
1744 | else { |
1745 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 1746 | drop_parent_pte(child, spte); |
38e3b2b2 XG |
1747 | } |
1748 | } | |
c3707958 | 1749 | |
38e3b2b2 XG |
1750 | if (is_large_pte(pte)) |
1751 | --kvm->stat.lpages; | |
1752 | } | |
1753 | ||
90cb0529 | 1754 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 1755 | struct kvm_mmu_page *sp) |
a436036b | 1756 | { |
697fe2e2 | 1757 | unsigned i; |
697fe2e2 | 1758 | |
38e3b2b2 XG |
1759 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
1760 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
1761 | } |
1762 | ||
4db35314 | 1763 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1764 | { |
4db35314 | 1765 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
1766 | } |
1767 | ||
12b7d28f AK |
1768 | static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm) |
1769 | { | |
1770 | int i; | |
988a2cae | 1771 | struct kvm_vcpu *vcpu; |
12b7d28f | 1772 | |
988a2cae GN |
1773 | kvm_for_each_vcpu(i, vcpu, kvm) |
1774 | vcpu->arch.last_pte_updated = NULL; | |
12b7d28f AK |
1775 | } |
1776 | ||
31aa2b44 | 1777 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b AK |
1778 | { |
1779 | u64 *parent_pte; | |
1780 | ||
bcdd9a93 XG |
1781 | while ((parent_pte = pte_list_next(&sp->parent_ptes, NULL))) |
1782 | drop_parent_pte(sp, parent_pte); | |
31aa2b44 AK |
1783 | } |
1784 | ||
60c8aec6 | 1785 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
1786 | struct kvm_mmu_page *parent, |
1787 | struct list_head *invalid_list) | |
4731d4c7 | 1788 | { |
60c8aec6 MT |
1789 | int i, zapped = 0; |
1790 | struct mmu_page_path parents; | |
1791 | struct kvm_mmu_pages pages; | |
4731d4c7 | 1792 | |
60c8aec6 | 1793 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1794 | return 0; |
60c8aec6 MT |
1795 | |
1796 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1797 | while (mmu_unsync_walk(parent, &pages)) { | |
1798 | struct kvm_mmu_page *sp; | |
1799 | ||
1800 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 1801 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 1802 | mmu_pages_clear_parents(&parents); |
77662e00 | 1803 | zapped++; |
60c8aec6 | 1804 | } |
60c8aec6 MT |
1805 | kvm_mmu_pages_init(parent, &parents, &pages); |
1806 | } | |
1807 | ||
1808 | return zapped; | |
4731d4c7 MT |
1809 | } |
1810 | ||
7775834a XG |
1811 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1812 | struct list_head *invalid_list) | |
31aa2b44 | 1813 | { |
4731d4c7 | 1814 | int ret; |
f691fe1d | 1815 | |
7775834a | 1816 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 1817 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 1818 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 1819 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 1820 | kvm_mmu_unlink_parents(kvm, sp); |
f6e2c02b | 1821 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 1822 | unaccount_shadowed(kvm, sp->gfn); |
4731d4c7 MT |
1823 | if (sp->unsync) |
1824 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 1825 | if (!sp->root_count) { |
54a4f023 GJ |
1826 | /* Count self */ |
1827 | ret++; | |
7775834a | 1828 | list_move(&sp->link, invalid_list); |
aa6bd187 | 1829 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 1830 | } else { |
5b5c6a5a | 1831 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
2e53d63a MT |
1832 | kvm_reload_remote_mmus(kvm); |
1833 | } | |
7775834a XG |
1834 | |
1835 | sp->role.invalid = 1; | |
12b7d28f | 1836 | kvm_mmu_reset_last_pte_updated(kvm); |
4731d4c7 | 1837 | return ret; |
a436036b AK |
1838 | } |
1839 | ||
c2a2ac2b XG |
1840 | static void kvm_mmu_isolate_pages(struct list_head *invalid_list) |
1841 | { | |
1842 | struct kvm_mmu_page *sp; | |
1843 | ||
1844 | list_for_each_entry(sp, invalid_list, link) | |
1845 | kvm_mmu_isolate_page(sp); | |
1846 | } | |
1847 | ||
1848 | static void free_pages_rcu(struct rcu_head *head) | |
1849 | { | |
1850 | struct kvm_mmu_page *next, *sp; | |
1851 | ||
1852 | sp = container_of(head, struct kvm_mmu_page, rcu); | |
1853 | while (sp) { | |
1854 | if (!list_empty(&sp->link)) | |
1855 | next = list_first_entry(&sp->link, | |
1856 | struct kvm_mmu_page, link); | |
1857 | else | |
1858 | next = NULL; | |
1859 | kvm_mmu_free_page(sp); | |
1860 | sp = next; | |
1861 | } | |
1862 | } | |
1863 | ||
7775834a XG |
1864 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
1865 | struct list_head *invalid_list) | |
1866 | { | |
1867 | struct kvm_mmu_page *sp; | |
1868 | ||
1869 | if (list_empty(invalid_list)) | |
1870 | return; | |
1871 | ||
1872 | kvm_flush_remote_tlbs(kvm); | |
1873 | ||
c2a2ac2b XG |
1874 | if (atomic_read(&kvm->arch.reader_counter)) { |
1875 | kvm_mmu_isolate_pages(invalid_list); | |
1876 | sp = list_first_entry(invalid_list, struct kvm_mmu_page, link); | |
1877 | list_del_init(invalid_list); | |
1878 | call_rcu(&sp->rcu, free_pages_rcu); | |
1879 | return; | |
1880 | } | |
1881 | ||
7775834a XG |
1882 | do { |
1883 | sp = list_first_entry(invalid_list, struct kvm_mmu_page, link); | |
1884 | WARN_ON(!sp->role.invalid || sp->root_count); | |
bd4c86ea | 1885 | kvm_mmu_isolate_page(sp); |
aa6bd187 | 1886 | kvm_mmu_free_page(sp); |
7775834a XG |
1887 | } while (!list_empty(invalid_list)); |
1888 | ||
1889 | } | |
1890 | ||
82ce2c96 IE |
1891 | /* |
1892 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 1893 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 1894 | */ |
49d5ca26 | 1895 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 1896 | { |
d98ba053 | 1897 | LIST_HEAD(invalid_list); |
82ce2c96 IE |
1898 | /* |
1899 | * If we set the number of mmu pages to be smaller be than the | |
1900 | * number of actived pages , we must to free some mmu pages before we | |
1901 | * change the value | |
1902 | */ | |
1903 | ||
49d5ca26 DH |
1904 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
1905 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages && | |
77662e00 | 1906 | !list_empty(&kvm->arch.active_mmu_pages)) { |
82ce2c96 IE |
1907 | struct kvm_mmu_page *page; |
1908 | ||
f05e70ac | 1909 | page = container_of(kvm->arch.active_mmu_pages.prev, |
82ce2c96 | 1910 | struct kvm_mmu_page, link); |
80b63faf | 1911 | kvm_mmu_prepare_zap_page(kvm, page, &invalid_list); |
82ce2c96 | 1912 | } |
aa6bd187 | 1913 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 1914 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 1915 | } |
82ce2c96 | 1916 | |
49d5ca26 | 1917 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
82ce2c96 IE |
1918 | } |
1919 | ||
f67a46f4 | 1920 | static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 1921 | { |
4db35314 | 1922 | struct kvm_mmu_page *sp; |
f41d335a | 1923 | struct hlist_node *node; |
d98ba053 | 1924 | LIST_HEAD(invalid_list); |
a436036b AK |
1925 | int r; |
1926 | ||
9ad17b10 | 1927 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 1928 | r = 0; |
f41d335a XG |
1929 | |
1930 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { | |
9ad17b10 | 1931 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
1932 | sp->role.word); |
1933 | r = 1; | |
f41d335a | 1934 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 1935 | } |
d98ba053 | 1936 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
a436036b | 1937 | return r; |
cea0f0e7 AK |
1938 | } |
1939 | ||
f67a46f4 | 1940 | static void mmu_unshadow(struct kvm *kvm, gfn_t gfn) |
97a0a01e | 1941 | { |
4db35314 | 1942 | struct kvm_mmu_page *sp; |
f41d335a | 1943 | struct hlist_node *node; |
d98ba053 | 1944 | LIST_HEAD(invalid_list); |
97a0a01e | 1945 | |
f41d335a | 1946 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { |
9ad17b10 | 1947 | pgprintk("%s: zap %llx %x\n", |
7ae680eb | 1948 | __func__, gfn, sp->role.word); |
f41d335a | 1949 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
97a0a01e | 1950 | } |
d98ba053 | 1951 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
97a0a01e AK |
1952 | } |
1953 | ||
38c335f1 | 1954 | static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn) |
6aa8b732 | 1955 | { |
bc6678a3 | 1956 | int slot = memslot_id(kvm, gfn); |
4db35314 | 1957 | struct kvm_mmu_page *sp = page_header(__pa(pte)); |
6aa8b732 | 1958 | |
291f26bc | 1959 | __set_bit(slot, sp->slot_bitmap); |
6aa8b732 AK |
1960 | } |
1961 | ||
74be52e3 SY |
1962 | /* |
1963 | * The function is based on mtrr_type_lookup() in | |
1964 | * arch/x86/kernel/cpu/mtrr/generic.c | |
1965 | */ | |
1966 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
1967 | u64 start, u64 end) | |
1968 | { | |
1969 | int i; | |
1970 | u64 base, mask; | |
1971 | u8 prev_match, curr_match; | |
1972 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
1973 | ||
1974 | if (!mtrr_state->enabled) | |
1975 | return 0xFF; | |
1976 | ||
1977 | /* Make end inclusive end, instead of exclusive */ | |
1978 | end--; | |
1979 | ||
1980 | /* Look in fixed ranges. Just return the type as per start */ | |
1981 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
1982 | int idx; | |
1983 | ||
1984 | if (start < 0x80000) { | |
1985 | idx = 0; | |
1986 | idx += (start >> 16); | |
1987 | return mtrr_state->fixed_ranges[idx]; | |
1988 | } else if (start < 0xC0000) { | |
1989 | idx = 1 * 8; | |
1990 | idx += ((start - 0x80000) >> 14); | |
1991 | return mtrr_state->fixed_ranges[idx]; | |
1992 | } else if (start < 0x1000000) { | |
1993 | idx = 3 * 8; | |
1994 | idx += ((start - 0xC0000) >> 12); | |
1995 | return mtrr_state->fixed_ranges[idx]; | |
1996 | } | |
1997 | } | |
1998 | ||
1999 | /* | |
2000 | * Look in variable ranges | |
2001 | * Look of multiple ranges matching this address and pick type | |
2002 | * as per MTRR precedence | |
2003 | */ | |
2004 | if (!(mtrr_state->enabled & 2)) | |
2005 | return mtrr_state->def_type; | |
2006 | ||
2007 | prev_match = 0xFF; | |
2008 | for (i = 0; i < num_var_ranges; ++i) { | |
2009 | unsigned short start_state, end_state; | |
2010 | ||
2011 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
2012 | continue; | |
2013 | ||
2014 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
2015 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
2016 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
2017 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
2018 | ||
2019 | start_state = ((start & mask) == (base & mask)); | |
2020 | end_state = ((end & mask) == (base & mask)); | |
2021 | if (start_state != end_state) | |
2022 | return 0xFE; | |
2023 | ||
2024 | if ((start & mask) != (base & mask)) | |
2025 | continue; | |
2026 | ||
2027 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
2028 | if (prev_match == 0xFF) { | |
2029 | prev_match = curr_match; | |
2030 | continue; | |
2031 | } | |
2032 | ||
2033 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
2034 | curr_match == MTRR_TYPE_UNCACHABLE) | |
2035 | return MTRR_TYPE_UNCACHABLE; | |
2036 | ||
2037 | if ((prev_match == MTRR_TYPE_WRBACK && | |
2038 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
2039 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
2040 | curr_match == MTRR_TYPE_WRBACK)) { | |
2041 | prev_match = MTRR_TYPE_WRTHROUGH; | |
2042 | curr_match = MTRR_TYPE_WRTHROUGH; | |
2043 | } | |
2044 | ||
2045 | if (prev_match != curr_match) | |
2046 | return MTRR_TYPE_UNCACHABLE; | |
2047 | } | |
2048 | ||
2049 | if (prev_match != 0xFF) | |
2050 | return prev_match; | |
2051 | ||
2052 | return mtrr_state->def_type; | |
2053 | } | |
2054 | ||
4b12f0de | 2055 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
2056 | { |
2057 | u8 mtrr; | |
2058 | ||
2059 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
2060 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
2061 | if (mtrr == 0xfe || mtrr == 0xff) | |
2062 | mtrr = MTRR_TYPE_WRBACK; | |
2063 | return mtrr; | |
2064 | } | |
4b12f0de | 2065 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 2066 | |
9cf5cf5a XG |
2067 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
2068 | { | |
2069 | trace_kvm_mmu_unsync_page(sp); | |
2070 | ++vcpu->kvm->stat.mmu_unsync; | |
2071 | sp->unsync = 1; | |
2072 | ||
2073 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2074 | } |
2075 | ||
2076 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 2077 | { |
4731d4c7 | 2078 | struct kvm_mmu_page *s; |
f41d335a | 2079 | struct hlist_node *node; |
9cf5cf5a | 2080 | |
f41d335a | 2081 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 2082 | if (s->unsync) |
4731d4c7 | 2083 | continue; |
9cf5cf5a XG |
2084 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
2085 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 2086 | } |
4731d4c7 MT |
2087 | } |
2088 | ||
2089 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
2090 | bool can_unsync) | |
2091 | { | |
9cf5cf5a | 2092 | struct kvm_mmu_page *s; |
f41d335a | 2093 | struct hlist_node *node; |
9cf5cf5a XG |
2094 | bool need_unsync = false; |
2095 | ||
f41d335a | 2096 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
36a2e677 XG |
2097 | if (!can_unsync) |
2098 | return 1; | |
2099 | ||
9cf5cf5a | 2100 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2101 | return 1; |
9cf5cf5a XG |
2102 | |
2103 | if (!need_unsync && !s->unsync) { | |
36a2e677 | 2104 | if (!oos_shadow) |
9cf5cf5a XG |
2105 | return 1; |
2106 | need_unsync = true; | |
2107 | } | |
4731d4c7 | 2108 | } |
9cf5cf5a XG |
2109 | if (need_unsync) |
2110 | kvm_unsync_pages(vcpu, gfn); | |
4731d4c7 MT |
2111 | return 0; |
2112 | } | |
2113 | ||
d555c333 | 2114 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd | 2115 | unsigned pte_access, int user_fault, |
640d9b0d | 2116 | int write_fault, int level, |
c2d0ee46 | 2117 | gfn_t gfn, pfn_t pfn, bool speculative, |
9bdbba13 | 2118 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2119 | { |
b330aa0c | 2120 | u64 spte, entry = *sptep; |
1e73f9dd | 2121 | int ret = 0; |
64d4d521 | 2122 | |
1c4f1fd6 AK |
2123 | /* |
2124 | * We don't set the accessed bit, since we sometimes want to see | |
2125 | * whether the guest actually used the pte (in order to detect | |
2126 | * demand paging). | |
2127 | */ | |
982c2565 | 2128 | spte = PT_PRESENT_MASK; |
947da538 | 2129 | if (!speculative) |
3201b5d9 | 2130 | spte |= shadow_accessed_mask; |
640d9b0d | 2131 | |
7b52345e SY |
2132 | if (pte_access & ACC_EXEC_MASK) |
2133 | spte |= shadow_x_mask; | |
2134 | else | |
2135 | spte |= shadow_nx_mask; | |
1c4f1fd6 | 2136 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2137 | spte |= shadow_user_mask; |
852e3c19 | 2138 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2139 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2140 | if (tdp_enabled) |
4b12f0de SY |
2141 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
2142 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 2143 | |
9bdbba13 | 2144 | if (host_writable) |
1403283a | 2145 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2146 | else |
2147 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2148 | |
35149e21 | 2149 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 AK |
2150 | |
2151 | if ((pte_access & ACC_WRITE_MASK) | |
c5a78f2b JR |
2152 | || (!vcpu->arch.mmu.direct_map && write_fault |
2153 | && !is_write_protection(vcpu) && !user_fault)) { | |
1c4f1fd6 | 2154 | |
852e3c19 JR |
2155 | if (level > PT_PAGE_TABLE_LEVEL && |
2156 | has_wrprotected_page(vcpu->kvm, gfn, level)) { | |
38187c83 | 2157 | ret = 1; |
c3707958 | 2158 | drop_spte(vcpu->kvm, sptep); |
be38d276 | 2159 | goto done; |
38187c83 MT |
2160 | } |
2161 | ||
1c4f1fd6 | 2162 | spte |= PT_WRITABLE_MASK; |
1c4f1fd6 | 2163 | |
c5a78f2b | 2164 | if (!vcpu->arch.mmu.direct_map |
411c588d | 2165 | && !(pte_access & ACC_WRITE_MASK)) { |
69325a12 | 2166 | spte &= ~PT_USER_MASK; |
411c588d AK |
2167 | /* |
2168 | * If we converted a user page to a kernel page, | |
2169 | * so that the kernel can write to it when cr0.wp=0, | |
2170 | * then we should prevent the kernel from executing it | |
2171 | * if SMEP is enabled. | |
2172 | */ | |
2173 | if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)) | |
2174 | spte |= PT64_NX_MASK; | |
2175 | } | |
69325a12 | 2176 | |
ecc5589f MT |
2177 | /* |
2178 | * Optimization: for pte sync, if spte was writable the hash | |
2179 | * lookup is unnecessary (and expensive). Write protection | |
2180 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2181 | * Same reasoning can be applied to dirty page accounting. | |
2182 | */ | |
8dae4445 | 2183 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2184 | goto set_pte; |
2185 | ||
4731d4c7 | 2186 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2187 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2188 | __func__, gfn); |
1e73f9dd | 2189 | ret = 1; |
1c4f1fd6 | 2190 | pte_access &= ~ACC_WRITE_MASK; |
8dae4445 | 2191 | if (is_writable_pte(spte)) |
1c4f1fd6 | 2192 | spte &= ~PT_WRITABLE_MASK; |
1c4f1fd6 AK |
2193 | } |
2194 | } | |
2195 | ||
1c4f1fd6 AK |
2196 | if (pte_access & ACC_WRITE_MASK) |
2197 | mark_page_dirty(vcpu->kvm, gfn); | |
2198 | ||
38187c83 | 2199 | set_pte: |
1df9f2dc | 2200 | mmu_spte_update(sptep, spte); |
b330aa0c XG |
2201 | /* |
2202 | * If we overwrite a writable spte with a read-only one we | |
2203 | * should flush remote TLBs. Otherwise rmap_write_protect | |
2204 | * will find a read-only spte, even though the writable spte | |
2205 | * might be cached on a CPU's TLB. | |
2206 | */ | |
2207 | if (is_writable_pte(entry) && !is_writable_pte(*sptep)) | |
2208 | kvm_flush_remote_tlbs(vcpu->kvm); | |
be38d276 | 2209 | done: |
1e73f9dd MT |
2210 | return ret; |
2211 | } | |
2212 | ||
d555c333 | 2213 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd | 2214 | unsigned pt_access, unsigned pte_access, |
640d9b0d | 2215 | int user_fault, int write_fault, |
b90a0e6c | 2216 | int *emulate, int level, gfn_t gfn, |
1403283a | 2217 | pfn_t pfn, bool speculative, |
9bdbba13 | 2218 | bool host_writable) |
1e73f9dd MT |
2219 | { |
2220 | int was_rmapped = 0; | |
53a27b39 | 2221 | int rmap_count; |
1e73f9dd MT |
2222 | |
2223 | pgprintk("%s: spte %llx access %x write_fault %d" | |
9ad17b10 | 2224 | " user_fault %d gfn %llx\n", |
d555c333 | 2225 | __func__, *sptep, pt_access, |
1e73f9dd MT |
2226 | write_fault, user_fault, gfn); |
2227 | ||
d555c333 | 2228 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
2229 | /* |
2230 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2231 | * the parent of the now unreachable PTE. | |
2232 | */ | |
852e3c19 JR |
2233 | if (level > PT_PAGE_TABLE_LEVEL && |
2234 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2235 | struct kvm_mmu_page *child; |
d555c333 | 2236 | u64 pte = *sptep; |
1e73f9dd MT |
2237 | |
2238 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 2239 | drop_parent_pte(child, sptep); |
3be2264b | 2240 | kvm_flush_remote_tlbs(vcpu->kvm); |
d555c333 | 2241 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2242 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2243 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2244 | drop_spte(vcpu->kvm, sptep); |
91546356 | 2245 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2246 | } else |
2247 | was_rmapped = 1; | |
1e73f9dd | 2248 | } |
852e3c19 | 2249 | |
d555c333 | 2250 | if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault, |
640d9b0d | 2251 | level, gfn, pfn, speculative, true, |
9bdbba13 | 2252 | host_writable)) { |
1e73f9dd | 2253 | if (write_fault) |
b90a0e6c | 2254 | *emulate = 1; |
5304efde | 2255 | kvm_mmu_flush_tlb(vcpu); |
a378b4e6 | 2256 | } |
1e73f9dd | 2257 | |
d555c333 | 2258 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2259 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2260 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
2261 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
2262 | *sptep, sptep); | |
d555c333 | 2263 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2264 | ++vcpu->kvm->stat.lpages; |
2265 | ||
ffb61bb3 XG |
2266 | if (is_shadow_present_pte(*sptep)) { |
2267 | page_header_update_slot(vcpu->kvm, sptep, gfn); | |
2268 | if (!was_rmapped) { | |
2269 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2270 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2271 | rmap_recycle(vcpu, sptep, gfn); | |
2272 | } | |
1c4f1fd6 | 2273 | } |
9ed5520d | 2274 | kvm_release_pfn_clean(pfn); |
1b7fcd32 | 2275 | if (speculative) { |
d555c333 | 2276 | vcpu->arch.last_pte_updated = sptep; |
1b7fcd32 AK |
2277 | vcpu->arch.last_pte_gfn = gfn; |
2278 | } | |
1c4f1fd6 AK |
2279 | } |
2280 | ||
6aa8b732 AK |
2281 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
2282 | { | |
2283 | } | |
2284 | ||
957ed9ef XG |
2285 | static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
2286 | bool no_dirty_log) | |
2287 | { | |
2288 | struct kvm_memory_slot *slot; | |
2289 | unsigned long hva; | |
2290 | ||
5d163b1c | 2291 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
957ed9ef | 2292 | if (!slot) { |
fce92dce XG |
2293 | get_page(fault_page); |
2294 | return page_to_pfn(fault_page); | |
957ed9ef XG |
2295 | } |
2296 | ||
2297 | hva = gfn_to_hva_memslot(slot, gfn); | |
2298 | ||
2299 | return hva_to_pfn_atomic(vcpu->kvm, hva); | |
2300 | } | |
2301 | ||
2302 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2303 | struct kvm_mmu_page *sp, | |
2304 | u64 *start, u64 *end) | |
2305 | { | |
2306 | struct page *pages[PTE_PREFETCH_NUM]; | |
2307 | unsigned access = sp->role.access; | |
2308 | int i, ret; | |
2309 | gfn_t gfn; | |
2310 | ||
2311 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
5d163b1c | 2312 | if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK)) |
957ed9ef XG |
2313 | return -1; |
2314 | ||
2315 | ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start); | |
2316 | if (ret <= 0) | |
2317 | return -1; | |
2318 | ||
2319 | for (i = 0; i < ret; i++, gfn++, start++) | |
2320 | mmu_set_spte(vcpu, start, ACC_ALL, | |
640d9b0d | 2321 | access, 0, 0, NULL, |
957ed9ef XG |
2322 | sp->role.level, gfn, |
2323 | page_to_pfn(pages[i]), true, true); | |
2324 | ||
2325 | return 0; | |
2326 | } | |
2327 | ||
2328 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2329 | struct kvm_mmu_page *sp, u64 *sptep) | |
2330 | { | |
2331 | u64 *spte, *start = NULL; | |
2332 | int i; | |
2333 | ||
2334 | WARN_ON(!sp->role.direct); | |
2335 | ||
2336 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2337 | spte = sp->spt + i; | |
2338 | ||
2339 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2340 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2341 | if (!start) |
2342 | continue; | |
2343 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2344 | break; | |
2345 | start = NULL; | |
2346 | } else if (!start) | |
2347 | start = spte; | |
2348 | } | |
2349 | } | |
2350 | ||
2351 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2352 | { | |
2353 | struct kvm_mmu_page *sp; | |
2354 | ||
2355 | /* | |
2356 | * Since it's no accessed bit on EPT, it's no way to | |
2357 | * distinguish between actually accessed translations | |
2358 | * and prefetched, so disable pte prefetch if EPT is | |
2359 | * enabled. | |
2360 | */ | |
2361 | if (!shadow_accessed_mask) | |
2362 | return; | |
2363 | ||
2364 | sp = page_header(__pa(sptep)); | |
2365 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2366 | return; | |
2367 | ||
2368 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2369 | } | |
2370 | ||
9f652d21 | 2371 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
2ec4739d XG |
2372 | int map_writable, int level, gfn_t gfn, pfn_t pfn, |
2373 | bool prefault) | |
140754bc | 2374 | { |
9f652d21 | 2375 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2376 | struct kvm_mmu_page *sp; |
b90a0e6c | 2377 | int emulate = 0; |
140754bc | 2378 | gfn_t pseudo_gfn; |
6aa8b732 | 2379 | |
9f652d21 | 2380 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2381 | if (iterator.level == level) { |
612819c3 MT |
2382 | unsigned pte_access = ACC_ALL; |
2383 | ||
612819c3 | 2384 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access, |
b90a0e6c | 2385 | 0, write, &emulate, |
2ec4739d | 2386 | level, gfn, pfn, prefault, map_writable); |
957ed9ef | 2387 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2388 | ++vcpu->stat.pf_fixed; |
2389 | break; | |
6aa8b732 AK |
2390 | } |
2391 | ||
c3707958 | 2392 | if (!is_shadow_present_pte(*iterator.sptep)) { |
c9fa0b3b LJ |
2393 | u64 base_addr = iterator.addr; |
2394 | ||
2395 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2396 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 AK |
2397 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
2398 | iterator.level - 1, | |
2399 | 1, ACC_ALL, iterator.sptep); | |
2400 | if (!sp) { | |
2401 | pgprintk("nonpaging_map: ENOMEM\n"); | |
2402 | kvm_release_pfn_clean(pfn); | |
2403 | return -ENOMEM; | |
2404 | } | |
140754bc | 2405 | |
1df9f2dc XG |
2406 | mmu_spte_set(iterator.sptep, |
2407 | __pa(sp->spt) | |
2408 | | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
2409 | | shadow_user_mask | shadow_x_mask | |
2410 | | shadow_accessed_mask); | |
9f652d21 AK |
2411 | } |
2412 | } | |
b90a0e6c | 2413 | return emulate; |
6aa8b732 AK |
2414 | } |
2415 | ||
77db5cbd | 2416 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2417 | { |
77db5cbd HY |
2418 | siginfo_t info; |
2419 | ||
2420 | info.si_signo = SIGBUS; | |
2421 | info.si_errno = 0; | |
2422 | info.si_code = BUS_MCEERR_AR; | |
2423 | info.si_addr = (void __user *)address; | |
2424 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 2425 | |
77db5cbd | 2426 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
2427 | } |
2428 | ||
d7c55201 | 2429 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn) |
bf998156 HY |
2430 | { |
2431 | kvm_release_pfn_clean(pfn); | |
2432 | if (is_hwpoison_pfn(pfn)) { | |
bebb106a | 2433 | kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current); |
bf998156 | 2434 | return 0; |
d7c55201 | 2435 | } |
edba23e5 | 2436 | |
d7c55201 | 2437 | return -EFAULT; |
bf998156 HY |
2438 | } |
2439 | ||
936a5fe6 AA |
2440 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
2441 | gfn_t *gfnp, pfn_t *pfnp, int *levelp) | |
2442 | { | |
2443 | pfn_t pfn = *pfnp; | |
2444 | gfn_t gfn = *gfnp; | |
2445 | int level = *levelp; | |
2446 | ||
2447 | /* | |
2448 | * Check if it's a transparent hugepage. If this would be an | |
2449 | * hugetlbfs page, level wouldn't be set to | |
2450 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
2451 | * here. | |
2452 | */ | |
2453 | if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) && | |
2454 | level == PT_PAGE_TABLE_LEVEL && | |
2455 | PageTransCompound(pfn_to_page(pfn)) && | |
2456 | !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) { | |
2457 | unsigned long mask; | |
2458 | /* | |
2459 | * mmu_notifier_retry was successful and we hold the | |
2460 | * mmu_lock here, so the pmd can't become splitting | |
2461 | * from under us, and in turn | |
2462 | * __split_huge_page_refcount() can't run from under | |
2463 | * us and we can safely transfer the refcount from | |
2464 | * PG_tail to PG_head as we switch the pfn to tail to | |
2465 | * head. | |
2466 | */ | |
2467 | *levelp = level = PT_DIRECTORY_LEVEL; | |
2468 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
2469 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2470 | if (pfn & mask) { | |
2471 | gfn &= ~mask; | |
2472 | *gfnp = gfn; | |
2473 | kvm_release_pfn_clean(pfn); | |
2474 | pfn &= ~mask; | |
2475 | if (!get_page_unless_zero(pfn_to_page(pfn))) | |
2476 | BUG(); | |
2477 | *pfnp = pfn; | |
2478 | } | |
2479 | } | |
2480 | } | |
2481 | ||
d7c55201 XG |
2482 | static bool mmu_invalid_pfn(pfn_t pfn) |
2483 | { | |
2484 | return unlikely(is_invalid_pfn(pfn) || is_noslot_pfn(pfn)); | |
2485 | } | |
2486 | ||
2487 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, | |
2488 | pfn_t pfn, unsigned access, int *ret_val) | |
2489 | { | |
2490 | bool ret = true; | |
2491 | ||
2492 | /* The pfn is invalid, report the error! */ | |
2493 | if (unlikely(is_invalid_pfn(pfn))) { | |
2494 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); | |
2495 | goto exit; | |
2496 | } | |
2497 | ||
2498 | if (unlikely(is_noslot_pfn(pfn))) { | |
2499 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); | |
2500 | *ret_val = 1; | |
2501 | goto exit; | |
2502 | } | |
2503 | ||
2504 | ret = false; | |
2505 | exit: | |
2506 | return ret; | |
2507 | } | |
2508 | ||
78b2c54a | 2509 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
060c2abe XG |
2510 | gva_t gva, pfn_t *pfn, bool write, bool *writable); |
2511 | ||
2512 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn, | |
78b2c54a | 2513 | bool prefault) |
10589a46 MT |
2514 | { |
2515 | int r; | |
852e3c19 | 2516 | int level; |
936a5fe6 | 2517 | int force_pt_level; |
35149e21 | 2518 | pfn_t pfn; |
e930bffe | 2519 | unsigned long mmu_seq; |
612819c3 | 2520 | bool map_writable; |
aaee2c94 | 2521 | |
936a5fe6 AA |
2522 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
2523 | if (likely(!force_pt_level)) { | |
2524 | level = mapping_level(vcpu, gfn); | |
2525 | /* | |
2526 | * This path builds a PAE pagetable - so we can map | |
2527 | * 2mb pages at maximum. Therefore check if the level | |
2528 | * is larger than that. | |
2529 | */ | |
2530 | if (level > PT_DIRECTORY_LEVEL) | |
2531 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 2532 | |
936a5fe6 AA |
2533 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
2534 | } else | |
2535 | level = PT_PAGE_TABLE_LEVEL; | |
05da4558 | 2536 | |
e930bffe | 2537 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2538 | smp_rmb(); |
060c2abe | 2539 | |
78b2c54a | 2540 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
060c2abe | 2541 | return 0; |
aaee2c94 | 2542 | |
d7c55201 XG |
2543 | if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r)) |
2544 | return r; | |
d196e343 | 2545 | |
aaee2c94 | 2546 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2547 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2548 | goto out_unlock; | |
eb787d10 | 2549 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
2550 | if (likely(!force_pt_level)) |
2551 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
2ec4739d XG |
2552 | r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn, |
2553 | prefault); | |
aaee2c94 MT |
2554 | spin_unlock(&vcpu->kvm->mmu_lock); |
2555 | ||
aaee2c94 | 2556 | |
10589a46 | 2557 | return r; |
e930bffe AA |
2558 | |
2559 | out_unlock: | |
2560 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2561 | kvm_release_pfn_clean(pfn); | |
2562 | return 0; | |
10589a46 MT |
2563 | } |
2564 | ||
2565 | ||
17ac10ad AK |
2566 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
2567 | { | |
2568 | int i; | |
4db35314 | 2569 | struct kvm_mmu_page *sp; |
d98ba053 | 2570 | LIST_HEAD(invalid_list); |
17ac10ad | 2571 | |
ad312c7c | 2572 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 2573 | return; |
aaee2c94 | 2574 | spin_lock(&vcpu->kvm->mmu_lock); |
81407ca5 JR |
2575 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL && |
2576 | (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL || | |
2577 | vcpu->arch.mmu.direct_map)) { | |
ad312c7c | 2578 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 2579 | |
4db35314 AK |
2580 | sp = page_header(root); |
2581 | --sp->root_count; | |
d98ba053 XG |
2582 | if (!sp->root_count && sp->role.invalid) { |
2583 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
2584 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
2585 | } | |
ad312c7c | 2586 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
aaee2c94 | 2587 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad AK |
2588 | return; |
2589 | } | |
17ac10ad | 2590 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2591 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2592 | |
417726a3 | 2593 | if (root) { |
417726a3 | 2594 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2595 | sp = page_header(root); |
2596 | --sp->root_count; | |
2e53d63a | 2597 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
2598 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2599 | &invalid_list); | |
417726a3 | 2600 | } |
ad312c7c | 2601 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2602 | } |
d98ba053 | 2603 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 2604 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2605 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2606 | } |
2607 | ||
8986ecc0 MT |
2608 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2609 | { | |
2610 | int ret = 0; | |
2611 | ||
2612 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 2613 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
2614 | ret = 1; |
2615 | } | |
2616 | ||
2617 | return ret; | |
2618 | } | |
2619 | ||
651dd37a JR |
2620 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
2621 | { | |
2622 | struct kvm_mmu_page *sp; | |
7ebaf15e | 2623 | unsigned i; |
651dd37a JR |
2624 | |
2625 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2626 | spin_lock(&vcpu->kvm->mmu_lock); | |
2627 | kvm_mmu_free_some_pages(vcpu); | |
2628 | sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, | |
2629 | 1, ACC_ALL, NULL); | |
2630 | ++sp->root_count; | |
2631 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2632 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
2633 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
2634 | for (i = 0; i < 4; ++i) { | |
2635 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2636 | ||
2637 | ASSERT(!VALID_PAGE(root)); | |
2638 | spin_lock(&vcpu->kvm->mmu_lock); | |
2639 | kvm_mmu_free_some_pages(vcpu); | |
649497d1 AK |
2640 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
2641 | i << 30, | |
651dd37a JR |
2642 | PT32_ROOT_LEVEL, 1, ACC_ALL, |
2643 | NULL); | |
2644 | root = __pa(sp->spt); | |
2645 | ++sp->root_count; | |
2646 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2647 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 2648 | } |
6292757f | 2649 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
2650 | } else |
2651 | BUG(); | |
2652 | ||
2653 | return 0; | |
2654 | } | |
2655 | ||
2656 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 2657 | { |
4db35314 | 2658 | struct kvm_mmu_page *sp; |
81407ca5 JR |
2659 | u64 pdptr, pm_mask; |
2660 | gfn_t root_gfn; | |
2661 | int i; | |
3bb65a22 | 2662 | |
5777ed34 | 2663 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 2664 | |
651dd37a JR |
2665 | if (mmu_check_root(vcpu, root_gfn)) |
2666 | return 1; | |
2667 | ||
2668 | /* | |
2669 | * Do we shadow a long mode page table? If so we need to | |
2670 | * write-protect the guests page table root. | |
2671 | */ | |
2672 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { | |
ad312c7c | 2673 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad AK |
2674 | |
2675 | ASSERT(!VALID_PAGE(root)); | |
651dd37a | 2676 | |
8facbbff | 2677 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2678 | kvm_mmu_free_some_pages(vcpu); |
651dd37a JR |
2679 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, |
2680 | 0, ACC_ALL, NULL); | |
4db35314 AK |
2681 | root = __pa(sp->spt); |
2682 | ++sp->root_count; | |
8facbbff | 2683 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2684 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 2685 | return 0; |
17ac10ad | 2686 | } |
f87f9288 | 2687 | |
651dd37a JR |
2688 | /* |
2689 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
2690 | * or a PAE 3-level page table. In either case we need to be aware that |
2691 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 2692 | */ |
81407ca5 JR |
2693 | pm_mask = PT_PRESENT_MASK; |
2694 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) | |
2695 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; | |
2696 | ||
17ac10ad | 2697 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2698 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
2699 | |
2700 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 2701 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
d41d1895 | 2702 | pdptr = kvm_pdptr_read_mmu(vcpu, &vcpu->arch.mmu, i); |
43a3795a | 2703 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 2704 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
2705 | continue; |
2706 | } | |
6de4f3ad | 2707 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
2708 | if (mmu_check_root(vcpu, root_gfn)) |
2709 | return 1; | |
5a7388c2 | 2710 | } |
8facbbff | 2711 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2712 | kvm_mmu_free_some_pages(vcpu); |
4db35314 | 2713 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
651dd37a | 2714 | PT32_ROOT_LEVEL, 0, |
f7d9c7b7 | 2715 | ACC_ALL, NULL); |
4db35314 AK |
2716 | root = __pa(sp->spt); |
2717 | ++sp->root_count; | |
8facbbff AK |
2718 | spin_unlock(&vcpu->kvm->mmu_lock); |
2719 | ||
81407ca5 | 2720 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 2721 | } |
6292757f | 2722 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
2723 | |
2724 | /* | |
2725 | * If we shadow a 32 bit page table with a long mode page | |
2726 | * table we enter this path. | |
2727 | */ | |
2728 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2729 | if (vcpu->arch.mmu.lm_root == NULL) { | |
2730 | /* | |
2731 | * The additional page necessary for this is only | |
2732 | * allocated on demand. | |
2733 | */ | |
2734 | ||
2735 | u64 *lm_root; | |
2736 | ||
2737 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
2738 | if (lm_root == NULL) | |
2739 | return 1; | |
2740 | ||
2741 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
2742 | ||
2743 | vcpu->arch.mmu.lm_root = lm_root; | |
2744 | } | |
2745 | ||
2746 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
2747 | } | |
2748 | ||
8986ecc0 | 2749 | return 0; |
17ac10ad AK |
2750 | } |
2751 | ||
651dd37a JR |
2752 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
2753 | { | |
2754 | if (vcpu->arch.mmu.direct_map) | |
2755 | return mmu_alloc_direct_roots(vcpu); | |
2756 | else | |
2757 | return mmu_alloc_shadow_roots(vcpu); | |
2758 | } | |
2759 | ||
0ba73cda MT |
2760 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
2761 | { | |
2762 | int i; | |
2763 | struct kvm_mmu_page *sp; | |
2764 | ||
81407ca5 JR |
2765 | if (vcpu->arch.mmu.direct_map) |
2766 | return; | |
2767 | ||
0ba73cda MT |
2768 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2769 | return; | |
6903074c | 2770 | |
bebb106a | 2771 | vcpu_clear_mmio_info(vcpu, ~0ul); |
6903074c | 2772 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
81407ca5 | 2773 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { |
0ba73cda MT |
2774 | hpa_t root = vcpu->arch.mmu.root_hpa; |
2775 | sp = page_header(root); | |
2776 | mmu_sync_children(vcpu, sp); | |
5054c0de | 2777 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
2778 | return; |
2779 | } | |
2780 | for (i = 0; i < 4; ++i) { | |
2781 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2782 | ||
8986ecc0 | 2783 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
2784 | root &= PT64_BASE_ADDR_MASK; |
2785 | sp = page_header(root); | |
2786 | mmu_sync_children(vcpu, sp); | |
2787 | } | |
2788 | } | |
6903074c | 2789 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
2790 | } |
2791 | ||
2792 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
2793 | { | |
2794 | spin_lock(&vcpu->kvm->mmu_lock); | |
2795 | mmu_sync_roots(vcpu); | |
6cffe8ca | 2796 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
2797 | } |
2798 | ||
1871c602 | 2799 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 2800 | u32 access, struct x86_exception *exception) |
6aa8b732 | 2801 | { |
ab9ae313 AK |
2802 | if (exception) |
2803 | exception->error_code = 0; | |
6aa8b732 AK |
2804 | return vaddr; |
2805 | } | |
2806 | ||
6539e738 | 2807 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
2808 | u32 access, |
2809 | struct x86_exception *exception) | |
6539e738 | 2810 | { |
ab9ae313 AK |
2811 | if (exception) |
2812 | exception->error_code = 0; | |
6539e738 JR |
2813 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access); |
2814 | } | |
2815 | ||
6aa8b732 | 2816 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 2817 | u32 error_code, bool prefault) |
6aa8b732 | 2818 | { |
e833240f | 2819 | gfn_t gfn; |
e2dec939 | 2820 | int r; |
6aa8b732 | 2821 | |
b8688d51 | 2822 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
e2dec939 AK |
2823 | r = mmu_topup_memory_caches(vcpu); |
2824 | if (r) | |
2825 | return r; | |
714b93da | 2826 | |
6aa8b732 | 2827 | ASSERT(vcpu); |
ad312c7c | 2828 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 2829 | |
e833240f | 2830 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 2831 | |
e833240f | 2832 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
78b2c54a | 2833 | error_code & PFERR_WRITE_MASK, gfn, prefault); |
6aa8b732 AK |
2834 | } |
2835 | ||
7e1fbeac | 2836 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
2837 | { |
2838 | struct kvm_arch_async_pf arch; | |
fb67e14f | 2839 | |
7c90705b | 2840 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 2841 | arch.gfn = gfn; |
c4806acd | 2842 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 2843 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 GN |
2844 | |
2845 | return kvm_setup_async_pf(vcpu, gva, gfn, &arch); | |
2846 | } | |
2847 | ||
2848 | static bool can_do_async_pf(struct kvm_vcpu *vcpu) | |
2849 | { | |
2850 | if (unlikely(!irqchip_in_kernel(vcpu->kvm) || | |
2851 | kvm_event_needs_reinjection(vcpu))) | |
2852 | return false; | |
2853 | ||
2854 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
2855 | } | |
2856 | ||
78b2c54a | 2857 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
612819c3 | 2858 | gva_t gva, pfn_t *pfn, bool write, bool *writable) |
af585b92 GN |
2859 | { |
2860 | bool async; | |
2861 | ||
612819c3 | 2862 | *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable); |
af585b92 GN |
2863 | |
2864 | if (!async) | |
2865 | return false; /* *pfn has correct page already */ | |
2866 | ||
2867 | put_page(pfn_to_page(*pfn)); | |
2868 | ||
78b2c54a | 2869 | if (!prefault && can_do_async_pf(vcpu)) { |
c9b263d2 | 2870 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
2871 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
2872 | trace_kvm_async_pf_doublefault(gva, gfn); | |
2873 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
2874 | return true; | |
2875 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
2876 | return true; | |
2877 | } | |
2878 | ||
612819c3 | 2879 | *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable); |
af585b92 GN |
2880 | |
2881 | return false; | |
2882 | } | |
2883 | ||
56028d08 | 2884 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 2885 | bool prefault) |
fb72d167 | 2886 | { |
35149e21 | 2887 | pfn_t pfn; |
fb72d167 | 2888 | int r; |
852e3c19 | 2889 | int level; |
936a5fe6 | 2890 | int force_pt_level; |
05da4558 | 2891 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 2892 | unsigned long mmu_seq; |
612819c3 MT |
2893 | int write = error_code & PFERR_WRITE_MASK; |
2894 | bool map_writable; | |
fb72d167 JR |
2895 | |
2896 | ASSERT(vcpu); | |
2897 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
2898 | ||
2899 | r = mmu_topup_memory_caches(vcpu); | |
2900 | if (r) | |
2901 | return r; | |
2902 | ||
936a5fe6 AA |
2903 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
2904 | if (likely(!force_pt_level)) { | |
2905 | level = mapping_level(vcpu, gfn); | |
2906 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
2907 | } else | |
2908 | level = PT_PAGE_TABLE_LEVEL; | |
852e3c19 | 2909 | |
e930bffe | 2910 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2911 | smp_rmb(); |
af585b92 | 2912 | |
78b2c54a | 2913 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
af585b92 GN |
2914 | return 0; |
2915 | ||
d7c55201 XG |
2916 | if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r)) |
2917 | return r; | |
2918 | ||
fb72d167 | 2919 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2920 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2921 | goto out_unlock; | |
fb72d167 | 2922 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
2923 | if (likely(!force_pt_level)) |
2924 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
612819c3 | 2925 | r = __direct_map(vcpu, gpa, write, map_writable, |
2ec4739d | 2926 | level, gfn, pfn, prefault); |
fb72d167 | 2927 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
2928 | |
2929 | return r; | |
e930bffe AA |
2930 | |
2931 | out_unlock: | |
2932 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2933 | kvm_release_pfn_clean(pfn); | |
2934 | return 0; | |
fb72d167 JR |
2935 | } |
2936 | ||
6aa8b732 AK |
2937 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
2938 | { | |
17ac10ad | 2939 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2940 | } |
2941 | ||
52fde8df JR |
2942 | static int nonpaging_init_context(struct kvm_vcpu *vcpu, |
2943 | struct kvm_mmu *context) | |
6aa8b732 | 2944 | { |
6aa8b732 AK |
2945 | context->new_cr3 = nonpaging_new_cr3; |
2946 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
2947 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
2948 | context->free = nonpaging_free; | |
e8bc217a | 2949 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2950 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 2951 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 2952 | context->root_level = 0; |
6aa8b732 | 2953 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 2954 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2955 | context->direct_map = true; |
2d48a985 | 2956 | context->nx = false; |
6aa8b732 AK |
2957 | return 0; |
2958 | } | |
2959 | ||
d835dfec | 2960 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 2961 | { |
1165f5fe | 2962 | ++vcpu->stat.tlb_flush; |
a8eeb04a | 2963 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
6aa8b732 AK |
2964 | } |
2965 | ||
2966 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
2967 | { | |
9f8fe504 | 2968 | pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu)); |
cea0f0e7 | 2969 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2970 | } |
2971 | ||
5777ed34 JR |
2972 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
2973 | { | |
9f8fe504 | 2974 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
2975 | } |
2976 | ||
6389ee94 AK |
2977 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
2978 | struct x86_exception *fault) | |
6aa8b732 | 2979 | { |
6389ee94 | 2980 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
2981 | } |
2982 | ||
6aa8b732 AK |
2983 | static void paging_free(struct kvm_vcpu *vcpu) |
2984 | { | |
2985 | nonpaging_free(vcpu); | |
2986 | } | |
2987 | ||
3241f22d | 2988 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) |
82725b20 DE |
2989 | { |
2990 | int bit7; | |
2991 | ||
2992 | bit7 = (gpte >> 7) & 1; | |
3241f22d | 2993 | return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0; |
82725b20 DE |
2994 | } |
2995 | ||
6aa8b732 AK |
2996 | #define PTTYPE 64 |
2997 | #include "paging_tmpl.h" | |
2998 | #undef PTTYPE | |
2999 | ||
3000 | #define PTTYPE 32 | |
3001 | #include "paging_tmpl.h" | |
3002 | #undef PTTYPE | |
3003 | ||
52fde8df JR |
3004 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
3005 | struct kvm_mmu *context, | |
3006 | int level) | |
82725b20 | 3007 | { |
82725b20 DE |
3008 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
3009 | u64 exb_bit_rsvd = 0; | |
3010 | ||
2d48a985 | 3011 | if (!context->nx) |
82725b20 DE |
3012 | exb_bit_rsvd = rsvd_bits(63, 63); |
3013 | switch (level) { | |
3014 | case PT32_ROOT_LEVEL: | |
3015 | /* no rsvd bits for 2 level 4K page table entries */ | |
3016 | context->rsvd_bits_mask[0][1] = 0; | |
3017 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
3018 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
3019 | ||
3020 | if (!is_pse(vcpu)) { | |
3021 | context->rsvd_bits_mask[1][1] = 0; | |
3022 | break; | |
3023 | } | |
3024 | ||
82725b20 DE |
3025 | if (is_cpuid_PSE36()) |
3026 | /* 36bits PSE 4MB page */ | |
3027 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
3028 | else | |
3029 | /* 32 bits PSE 4MB page */ | |
3030 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
3031 | break; |
3032 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
3033 | context->rsvd_bits_mask[0][2] = |
3034 | rsvd_bits(maxphyaddr, 63) | | |
3035 | rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ | |
82725b20 | 3036 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 3037 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
3038 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
3039 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
3040 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
3041 | rsvd_bits(maxphyaddr, 62) | | |
3042 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 3043 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
3044 | break; |
3045 | case PT64_ROOT_LEVEL: | |
3046 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
3047 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
3048 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | | |
3049 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
3050 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | | |
4c26b4cd | 3051 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
3052 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
3053 | rsvd_bits(maxphyaddr, 51); | |
3054 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 JR |
3055 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
3056 | rsvd_bits(maxphyaddr, 51) | | |
3057 | rsvd_bits(13, 29); | |
82725b20 | 3058 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
3059 | rsvd_bits(maxphyaddr, 51) | |
3060 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 3061 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
3062 | break; |
3063 | } | |
3064 | } | |
3065 | ||
52fde8df JR |
3066 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, |
3067 | struct kvm_mmu *context, | |
3068 | int level) | |
6aa8b732 | 3069 | { |
2d48a985 JR |
3070 | context->nx = is_nx(vcpu); |
3071 | ||
52fde8df | 3072 | reset_rsvds_bits_mask(vcpu, context, level); |
6aa8b732 AK |
3073 | |
3074 | ASSERT(is_pae(vcpu)); | |
3075 | context->new_cr3 = paging_new_cr3; | |
3076 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 3077 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 3078 | context->sync_page = paging64_sync_page; |
a7052897 | 3079 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 3080 | context->update_pte = paging64_update_pte; |
6aa8b732 | 3081 | context->free = paging_free; |
17ac10ad AK |
3082 | context->root_level = level; |
3083 | context->shadow_root_level = level; | |
17c3ba9d | 3084 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3085 | context->direct_map = false; |
6aa8b732 AK |
3086 | return 0; |
3087 | } | |
3088 | ||
52fde8df JR |
3089 | static int paging64_init_context(struct kvm_vcpu *vcpu, |
3090 | struct kvm_mmu *context) | |
17ac10ad | 3091 | { |
52fde8df | 3092 | return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
3093 | } |
3094 | ||
52fde8df JR |
3095 | static int paging32_init_context(struct kvm_vcpu *vcpu, |
3096 | struct kvm_mmu *context) | |
6aa8b732 | 3097 | { |
2d48a985 JR |
3098 | context->nx = false; |
3099 | ||
52fde8df | 3100 | reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL); |
6aa8b732 AK |
3101 | |
3102 | context->new_cr3 = paging_new_cr3; | |
3103 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
3104 | context->gva_to_gpa = paging32_gva_to_gpa; |
3105 | context->free = paging_free; | |
e8bc217a | 3106 | context->sync_page = paging32_sync_page; |
a7052897 | 3107 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 3108 | context->update_pte = paging32_update_pte; |
6aa8b732 AK |
3109 | context->root_level = PT32_ROOT_LEVEL; |
3110 | context->shadow_root_level = PT32E_ROOT_LEVEL; | |
17c3ba9d | 3111 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3112 | context->direct_map = false; |
6aa8b732 AK |
3113 | return 0; |
3114 | } | |
3115 | ||
52fde8df JR |
3116 | static int paging32E_init_context(struct kvm_vcpu *vcpu, |
3117 | struct kvm_mmu *context) | |
6aa8b732 | 3118 | { |
52fde8df | 3119 | return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
3120 | } |
3121 | ||
fb72d167 JR |
3122 | static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
3123 | { | |
14dfe855 | 3124 | struct kvm_mmu *context = vcpu->arch.walk_mmu; |
fb72d167 | 3125 | |
c445f8ef | 3126 | context->base_role.word = 0; |
fb72d167 JR |
3127 | context->new_cr3 = nonpaging_new_cr3; |
3128 | context->page_fault = tdp_page_fault; | |
3129 | context->free = nonpaging_free; | |
e8bc217a | 3130 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3131 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3132 | context->update_pte = nonpaging_update_pte; |
67253af5 | 3133 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 3134 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3135 | context->direct_map = true; |
1c97f0a0 | 3136 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 3137 | context->get_cr3 = get_cr3; |
cb659db8 | 3138 | context->inject_page_fault = kvm_inject_page_fault; |
2d48a985 | 3139 | context->nx = is_nx(vcpu); |
fb72d167 JR |
3140 | |
3141 | if (!is_paging(vcpu)) { | |
2d48a985 | 3142 | context->nx = false; |
fb72d167 JR |
3143 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
3144 | context->root_level = 0; | |
3145 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3146 | context->nx = is_nx(vcpu); |
52fde8df | 3147 | reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL); |
fb72d167 JR |
3148 | context->gva_to_gpa = paging64_gva_to_gpa; |
3149 | context->root_level = PT64_ROOT_LEVEL; | |
3150 | } else if (is_pae(vcpu)) { | |
2d48a985 | 3151 | context->nx = is_nx(vcpu); |
52fde8df | 3152 | reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL); |
fb72d167 JR |
3153 | context->gva_to_gpa = paging64_gva_to_gpa; |
3154 | context->root_level = PT32E_ROOT_LEVEL; | |
3155 | } else { | |
2d48a985 | 3156 | context->nx = false; |
52fde8df | 3157 | reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL); |
fb72d167 JR |
3158 | context->gva_to_gpa = paging32_gva_to_gpa; |
3159 | context->root_level = PT32_ROOT_LEVEL; | |
3160 | } | |
3161 | ||
3162 | return 0; | |
3163 | } | |
3164 | ||
52fde8df | 3165 | int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context) |
6aa8b732 | 3166 | { |
a770f6f2 | 3167 | int r; |
411c588d | 3168 | bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
6aa8b732 | 3169 | ASSERT(vcpu); |
ad312c7c | 3170 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
3171 | |
3172 | if (!is_paging(vcpu)) | |
52fde8df | 3173 | r = nonpaging_init_context(vcpu, context); |
a9058ecd | 3174 | else if (is_long_mode(vcpu)) |
52fde8df | 3175 | r = paging64_init_context(vcpu, context); |
6aa8b732 | 3176 | else if (is_pae(vcpu)) |
52fde8df | 3177 | r = paging32E_init_context(vcpu, context); |
6aa8b732 | 3178 | else |
52fde8df | 3179 | r = paging32_init_context(vcpu, context); |
a770f6f2 | 3180 | |
5b7e0102 | 3181 | vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu); |
f43addd4 | 3182 | vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu); |
411c588d AK |
3183 | vcpu->arch.mmu.base_role.smep_andnot_wp |
3184 | = smep && !is_write_protection(vcpu); | |
52fde8df JR |
3185 | |
3186 | return r; | |
3187 | } | |
3188 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
3189 | ||
3190 | static int init_kvm_softmmu(struct kvm_vcpu *vcpu) | |
3191 | { | |
14dfe855 | 3192 | int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu); |
52fde8df | 3193 | |
14dfe855 JR |
3194 | vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3; |
3195 | vcpu->arch.walk_mmu->get_cr3 = get_cr3; | |
3196 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; | |
a770f6f2 AK |
3197 | |
3198 | return r; | |
6aa8b732 AK |
3199 | } |
3200 | ||
02f59dc9 JR |
3201 | static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
3202 | { | |
3203 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
3204 | ||
3205 | g_context->get_cr3 = get_cr3; | |
3206 | g_context->inject_page_fault = kvm_inject_page_fault; | |
3207 | ||
3208 | /* | |
3209 | * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The | |
3210 | * translation of l2_gpa to l1_gpa addresses is done using the | |
3211 | * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa | |
3212 | * functions between mmu and nested_mmu are swapped. | |
3213 | */ | |
3214 | if (!is_paging(vcpu)) { | |
2d48a985 | 3215 | g_context->nx = false; |
02f59dc9 JR |
3216 | g_context->root_level = 0; |
3217 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
3218 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3219 | g_context->nx = is_nx(vcpu); |
02f59dc9 JR |
3220 | reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL); |
3221 | g_context->root_level = PT64_ROOT_LEVEL; | |
3222 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; | |
3223 | } else if (is_pae(vcpu)) { | |
2d48a985 | 3224 | g_context->nx = is_nx(vcpu); |
02f59dc9 JR |
3225 | reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL); |
3226 | g_context->root_level = PT32E_ROOT_LEVEL; | |
3227 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; | |
3228 | } else { | |
2d48a985 | 3229 | g_context->nx = false; |
02f59dc9 JR |
3230 | reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL); |
3231 | g_context->root_level = PT32_ROOT_LEVEL; | |
3232 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; | |
3233 | } | |
3234 | ||
3235 | return 0; | |
3236 | } | |
3237 | ||
fb72d167 JR |
3238 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) |
3239 | { | |
02f59dc9 JR |
3240 | if (mmu_is_nested(vcpu)) |
3241 | return init_kvm_nested_mmu(vcpu); | |
3242 | else if (tdp_enabled) | |
fb72d167 JR |
3243 | return init_kvm_tdp_mmu(vcpu); |
3244 | else | |
3245 | return init_kvm_softmmu(vcpu); | |
3246 | } | |
3247 | ||
6aa8b732 AK |
3248 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) |
3249 | { | |
3250 | ASSERT(vcpu); | |
62ad0755 SY |
3251 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3252 | /* mmu.free() should set root_hpa = INVALID_PAGE */ | |
ad312c7c | 3253 | vcpu->arch.mmu.free(vcpu); |
6aa8b732 AK |
3254 | } |
3255 | ||
3256 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
3257 | { |
3258 | destroy_kvm_mmu(vcpu); | |
f8f7e5ee | 3259 | return init_kvm_mmu(vcpu); |
17c3ba9d | 3260 | } |
8668a3c4 | 3261 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
3262 | |
3263 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 3264 | { |
714b93da AK |
3265 | int r; |
3266 | ||
e2dec939 | 3267 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
3268 | if (r) |
3269 | goto out; | |
8986ecc0 | 3270 | r = mmu_alloc_roots(vcpu); |
8facbbff | 3271 | spin_lock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3272 | mmu_sync_roots(vcpu); |
aaee2c94 | 3273 | spin_unlock(&vcpu->kvm->mmu_lock); |
8986ecc0 MT |
3274 | if (r) |
3275 | goto out; | |
3662cb1c | 3276 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 3277 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
3278 | out: |
3279 | return r; | |
6aa8b732 | 3280 | } |
17c3ba9d AK |
3281 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
3282 | ||
3283 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
3284 | { | |
3285 | mmu_free_roots(vcpu); | |
3286 | } | |
4b16184c | 3287 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 3288 | |
0028425f | 3289 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
3290 | struct kvm_mmu_page *sp, u64 *spte, |
3291 | const void *new) | |
0028425f | 3292 | { |
30945387 | 3293 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
3294 | ++vcpu->kvm->stat.mmu_pde_zapped; |
3295 | return; | |
30945387 | 3296 | } |
0028425f | 3297 | |
4cee5764 | 3298 | ++vcpu->kvm->stat.mmu_pte_updated; |
7c562522 | 3299 | vcpu->arch.mmu.update_pte(vcpu, sp, spte, new); |
0028425f AK |
3300 | } |
3301 | ||
79539cec AK |
3302 | static bool need_remote_flush(u64 old, u64 new) |
3303 | { | |
3304 | if (!is_shadow_present_pte(old)) | |
3305 | return false; | |
3306 | if (!is_shadow_present_pte(new)) | |
3307 | return true; | |
3308 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
3309 | return true; | |
3310 | old ^= PT64_NX_MASK; | |
3311 | new ^= PT64_NX_MASK; | |
3312 | return (old & ~new & PT64_PERM_MASK) != 0; | |
3313 | } | |
3314 | ||
0671a8e7 XG |
3315 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
3316 | bool remote_flush, bool local_flush) | |
79539cec | 3317 | { |
0671a8e7 XG |
3318 | if (zap_page) |
3319 | return; | |
3320 | ||
3321 | if (remote_flush) | |
79539cec | 3322 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 3323 | else if (local_flush) |
79539cec AK |
3324 | kvm_mmu_flush_tlb(vcpu); |
3325 | } | |
3326 | ||
12b7d28f AK |
3327 | static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu) |
3328 | { | |
ad312c7c | 3329 | u64 *spte = vcpu->arch.last_pte_updated; |
12b7d28f | 3330 | |
7b52345e | 3331 | return !!(spte && (*spte & shadow_accessed_mask)); |
12b7d28f AK |
3332 | } |
3333 | ||
1b7fcd32 AK |
3334 | static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn) |
3335 | { | |
3336 | u64 *spte = vcpu->arch.last_pte_updated; | |
3337 | ||
3338 | if (spte | |
3339 | && vcpu->arch.last_pte_gfn == gfn | |
3340 | && shadow_accessed_mask | |
3341 | && !(*spte & shadow_accessed_mask) | |
3342 | && is_shadow_present_pte(*spte)) | |
3343 | set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
3344 | } | |
3345 | ||
09072daf | 3346 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
ad218f85 MT |
3347 | const u8 *new, int bytes, |
3348 | bool guest_initiated) | |
da4a00f0 | 3349 | { |
9b7a0325 | 3350 | gfn_t gfn = gpa >> PAGE_SHIFT; |
fa1de2bf | 3351 | union kvm_mmu_page_role mask = { .word = 0 }; |
4db35314 | 3352 | struct kvm_mmu_page *sp; |
f41d335a | 3353 | struct hlist_node *node; |
d98ba053 | 3354 | LIST_HEAD(invalid_list); |
0f53b5b1 XG |
3355 | u64 entry, gentry, *spte; |
3356 | unsigned pte_size, page_offset, misaligned, quadrant, offset; | |
3357 | int level, npte, invlpg_counter, r, flooded = 0; | |
0671a8e7 XG |
3358 | bool remote_flush, local_flush, zap_page; |
3359 | ||
332b207d XG |
3360 | /* |
3361 | * If we don't have indirect shadow pages, it means no page is | |
3362 | * write-protected, so we can exit simply. | |
3363 | */ | |
3364 | if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) | |
3365 | return; | |
3366 | ||
0671a8e7 | 3367 | zap_page = remote_flush = local_flush = false; |
0f53b5b1 | 3368 | offset = offset_in_page(gpa); |
9b7a0325 | 3369 | |
b8688d51 | 3370 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); |
72016f3a | 3371 | |
08e850c6 | 3372 | invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter); |
72016f3a AK |
3373 | |
3374 | /* | |
3375 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
3376 | * as the current vcpu paging mode since we update the sptes only |
3377 | * when they have the same mode. | |
72016f3a | 3378 | */ |
08e850c6 | 3379 | if ((is_pae(vcpu) && bytes == 4) || !new) { |
72016f3a | 3380 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
08e850c6 AK |
3381 | if (is_pae(vcpu)) { |
3382 | gpa &= ~(gpa_t)7; | |
3383 | bytes = 8; | |
3384 | } | |
3385 | r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8)); | |
72016f3a AK |
3386 | if (r) |
3387 | gentry = 0; | |
08e850c6 AK |
3388 | new = (const u8 *)&gentry; |
3389 | } | |
3390 | ||
3391 | switch (bytes) { | |
3392 | case 4: | |
3393 | gentry = *(const u32 *)new; | |
3394 | break; | |
3395 | case 8: | |
3396 | gentry = *(const u64 *)new; | |
3397 | break; | |
3398 | default: | |
3399 | gentry = 0; | |
3400 | break; | |
72016f3a AK |
3401 | } |
3402 | ||
aaee2c94 | 3403 | spin_lock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
3404 | if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter) |
3405 | gentry = 0; | |
eb787d10 | 3406 | kvm_mmu_free_some_pages(vcpu); |
4cee5764 | 3407 | ++vcpu->kvm->stat.mmu_pte_write; |
8b1fe17c | 3408 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
ad218f85 | 3409 | if (guest_initiated) { |
1b7fd45c | 3410 | kvm_mmu_access_page(vcpu, gfn); |
ad218f85 MT |
3411 | if (gfn == vcpu->arch.last_pt_write_gfn |
3412 | && !last_updated_pte_accessed(vcpu)) { | |
3413 | ++vcpu->arch.last_pt_write_count; | |
3414 | if (vcpu->arch.last_pt_write_count >= 3) | |
3415 | flooded = 1; | |
3416 | } else { | |
3417 | vcpu->arch.last_pt_write_gfn = gfn; | |
3418 | vcpu->arch.last_pt_write_count = 1; | |
3419 | vcpu->arch.last_pte_updated = NULL; | |
3420 | } | |
86a5ba02 | 3421 | } |
3246af0e | 3422 | |
fa1de2bf | 3423 | mask.cr0_wp = mask.cr4_pae = mask.nxe = 1; |
f41d335a | 3424 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) { |
5b7e0102 | 3425 | pte_size = sp->role.cr4_pae ? 8 : 4; |
0e7bc4b9 | 3426 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
e925c5ba | 3427 | misaligned |= bytes < 4; |
86a5ba02 | 3428 | if (misaligned || flooded) { |
0e7bc4b9 AK |
3429 | /* |
3430 | * Misaligned accesses are too much trouble to fix | |
3431 | * up; also, they usually indicate a page is not used | |
3432 | * as a page table. | |
86a5ba02 AK |
3433 | * |
3434 | * If we're seeing too many writes to a page, | |
3435 | * it may no longer be a page table, or we may be | |
3436 | * forking, in which case it is better to unmap the | |
3437 | * page. | |
0e7bc4b9 AK |
3438 | */ |
3439 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4db35314 | 3440 | gpa, bytes, sp->role.word); |
0671a8e7 | 3441 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 3442 | &invalid_list); |
4cee5764 | 3443 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
3444 | continue; |
3445 | } | |
9b7a0325 | 3446 | page_offset = offset; |
4db35314 | 3447 | level = sp->role.level; |
ac1b714e | 3448 | npte = 1; |
5b7e0102 | 3449 | if (!sp->role.cr4_pae) { |
ac1b714e AK |
3450 | page_offset <<= 1; /* 32->64 */ |
3451 | /* | |
3452 | * A 32-bit pde maps 4MB while the shadow pdes map | |
3453 | * only 2MB. So we need to double the offset again | |
3454 | * and zap two pdes instead of one. | |
3455 | */ | |
3456 | if (level == PT32_ROOT_LEVEL) { | |
6b8d0f9b | 3457 | page_offset &= ~7; /* kill rounding error */ |
ac1b714e AK |
3458 | page_offset <<= 1; |
3459 | npte = 2; | |
3460 | } | |
fce0657f | 3461 | quadrant = page_offset >> PAGE_SHIFT; |
9b7a0325 | 3462 | page_offset &= ~PAGE_MASK; |
4db35314 | 3463 | if (quadrant != sp->role.quadrant) |
fce0657f | 3464 | continue; |
9b7a0325 | 3465 | } |
0671a8e7 | 3466 | local_flush = true; |
4db35314 | 3467 | spte = &sp->spt[page_offset / sizeof(*spte)]; |
ac1b714e | 3468 | while (npte--) { |
79539cec | 3469 | entry = *spte; |
38e3b2b2 | 3470 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf XG |
3471 | if (gentry && |
3472 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
3473 | & mask.word)) | |
7c562522 | 3474 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
0671a8e7 XG |
3475 | if (!remote_flush && need_remote_flush(entry, *spte)) |
3476 | remote_flush = true; | |
ac1b714e | 3477 | ++spte; |
9b7a0325 | 3478 | } |
9b7a0325 | 3479 | } |
0671a8e7 | 3480 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 3481 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
8b1fe17c | 3482 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 3483 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
3484 | } |
3485 | ||
a436036b AK |
3486 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
3487 | { | |
10589a46 MT |
3488 | gpa_t gpa; |
3489 | int r; | |
a436036b | 3490 | |
c5a78f2b | 3491 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
3492 | return 0; |
3493 | ||
1871c602 | 3494 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 3495 | |
aaee2c94 | 3496 | spin_lock(&vcpu->kvm->mmu_lock); |
10589a46 | 3497 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
aaee2c94 | 3498 | spin_unlock(&vcpu->kvm->mmu_lock); |
10589a46 | 3499 | return r; |
a436036b | 3500 | } |
577bdc49 | 3501 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 3502 | |
22d95b12 | 3503 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu) |
ebeace86 | 3504 | { |
d98ba053 | 3505 | LIST_HEAD(invalid_list); |
103ad25a | 3506 | |
e0df7b9f | 3507 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES && |
3b80fffe | 3508 | !list_empty(&vcpu->kvm->arch.active_mmu_pages)) { |
4db35314 | 3509 | struct kvm_mmu_page *sp; |
ebeace86 | 3510 | |
f05e70ac | 3511 | sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev, |
4db35314 | 3512 | struct kvm_mmu_page, link); |
e0df7b9f | 3513 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 3514 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 3515 | } |
aa6bd187 | 3516 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
ebeace86 | 3517 | } |
ebeace86 | 3518 | |
dc25e89e AP |
3519 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code, |
3520 | void *insn, int insn_len) | |
3067714c AK |
3521 | { |
3522 | int r; | |
3523 | enum emulation_result er; | |
3524 | ||
56028d08 | 3525 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false); |
3067714c AK |
3526 | if (r < 0) |
3527 | goto out; | |
3528 | ||
3529 | if (!r) { | |
3530 | r = 1; | |
3531 | goto out; | |
3532 | } | |
3533 | ||
b733bfb5 AK |
3534 | r = mmu_topup_memory_caches(vcpu); |
3535 | if (r) | |
3536 | goto out; | |
3537 | ||
dc25e89e | 3538 | er = x86_emulate_instruction(vcpu, cr2, 0, insn, insn_len); |
3067714c AK |
3539 | |
3540 | switch (er) { | |
3541 | case EMULATE_DONE: | |
3542 | return 1; | |
3543 | case EMULATE_DO_MMIO: | |
3544 | ++vcpu->stat.mmio_exits; | |
6d77dbfc | 3545 | /* fall through */ |
3067714c | 3546 | case EMULATE_FAIL: |
3f5d18a9 | 3547 | return 0; |
3067714c AK |
3548 | default: |
3549 | BUG(); | |
3550 | } | |
3551 | out: | |
3067714c AK |
3552 | return r; |
3553 | } | |
3554 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
3555 | ||
a7052897 MT |
3556 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
3557 | { | |
a7052897 | 3558 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
3559 | kvm_mmu_flush_tlb(vcpu); |
3560 | ++vcpu->stat.invlpg; | |
3561 | } | |
3562 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
3563 | ||
18552672 JR |
3564 | void kvm_enable_tdp(void) |
3565 | { | |
3566 | tdp_enabled = true; | |
3567 | } | |
3568 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
3569 | ||
5f4cb662 JR |
3570 | void kvm_disable_tdp(void) |
3571 | { | |
3572 | tdp_enabled = false; | |
3573 | } | |
3574 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
3575 | ||
6aa8b732 AK |
3576 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
3577 | { | |
ad312c7c | 3578 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3579 | if (vcpu->arch.mmu.lm_root != NULL) |
3580 | free_page((unsigned long)vcpu->arch.mmu.lm_root); | |
6aa8b732 AK |
3581 | } |
3582 | ||
3583 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
3584 | { | |
17ac10ad | 3585 | struct page *page; |
6aa8b732 AK |
3586 | int i; |
3587 | ||
3588 | ASSERT(vcpu); | |
3589 | ||
17ac10ad AK |
3590 | /* |
3591 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
3592 | * Therefore we need to allocate shadow page tables in the first | |
3593 | * 4GB of memory, which happens to fit the DMA32 zone. | |
3594 | */ | |
3595 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
3596 | if (!page) | |
d7fa6ab2 WY |
3597 | return -ENOMEM; |
3598 | ||
ad312c7c | 3599 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 3600 | for (i = 0; i < 4; ++i) |
ad312c7c | 3601 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 3602 | |
6aa8b732 | 3603 | return 0; |
6aa8b732 AK |
3604 | } |
3605 | ||
8018c27b | 3606 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 3607 | { |
6aa8b732 | 3608 | ASSERT(vcpu); |
ad312c7c | 3609 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3610 | |
8018c27b IM |
3611 | return alloc_mmu_pages(vcpu); |
3612 | } | |
6aa8b732 | 3613 | |
8018c27b IM |
3614 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
3615 | { | |
3616 | ASSERT(vcpu); | |
ad312c7c | 3617 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 3618 | |
8018c27b | 3619 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
3620 | } |
3621 | ||
90cb0529 | 3622 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 3623 | { |
4db35314 | 3624 | struct kvm_mmu_page *sp; |
6aa8b732 | 3625 | |
f05e70ac | 3626 | list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) { |
6aa8b732 AK |
3627 | int i; |
3628 | u64 *pt; | |
3629 | ||
291f26bc | 3630 | if (!test_bit(slot, sp->slot_bitmap)) |
6aa8b732 AK |
3631 | continue; |
3632 | ||
4db35314 | 3633 | pt = sp->spt; |
8234b22e | 3634 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { |
da8dc75f XG |
3635 | if (!is_shadow_present_pte(pt[i]) || |
3636 | !is_last_spte(pt[i], sp->role.level)) | |
3637 | continue; | |
3638 | ||
3639 | if (is_large_pte(pt[i])) { | |
c3707958 | 3640 | drop_spte(kvm, &pt[i]); |
8234b22e | 3641 | --kvm->stat.lpages; |
da8dc75f | 3642 | continue; |
8234b22e | 3643 | } |
da8dc75f | 3644 | |
6aa8b732 | 3645 | /* avoid RMW */ |
01c168ac | 3646 | if (is_writable_pte(pt[i])) |
1df9f2dc XG |
3647 | mmu_spte_update(&pt[i], |
3648 | pt[i] & ~PT_WRITABLE_MASK); | |
8234b22e | 3649 | } |
6aa8b732 | 3650 | } |
171d595d | 3651 | kvm_flush_remote_tlbs(kvm); |
6aa8b732 | 3652 | } |
37a7d8b0 | 3653 | |
90cb0529 | 3654 | void kvm_mmu_zap_all(struct kvm *kvm) |
e0fa826f | 3655 | { |
4db35314 | 3656 | struct kvm_mmu_page *sp, *node; |
d98ba053 | 3657 | LIST_HEAD(invalid_list); |
e0fa826f | 3658 | |
aaee2c94 | 3659 | spin_lock(&kvm->mmu_lock); |
3246af0e | 3660 | restart: |
f05e70ac | 3661 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) |
d98ba053 | 3662 | if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list)) |
3246af0e XG |
3663 | goto restart; |
3664 | ||
d98ba053 | 3665 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
aaee2c94 | 3666 | spin_unlock(&kvm->mmu_lock); |
e0fa826f DL |
3667 | } |
3668 | ||
d98ba053 XG |
3669 | static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm, |
3670 | struct list_head *invalid_list) | |
3ee16c81 IE |
3671 | { |
3672 | struct kvm_mmu_page *page; | |
3673 | ||
3674 | page = container_of(kvm->arch.active_mmu_pages.prev, | |
3675 | struct kvm_mmu_page, link); | |
d98ba053 | 3676 | return kvm_mmu_prepare_zap_page(kvm, page, invalid_list); |
3ee16c81 IE |
3677 | } |
3678 | ||
1495f230 | 3679 | static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc) |
3ee16c81 IE |
3680 | { |
3681 | struct kvm *kvm; | |
3682 | struct kvm *kvm_freed = NULL; | |
1495f230 | 3683 | int nr_to_scan = sc->nr_to_scan; |
45221ab6 DH |
3684 | |
3685 | if (nr_to_scan == 0) | |
3686 | goto out; | |
3ee16c81 | 3687 | |
e935b837 | 3688 | raw_spin_lock(&kvm_lock); |
3ee16c81 IE |
3689 | |
3690 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
45221ab6 | 3691 | int idx, freed_pages; |
d98ba053 | 3692 | LIST_HEAD(invalid_list); |
3ee16c81 | 3693 | |
f656ce01 | 3694 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 3695 | spin_lock(&kvm->mmu_lock); |
45221ab6 DH |
3696 | if (!kvm_freed && nr_to_scan > 0 && |
3697 | kvm->arch.n_used_mmu_pages > 0) { | |
d98ba053 XG |
3698 | freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm, |
3699 | &invalid_list); | |
3ee16c81 IE |
3700 | kvm_freed = kvm; |
3701 | } | |
3702 | nr_to_scan--; | |
3703 | ||
d98ba053 | 3704 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
3ee16c81 | 3705 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 3706 | srcu_read_unlock(&kvm->srcu, idx); |
3ee16c81 IE |
3707 | } |
3708 | if (kvm_freed) | |
3709 | list_move_tail(&kvm_freed->vm_list, &vm_list); | |
3710 | ||
e935b837 | 3711 | raw_spin_unlock(&kvm_lock); |
3ee16c81 | 3712 | |
45221ab6 DH |
3713 | out: |
3714 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); | |
3ee16c81 IE |
3715 | } |
3716 | ||
3717 | static struct shrinker mmu_shrinker = { | |
3718 | .shrink = mmu_shrink, | |
3719 | .seeks = DEFAULT_SEEKS * 10, | |
3720 | }; | |
3721 | ||
2ddfd20e | 3722 | static void mmu_destroy_caches(void) |
b5a33a75 | 3723 | { |
53c07b18 XG |
3724 | if (pte_list_desc_cache) |
3725 | kmem_cache_destroy(pte_list_desc_cache); | |
d3d25b04 AK |
3726 | if (mmu_page_header_cache) |
3727 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
3728 | } |
3729 | ||
3730 | int kvm_mmu_module_init(void) | |
3731 | { | |
53c07b18 XG |
3732 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
3733 | sizeof(struct pte_list_desc), | |
20c2df83 | 3734 | 0, 0, NULL); |
53c07b18 | 3735 | if (!pte_list_desc_cache) |
b5a33a75 AK |
3736 | goto nomem; |
3737 | ||
d3d25b04 AK |
3738 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
3739 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 3740 | 0, 0, NULL); |
d3d25b04 AK |
3741 | if (!mmu_page_header_cache) |
3742 | goto nomem; | |
3743 | ||
45bf21a8 WY |
3744 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0)) |
3745 | goto nomem; | |
3746 | ||
3ee16c81 IE |
3747 | register_shrinker(&mmu_shrinker); |
3748 | ||
b5a33a75 AK |
3749 | return 0; |
3750 | ||
3751 | nomem: | |
3ee16c81 | 3752 | mmu_destroy_caches(); |
b5a33a75 AK |
3753 | return -ENOMEM; |
3754 | } | |
3755 | ||
3ad82a7e ZX |
3756 | /* |
3757 | * Caculate mmu pages needed for kvm. | |
3758 | */ | |
3759 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
3760 | { | |
3761 | int i; | |
3762 | unsigned int nr_mmu_pages; | |
3763 | unsigned int nr_pages = 0; | |
bc6678a3 | 3764 | struct kvm_memslots *slots; |
3ad82a7e | 3765 | |
90d83dc3 LJ |
3766 | slots = kvm_memslots(kvm); |
3767 | ||
bc6678a3 MT |
3768 | for (i = 0; i < slots->nmemslots; i++) |
3769 | nr_pages += slots->memslots[i].npages; | |
3ad82a7e ZX |
3770 | |
3771 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
3772 | nr_mmu_pages = max(nr_mmu_pages, | |
3773 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
3774 | ||
3775 | return nr_mmu_pages; | |
3776 | } | |
3777 | ||
2f333bcb MT |
3778 | static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer, |
3779 | unsigned len) | |
3780 | { | |
3781 | if (len > buffer->len) | |
3782 | return NULL; | |
3783 | return buffer->ptr; | |
3784 | } | |
3785 | ||
3786 | static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer, | |
3787 | unsigned len) | |
3788 | { | |
3789 | void *ret; | |
3790 | ||
3791 | ret = pv_mmu_peek_buffer(buffer, len); | |
3792 | if (!ret) | |
3793 | return ret; | |
3794 | buffer->ptr += len; | |
3795 | buffer->len -= len; | |
3796 | buffer->processed += len; | |
3797 | return ret; | |
3798 | } | |
3799 | ||
3800 | static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu, | |
3801 | gpa_t addr, gpa_t value) | |
3802 | { | |
3803 | int bytes = 8; | |
3804 | int r; | |
3805 | ||
3806 | if (!is_long_mode(vcpu) && !is_pae(vcpu)) | |
3807 | bytes = 4; | |
3808 | ||
3809 | r = mmu_topup_memory_caches(vcpu); | |
3810 | if (r) | |
3811 | return r; | |
3812 | ||
3200f405 | 3813 | if (!emulator_write_phys(vcpu, addr, &value, bytes)) |
2f333bcb MT |
3814 | return -EFAULT; |
3815 | ||
3816 | return 1; | |
3817 | } | |
3818 | ||
3819 | static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu) | |
3820 | { | |
9f8fe504 | 3821 | (void)kvm_set_cr3(vcpu, kvm_read_cr3(vcpu)); |
2f333bcb MT |
3822 | return 1; |
3823 | } | |
3824 | ||
3825 | static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr) | |
3826 | { | |
3827 | spin_lock(&vcpu->kvm->mmu_lock); | |
3828 | mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT); | |
3829 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3830 | return 1; | |
3831 | } | |
3832 | ||
3833 | static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu, | |
3834 | struct kvm_pv_mmu_op_buffer *buffer) | |
3835 | { | |
3836 | struct kvm_mmu_op_header *header; | |
3837 | ||
3838 | header = pv_mmu_peek_buffer(buffer, sizeof *header); | |
3839 | if (!header) | |
3840 | return 0; | |
3841 | switch (header->op) { | |
3842 | case KVM_MMU_OP_WRITE_PTE: { | |
3843 | struct kvm_mmu_op_write_pte *wpte; | |
3844 | ||
3845 | wpte = pv_mmu_read_buffer(buffer, sizeof *wpte); | |
3846 | if (!wpte) | |
3847 | return 0; | |
3848 | return kvm_pv_mmu_write(vcpu, wpte->pte_phys, | |
3849 | wpte->pte_val); | |
3850 | } | |
3851 | case KVM_MMU_OP_FLUSH_TLB: { | |
3852 | struct kvm_mmu_op_flush_tlb *ftlb; | |
3853 | ||
3854 | ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb); | |
3855 | if (!ftlb) | |
3856 | return 0; | |
3857 | return kvm_pv_mmu_flush_tlb(vcpu); | |
3858 | } | |
3859 | case KVM_MMU_OP_RELEASE_PT: { | |
3860 | struct kvm_mmu_op_release_pt *rpt; | |
3861 | ||
3862 | rpt = pv_mmu_read_buffer(buffer, sizeof *rpt); | |
3863 | if (!rpt) | |
3864 | return 0; | |
3865 | return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys); | |
3866 | } | |
3867 | default: return 0; | |
3868 | } | |
3869 | } | |
3870 | ||
3871 | int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes, | |
3872 | gpa_t addr, unsigned long *ret) | |
3873 | { | |
3874 | int r; | |
6ad18fba | 3875 | struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer; |
2f333bcb | 3876 | |
6ad18fba DH |
3877 | buffer->ptr = buffer->buf; |
3878 | buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf); | |
3879 | buffer->processed = 0; | |
2f333bcb | 3880 | |
6ad18fba | 3881 | r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len); |
2f333bcb MT |
3882 | if (r) |
3883 | goto out; | |
3884 | ||
6ad18fba DH |
3885 | while (buffer->len) { |
3886 | r = kvm_pv_mmu_op_one(vcpu, buffer); | |
2f333bcb MT |
3887 | if (r < 0) |
3888 | goto out; | |
3889 | if (r == 0) | |
3890 | break; | |
3891 | } | |
3892 | ||
3893 | r = 1; | |
3894 | out: | |
6ad18fba | 3895 | *ret = buffer->processed; |
2f333bcb MT |
3896 | return r; |
3897 | } | |
3898 | ||
94d8b056 MT |
3899 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
3900 | { | |
3901 | struct kvm_shadow_walk_iterator iterator; | |
c2a2ac2b | 3902 | u64 spte; |
94d8b056 MT |
3903 | int nr_sptes = 0; |
3904 | ||
c2a2ac2b XG |
3905 | walk_shadow_page_lockless_begin(vcpu); |
3906 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
3907 | sptes[iterator.level-1] = spte; | |
94d8b056 | 3908 | nr_sptes++; |
c2a2ac2b | 3909 | if (!is_shadow_present_pte(spte)) |
94d8b056 MT |
3910 | break; |
3911 | } | |
c2a2ac2b | 3912 | walk_shadow_page_lockless_end(vcpu); |
94d8b056 MT |
3913 | |
3914 | return nr_sptes; | |
3915 | } | |
3916 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
3917 | ||
c42fffe3 XG |
3918 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
3919 | { | |
3920 | ASSERT(vcpu); | |
3921 | ||
3922 | destroy_kvm_mmu(vcpu); | |
3923 | free_mmu_pages(vcpu); | |
3924 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
3925 | } |
3926 | ||
3927 | #ifdef CONFIG_KVM_MMU_AUDIT | |
3928 | #include "mmu_audit.c" | |
3929 | #else | |
3930 | static void mmu_audit_disable(void) { } | |
3931 | #endif | |
3932 | ||
3933 | void kvm_mmu_module_exit(void) | |
3934 | { | |
3935 | mmu_destroy_caches(); | |
3936 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
3937 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
3938 | mmu_audit_disable(); |
3939 | } |