Commit | Line | Data |
---|---|---|
6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
e495606d | 25 | |
edf88417 | 26 | #include <linux/kvm_host.h> |
6aa8b732 AK |
27 | #include <linux/types.h> |
28 | #include <linux/string.h> | |
6aa8b732 AK |
29 | #include <linux/mm.h> |
30 | #include <linux/highmem.h> | |
31 | #include <linux/module.h> | |
448353ca | 32 | #include <linux/swap.h> |
05da4558 | 33 | #include <linux/hugetlb.h> |
2f333bcb | 34 | #include <linux/compiler.h> |
bc6678a3 | 35 | #include <linux/srcu.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
bf998156 | 37 | #include <linux/uaccess.h> |
6aa8b732 | 38 | |
e495606d AK |
39 | #include <asm/page.h> |
40 | #include <asm/cmpxchg.h> | |
4e542370 | 41 | #include <asm/io.h> |
13673a90 | 42 | #include <asm/vmx.h> |
6aa8b732 | 43 | |
18552672 JR |
44 | /* |
45 | * When setting this variable to true it enables Two-Dimensional-Paging | |
46 | * where the hardware walks 2 page tables: | |
47 | * 1. the guest-virtual to guest-physical | |
48 | * 2. while doing 1. it walks guest-physical to host-physical | |
49 | * If the hardware supports that we don't need to do shadow paging. | |
50 | */ | |
2f333bcb | 51 | bool tdp_enabled = false; |
18552672 | 52 | |
8b1fe17c XG |
53 | enum { |
54 | AUDIT_PRE_PAGE_FAULT, | |
55 | AUDIT_POST_PAGE_FAULT, | |
56 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
57 | AUDIT_POST_PTE_WRITE, |
58 | AUDIT_PRE_SYNC, | |
59 | AUDIT_POST_SYNC | |
8b1fe17c | 60 | }; |
37a7d8b0 | 61 | |
8b1fe17c | 62 | #undef MMU_DEBUG |
37a7d8b0 AK |
63 | |
64 | #ifdef MMU_DEBUG | |
65 | ||
66 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
67 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
68 | ||
69 | #else | |
70 | ||
71 | #define pgprintk(x...) do { } while (0) | |
72 | #define rmap_printk(x...) do { } while (0) | |
73 | ||
74 | #endif | |
75 | ||
8b1fe17c | 76 | #ifdef MMU_DEBUG |
476bc001 | 77 | static bool dbg = 0; |
6ada8cca | 78 | module_param(dbg, bool, 0644); |
37a7d8b0 | 79 | #endif |
6aa8b732 | 80 | |
d6c69ee9 YD |
81 | #ifndef MMU_DEBUG |
82 | #define ASSERT(x) do { } while (0) | |
83 | #else | |
6aa8b732 AK |
84 | #define ASSERT(x) \ |
85 | if (!(x)) { \ | |
86 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
87 | __FILE__, __LINE__, #x); \ | |
88 | } | |
d6c69ee9 | 89 | #endif |
6aa8b732 | 90 | |
957ed9ef XG |
91 | #define PTE_PREFETCH_NUM 8 |
92 | ||
6aa8b732 AK |
93 | #define PT_FIRST_AVAIL_BITS_SHIFT 9 |
94 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 | |
95 | ||
6aa8b732 AK |
96 | #define PT64_LEVEL_BITS 9 |
97 | ||
98 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 99 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 100 | |
6aa8b732 AK |
101 | #define PT64_INDEX(address, level)\ |
102 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
103 | ||
104 | ||
105 | #define PT32_LEVEL_BITS 10 | |
106 | ||
107 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 108 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 109 | |
e04da980 JR |
110 | #define PT32_LVL_OFFSET_MASK(level) \ |
111 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
112 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
113 | |
114 | #define PT32_INDEX(address, level)\ | |
115 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
116 | ||
117 | ||
27aba766 | 118 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
119 | #define PT64_DIR_BASE_ADDR_MASK \ |
120 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
121 | #define PT64_LVL_ADDR_MASK(level) \ |
122 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
123 | * PT64_LEVEL_BITS))) - 1)) | |
124 | #define PT64_LVL_OFFSET_MASK(level) \ | |
125 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
126 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
127 | |
128 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
129 | #define PT32_DIR_BASE_ADDR_MASK \ | |
130 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
131 | #define PT32_LVL_ADDR_MASK(level) \ |
132 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
133 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 134 | |
79539cec AK |
135 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
136 | | PT64_NX_MASK) | |
6aa8b732 | 137 | |
fe135d2c AK |
138 | #define ACC_EXEC_MASK 1 |
139 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
140 | #define ACC_USER_MASK PT_USER_MASK | |
141 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
142 | ||
90bb6fc5 AK |
143 | #include <trace/events/kvm.h> |
144 | ||
07420171 AK |
145 | #define CREATE_TRACE_POINTS |
146 | #include "mmutrace.h" | |
147 | ||
1403283a IE |
148 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
149 | ||
135f8c2b AK |
150 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
151 | ||
220f773a TY |
152 | /* make pte_list_desc fit well in cache line */ |
153 | #define PTE_LIST_EXT 3 | |
154 | ||
53c07b18 XG |
155 | struct pte_list_desc { |
156 | u64 *sptes[PTE_LIST_EXT]; | |
157 | struct pte_list_desc *more; | |
cd4a4e53 AK |
158 | }; |
159 | ||
2d11123a AK |
160 | struct kvm_shadow_walk_iterator { |
161 | u64 addr; | |
162 | hpa_t shadow_addr; | |
2d11123a | 163 | u64 *sptep; |
dd3bfd59 | 164 | int level; |
2d11123a AK |
165 | unsigned index; |
166 | }; | |
167 | ||
168 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
169 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
170 | shadow_walk_okay(&(_walker)); \ | |
171 | shadow_walk_next(&(_walker))) | |
172 | ||
c2a2ac2b XG |
173 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
174 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
175 | shadow_walk_okay(&(_walker)) && \ | |
176 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
177 | __shadow_walk_next(&(_walker), spte)) | |
178 | ||
53c07b18 | 179 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 180 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 181 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 182 | |
7b52345e SY |
183 | static u64 __read_mostly shadow_nx_mask; |
184 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
185 | static u64 __read_mostly shadow_user_mask; | |
186 | static u64 __read_mostly shadow_accessed_mask; | |
187 | static u64 __read_mostly shadow_dirty_mask; | |
ce88decf XG |
188 | static u64 __read_mostly shadow_mmio_mask; |
189 | ||
190 | static void mmu_spte_set(u64 *sptep, u64 spte); | |
191 | ||
192 | void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask) | |
193 | { | |
194 | shadow_mmio_mask = mmio_mask; | |
195 | } | |
196 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); | |
197 | ||
198 | static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access) | |
199 | { | |
200 | access &= ACC_WRITE_MASK | ACC_USER_MASK; | |
201 | ||
4f022648 | 202 | trace_mark_mmio_spte(sptep, gfn, access); |
ce88decf XG |
203 | mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT); |
204 | } | |
205 | ||
206 | static bool is_mmio_spte(u64 spte) | |
207 | { | |
208 | return (spte & shadow_mmio_mask) == shadow_mmio_mask; | |
209 | } | |
210 | ||
211 | static gfn_t get_mmio_spte_gfn(u64 spte) | |
212 | { | |
213 | return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT; | |
214 | } | |
215 | ||
216 | static unsigned get_mmio_spte_access(u64 spte) | |
217 | { | |
218 | return (spte & ~shadow_mmio_mask) & ~PAGE_MASK; | |
219 | } | |
220 | ||
221 | static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access) | |
222 | { | |
223 | if (unlikely(is_noslot_pfn(pfn))) { | |
224 | mark_mmio_spte(sptep, gfn, access); | |
225 | return true; | |
226 | } | |
227 | ||
228 | return false; | |
229 | } | |
c7addb90 | 230 | |
82725b20 DE |
231 | static inline u64 rsvd_bits(int s, int e) |
232 | { | |
233 | return ((1ULL << (e - s + 1)) - 1) << s; | |
234 | } | |
235 | ||
7b52345e | 236 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 237 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
238 | { |
239 | shadow_user_mask = user_mask; | |
240 | shadow_accessed_mask = accessed_mask; | |
241 | shadow_dirty_mask = dirty_mask; | |
242 | shadow_nx_mask = nx_mask; | |
243 | shadow_x_mask = x_mask; | |
244 | } | |
245 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
246 | ||
6aa8b732 AK |
247 | static int is_cpuid_PSE36(void) |
248 | { | |
249 | return 1; | |
250 | } | |
251 | ||
73b1087e AK |
252 | static int is_nx(struct kvm_vcpu *vcpu) |
253 | { | |
f6801dff | 254 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
255 | } |
256 | ||
c7addb90 AK |
257 | static int is_shadow_present_pte(u64 pte) |
258 | { | |
ce88decf | 259 | return pte & PT_PRESENT_MASK && !is_mmio_spte(pte); |
c7addb90 AK |
260 | } |
261 | ||
05da4558 MT |
262 | static int is_large_pte(u64 pte) |
263 | { | |
264 | return pte & PT_PAGE_SIZE_MASK; | |
265 | } | |
266 | ||
43a3795a | 267 | static int is_dirty_gpte(unsigned long pte) |
e3c5e7ec | 268 | { |
439e218a | 269 | return pte & PT_DIRTY_MASK; |
e3c5e7ec AK |
270 | } |
271 | ||
43a3795a | 272 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 273 | { |
4b1a80fa | 274 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
275 | } |
276 | ||
776e6633 MT |
277 | static int is_last_spte(u64 pte, int level) |
278 | { | |
279 | if (level == PT_PAGE_TABLE_LEVEL) | |
280 | return 1; | |
852e3c19 | 281 | if (is_large_pte(pte)) |
776e6633 MT |
282 | return 1; |
283 | return 0; | |
284 | } | |
285 | ||
35149e21 | 286 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 287 | { |
35149e21 | 288 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
289 | } |
290 | ||
da928521 AK |
291 | static gfn_t pse36_gfn_delta(u32 gpte) |
292 | { | |
293 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
294 | ||
295 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
296 | } | |
297 | ||
603e0651 | 298 | #ifdef CONFIG_X86_64 |
d555c333 | 299 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 300 | { |
603e0651 | 301 | *sptep = spte; |
e663ee64 AK |
302 | } |
303 | ||
603e0651 | 304 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 305 | { |
603e0651 XG |
306 | *sptep = spte; |
307 | } | |
308 | ||
309 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
310 | { | |
311 | return xchg(sptep, spte); | |
312 | } | |
c2a2ac2b XG |
313 | |
314 | static u64 __get_spte_lockless(u64 *sptep) | |
315 | { | |
316 | return ACCESS_ONCE(*sptep); | |
317 | } | |
ce88decf XG |
318 | |
319 | static bool __check_direct_spte_mmio_pf(u64 spte) | |
320 | { | |
321 | /* It is valid if the spte is zapped. */ | |
322 | return spte == 0ull; | |
323 | } | |
a9221dd5 | 324 | #else |
603e0651 XG |
325 | union split_spte { |
326 | struct { | |
327 | u32 spte_low; | |
328 | u32 spte_high; | |
329 | }; | |
330 | u64 spte; | |
331 | }; | |
a9221dd5 | 332 | |
c2a2ac2b XG |
333 | static void count_spte_clear(u64 *sptep, u64 spte) |
334 | { | |
335 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
336 | ||
337 | if (is_shadow_present_pte(spte)) | |
338 | return; | |
339 | ||
340 | /* Ensure the spte is completely set before we increase the count */ | |
341 | smp_wmb(); | |
342 | sp->clear_spte_count++; | |
343 | } | |
344 | ||
603e0651 XG |
345 | static void __set_spte(u64 *sptep, u64 spte) |
346 | { | |
347 | union split_spte *ssptep, sspte; | |
a9221dd5 | 348 | |
603e0651 XG |
349 | ssptep = (union split_spte *)sptep; |
350 | sspte = (union split_spte)spte; | |
351 | ||
352 | ssptep->spte_high = sspte.spte_high; | |
353 | ||
354 | /* | |
355 | * If we map the spte from nonpresent to present, We should store | |
356 | * the high bits firstly, then set present bit, so cpu can not | |
357 | * fetch this spte while we are setting the spte. | |
358 | */ | |
359 | smp_wmb(); | |
360 | ||
361 | ssptep->spte_low = sspte.spte_low; | |
a9221dd5 AK |
362 | } |
363 | ||
603e0651 XG |
364 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
365 | { | |
366 | union split_spte *ssptep, sspte; | |
367 | ||
368 | ssptep = (union split_spte *)sptep; | |
369 | sspte = (union split_spte)spte; | |
370 | ||
371 | ssptep->spte_low = sspte.spte_low; | |
372 | ||
373 | /* | |
374 | * If we map the spte from present to nonpresent, we should clear | |
375 | * present bit firstly to avoid vcpu fetch the old high bits. | |
376 | */ | |
377 | smp_wmb(); | |
378 | ||
379 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 380 | count_spte_clear(sptep, spte); |
603e0651 XG |
381 | } |
382 | ||
383 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
384 | { | |
385 | union split_spte *ssptep, sspte, orig; | |
386 | ||
387 | ssptep = (union split_spte *)sptep; | |
388 | sspte = (union split_spte)spte; | |
389 | ||
390 | /* xchg acts as a barrier before the setting of the high bits */ | |
391 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
392 | orig.spte_high = ssptep->spte_high; |
393 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 394 | count_spte_clear(sptep, spte); |
603e0651 XG |
395 | |
396 | return orig.spte; | |
397 | } | |
c2a2ac2b XG |
398 | |
399 | /* | |
400 | * The idea using the light way get the spte on x86_32 guest is from | |
401 | * gup_get_pte(arch/x86/mm/gup.c). | |
402 | * The difference is we can not catch the spte tlb flush if we leave | |
403 | * guest mode, so we emulate it by increase clear_spte_count when spte | |
404 | * is cleared. | |
405 | */ | |
406 | static u64 __get_spte_lockless(u64 *sptep) | |
407 | { | |
408 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
409 | union split_spte spte, *orig = (union split_spte *)sptep; | |
410 | int count; | |
411 | ||
412 | retry: | |
413 | count = sp->clear_spte_count; | |
414 | smp_rmb(); | |
415 | ||
416 | spte.spte_low = orig->spte_low; | |
417 | smp_rmb(); | |
418 | ||
419 | spte.spte_high = orig->spte_high; | |
420 | smp_rmb(); | |
421 | ||
422 | if (unlikely(spte.spte_low != orig->spte_low || | |
423 | count != sp->clear_spte_count)) | |
424 | goto retry; | |
425 | ||
426 | return spte.spte; | |
427 | } | |
ce88decf XG |
428 | |
429 | static bool __check_direct_spte_mmio_pf(u64 spte) | |
430 | { | |
431 | union split_spte sspte = (union split_spte)spte; | |
432 | u32 high_mmio_mask = shadow_mmio_mask >> 32; | |
433 | ||
434 | /* It is valid if the spte is zapped. */ | |
435 | if (spte == 0ull) | |
436 | return true; | |
437 | ||
438 | /* It is valid if the spte is being zapped. */ | |
439 | if (sspte.spte_low == 0ull && | |
440 | (sspte.spte_high & high_mmio_mask) == high_mmio_mask) | |
441 | return true; | |
442 | ||
443 | return false; | |
444 | } | |
603e0651 XG |
445 | #endif |
446 | ||
8672b721 XG |
447 | static bool spte_has_volatile_bits(u64 spte) |
448 | { | |
449 | if (!shadow_accessed_mask) | |
450 | return false; | |
451 | ||
452 | if (!is_shadow_present_pte(spte)) | |
453 | return false; | |
454 | ||
4132779b XG |
455 | if ((spte & shadow_accessed_mask) && |
456 | (!is_writable_pte(spte) || (spte & shadow_dirty_mask))) | |
8672b721 XG |
457 | return false; |
458 | ||
459 | return true; | |
460 | } | |
461 | ||
4132779b XG |
462 | static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask) |
463 | { | |
464 | return (old_spte & bit_mask) && !(new_spte & bit_mask); | |
465 | } | |
466 | ||
1df9f2dc XG |
467 | /* Rules for using mmu_spte_set: |
468 | * Set the sptep from nonpresent to present. | |
469 | * Note: the sptep being assigned *must* be either not present | |
470 | * or in a state where the hardware will not attempt to update | |
471 | * the spte. | |
472 | */ | |
473 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
474 | { | |
475 | WARN_ON(is_shadow_present_pte(*sptep)); | |
476 | __set_spte(sptep, new_spte); | |
477 | } | |
478 | ||
479 | /* Rules for using mmu_spte_update: | |
480 | * Update the state bits, it means the mapped pfn is not changged. | |
481 | */ | |
482 | static void mmu_spte_update(u64 *sptep, u64 new_spte) | |
b79b93f9 | 483 | { |
4132779b XG |
484 | u64 mask, old_spte = *sptep; |
485 | ||
486 | WARN_ON(!is_rmap_spte(new_spte)); | |
b79b93f9 | 487 | |
1df9f2dc XG |
488 | if (!is_shadow_present_pte(old_spte)) |
489 | return mmu_spte_set(sptep, new_spte); | |
490 | ||
4132779b XG |
491 | new_spte |= old_spte & shadow_dirty_mask; |
492 | ||
493 | mask = shadow_accessed_mask; | |
494 | if (is_writable_pte(old_spte)) | |
495 | mask |= shadow_dirty_mask; | |
496 | ||
497 | if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask) | |
603e0651 | 498 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 499 | else |
603e0651 | 500 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b XG |
501 | |
502 | if (!shadow_accessed_mask) | |
503 | return; | |
504 | ||
505 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask)) | |
506 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); | |
507 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask)) | |
508 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); | |
b79b93f9 AK |
509 | } |
510 | ||
1df9f2dc XG |
511 | /* |
512 | * Rules for using mmu_spte_clear_track_bits: | |
513 | * It sets the sptep from present to nonpresent, and track the | |
514 | * state bits, it is used to clear the last level sptep. | |
515 | */ | |
516 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
517 | { | |
518 | pfn_t pfn; | |
519 | u64 old_spte = *sptep; | |
520 | ||
521 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 522 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 523 | else |
603e0651 | 524 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc XG |
525 | |
526 | if (!is_rmap_spte(old_spte)) | |
527 | return 0; | |
528 | ||
529 | pfn = spte_to_pfn(old_spte); | |
530 | if (!shadow_accessed_mask || old_spte & shadow_accessed_mask) | |
531 | kvm_set_pfn_accessed(pfn); | |
532 | if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask)) | |
533 | kvm_set_pfn_dirty(pfn); | |
534 | return 1; | |
535 | } | |
536 | ||
537 | /* | |
538 | * Rules for using mmu_spte_clear_no_track: | |
539 | * Directly clear spte without caring the state bits of sptep, | |
540 | * it is used to set the upper level spte. | |
541 | */ | |
542 | static void mmu_spte_clear_no_track(u64 *sptep) | |
543 | { | |
603e0651 | 544 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
545 | } |
546 | ||
c2a2ac2b XG |
547 | static u64 mmu_spte_get_lockless(u64 *sptep) |
548 | { | |
549 | return __get_spte_lockless(sptep); | |
550 | } | |
551 | ||
552 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) | |
553 | { | |
554 | rcu_read_lock(); | |
555 | atomic_inc(&vcpu->kvm->arch.reader_counter); | |
556 | ||
557 | /* Increase the counter before walking shadow page table */ | |
558 | smp_mb__after_atomic_inc(); | |
559 | } | |
560 | ||
561 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
562 | { | |
563 | /* Decrease the counter after walking shadow page table finished */ | |
564 | smp_mb__before_atomic_dec(); | |
565 | atomic_dec(&vcpu->kvm->arch.reader_counter); | |
566 | rcu_read_unlock(); | |
567 | } | |
568 | ||
e2dec939 | 569 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 570 | struct kmem_cache *base_cache, int min) |
714b93da AK |
571 | { |
572 | void *obj; | |
573 | ||
574 | if (cache->nobjs >= min) | |
e2dec939 | 575 | return 0; |
714b93da | 576 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 577 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 578 | if (!obj) |
e2dec939 | 579 | return -ENOMEM; |
714b93da AK |
580 | cache->objects[cache->nobjs++] = obj; |
581 | } | |
e2dec939 | 582 | return 0; |
714b93da AK |
583 | } |
584 | ||
f759e2b4 XG |
585 | static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache) |
586 | { | |
587 | return cache->nobjs; | |
588 | } | |
589 | ||
e8ad9a70 XG |
590 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
591 | struct kmem_cache *cache) | |
714b93da AK |
592 | { |
593 | while (mc->nobjs) | |
e8ad9a70 | 594 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
595 | } |
596 | ||
c1158e63 | 597 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 598 | int min) |
c1158e63 | 599 | { |
842f22ed | 600 | void *page; |
c1158e63 AK |
601 | |
602 | if (cache->nobjs >= min) | |
603 | return 0; | |
604 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
842f22ed | 605 | page = (void *)__get_free_page(GFP_KERNEL); |
c1158e63 AK |
606 | if (!page) |
607 | return -ENOMEM; | |
842f22ed | 608 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
609 | } |
610 | return 0; | |
611 | } | |
612 | ||
613 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
614 | { | |
615 | while (mc->nobjs) | |
c4d198d5 | 616 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
617 | } |
618 | ||
2e3e5882 | 619 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 620 | { |
e2dec939 AK |
621 | int r; |
622 | ||
53c07b18 | 623 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 624 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
625 | if (r) |
626 | goto out; | |
ad312c7c | 627 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
628 | if (r) |
629 | goto out; | |
ad312c7c | 630 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 631 | mmu_page_header_cache, 4); |
e2dec939 AK |
632 | out: |
633 | return r; | |
714b93da AK |
634 | } |
635 | ||
636 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
637 | { | |
53c07b18 XG |
638 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
639 | pte_list_desc_cache); | |
ad312c7c | 640 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
641 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
642 | mmu_page_header_cache); | |
714b93da AK |
643 | } |
644 | ||
645 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc, | |
646 | size_t size) | |
647 | { | |
648 | void *p; | |
649 | ||
650 | BUG_ON(!mc->nobjs); | |
651 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
652 | return p; |
653 | } | |
654 | ||
53c07b18 | 655 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 656 | { |
53c07b18 XG |
657 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache, |
658 | sizeof(struct pte_list_desc)); | |
714b93da AK |
659 | } |
660 | ||
53c07b18 | 661 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 662 | { |
53c07b18 | 663 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
664 | } |
665 | ||
2032a93d LJ |
666 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
667 | { | |
668 | if (!sp->role.direct) | |
669 | return sp->gfns[index]; | |
670 | ||
671 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
672 | } | |
673 | ||
674 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
675 | { | |
676 | if (sp->role.direct) | |
677 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
678 | else | |
679 | sp->gfns[index] = gfn; | |
680 | } | |
681 | ||
05da4558 | 682 | /* |
d4dbf470 TY |
683 | * Return the pointer to the large page information for a given gfn, |
684 | * handling slots that are not large page aligned. | |
05da4558 | 685 | */ |
d4dbf470 TY |
686 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
687 | struct kvm_memory_slot *slot, | |
688 | int level) | |
05da4558 MT |
689 | { |
690 | unsigned long idx; | |
691 | ||
fb03cb6f | 692 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 693 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
694 | } |
695 | ||
696 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
697 | { | |
d25797b2 | 698 | struct kvm_memory_slot *slot; |
d4dbf470 | 699 | struct kvm_lpage_info *linfo; |
d25797b2 | 700 | int i; |
05da4558 | 701 | |
a1f4d395 | 702 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
703 | for (i = PT_DIRECTORY_LEVEL; |
704 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
705 | linfo = lpage_info_slot(gfn, slot, i); |
706 | linfo->write_count += 1; | |
d25797b2 | 707 | } |
332b207d | 708 | kvm->arch.indirect_shadow_pages++; |
05da4558 MT |
709 | } |
710 | ||
711 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
712 | { | |
d25797b2 | 713 | struct kvm_memory_slot *slot; |
d4dbf470 | 714 | struct kvm_lpage_info *linfo; |
d25797b2 | 715 | int i; |
05da4558 | 716 | |
a1f4d395 | 717 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
718 | for (i = PT_DIRECTORY_LEVEL; |
719 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
720 | linfo = lpage_info_slot(gfn, slot, i); |
721 | linfo->write_count -= 1; | |
722 | WARN_ON(linfo->write_count < 0); | |
d25797b2 | 723 | } |
332b207d | 724 | kvm->arch.indirect_shadow_pages--; |
05da4558 MT |
725 | } |
726 | ||
d25797b2 JR |
727 | static int has_wrprotected_page(struct kvm *kvm, |
728 | gfn_t gfn, | |
729 | int level) | |
05da4558 | 730 | { |
2843099f | 731 | struct kvm_memory_slot *slot; |
d4dbf470 | 732 | struct kvm_lpage_info *linfo; |
05da4558 | 733 | |
a1f4d395 | 734 | slot = gfn_to_memslot(kvm, gfn); |
05da4558 | 735 | if (slot) { |
d4dbf470 TY |
736 | linfo = lpage_info_slot(gfn, slot, level); |
737 | return linfo->write_count; | |
05da4558 MT |
738 | } |
739 | ||
740 | return 1; | |
741 | } | |
742 | ||
d25797b2 | 743 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 744 | { |
8f0b1ab6 | 745 | unsigned long page_size; |
d25797b2 | 746 | int i, ret = 0; |
05da4558 | 747 | |
8f0b1ab6 | 748 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 749 | |
d25797b2 JR |
750 | for (i = PT_PAGE_TABLE_LEVEL; |
751 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
752 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
753 | ret = i; | |
754 | else | |
755 | break; | |
756 | } | |
757 | ||
4c2155ce | 758 | return ret; |
05da4558 MT |
759 | } |
760 | ||
5d163b1c XG |
761 | static struct kvm_memory_slot * |
762 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
763 | bool no_dirty_log) | |
05da4558 MT |
764 | { |
765 | struct kvm_memory_slot *slot; | |
5d163b1c XG |
766 | |
767 | slot = gfn_to_memslot(vcpu->kvm, gfn); | |
768 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID || | |
769 | (no_dirty_log && slot->dirty_bitmap)) | |
770 | slot = NULL; | |
771 | ||
772 | return slot; | |
773 | } | |
774 | ||
775 | static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
776 | { | |
a0a8eaba | 777 | return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true); |
936a5fe6 AA |
778 | } |
779 | ||
780 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
781 | { | |
782 | int host_level, level, max_level; | |
05da4558 | 783 | |
d25797b2 JR |
784 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
785 | ||
786 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
787 | return host_level; | |
788 | ||
878403b7 SY |
789 | max_level = kvm_x86_ops->get_lpage_level() < host_level ? |
790 | kvm_x86_ops->get_lpage_level() : host_level; | |
791 | ||
792 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
793 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
794 | break; | |
d25797b2 JR |
795 | |
796 | return level - 1; | |
05da4558 MT |
797 | } |
798 | ||
290fc38d | 799 | /* |
53c07b18 | 800 | * Pte mapping structures: |
cd4a4e53 | 801 | * |
53c07b18 | 802 | * If pte_list bit zero is zero, then pte_list point to the spte. |
cd4a4e53 | 803 | * |
53c07b18 XG |
804 | * If pte_list bit zero is one, (then pte_list & ~1) points to a struct |
805 | * pte_list_desc containing more mappings. | |
53a27b39 | 806 | * |
53c07b18 | 807 | * Returns the number of pte entries before the spte was added or zero if |
53a27b39 MT |
808 | * the spte was not added. |
809 | * | |
cd4a4e53 | 810 | */ |
53c07b18 XG |
811 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
812 | unsigned long *pte_list) | |
cd4a4e53 | 813 | { |
53c07b18 | 814 | struct pte_list_desc *desc; |
53a27b39 | 815 | int i, count = 0; |
cd4a4e53 | 816 | |
53c07b18 XG |
817 | if (!*pte_list) { |
818 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); | |
819 | *pte_list = (unsigned long)spte; | |
820 | } else if (!(*pte_list & 1)) { | |
821 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); | |
822 | desc = mmu_alloc_pte_list_desc(vcpu); | |
823 | desc->sptes[0] = (u64 *)*pte_list; | |
d555c333 | 824 | desc->sptes[1] = spte; |
53c07b18 | 825 | *pte_list = (unsigned long)desc | 1; |
cb16a7b3 | 826 | ++count; |
cd4a4e53 | 827 | } else { |
53c07b18 XG |
828 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
829 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
830 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { | |
cd4a4e53 | 831 | desc = desc->more; |
53c07b18 | 832 | count += PTE_LIST_EXT; |
53a27b39 | 833 | } |
53c07b18 XG |
834 | if (desc->sptes[PTE_LIST_EXT-1]) { |
835 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
836 | desc = desc->more; |
837 | } | |
d555c333 | 838 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 839 | ++count; |
d555c333 | 840 | desc->sptes[i] = spte; |
cd4a4e53 | 841 | } |
53a27b39 | 842 | return count; |
cd4a4e53 AK |
843 | } |
844 | ||
53c07b18 XG |
845 | static void |
846 | pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc, | |
847 | int i, struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
848 | { |
849 | int j; | |
850 | ||
53c07b18 | 851 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 852 | ; |
d555c333 AK |
853 | desc->sptes[i] = desc->sptes[j]; |
854 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
855 | if (j != 0) |
856 | return; | |
857 | if (!prev_desc && !desc->more) | |
53c07b18 | 858 | *pte_list = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
859 | else |
860 | if (prev_desc) | |
861 | prev_desc->more = desc->more; | |
862 | else | |
53c07b18 XG |
863 | *pte_list = (unsigned long)desc->more | 1; |
864 | mmu_free_pte_list_desc(desc); | |
cd4a4e53 AK |
865 | } |
866 | ||
53c07b18 | 867 | static void pte_list_remove(u64 *spte, unsigned long *pte_list) |
cd4a4e53 | 868 | { |
53c07b18 XG |
869 | struct pte_list_desc *desc; |
870 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
871 | int i; |
872 | ||
53c07b18 XG |
873 | if (!*pte_list) { |
874 | printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte); | |
cd4a4e53 | 875 | BUG(); |
53c07b18 XG |
876 | } else if (!(*pte_list & 1)) { |
877 | rmap_printk("pte_list_remove: %p 1->0\n", spte); | |
878 | if ((u64 *)*pte_list != spte) { | |
879 | printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte); | |
cd4a4e53 AK |
880 | BUG(); |
881 | } | |
53c07b18 | 882 | *pte_list = 0; |
cd4a4e53 | 883 | } else { |
53c07b18 XG |
884 | rmap_printk("pte_list_remove: %p many->many\n", spte); |
885 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
cd4a4e53 AK |
886 | prev_desc = NULL; |
887 | while (desc) { | |
53c07b18 | 888 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) |
d555c333 | 889 | if (desc->sptes[i] == spte) { |
53c07b18 | 890 | pte_list_desc_remove_entry(pte_list, |
714b93da | 891 | desc, i, |
cd4a4e53 AK |
892 | prev_desc); |
893 | return; | |
894 | } | |
895 | prev_desc = desc; | |
896 | desc = desc->more; | |
897 | } | |
53c07b18 | 898 | pr_err("pte_list_remove: %p many->many\n", spte); |
cd4a4e53 AK |
899 | BUG(); |
900 | } | |
901 | } | |
902 | ||
67052b35 XG |
903 | typedef void (*pte_list_walk_fn) (u64 *spte); |
904 | static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn) | |
905 | { | |
906 | struct pte_list_desc *desc; | |
907 | int i; | |
908 | ||
909 | if (!*pte_list) | |
910 | return; | |
911 | ||
912 | if (!(*pte_list & 1)) | |
913 | return fn((u64 *)*pte_list); | |
914 | ||
915 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
916 | while (desc) { | |
917 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) | |
918 | fn(desc->sptes[i]); | |
919 | desc = desc->more; | |
920 | } | |
921 | } | |
922 | ||
9373e2c0 | 923 | static unsigned long *__gfn_to_rmap(gfn_t gfn, int level, |
9b9b1492 | 924 | struct kvm_memory_slot *slot) |
53c07b18 | 925 | { |
53c07b18 XG |
926 | struct kvm_lpage_info *linfo; |
927 | ||
53c07b18 XG |
928 | if (likely(level == PT_PAGE_TABLE_LEVEL)) |
929 | return &slot->rmap[gfn - slot->base_gfn]; | |
930 | ||
931 | linfo = lpage_info_slot(gfn, slot, level); | |
53c07b18 XG |
932 | return &linfo->rmap_pde; |
933 | } | |
934 | ||
9b9b1492 TY |
935 | /* |
936 | * Take gfn and return the reverse mapping to it. | |
937 | */ | |
938 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) | |
939 | { | |
940 | struct kvm_memory_slot *slot; | |
941 | ||
942 | slot = gfn_to_memslot(kvm, gfn); | |
9373e2c0 | 943 | return __gfn_to_rmap(gfn, level, slot); |
9b9b1492 TY |
944 | } |
945 | ||
f759e2b4 XG |
946 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
947 | { | |
948 | struct kvm_mmu_memory_cache *cache; | |
949 | ||
950 | cache = &vcpu->arch.mmu_pte_list_desc_cache; | |
951 | return mmu_memory_cache_free_objects(cache); | |
952 | } | |
953 | ||
53c07b18 XG |
954 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
955 | { | |
956 | struct kvm_mmu_page *sp; | |
957 | unsigned long *rmapp; | |
958 | ||
53c07b18 XG |
959 | sp = page_header(__pa(spte)); |
960 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
961 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); | |
962 | return pte_list_add(vcpu, spte, rmapp); | |
963 | } | |
964 | ||
53c07b18 XG |
965 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
966 | { | |
967 | struct kvm_mmu_page *sp; | |
968 | gfn_t gfn; | |
969 | unsigned long *rmapp; | |
970 | ||
971 | sp = page_header(__pa(spte)); | |
972 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
973 | rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); | |
974 | pte_list_remove(spte, rmapp); | |
975 | } | |
976 | ||
1e3f42f0 TY |
977 | /* |
978 | * Used by the following functions to iterate through the sptes linked by a | |
979 | * rmap. All fields are private and not assumed to be used outside. | |
980 | */ | |
981 | struct rmap_iterator { | |
982 | /* private fields */ | |
983 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
984 | int pos; /* index of the sptep */ | |
985 | }; | |
986 | ||
987 | /* | |
988 | * Iteration must be started by this function. This should also be used after | |
989 | * removing/dropping sptes from the rmap link because in such cases the | |
990 | * information in the itererator may not be valid. | |
991 | * | |
992 | * Returns sptep if found, NULL otherwise. | |
993 | */ | |
994 | static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter) | |
995 | { | |
996 | if (!rmap) | |
997 | return NULL; | |
998 | ||
999 | if (!(rmap & 1)) { | |
1000 | iter->desc = NULL; | |
1001 | return (u64 *)rmap; | |
1002 | } | |
1003 | ||
1004 | iter->desc = (struct pte_list_desc *)(rmap & ~1ul); | |
1005 | iter->pos = 0; | |
1006 | return iter->desc->sptes[iter->pos]; | |
1007 | } | |
1008 | ||
1009 | /* | |
1010 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1011 | * | |
1012 | * Returns sptep if found, NULL otherwise. | |
1013 | */ | |
1014 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1015 | { | |
1016 | if (iter->desc) { | |
1017 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1018 | u64 *sptep; | |
1019 | ||
1020 | ++iter->pos; | |
1021 | sptep = iter->desc->sptes[iter->pos]; | |
1022 | if (sptep) | |
1023 | return sptep; | |
1024 | } | |
1025 | ||
1026 | iter->desc = iter->desc->more; | |
1027 | ||
1028 | if (iter->desc) { | |
1029 | iter->pos = 0; | |
1030 | /* desc->sptes[0] cannot be NULL */ | |
1031 | return iter->desc->sptes[iter->pos]; | |
1032 | } | |
1033 | } | |
1034 | ||
1035 | return NULL; | |
1036 | } | |
1037 | ||
c3707958 | 1038 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1039 | { |
1df9f2dc | 1040 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1041 | rmap_remove(kvm, sptep); |
be38d276 AK |
1042 | } |
1043 | ||
a0ed4607 | 1044 | static int __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp, int level) |
98348e95 | 1045 | { |
1e3f42f0 TY |
1046 | u64 *sptep; |
1047 | struct rmap_iterator iter; | |
a0ed4607 | 1048 | int write_protected = 0; |
374cbac0 | 1049 | |
1e3f42f0 TY |
1050 | for (sptep = rmap_get_first(*rmapp, &iter); sptep;) { |
1051 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
1052 | rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); | |
a0ed4607 | 1053 | |
1e3f42f0 TY |
1054 | if (!is_writable_pte(*sptep)) { |
1055 | sptep = rmap_get_next(&iter); | |
a0ed4607 | 1056 | continue; |
1e3f42f0 | 1057 | } |
a0ed4607 TY |
1058 | |
1059 | if (level == PT_PAGE_TABLE_LEVEL) { | |
1e3f42f0 TY |
1060 | mmu_spte_update(sptep, *sptep & ~PT_WRITABLE_MASK); |
1061 | sptep = rmap_get_next(&iter); | |
a0ed4607 | 1062 | } else { |
1e3f42f0 TY |
1063 | BUG_ON(!is_large_pte(*sptep)); |
1064 | drop_spte(kvm, sptep); | |
a0ed4607 | 1065 | --kvm->stat.lpages; |
1e3f42f0 | 1066 | sptep = rmap_get_first(*rmapp, &iter); |
caa5b8a5 | 1067 | } |
a0ed4607 TY |
1068 | |
1069 | write_protected = 1; | |
374cbac0 | 1070 | } |
855149aa | 1071 | |
a0ed4607 TY |
1072 | return write_protected; |
1073 | } | |
1074 | ||
5dc99b23 TY |
1075 | /** |
1076 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages | |
1077 | * @kvm: kvm instance | |
1078 | * @slot: slot to protect | |
1079 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1080 | * @mask: indicates which pages we should protect | |
1081 | * | |
1082 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1083 | * logging we do not have any such mappings. | |
1084 | */ | |
1085 | void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, | |
1086 | struct kvm_memory_slot *slot, | |
1087 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 TY |
1088 | { |
1089 | unsigned long *rmapp; | |
a0ed4607 | 1090 | |
5dc99b23 TY |
1091 | while (mask) { |
1092 | rmapp = &slot->rmap[gfn_offset + __ffs(mask)]; | |
1093 | __rmap_write_protect(kvm, rmapp, PT_PAGE_TABLE_LEVEL); | |
05da4558 | 1094 | |
5dc99b23 TY |
1095 | /* clear the first set bit */ |
1096 | mask &= mask - 1; | |
1097 | } | |
374cbac0 AK |
1098 | } |
1099 | ||
95d4c16c TY |
1100 | static int rmap_write_protect(struct kvm *kvm, u64 gfn) |
1101 | { | |
1102 | struct kvm_memory_slot *slot; | |
5dc99b23 TY |
1103 | unsigned long *rmapp; |
1104 | int i; | |
1105 | int write_protected = 0; | |
95d4c16c TY |
1106 | |
1107 | slot = gfn_to_memslot(kvm, gfn); | |
5dc99b23 TY |
1108 | |
1109 | for (i = PT_PAGE_TABLE_LEVEL; | |
1110 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
1111 | rmapp = __gfn_to_rmap(gfn, i, slot); | |
1112 | write_protected |= __rmap_write_protect(kvm, rmapp, i); | |
1113 | } | |
1114 | ||
1115 | return write_protected; | |
95d4c16c TY |
1116 | } |
1117 | ||
8a8365c5 FD |
1118 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
1119 | unsigned long data) | |
e930bffe | 1120 | { |
1e3f42f0 TY |
1121 | u64 *sptep; |
1122 | struct rmap_iterator iter; | |
e930bffe AA |
1123 | int need_tlb_flush = 0; |
1124 | ||
1e3f42f0 TY |
1125 | while ((sptep = rmap_get_first(*rmapp, &iter))) { |
1126 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
1127 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep); | |
1128 | ||
1129 | drop_spte(kvm, sptep); | |
e930bffe AA |
1130 | need_tlb_flush = 1; |
1131 | } | |
1e3f42f0 | 1132 | |
e930bffe AA |
1133 | return need_tlb_flush; |
1134 | } | |
1135 | ||
8a8365c5 FD |
1136 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
1137 | unsigned long data) | |
3da0dd43 | 1138 | { |
1e3f42f0 TY |
1139 | u64 *sptep; |
1140 | struct rmap_iterator iter; | |
3da0dd43 | 1141 | int need_flush = 0; |
1e3f42f0 | 1142 | u64 new_spte; |
3da0dd43 IE |
1143 | pte_t *ptep = (pte_t *)data; |
1144 | pfn_t new_pfn; | |
1145 | ||
1146 | WARN_ON(pte_huge(*ptep)); | |
1147 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 TY |
1148 | |
1149 | for (sptep = rmap_get_first(*rmapp, &iter); sptep;) { | |
1150 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1151 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep); | |
1152 | ||
3da0dd43 | 1153 | need_flush = 1; |
1e3f42f0 | 1154 | |
3da0dd43 | 1155 | if (pte_write(*ptep)) { |
1e3f42f0 TY |
1156 | drop_spte(kvm, sptep); |
1157 | sptep = rmap_get_first(*rmapp, &iter); | |
3da0dd43 | 1158 | } else { |
1e3f42f0 | 1159 | new_spte = *sptep & ~PT64_BASE_ADDR_MASK; |
3da0dd43 IE |
1160 | new_spte |= (u64)new_pfn << PAGE_SHIFT; |
1161 | ||
1162 | new_spte &= ~PT_WRITABLE_MASK; | |
1163 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 1164 | new_spte &= ~shadow_accessed_mask; |
1e3f42f0 TY |
1165 | |
1166 | mmu_spte_clear_track_bits(sptep); | |
1167 | mmu_spte_set(sptep, new_spte); | |
1168 | sptep = rmap_get_next(&iter); | |
3da0dd43 IE |
1169 | } |
1170 | } | |
1e3f42f0 | 1171 | |
3da0dd43 IE |
1172 | if (need_flush) |
1173 | kvm_flush_remote_tlbs(kvm); | |
1174 | ||
1175 | return 0; | |
1176 | } | |
1177 | ||
8a8365c5 FD |
1178 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1179 | unsigned long data, | |
3da0dd43 | 1180 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, |
8a8365c5 | 1181 | unsigned long data)) |
e930bffe | 1182 | { |
be6ba0f0 | 1183 | int j; |
90bb6fc5 | 1184 | int ret; |
e930bffe | 1185 | int retval = 0; |
bc6678a3 | 1186 | struct kvm_memslots *slots; |
be6ba0f0 | 1187 | struct kvm_memory_slot *memslot; |
bc6678a3 | 1188 | |
90d83dc3 | 1189 | slots = kvm_memslots(kvm); |
e930bffe | 1190 | |
be6ba0f0 | 1191 | kvm_for_each_memslot(memslot, slots) { |
e930bffe AA |
1192 | unsigned long start = memslot->userspace_addr; |
1193 | unsigned long end; | |
1194 | ||
e930bffe AA |
1195 | end = start + (memslot->npages << PAGE_SHIFT); |
1196 | if (hva >= start && hva < end) { | |
1197 | gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT; | |
d4dbf470 | 1198 | gfn_t gfn = memslot->base_gfn + gfn_offset; |
852e3c19 | 1199 | |
90bb6fc5 | 1200 | ret = handler(kvm, &memslot->rmap[gfn_offset], data); |
852e3c19 JR |
1201 | |
1202 | for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) { | |
d4dbf470 TY |
1203 | struct kvm_lpage_info *linfo; |
1204 | ||
1205 | linfo = lpage_info_slot(gfn, memslot, | |
1206 | PT_DIRECTORY_LEVEL + j); | |
1207 | ret |= handler(kvm, &linfo->rmap_pde, data); | |
852e3c19 | 1208 | } |
90bb6fc5 AK |
1209 | trace_kvm_age_page(hva, memslot, ret); |
1210 | retval |= ret; | |
e930bffe AA |
1211 | } |
1212 | } | |
1213 | ||
1214 | return retval; | |
1215 | } | |
1216 | ||
1217 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
1218 | { | |
3da0dd43 IE |
1219 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
1220 | } | |
1221 | ||
1222 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) | |
1223 | { | |
8a8365c5 | 1224 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1225 | } |
1226 | ||
8a8365c5 FD |
1227 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
1228 | unsigned long data) | |
e930bffe | 1229 | { |
1e3f42f0 TY |
1230 | u64 *sptep; |
1231 | struct rmap_iterator iter; | |
e930bffe AA |
1232 | int young = 0; |
1233 | ||
6316e1c8 RR |
1234 | /* |
1235 | * Emulate the accessed bit for EPT, by checking if this page has | |
1236 | * an EPT mapping, and clearing it if it does. On the next access, | |
1237 | * a new EPT mapping will be established. | |
1238 | * This has some overhead, but not as much as the cost of swapping | |
1239 | * out actively used pages or breaking up actively used hugepages. | |
1240 | */ | |
534e38b4 | 1241 | if (!shadow_accessed_mask) |
6316e1c8 | 1242 | return kvm_unmap_rmapp(kvm, rmapp, data); |
534e38b4 | 1243 | |
1e3f42f0 TY |
1244 | for (sptep = rmap_get_first(*rmapp, &iter); sptep; |
1245 | sptep = rmap_get_next(&iter)) { | |
1246 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
1247 | ||
1248 | if (*sptep & PT_ACCESSED_MASK) { | |
e930bffe | 1249 | young = 1; |
1e3f42f0 | 1250 | clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)sptep); |
e930bffe | 1251 | } |
e930bffe | 1252 | } |
1e3f42f0 | 1253 | |
e930bffe AA |
1254 | return young; |
1255 | } | |
1256 | ||
8ee53820 AA |
1257 | static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
1258 | unsigned long data) | |
1259 | { | |
1e3f42f0 TY |
1260 | u64 *sptep; |
1261 | struct rmap_iterator iter; | |
8ee53820 AA |
1262 | int young = 0; |
1263 | ||
1264 | /* | |
1265 | * If there's no access bit in the secondary pte set by the | |
1266 | * hardware it's up to gup-fast/gup to set the access bit in | |
1267 | * the primary pte or in the page structure. | |
1268 | */ | |
1269 | if (!shadow_accessed_mask) | |
1270 | goto out; | |
1271 | ||
1e3f42f0 TY |
1272 | for (sptep = rmap_get_first(*rmapp, &iter); sptep; |
1273 | sptep = rmap_get_next(&iter)) { | |
1274 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
1275 | ||
1276 | if (*sptep & PT_ACCESSED_MASK) { | |
8ee53820 AA |
1277 | young = 1; |
1278 | break; | |
1279 | } | |
8ee53820 AA |
1280 | } |
1281 | out: | |
1282 | return young; | |
1283 | } | |
1284 | ||
53a27b39 MT |
1285 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1286 | ||
852e3c19 | 1287 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
1288 | { |
1289 | unsigned long *rmapp; | |
852e3c19 JR |
1290 | struct kvm_mmu_page *sp; |
1291 | ||
1292 | sp = page_header(__pa(spte)); | |
53a27b39 | 1293 | |
852e3c19 | 1294 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 1295 | |
3da0dd43 | 1296 | kvm_unmap_rmapp(vcpu->kvm, rmapp, 0); |
53a27b39 MT |
1297 | kvm_flush_remote_tlbs(vcpu->kvm); |
1298 | } | |
1299 | ||
e930bffe AA |
1300 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
1301 | { | |
3da0dd43 | 1302 | return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp); |
e930bffe AA |
1303 | } |
1304 | ||
8ee53820 AA |
1305 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1306 | { | |
1307 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1308 | } | |
1309 | ||
d6c69ee9 | 1310 | #ifdef MMU_DEBUG |
47ad8e68 | 1311 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1312 | { |
139bdb2d AK |
1313 | u64 *pos; |
1314 | u64 *end; | |
1315 | ||
47ad8e68 | 1316 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1317 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1318 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1319 | pos, *pos); |
6aa8b732 | 1320 | return 0; |
139bdb2d | 1321 | } |
6aa8b732 AK |
1322 | return 1; |
1323 | } | |
d6c69ee9 | 1324 | #endif |
6aa8b732 | 1325 | |
45221ab6 DH |
1326 | /* |
1327 | * This value is the sum of all of the kvm instances's | |
1328 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1329 | * aggregate version in order to make the slab shrinker | |
1330 | * faster | |
1331 | */ | |
1332 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
1333 | { | |
1334 | kvm->arch.n_used_mmu_pages += nr; | |
1335 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1336 | } | |
1337 | ||
bd4c86ea XG |
1338 | /* |
1339 | * Remove the sp from shadow page cache, after call it, | |
1340 | * we can not find this sp from the cache, and the shadow | |
1341 | * page table is still valid. | |
1342 | * It should be under the protection of mmu lock. | |
1343 | */ | |
1344 | static void kvm_mmu_isolate_page(struct kvm_mmu_page *sp) | |
260746c0 | 1345 | { |
4db35314 | 1346 | ASSERT(is_empty_shadow_page(sp->spt)); |
7775834a | 1347 | hlist_del(&sp->hash_link); |
2032a93d | 1348 | if (!sp->role.direct) |
842f22ed | 1349 | free_page((unsigned long)sp->gfns); |
bd4c86ea XG |
1350 | } |
1351 | ||
1352 | /* | |
1353 | * Free the shadow page table and the sp, we can do it | |
1354 | * out of the protection of mmu lock. | |
1355 | */ | |
1356 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) | |
1357 | { | |
1358 | list_del(&sp->link); | |
1359 | free_page((unsigned long)sp->spt); | |
e8ad9a70 | 1360 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1361 | } |
1362 | ||
cea0f0e7 AK |
1363 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1364 | { | |
1ae0a13d | 1365 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
1366 | } |
1367 | ||
714b93da | 1368 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1369 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1370 | { |
cea0f0e7 AK |
1371 | if (!parent_pte) |
1372 | return; | |
cea0f0e7 | 1373 | |
67052b35 | 1374 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1375 | } |
1376 | ||
4db35314 | 1377 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1378 | u64 *parent_pte) |
1379 | { | |
67052b35 | 1380 | pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1381 | } |
1382 | ||
bcdd9a93 XG |
1383 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1384 | u64 *parent_pte) | |
1385 | { | |
1386 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1387 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1388 | } |
1389 | ||
67052b35 XG |
1390 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
1391 | u64 *parent_pte, int direct) | |
ad8cfbe3 | 1392 | { |
67052b35 XG |
1393 | struct kvm_mmu_page *sp; |
1394 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, | |
1395 | sizeof *sp); | |
1396 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE); | |
1397 | if (!direct) | |
1398 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, | |
1399 | PAGE_SIZE); | |
1400 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); | |
1401 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); | |
93a5cef0 | 1402 | bitmap_zero(sp->slot_bitmap, KVM_MEM_SLOTS_NUM); |
67052b35 XG |
1403 | sp->parent_ptes = 0; |
1404 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); | |
1405 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); | |
1406 | return sp; | |
ad8cfbe3 MT |
1407 | } |
1408 | ||
67052b35 | 1409 | static void mark_unsync(u64 *spte); |
1047df1f | 1410 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1411 | { |
67052b35 | 1412 | pte_list_walk(&sp->parent_ptes, mark_unsync); |
0074ff63 MT |
1413 | } |
1414 | ||
67052b35 | 1415 | static void mark_unsync(u64 *spte) |
0074ff63 | 1416 | { |
67052b35 | 1417 | struct kvm_mmu_page *sp; |
1047df1f | 1418 | unsigned int index; |
0074ff63 | 1419 | |
67052b35 | 1420 | sp = page_header(__pa(spte)); |
1047df1f XG |
1421 | index = spte - sp->spt; |
1422 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1423 | return; |
1047df1f | 1424 | if (sp->unsync_children++) |
0074ff63 | 1425 | return; |
1047df1f | 1426 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1427 | } |
1428 | ||
e8bc217a | 1429 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1430 | struct kvm_mmu_page *sp) |
e8bc217a MT |
1431 | { |
1432 | return 1; | |
1433 | } | |
1434 | ||
a7052897 MT |
1435 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1436 | { | |
1437 | } | |
1438 | ||
0f53b5b1 XG |
1439 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1440 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 1441 | const void *pte) |
0f53b5b1 XG |
1442 | { |
1443 | WARN_ON(1); | |
1444 | } | |
1445 | ||
60c8aec6 MT |
1446 | #define KVM_PAGE_ARRAY_NR 16 |
1447 | ||
1448 | struct kvm_mmu_pages { | |
1449 | struct mmu_page_and_offset { | |
1450 | struct kvm_mmu_page *sp; | |
1451 | unsigned int idx; | |
1452 | } page[KVM_PAGE_ARRAY_NR]; | |
1453 | unsigned int nr; | |
1454 | }; | |
1455 | ||
cded19f3 HE |
1456 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1457 | int idx) | |
4731d4c7 | 1458 | { |
60c8aec6 | 1459 | int i; |
4731d4c7 | 1460 | |
60c8aec6 MT |
1461 | if (sp->unsync) |
1462 | for (i=0; i < pvec->nr; i++) | |
1463 | if (pvec->page[i].sp == sp) | |
1464 | return 0; | |
1465 | ||
1466 | pvec->page[pvec->nr].sp = sp; | |
1467 | pvec->page[pvec->nr].idx = idx; | |
1468 | pvec->nr++; | |
1469 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1470 | } | |
1471 | ||
1472 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1473 | struct kvm_mmu_pages *pvec) | |
1474 | { | |
1475 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1476 | |
37178b8b | 1477 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 1478 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1479 | u64 ent = sp->spt[i]; |
1480 | ||
7a8f1a74 XG |
1481 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) |
1482 | goto clear_child_bitmap; | |
1483 | ||
1484 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1485 | ||
1486 | if (child->unsync_children) { | |
1487 | if (mmu_pages_add(pvec, child, i)) | |
1488 | return -ENOSPC; | |
1489 | ||
1490 | ret = __mmu_unsync_walk(child, pvec); | |
1491 | if (!ret) | |
1492 | goto clear_child_bitmap; | |
1493 | else if (ret > 0) | |
1494 | nr_unsync_leaf += ret; | |
1495 | else | |
1496 | return ret; | |
1497 | } else if (child->unsync) { | |
1498 | nr_unsync_leaf++; | |
1499 | if (mmu_pages_add(pvec, child, i)) | |
1500 | return -ENOSPC; | |
1501 | } else | |
1502 | goto clear_child_bitmap; | |
1503 | ||
1504 | continue; | |
1505 | ||
1506 | clear_child_bitmap: | |
1507 | __clear_bit(i, sp->unsync_child_bitmap); | |
1508 | sp->unsync_children--; | |
1509 | WARN_ON((int)sp->unsync_children < 0); | |
4731d4c7 MT |
1510 | } |
1511 | ||
4731d4c7 | 1512 | |
60c8aec6 MT |
1513 | return nr_unsync_leaf; |
1514 | } | |
1515 | ||
1516 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1517 | struct kvm_mmu_pages *pvec) | |
1518 | { | |
1519 | if (!sp->unsync_children) | |
1520 | return 0; | |
1521 | ||
1522 | mmu_pages_add(pvec, sp, 0); | |
1523 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1524 | } |
1525 | ||
4731d4c7 MT |
1526 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1527 | { | |
1528 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1529 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1530 | sp->unsync = 0; |
1531 | --kvm->stat.mmu_unsync; | |
1532 | } | |
1533 | ||
7775834a XG |
1534 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1535 | struct list_head *invalid_list); | |
1536 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1537 | struct list_head *invalid_list); | |
4731d4c7 | 1538 | |
f41d335a XG |
1539 | #define for_each_gfn_sp(kvm, sp, gfn, pos) \ |
1540 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1541 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1542 | if ((sp)->gfn != (gfn)) {} else | |
1543 | ||
f41d335a XG |
1544 | #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \ |
1545 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1546 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1547 | if ((sp)->gfn != (gfn) || (sp)->role.direct || \ | |
1548 | (sp)->role.invalid) {} else | |
1549 | ||
f918b443 | 1550 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1551 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1552 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1553 | { |
5b7e0102 | 1554 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1555 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1556 | return 1; |
1557 | } | |
1558 | ||
f918b443 | 1559 | if (clear_unsync) |
1d9dc7e0 | 1560 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1561 | |
a4a8e6f7 | 1562 | if (vcpu->arch.mmu.sync_page(vcpu, sp)) { |
d98ba053 | 1563 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1564 | return 1; |
1565 | } | |
1566 | ||
1567 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1568 | return 0; |
1569 | } | |
1570 | ||
1d9dc7e0 XG |
1571 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1572 | struct kvm_mmu_page *sp) | |
1573 | { | |
d98ba053 | 1574 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1575 | int ret; |
1576 | ||
d98ba053 | 1577 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1578 | if (ret) |
d98ba053 XG |
1579 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1580 | ||
1d9dc7e0 XG |
1581 | return ret; |
1582 | } | |
1583 | ||
e37fa785 XG |
1584 | #ifdef CONFIG_KVM_MMU_AUDIT |
1585 | #include "mmu_audit.c" | |
1586 | #else | |
1587 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
1588 | static void mmu_audit_disable(void) { } | |
1589 | #endif | |
1590 | ||
d98ba053 XG |
1591 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1592 | struct list_head *invalid_list) | |
1d9dc7e0 | 1593 | { |
d98ba053 | 1594 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1595 | } |
1596 | ||
9f1a122f XG |
1597 | /* @gfn should be write-protected at the call site */ |
1598 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1599 | { | |
9f1a122f | 1600 | struct kvm_mmu_page *s; |
f41d335a | 1601 | struct hlist_node *node; |
d98ba053 | 1602 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1603 | bool flush = false; |
1604 | ||
f41d335a | 1605 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1606 | if (!s->unsync) |
9f1a122f XG |
1607 | continue; |
1608 | ||
1609 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
a4a8e6f7 | 1610 | kvm_unlink_unsync_page(vcpu->kvm, s); |
9f1a122f | 1611 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || |
a4a8e6f7 | 1612 | (vcpu->arch.mmu.sync_page(vcpu, s))) { |
d98ba053 | 1613 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1614 | continue; |
1615 | } | |
9f1a122f XG |
1616 | flush = true; |
1617 | } | |
1618 | ||
d98ba053 | 1619 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f XG |
1620 | if (flush) |
1621 | kvm_mmu_flush_tlb(vcpu); | |
1622 | } | |
1623 | ||
60c8aec6 MT |
1624 | struct mmu_page_path { |
1625 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1626 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1627 | }; |
1628 | ||
60c8aec6 MT |
1629 | #define for_each_sp(pvec, sp, parents, i) \ |
1630 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1631 | sp = pvec.page[i].sp; \ | |
1632 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1633 | i = mmu_pages_next(&pvec, &parents, i)) | |
1634 | ||
cded19f3 HE |
1635 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1636 | struct mmu_page_path *parents, | |
1637 | int i) | |
60c8aec6 MT |
1638 | { |
1639 | int n; | |
1640 | ||
1641 | for (n = i+1; n < pvec->nr; n++) { | |
1642 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1643 | ||
1644 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1645 | parents->idx[0] = pvec->page[n].idx; | |
1646 | return n; | |
1647 | } | |
1648 | ||
1649 | parents->parent[sp->role.level-2] = sp; | |
1650 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1651 | } | |
1652 | ||
1653 | return n; | |
1654 | } | |
1655 | ||
cded19f3 | 1656 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1657 | { |
60c8aec6 MT |
1658 | struct kvm_mmu_page *sp; |
1659 | unsigned int level = 0; | |
1660 | ||
1661 | do { | |
1662 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1663 | |
60c8aec6 MT |
1664 | sp = parents->parent[level]; |
1665 | if (!sp) | |
1666 | return; | |
1667 | ||
1668 | --sp->unsync_children; | |
1669 | WARN_ON((int)sp->unsync_children < 0); | |
1670 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1671 | level++; | |
1672 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1673 | } |
1674 | ||
60c8aec6 MT |
1675 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1676 | struct mmu_page_path *parents, | |
1677 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1678 | { |
60c8aec6 MT |
1679 | parents->parent[parent->role.level-1] = NULL; |
1680 | pvec->nr = 0; | |
1681 | } | |
4731d4c7 | 1682 | |
60c8aec6 MT |
1683 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1684 | struct kvm_mmu_page *parent) | |
1685 | { | |
1686 | int i; | |
1687 | struct kvm_mmu_page *sp; | |
1688 | struct mmu_page_path parents; | |
1689 | struct kvm_mmu_pages pages; | |
d98ba053 | 1690 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
1691 | |
1692 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1693 | while (mmu_unsync_walk(parent, &pages)) { | |
b1a36821 MT |
1694 | int protected = 0; |
1695 | ||
1696 | for_each_sp(pages, sp, parents, i) | |
1697 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1698 | ||
1699 | if (protected) | |
1700 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1701 | ||
60c8aec6 | 1702 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 1703 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1704 | mmu_pages_clear_parents(&parents); |
1705 | } | |
d98ba053 | 1706 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 1707 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1708 | kvm_mmu_pages_init(parent, &parents, &pages); |
1709 | } | |
4731d4c7 MT |
1710 | } |
1711 | ||
c3707958 XG |
1712 | static void init_shadow_page_table(struct kvm_mmu_page *sp) |
1713 | { | |
1714 | int i; | |
1715 | ||
1716 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1717 | sp->spt[i] = 0ull; | |
1718 | } | |
1719 | ||
a30f47cb XG |
1720 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
1721 | { | |
1722 | sp->write_flooding_count = 0; | |
1723 | } | |
1724 | ||
1725 | static void clear_sp_write_flooding_count(u64 *spte) | |
1726 | { | |
1727 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
1728 | ||
1729 | __clear_sp_write_flooding_count(sp); | |
1730 | } | |
1731 | ||
cea0f0e7 AK |
1732 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1733 | gfn_t gfn, | |
1734 | gva_t gaddr, | |
1735 | unsigned level, | |
f6e2c02b | 1736 | int direct, |
41074d07 | 1737 | unsigned access, |
f7d9c7b7 | 1738 | u64 *parent_pte) |
cea0f0e7 AK |
1739 | { |
1740 | union kvm_mmu_page_role role; | |
cea0f0e7 | 1741 | unsigned quadrant; |
9f1a122f | 1742 | struct kvm_mmu_page *sp; |
f41d335a | 1743 | struct hlist_node *node; |
9f1a122f | 1744 | bool need_sync = false; |
cea0f0e7 | 1745 | |
a770f6f2 | 1746 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1747 | role.level = level; |
f6e2c02b | 1748 | role.direct = direct; |
84b0c8c6 | 1749 | if (role.direct) |
5b7e0102 | 1750 | role.cr4_pae = 0; |
41074d07 | 1751 | role.access = access; |
c5a78f2b JR |
1752 | if (!vcpu->arch.mmu.direct_map |
1753 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
1754 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1755 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1756 | role.quadrant = quadrant; | |
1757 | } | |
f41d335a | 1758 | for_each_gfn_sp(vcpu->kvm, sp, gfn, node) { |
7ae680eb XG |
1759 | if (!need_sync && sp->unsync) |
1760 | need_sync = true; | |
4731d4c7 | 1761 | |
7ae680eb XG |
1762 | if (sp->role.word != role.word) |
1763 | continue; | |
4731d4c7 | 1764 | |
7ae680eb XG |
1765 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
1766 | break; | |
e02aa901 | 1767 | |
7ae680eb XG |
1768 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
1769 | if (sp->unsync_children) { | |
a8eeb04a | 1770 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
7ae680eb XG |
1771 | kvm_mmu_mark_parents_unsync(sp); |
1772 | } else if (sp->unsync) | |
1773 | kvm_mmu_mark_parents_unsync(sp); | |
e02aa901 | 1774 | |
a30f47cb | 1775 | __clear_sp_write_flooding_count(sp); |
7ae680eb XG |
1776 | trace_kvm_mmu_get_page(sp, false); |
1777 | return sp; | |
1778 | } | |
dfc5aa00 | 1779 | ++vcpu->kvm->stat.mmu_cache_miss; |
2032a93d | 1780 | sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct); |
4db35314 AK |
1781 | if (!sp) |
1782 | return sp; | |
4db35314 AK |
1783 | sp->gfn = gfn; |
1784 | sp->role = role; | |
7ae680eb XG |
1785 | hlist_add_head(&sp->hash_link, |
1786 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 1787 | if (!direct) { |
b1a36821 MT |
1788 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1789 | kvm_flush_remote_tlbs(vcpu->kvm); | |
9f1a122f XG |
1790 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
1791 | kvm_sync_pages(vcpu, gfn); | |
1792 | ||
4731d4c7 MT |
1793 | account_shadowed(vcpu->kvm, gfn); |
1794 | } | |
c3707958 | 1795 | init_shadow_page_table(sp); |
f691fe1d | 1796 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1797 | return sp; |
cea0f0e7 AK |
1798 | } |
1799 | ||
2d11123a AK |
1800 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1801 | struct kvm_vcpu *vcpu, u64 addr) | |
1802 | { | |
1803 | iterator->addr = addr; | |
1804 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1805 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 JR |
1806 | |
1807 | if (iterator->level == PT64_ROOT_LEVEL && | |
1808 | vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL && | |
1809 | !vcpu->arch.mmu.direct_map) | |
1810 | --iterator->level; | |
1811 | ||
2d11123a AK |
1812 | if (iterator->level == PT32E_ROOT_LEVEL) { |
1813 | iterator->shadow_addr | |
1814 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
1815 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
1816 | --iterator->level; | |
1817 | if (!iterator->shadow_addr) | |
1818 | iterator->level = 0; | |
1819 | } | |
1820 | } | |
1821 | ||
1822 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
1823 | { | |
1824 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
1825 | return false; | |
4d88954d | 1826 | |
2d11123a AK |
1827 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
1828 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
1829 | return true; | |
1830 | } | |
1831 | ||
c2a2ac2b XG |
1832 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
1833 | u64 spte) | |
2d11123a | 1834 | { |
c2a2ac2b | 1835 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
1836 | iterator->level = 0; |
1837 | return; | |
1838 | } | |
1839 | ||
c2a2ac2b | 1840 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
1841 | --iterator->level; |
1842 | } | |
1843 | ||
c2a2ac2b XG |
1844 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
1845 | { | |
1846 | return __shadow_walk_next(iterator, *iterator->sptep); | |
1847 | } | |
1848 | ||
32ef26a3 AK |
1849 | static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp) |
1850 | { | |
1851 | u64 spte; | |
1852 | ||
1853 | spte = __pa(sp->spt) | |
1854 | | PT_PRESENT_MASK | PT_ACCESSED_MASK | |
1855 | | PT_WRITABLE_MASK | PT_USER_MASK; | |
1df9f2dc | 1856 | mmu_spte_set(sptep, spte); |
32ef26a3 AK |
1857 | } |
1858 | ||
a3aa51cf AK |
1859 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) |
1860 | { | |
1861 | if (is_large_pte(*sptep)) { | |
c3707958 | 1862 | drop_spte(vcpu->kvm, sptep); |
6addd1aa | 1863 | --vcpu->kvm->stat.lpages; |
a3aa51cf AK |
1864 | kvm_flush_remote_tlbs(vcpu->kvm); |
1865 | } | |
1866 | } | |
1867 | ||
a357bd22 AK |
1868 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1869 | unsigned direct_access) | |
1870 | { | |
1871 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
1872 | struct kvm_mmu_page *child; | |
1873 | ||
1874 | /* | |
1875 | * For the direct sp, if the guest pte's dirty bit | |
1876 | * changed form clean to dirty, it will corrupt the | |
1877 | * sp's access: allow writable in the read-only sp, | |
1878 | * so we should update the spte at this point to get | |
1879 | * a new sp with the correct access. | |
1880 | */ | |
1881 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
1882 | if (child->role.access == direct_access) | |
1883 | return; | |
1884 | ||
bcdd9a93 | 1885 | drop_parent_pte(child, sptep); |
a357bd22 AK |
1886 | kvm_flush_remote_tlbs(vcpu->kvm); |
1887 | } | |
1888 | } | |
1889 | ||
505aef8f | 1890 | static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
38e3b2b2 XG |
1891 | u64 *spte) |
1892 | { | |
1893 | u64 pte; | |
1894 | struct kvm_mmu_page *child; | |
1895 | ||
1896 | pte = *spte; | |
1897 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 1898 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 1899 | drop_spte(kvm, spte); |
505aef8f XG |
1900 | if (is_large_pte(pte)) |
1901 | --kvm->stat.lpages; | |
1902 | } else { | |
38e3b2b2 | 1903 | child = page_header(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 1904 | drop_parent_pte(child, spte); |
38e3b2b2 | 1905 | } |
505aef8f XG |
1906 | return true; |
1907 | } | |
1908 | ||
1909 | if (is_mmio_spte(pte)) | |
ce88decf | 1910 | mmu_spte_clear_no_track(spte); |
c3707958 | 1911 | |
505aef8f | 1912 | return false; |
38e3b2b2 XG |
1913 | } |
1914 | ||
90cb0529 | 1915 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 1916 | struct kvm_mmu_page *sp) |
a436036b | 1917 | { |
697fe2e2 | 1918 | unsigned i; |
697fe2e2 | 1919 | |
38e3b2b2 XG |
1920 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
1921 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
1922 | } |
1923 | ||
4db35314 | 1924 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1925 | { |
4db35314 | 1926 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
1927 | } |
1928 | ||
31aa2b44 | 1929 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 1930 | { |
1e3f42f0 TY |
1931 | u64 *sptep; |
1932 | struct rmap_iterator iter; | |
a436036b | 1933 | |
1e3f42f0 TY |
1934 | while ((sptep = rmap_get_first(sp->parent_ptes, &iter))) |
1935 | drop_parent_pte(sp, sptep); | |
31aa2b44 AK |
1936 | } |
1937 | ||
60c8aec6 | 1938 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
1939 | struct kvm_mmu_page *parent, |
1940 | struct list_head *invalid_list) | |
4731d4c7 | 1941 | { |
60c8aec6 MT |
1942 | int i, zapped = 0; |
1943 | struct mmu_page_path parents; | |
1944 | struct kvm_mmu_pages pages; | |
4731d4c7 | 1945 | |
60c8aec6 | 1946 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1947 | return 0; |
60c8aec6 MT |
1948 | |
1949 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1950 | while (mmu_unsync_walk(parent, &pages)) { | |
1951 | struct kvm_mmu_page *sp; | |
1952 | ||
1953 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 1954 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 1955 | mmu_pages_clear_parents(&parents); |
77662e00 | 1956 | zapped++; |
60c8aec6 | 1957 | } |
60c8aec6 MT |
1958 | kvm_mmu_pages_init(parent, &parents, &pages); |
1959 | } | |
1960 | ||
1961 | return zapped; | |
4731d4c7 MT |
1962 | } |
1963 | ||
7775834a XG |
1964 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1965 | struct list_head *invalid_list) | |
31aa2b44 | 1966 | { |
4731d4c7 | 1967 | int ret; |
f691fe1d | 1968 | |
7775834a | 1969 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 1970 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 1971 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 1972 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 1973 | kvm_mmu_unlink_parents(kvm, sp); |
f6e2c02b | 1974 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 1975 | unaccount_shadowed(kvm, sp->gfn); |
4731d4c7 MT |
1976 | if (sp->unsync) |
1977 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 1978 | if (!sp->root_count) { |
54a4f023 GJ |
1979 | /* Count self */ |
1980 | ret++; | |
7775834a | 1981 | list_move(&sp->link, invalid_list); |
aa6bd187 | 1982 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 1983 | } else { |
5b5c6a5a | 1984 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
2e53d63a MT |
1985 | kvm_reload_remote_mmus(kvm); |
1986 | } | |
7775834a XG |
1987 | |
1988 | sp->role.invalid = 1; | |
4731d4c7 | 1989 | return ret; |
a436036b AK |
1990 | } |
1991 | ||
c2a2ac2b XG |
1992 | static void kvm_mmu_isolate_pages(struct list_head *invalid_list) |
1993 | { | |
1994 | struct kvm_mmu_page *sp; | |
1995 | ||
1996 | list_for_each_entry(sp, invalid_list, link) | |
1997 | kvm_mmu_isolate_page(sp); | |
1998 | } | |
1999 | ||
2000 | static void free_pages_rcu(struct rcu_head *head) | |
2001 | { | |
2002 | struct kvm_mmu_page *next, *sp; | |
2003 | ||
2004 | sp = container_of(head, struct kvm_mmu_page, rcu); | |
2005 | while (sp) { | |
2006 | if (!list_empty(&sp->link)) | |
2007 | next = list_first_entry(&sp->link, | |
2008 | struct kvm_mmu_page, link); | |
2009 | else | |
2010 | next = NULL; | |
2011 | kvm_mmu_free_page(sp); | |
2012 | sp = next; | |
2013 | } | |
2014 | } | |
2015 | ||
7775834a XG |
2016 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2017 | struct list_head *invalid_list) | |
2018 | { | |
2019 | struct kvm_mmu_page *sp; | |
2020 | ||
2021 | if (list_empty(invalid_list)) | |
2022 | return; | |
2023 | ||
2024 | kvm_flush_remote_tlbs(kvm); | |
2025 | ||
c2a2ac2b XG |
2026 | if (atomic_read(&kvm->arch.reader_counter)) { |
2027 | kvm_mmu_isolate_pages(invalid_list); | |
2028 | sp = list_first_entry(invalid_list, struct kvm_mmu_page, link); | |
2029 | list_del_init(invalid_list); | |
4f022648 XG |
2030 | |
2031 | trace_kvm_mmu_delay_free_pages(sp); | |
c2a2ac2b XG |
2032 | call_rcu(&sp->rcu, free_pages_rcu); |
2033 | return; | |
2034 | } | |
2035 | ||
7775834a XG |
2036 | do { |
2037 | sp = list_first_entry(invalid_list, struct kvm_mmu_page, link); | |
2038 | WARN_ON(!sp->role.invalid || sp->root_count); | |
bd4c86ea | 2039 | kvm_mmu_isolate_page(sp); |
aa6bd187 | 2040 | kvm_mmu_free_page(sp); |
7775834a XG |
2041 | } while (!list_empty(invalid_list)); |
2042 | ||
2043 | } | |
2044 | ||
82ce2c96 IE |
2045 | /* |
2046 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2047 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2048 | */ |
49d5ca26 | 2049 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 2050 | { |
d98ba053 | 2051 | LIST_HEAD(invalid_list); |
82ce2c96 IE |
2052 | /* |
2053 | * If we set the number of mmu pages to be smaller be than the | |
2054 | * number of actived pages , we must to free some mmu pages before we | |
2055 | * change the value | |
2056 | */ | |
2057 | ||
49d5ca26 DH |
2058 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
2059 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages && | |
77662e00 | 2060 | !list_empty(&kvm->arch.active_mmu_pages)) { |
82ce2c96 IE |
2061 | struct kvm_mmu_page *page; |
2062 | ||
f05e70ac | 2063 | page = container_of(kvm->arch.active_mmu_pages.prev, |
82ce2c96 | 2064 | struct kvm_mmu_page, link); |
80b63faf | 2065 | kvm_mmu_prepare_zap_page(kvm, page, &invalid_list); |
82ce2c96 | 2066 | } |
aa6bd187 | 2067 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 2068 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2069 | } |
82ce2c96 | 2070 | |
49d5ca26 | 2071 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
82ce2c96 IE |
2072 | } |
2073 | ||
1cb3f3ae | 2074 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2075 | { |
4db35314 | 2076 | struct kvm_mmu_page *sp; |
f41d335a | 2077 | struct hlist_node *node; |
d98ba053 | 2078 | LIST_HEAD(invalid_list); |
a436036b AK |
2079 | int r; |
2080 | ||
9ad17b10 | 2081 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2082 | r = 0; |
1cb3f3ae | 2083 | spin_lock(&kvm->mmu_lock); |
f41d335a | 2084 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { |
9ad17b10 | 2085 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2086 | sp->role.word); |
2087 | r = 1; | |
f41d335a | 2088 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2089 | } |
d98ba053 | 2090 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2091 | spin_unlock(&kvm->mmu_lock); |
2092 | ||
a436036b | 2093 | return r; |
cea0f0e7 | 2094 | } |
1cb3f3ae | 2095 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2096 | |
38c335f1 | 2097 | static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn) |
6aa8b732 | 2098 | { |
bc6678a3 | 2099 | int slot = memslot_id(kvm, gfn); |
4db35314 | 2100 | struct kvm_mmu_page *sp = page_header(__pa(pte)); |
6aa8b732 | 2101 | |
291f26bc | 2102 | __set_bit(slot, sp->slot_bitmap); |
6aa8b732 AK |
2103 | } |
2104 | ||
74be52e3 SY |
2105 | /* |
2106 | * The function is based on mtrr_type_lookup() in | |
2107 | * arch/x86/kernel/cpu/mtrr/generic.c | |
2108 | */ | |
2109 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
2110 | u64 start, u64 end) | |
2111 | { | |
2112 | int i; | |
2113 | u64 base, mask; | |
2114 | u8 prev_match, curr_match; | |
2115 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
2116 | ||
2117 | if (!mtrr_state->enabled) | |
2118 | return 0xFF; | |
2119 | ||
2120 | /* Make end inclusive end, instead of exclusive */ | |
2121 | end--; | |
2122 | ||
2123 | /* Look in fixed ranges. Just return the type as per start */ | |
2124 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
2125 | int idx; | |
2126 | ||
2127 | if (start < 0x80000) { | |
2128 | idx = 0; | |
2129 | idx += (start >> 16); | |
2130 | return mtrr_state->fixed_ranges[idx]; | |
2131 | } else if (start < 0xC0000) { | |
2132 | idx = 1 * 8; | |
2133 | idx += ((start - 0x80000) >> 14); | |
2134 | return mtrr_state->fixed_ranges[idx]; | |
2135 | } else if (start < 0x1000000) { | |
2136 | idx = 3 * 8; | |
2137 | idx += ((start - 0xC0000) >> 12); | |
2138 | return mtrr_state->fixed_ranges[idx]; | |
2139 | } | |
2140 | } | |
2141 | ||
2142 | /* | |
2143 | * Look in variable ranges | |
2144 | * Look of multiple ranges matching this address and pick type | |
2145 | * as per MTRR precedence | |
2146 | */ | |
2147 | if (!(mtrr_state->enabled & 2)) | |
2148 | return mtrr_state->def_type; | |
2149 | ||
2150 | prev_match = 0xFF; | |
2151 | for (i = 0; i < num_var_ranges; ++i) { | |
2152 | unsigned short start_state, end_state; | |
2153 | ||
2154 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
2155 | continue; | |
2156 | ||
2157 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
2158 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
2159 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
2160 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
2161 | ||
2162 | start_state = ((start & mask) == (base & mask)); | |
2163 | end_state = ((end & mask) == (base & mask)); | |
2164 | if (start_state != end_state) | |
2165 | return 0xFE; | |
2166 | ||
2167 | if ((start & mask) != (base & mask)) | |
2168 | continue; | |
2169 | ||
2170 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
2171 | if (prev_match == 0xFF) { | |
2172 | prev_match = curr_match; | |
2173 | continue; | |
2174 | } | |
2175 | ||
2176 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
2177 | curr_match == MTRR_TYPE_UNCACHABLE) | |
2178 | return MTRR_TYPE_UNCACHABLE; | |
2179 | ||
2180 | if ((prev_match == MTRR_TYPE_WRBACK && | |
2181 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
2182 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
2183 | curr_match == MTRR_TYPE_WRBACK)) { | |
2184 | prev_match = MTRR_TYPE_WRTHROUGH; | |
2185 | curr_match = MTRR_TYPE_WRTHROUGH; | |
2186 | } | |
2187 | ||
2188 | if (prev_match != curr_match) | |
2189 | return MTRR_TYPE_UNCACHABLE; | |
2190 | } | |
2191 | ||
2192 | if (prev_match != 0xFF) | |
2193 | return prev_match; | |
2194 | ||
2195 | return mtrr_state->def_type; | |
2196 | } | |
2197 | ||
4b12f0de | 2198 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
2199 | { |
2200 | u8 mtrr; | |
2201 | ||
2202 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
2203 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
2204 | if (mtrr == 0xfe || mtrr == 0xff) | |
2205 | mtrr = MTRR_TYPE_WRBACK; | |
2206 | return mtrr; | |
2207 | } | |
4b12f0de | 2208 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 2209 | |
9cf5cf5a XG |
2210 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
2211 | { | |
2212 | trace_kvm_mmu_unsync_page(sp); | |
2213 | ++vcpu->kvm->stat.mmu_unsync; | |
2214 | sp->unsync = 1; | |
2215 | ||
2216 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2217 | } |
2218 | ||
2219 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 2220 | { |
4731d4c7 | 2221 | struct kvm_mmu_page *s; |
f41d335a | 2222 | struct hlist_node *node; |
9cf5cf5a | 2223 | |
f41d335a | 2224 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 2225 | if (s->unsync) |
4731d4c7 | 2226 | continue; |
9cf5cf5a XG |
2227 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
2228 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 2229 | } |
4731d4c7 MT |
2230 | } |
2231 | ||
2232 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
2233 | bool can_unsync) | |
2234 | { | |
9cf5cf5a | 2235 | struct kvm_mmu_page *s; |
f41d335a | 2236 | struct hlist_node *node; |
9cf5cf5a XG |
2237 | bool need_unsync = false; |
2238 | ||
f41d335a | 2239 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
36a2e677 XG |
2240 | if (!can_unsync) |
2241 | return 1; | |
2242 | ||
9cf5cf5a | 2243 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2244 | return 1; |
9cf5cf5a XG |
2245 | |
2246 | if (!need_unsync && !s->unsync) { | |
9cf5cf5a XG |
2247 | need_unsync = true; |
2248 | } | |
4731d4c7 | 2249 | } |
9cf5cf5a XG |
2250 | if (need_unsync) |
2251 | kvm_unsync_pages(vcpu, gfn); | |
4731d4c7 MT |
2252 | return 0; |
2253 | } | |
2254 | ||
d555c333 | 2255 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd | 2256 | unsigned pte_access, int user_fault, |
640d9b0d | 2257 | int write_fault, int level, |
c2d0ee46 | 2258 | gfn_t gfn, pfn_t pfn, bool speculative, |
9bdbba13 | 2259 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2260 | { |
b330aa0c | 2261 | u64 spte, entry = *sptep; |
1e73f9dd | 2262 | int ret = 0; |
64d4d521 | 2263 | |
ce88decf XG |
2264 | if (set_mmio_spte(sptep, gfn, pfn, pte_access)) |
2265 | return 0; | |
2266 | ||
982c2565 | 2267 | spte = PT_PRESENT_MASK; |
947da538 | 2268 | if (!speculative) |
3201b5d9 | 2269 | spte |= shadow_accessed_mask; |
640d9b0d | 2270 | |
7b52345e SY |
2271 | if (pte_access & ACC_EXEC_MASK) |
2272 | spte |= shadow_x_mask; | |
2273 | else | |
2274 | spte |= shadow_nx_mask; | |
1c4f1fd6 | 2275 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2276 | spte |= shadow_user_mask; |
852e3c19 | 2277 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2278 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2279 | if (tdp_enabled) |
4b12f0de SY |
2280 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
2281 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 2282 | |
9bdbba13 | 2283 | if (host_writable) |
1403283a | 2284 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2285 | else |
2286 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2287 | |
35149e21 | 2288 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 AK |
2289 | |
2290 | if ((pte_access & ACC_WRITE_MASK) | |
c5a78f2b JR |
2291 | || (!vcpu->arch.mmu.direct_map && write_fault |
2292 | && !is_write_protection(vcpu) && !user_fault)) { | |
1c4f1fd6 | 2293 | |
852e3c19 JR |
2294 | if (level > PT_PAGE_TABLE_LEVEL && |
2295 | has_wrprotected_page(vcpu->kvm, gfn, level)) { | |
38187c83 | 2296 | ret = 1; |
c3707958 | 2297 | drop_spte(vcpu->kvm, sptep); |
be38d276 | 2298 | goto done; |
38187c83 MT |
2299 | } |
2300 | ||
1c4f1fd6 | 2301 | spte |= PT_WRITABLE_MASK; |
1c4f1fd6 | 2302 | |
c5a78f2b | 2303 | if (!vcpu->arch.mmu.direct_map |
411c588d | 2304 | && !(pte_access & ACC_WRITE_MASK)) { |
69325a12 | 2305 | spte &= ~PT_USER_MASK; |
411c588d AK |
2306 | /* |
2307 | * If we converted a user page to a kernel page, | |
2308 | * so that the kernel can write to it when cr0.wp=0, | |
2309 | * then we should prevent the kernel from executing it | |
2310 | * if SMEP is enabled. | |
2311 | */ | |
2312 | if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)) | |
2313 | spte |= PT64_NX_MASK; | |
2314 | } | |
69325a12 | 2315 | |
ecc5589f MT |
2316 | /* |
2317 | * Optimization: for pte sync, if spte was writable the hash | |
2318 | * lookup is unnecessary (and expensive). Write protection | |
2319 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2320 | * Same reasoning can be applied to dirty page accounting. | |
2321 | */ | |
8dae4445 | 2322 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2323 | goto set_pte; |
2324 | ||
4731d4c7 | 2325 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2326 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2327 | __func__, gfn); |
1e73f9dd | 2328 | ret = 1; |
1c4f1fd6 | 2329 | pte_access &= ~ACC_WRITE_MASK; |
8dae4445 | 2330 | if (is_writable_pte(spte)) |
1c4f1fd6 | 2331 | spte &= ~PT_WRITABLE_MASK; |
1c4f1fd6 AK |
2332 | } |
2333 | } | |
2334 | ||
1c4f1fd6 AK |
2335 | if (pte_access & ACC_WRITE_MASK) |
2336 | mark_page_dirty(vcpu->kvm, gfn); | |
2337 | ||
38187c83 | 2338 | set_pte: |
1df9f2dc | 2339 | mmu_spte_update(sptep, spte); |
b330aa0c XG |
2340 | /* |
2341 | * If we overwrite a writable spte with a read-only one we | |
2342 | * should flush remote TLBs. Otherwise rmap_write_protect | |
2343 | * will find a read-only spte, even though the writable spte | |
2344 | * might be cached on a CPU's TLB. | |
2345 | */ | |
2346 | if (is_writable_pte(entry) && !is_writable_pte(*sptep)) | |
2347 | kvm_flush_remote_tlbs(vcpu->kvm); | |
be38d276 | 2348 | done: |
1e73f9dd MT |
2349 | return ret; |
2350 | } | |
2351 | ||
d555c333 | 2352 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd | 2353 | unsigned pt_access, unsigned pte_access, |
640d9b0d | 2354 | int user_fault, int write_fault, |
b90a0e6c | 2355 | int *emulate, int level, gfn_t gfn, |
1403283a | 2356 | pfn_t pfn, bool speculative, |
9bdbba13 | 2357 | bool host_writable) |
1e73f9dd MT |
2358 | { |
2359 | int was_rmapped = 0; | |
53a27b39 | 2360 | int rmap_count; |
1e73f9dd MT |
2361 | |
2362 | pgprintk("%s: spte %llx access %x write_fault %d" | |
9ad17b10 | 2363 | " user_fault %d gfn %llx\n", |
d555c333 | 2364 | __func__, *sptep, pt_access, |
1e73f9dd MT |
2365 | write_fault, user_fault, gfn); |
2366 | ||
d555c333 | 2367 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
2368 | /* |
2369 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2370 | * the parent of the now unreachable PTE. | |
2371 | */ | |
852e3c19 JR |
2372 | if (level > PT_PAGE_TABLE_LEVEL && |
2373 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2374 | struct kvm_mmu_page *child; |
d555c333 | 2375 | u64 pte = *sptep; |
1e73f9dd MT |
2376 | |
2377 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 2378 | drop_parent_pte(child, sptep); |
3be2264b | 2379 | kvm_flush_remote_tlbs(vcpu->kvm); |
d555c333 | 2380 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2381 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2382 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2383 | drop_spte(vcpu->kvm, sptep); |
91546356 | 2384 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2385 | } else |
2386 | was_rmapped = 1; | |
1e73f9dd | 2387 | } |
852e3c19 | 2388 | |
d555c333 | 2389 | if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault, |
640d9b0d | 2390 | level, gfn, pfn, speculative, true, |
9bdbba13 | 2391 | host_writable)) { |
1e73f9dd | 2392 | if (write_fault) |
b90a0e6c | 2393 | *emulate = 1; |
5304efde | 2394 | kvm_mmu_flush_tlb(vcpu); |
a378b4e6 | 2395 | } |
1e73f9dd | 2396 | |
ce88decf XG |
2397 | if (unlikely(is_mmio_spte(*sptep) && emulate)) |
2398 | *emulate = 1; | |
2399 | ||
d555c333 | 2400 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2401 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2402 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
2403 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
2404 | *sptep, sptep); | |
d555c333 | 2405 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2406 | ++vcpu->kvm->stat.lpages; |
2407 | ||
ffb61bb3 XG |
2408 | if (is_shadow_present_pte(*sptep)) { |
2409 | page_header_update_slot(vcpu->kvm, sptep, gfn); | |
2410 | if (!was_rmapped) { | |
2411 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2412 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2413 | rmap_recycle(vcpu, sptep, gfn); | |
2414 | } | |
1c4f1fd6 | 2415 | } |
9ed5520d | 2416 | kvm_release_pfn_clean(pfn); |
1c4f1fd6 AK |
2417 | } |
2418 | ||
6aa8b732 AK |
2419 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
2420 | { | |
2421 | } | |
2422 | ||
957ed9ef XG |
2423 | static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
2424 | bool no_dirty_log) | |
2425 | { | |
2426 | struct kvm_memory_slot *slot; | |
2427 | unsigned long hva; | |
2428 | ||
5d163b1c | 2429 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
957ed9ef | 2430 | if (!slot) { |
fce92dce XG |
2431 | get_page(fault_page); |
2432 | return page_to_pfn(fault_page); | |
957ed9ef XG |
2433 | } |
2434 | ||
2435 | hva = gfn_to_hva_memslot(slot, gfn); | |
2436 | ||
2437 | return hva_to_pfn_atomic(vcpu->kvm, hva); | |
2438 | } | |
2439 | ||
2440 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2441 | struct kvm_mmu_page *sp, | |
2442 | u64 *start, u64 *end) | |
2443 | { | |
2444 | struct page *pages[PTE_PREFETCH_NUM]; | |
2445 | unsigned access = sp->role.access; | |
2446 | int i, ret; | |
2447 | gfn_t gfn; | |
2448 | ||
2449 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
5d163b1c | 2450 | if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK)) |
957ed9ef XG |
2451 | return -1; |
2452 | ||
2453 | ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start); | |
2454 | if (ret <= 0) | |
2455 | return -1; | |
2456 | ||
2457 | for (i = 0; i < ret; i++, gfn++, start++) | |
2458 | mmu_set_spte(vcpu, start, ACC_ALL, | |
640d9b0d | 2459 | access, 0, 0, NULL, |
957ed9ef XG |
2460 | sp->role.level, gfn, |
2461 | page_to_pfn(pages[i]), true, true); | |
2462 | ||
2463 | return 0; | |
2464 | } | |
2465 | ||
2466 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2467 | struct kvm_mmu_page *sp, u64 *sptep) | |
2468 | { | |
2469 | u64 *spte, *start = NULL; | |
2470 | int i; | |
2471 | ||
2472 | WARN_ON(!sp->role.direct); | |
2473 | ||
2474 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2475 | spte = sp->spt + i; | |
2476 | ||
2477 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2478 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2479 | if (!start) |
2480 | continue; | |
2481 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2482 | break; | |
2483 | start = NULL; | |
2484 | } else if (!start) | |
2485 | start = spte; | |
2486 | } | |
2487 | } | |
2488 | ||
2489 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2490 | { | |
2491 | struct kvm_mmu_page *sp; | |
2492 | ||
2493 | /* | |
2494 | * Since it's no accessed bit on EPT, it's no way to | |
2495 | * distinguish between actually accessed translations | |
2496 | * and prefetched, so disable pte prefetch if EPT is | |
2497 | * enabled. | |
2498 | */ | |
2499 | if (!shadow_accessed_mask) | |
2500 | return; | |
2501 | ||
2502 | sp = page_header(__pa(sptep)); | |
2503 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2504 | return; | |
2505 | ||
2506 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2507 | } | |
2508 | ||
9f652d21 | 2509 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
2ec4739d XG |
2510 | int map_writable, int level, gfn_t gfn, pfn_t pfn, |
2511 | bool prefault) | |
140754bc | 2512 | { |
9f652d21 | 2513 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2514 | struct kvm_mmu_page *sp; |
b90a0e6c | 2515 | int emulate = 0; |
140754bc | 2516 | gfn_t pseudo_gfn; |
6aa8b732 | 2517 | |
9f652d21 | 2518 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2519 | if (iterator.level == level) { |
612819c3 MT |
2520 | unsigned pte_access = ACC_ALL; |
2521 | ||
612819c3 | 2522 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access, |
b90a0e6c | 2523 | 0, write, &emulate, |
2ec4739d | 2524 | level, gfn, pfn, prefault, map_writable); |
957ed9ef | 2525 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2526 | ++vcpu->stat.pf_fixed; |
2527 | break; | |
6aa8b732 AK |
2528 | } |
2529 | ||
c3707958 | 2530 | if (!is_shadow_present_pte(*iterator.sptep)) { |
c9fa0b3b LJ |
2531 | u64 base_addr = iterator.addr; |
2532 | ||
2533 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2534 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 AK |
2535 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
2536 | iterator.level - 1, | |
2537 | 1, ACC_ALL, iterator.sptep); | |
2538 | if (!sp) { | |
2539 | pgprintk("nonpaging_map: ENOMEM\n"); | |
2540 | kvm_release_pfn_clean(pfn); | |
2541 | return -ENOMEM; | |
2542 | } | |
140754bc | 2543 | |
1df9f2dc XG |
2544 | mmu_spte_set(iterator.sptep, |
2545 | __pa(sp->spt) | |
2546 | | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
2547 | | shadow_user_mask | shadow_x_mask | |
2548 | | shadow_accessed_mask); | |
9f652d21 AK |
2549 | } |
2550 | } | |
b90a0e6c | 2551 | return emulate; |
6aa8b732 AK |
2552 | } |
2553 | ||
77db5cbd | 2554 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2555 | { |
77db5cbd HY |
2556 | siginfo_t info; |
2557 | ||
2558 | info.si_signo = SIGBUS; | |
2559 | info.si_errno = 0; | |
2560 | info.si_code = BUS_MCEERR_AR; | |
2561 | info.si_addr = (void __user *)address; | |
2562 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 2563 | |
77db5cbd | 2564 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
2565 | } |
2566 | ||
d7c55201 | 2567 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn) |
bf998156 HY |
2568 | { |
2569 | kvm_release_pfn_clean(pfn); | |
2570 | if (is_hwpoison_pfn(pfn)) { | |
bebb106a | 2571 | kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current); |
bf998156 | 2572 | return 0; |
d7c55201 | 2573 | } |
edba23e5 | 2574 | |
d7c55201 | 2575 | return -EFAULT; |
bf998156 HY |
2576 | } |
2577 | ||
936a5fe6 AA |
2578 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
2579 | gfn_t *gfnp, pfn_t *pfnp, int *levelp) | |
2580 | { | |
2581 | pfn_t pfn = *pfnp; | |
2582 | gfn_t gfn = *gfnp; | |
2583 | int level = *levelp; | |
2584 | ||
2585 | /* | |
2586 | * Check if it's a transparent hugepage. If this would be an | |
2587 | * hugetlbfs page, level wouldn't be set to | |
2588 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
2589 | * here. | |
2590 | */ | |
2591 | if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) && | |
2592 | level == PT_PAGE_TABLE_LEVEL && | |
2593 | PageTransCompound(pfn_to_page(pfn)) && | |
2594 | !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) { | |
2595 | unsigned long mask; | |
2596 | /* | |
2597 | * mmu_notifier_retry was successful and we hold the | |
2598 | * mmu_lock here, so the pmd can't become splitting | |
2599 | * from under us, and in turn | |
2600 | * __split_huge_page_refcount() can't run from under | |
2601 | * us and we can safely transfer the refcount from | |
2602 | * PG_tail to PG_head as we switch the pfn to tail to | |
2603 | * head. | |
2604 | */ | |
2605 | *levelp = level = PT_DIRECTORY_LEVEL; | |
2606 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
2607 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2608 | if (pfn & mask) { | |
2609 | gfn &= ~mask; | |
2610 | *gfnp = gfn; | |
2611 | kvm_release_pfn_clean(pfn); | |
2612 | pfn &= ~mask; | |
2613 | if (!get_page_unless_zero(pfn_to_page(pfn))) | |
2614 | BUG(); | |
2615 | *pfnp = pfn; | |
2616 | } | |
2617 | } | |
2618 | } | |
2619 | ||
d7c55201 XG |
2620 | static bool mmu_invalid_pfn(pfn_t pfn) |
2621 | { | |
ce88decf | 2622 | return unlikely(is_invalid_pfn(pfn)); |
d7c55201 XG |
2623 | } |
2624 | ||
2625 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, | |
2626 | pfn_t pfn, unsigned access, int *ret_val) | |
2627 | { | |
2628 | bool ret = true; | |
2629 | ||
2630 | /* The pfn is invalid, report the error! */ | |
2631 | if (unlikely(is_invalid_pfn(pfn))) { | |
2632 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); | |
2633 | goto exit; | |
2634 | } | |
2635 | ||
ce88decf | 2636 | if (unlikely(is_noslot_pfn(pfn))) |
d7c55201 | 2637 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); |
d7c55201 XG |
2638 | |
2639 | ret = false; | |
2640 | exit: | |
2641 | return ret; | |
2642 | } | |
2643 | ||
78b2c54a | 2644 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
060c2abe XG |
2645 | gva_t gva, pfn_t *pfn, bool write, bool *writable); |
2646 | ||
2647 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn, | |
78b2c54a | 2648 | bool prefault) |
10589a46 MT |
2649 | { |
2650 | int r; | |
852e3c19 | 2651 | int level; |
936a5fe6 | 2652 | int force_pt_level; |
35149e21 | 2653 | pfn_t pfn; |
e930bffe | 2654 | unsigned long mmu_seq; |
612819c3 | 2655 | bool map_writable; |
aaee2c94 | 2656 | |
936a5fe6 AA |
2657 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
2658 | if (likely(!force_pt_level)) { | |
2659 | level = mapping_level(vcpu, gfn); | |
2660 | /* | |
2661 | * This path builds a PAE pagetable - so we can map | |
2662 | * 2mb pages at maximum. Therefore check if the level | |
2663 | * is larger than that. | |
2664 | */ | |
2665 | if (level > PT_DIRECTORY_LEVEL) | |
2666 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 2667 | |
936a5fe6 AA |
2668 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
2669 | } else | |
2670 | level = PT_PAGE_TABLE_LEVEL; | |
05da4558 | 2671 | |
e930bffe | 2672 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2673 | smp_rmb(); |
060c2abe | 2674 | |
78b2c54a | 2675 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
060c2abe | 2676 | return 0; |
aaee2c94 | 2677 | |
d7c55201 XG |
2678 | if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r)) |
2679 | return r; | |
d196e343 | 2680 | |
aaee2c94 | 2681 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2682 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2683 | goto out_unlock; | |
eb787d10 | 2684 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
2685 | if (likely(!force_pt_level)) |
2686 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
2ec4739d XG |
2687 | r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn, |
2688 | prefault); | |
aaee2c94 MT |
2689 | spin_unlock(&vcpu->kvm->mmu_lock); |
2690 | ||
aaee2c94 | 2691 | |
10589a46 | 2692 | return r; |
e930bffe AA |
2693 | |
2694 | out_unlock: | |
2695 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2696 | kvm_release_pfn_clean(pfn); | |
2697 | return 0; | |
10589a46 MT |
2698 | } |
2699 | ||
2700 | ||
17ac10ad AK |
2701 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
2702 | { | |
2703 | int i; | |
4db35314 | 2704 | struct kvm_mmu_page *sp; |
d98ba053 | 2705 | LIST_HEAD(invalid_list); |
17ac10ad | 2706 | |
ad312c7c | 2707 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 2708 | return; |
aaee2c94 | 2709 | spin_lock(&vcpu->kvm->mmu_lock); |
81407ca5 JR |
2710 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL && |
2711 | (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL || | |
2712 | vcpu->arch.mmu.direct_map)) { | |
ad312c7c | 2713 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 2714 | |
4db35314 AK |
2715 | sp = page_header(root); |
2716 | --sp->root_count; | |
d98ba053 XG |
2717 | if (!sp->root_count && sp->role.invalid) { |
2718 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
2719 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
2720 | } | |
ad312c7c | 2721 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
aaee2c94 | 2722 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad AK |
2723 | return; |
2724 | } | |
17ac10ad | 2725 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2726 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2727 | |
417726a3 | 2728 | if (root) { |
417726a3 | 2729 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2730 | sp = page_header(root); |
2731 | --sp->root_count; | |
2e53d63a | 2732 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
2733 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2734 | &invalid_list); | |
417726a3 | 2735 | } |
ad312c7c | 2736 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2737 | } |
d98ba053 | 2738 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 2739 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2740 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2741 | } |
2742 | ||
8986ecc0 MT |
2743 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2744 | { | |
2745 | int ret = 0; | |
2746 | ||
2747 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 2748 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
2749 | ret = 1; |
2750 | } | |
2751 | ||
2752 | return ret; | |
2753 | } | |
2754 | ||
651dd37a JR |
2755 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
2756 | { | |
2757 | struct kvm_mmu_page *sp; | |
7ebaf15e | 2758 | unsigned i; |
651dd37a JR |
2759 | |
2760 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2761 | spin_lock(&vcpu->kvm->mmu_lock); | |
2762 | kvm_mmu_free_some_pages(vcpu); | |
2763 | sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, | |
2764 | 1, ACC_ALL, NULL); | |
2765 | ++sp->root_count; | |
2766 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2767 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
2768 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
2769 | for (i = 0; i < 4; ++i) { | |
2770 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2771 | ||
2772 | ASSERT(!VALID_PAGE(root)); | |
2773 | spin_lock(&vcpu->kvm->mmu_lock); | |
2774 | kvm_mmu_free_some_pages(vcpu); | |
649497d1 AK |
2775 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
2776 | i << 30, | |
651dd37a JR |
2777 | PT32_ROOT_LEVEL, 1, ACC_ALL, |
2778 | NULL); | |
2779 | root = __pa(sp->spt); | |
2780 | ++sp->root_count; | |
2781 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2782 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 2783 | } |
6292757f | 2784 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
2785 | } else |
2786 | BUG(); | |
2787 | ||
2788 | return 0; | |
2789 | } | |
2790 | ||
2791 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 2792 | { |
4db35314 | 2793 | struct kvm_mmu_page *sp; |
81407ca5 JR |
2794 | u64 pdptr, pm_mask; |
2795 | gfn_t root_gfn; | |
2796 | int i; | |
3bb65a22 | 2797 | |
5777ed34 | 2798 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 2799 | |
651dd37a JR |
2800 | if (mmu_check_root(vcpu, root_gfn)) |
2801 | return 1; | |
2802 | ||
2803 | /* | |
2804 | * Do we shadow a long mode page table? If so we need to | |
2805 | * write-protect the guests page table root. | |
2806 | */ | |
2807 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { | |
ad312c7c | 2808 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad AK |
2809 | |
2810 | ASSERT(!VALID_PAGE(root)); | |
651dd37a | 2811 | |
8facbbff | 2812 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2813 | kvm_mmu_free_some_pages(vcpu); |
651dd37a JR |
2814 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, |
2815 | 0, ACC_ALL, NULL); | |
4db35314 AK |
2816 | root = __pa(sp->spt); |
2817 | ++sp->root_count; | |
8facbbff | 2818 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2819 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 2820 | return 0; |
17ac10ad | 2821 | } |
f87f9288 | 2822 | |
651dd37a JR |
2823 | /* |
2824 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
2825 | * or a PAE 3-level page table. In either case we need to be aware that |
2826 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 2827 | */ |
81407ca5 JR |
2828 | pm_mask = PT_PRESENT_MASK; |
2829 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) | |
2830 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; | |
2831 | ||
17ac10ad | 2832 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2833 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
2834 | |
2835 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 2836 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 2837 | pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i); |
43a3795a | 2838 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 2839 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
2840 | continue; |
2841 | } | |
6de4f3ad | 2842 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
2843 | if (mmu_check_root(vcpu, root_gfn)) |
2844 | return 1; | |
5a7388c2 | 2845 | } |
8facbbff | 2846 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2847 | kvm_mmu_free_some_pages(vcpu); |
4db35314 | 2848 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
651dd37a | 2849 | PT32_ROOT_LEVEL, 0, |
f7d9c7b7 | 2850 | ACC_ALL, NULL); |
4db35314 AK |
2851 | root = __pa(sp->spt); |
2852 | ++sp->root_count; | |
8facbbff AK |
2853 | spin_unlock(&vcpu->kvm->mmu_lock); |
2854 | ||
81407ca5 | 2855 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 2856 | } |
6292757f | 2857 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
2858 | |
2859 | /* | |
2860 | * If we shadow a 32 bit page table with a long mode page | |
2861 | * table we enter this path. | |
2862 | */ | |
2863 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2864 | if (vcpu->arch.mmu.lm_root == NULL) { | |
2865 | /* | |
2866 | * The additional page necessary for this is only | |
2867 | * allocated on demand. | |
2868 | */ | |
2869 | ||
2870 | u64 *lm_root; | |
2871 | ||
2872 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
2873 | if (lm_root == NULL) | |
2874 | return 1; | |
2875 | ||
2876 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
2877 | ||
2878 | vcpu->arch.mmu.lm_root = lm_root; | |
2879 | } | |
2880 | ||
2881 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
2882 | } | |
2883 | ||
8986ecc0 | 2884 | return 0; |
17ac10ad AK |
2885 | } |
2886 | ||
651dd37a JR |
2887 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
2888 | { | |
2889 | if (vcpu->arch.mmu.direct_map) | |
2890 | return mmu_alloc_direct_roots(vcpu); | |
2891 | else | |
2892 | return mmu_alloc_shadow_roots(vcpu); | |
2893 | } | |
2894 | ||
0ba73cda MT |
2895 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
2896 | { | |
2897 | int i; | |
2898 | struct kvm_mmu_page *sp; | |
2899 | ||
81407ca5 JR |
2900 | if (vcpu->arch.mmu.direct_map) |
2901 | return; | |
2902 | ||
0ba73cda MT |
2903 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2904 | return; | |
6903074c | 2905 | |
bebb106a | 2906 | vcpu_clear_mmio_info(vcpu, ~0ul); |
0375f7fa | 2907 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
81407ca5 | 2908 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { |
0ba73cda MT |
2909 | hpa_t root = vcpu->arch.mmu.root_hpa; |
2910 | sp = page_header(root); | |
2911 | mmu_sync_children(vcpu, sp); | |
0375f7fa | 2912 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
2913 | return; |
2914 | } | |
2915 | for (i = 0; i < 4; ++i) { | |
2916 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2917 | ||
8986ecc0 | 2918 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
2919 | root &= PT64_BASE_ADDR_MASK; |
2920 | sp = page_header(root); | |
2921 | mmu_sync_children(vcpu, sp); | |
2922 | } | |
2923 | } | |
0375f7fa | 2924 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
2925 | } |
2926 | ||
2927 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
2928 | { | |
2929 | spin_lock(&vcpu->kvm->mmu_lock); | |
2930 | mmu_sync_roots(vcpu); | |
6cffe8ca | 2931 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
2932 | } |
2933 | ||
1871c602 | 2934 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 2935 | u32 access, struct x86_exception *exception) |
6aa8b732 | 2936 | { |
ab9ae313 AK |
2937 | if (exception) |
2938 | exception->error_code = 0; | |
6aa8b732 AK |
2939 | return vaddr; |
2940 | } | |
2941 | ||
6539e738 | 2942 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
2943 | u32 access, |
2944 | struct x86_exception *exception) | |
6539e738 | 2945 | { |
ab9ae313 AK |
2946 | if (exception) |
2947 | exception->error_code = 0; | |
6539e738 JR |
2948 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access); |
2949 | } | |
2950 | ||
ce88decf XG |
2951 | static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
2952 | { | |
2953 | if (direct) | |
2954 | return vcpu_match_mmio_gpa(vcpu, addr); | |
2955 | ||
2956 | return vcpu_match_mmio_gva(vcpu, addr); | |
2957 | } | |
2958 | ||
2959 | ||
2960 | /* | |
2961 | * On direct hosts, the last spte is only allows two states | |
2962 | * for mmio page fault: | |
2963 | * - It is the mmio spte | |
2964 | * - It is zapped or it is being zapped. | |
2965 | * | |
2966 | * This function completely checks the spte when the last spte | |
2967 | * is not the mmio spte. | |
2968 | */ | |
2969 | static bool check_direct_spte_mmio_pf(u64 spte) | |
2970 | { | |
2971 | return __check_direct_spte_mmio_pf(spte); | |
2972 | } | |
2973 | ||
2974 | static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr) | |
2975 | { | |
2976 | struct kvm_shadow_walk_iterator iterator; | |
2977 | u64 spte = 0ull; | |
2978 | ||
2979 | walk_shadow_page_lockless_begin(vcpu); | |
2980 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) | |
2981 | if (!is_shadow_present_pte(spte)) | |
2982 | break; | |
2983 | walk_shadow_page_lockless_end(vcpu); | |
2984 | ||
2985 | return spte; | |
2986 | } | |
2987 | ||
2988 | /* | |
2989 | * If it is a real mmio page fault, return 1 and emulat the instruction | |
2990 | * directly, return 0 to let CPU fault again on the address, -1 is | |
2991 | * returned if bug is detected. | |
2992 | */ | |
2993 | int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct) | |
2994 | { | |
2995 | u64 spte; | |
2996 | ||
2997 | if (quickly_check_mmio_pf(vcpu, addr, direct)) | |
2998 | return 1; | |
2999 | ||
3000 | spte = walk_shadow_page_get_mmio_spte(vcpu, addr); | |
3001 | ||
3002 | if (is_mmio_spte(spte)) { | |
3003 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
3004 | unsigned access = get_mmio_spte_access(spte); | |
3005 | ||
3006 | if (direct) | |
3007 | addr = 0; | |
4f022648 XG |
3008 | |
3009 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf XG |
3010 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
3011 | return 1; | |
3012 | } | |
3013 | ||
3014 | /* | |
3015 | * It's ok if the gva is remapped by other cpus on shadow guest, | |
3016 | * it's a BUG if the gfn is not a mmio page. | |
3017 | */ | |
3018 | if (direct && !check_direct_spte_mmio_pf(spte)) | |
3019 | return -1; | |
3020 | ||
3021 | /* | |
3022 | * If the page table is zapped by other cpus, let CPU fault again on | |
3023 | * the address. | |
3024 | */ | |
3025 | return 0; | |
3026 | } | |
3027 | EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common); | |
3028 | ||
3029 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, | |
3030 | u32 error_code, bool direct) | |
3031 | { | |
3032 | int ret; | |
3033 | ||
3034 | ret = handle_mmio_page_fault_common(vcpu, addr, direct); | |
3035 | WARN_ON(ret < 0); | |
3036 | return ret; | |
3037 | } | |
3038 | ||
6aa8b732 | 3039 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 3040 | u32 error_code, bool prefault) |
6aa8b732 | 3041 | { |
e833240f | 3042 | gfn_t gfn; |
e2dec939 | 3043 | int r; |
6aa8b732 | 3044 | |
b8688d51 | 3045 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
ce88decf XG |
3046 | |
3047 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3048 | return handle_mmio_page_fault(vcpu, gva, error_code, true); | |
3049 | ||
e2dec939 AK |
3050 | r = mmu_topup_memory_caches(vcpu); |
3051 | if (r) | |
3052 | return r; | |
714b93da | 3053 | |
6aa8b732 | 3054 | ASSERT(vcpu); |
ad312c7c | 3055 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3056 | |
e833240f | 3057 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 3058 | |
e833240f | 3059 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
78b2c54a | 3060 | error_code & PFERR_WRITE_MASK, gfn, prefault); |
6aa8b732 AK |
3061 | } |
3062 | ||
7e1fbeac | 3063 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
3064 | { |
3065 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3066 | |
7c90705b | 3067 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3068 | arch.gfn = gfn; |
c4806acd | 3069 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 3070 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 GN |
3071 | |
3072 | return kvm_setup_async_pf(vcpu, gva, gfn, &arch); | |
3073 | } | |
3074 | ||
3075 | static bool can_do_async_pf(struct kvm_vcpu *vcpu) | |
3076 | { | |
3077 | if (unlikely(!irqchip_in_kernel(vcpu->kvm) || | |
3078 | kvm_event_needs_reinjection(vcpu))) | |
3079 | return false; | |
3080 | ||
3081 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
3082 | } | |
3083 | ||
78b2c54a | 3084 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
612819c3 | 3085 | gva_t gva, pfn_t *pfn, bool write, bool *writable) |
af585b92 GN |
3086 | { |
3087 | bool async; | |
3088 | ||
612819c3 | 3089 | *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable); |
af585b92 GN |
3090 | |
3091 | if (!async) | |
3092 | return false; /* *pfn has correct page already */ | |
3093 | ||
3094 | put_page(pfn_to_page(*pfn)); | |
3095 | ||
78b2c54a | 3096 | if (!prefault && can_do_async_pf(vcpu)) { |
c9b263d2 | 3097 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
3098 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
3099 | trace_kvm_async_pf_doublefault(gva, gfn); | |
3100 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
3101 | return true; | |
3102 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
3103 | return true; | |
3104 | } | |
3105 | ||
612819c3 | 3106 | *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable); |
af585b92 GN |
3107 | |
3108 | return false; | |
3109 | } | |
3110 | ||
56028d08 | 3111 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 3112 | bool prefault) |
fb72d167 | 3113 | { |
35149e21 | 3114 | pfn_t pfn; |
fb72d167 | 3115 | int r; |
852e3c19 | 3116 | int level; |
936a5fe6 | 3117 | int force_pt_level; |
05da4558 | 3118 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 3119 | unsigned long mmu_seq; |
612819c3 MT |
3120 | int write = error_code & PFERR_WRITE_MASK; |
3121 | bool map_writable; | |
fb72d167 JR |
3122 | |
3123 | ASSERT(vcpu); | |
3124 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
3125 | ||
ce88decf XG |
3126 | if (unlikely(error_code & PFERR_RSVD_MASK)) |
3127 | return handle_mmio_page_fault(vcpu, gpa, error_code, true); | |
3128 | ||
fb72d167 JR |
3129 | r = mmu_topup_memory_caches(vcpu); |
3130 | if (r) | |
3131 | return r; | |
3132 | ||
936a5fe6 AA |
3133 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
3134 | if (likely(!force_pt_level)) { | |
3135 | level = mapping_level(vcpu, gfn); | |
3136 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
3137 | } else | |
3138 | level = PT_PAGE_TABLE_LEVEL; | |
852e3c19 | 3139 | |
e930bffe | 3140 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3141 | smp_rmb(); |
af585b92 | 3142 | |
78b2c54a | 3143 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
af585b92 GN |
3144 | return 0; |
3145 | ||
d7c55201 XG |
3146 | if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r)) |
3147 | return r; | |
3148 | ||
fb72d167 | 3149 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
3150 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
3151 | goto out_unlock; | |
fb72d167 | 3152 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
3153 | if (likely(!force_pt_level)) |
3154 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
612819c3 | 3155 | r = __direct_map(vcpu, gpa, write, map_writable, |
2ec4739d | 3156 | level, gfn, pfn, prefault); |
fb72d167 | 3157 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
3158 | |
3159 | return r; | |
e930bffe AA |
3160 | |
3161 | out_unlock: | |
3162 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3163 | kvm_release_pfn_clean(pfn); | |
3164 | return 0; | |
fb72d167 JR |
3165 | } |
3166 | ||
6aa8b732 AK |
3167 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
3168 | { | |
17ac10ad | 3169 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3170 | } |
3171 | ||
52fde8df JR |
3172 | static int nonpaging_init_context(struct kvm_vcpu *vcpu, |
3173 | struct kvm_mmu *context) | |
6aa8b732 | 3174 | { |
6aa8b732 AK |
3175 | context->new_cr3 = nonpaging_new_cr3; |
3176 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
3177 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
3178 | context->free = nonpaging_free; | |
e8bc217a | 3179 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3180 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3181 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 3182 | context->root_level = 0; |
6aa8b732 | 3183 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3184 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3185 | context->direct_map = true; |
2d48a985 | 3186 | context->nx = false; |
6aa8b732 AK |
3187 | return 0; |
3188 | } | |
3189 | ||
d835dfec | 3190 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 3191 | { |
1165f5fe | 3192 | ++vcpu->stat.tlb_flush; |
a8eeb04a | 3193 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
6aa8b732 AK |
3194 | } |
3195 | ||
3196 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
3197 | { | |
9f8fe504 | 3198 | pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu)); |
cea0f0e7 | 3199 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3200 | } |
3201 | ||
5777ed34 JR |
3202 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
3203 | { | |
9f8fe504 | 3204 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
3205 | } |
3206 | ||
6389ee94 AK |
3207 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
3208 | struct x86_exception *fault) | |
6aa8b732 | 3209 | { |
6389ee94 | 3210 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
3211 | } |
3212 | ||
6aa8b732 AK |
3213 | static void paging_free(struct kvm_vcpu *vcpu) |
3214 | { | |
3215 | nonpaging_free(vcpu); | |
3216 | } | |
3217 | ||
3241f22d | 3218 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) |
82725b20 DE |
3219 | { |
3220 | int bit7; | |
3221 | ||
3222 | bit7 = (gpte >> 7) & 1; | |
3241f22d | 3223 | return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0; |
82725b20 DE |
3224 | } |
3225 | ||
ce88decf XG |
3226 | static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access, |
3227 | int *nr_present) | |
3228 | { | |
3229 | if (unlikely(is_mmio_spte(*sptep))) { | |
3230 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
3231 | mmu_spte_clear_no_track(sptep); | |
3232 | return true; | |
3233 | } | |
3234 | ||
3235 | (*nr_present)++; | |
3236 | mark_mmio_spte(sptep, gfn, access); | |
3237 | return true; | |
3238 | } | |
3239 | ||
3240 | return false; | |
3241 | } | |
3242 | ||
6aa8b732 AK |
3243 | #define PTTYPE 64 |
3244 | #include "paging_tmpl.h" | |
3245 | #undef PTTYPE | |
3246 | ||
3247 | #define PTTYPE 32 | |
3248 | #include "paging_tmpl.h" | |
3249 | #undef PTTYPE | |
3250 | ||
52fde8df | 3251 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4d6931c3 | 3252 | struct kvm_mmu *context) |
82725b20 | 3253 | { |
82725b20 DE |
3254 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
3255 | u64 exb_bit_rsvd = 0; | |
3256 | ||
2d48a985 | 3257 | if (!context->nx) |
82725b20 | 3258 | exb_bit_rsvd = rsvd_bits(63, 63); |
4d6931c3 | 3259 | switch (context->root_level) { |
82725b20 DE |
3260 | case PT32_ROOT_LEVEL: |
3261 | /* no rsvd bits for 2 level 4K page table entries */ | |
3262 | context->rsvd_bits_mask[0][1] = 0; | |
3263 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
3264 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
3265 | ||
3266 | if (!is_pse(vcpu)) { | |
3267 | context->rsvd_bits_mask[1][1] = 0; | |
3268 | break; | |
3269 | } | |
3270 | ||
82725b20 DE |
3271 | if (is_cpuid_PSE36()) |
3272 | /* 36bits PSE 4MB page */ | |
3273 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
3274 | else | |
3275 | /* 32 bits PSE 4MB page */ | |
3276 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
3277 | break; |
3278 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
3279 | context->rsvd_bits_mask[0][2] = |
3280 | rsvd_bits(maxphyaddr, 63) | | |
3281 | rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ | |
82725b20 | 3282 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 3283 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
3284 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
3285 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
3286 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
3287 | rsvd_bits(maxphyaddr, 62) | | |
3288 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 3289 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
3290 | break; |
3291 | case PT64_ROOT_LEVEL: | |
3292 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
3293 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
3294 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | | |
3295 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
3296 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | | |
4c26b4cd | 3297 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
3298 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
3299 | rsvd_bits(maxphyaddr, 51); | |
3300 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 JR |
3301 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
3302 | rsvd_bits(maxphyaddr, 51) | | |
3303 | rsvd_bits(13, 29); | |
82725b20 | 3304 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
3305 | rsvd_bits(maxphyaddr, 51) | |
3306 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 3307 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
3308 | break; |
3309 | } | |
3310 | } | |
3311 | ||
52fde8df JR |
3312 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, |
3313 | struct kvm_mmu *context, | |
3314 | int level) | |
6aa8b732 | 3315 | { |
2d48a985 | 3316 | context->nx = is_nx(vcpu); |
4d6931c3 | 3317 | context->root_level = level; |
2d48a985 | 3318 | |
4d6931c3 | 3319 | reset_rsvds_bits_mask(vcpu, context); |
6aa8b732 AK |
3320 | |
3321 | ASSERT(is_pae(vcpu)); | |
3322 | context->new_cr3 = paging_new_cr3; | |
3323 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 3324 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 3325 | context->sync_page = paging64_sync_page; |
a7052897 | 3326 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 3327 | context->update_pte = paging64_update_pte; |
6aa8b732 | 3328 | context->free = paging_free; |
17ac10ad | 3329 | context->shadow_root_level = level; |
17c3ba9d | 3330 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3331 | context->direct_map = false; |
6aa8b732 AK |
3332 | return 0; |
3333 | } | |
3334 | ||
52fde8df JR |
3335 | static int paging64_init_context(struct kvm_vcpu *vcpu, |
3336 | struct kvm_mmu *context) | |
17ac10ad | 3337 | { |
52fde8df | 3338 | return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
3339 | } |
3340 | ||
52fde8df JR |
3341 | static int paging32_init_context(struct kvm_vcpu *vcpu, |
3342 | struct kvm_mmu *context) | |
6aa8b732 | 3343 | { |
2d48a985 | 3344 | context->nx = false; |
4d6931c3 | 3345 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 3346 | |
4d6931c3 | 3347 | reset_rsvds_bits_mask(vcpu, context); |
6aa8b732 AK |
3348 | |
3349 | context->new_cr3 = paging_new_cr3; | |
3350 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
3351 | context->gva_to_gpa = paging32_gva_to_gpa; |
3352 | context->free = paging_free; | |
e8bc217a | 3353 | context->sync_page = paging32_sync_page; |
a7052897 | 3354 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 3355 | context->update_pte = paging32_update_pte; |
6aa8b732 | 3356 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3357 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3358 | context->direct_map = false; |
6aa8b732 AK |
3359 | return 0; |
3360 | } | |
3361 | ||
52fde8df JR |
3362 | static int paging32E_init_context(struct kvm_vcpu *vcpu, |
3363 | struct kvm_mmu *context) | |
6aa8b732 | 3364 | { |
52fde8df | 3365 | return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
3366 | } |
3367 | ||
fb72d167 JR |
3368 | static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
3369 | { | |
14dfe855 | 3370 | struct kvm_mmu *context = vcpu->arch.walk_mmu; |
fb72d167 | 3371 | |
c445f8ef | 3372 | context->base_role.word = 0; |
fb72d167 JR |
3373 | context->new_cr3 = nonpaging_new_cr3; |
3374 | context->page_fault = tdp_page_fault; | |
3375 | context->free = nonpaging_free; | |
e8bc217a | 3376 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3377 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3378 | context->update_pte = nonpaging_update_pte; |
67253af5 | 3379 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 3380 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3381 | context->direct_map = true; |
1c97f0a0 | 3382 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 3383 | context->get_cr3 = get_cr3; |
e4e517b4 | 3384 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 3385 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
3386 | |
3387 | if (!is_paging(vcpu)) { | |
2d48a985 | 3388 | context->nx = false; |
fb72d167 JR |
3389 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
3390 | context->root_level = 0; | |
3391 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3392 | context->nx = is_nx(vcpu); |
fb72d167 | 3393 | context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 DB |
3394 | reset_rsvds_bits_mask(vcpu, context); |
3395 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 3396 | } else if (is_pae(vcpu)) { |
2d48a985 | 3397 | context->nx = is_nx(vcpu); |
fb72d167 | 3398 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
3399 | reset_rsvds_bits_mask(vcpu, context); |
3400 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 3401 | } else { |
2d48a985 | 3402 | context->nx = false; |
fb72d167 | 3403 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
3404 | reset_rsvds_bits_mask(vcpu, context); |
3405 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
3406 | } |
3407 | ||
3408 | return 0; | |
3409 | } | |
3410 | ||
52fde8df | 3411 | int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context) |
6aa8b732 | 3412 | { |
a770f6f2 | 3413 | int r; |
411c588d | 3414 | bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
6aa8b732 | 3415 | ASSERT(vcpu); |
ad312c7c | 3416 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
3417 | |
3418 | if (!is_paging(vcpu)) | |
52fde8df | 3419 | r = nonpaging_init_context(vcpu, context); |
a9058ecd | 3420 | else if (is_long_mode(vcpu)) |
52fde8df | 3421 | r = paging64_init_context(vcpu, context); |
6aa8b732 | 3422 | else if (is_pae(vcpu)) |
52fde8df | 3423 | r = paging32E_init_context(vcpu, context); |
6aa8b732 | 3424 | else |
52fde8df | 3425 | r = paging32_init_context(vcpu, context); |
a770f6f2 | 3426 | |
5b7e0102 | 3427 | vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu); |
f43addd4 | 3428 | vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu); |
411c588d AK |
3429 | vcpu->arch.mmu.base_role.smep_andnot_wp |
3430 | = smep && !is_write_protection(vcpu); | |
52fde8df JR |
3431 | |
3432 | return r; | |
3433 | } | |
3434 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
3435 | ||
3436 | static int init_kvm_softmmu(struct kvm_vcpu *vcpu) | |
3437 | { | |
14dfe855 | 3438 | int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu); |
52fde8df | 3439 | |
14dfe855 JR |
3440 | vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3; |
3441 | vcpu->arch.walk_mmu->get_cr3 = get_cr3; | |
e4e517b4 | 3442 | vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read; |
14dfe855 | 3443 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; |
a770f6f2 AK |
3444 | |
3445 | return r; | |
6aa8b732 AK |
3446 | } |
3447 | ||
02f59dc9 JR |
3448 | static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
3449 | { | |
3450 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
3451 | ||
3452 | g_context->get_cr3 = get_cr3; | |
e4e517b4 | 3453 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
3454 | g_context->inject_page_fault = kvm_inject_page_fault; |
3455 | ||
3456 | /* | |
3457 | * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The | |
3458 | * translation of l2_gpa to l1_gpa addresses is done using the | |
3459 | * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa | |
3460 | * functions between mmu and nested_mmu are swapped. | |
3461 | */ | |
3462 | if (!is_paging(vcpu)) { | |
2d48a985 | 3463 | g_context->nx = false; |
02f59dc9 JR |
3464 | g_context->root_level = 0; |
3465 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
3466 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3467 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 3468 | g_context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 | 3469 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3470 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
3471 | } else if (is_pae(vcpu)) { | |
2d48a985 | 3472 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 3473 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 3474 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3475 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
3476 | } else { | |
2d48a985 | 3477 | g_context->nx = false; |
02f59dc9 | 3478 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 3479 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3480 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
3481 | } | |
3482 | ||
3483 | return 0; | |
3484 | } | |
3485 | ||
fb72d167 JR |
3486 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) |
3487 | { | |
02f59dc9 JR |
3488 | if (mmu_is_nested(vcpu)) |
3489 | return init_kvm_nested_mmu(vcpu); | |
3490 | else if (tdp_enabled) | |
fb72d167 JR |
3491 | return init_kvm_tdp_mmu(vcpu); |
3492 | else | |
3493 | return init_kvm_softmmu(vcpu); | |
3494 | } | |
3495 | ||
6aa8b732 AK |
3496 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) |
3497 | { | |
3498 | ASSERT(vcpu); | |
62ad0755 SY |
3499 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3500 | /* mmu.free() should set root_hpa = INVALID_PAGE */ | |
ad312c7c | 3501 | vcpu->arch.mmu.free(vcpu); |
6aa8b732 AK |
3502 | } |
3503 | ||
3504 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
3505 | { |
3506 | destroy_kvm_mmu(vcpu); | |
f8f7e5ee | 3507 | return init_kvm_mmu(vcpu); |
17c3ba9d | 3508 | } |
8668a3c4 | 3509 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
3510 | |
3511 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 3512 | { |
714b93da AK |
3513 | int r; |
3514 | ||
e2dec939 | 3515 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
3516 | if (r) |
3517 | goto out; | |
8986ecc0 | 3518 | r = mmu_alloc_roots(vcpu); |
8facbbff | 3519 | spin_lock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3520 | mmu_sync_roots(vcpu); |
aaee2c94 | 3521 | spin_unlock(&vcpu->kvm->mmu_lock); |
8986ecc0 MT |
3522 | if (r) |
3523 | goto out; | |
3662cb1c | 3524 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 3525 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
3526 | out: |
3527 | return r; | |
6aa8b732 | 3528 | } |
17c3ba9d AK |
3529 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
3530 | ||
3531 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
3532 | { | |
3533 | mmu_free_roots(vcpu); | |
3534 | } | |
4b16184c | 3535 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 3536 | |
0028425f | 3537 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
3538 | struct kvm_mmu_page *sp, u64 *spte, |
3539 | const void *new) | |
0028425f | 3540 | { |
30945387 | 3541 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
3542 | ++vcpu->kvm->stat.mmu_pde_zapped; |
3543 | return; | |
30945387 | 3544 | } |
0028425f | 3545 | |
4cee5764 | 3546 | ++vcpu->kvm->stat.mmu_pte_updated; |
7c562522 | 3547 | vcpu->arch.mmu.update_pte(vcpu, sp, spte, new); |
0028425f AK |
3548 | } |
3549 | ||
79539cec AK |
3550 | static bool need_remote_flush(u64 old, u64 new) |
3551 | { | |
3552 | if (!is_shadow_present_pte(old)) | |
3553 | return false; | |
3554 | if (!is_shadow_present_pte(new)) | |
3555 | return true; | |
3556 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
3557 | return true; | |
3558 | old ^= PT64_NX_MASK; | |
3559 | new ^= PT64_NX_MASK; | |
3560 | return (old & ~new & PT64_PERM_MASK) != 0; | |
3561 | } | |
3562 | ||
0671a8e7 XG |
3563 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
3564 | bool remote_flush, bool local_flush) | |
79539cec | 3565 | { |
0671a8e7 XG |
3566 | if (zap_page) |
3567 | return; | |
3568 | ||
3569 | if (remote_flush) | |
79539cec | 3570 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 3571 | else if (local_flush) |
79539cec AK |
3572 | kvm_mmu_flush_tlb(vcpu); |
3573 | } | |
3574 | ||
889e5cbc XG |
3575 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
3576 | const u8 *new, int *bytes) | |
da4a00f0 | 3577 | { |
889e5cbc XG |
3578 | u64 gentry; |
3579 | int r; | |
72016f3a | 3580 | |
72016f3a AK |
3581 | /* |
3582 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
3583 | * as the current vcpu paging mode since we update the sptes only |
3584 | * when they have the same mode. | |
72016f3a | 3585 | */ |
889e5cbc | 3586 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 3587 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
3588 | *gpa &= ~(gpa_t)7; |
3589 | *bytes = 8; | |
3590 | r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, min(*bytes, 8)); | |
72016f3a AK |
3591 | if (r) |
3592 | gentry = 0; | |
08e850c6 AK |
3593 | new = (const u8 *)&gentry; |
3594 | } | |
3595 | ||
889e5cbc | 3596 | switch (*bytes) { |
08e850c6 AK |
3597 | case 4: |
3598 | gentry = *(const u32 *)new; | |
3599 | break; | |
3600 | case 8: | |
3601 | gentry = *(const u64 *)new; | |
3602 | break; | |
3603 | default: | |
3604 | gentry = 0; | |
3605 | break; | |
72016f3a AK |
3606 | } |
3607 | ||
889e5cbc XG |
3608 | return gentry; |
3609 | } | |
3610 | ||
3611 | /* | |
3612 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
3613 | * or we may be forking, in which case it is better to unmap the page. | |
3614 | */ | |
a138fe75 | 3615 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 3616 | { |
a30f47cb XG |
3617 | /* |
3618 | * Skip write-flooding detected for the sp whose level is 1, because | |
3619 | * it can become unsync, then the guest page is not write-protected. | |
3620 | */ | |
f71fa31f | 3621 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) |
a30f47cb | 3622 | return false; |
3246af0e | 3623 | |
a30f47cb | 3624 | return ++sp->write_flooding_count >= 3; |
889e5cbc XG |
3625 | } |
3626 | ||
3627 | /* | |
3628 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
3629 | * indicate a page is not used as a page table. | |
3630 | */ | |
3631 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
3632 | int bytes) | |
3633 | { | |
3634 | unsigned offset, pte_size, misaligned; | |
3635 | ||
3636 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
3637 | gpa, bytes, sp->role.word); | |
3638 | ||
3639 | offset = offset_in_page(gpa); | |
3640 | pte_size = sp->role.cr4_pae ? 8 : 4; | |
5d9ca30e XG |
3641 | |
3642 | /* | |
3643 | * Sometimes, the OS only writes the last one bytes to update status | |
3644 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
3645 | */ | |
3646 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
3647 | return false; | |
3648 | ||
889e5cbc XG |
3649 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
3650 | misaligned |= bytes < 4; | |
3651 | ||
3652 | return misaligned; | |
3653 | } | |
3654 | ||
3655 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
3656 | { | |
3657 | unsigned page_offset, quadrant; | |
3658 | u64 *spte; | |
3659 | int level; | |
3660 | ||
3661 | page_offset = offset_in_page(gpa); | |
3662 | level = sp->role.level; | |
3663 | *nspte = 1; | |
3664 | if (!sp->role.cr4_pae) { | |
3665 | page_offset <<= 1; /* 32->64 */ | |
3666 | /* | |
3667 | * A 32-bit pde maps 4MB while the shadow pdes map | |
3668 | * only 2MB. So we need to double the offset again | |
3669 | * and zap two pdes instead of one. | |
3670 | */ | |
3671 | if (level == PT32_ROOT_LEVEL) { | |
3672 | page_offset &= ~7; /* kill rounding error */ | |
3673 | page_offset <<= 1; | |
3674 | *nspte = 2; | |
3675 | } | |
3676 | quadrant = page_offset >> PAGE_SHIFT; | |
3677 | page_offset &= ~PAGE_MASK; | |
3678 | if (quadrant != sp->role.quadrant) | |
3679 | return NULL; | |
3680 | } | |
3681 | ||
3682 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
3683 | return spte; | |
3684 | } | |
3685 | ||
3686 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, | |
3687 | const u8 *new, int bytes) | |
3688 | { | |
3689 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
3690 | union kvm_mmu_page_role mask = { .word = 0 }; | |
3691 | struct kvm_mmu_page *sp; | |
3692 | struct hlist_node *node; | |
3693 | LIST_HEAD(invalid_list); | |
3694 | u64 entry, gentry, *spte; | |
3695 | int npte; | |
a30f47cb | 3696 | bool remote_flush, local_flush, zap_page; |
889e5cbc XG |
3697 | |
3698 | /* | |
3699 | * If we don't have indirect shadow pages, it means no page is | |
3700 | * write-protected, so we can exit simply. | |
3701 | */ | |
3702 | if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) | |
3703 | return; | |
3704 | ||
3705 | zap_page = remote_flush = local_flush = false; | |
3706 | ||
3707 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
3708 | ||
3709 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes); | |
3710 | ||
3711 | /* | |
3712 | * No need to care whether allocation memory is successful | |
3713 | * or not since pte prefetch is skiped if it does not have | |
3714 | * enough objects in the cache. | |
3715 | */ | |
3716 | mmu_topup_memory_caches(vcpu); | |
3717 | ||
3718 | spin_lock(&vcpu->kvm->mmu_lock); | |
3719 | ++vcpu->kvm->stat.mmu_pte_write; | |
0375f7fa | 3720 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 3721 | |
fa1de2bf | 3722 | mask.cr0_wp = mask.cr4_pae = mask.nxe = 1; |
f41d335a | 3723 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) { |
a30f47cb | 3724 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 3725 | detect_write_flooding(sp)) { |
0671a8e7 | 3726 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 3727 | &invalid_list); |
4cee5764 | 3728 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
3729 | continue; |
3730 | } | |
889e5cbc XG |
3731 | |
3732 | spte = get_written_sptes(sp, gpa, &npte); | |
3733 | if (!spte) | |
3734 | continue; | |
3735 | ||
0671a8e7 | 3736 | local_flush = true; |
ac1b714e | 3737 | while (npte--) { |
79539cec | 3738 | entry = *spte; |
38e3b2b2 | 3739 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf XG |
3740 | if (gentry && |
3741 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
f759e2b4 | 3742 | & mask.word) && rmap_can_add(vcpu)) |
7c562522 | 3743 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
0671a8e7 XG |
3744 | if (!remote_flush && need_remote_flush(entry, *spte)) |
3745 | remote_flush = true; | |
ac1b714e | 3746 | ++spte; |
9b7a0325 | 3747 | } |
9b7a0325 | 3748 | } |
0671a8e7 | 3749 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 3750 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
0375f7fa | 3751 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 3752 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
3753 | } |
3754 | ||
a436036b AK |
3755 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
3756 | { | |
10589a46 MT |
3757 | gpa_t gpa; |
3758 | int r; | |
a436036b | 3759 | |
c5a78f2b | 3760 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
3761 | return 0; |
3762 | ||
1871c602 | 3763 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 3764 | |
10589a46 | 3765 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 3766 | |
10589a46 | 3767 | return r; |
a436036b | 3768 | } |
577bdc49 | 3769 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 3770 | |
22d95b12 | 3771 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu) |
ebeace86 | 3772 | { |
d98ba053 | 3773 | LIST_HEAD(invalid_list); |
103ad25a | 3774 | |
e0df7b9f | 3775 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES && |
3b80fffe | 3776 | !list_empty(&vcpu->kvm->arch.active_mmu_pages)) { |
4db35314 | 3777 | struct kvm_mmu_page *sp; |
ebeace86 | 3778 | |
f05e70ac | 3779 | sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev, |
4db35314 | 3780 | struct kvm_mmu_page, link); |
e0df7b9f | 3781 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 3782 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 3783 | } |
aa6bd187 | 3784 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
ebeace86 | 3785 | } |
ebeace86 | 3786 | |
1cb3f3ae XG |
3787 | static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr) |
3788 | { | |
3789 | if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu)) | |
3790 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3791 | ||
3792 | return vcpu_match_mmio_gva(vcpu, addr); | |
3793 | } | |
3794 | ||
dc25e89e AP |
3795 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code, |
3796 | void *insn, int insn_len) | |
3067714c | 3797 | { |
1cb3f3ae | 3798 | int r, emulation_type = EMULTYPE_RETRY; |
3067714c AK |
3799 | enum emulation_result er; |
3800 | ||
56028d08 | 3801 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false); |
3067714c AK |
3802 | if (r < 0) |
3803 | goto out; | |
3804 | ||
3805 | if (!r) { | |
3806 | r = 1; | |
3807 | goto out; | |
3808 | } | |
3809 | ||
1cb3f3ae XG |
3810 | if (is_mmio_page_fault(vcpu, cr2)) |
3811 | emulation_type = 0; | |
3812 | ||
3813 | er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len); | |
3067714c AK |
3814 | |
3815 | switch (er) { | |
3816 | case EMULATE_DONE: | |
3817 | return 1; | |
3818 | case EMULATE_DO_MMIO: | |
3819 | ++vcpu->stat.mmio_exits; | |
6d77dbfc | 3820 | /* fall through */ |
3067714c | 3821 | case EMULATE_FAIL: |
3f5d18a9 | 3822 | return 0; |
3067714c AK |
3823 | default: |
3824 | BUG(); | |
3825 | } | |
3826 | out: | |
3067714c AK |
3827 | return r; |
3828 | } | |
3829 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
3830 | ||
a7052897 MT |
3831 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
3832 | { | |
a7052897 | 3833 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
3834 | kvm_mmu_flush_tlb(vcpu); |
3835 | ++vcpu->stat.invlpg; | |
3836 | } | |
3837 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
3838 | ||
18552672 JR |
3839 | void kvm_enable_tdp(void) |
3840 | { | |
3841 | tdp_enabled = true; | |
3842 | } | |
3843 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
3844 | ||
5f4cb662 JR |
3845 | void kvm_disable_tdp(void) |
3846 | { | |
3847 | tdp_enabled = false; | |
3848 | } | |
3849 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
3850 | ||
6aa8b732 AK |
3851 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
3852 | { | |
ad312c7c | 3853 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3854 | if (vcpu->arch.mmu.lm_root != NULL) |
3855 | free_page((unsigned long)vcpu->arch.mmu.lm_root); | |
6aa8b732 AK |
3856 | } |
3857 | ||
3858 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
3859 | { | |
17ac10ad | 3860 | struct page *page; |
6aa8b732 AK |
3861 | int i; |
3862 | ||
3863 | ASSERT(vcpu); | |
3864 | ||
17ac10ad AK |
3865 | /* |
3866 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
3867 | * Therefore we need to allocate shadow page tables in the first | |
3868 | * 4GB of memory, which happens to fit the DMA32 zone. | |
3869 | */ | |
3870 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
3871 | if (!page) | |
d7fa6ab2 WY |
3872 | return -ENOMEM; |
3873 | ||
ad312c7c | 3874 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 3875 | for (i = 0; i < 4; ++i) |
ad312c7c | 3876 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 3877 | |
6aa8b732 | 3878 | return 0; |
6aa8b732 AK |
3879 | } |
3880 | ||
8018c27b | 3881 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 3882 | { |
6aa8b732 | 3883 | ASSERT(vcpu); |
e459e322 XG |
3884 | |
3885 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
3886 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; | |
3887 | vcpu->arch.mmu.translate_gpa = translate_gpa; | |
3888 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; | |
6aa8b732 | 3889 | |
8018c27b IM |
3890 | return alloc_mmu_pages(vcpu); |
3891 | } | |
6aa8b732 | 3892 | |
8018c27b IM |
3893 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
3894 | { | |
3895 | ASSERT(vcpu); | |
ad312c7c | 3896 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 3897 | |
8018c27b | 3898 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
3899 | } |
3900 | ||
90cb0529 | 3901 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 3902 | { |
4db35314 | 3903 | struct kvm_mmu_page *sp; |
6aa8b732 | 3904 | |
f05e70ac | 3905 | list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) { |
6aa8b732 AK |
3906 | int i; |
3907 | u64 *pt; | |
3908 | ||
291f26bc | 3909 | if (!test_bit(slot, sp->slot_bitmap)) |
6aa8b732 AK |
3910 | continue; |
3911 | ||
4db35314 | 3912 | pt = sp->spt; |
8234b22e | 3913 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { |
da8dc75f XG |
3914 | if (!is_shadow_present_pte(pt[i]) || |
3915 | !is_last_spte(pt[i], sp->role.level)) | |
3916 | continue; | |
3917 | ||
3918 | if (is_large_pte(pt[i])) { | |
c3707958 | 3919 | drop_spte(kvm, &pt[i]); |
8234b22e | 3920 | --kvm->stat.lpages; |
da8dc75f | 3921 | continue; |
8234b22e | 3922 | } |
da8dc75f | 3923 | |
6aa8b732 | 3924 | /* avoid RMW */ |
01c168ac | 3925 | if (is_writable_pte(pt[i])) |
1df9f2dc XG |
3926 | mmu_spte_update(&pt[i], |
3927 | pt[i] & ~PT_WRITABLE_MASK); | |
8234b22e | 3928 | } |
6aa8b732 | 3929 | } |
171d595d | 3930 | kvm_flush_remote_tlbs(kvm); |
6aa8b732 | 3931 | } |
37a7d8b0 | 3932 | |
90cb0529 | 3933 | void kvm_mmu_zap_all(struct kvm *kvm) |
e0fa826f | 3934 | { |
4db35314 | 3935 | struct kvm_mmu_page *sp, *node; |
d98ba053 | 3936 | LIST_HEAD(invalid_list); |
e0fa826f | 3937 | |
aaee2c94 | 3938 | spin_lock(&kvm->mmu_lock); |
3246af0e | 3939 | restart: |
f05e70ac | 3940 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) |
d98ba053 | 3941 | if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list)) |
3246af0e XG |
3942 | goto restart; |
3943 | ||
d98ba053 | 3944 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
aaee2c94 | 3945 | spin_unlock(&kvm->mmu_lock); |
e0fa826f DL |
3946 | } |
3947 | ||
3d56cbdf JK |
3948 | static void kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm, |
3949 | struct list_head *invalid_list) | |
3ee16c81 IE |
3950 | { |
3951 | struct kvm_mmu_page *page; | |
3952 | ||
3953 | page = container_of(kvm->arch.active_mmu_pages.prev, | |
3954 | struct kvm_mmu_page, link); | |
3d56cbdf | 3955 | kvm_mmu_prepare_zap_page(kvm, page, invalid_list); |
3ee16c81 IE |
3956 | } |
3957 | ||
1495f230 | 3958 | static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc) |
3ee16c81 IE |
3959 | { |
3960 | struct kvm *kvm; | |
3961 | struct kvm *kvm_freed = NULL; | |
1495f230 | 3962 | int nr_to_scan = sc->nr_to_scan; |
45221ab6 DH |
3963 | |
3964 | if (nr_to_scan == 0) | |
3965 | goto out; | |
3ee16c81 | 3966 | |
e935b837 | 3967 | raw_spin_lock(&kvm_lock); |
3ee16c81 IE |
3968 | |
3969 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 3970 | int idx; |
d98ba053 | 3971 | LIST_HEAD(invalid_list); |
3ee16c81 | 3972 | |
f656ce01 | 3973 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 3974 | spin_lock(&kvm->mmu_lock); |
45221ab6 DH |
3975 | if (!kvm_freed && nr_to_scan > 0 && |
3976 | kvm->arch.n_used_mmu_pages > 0) { | |
3d56cbdf JK |
3977 | kvm_mmu_remove_some_alloc_mmu_pages(kvm, |
3978 | &invalid_list); | |
3ee16c81 IE |
3979 | kvm_freed = kvm; |
3980 | } | |
3981 | nr_to_scan--; | |
3982 | ||
d98ba053 | 3983 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
3ee16c81 | 3984 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 3985 | srcu_read_unlock(&kvm->srcu, idx); |
3ee16c81 IE |
3986 | } |
3987 | if (kvm_freed) | |
3988 | list_move_tail(&kvm_freed->vm_list, &vm_list); | |
3989 | ||
e935b837 | 3990 | raw_spin_unlock(&kvm_lock); |
3ee16c81 | 3991 | |
45221ab6 DH |
3992 | out: |
3993 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); | |
3ee16c81 IE |
3994 | } |
3995 | ||
3996 | static struct shrinker mmu_shrinker = { | |
3997 | .shrink = mmu_shrink, | |
3998 | .seeks = DEFAULT_SEEKS * 10, | |
3999 | }; | |
4000 | ||
2ddfd20e | 4001 | static void mmu_destroy_caches(void) |
b5a33a75 | 4002 | { |
53c07b18 XG |
4003 | if (pte_list_desc_cache) |
4004 | kmem_cache_destroy(pte_list_desc_cache); | |
d3d25b04 AK |
4005 | if (mmu_page_header_cache) |
4006 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
4007 | } |
4008 | ||
4009 | int kvm_mmu_module_init(void) | |
4010 | { | |
53c07b18 XG |
4011 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
4012 | sizeof(struct pte_list_desc), | |
20c2df83 | 4013 | 0, 0, NULL); |
53c07b18 | 4014 | if (!pte_list_desc_cache) |
b5a33a75 AK |
4015 | goto nomem; |
4016 | ||
d3d25b04 AK |
4017 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
4018 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 4019 | 0, 0, NULL); |
d3d25b04 AK |
4020 | if (!mmu_page_header_cache) |
4021 | goto nomem; | |
4022 | ||
45bf21a8 WY |
4023 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0)) |
4024 | goto nomem; | |
4025 | ||
3ee16c81 IE |
4026 | register_shrinker(&mmu_shrinker); |
4027 | ||
b5a33a75 AK |
4028 | return 0; |
4029 | ||
4030 | nomem: | |
3ee16c81 | 4031 | mmu_destroy_caches(); |
b5a33a75 AK |
4032 | return -ENOMEM; |
4033 | } | |
4034 | ||
3ad82a7e ZX |
4035 | /* |
4036 | * Caculate mmu pages needed for kvm. | |
4037 | */ | |
4038 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
4039 | { | |
3ad82a7e ZX |
4040 | unsigned int nr_mmu_pages; |
4041 | unsigned int nr_pages = 0; | |
bc6678a3 | 4042 | struct kvm_memslots *slots; |
be6ba0f0 | 4043 | struct kvm_memory_slot *memslot; |
3ad82a7e | 4044 | |
90d83dc3 LJ |
4045 | slots = kvm_memslots(kvm); |
4046 | ||
be6ba0f0 XG |
4047 | kvm_for_each_memslot(memslot, slots) |
4048 | nr_pages += memslot->npages; | |
3ad82a7e ZX |
4049 | |
4050 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
4051 | nr_mmu_pages = max(nr_mmu_pages, | |
4052 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
4053 | ||
4054 | return nr_mmu_pages; | |
4055 | } | |
4056 | ||
94d8b056 MT |
4057 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
4058 | { | |
4059 | struct kvm_shadow_walk_iterator iterator; | |
c2a2ac2b | 4060 | u64 spte; |
94d8b056 MT |
4061 | int nr_sptes = 0; |
4062 | ||
c2a2ac2b XG |
4063 | walk_shadow_page_lockless_begin(vcpu); |
4064 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
4065 | sptes[iterator.level-1] = spte; | |
94d8b056 | 4066 | nr_sptes++; |
c2a2ac2b | 4067 | if (!is_shadow_present_pte(spte)) |
94d8b056 MT |
4068 | break; |
4069 | } | |
c2a2ac2b | 4070 | walk_shadow_page_lockless_end(vcpu); |
94d8b056 MT |
4071 | |
4072 | return nr_sptes; | |
4073 | } | |
4074 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
4075 | ||
c42fffe3 XG |
4076 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
4077 | { | |
4078 | ASSERT(vcpu); | |
4079 | ||
4080 | destroy_kvm_mmu(vcpu); | |
4081 | free_mmu_pages(vcpu); | |
4082 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
4083 | } |
4084 | ||
b034cf01 XG |
4085 | void kvm_mmu_module_exit(void) |
4086 | { | |
4087 | mmu_destroy_caches(); | |
4088 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
4089 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
4090 | mmu_audit_disable(); |
4091 | } |