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KVM: Enable ERMS feature support for KVM
[linux-block.git] / arch / x86 / kvm / mmu.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
9611c187 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 11 *
12 * Authors:
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
e495606d 20
af585b92 21#include "irq.h"
1d737c8a 22#include "mmu.h"
836a1b3c 23#include "x86.h"
6de4f3ad 24#include "kvm_cache_regs.h"
af585b92 25#include "x86.h"
e495606d 26
edf88417 27#include <linux/kvm_host.h>
6aa8b732
AK		 28#include <linux/types.h>
29#include <linux/string.h>
6aa8b732
AK		 30#include <linux/mm.h>
31#include <linux/highmem.h>
32#include <linux/module.h>
448353ca 33#include <linux/swap.h>
05da4558 34#include <linux/hugetlb.h>
2f333bcb 35#include <linux/compiler.h>
bc6678a3 36#include <linux/srcu.h>
5a0e3ad6 37#include <linux/slab.h>
bf998156 38#include <linux/uaccess.h>
6aa8b732 39
e495606d
AK		 40#include <asm/page.h>
41#include <asm/cmpxchg.h>
4e542370 42#include <asm/io.h>
13673a90 43#include <asm/vmx.h>
6aa8b732 44
18552672
JR		 45/*
46 * When setting this variable to true it enables Two-Dimensional-Paging
47 * where the hardware walks 2 page tables:
48 * 1. the guest-virtual to guest-physical
49 * 2. while doing 1. it walks guest-physical to host-physical
50 * If the hardware supports that we don't need to do shadow paging.
51 */
2f333bcb 52bool tdp_enabled = false;
18552672 53
8b1fe17c
XG		 54enum {
55 AUDIT_PRE_PAGE_FAULT,
56 AUDIT_POST_PAGE_FAULT,
57 AUDIT_PRE_PTE_WRITE,
6903074c
XG		 58 AUDIT_POST_PTE_WRITE,
59 AUDIT_PRE_SYNC,
60 AUDIT_POST_SYNC
8b1fe17c 61};
37a7d8b0 62
8b1fe17c
XG		 63char *audit_point_name[] = {
64 "pre page fault",
65 "post page fault",
66 "pre pte write",
6903074c
XG		 67 "post pte write",
68 "pre sync",
69 "post sync"
8b1fe17c 70};
37a7d8b0 71
8b1fe17c 72#undef MMU_DEBUG
37a7d8b0
AK		 73
74#ifdef MMU_DEBUG
75
76#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
77#define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
78
79#else
80
81#define pgprintk(x...) do { } while (0)
82#define rmap_printk(x...) do { } while (0)
83
84#endif
85
8b1fe17c 86#ifdef MMU_DEBUG
6ada8cca
AK		 87static int dbg = 0;
88module_param(dbg, bool, 0644);
37a7d8b0 89#endif
6aa8b732 90
582801a9
MT		 91static int oos_shadow = 1;
92module_param(oos_shadow, bool, 0644);
93
d6c69ee9
YD		 94#ifndef MMU_DEBUG
95#define ASSERT(x) do { } while (0)
96#else
6aa8b732
AK		 97#define ASSERT(x) \
98 if (!(x)) { \
99 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
100 __FILE__, __LINE__, #x); \
101 }
d6c69ee9 102#endif
6aa8b732 103
957ed9ef
XG		 104#define PTE_PREFETCH_NUM 8
105
6aa8b732
AK		 106#define PT_FIRST_AVAIL_BITS_SHIFT 9
107#define PT64_SECOND_AVAIL_BITS_SHIFT 52
108
6aa8b732
AK		 109#define PT64_LEVEL_BITS 9
110
111#define PT64_LEVEL_SHIFT(level) \
d77c26fc 112 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
6aa8b732 113
6aa8b732
AK		 114#define PT64_INDEX(address, level)\
115 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
116
117
118#define PT32_LEVEL_BITS 10
119
120#define PT32_LEVEL_SHIFT(level) \
d77c26fc 121 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
6aa8b732 122
e04da980
JR		 123#define PT32_LVL_OFFSET_MASK(level) \
124 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
125 * PT32_LEVEL_BITS))) - 1))
6aa8b732
AK		 126
127#define PT32_INDEX(address, level)\
128 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
129
130
27aba766 131#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
6aa8b732
AK		 132#define PT64_DIR_BASE_ADDR_MASK \
133 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
e04da980
JR		 134#define PT64_LVL_ADDR_MASK(level) \
135 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
136 * PT64_LEVEL_BITS))) - 1))
137#define PT64_LVL_OFFSET_MASK(level) \
138 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
139 * PT64_LEVEL_BITS))) - 1))
6aa8b732
AK		 140
141#define PT32_BASE_ADDR_MASK PAGE_MASK
142#define PT32_DIR_BASE_ADDR_MASK \
143 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
e04da980
JR		 144#define PT32_LVL_ADDR_MASK(level) \
145 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
146 * PT32_LEVEL_BITS))) - 1))
6aa8b732 147
79539cec
AK		 148#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
149 | PT64_NX_MASK)
6aa8b732 150
53c07b18 151#define PTE_LIST_EXT 4
cd4a4e53 152
fe135d2c
AK		 153#define ACC_EXEC_MASK 1
154#define ACC_WRITE_MASK PT_WRITABLE_MASK
155#define ACC_USER_MASK PT_USER_MASK
156#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
157
90bb6fc5
AK		 158#include <trace/events/kvm.h>
159
07420171
AK		 160#define CREATE_TRACE_POINTS
161#include "mmutrace.h"
162
1403283a
IE		 163#define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
164
135f8c2b
AK		 165#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
166
53c07b18
XG		 167struct pte_list_desc {
168 u64 *sptes[PTE_LIST_EXT];
169 struct pte_list_desc *more;
cd4a4e53
AK		 170};
171
2d11123a
AK		 172struct kvm_shadow_walk_iterator {
173 u64 addr;
174 hpa_t shadow_addr;
175 int level;
176 u64 *sptep;
177 unsigned index;
178};
179
180#define for_each_shadow_entry(_vcpu, _addr, _walker) \
181 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
182 shadow_walk_okay(&(_walker)); \
183 shadow_walk_next(&(_walker)))
184
53c07b18 185static struct kmem_cache *pte_list_desc_cache;
d3d25b04 186static struct kmem_cache *mmu_page_header_cache;
45221ab6 187static struct percpu_counter kvm_total_used_mmu_pages;
b5a33a75 188
c7addb90
AK		 189static u64 __read_mostly shadow_trap_nonpresent_pte;
190static u64 __read_mostly shadow_notrap_nonpresent_pte;
7b52345e
SY		 191static u64 __read_mostly shadow_nx_mask;
192static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
193static u64 __read_mostly shadow_user_mask;
194static u64 __read_mostly shadow_accessed_mask;
195static u64 __read_mostly shadow_dirty_mask;
c7addb90 196
82725b20
DE		 197static inline u64 rsvd_bits(int s, int e)
198{
199 return ((1ULL << (e - s + 1)) - 1) << s;
200}
201
c7addb90
AK		 202void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
203{
204 shadow_trap_nonpresent_pte = trap_pte;
205 shadow_notrap_nonpresent_pte = notrap_pte;
206}
207EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
208
7b52345e 209void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
4b12f0de 210 u64 dirty_mask, u64 nx_mask, u64 x_mask)
7b52345e
SY		 211{
212 shadow_user_mask = user_mask;
213 shadow_accessed_mask = accessed_mask;
214 shadow_dirty_mask = dirty_mask;
215 shadow_nx_mask = nx_mask;
216 shadow_x_mask = x_mask;
217}
218EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
219
3dbe1415 220static bool is_write_protection(struct kvm_vcpu *vcpu)
6aa8b732 221{
4d4ec087 222 return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
6aa8b732
AK		 223}
224
225static int is_cpuid_PSE36(void)
226{
227 return 1;
228}
229
73b1087e
AK		 230static int is_nx(struct kvm_vcpu *vcpu)
231{
f6801dff 232 return vcpu->arch.efer & EFER_NX;
73b1087e
AK		 233}
234
c7addb90
AK		 235static int is_shadow_present_pte(u64 pte)
236{
c7addb90
AK		 237 return pte != shadow_trap_nonpresent_pte
238 && pte != shadow_notrap_nonpresent_pte;
239}
240
05da4558
MT		 241static int is_large_pte(u64 pte)
242{
243 return pte & PT_PAGE_SIZE_MASK;
244}
245
8dae4445 246static int is_writable_pte(unsigned long pte)
6aa8b732
AK		 247{
248 return pte & PT_WRITABLE_MASK;
249}
250
43a3795a 251static int is_dirty_gpte(unsigned long pte)
e3c5e7ec 252{
439e218a 253 return pte & PT_DIRTY_MASK;
e3c5e7ec
AK		 254}
255
43a3795a 256static int is_rmap_spte(u64 pte)
cd4a4e53 257{
4b1a80fa 258 return is_shadow_present_pte(pte);
cd4a4e53
AK		 259}
260
776e6633
MT		 261static int is_last_spte(u64 pte, int level)
262{
263 if (level == PT_PAGE_TABLE_LEVEL)
264 return 1;
852e3c19 265 if (is_large_pte(pte))
776e6633
MT		 266 return 1;
267 return 0;
268}
269
35149e21 270static pfn_t spte_to_pfn(u64 pte)
0b49ea86 271{
35149e21 272 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
0b49ea86
AK		 273}
274
da928521
AK		 275static gfn_t pse36_gfn_delta(u32 gpte)
276{
277 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
278
279 return (gpte & PT32_DIR_PSE36_MASK) << shift;
280}
281
d555c333 282static void __set_spte(u64 *sptep, u64 spte)
e663ee64 283{
7645e432 284 set_64bit(sptep, spte);
e663ee64
AK		 285}
286
a9221dd5
AK		 287static u64 __xchg_spte(u64 *sptep, u64 new_spte)
288{
289#ifdef CONFIG_X86_64
290 return xchg(sptep, new_spte);
291#else
292 u64 old_spte;
293
294 do {
295 old_spte = *sptep;
296 } while (cmpxchg64(sptep, old_spte, new_spte) != old_spte);
297
298 return old_spte;
299#endif
300}
301
8672b721
XG		 302static bool spte_has_volatile_bits(u64 spte)
303{
304 if (!shadow_accessed_mask)
305 return false;
306
307 if (!is_shadow_present_pte(spte))
308 return false;
309
4132779b
XG		 310 if ((spte & shadow_accessed_mask) &&
311 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
8672b721
XG		 312 return false;
313
314 return true;
315}
316
4132779b
XG		 317static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
318{
319 return (old_spte & bit_mask) && !(new_spte & bit_mask);
320}
321
b79b93f9
AK		 322static void update_spte(u64 *sptep, u64 new_spte)
323{
4132779b
XG		 324 u64 mask, old_spte = *sptep;
325
326 WARN_ON(!is_rmap_spte(new_spte));
b79b93f9 327
4132779b
XG		 328 new_spte |= old_spte & shadow_dirty_mask;
329
330 mask = shadow_accessed_mask;
331 if (is_writable_pte(old_spte))
332 mask |= shadow_dirty_mask;
333
334 if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask)
b79b93f9 335 __set_spte(sptep, new_spte);
4132779b 336 else
b79b93f9 337 old_spte = __xchg_spte(sptep, new_spte);
4132779b
XG		 338
339 if (!shadow_accessed_mask)
340 return;
341
342 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
343 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
344 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
345 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
b79b93f9
AK		 346}
347
e2dec939 348static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
2e3e5882 349 struct kmem_cache *base_cache, int min)
714b93da
AK		 350{
351 void *obj;
352
353 if (cache->nobjs >= min)
e2dec939 354 return 0;
714b93da 355 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 356 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
714b93da 357 if (!obj)
e2dec939 358 return -ENOMEM;
714b93da
AK		 359 cache->objects[cache->nobjs++] = obj;
360 }
e2dec939 361 return 0;
714b93da
AK		 362}
363
e8ad9a70
XG		 364static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
365 struct kmem_cache *cache)
714b93da
AK		 366{
367 while (mc->nobjs)
e8ad9a70 368 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
714b93da
AK		 369}
370
c1158e63 371static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
2e3e5882 372 int min)
c1158e63 373{
842f22ed 374 void *page;
c1158e63
AK		 375
376 if (cache->nobjs >= min)
377 return 0;
378 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
842f22ed 379 page = (void *)__get_free_page(GFP_KERNEL);
c1158e63
AK		 380 if (!page)
381 return -ENOMEM;
842f22ed 382 cache->objects[cache->nobjs++] = page;
c1158e63
AK		 383 }
384 return 0;
385}
386
387static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
388{
389 while (mc->nobjs)
c4d198d5 390 free_page((unsigned long)mc->objects[--mc->nobjs]);
c1158e63
AK		 391}
392
2e3e5882 393static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
714b93da 394{
e2dec939
AK		 395 int r;
396
53c07b18 397 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
67052b35 398 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
d3d25b04
AK		 399 if (r)
400 goto out;
ad312c7c 401 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
d3d25b04
AK		 402 if (r)
403 goto out;
ad312c7c 404 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
2e3e5882 405 mmu_page_header_cache, 4);
e2dec939
AK		 406out:
407 return r;
714b93da
AK		 408}
409
410static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
411{
53c07b18
XG		 412 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
413 pte_list_desc_cache);
ad312c7c 414 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
e8ad9a70
XG		 415 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
416 mmu_page_header_cache);
714b93da
AK		 417}
418
419static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
420 size_t size)
421{
422 void *p;
423
424 BUG_ON(!mc->nobjs);
425 p = mc->objects[--mc->nobjs];
714b93da
AK		 426 return p;
427}
428
53c07b18 429static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
714b93da 430{
53c07b18
XG		 431 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache,
432 sizeof(struct pte_list_desc));
714b93da
AK		 433}
434
53c07b18 435static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
714b93da 436{
53c07b18 437 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
714b93da
AK		 438}
439
2032a93d
LJ		 440static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
441{
442 if (!sp->role.direct)
443 return sp->gfns[index];
444
445 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
446}
447
448static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
449{
450 if (sp->role.direct)
451 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
452 else
453 sp->gfns[index] = gfn;
454}
455
05da4558 456/*
d4dbf470
TY		 457 * Return the pointer to the large page information for a given gfn,
458 * handling slots that are not large page aligned.
05da4558 459 */
d4dbf470
TY		 460static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
461 struct kvm_memory_slot *slot,
462 int level)
05da4558
MT		 463{
464 unsigned long idx;
465
82855413
JR		 466 idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
467 (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
d4dbf470 468 return &slot->lpage_info[level - 2][idx];
05da4558
MT		 469}
470
471static void account_shadowed(struct kvm *kvm, gfn_t gfn)
472{
d25797b2 473 struct kvm_memory_slot *slot;
d4dbf470 474 struct kvm_lpage_info *linfo;
d25797b2 475 int i;
05da4558 476
a1f4d395 477 slot = gfn_to_memslot(kvm, gfn);
d25797b2
JR		 478 for (i = PT_DIRECTORY_LEVEL;
479 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
d4dbf470
TY		 480 linfo = lpage_info_slot(gfn, slot, i);
481 linfo->write_count += 1;
d25797b2 482 }
332b207d 483 kvm->arch.indirect_shadow_pages++;
05da4558
MT		 484}
485
486static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
487{
d25797b2 488 struct kvm_memory_slot *slot;
d4dbf470 489 struct kvm_lpage_info *linfo;
d25797b2 490 int i;
05da4558 491
a1f4d395 492 slot = gfn_to_memslot(kvm, gfn);
d25797b2
JR		 493 for (i = PT_DIRECTORY_LEVEL;
494 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
d4dbf470
TY		 495 linfo = lpage_info_slot(gfn, slot, i);
496 linfo->write_count -= 1;
497 WARN_ON(linfo->write_count < 0);
d25797b2 498 }
332b207d 499 kvm->arch.indirect_shadow_pages--;
05da4558
MT		 500}
501
d25797b2
JR		 502static int has_wrprotected_page(struct kvm *kvm,
503 gfn_t gfn,
504 int level)
05da4558 505{
2843099f 506 struct kvm_memory_slot *slot;
d4dbf470 507 struct kvm_lpage_info *linfo;
05da4558 508
a1f4d395 509 slot = gfn_to_memslot(kvm, gfn);
05da4558 510 if (slot) {
d4dbf470
TY		 511 linfo = lpage_info_slot(gfn, slot, level);
512 return linfo->write_count;
05da4558
MT		 513 }
514
515 return 1;
516}
517
d25797b2 518static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
05da4558 519{
8f0b1ab6 520 unsigned long page_size;
d25797b2 521 int i, ret = 0;
05da4558 522
8f0b1ab6 523 page_size = kvm_host_page_size(kvm, gfn);
05da4558 524
d25797b2
JR		 525 for (i = PT_PAGE_TABLE_LEVEL;
526 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
527 if (page_size >= KVM_HPAGE_SIZE(i))
528 ret = i;
529 else
530 break;
531 }
532
4c2155ce 533 return ret;
05da4558
MT		 534}
535
5d163b1c
XG		 536static struct kvm_memory_slot *
537gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
538 bool no_dirty_log)
05da4558
MT		 539{
540 struct kvm_memory_slot *slot;
5d163b1c
XG		 541
542 slot = gfn_to_memslot(vcpu->kvm, gfn);
543 if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
544 (no_dirty_log && slot->dirty_bitmap))
545 slot = NULL;
546
547 return slot;
548}
549
550static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
551{
a0a8eaba 552 return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
936a5fe6
AA		 553}
554
555static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
556{
557 int host_level, level, max_level;
05da4558 558
d25797b2
JR		 559 host_level = host_mapping_level(vcpu->kvm, large_gfn);
560
561 if (host_level == PT_PAGE_TABLE_LEVEL)
562 return host_level;
563
878403b7
SY		 564 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
565 kvm_x86_ops->get_lpage_level() : host_level;
566
567 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
d25797b2
JR		 568 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
569 break;
d25797b2
JR		 570
571 return level - 1;
05da4558
MT		 572}
573
290fc38d 574/*
53c07b18 575 * Pte mapping structures:
cd4a4e53 576 *
53c07b18 577 * If pte_list bit zero is zero, then pte_list point to the spte.
cd4a4e53 578 *
53c07b18
XG		 579 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
580 * pte_list_desc containing more mappings.
53a27b39 581 *
53c07b18 582 * Returns the number of pte entries before the spte was added or zero if
53a27b39
MT		 583 * the spte was not added.
584 *
cd4a4e53 585 */
53c07b18
XG		 586static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
587 unsigned long *pte_list)
cd4a4e53 588{
53c07b18 589 struct pte_list_desc *desc;
53a27b39 590 int i, count = 0;
cd4a4e53 591
53c07b18
XG		 592 if (!*pte_list) {
593 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
594 *pte_list = (unsigned long)spte;
595 } else if (!(*pte_list & 1)) {
596 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
597 desc = mmu_alloc_pte_list_desc(vcpu);
598 desc->sptes[0] = (u64 *)*pte_list;
d555c333 599 desc->sptes[1] = spte;
53c07b18 600 *pte_list = (unsigned long)desc | 1;
cb16a7b3 601 ++count;
cd4a4e53 602 } else {
53c07b18
XG		 603 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
604 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
605 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
cd4a4e53 606 desc = desc->more;
53c07b18 607 count += PTE_LIST_EXT;
53a27b39 608 }
53c07b18
XG		 609 if (desc->sptes[PTE_LIST_EXT-1]) {
610 desc->more = mmu_alloc_pte_list_desc(vcpu);
cd4a4e53
AK		 611 desc = desc->more;
612 }
d555c333 613 for (i = 0; desc->sptes[i]; ++i)
cb16a7b3 614 ++count;
d555c333 615 desc->sptes[i] = spte;
cd4a4e53 616 }
53a27b39 617 return count;
cd4a4e53
AK		 618}
619
53c07b18
XG		 620static u64 *pte_list_next(unsigned long *pte_list, u64 *spte)
621{
622 struct pte_list_desc *desc;
623 u64 *prev_spte;
624 int i;
625
626 if (!*pte_list)
627 return NULL;
628 else if (!(*pte_list & 1)) {
629 if (!spte)
630 return (u64 *)*pte_list;
631 return NULL;
632 }
633 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
634 prev_spte = NULL;
635 while (desc) {
636 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
637 if (prev_spte == spte)
638 return desc->sptes[i];
639 prev_spte = desc->sptes[i];
640 }
641 desc = desc->more;
642 }
643 return NULL;
644}
645
646static void
647pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
648 int i, struct pte_list_desc *prev_desc)
cd4a4e53
AK		 649{
650 int j;
651
53c07b18 652 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
cd4a4e53 653 ;
d555c333
AK		 654 desc->sptes[i] = desc->sptes[j];
655 desc->sptes[j] = NULL;
cd4a4e53
AK		 656 if (j != 0)
657 return;
658 if (!prev_desc && !desc->more)
53c07b18 659 *pte_list = (unsigned long)desc->sptes[0];
cd4a4e53
AK		 660 else
661 if (prev_desc)
662 prev_desc->more = desc->more;
663 else
53c07b18
XG		 664 *pte_list = (unsigned long)desc->more | 1;
665 mmu_free_pte_list_desc(desc);
cd4a4e53
AK		 666}
667
53c07b18 668static void pte_list_remove(u64 *spte, unsigned long *pte_list)
cd4a4e53 669{
53c07b18
XG		 670 struct pte_list_desc *desc;
671 struct pte_list_desc *prev_desc;
cd4a4e53
AK		 672 int i;
673
53c07b18
XG		 674 if (!*pte_list) {
675 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
cd4a4e53 676 BUG();
53c07b18
XG		 677 } else if (!(*pte_list & 1)) {
678 rmap_printk("pte_list_remove: %p 1->0\n", spte);
679 if ((u64 *)*pte_list != spte) {
680 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
cd4a4e53
AK		 681 BUG();
682 }
53c07b18 683 *pte_list = 0;
cd4a4e53 684 } else {
53c07b18
XG		 685 rmap_printk("pte_list_remove: %p many->many\n", spte);
686 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
cd4a4e53
AK		 687 prev_desc = NULL;
688 while (desc) {
53c07b18 689 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
d555c333 690 if (desc->sptes[i] == spte) {
53c07b18 691 pte_list_desc_remove_entry(pte_list,
714b93da 692 desc, i,
cd4a4e53
AK		 693 prev_desc);
694 return;
695 }
696 prev_desc = desc;
697 desc = desc->more;
698 }
53c07b18 699 pr_err("pte_list_remove: %p many->many\n", spte);
cd4a4e53
AK		 700 BUG();
701 }
702}
703
67052b35
XG		 704typedef void (*pte_list_walk_fn) (u64 *spte);
705static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
706{
707 struct pte_list_desc *desc;
708 int i;
709
710 if (!*pte_list)
711 return;
712
713 if (!(*pte_list & 1))
714 return fn((u64 *)*pte_list);
715
716 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
717 while (desc) {
718 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
719 fn(desc->sptes[i]);
720 desc = desc->more;
721 }
722}
723
53c07b18
XG		 724/*
725 * Take gfn and return the reverse mapping to it.
726 */
727static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
728{
729 struct kvm_memory_slot *slot;
730 struct kvm_lpage_info *linfo;
731
732 slot = gfn_to_memslot(kvm, gfn);
733 if (likely(level == PT_PAGE_TABLE_LEVEL))
734 return &slot->rmap[gfn - slot->base_gfn];
735
736 linfo = lpage_info_slot(gfn, slot, level);
737
738 return &linfo->rmap_pde;
739}
740
741static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
742{
743 struct kvm_mmu_page *sp;
744 unsigned long *rmapp;
745
746 if (!is_rmap_spte(*spte))
747 return 0;
748
749 sp = page_header(__pa(spte));
750 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
751 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
752 return pte_list_add(vcpu, spte, rmapp);
753}
754
755static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
756{
757 return pte_list_next(rmapp, spte);
758}
759
760static void rmap_remove(struct kvm *kvm, u64 *spte)
761{
762 struct kvm_mmu_page *sp;
763 gfn_t gfn;
764 unsigned long *rmapp;
765
766 sp = page_header(__pa(spte));
767 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
768 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
769 pte_list_remove(spte, rmapp);
770}
771
eb45fda4 772static int set_spte_track_bits(u64 *sptep, u64 new_spte)
be38d276 773{
ce061867 774 pfn_t pfn;
9a3aad70
XG		 775 u64 old_spte = *sptep;
776
8672b721 777 if (!spte_has_volatile_bits(old_spte))
9a3aad70 778 __set_spte(sptep, new_spte);
8672b721 779 else
9a3aad70 780 old_spte = __xchg_spte(sptep, new_spte);
ce061867 781
a9221dd5 782 if (!is_rmap_spte(old_spte))
eb45fda4 783 return 0;
8672b721 784
a9221dd5 785 pfn = spte_to_pfn(old_spte);
daa3db69 786 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
ce061867 787 kvm_set_pfn_accessed(pfn);
4132779b 788 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
ce061867 789 kvm_set_pfn_dirty(pfn);
eb45fda4 790 return 1;
e4b502ea
XG		 791}
792
793static void drop_spte(struct kvm *kvm, u64 *sptep, u64 new_spte)
794{
eb45fda4
MT		 795 if (set_spte_track_bits(sptep, new_spte))
796 rmap_remove(kvm, sptep);
be38d276
AK		 797}
798
b1a36821 799static int rmap_write_protect(struct kvm *kvm, u64 gfn)
98348e95 800{
290fc38d 801 unsigned long *rmapp;
374cbac0 802 u64 *spte;
44ad9944 803 int i, write_protected = 0;
374cbac0 804
44ad9944 805 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
374cbac0 806
98348e95
IE		 807 spte = rmap_next(kvm, rmapp, NULL);
808 while (spte) {
374cbac0 809 BUG_ON(!spte);
374cbac0 810 BUG_ON(!(*spte & PT_PRESENT_MASK));
374cbac0 811 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
8dae4445 812 if (is_writable_pte(*spte)) {
b79b93f9 813 update_spte(spte, *spte & ~PT_WRITABLE_MASK);
caa5b8a5
ED		 814 write_protected = 1;
815 }
9647c14c 816 spte = rmap_next(kvm, rmapp, spte);
374cbac0 817 }
855149aa 818
05da4558 819 /* check for huge page mappings */
44ad9944
JR		 820 for (i = PT_DIRECTORY_LEVEL;
821 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
822 rmapp = gfn_to_rmap(kvm, gfn, i);
823 spte = rmap_next(kvm, rmapp, NULL);
824 while (spte) {
825 BUG_ON(!spte);
826 BUG_ON(!(*spte & PT_PRESENT_MASK));
827 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
828 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
8dae4445 829 if (is_writable_pte(*spte)) {
be38d276
AK		 830 drop_spte(kvm, spte,
831 shadow_trap_nonpresent_pte);
44ad9944 832 --kvm->stat.lpages;
44ad9944
JR		 833 spte = NULL;
834 write_protected = 1;
835 }
836 spte = rmap_next(kvm, rmapp, spte);
05da4558 837 }
05da4558
MT		 838 }
839
b1a36821 840 return write_protected;
374cbac0
AK		 841}
842
8a8365c5
FD		 843static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
844 unsigned long data)
e930bffe
AA		 845{
846 u64 *spte;
847 int need_tlb_flush = 0;
848
849 while ((spte = rmap_next(kvm, rmapp, NULL))) {
850 BUG_ON(!(*spte & PT_PRESENT_MASK));
851 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
be38d276 852 drop_spte(kvm, spte, shadow_trap_nonpresent_pte);
e930bffe
AA		 853 need_tlb_flush = 1;
854 }
855 return need_tlb_flush;
856}
857
8a8365c5
FD		 858static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
859 unsigned long data)
3da0dd43
IE		 860{
861 int need_flush = 0;
e4b502ea 862 u64 *spte, new_spte;
3da0dd43
IE		 863 pte_t *ptep = (pte_t *)data;
864 pfn_t new_pfn;
865
866 WARN_ON(pte_huge(*ptep));
867 new_pfn = pte_pfn(*ptep);
868 spte = rmap_next(kvm, rmapp, NULL);
869 while (spte) {
870 BUG_ON(!is_shadow_present_pte(*spte));
871 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
872 need_flush = 1;
873 if (pte_write(*ptep)) {
be38d276 874 drop_spte(kvm, spte, shadow_trap_nonpresent_pte);
3da0dd43
IE		 875 spte = rmap_next(kvm, rmapp, NULL);
876 } else {
877 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
878 new_spte |= (u64)new_pfn << PAGE_SHIFT;
879
880 new_spte &= ~PT_WRITABLE_MASK;
881 new_spte &= ~SPTE_HOST_WRITEABLE;
b79b93f9 882 new_spte &= ~shadow_accessed_mask;
e4b502ea 883 set_spte_track_bits(spte, new_spte);
3da0dd43
IE		 884 spte = rmap_next(kvm, rmapp, spte);
885 }
886 }
887 if (need_flush)
888 kvm_flush_remote_tlbs(kvm);
889
890 return 0;
891}
892
8a8365c5
FD		 893static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
894 unsigned long data,
3da0dd43 895 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
8a8365c5 896 unsigned long data))
e930bffe 897{
852e3c19 898 int i, j;
90bb6fc5 899 int ret;
e930bffe 900 int retval = 0;
bc6678a3
MT		 901 struct kvm_memslots *slots;
902
90d83dc3 903 slots = kvm_memslots(kvm);
e930bffe 904
46a26bf5
MT		 905 for (i = 0; i < slots->nmemslots; i++) {
906 struct kvm_memory_slot *memslot = &slots->memslots[i];
e930bffe
AA		 907 unsigned long start = memslot->userspace_addr;
908 unsigned long end;
909
e930bffe
AA		 910 end = start + (memslot->npages << PAGE_SHIFT);
911 if (hva >= start && hva < end) {
912 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
d4dbf470 913 gfn_t gfn = memslot->base_gfn + gfn_offset;
852e3c19 914
90bb6fc5 915 ret = handler(kvm, &memslot->rmap[gfn_offset], data);
852e3c19
JR		 916
917 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
d4dbf470
TY		 918 struct kvm_lpage_info *linfo;
919
920 linfo = lpage_info_slot(gfn, memslot,
921 PT_DIRECTORY_LEVEL + j);
922 ret |= handler(kvm, &linfo->rmap_pde, data);
852e3c19 923 }
90bb6fc5
AK		 924 trace_kvm_age_page(hva, memslot, ret);
925 retval |= ret;
e930bffe
AA		 926 }
927 }
928
929 return retval;
930}
931
932int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
933{
3da0dd43
IE		 934 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
935}
936
937void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
938{
8a8365c5 939 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
e930bffe
AA		 940}
941
8a8365c5
FD		 942static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
943 unsigned long data)
e930bffe
AA		 944{
945 u64 *spte;
946 int young = 0;
947
6316e1c8
RR		 948 /*
949 * Emulate the accessed bit for EPT, by checking if this page has
950 * an EPT mapping, and clearing it if it does. On the next access,
951 * a new EPT mapping will be established.
952 * This has some overhead, but not as much as the cost of swapping
953 * out actively used pages or breaking up actively used hugepages.
954 */
534e38b4 955 if (!shadow_accessed_mask)
6316e1c8 956 return kvm_unmap_rmapp(kvm, rmapp, data);
534e38b4 957
e930bffe
AA		 958 spte = rmap_next(kvm, rmapp, NULL);
959 while (spte) {
960 int _young;
961 u64 _spte = *spte;
962 BUG_ON(!(_spte & PT_PRESENT_MASK));
963 _young = _spte & PT_ACCESSED_MASK;
964 if (_young) {
965 young = 1;
966 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
967 }
968 spte = rmap_next(kvm, rmapp, spte);
969 }
970 return young;
971}
972
8ee53820
AA		 973static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
974 unsigned long data)
975{
976 u64 *spte;
977 int young = 0;
978
979 /*
980 * If there's no access bit in the secondary pte set by the
981 * hardware it's up to gup-fast/gup to set the access bit in
982 * the primary pte or in the page structure.
983 */
984 if (!shadow_accessed_mask)
985 goto out;
986
987 spte = rmap_next(kvm, rmapp, NULL);
988 while (spte) {
989 u64 _spte = *spte;
990 BUG_ON(!(_spte & PT_PRESENT_MASK));
991 young = _spte & PT_ACCESSED_MASK;
992 if (young) {
993 young = 1;
994 break;
995 }
996 spte = rmap_next(kvm, rmapp, spte);
997 }
998out:
999 return young;
1000}
1001
53a27b39
MT		 1002#define RMAP_RECYCLE_THRESHOLD 1000
1003
852e3c19 1004static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
53a27b39
MT		 1005{
1006 unsigned long *rmapp;
852e3c19
JR		 1007 struct kvm_mmu_page *sp;
1008
1009 sp = page_header(__pa(spte));
53a27b39 1010
852e3c19 1011 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
53a27b39 1012
3da0dd43 1013 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
53a27b39
MT		 1014 kvm_flush_remote_tlbs(vcpu->kvm);
1015}
1016
e930bffe
AA		 1017int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1018{
3da0dd43 1019 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
e930bffe
AA		 1020}
1021
8ee53820
AA		 1022int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1023{
1024 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1025}
1026
d6c69ee9 1027#ifdef MMU_DEBUG
47ad8e68 1028static int is_empty_shadow_page(u64 *spt)
6aa8b732 1029{
139bdb2d
AK		 1030 u64 *pos;
1031 u64 *end;
1032
47ad8e68 1033 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
3c915510 1034 if (is_shadow_present_pte(*pos)) {
b8688d51 1035 printk(KERN_ERR "%s: %p %llx\n", __func__,
139bdb2d 1036 pos, *pos);
6aa8b732 1037 return 0;
139bdb2d 1038 }
6aa8b732
AK		 1039 return 1;
1040}
d6c69ee9 1041#endif
6aa8b732 1042
45221ab6
DH		 1043/*
1044 * This value is the sum of all of the kvm instances's
1045 * kvm->arch.n_used_mmu_pages values. We need a global,
1046 * aggregate version in order to make the slab shrinker
1047 * faster
1048 */
1049static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1050{
1051 kvm->arch.n_used_mmu_pages += nr;
1052 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1053}
1054
4db35314 1055static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
260746c0 1056{
4db35314 1057 ASSERT(is_empty_shadow_page(sp->spt));
7775834a 1058 hlist_del(&sp->hash_link);
4db35314 1059 list_del(&sp->link);
842f22ed 1060 free_page((unsigned long)sp->spt);
2032a93d 1061 if (!sp->role.direct)
842f22ed 1062 free_page((unsigned long)sp->gfns);
e8ad9a70 1063 kmem_cache_free(mmu_page_header_cache, sp);
45221ab6 1064 kvm_mod_used_mmu_pages(kvm, -1);
260746c0
AK		 1065}
1066
cea0f0e7
AK		 1067static unsigned kvm_page_table_hashfn(gfn_t gfn)
1068{
1ae0a13d 1069 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
cea0f0e7
AK		 1070}
1071
714b93da 1072static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
4db35314 1073 struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 1074{
cea0f0e7
AK		 1075 if (!parent_pte)
1076 return;
cea0f0e7 1077
67052b35 1078 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
cea0f0e7
AK		 1079}
1080
4db35314 1081static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
cea0f0e7
AK		 1082 u64 *parent_pte)
1083{
67052b35 1084 pte_list_remove(parent_pte, &sp->parent_ptes);
cea0f0e7
AK		 1085}
1086
bcdd9a93
XG		 1087static void drop_parent_pte(struct kvm_mmu_page *sp,
1088 u64 *parent_pte)
1089{
1090 mmu_page_remove_parent_pte(sp, parent_pte);
1091 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
1092}
1093
67052b35
XG		 1094static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1095 u64 *parent_pte, int direct)
ad8cfbe3 1096{
67052b35
XG		 1097 struct kvm_mmu_page *sp;
1098 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache,
1099 sizeof *sp);
1100 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
1101 if (!direct)
1102 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache,
1103 PAGE_SIZE);
1104 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1105 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1106 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
1107 sp->parent_ptes = 0;
1108 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1109 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1110 return sp;
ad8cfbe3
MT		 1111}
1112
67052b35 1113static void mark_unsync(u64 *spte);
1047df1f 1114static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
0074ff63 1115{
67052b35 1116 pte_list_walk(&sp->parent_ptes, mark_unsync);
0074ff63
MT		 1117}
1118
67052b35 1119static void mark_unsync(u64 *spte)
0074ff63 1120{
67052b35 1121 struct kvm_mmu_page *sp;
1047df1f 1122 unsigned int index;
0074ff63 1123
67052b35 1124 sp = page_header(__pa(spte));
1047df1f
XG		 1125 index = spte - sp->spt;
1126 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
0074ff63 1127 return;
1047df1f 1128 if (sp->unsync_children++)
0074ff63 1129 return;
1047df1f 1130 kvm_mmu_mark_parents_unsync(sp);
0074ff63
MT		 1131}
1132
d761a501
AK		 1133static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1134 struct kvm_mmu_page *sp)
1135{
1136 int i;
1137
1138 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1139 sp->spt[i] = shadow_trap_nonpresent_pte;
1140}
1141
e8bc217a 1142static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
a4a8e6f7 1143 struct kvm_mmu_page *sp)
e8bc217a
MT		 1144{
1145 return 1;
1146}
1147
a7052897
MT		 1148static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1149{
1150}
1151
0f53b5b1
XG		 1152static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1153 struct kvm_mmu_page *sp, u64 *spte,
7c562522 1154 const void *pte)
0f53b5b1
XG		 1155{
1156 WARN_ON(1);
1157}
1158
60c8aec6
MT		 1159#define KVM_PAGE_ARRAY_NR 16
1160
1161struct kvm_mmu_pages {
1162 struct mmu_page_and_offset {
1163 struct kvm_mmu_page *sp;
1164 unsigned int idx;
1165 } page[KVM_PAGE_ARRAY_NR];
1166 unsigned int nr;
1167};
1168
0074ff63
MT		 1169#define for_each_unsync_children(bitmap, idx) \
1170 for (idx = find_first_bit(bitmap, 512); \
1171 idx < 512; \
1172 idx = find_next_bit(bitmap, 512, idx+1))
1173
cded19f3
HE		 1174static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1175 int idx)
4731d4c7 1176{
60c8aec6 1177 int i;
4731d4c7 1178
60c8aec6
MT		 1179 if (sp->unsync)
1180 for (i=0; i < pvec->nr; i++)
1181 if (pvec->page[i].sp == sp)
1182 return 0;
1183
1184 pvec->page[pvec->nr].sp = sp;
1185 pvec->page[pvec->nr].idx = idx;
1186 pvec->nr++;
1187 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1188}
1189
1190static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1191 struct kvm_mmu_pages *pvec)
1192{
1193 int i, ret, nr_unsync_leaf = 0;
4731d4c7 1194
0074ff63 1195 for_each_unsync_children(sp->unsync_child_bitmap, i) {
7a8f1a74 1196 struct kvm_mmu_page *child;
4731d4c7
MT		 1197 u64 ent = sp->spt[i];
1198
7a8f1a74
XG		 1199 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1200 goto clear_child_bitmap;
1201
1202 child = page_header(ent & PT64_BASE_ADDR_MASK);
1203
1204 if (child->unsync_children) {
1205 if (mmu_pages_add(pvec, child, i))
1206 return -ENOSPC;
1207
1208 ret = __mmu_unsync_walk(child, pvec);
1209 if (!ret)
1210 goto clear_child_bitmap;
1211 else if (ret > 0)
1212 nr_unsync_leaf += ret;
1213 else
1214 return ret;
1215 } else if (child->unsync) {
1216 nr_unsync_leaf++;
1217 if (mmu_pages_add(pvec, child, i))
1218 return -ENOSPC;
1219 } else
1220 goto clear_child_bitmap;
1221
1222 continue;
1223
1224clear_child_bitmap:
1225 __clear_bit(i, sp->unsync_child_bitmap);
1226 sp->unsync_children--;
1227 WARN_ON((int)sp->unsync_children < 0);
4731d4c7
MT		 1228 }
1229
4731d4c7 1230
60c8aec6
MT		 1231 return nr_unsync_leaf;
1232}
1233
1234static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1235 struct kvm_mmu_pages *pvec)
1236{
1237 if (!sp->unsync_children)
1238 return 0;
1239
1240 mmu_pages_add(pvec, sp, 0);
1241 return __mmu_unsync_walk(sp, pvec);
4731d4c7
MT		 1242}
1243
4731d4c7
MT		 1244static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1245{
1246 WARN_ON(!sp->unsync);
5e1b3ddb 1247 trace_kvm_mmu_sync_page(sp);
4731d4c7
MT		 1248 sp->unsync = 0;
1249 --kvm->stat.mmu_unsync;
1250}
1251
7775834a
XG		 1252static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1253 struct list_head *invalid_list);
1254static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1255 struct list_head *invalid_list);
4731d4c7 1256
f41d335a
XG		 1257#define for_each_gfn_sp(kvm, sp, gfn, pos) \
1258 hlist_for_each_entry(sp, pos, \
7ae680eb
XG		 1259 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1260 if ((sp)->gfn != (gfn)) {} else
1261
f41d335a
XG		 1262#define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \
1263 hlist_for_each_entry(sp, pos, \
7ae680eb
XG		 1264 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1265 if ((sp)->gfn != (gfn) || (sp)->role.direct || \
1266 (sp)->role.invalid) {} else
1267
f918b443 1268/* @sp->gfn should be write-protected at the call site */
1d9dc7e0 1269static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
d98ba053 1270 struct list_head *invalid_list, bool clear_unsync)
4731d4c7 1271{
5b7e0102 1272 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
d98ba053 1273 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
4731d4c7
MT		 1274 return 1;
1275 }
1276
f918b443 1277 if (clear_unsync)
1d9dc7e0 1278 kvm_unlink_unsync_page(vcpu->kvm, sp);
1d9dc7e0 1279
a4a8e6f7 1280 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
d98ba053 1281 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
4731d4c7
MT		 1282 return 1;
1283 }
1284
1285 kvm_mmu_flush_tlb(vcpu);
4731d4c7
MT		 1286 return 0;
1287}
1288
1d9dc7e0
XG		 1289static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1290 struct kvm_mmu_page *sp)
1291{
d98ba053 1292 LIST_HEAD(invalid_list);
1d9dc7e0
XG		 1293 int ret;
1294
d98ba053 1295 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
be71e061 1296 if (ret)
d98ba053
XG		 1297 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1298
1d9dc7e0
XG		 1299 return ret;
1300}
1301
d98ba053
XG		 1302static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1303 struct list_head *invalid_list)
1d9dc7e0 1304{
d98ba053 1305 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1d9dc7e0
XG		 1306}
1307
9f1a122f
XG		 1308/* @gfn should be write-protected at the call site */
1309static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1310{
9f1a122f 1311 struct kvm_mmu_page *s;
f41d335a 1312 struct hlist_node *node;
d98ba053 1313 LIST_HEAD(invalid_list);
9f1a122f
XG		 1314 bool flush = false;
1315
f41d335a 1316 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
7ae680eb 1317 if (!s->unsync)
9f1a122f
XG		 1318 continue;
1319
1320 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
a4a8e6f7 1321 kvm_unlink_unsync_page(vcpu->kvm, s);
9f1a122f 1322 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
a4a8e6f7 1323 (vcpu->arch.mmu.sync_page(vcpu, s))) {
d98ba053 1324 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
9f1a122f
XG		 1325 continue;
1326 }
9f1a122f
XG		 1327 flush = true;
1328 }
1329
d98ba053 1330 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
9f1a122f
XG		 1331 if (flush)
1332 kvm_mmu_flush_tlb(vcpu);
1333}
1334
60c8aec6
MT		 1335struct mmu_page_path {
1336 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1337 unsigned int idx[PT64_ROOT_LEVEL-1];
4731d4c7
MT		 1338};
1339
60c8aec6
MT		 1340#define for_each_sp(pvec, sp, parents, i) \
1341 for (i = mmu_pages_next(&pvec, &parents, -1), \
1342 sp = pvec.page[i].sp; \
1343 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1344 i = mmu_pages_next(&pvec, &parents, i))
1345
cded19f3
HE		 1346static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1347 struct mmu_page_path *parents,
1348 int i)
60c8aec6
MT		 1349{
1350 int n;
1351
1352 for (n = i+1; n < pvec->nr; n++) {
1353 struct kvm_mmu_page *sp = pvec->page[n].sp;
1354
1355 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1356 parents->idx[0] = pvec->page[n].idx;
1357 return n;
1358 }
1359
1360 parents->parent[sp->role.level-2] = sp;
1361 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1362 }
1363
1364 return n;
1365}
1366
cded19f3 1367static void mmu_pages_clear_parents(struct mmu_page_path *parents)
4731d4c7 1368{
60c8aec6
MT		 1369 struct kvm_mmu_page *sp;
1370 unsigned int level = 0;
1371
1372 do {
1373 unsigned int idx = parents->idx[level];
4731d4c7 1374
60c8aec6
MT		 1375 sp = parents->parent[level];
1376 if (!sp)
1377 return;
1378
1379 --sp->unsync_children;
1380 WARN_ON((int)sp->unsync_children < 0);
1381 __clear_bit(idx, sp->unsync_child_bitmap);
1382 level++;
1383 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
4731d4c7
MT		 1384}
1385
60c8aec6
MT		 1386static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1387 struct mmu_page_path *parents,
1388 struct kvm_mmu_pages *pvec)
4731d4c7 1389{
60c8aec6
MT		 1390 parents->parent[parent->role.level-1] = NULL;
1391 pvec->nr = 0;
1392}
4731d4c7 1393
60c8aec6
MT		 1394static void mmu_sync_children(struct kvm_vcpu *vcpu,
1395 struct kvm_mmu_page *parent)
1396{
1397 int i;
1398 struct kvm_mmu_page *sp;
1399 struct mmu_page_path parents;
1400 struct kvm_mmu_pages pages;
d98ba053 1401 LIST_HEAD(invalid_list);
60c8aec6
MT		 1402
1403 kvm_mmu_pages_init(parent, &parents, &pages);
1404 while (mmu_unsync_walk(parent, &pages)) {
b1a36821
MT		 1405 int protected = 0;
1406
1407 for_each_sp(pages, sp, parents, i)
1408 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1409
1410 if (protected)
1411 kvm_flush_remote_tlbs(vcpu->kvm);
1412
60c8aec6 1413 for_each_sp(pages, sp, parents, i) {
d98ba053 1414 kvm_sync_page(vcpu, sp, &invalid_list);
60c8aec6
MT		 1415 mmu_pages_clear_parents(&parents);
1416 }
d98ba053 1417 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4731d4c7 1418 cond_resched_lock(&vcpu->kvm->mmu_lock);
60c8aec6
MT		 1419 kvm_mmu_pages_init(parent, &parents, &pages);
1420 }
4731d4c7
MT		 1421}
1422
cea0f0e7
AK		 1423static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1424 gfn_t gfn,
1425 gva_t gaddr,
1426 unsigned level,
f6e2c02b 1427 int direct,
41074d07 1428 unsigned access,
f7d9c7b7 1429 u64 *parent_pte)
cea0f0e7
AK		 1430{
1431 union kvm_mmu_page_role role;
cea0f0e7 1432 unsigned quadrant;
9f1a122f 1433 struct kvm_mmu_page *sp;
f41d335a 1434 struct hlist_node *node;
9f1a122f 1435 bool need_sync = false;
cea0f0e7 1436
a770f6f2 1437 role = vcpu->arch.mmu.base_role;
cea0f0e7 1438 role.level = level;
f6e2c02b 1439 role.direct = direct;
84b0c8c6 1440 if (role.direct)
5b7e0102 1441 role.cr4_pae = 0;
41074d07 1442 role.access = access;
c5a78f2b
JR		 1443 if (!vcpu->arch.mmu.direct_map
1444 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
cea0f0e7
AK		 1445 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1446 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1447 role.quadrant = quadrant;
1448 }
f41d335a 1449 for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
7ae680eb
XG		 1450 if (!need_sync && sp->unsync)
1451 need_sync = true;
4731d4c7 1452
7ae680eb
XG		 1453 if (sp->role.word != role.word)
1454 continue;
4731d4c7 1455
7ae680eb
XG		 1456 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1457 break;
e02aa901 1458
7ae680eb
XG		 1459 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1460 if (sp->unsync_children) {
a8eeb04a 1461 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
7ae680eb
XG		 1462 kvm_mmu_mark_parents_unsync(sp);
1463 } else if (sp->unsync)
1464 kvm_mmu_mark_parents_unsync(sp);
e02aa901 1465
7ae680eb
XG		 1466 trace_kvm_mmu_get_page(sp, false);
1467 return sp;
1468 }
dfc5aa00 1469 ++vcpu->kvm->stat.mmu_cache_miss;
2032a93d 1470 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
4db35314
AK		 1471 if (!sp)
1472 return sp;
4db35314
AK		 1473 sp->gfn = gfn;
1474 sp->role = role;
7ae680eb
XG		 1475 hlist_add_head(&sp->hash_link,
1476 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
f6e2c02b 1477 if (!direct) {
b1a36821
MT		 1478 if (rmap_write_protect(vcpu->kvm, gfn))
1479 kvm_flush_remote_tlbs(vcpu->kvm);
9f1a122f
XG		 1480 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1481 kvm_sync_pages(vcpu, gfn);
1482
4731d4c7
MT		 1483 account_shadowed(vcpu->kvm, gfn);
1484 }
131d8279
AK		 1485 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1486 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1487 else
1488 nonpaging_prefetch_page(vcpu, sp);
f691fe1d 1489 trace_kvm_mmu_get_page(sp, true);
4db35314 1490 return sp;
cea0f0e7
AK		 1491}
1492
2d11123a
AK		 1493static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1494 struct kvm_vcpu *vcpu, u64 addr)
1495{
1496 iterator->addr = addr;
1497 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1498 iterator->level = vcpu->arch.mmu.shadow_root_level;
81407ca5
JR		 1499
1500 if (iterator->level == PT64_ROOT_LEVEL &&
1501 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1502 !vcpu->arch.mmu.direct_map)
1503 --iterator->level;
1504
2d11123a
AK		 1505 if (iterator->level == PT32E_ROOT_LEVEL) {
1506 iterator->shadow_addr
1507 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1508 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1509 --iterator->level;
1510 if (!iterator->shadow_addr)
1511 iterator->level = 0;
1512 }
1513}
1514
1515static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1516{
1517 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1518 return false;
4d88954d
MT		 1519
1520 if (iterator->level == PT_PAGE_TABLE_LEVEL)
1521 if (is_large_pte(*iterator->sptep))
1522 return false;
1523
2d11123a
AK		 1524 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1525 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1526 return true;
1527}
1528
1529static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1530{
1531 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1532 --iterator->level;
1533}
1534
32ef26a3
AK		 1535static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1536{
1537 u64 spte;
1538
1539 spte = __pa(sp->spt)
1540 | PT_PRESENT_MASK | PT_ACCESSED_MASK
1541 | PT_WRITABLE_MASK | PT_USER_MASK;
121eee97 1542 __set_spte(sptep, spte);
32ef26a3
AK		 1543}
1544
a3aa51cf
AK		 1545static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1546{
1547 if (is_large_pte(*sptep)) {
1548 drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte);
1549 kvm_flush_remote_tlbs(vcpu->kvm);
1550 }
1551}
1552
a357bd22
AK		 1553static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1554 unsigned direct_access)
1555{
1556 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1557 struct kvm_mmu_page *child;
1558
1559 /*
1560 * For the direct sp, if the guest pte's dirty bit
1561 * changed form clean to dirty, it will corrupt the
1562 * sp's access: allow writable in the read-only sp,
1563 * so we should update the spte at this point to get
1564 * a new sp with the correct access.
1565 */
1566 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1567 if (child->role.access == direct_access)
1568 return;
1569
bcdd9a93 1570 drop_parent_pte(child, sptep);
a357bd22
AK		 1571 kvm_flush_remote_tlbs(vcpu->kvm);
1572 }
1573}
1574
38e3b2b2
XG		 1575static void mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
1576 u64 *spte)
1577{
1578 u64 pte;
1579 struct kvm_mmu_page *child;
1580
1581 pte = *spte;
1582 if (is_shadow_present_pte(pte)) {
1583 if (is_last_spte(pte, sp->role.level))
1584 drop_spte(kvm, spte, shadow_trap_nonpresent_pte);
1585 else {
1586 child = page_header(pte & PT64_BASE_ADDR_MASK);
bcdd9a93 1587 drop_parent_pte(child, spte);
38e3b2b2
XG		 1588 }
1589 }
1590 __set_spte(spte, shadow_trap_nonpresent_pte);
1591 if (is_large_pte(pte))
1592 --kvm->stat.lpages;
1593}
1594
90cb0529 1595static void kvm_mmu_page_unlink_children(struct kvm *kvm,
4db35314 1596 struct kvm_mmu_page *sp)
a436036b 1597{
697fe2e2 1598 unsigned i;
697fe2e2 1599
38e3b2b2
XG		 1600 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1601 mmu_page_zap_pte(kvm, sp, sp->spt + i);
a436036b
AK		 1602}
1603
4db35314 1604static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 1605{
4db35314 1606 mmu_page_remove_parent_pte(sp, parent_pte);
a436036b
AK		 1607}
1608
12b7d28f
AK		 1609static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1610{
1611 int i;
988a2cae 1612 struct kvm_vcpu *vcpu;
12b7d28f 1613
988a2cae
GN		 1614 kvm_for_each_vcpu(i, vcpu, kvm)
1615 vcpu->arch.last_pte_updated = NULL;
12b7d28f
AK		 1616}
1617
31aa2b44 1618static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
a436036b
AK		 1619{
1620 u64 *parent_pte;
1621
bcdd9a93
XG		 1622 while ((parent_pte = pte_list_next(&sp->parent_ptes, NULL)))
1623 drop_parent_pte(sp, parent_pte);
31aa2b44
AK		 1624}
1625
60c8aec6 1626static int mmu_zap_unsync_children(struct kvm *kvm,
7775834a
XG		 1627 struct kvm_mmu_page *parent,
1628 struct list_head *invalid_list)
4731d4c7 1629{
60c8aec6
MT		 1630 int i, zapped = 0;
1631 struct mmu_page_path parents;
1632 struct kvm_mmu_pages pages;
4731d4c7 1633
60c8aec6 1634 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
4731d4c7 1635 return 0;
60c8aec6
MT		 1636
1637 kvm_mmu_pages_init(parent, &parents, &pages);
1638 while (mmu_unsync_walk(parent, &pages)) {
1639 struct kvm_mmu_page *sp;
1640
1641 for_each_sp(pages, sp, parents, i) {
7775834a 1642 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
60c8aec6 1643 mmu_pages_clear_parents(&parents);
77662e00 1644 zapped++;
60c8aec6 1645 }
60c8aec6
MT		 1646 kvm_mmu_pages_init(parent, &parents, &pages);
1647 }
1648
1649 return zapped;
4731d4c7
MT		 1650}
1651
7775834a
XG		 1652static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1653 struct list_head *invalid_list)
31aa2b44 1654{
4731d4c7 1655 int ret;
f691fe1d 1656
7775834a 1657 trace_kvm_mmu_prepare_zap_page(sp);
31aa2b44 1658 ++kvm->stat.mmu_shadow_zapped;
7775834a 1659 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
4db35314 1660 kvm_mmu_page_unlink_children(kvm, sp);
31aa2b44 1661 kvm_mmu_unlink_parents(kvm, sp);
f6e2c02b 1662 if (!sp->role.invalid && !sp->role.direct)
5b5c6a5a 1663 unaccount_shadowed(kvm, sp->gfn);
4731d4c7
MT		 1664 if (sp->unsync)
1665 kvm_unlink_unsync_page(kvm, sp);
4db35314 1666 if (!sp->root_count) {
54a4f023
GJ		 1667 /* Count self */
1668 ret++;
7775834a 1669 list_move(&sp->link, invalid_list);
2e53d63a 1670 } else {
5b5c6a5a 1671 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2e53d63a
MT		 1672 kvm_reload_remote_mmus(kvm);
1673 }
7775834a
XG		 1674
1675 sp->role.invalid = 1;
12b7d28f 1676 kvm_mmu_reset_last_pte_updated(kvm);
4731d4c7 1677 return ret;
a436036b
AK		 1678}
1679
7775834a
XG		 1680static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1681 struct list_head *invalid_list)
1682{
1683 struct kvm_mmu_page *sp;
1684
1685 if (list_empty(invalid_list))
1686 return;
1687
1688 kvm_flush_remote_tlbs(kvm);
1689
1690 do {
1691 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1692 WARN_ON(!sp->role.invalid || sp->root_count);
1693 kvm_mmu_free_page(kvm, sp);
1694 } while (!list_empty(invalid_list));
1695
1696}
1697
82ce2c96
IE		 1698/*
1699 * Changing the number of mmu pages allocated to the vm
49d5ca26 1700 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
82ce2c96 1701 */
49d5ca26 1702void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
82ce2c96 1703{
d98ba053 1704 LIST_HEAD(invalid_list);
82ce2c96
IE		 1705 /*
1706 * If we set the number of mmu pages to be smaller be than the
1707 * number of actived pages , we must to free some mmu pages before we
1708 * change the value
1709 */
1710
49d5ca26
DH		 1711 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
1712 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
77662e00 1713 !list_empty(&kvm->arch.active_mmu_pages)) {
82ce2c96
IE		 1714 struct kvm_mmu_page *page;
1715
f05e70ac 1716 page = container_of(kvm->arch.active_mmu_pages.prev,
82ce2c96 1717 struct kvm_mmu_page, link);
80b63faf
XF		 1718 kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
1719 kvm_mmu_commit_zap_page(kvm, &invalid_list);
82ce2c96 1720 }
49d5ca26 1721 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
82ce2c96 1722 }
82ce2c96 1723
49d5ca26 1724 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
82ce2c96
IE		 1725}
1726
f67a46f4 1727static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
a436036b 1728{
4db35314 1729 struct kvm_mmu_page *sp;
f41d335a 1730 struct hlist_node *node;
d98ba053 1731 LIST_HEAD(invalid_list);
a436036b
AK		 1732 int r;
1733
9ad17b10 1734 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
a436036b 1735 r = 0;
f41d335a
XG		 1736
1737 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
9ad17b10 1738 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
7ae680eb
XG		 1739 sp->role.word);
1740 r = 1;
f41d335a 1741 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
7ae680eb 1742 }
d98ba053 1743 kvm_mmu_commit_zap_page(kvm, &invalid_list);
a436036b 1744 return r;
cea0f0e7
AK		 1745}
1746
f67a46f4 1747static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
97a0a01e 1748{
4db35314 1749 struct kvm_mmu_page *sp;
f41d335a 1750 struct hlist_node *node;
d98ba053 1751 LIST_HEAD(invalid_list);
97a0a01e 1752
f41d335a 1753 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
9ad17b10 1754 pgprintk("%s: zap %llx %x\n",
7ae680eb 1755 __func__, gfn, sp->role.word);
f41d335a 1756 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
97a0a01e 1757 }
d98ba053 1758 kvm_mmu_commit_zap_page(kvm, &invalid_list);
97a0a01e
AK		 1759}
1760
38c335f1 1761static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
6aa8b732 1762{
bc6678a3 1763 int slot = memslot_id(kvm, gfn);
4db35314 1764 struct kvm_mmu_page *sp = page_header(__pa(pte));
6aa8b732 1765
291f26bc 1766 __set_bit(slot, sp->slot_bitmap);
6aa8b732
AK		 1767}
1768
6844dec6
MT		 1769static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1770{
1771 int i;
1772 u64 *pt = sp->spt;
1773
1774 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1775 return;
1776
1777 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1778 if (pt[i] == shadow_notrap_nonpresent_pte)
d555c333 1779 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
6844dec6
MT		 1780 }
1781}
1782
74be52e3
SY		 1783/*
1784 * The function is based on mtrr_type_lookup() in
1785 * arch/x86/kernel/cpu/mtrr/generic.c
1786 */
1787static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1788 u64 start, u64 end)
1789{
1790 int i;
1791 u64 base, mask;
1792 u8 prev_match, curr_match;
1793 int num_var_ranges = KVM_NR_VAR_MTRR;
1794
1795 if (!mtrr_state->enabled)
1796 return 0xFF;
1797
1798 /* Make end inclusive end, instead of exclusive */
1799 end--;
1800
1801 /* Look in fixed ranges. Just return the type as per start */
1802 if (mtrr_state->have_fixed && (start < 0x100000)) {
1803 int idx;
1804
1805 if (start < 0x80000) {
1806 idx = 0;
1807 idx += (start >> 16);
1808 return mtrr_state->fixed_ranges[idx];
1809 } else if (start < 0xC0000) {
1810 idx = 1 * 8;
1811 idx += ((start - 0x80000) >> 14);
1812 return mtrr_state->fixed_ranges[idx];
1813 } else if (start < 0x1000000) {
1814 idx = 3 * 8;
1815 idx += ((start - 0xC0000) >> 12);
1816 return mtrr_state->fixed_ranges[idx];
1817 }
1818 }
1819
1820 /*
1821 * Look in variable ranges
1822 * Look of multiple ranges matching this address and pick type
1823 * as per MTRR precedence
1824 */
1825 if (!(mtrr_state->enabled & 2))
1826 return mtrr_state->def_type;
1827
1828 prev_match = 0xFF;
1829 for (i = 0; i < num_var_ranges; ++i) {
1830 unsigned short start_state, end_state;
1831
1832 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1833 continue;
1834
1835 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1836 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1837 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1838 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1839
1840 start_state = ((start & mask) == (base & mask));
1841 end_state = ((end & mask) == (base & mask));
1842 if (start_state != end_state)
1843 return 0xFE;
1844
1845 if ((start & mask) != (base & mask))
1846 continue;
1847
1848 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1849 if (prev_match == 0xFF) {
1850 prev_match = curr_match;
1851 continue;
1852 }
1853
1854 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1855 curr_match == MTRR_TYPE_UNCACHABLE)
1856 return MTRR_TYPE_UNCACHABLE;
1857
1858 if ((prev_match == MTRR_TYPE_WRBACK &&
1859 curr_match == MTRR_TYPE_WRTHROUGH) ||
1860 (prev_match == MTRR_TYPE_WRTHROUGH &&
1861 curr_match == MTRR_TYPE_WRBACK)) {
1862 prev_match = MTRR_TYPE_WRTHROUGH;
1863 curr_match = MTRR_TYPE_WRTHROUGH;
1864 }
1865
1866 if (prev_match != curr_match)
1867 return MTRR_TYPE_UNCACHABLE;
1868 }
1869
1870 if (prev_match != 0xFF)
1871 return prev_match;
1872
1873 return mtrr_state->def_type;
1874}
1875
4b12f0de 1876u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
74be52e3
SY		 1877{
1878 u8 mtrr;
1879
1880 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1881 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1882 if (mtrr == 0xfe || mtrr == 0xff)
1883 mtrr = MTRR_TYPE_WRBACK;
1884 return mtrr;
1885}
4b12f0de 1886EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
74be52e3 1887
9cf5cf5a
XG		 1888static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1889{
1890 trace_kvm_mmu_unsync_page(sp);
1891 ++vcpu->kvm->stat.mmu_unsync;
1892 sp->unsync = 1;
1893
1894 kvm_mmu_mark_parents_unsync(sp);
1895 mmu_convert_notrap(sp);
1896}
1897
1898static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
4731d4c7 1899{
4731d4c7 1900 struct kvm_mmu_page *s;
f41d335a 1901 struct hlist_node *node;
9cf5cf5a 1902
f41d335a 1903 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
7ae680eb 1904 if (s->unsync)
4731d4c7 1905 continue;
9cf5cf5a
XG		 1906 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1907 __kvm_unsync_page(vcpu, s);
4731d4c7 1908 }
4731d4c7
MT		 1909}
1910
1911static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1912 bool can_unsync)
1913{
9cf5cf5a 1914 struct kvm_mmu_page *s;
f41d335a 1915 struct hlist_node *node;
9cf5cf5a
XG		 1916 bool need_unsync = false;
1917
f41d335a 1918 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
36a2e677
XG		 1919 if (!can_unsync)
1920 return 1;
1921
9cf5cf5a 1922 if (s->role.level != PT_PAGE_TABLE_LEVEL)
4731d4c7 1923 return 1;
9cf5cf5a
XG		 1924
1925 if (!need_unsync && !s->unsync) {
36a2e677 1926 if (!oos_shadow)
9cf5cf5a
XG		 1927 return 1;
1928 need_unsync = true;
1929 }
4731d4c7 1930 }
9cf5cf5a
XG		 1931 if (need_unsync)
1932 kvm_unsync_pages(vcpu, gfn);
4731d4c7
MT		 1933 return 0;
1934}
1935
d555c333 1936static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd 1937 unsigned pte_access, int user_fault,
852e3c19 1938 int write_fault, int dirty, int level,
c2d0ee46 1939 gfn_t gfn, pfn_t pfn, bool speculative,
9bdbba13 1940 bool can_unsync, bool host_writable)
1c4f1fd6 1941{
b330aa0c 1942 u64 spte, entry = *sptep;
1e73f9dd 1943 int ret = 0;
64d4d521 1944
1c4f1fd6
AK		 1945 /*
1946 * We don't set the accessed bit, since we sometimes want to see
1947 * whether the guest actually used the pte (in order to detect
1948 * demand paging).
1949 */
982c2565 1950 spte = PT_PRESENT_MASK;
947da538 1951 if (!speculative)
3201b5d9 1952 spte |= shadow_accessed_mask;
1c4f1fd6
AK		 1953 if (!dirty)
1954 pte_access &= ~ACC_WRITE_MASK;
7b52345e
SY		 1955 if (pte_access & ACC_EXEC_MASK)
1956 spte |= shadow_x_mask;
1957 else
1958 spte |= shadow_nx_mask;
1c4f1fd6 1959 if (pte_access & ACC_USER_MASK)
7b52345e 1960 spte |= shadow_user_mask;
852e3c19 1961 if (level > PT_PAGE_TABLE_LEVEL)
05da4558 1962 spte |= PT_PAGE_SIZE_MASK;
b0bc3ee2 1963 if (tdp_enabled)
4b12f0de
SY		 1964 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1965 kvm_is_mmio_pfn(pfn));
1c4f1fd6 1966
9bdbba13 1967 if (host_writable)
1403283a 1968 spte |= SPTE_HOST_WRITEABLE;
f8e453b0
XG		 1969 else
1970 pte_access &= ~ACC_WRITE_MASK;
1403283a 1971
35149e21 1972 spte |= (u64)pfn << PAGE_SHIFT;
1c4f1fd6
AK		 1973
1974 if ((pte_access & ACC_WRITE_MASK)
c5a78f2b
JR		 1975 || (!vcpu->arch.mmu.direct_map && write_fault
1976 && !is_write_protection(vcpu) && !user_fault)) {
1c4f1fd6 1977
852e3c19
JR		 1978 if (level > PT_PAGE_TABLE_LEVEL &&
1979 has_wrprotected_page(vcpu->kvm, gfn, level)) {
38187c83 1980 ret = 1;
be38d276
AK		 1981 drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte);
1982 goto done;
38187c83
MT		 1983 }
1984
1c4f1fd6 1985 spte |= PT_WRITABLE_MASK;
1c4f1fd6 1986
c5a78f2b
JR		 1987 if (!vcpu->arch.mmu.direct_map
1988 && !(pte_access & ACC_WRITE_MASK))
69325a12
AK		 1989 spte &= ~PT_USER_MASK;
1990
ecc5589f
MT		 1991 /*
1992 * Optimization: for pte sync, if spte was writable the hash
1993 * lookup is unnecessary (and expensive). Write protection
1994 * is responsibility of mmu_get_page / kvm_sync_page.
1995 * Same reasoning can be applied to dirty page accounting.
1996 */
8dae4445 1997 if (!can_unsync && is_writable_pte(*sptep))
ecc5589f
MT		 1998 goto set_pte;
1999
4731d4c7 2000 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
9ad17b10 2001 pgprintk("%s: found shadow page for %llx, marking ro\n",
b8688d51 2002 __func__, gfn);
1e73f9dd 2003 ret = 1;
1c4f1fd6 2004 pte_access &= ~ACC_WRITE_MASK;
8dae4445 2005 if (is_writable_pte(spte))
1c4f1fd6 2006 spte &= ~PT_WRITABLE_MASK;
1c4f1fd6
AK		 2007 }
2008 }
2009
1c4f1fd6
AK		 2010 if (pte_access & ACC_WRITE_MASK)
2011 mark_page_dirty(vcpu->kvm, gfn);
2012
38187c83 2013set_pte:
b79b93f9 2014 update_spte(sptep, spte);
b330aa0c
XG		 2015 /*
2016 * If we overwrite a writable spte with a read-only one we
2017 * should flush remote TLBs. Otherwise rmap_write_protect
2018 * will find a read-only spte, even though the writable spte
2019 * might be cached on a CPU's TLB.
2020 */
2021 if (is_writable_pte(entry) && !is_writable_pte(*sptep))
2022 kvm_flush_remote_tlbs(vcpu->kvm);
be38d276 2023done:
1e73f9dd
MT		 2024 return ret;
2025}
2026
d555c333 2027static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd
MT		 2028 unsigned pt_access, unsigned pte_access,
2029 int user_fault, int write_fault, int dirty,
852e3c19 2030 int *ptwrite, int level, gfn_t gfn,
1403283a 2031 pfn_t pfn, bool speculative,
9bdbba13 2032 bool host_writable)
1e73f9dd
MT		 2033{
2034 int was_rmapped = 0;
53a27b39 2035 int rmap_count;
1e73f9dd
MT		 2036
2037 pgprintk("%s: spte %llx access %x write_fault %d"
9ad17b10 2038 " user_fault %d gfn %llx\n",
d555c333 2039 __func__, *sptep, pt_access,
1e73f9dd
MT		 2040 write_fault, user_fault, gfn);
2041
d555c333 2042 if (is_rmap_spte(*sptep)) {
1e73f9dd
MT		 2043 /*
2044 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2045 * the parent of the now unreachable PTE.
2046 */
852e3c19
JR		 2047 if (level > PT_PAGE_TABLE_LEVEL &&
2048 !is_large_pte(*sptep)) {
1e73f9dd 2049 struct kvm_mmu_page *child;
d555c333 2050 u64 pte = *sptep;
1e73f9dd
MT		 2051
2052 child = page_header(pte & PT64_BASE_ADDR_MASK);
bcdd9a93 2053 drop_parent_pte(child, sptep);
3be2264b 2054 kvm_flush_remote_tlbs(vcpu->kvm);
d555c333 2055 } else if (pfn != spte_to_pfn(*sptep)) {
9ad17b10 2056 pgprintk("hfn old %llx new %llx\n",
d555c333 2057 spte_to_pfn(*sptep), pfn);
be38d276 2058 drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte);
91546356 2059 kvm_flush_remote_tlbs(vcpu->kvm);
6bed6b9e
JR		 2060 } else
2061 was_rmapped = 1;
1e73f9dd 2062 }
852e3c19 2063
d555c333 2064 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
1403283a 2065 dirty, level, gfn, pfn, speculative, true,
9bdbba13 2066 host_writable)) {
1e73f9dd
MT		 2067 if (write_fault)
2068 *ptwrite = 1;
5304efde 2069 kvm_mmu_flush_tlb(vcpu);
a378b4e6 2070 }
1e73f9dd 2071
d555c333 2072 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
9ad17b10 2073 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
d555c333 2074 is_large_pte(*sptep)? "2MB" : "4kB",
a205bc19
JR		 2075 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2076 *sptep, sptep);
d555c333 2077 if (!was_rmapped && is_large_pte(*sptep))
05da4558
MT		 2078 ++vcpu->kvm->stat.lpages;
2079
d555c333 2080 page_header_update_slot(vcpu->kvm, sptep, gfn);
1c4f1fd6 2081 if (!was_rmapped) {
44ad9944 2082 rmap_count = rmap_add(vcpu, sptep, gfn);
53a27b39 2083 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
852e3c19 2084 rmap_recycle(vcpu, sptep, gfn);
1c4f1fd6 2085 }
9ed5520d 2086 kvm_release_pfn_clean(pfn);
1b7fcd32 2087 if (speculative) {
d555c333 2088 vcpu->arch.last_pte_updated = sptep;
1b7fcd32
AK		 2089 vcpu->arch.last_pte_gfn = gfn;
2090 }
1c4f1fd6
AK		 2091}
2092
6aa8b732
AK		 2093static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2094{
2095}
2096
957ed9ef
XG		 2097static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2098 bool no_dirty_log)
2099{
2100 struct kvm_memory_slot *slot;
2101 unsigned long hva;
2102
5d163b1c 2103 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
957ed9ef
XG		 2104 if (!slot) {
2105 get_page(bad_page);
2106 return page_to_pfn(bad_page);
2107 }
2108
2109 hva = gfn_to_hva_memslot(slot, gfn);
2110
2111 return hva_to_pfn_atomic(vcpu->kvm, hva);
2112}
2113
2114static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2115 struct kvm_mmu_page *sp,
2116 u64 *start, u64 *end)
2117{
2118 struct page *pages[PTE_PREFETCH_NUM];
2119 unsigned access = sp->role.access;
2120 int i, ret;
2121 gfn_t gfn;
2122
2123 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
5d163b1c 2124 if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
957ed9ef
XG		 2125 return -1;
2126
2127 ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2128 if (ret <= 0)
2129 return -1;
2130
2131 for (i = 0; i < ret; i++, gfn++, start++)
2132 mmu_set_spte(vcpu, start, ACC_ALL,
2133 access, 0, 0, 1, NULL,
2134 sp->role.level, gfn,
2135 page_to_pfn(pages[i]), true, true);
2136
2137 return 0;
2138}
2139
2140static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2141 struct kvm_mmu_page *sp, u64 *sptep)
2142{
2143 u64 *spte, *start = NULL;
2144 int i;
2145
2146 WARN_ON(!sp->role.direct);
2147
2148 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2149 spte = sp->spt + i;
2150
2151 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2152 if (*spte != shadow_trap_nonpresent_pte || spte == sptep) {
2153 if (!start)
2154 continue;
2155 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2156 break;
2157 start = NULL;
2158 } else if (!start)
2159 start = spte;
2160 }
2161}
2162
2163static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2164{
2165 struct kvm_mmu_page *sp;
2166
2167 /*
2168 * Since it's no accessed bit on EPT, it's no way to
2169 * distinguish between actually accessed translations
2170 * and prefetched, so disable pte prefetch if EPT is
2171 * enabled.
2172 */
2173 if (!shadow_accessed_mask)
2174 return;
2175
2176 sp = page_header(__pa(sptep));
2177 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2178 return;
2179
2180 __direct_pte_prefetch(vcpu, sp, sptep);
2181}
2182
9f652d21 2183static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2ec4739d
XG		 2184 int map_writable, int level, gfn_t gfn, pfn_t pfn,
2185 bool prefault)
140754bc 2186{
9f652d21 2187 struct kvm_shadow_walk_iterator iterator;
140754bc 2188 struct kvm_mmu_page *sp;
9f652d21 2189 int pt_write = 0;
140754bc 2190 gfn_t pseudo_gfn;
6aa8b732 2191
9f652d21 2192 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
852e3c19 2193 if (iterator.level == level) {
612819c3
MT		 2194 unsigned pte_access = ACC_ALL;
2195
612819c3 2196 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access,
9f652d21 2197 0, write, 1, &pt_write,
2ec4739d 2198 level, gfn, pfn, prefault, map_writable);
957ed9ef 2199 direct_pte_prefetch(vcpu, iterator.sptep);
9f652d21
AK		 2200 ++vcpu->stat.pf_fixed;
2201 break;
6aa8b732
AK		 2202 }
2203
9f652d21 2204 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
c9fa0b3b
LJ		 2205 u64 base_addr = iterator.addr;
2206
2207 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2208 pseudo_gfn = base_addr >> PAGE_SHIFT;
9f652d21
AK		 2209 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2210 iterator.level - 1,
2211 1, ACC_ALL, iterator.sptep);
2212 if (!sp) {
2213 pgprintk("nonpaging_map: ENOMEM\n");
2214 kvm_release_pfn_clean(pfn);
2215 return -ENOMEM;
2216 }
140754bc 2217
d555c333
AK		 2218 __set_spte(iterator.sptep,
2219 __pa(sp->spt)
2220 | PT_PRESENT_MASK | PT_WRITABLE_MASK
33f91edb
XG		 2221 | shadow_user_mask | shadow_x_mask
2222 | shadow_accessed_mask);
9f652d21
AK		 2223 }
2224 }
2225 return pt_write;
6aa8b732
AK		 2226}
2227
77db5cbd 2228static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
bf998156 2229{
77db5cbd
HY		 2230 siginfo_t info;
2231
2232 info.si_signo = SIGBUS;
2233 info.si_errno = 0;
2234 info.si_code = BUS_MCEERR_AR;
2235 info.si_addr = (void __user *)address;
2236 info.si_addr_lsb = PAGE_SHIFT;
bf998156 2237
77db5cbd 2238 send_sig_info(SIGBUS, &info, tsk);
bf998156
HY		 2239}
2240
2241static int kvm_handle_bad_page(struct kvm *kvm, gfn_t gfn, pfn_t pfn)
2242{
2243 kvm_release_pfn_clean(pfn);
2244 if (is_hwpoison_pfn(pfn)) {
77db5cbd 2245 kvm_send_hwpoison_signal(gfn_to_hva(kvm, gfn), current);
bf998156 2246 return 0;
edba23e5
GN		 2247 } else if (is_fault_pfn(pfn))
2248 return -EFAULT;
2249
bf998156
HY		 2250 return 1;
2251}
2252
936a5fe6
AA		 2253static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2254 gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2255{
2256 pfn_t pfn = *pfnp;
2257 gfn_t gfn = *gfnp;
2258 int level = *levelp;
2259
2260 /*
2261 * Check if it's a transparent hugepage. If this would be an
2262 * hugetlbfs page, level wouldn't be set to
2263 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2264 * here.
2265 */
2266 if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2267 level == PT_PAGE_TABLE_LEVEL &&
2268 PageTransCompound(pfn_to_page(pfn)) &&
2269 !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2270 unsigned long mask;
2271 /*
2272 * mmu_notifier_retry was successful and we hold the
2273 * mmu_lock here, so the pmd can't become splitting
2274 * from under us, and in turn
2275 * __split_huge_page_refcount() can't run from under
2276 * us and we can safely transfer the refcount from
2277 * PG_tail to PG_head as we switch the pfn to tail to
2278 * head.
2279 */
2280 *levelp = level = PT_DIRECTORY_LEVEL;
2281 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2282 VM_BUG_ON((gfn & mask) != (pfn & mask));
2283 if (pfn & mask) {
2284 gfn &= ~mask;
2285 *gfnp = gfn;
2286 kvm_release_pfn_clean(pfn);
2287 pfn &= ~mask;
2288 if (!get_page_unless_zero(pfn_to_page(pfn)))
2289 BUG();
2290 *pfnp = pfn;
2291 }
2292 }
2293}
2294
78b2c54a 2295static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
060c2abe
XG		 2296 gva_t gva, pfn_t *pfn, bool write, bool *writable);
2297
2298static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn,
78b2c54a 2299 bool prefault)
10589a46
MT		 2300{
2301 int r;
852e3c19 2302 int level;
936a5fe6 2303 int force_pt_level;
35149e21 2304 pfn_t pfn;
e930bffe 2305 unsigned long mmu_seq;
612819c3 2306 bool map_writable;
aaee2c94 2307
936a5fe6
AA		 2308 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2309 if (likely(!force_pt_level)) {
2310 level = mapping_level(vcpu, gfn);
2311 /*
2312 * This path builds a PAE pagetable - so we can map
2313 * 2mb pages at maximum. Therefore check if the level
2314 * is larger than that.
2315 */
2316 if (level > PT_DIRECTORY_LEVEL)
2317 level = PT_DIRECTORY_LEVEL;
852e3c19 2318
936a5fe6
AA		 2319 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2320 } else
2321 level = PT_PAGE_TABLE_LEVEL;
05da4558 2322
e930bffe 2323 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2324 smp_rmb();
060c2abe 2325
78b2c54a 2326 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
060c2abe 2327 return 0;
aaee2c94 2328
d196e343 2329 /* mmio */
bf998156
HY		 2330 if (is_error_pfn(pfn))
2331 return kvm_handle_bad_page(vcpu->kvm, gfn, pfn);
d196e343 2332
aaee2c94 2333 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2334 if (mmu_notifier_retry(vcpu, mmu_seq))
2335 goto out_unlock;
eb787d10 2336 kvm_mmu_free_some_pages(vcpu);
936a5fe6
AA		 2337 if (likely(!force_pt_level))
2338 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2ec4739d
XG		 2339 r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2340 prefault);
aaee2c94
MT		 2341 spin_unlock(&vcpu->kvm->mmu_lock);
2342
aaee2c94 2343
10589a46 2344 return r;
e930bffe
AA		 2345
2346out_unlock:
2347 spin_unlock(&vcpu->kvm->mmu_lock);
2348 kvm_release_pfn_clean(pfn);
2349 return 0;
10589a46
MT		 2350}
2351
2352
17ac10ad
AK		 2353static void mmu_free_roots(struct kvm_vcpu *vcpu)
2354{
2355 int i;
4db35314 2356 struct kvm_mmu_page *sp;
d98ba053 2357 LIST_HEAD(invalid_list);
17ac10ad 2358
ad312c7c 2359 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
7b53aa56 2360 return;
aaee2c94 2361 spin_lock(&vcpu->kvm->mmu_lock);
81407ca5
JR		 2362 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2363 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2364 vcpu->arch.mmu.direct_map)) {
ad312c7c 2365 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad 2366
4db35314
AK		 2367 sp = page_header(root);
2368 --sp->root_count;
d98ba053
XG		 2369 if (!sp->root_count && sp->role.invalid) {
2370 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2371 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2372 }
ad312c7c 2373 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
aaee2c94 2374 spin_unlock(&vcpu->kvm->mmu_lock);
17ac10ad
AK		 2375 return;
2376 }
17ac10ad 2377 for (i = 0; i < 4; ++i) {
ad312c7c 2378 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad 2379
417726a3 2380 if (root) {
417726a3 2381 root &= PT64_BASE_ADDR_MASK;
4db35314
AK		 2382 sp = page_header(root);
2383 --sp->root_count;
2e53d63a 2384 if (!sp->root_count && sp->role.invalid)
d98ba053
XG		 2385 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2386 &invalid_list);
417726a3 2387 }
ad312c7c 2388 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2389 }
d98ba053 2390 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
aaee2c94 2391 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2392 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
17ac10ad
AK		 2393}
2394
8986ecc0
MT		 2395static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2396{
2397 int ret = 0;
2398
2399 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
a8eeb04a 2400 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
8986ecc0
MT		 2401 ret = 1;
2402 }
2403
2404 return ret;
2405}
2406
651dd37a
JR		 2407static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2408{
2409 struct kvm_mmu_page *sp;
7ebaf15e 2410 unsigned i;
651dd37a
JR		 2411
2412 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2413 spin_lock(&vcpu->kvm->mmu_lock);
2414 kvm_mmu_free_some_pages(vcpu);
2415 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2416 1, ACC_ALL, NULL);
2417 ++sp->root_count;
2418 spin_unlock(&vcpu->kvm->mmu_lock);
2419 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2420 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2421 for (i = 0; i < 4; ++i) {
2422 hpa_t root = vcpu->arch.mmu.pae_root[i];
2423
2424 ASSERT(!VALID_PAGE(root));
2425 spin_lock(&vcpu->kvm->mmu_lock);
2426 kvm_mmu_free_some_pages(vcpu);
649497d1
AK		 2427 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
2428 i << 30,
651dd37a
JR		 2429 PT32_ROOT_LEVEL, 1, ACC_ALL,
2430 NULL);
2431 root = __pa(sp->spt);
2432 ++sp->root_count;
2433 spin_unlock(&vcpu->kvm->mmu_lock);
2434 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
651dd37a 2435 }
6292757f 2436 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
651dd37a
JR		 2437 } else
2438 BUG();
2439
2440 return 0;
2441}
2442
2443static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
17ac10ad 2444{
4db35314 2445 struct kvm_mmu_page *sp;
81407ca5
JR		 2446 u64 pdptr, pm_mask;
2447 gfn_t root_gfn;
2448 int i;
3bb65a22 2449
5777ed34 2450 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
17ac10ad 2451
651dd37a
JR		 2452 if (mmu_check_root(vcpu, root_gfn))
2453 return 1;
2454
2455 /*
2456 * Do we shadow a long mode page table? If so we need to
2457 * write-protect the guests page table root.
2458 */
2459 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
ad312c7c 2460 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad
AK		 2461
2462 ASSERT(!VALID_PAGE(root));
651dd37a 2463
8facbbff 2464 spin_lock(&vcpu->kvm->mmu_lock);
24955b6c 2465 kvm_mmu_free_some_pages(vcpu);
651dd37a
JR		 2466 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
2467 0, ACC_ALL, NULL);
4db35314
AK		 2468 root = __pa(sp->spt);
2469 ++sp->root_count;
8facbbff 2470 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2471 vcpu->arch.mmu.root_hpa = root;
8986ecc0 2472 return 0;
17ac10ad 2473 }
f87f9288 2474
651dd37a
JR		 2475 /*
2476 * We shadow a 32 bit page table. This may be a legacy 2-level
81407ca5
JR		 2477 * or a PAE 3-level page table. In either case we need to be aware that
2478 * the shadow page table may be a PAE or a long mode page table.
651dd37a 2479 */
81407ca5
JR		 2480 pm_mask = PT_PRESENT_MASK;
2481 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
2482 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
2483
17ac10ad 2484 for (i = 0; i < 4; ++i) {
ad312c7c 2485 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad
AK		 2486
2487 ASSERT(!VALID_PAGE(root));
ad312c7c 2488 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
d41d1895 2489 pdptr = kvm_pdptr_read_mmu(vcpu, &vcpu->arch.mmu, i);
43a3795a 2490 if (!is_present_gpte(pdptr)) {
ad312c7c 2491 vcpu->arch.mmu.pae_root[i] = 0;
417726a3
AK		 2492 continue;
2493 }
6de4f3ad 2494 root_gfn = pdptr >> PAGE_SHIFT;
f87f9288
JR		 2495 if (mmu_check_root(vcpu, root_gfn))
2496 return 1;
5a7388c2 2497 }
8facbbff 2498 spin_lock(&vcpu->kvm->mmu_lock);
24955b6c 2499 kvm_mmu_free_some_pages(vcpu);
4db35314 2500 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
651dd37a 2501 PT32_ROOT_LEVEL, 0,
f7d9c7b7 2502 ACC_ALL, NULL);
4db35314
AK		 2503 root = __pa(sp->spt);
2504 ++sp->root_count;
8facbbff
AK		 2505 spin_unlock(&vcpu->kvm->mmu_lock);
2506
81407ca5 2507 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
17ac10ad 2508 }
6292757f 2509 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
81407ca5
JR		 2510
2511 /*
2512 * If we shadow a 32 bit page table with a long mode page
2513 * table we enter this path.
2514 */
2515 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2516 if (vcpu->arch.mmu.lm_root == NULL) {
2517 /*
2518 * The additional page necessary for this is only
2519 * allocated on demand.
2520 */
2521
2522 u64 *lm_root;
2523
2524 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
2525 if (lm_root == NULL)
2526 return 1;
2527
2528 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
2529
2530 vcpu->arch.mmu.lm_root = lm_root;
2531 }
2532
2533 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
2534 }
2535
8986ecc0 2536 return 0;
17ac10ad
AK		 2537}
2538
651dd37a
JR		 2539static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
2540{
2541 if (vcpu->arch.mmu.direct_map)
2542 return mmu_alloc_direct_roots(vcpu);
2543 else
2544 return mmu_alloc_shadow_roots(vcpu);
2545}
2546
0ba73cda
MT		 2547static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2548{
2549 int i;
2550 struct kvm_mmu_page *sp;
2551
81407ca5
JR		 2552 if (vcpu->arch.mmu.direct_map)
2553 return;
2554
0ba73cda
MT		 2555 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2556 return;
6903074c
XG		 2557
2558 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
81407ca5 2559 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
0ba73cda
MT		 2560 hpa_t root = vcpu->arch.mmu.root_hpa;
2561 sp = page_header(root);
2562 mmu_sync_children(vcpu, sp);
5054c0de 2563 trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
0ba73cda
MT		 2564 return;
2565 }
2566 for (i = 0; i < 4; ++i) {
2567 hpa_t root = vcpu->arch.mmu.pae_root[i];
2568
8986ecc0 2569 if (root && VALID_PAGE(root)) {
0ba73cda
MT		 2570 root &= PT64_BASE_ADDR_MASK;
2571 sp = page_header(root);
2572 mmu_sync_children(vcpu, sp);
2573 }
2574 }
6903074c 2575 trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
0ba73cda
MT		 2576}
2577
2578void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2579{
2580 spin_lock(&vcpu->kvm->mmu_lock);
2581 mmu_sync_roots(vcpu);
6cffe8ca 2582 spin_unlock(&vcpu->kvm->mmu_lock);
0ba73cda
MT		 2583}
2584
1871c602 2585static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
ab9ae313 2586 u32 access, struct x86_exception *exception)
6aa8b732 2587{
ab9ae313
AK		 2588 if (exception)
2589 exception->error_code = 0;
6aa8b732
AK		 2590 return vaddr;
2591}
2592
6539e738 2593static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
ab9ae313
AK		 2594 u32 access,
2595 struct x86_exception *exception)
6539e738 2596{
ab9ae313
AK		 2597 if (exception)
2598 exception->error_code = 0;
6539e738
JR		 2599 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
2600}
2601
6aa8b732 2602static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
78b2c54a 2603 u32 error_code, bool prefault)
6aa8b732 2604{
e833240f 2605 gfn_t gfn;
e2dec939 2606 int r;
6aa8b732 2607
b8688d51 2608 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
e2dec939
AK		 2609 r = mmu_topup_memory_caches(vcpu);
2610 if (r)
2611 return r;
714b93da 2612
6aa8b732 2613 ASSERT(vcpu);
ad312c7c 2614 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2615
e833240f 2616 gfn = gva >> PAGE_SHIFT;
6aa8b732 2617
e833240f 2618 return nonpaging_map(vcpu, gva & PAGE_MASK,
78b2c54a 2619 error_code & PFERR_WRITE_MASK, gfn, prefault);
6aa8b732
AK		 2620}
2621
7e1fbeac 2622static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
af585b92
GN		 2623{
2624 struct kvm_arch_async_pf arch;
fb67e14f 2625
7c90705b 2626 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
af585b92 2627 arch.gfn = gfn;
c4806acd 2628 arch.direct_map = vcpu->arch.mmu.direct_map;
fb67e14f 2629 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
af585b92
GN		 2630
2631 return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
2632}
2633
2634static bool can_do_async_pf(struct kvm_vcpu *vcpu)
2635{
2636 if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
2637 kvm_event_needs_reinjection(vcpu)))
2638 return false;
2639
2640 return kvm_x86_ops->interrupt_allowed(vcpu);
2641}
2642
78b2c54a 2643static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
612819c3 2644 gva_t gva, pfn_t *pfn, bool write, bool *writable)
af585b92
GN		 2645{
2646 bool async;
2647
612819c3 2648 *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
af585b92
GN		 2649
2650 if (!async)
2651 return false; /* *pfn has correct page already */
2652
2653 put_page(pfn_to_page(*pfn));
2654
78b2c54a 2655 if (!prefault && can_do_async_pf(vcpu)) {
c9b263d2 2656 trace_kvm_try_async_get_page(gva, gfn);
af585b92
GN		 2657 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
2658 trace_kvm_async_pf_doublefault(gva, gfn);
2659 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
2660 return true;
2661 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
2662 return true;
2663 }
2664
612819c3 2665 *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
af585b92
GN		 2666
2667 return false;
2668}
2669
56028d08 2670static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
78b2c54a 2671 bool prefault)
fb72d167 2672{
35149e21 2673 pfn_t pfn;
fb72d167 2674 int r;
852e3c19 2675 int level;
936a5fe6 2676 int force_pt_level;
05da4558 2677 gfn_t gfn = gpa >> PAGE_SHIFT;
e930bffe 2678 unsigned long mmu_seq;
612819c3
MT		 2679 int write = error_code & PFERR_WRITE_MASK;
2680 bool map_writable;
fb72d167
JR		 2681
2682 ASSERT(vcpu);
2683 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2684
2685 r = mmu_topup_memory_caches(vcpu);
2686 if (r)
2687 return r;
2688
936a5fe6
AA		 2689 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2690 if (likely(!force_pt_level)) {
2691 level = mapping_level(vcpu, gfn);
2692 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2693 } else
2694 level = PT_PAGE_TABLE_LEVEL;
852e3c19 2695
e930bffe 2696 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2697 smp_rmb();
af585b92 2698
78b2c54a 2699 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
af585b92
GN		 2700 return 0;
2701
2702 /* mmio */
bf998156
HY		 2703 if (is_error_pfn(pfn))
2704 return kvm_handle_bad_page(vcpu->kvm, gfn, pfn);
fb72d167 2705 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2706 if (mmu_notifier_retry(vcpu, mmu_seq))
2707 goto out_unlock;
fb72d167 2708 kvm_mmu_free_some_pages(vcpu);
936a5fe6
AA		 2709 if (likely(!force_pt_level))
2710 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
612819c3 2711 r = __direct_map(vcpu, gpa, write, map_writable,
2ec4739d 2712 level, gfn, pfn, prefault);
fb72d167 2713 spin_unlock(&vcpu->kvm->mmu_lock);
fb72d167
JR		 2714
2715 return r;
e930bffe
AA		 2716
2717out_unlock:
2718 spin_unlock(&vcpu->kvm->mmu_lock);
2719 kvm_release_pfn_clean(pfn);
2720 return 0;
fb72d167
JR		 2721}
2722
6aa8b732
AK		 2723static void nonpaging_free(struct kvm_vcpu *vcpu)
2724{
17ac10ad 2725 mmu_free_roots(vcpu);
6aa8b732
AK		 2726}
2727
52fde8df
JR		 2728static int nonpaging_init_context(struct kvm_vcpu *vcpu,
2729 struct kvm_mmu *context)
6aa8b732 2730{
6aa8b732
AK		 2731 context->new_cr3 = nonpaging_new_cr3;
2732 context->page_fault = nonpaging_page_fault;
6aa8b732
AK		 2733 context->gva_to_gpa = nonpaging_gva_to_gpa;
2734 context->free = nonpaging_free;
c7addb90 2735 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2736 context->sync_page = nonpaging_sync_page;
a7052897 2737 context->invlpg = nonpaging_invlpg;
0f53b5b1 2738 context->update_pte = nonpaging_update_pte;
cea0f0e7 2739 context->root_level = 0;
6aa8b732 2740 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2741 context->root_hpa = INVALID_PAGE;
c5a78f2b 2742 context->direct_map = true;
2d48a985 2743 context->nx = false;
6aa8b732
AK		 2744 return 0;
2745}
2746
d835dfec 2747void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
6aa8b732 2748{
1165f5fe 2749 ++vcpu->stat.tlb_flush;
a8eeb04a 2750 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
6aa8b732
AK		 2751}
2752
2753static void paging_new_cr3(struct kvm_vcpu *vcpu)
2754{
9f8fe504 2755 pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
cea0f0e7 2756 mmu_free_roots(vcpu);
6aa8b732
AK		 2757}
2758
5777ed34
JR		 2759static unsigned long get_cr3(struct kvm_vcpu *vcpu)
2760{
9f8fe504 2761 return kvm_read_cr3(vcpu);
5777ed34
JR		 2762}
2763
6389ee94
AK		 2764static void inject_page_fault(struct kvm_vcpu *vcpu,
2765 struct x86_exception *fault)
6aa8b732 2766{
6389ee94 2767 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
6aa8b732
AK		 2768}
2769
6aa8b732
AK		 2770static void paging_free(struct kvm_vcpu *vcpu)
2771{
2772 nonpaging_free(vcpu);
2773}
2774
3241f22d 2775static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
82725b20
DE		 2776{
2777 int bit7;
2778
2779 bit7 = (gpte >> 7) & 1;
3241f22d 2780 return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
82725b20
DE		 2781}
2782
6aa8b732
AK		 2783#define PTTYPE 64
2784#include "paging_tmpl.h"
2785#undef PTTYPE
2786
2787#define PTTYPE 32
2788#include "paging_tmpl.h"
2789#undef PTTYPE
2790
52fde8df
JR		 2791static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
2792 struct kvm_mmu *context,
2793 int level)
82725b20 2794{
82725b20
DE		 2795 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2796 u64 exb_bit_rsvd = 0;
2797
2d48a985 2798 if (!context->nx)
82725b20
DE		 2799 exb_bit_rsvd = rsvd_bits(63, 63);
2800 switch (level) {
2801 case PT32_ROOT_LEVEL:
2802 /* no rsvd bits for 2 level 4K page table entries */
2803 context->rsvd_bits_mask[0][1] = 0;
2804 context->rsvd_bits_mask[0][0] = 0;
f815bce8
XG		 2805 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
2806
2807 if (!is_pse(vcpu)) {
2808 context->rsvd_bits_mask[1][1] = 0;
2809 break;
2810 }
2811
82725b20
DE		 2812 if (is_cpuid_PSE36())
2813 /* 36bits PSE 4MB page */
2814 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2815 else
2816 /* 32 bits PSE 4MB page */
2817 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
82725b20
DE		 2818 break;
2819 case PT32E_ROOT_LEVEL:
20c466b5
DE		 2820 context->rsvd_bits_mask[0][2] =
2821 rsvd_bits(maxphyaddr, 63) |
2822 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
82725b20 2823 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2824 rsvd_bits(maxphyaddr, 62); /* PDE */
82725b20
DE		 2825 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2826 rsvd_bits(maxphyaddr, 62); /* PTE */
2827 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2828 rsvd_bits(maxphyaddr, 62) |
2829 rsvd_bits(13, 20); /* large page */
f815bce8 2830 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
82725b20
DE		 2831 break;
2832 case PT64_ROOT_LEVEL:
2833 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2834 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2835 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2836 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2837 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2838 rsvd_bits(maxphyaddr, 51);
82725b20
DE		 2839 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2840 rsvd_bits(maxphyaddr, 51);
2841 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
e04da980
JR		 2842 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
2843 rsvd_bits(maxphyaddr, 51) |
2844 rsvd_bits(13, 29);
82725b20 2845 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4c26b4cd
SY		 2846 rsvd_bits(maxphyaddr, 51) |
2847 rsvd_bits(13, 20); /* large page */
f815bce8 2848 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
82725b20
DE		 2849 break;
2850 }
2851}
2852
52fde8df
JR		 2853static int paging64_init_context_common(struct kvm_vcpu *vcpu,
2854 struct kvm_mmu *context,
2855 int level)
6aa8b732 2856{
2d48a985
JR		 2857 context->nx = is_nx(vcpu);
2858
52fde8df 2859 reset_rsvds_bits_mask(vcpu, context, level);
6aa8b732
AK		 2860
2861 ASSERT(is_pae(vcpu));
2862 context->new_cr3 = paging_new_cr3;
2863 context->page_fault = paging64_page_fault;
6aa8b732 2864 context->gva_to_gpa = paging64_gva_to_gpa;
c7addb90 2865 context->prefetch_page = paging64_prefetch_page;
e8bc217a 2866 context->sync_page = paging64_sync_page;
a7052897 2867 context->invlpg = paging64_invlpg;
0f53b5b1 2868 context->update_pte = paging64_update_pte;
6aa8b732 2869 context->free = paging_free;
17ac10ad
AK		 2870 context->root_level = level;
2871 context->shadow_root_level = level;
17c3ba9d 2872 context->root_hpa = INVALID_PAGE;
c5a78f2b 2873 context->direct_map = false;
6aa8b732
AK		 2874 return 0;
2875}
2876
52fde8df
JR		 2877static int paging64_init_context(struct kvm_vcpu *vcpu,
2878 struct kvm_mmu *context)
17ac10ad 2879{
52fde8df 2880 return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
17ac10ad
AK		 2881}
2882
52fde8df
JR		 2883static int paging32_init_context(struct kvm_vcpu *vcpu,
2884 struct kvm_mmu *context)
6aa8b732 2885{
2d48a985
JR		 2886 context->nx = false;
2887
52fde8df 2888 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
6aa8b732
AK		 2889
2890 context->new_cr3 = paging_new_cr3;
2891 context->page_fault = paging32_page_fault;
6aa8b732
AK		 2892 context->gva_to_gpa = paging32_gva_to_gpa;
2893 context->free = paging_free;
c7addb90 2894 context->prefetch_page = paging32_prefetch_page;
e8bc217a 2895 context->sync_page = paging32_sync_page;
a7052897 2896 context->invlpg = paging32_invlpg;
0f53b5b1 2897 context->update_pte = paging32_update_pte;
6aa8b732
AK		 2898 context->root_level = PT32_ROOT_LEVEL;
2899 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2900 context->root_hpa = INVALID_PAGE;
c5a78f2b 2901 context->direct_map = false;
6aa8b732
AK		 2902 return 0;
2903}
2904
52fde8df
JR		 2905static int paging32E_init_context(struct kvm_vcpu *vcpu,
2906 struct kvm_mmu *context)
6aa8b732 2907{
52fde8df 2908 return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
6aa8b732
AK		 2909}
2910
fb72d167
JR		 2911static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2912{
14dfe855 2913 struct kvm_mmu *context = vcpu->arch.walk_mmu;
fb72d167 2914
c445f8ef 2915 context->base_role.word = 0;
fb72d167
JR		 2916 context->new_cr3 = nonpaging_new_cr3;
2917 context->page_fault = tdp_page_fault;
2918 context->free = nonpaging_free;
2919 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2920 context->sync_page = nonpaging_sync_page;
a7052897 2921 context->invlpg = nonpaging_invlpg;
0f53b5b1 2922 context->update_pte = nonpaging_update_pte;
67253af5 2923 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
fb72d167 2924 context->root_hpa = INVALID_PAGE;
c5a78f2b 2925 context->direct_map = true;
1c97f0a0 2926 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
5777ed34 2927 context->get_cr3 = get_cr3;
cb659db8 2928 context->inject_page_fault = kvm_inject_page_fault;
2d48a985 2929 context->nx = is_nx(vcpu);
fb72d167
JR		 2930
2931 if (!is_paging(vcpu)) {
2d48a985 2932 context->nx = false;
fb72d167
JR		 2933 context->gva_to_gpa = nonpaging_gva_to_gpa;
2934 context->root_level = 0;
2935 } else if (is_long_mode(vcpu)) {
2d48a985 2936 context->nx = is_nx(vcpu);
52fde8df 2937 reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL);
fb72d167
JR		 2938 context->gva_to_gpa = paging64_gva_to_gpa;
2939 context->root_level = PT64_ROOT_LEVEL;
2940 } else if (is_pae(vcpu)) {
2d48a985 2941 context->nx = is_nx(vcpu);
52fde8df 2942 reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL);
fb72d167
JR		 2943 context->gva_to_gpa = paging64_gva_to_gpa;
2944 context->root_level = PT32E_ROOT_LEVEL;
2945 } else {
2d48a985 2946 context->nx = false;
52fde8df 2947 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
fb72d167
JR		 2948 context->gva_to_gpa = paging32_gva_to_gpa;
2949 context->root_level = PT32_ROOT_LEVEL;
2950 }
2951
2952 return 0;
2953}
2954
52fde8df 2955int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
6aa8b732 2956{
a770f6f2 2957 int r;
6aa8b732 2958 ASSERT(vcpu);
ad312c7c 2959 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732
AK		 2960
2961 if (!is_paging(vcpu))
52fde8df 2962 r = nonpaging_init_context(vcpu, context);
a9058ecd 2963 else if (is_long_mode(vcpu))
52fde8df 2964 r = paging64_init_context(vcpu, context);
6aa8b732 2965 else if (is_pae(vcpu))
52fde8df 2966 r = paging32E_init_context(vcpu, context);
6aa8b732 2967 else
52fde8df 2968 r = paging32_init_context(vcpu, context);
a770f6f2 2969
5b7e0102 2970 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
f43addd4 2971 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
52fde8df
JR		 2972
2973 return r;
2974}
2975EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
2976
2977static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
2978{
14dfe855 2979 int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
52fde8df 2980
14dfe855
JR		 2981 vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3;
2982 vcpu->arch.walk_mmu->get_cr3 = get_cr3;
2983 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
a770f6f2
AK		 2984
2985 return r;
6aa8b732
AK		 2986}
2987
02f59dc9
JR		 2988static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
2989{
2990 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
2991
2992 g_context->get_cr3 = get_cr3;
2993 g_context->inject_page_fault = kvm_inject_page_fault;
2994
2995 /*
2996 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
2997 * translation of l2_gpa to l1_gpa addresses is done using the
2998 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
2999 * functions between mmu and nested_mmu are swapped.
3000 */
3001 if (!is_paging(vcpu)) {
2d48a985 3002 g_context->nx = false;
02f59dc9
JR		 3003 g_context->root_level = 0;
3004 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3005 } else if (is_long_mode(vcpu)) {
2d48a985 3006 g_context->nx = is_nx(vcpu);
02f59dc9
JR		 3007 reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL);
3008 g_context->root_level = PT64_ROOT_LEVEL;
3009 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3010 } else if (is_pae(vcpu)) {
2d48a985 3011 g_context->nx = is_nx(vcpu);
02f59dc9
JR		 3012 reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL);
3013 g_context->root_level = PT32E_ROOT_LEVEL;
3014 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3015 } else {
2d48a985 3016 g_context->nx = false;
02f59dc9
JR		 3017 reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL);
3018 g_context->root_level = PT32_ROOT_LEVEL;
3019 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3020 }
3021
3022 return 0;
3023}
3024
fb72d167
JR		 3025static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3026{
02f59dc9
JR		 3027 if (mmu_is_nested(vcpu))
3028 return init_kvm_nested_mmu(vcpu);
3029 else if (tdp_enabled)
fb72d167
JR		 3030 return init_kvm_tdp_mmu(vcpu);
3031 else
3032 return init_kvm_softmmu(vcpu);
3033}
3034
6aa8b732
AK		 3035static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3036{
3037 ASSERT(vcpu);
62ad0755
SY		 3038 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3039 /* mmu.free() should set root_hpa = INVALID_PAGE */
ad312c7c 3040 vcpu->arch.mmu.free(vcpu);
6aa8b732
AK		 3041}
3042
3043int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
17c3ba9d
AK		 3044{
3045 destroy_kvm_mmu(vcpu);
3046 return init_kvm_mmu(vcpu);
3047}
8668a3c4 3048EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
17c3ba9d
AK		 3049
3050int kvm_mmu_load(struct kvm_vcpu *vcpu)
6aa8b732 3051{
714b93da
AK		 3052 int r;
3053
e2dec939 3054 r = mmu_topup_memory_caches(vcpu);
17c3ba9d
AK		 3055 if (r)
3056 goto out;
8986ecc0 3057 r = mmu_alloc_roots(vcpu);
8facbbff 3058 spin_lock(&vcpu->kvm->mmu_lock);
0ba73cda 3059 mmu_sync_roots(vcpu);
aaee2c94 3060 spin_unlock(&vcpu->kvm->mmu_lock);
8986ecc0
MT		 3061 if (r)
3062 goto out;
3662cb1c 3063 /* set_cr3() should ensure TLB has been flushed */
f43addd4 3064 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
714b93da
AK		 3065out:
3066 return r;
6aa8b732 3067}
17c3ba9d
AK		 3068EXPORT_SYMBOL_GPL(kvm_mmu_load);
3069
3070void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3071{
3072 mmu_free_roots(vcpu);
3073}
4b16184c 3074EXPORT_SYMBOL_GPL(kvm_mmu_unload);
6aa8b732 3075
0028425f 3076static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
7c562522
XG		 3077 struct kvm_mmu_page *sp, u64 *spte,
3078 const void *new)
0028425f 3079{
30945387 3080 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
7e4e4056
JR		 3081 ++vcpu->kvm->stat.mmu_pde_zapped;
3082 return;
30945387 3083 }
0028425f 3084
4cee5764 3085 ++vcpu->kvm->stat.mmu_pte_updated;
7c562522 3086 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
0028425f
AK		 3087}
3088
79539cec
AK		 3089static bool need_remote_flush(u64 old, u64 new)
3090{
3091 if (!is_shadow_present_pte(old))
3092 return false;
3093 if (!is_shadow_present_pte(new))
3094 return true;
3095 if ((old ^ new) & PT64_BASE_ADDR_MASK)
3096 return true;
3097 old ^= PT64_NX_MASK;
3098 new ^= PT64_NX_MASK;
3099 return (old & ~new & PT64_PERM_MASK) != 0;
3100}
3101
0671a8e7
XG		 3102static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3103 bool remote_flush, bool local_flush)
79539cec 3104{
0671a8e7
XG		 3105 if (zap_page)
3106 return;
3107
3108 if (remote_flush)
79539cec 3109 kvm_flush_remote_tlbs(vcpu->kvm);
0671a8e7 3110 else if (local_flush)
79539cec
AK		 3111 kvm_mmu_flush_tlb(vcpu);
3112}
3113
12b7d28f
AK		 3114static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
3115{
ad312c7c 3116 u64 *spte = vcpu->arch.last_pte_updated;
12b7d28f 3117
7b52345e 3118 return !!(spte && (*spte & shadow_accessed_mask));
12b7d28f
AK		 3119}
3120
1b7fcd32
AK		 3121static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
3122{
3123 u64 *spte = vcpu->arch.last_pte_updated;
3124
3125 if (spte
3126 && vcpu->arch.last_pte_gfn == gfn
3127 && shadow_accessed_mask
3128 && !(*spte & shadow_accessed_mask)
3129 && is_shadow_present_pte(*spte))
3130 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
3131}
3132
09072daf 3133void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
ad218f85
MT		 3134 const u8 *new, int bytes,
3135 bool guest_initiated)
da4a00f0 3136{
9b7a0325 3137 gfn_t gfn = gpa >> PAGE_SHIFT;
fa1de2bf 3138 union kvm_mmu_page_role mask = { .word = 0 };
4db35314 3139 struct kvm_mmu_page *sp;
f41d335a 3140 struct hlist_node *node;
d98ba053 3141 LIST_HEAD(invalid_list);
0f53b5b1
XG		 3142 u64 entry, gentry, *spte;
3143 unsigned pte_size, page_offset, misaligned, quadrant, offset;
3144 int level, npte, invlpg_counter, r, flooded = 0;
0671a8e7
XG		 3145 bool remote_flush, local_flush, zap_page;
3146
332b207d
XG		 3147 /*
3148 * If we don't have indirect shadow pages, it means no page is
3149 * write-protected, so we can exit simply.
3150 */
3151 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
3152 return;
3153
0671a8e7 3154 zap_page = remote_flush = local_flush = false;
0f53b5b1 3155 offset = offset_in_page(gpa);
9b7a0325 3156
b8688d51 3157 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
72016f3a 3158
08e850c6 3159 invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter);
72016f3a
AK		 3160
3161 /*
3162 * Assume that the pte write on a page table of the same type
49b26e26
XG		 3163 * as the current vcpu paging mode since we update the sptes only
3164 * when they have the same mode.
72016f3a 3165 */
08e850c6 3166 if ((is_pae(vcpu) && bytes == 4) || !new) {
72016f3a 3167 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
08e850c6
AK		 3168 if (is_pae(vcpu)) {
3169 gpa &= ~(gpa_t)7;
3170 bytes = 8;
3171 }
3172 r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8));
72016f3a
AK		 3173 if (r)
3174 gentry = 0;
08e850c6
AK		 3175 new = (const u8 *)&gentry;
3176 }
3177
3178 switch (bytes) {
3179 case 4:
3180 gentry = *(const u32 *)new;
3181 break;
3182 case 8:
3183 gentry = *(const u64 *)new;
3184 break;
3185 default:
3186 gentry = 0;
3187 break;
72016f3a
AK		 3188 }
3189
aaee2c94 3190 spin_lock(&vcpu->kvm->mmu_lock);
08e850c6
AK		 3191 if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter)
3192 gentry = 0;
eb787d10 3193 kvm_mmu_free_some_pages(vcpu);
4cee5764 3194 ++vcpu->kvm->stat.mmu_pte_write;
8b1fe17c 3195 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
ad218f85 3196 if (guest_initiated) {
1b7fd45c 3197 kvm_mmu_access_page(vcpu, gfn);
ad218f85
MT		 3198 if (gfn == vcpu->arch.last_pt_write_gfn
3199 && !last_updated_pte_accessed(vcpu)) {
3200 ++vcpu->arch.last_pt_write_count;
3201 if (vcpu->arch.last_pt_write_count >= 3)
3202 flooded = 1;
3203 } else {
3204 vcpu->arch.last_pt_write_gfn = gfn;
3205 vcpu->arch.last_pt_write_count = 1;
3206 vcpu->arch.last_pte_updated = NULL;
3207 }
86a5ba02 3208 }
3246af0e 3209
fa1de2bf 3210 mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
f41d335a 3211 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
5b7e0102 3212 pte_size = sp->role.cr4_pae ? 8 : 4;
0e7bc4b9 3213 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
e925c5ba 3214 misaligned |= bytes < 4;
86a5ba02 3215 if (misaligned || flooded) {
0e7bc4b9
AK		 3216 /*
3217 * Misaligned accesses are too much trouble to fix
3218 * up; also, they usually indicate a page is not used
3219 * as a page table.
86a5ba02
AK		 3220 *
3221 * If we're seeing too many writes to a page,
3222 * it may no longer be a page table, or we may be
3223 * forking, in which case it is better to unmap the
3224 * page.
0e7bc4b9
AK		 3225 */
3226 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4db35314 3227 gpa, bytes, sp->role.word);
0671a8e7 3228 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
f41d335a 3229 &invalid_list);
4cee5764 3230 ++vcpu->kvm->stat.mmu_flooded;
0e7bc4b9
AK		 3231 continue;
3232 }
9b7a0325 3233 page_offset = offset;
4db35314 3234 level = sp->role.level;
ac1b714e 3235 npte = 1;
5b7e0102 3236 if (!sp->role.cr4_pae) {
ac1b714e
AK		 3237 page_offset <<= 1; /* 32->64 */
3238 /*
3239 * A 32-bit pde maps 4MB while the shadow pdes map
3240 * only 2MB. So we need to double the offset again
3241 * and zap two pdes instead of one.
3242 */
3243 if (level == PT32_ROOT_LEVEL) {
6b8d0f9b 3244 page_offset &= ~7; /* kill rounding error */
ac1b714e
AK		 3245 page_offset <<= 1;
3246 npte = 2;
3247 }
fce0657f 3248 quadrant = page_offset >> PAGE_SHIFT;
9b7a0325 3249 page_offset &= ~PAGE_MASK;
4db35314 3250 if (quadrant != sp->role.quadrant)
fce0657f 3251 continue;
9b7a0325 3252 }
0671a8e7 3253 local_flush = true;
4db35314 3254 spte = &sp->spt[page_offset / sizeof(*spte)];
ac1b714e 3255 while (npte--) {
79539cec 3256 entry = *spte;
38e3b2b2 3257 mmu_page_zap_pte(vcpu->kvm, sp, spte);
fa1de2bf
XG		 3258 if (gentry &&
3259 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
3260 & mask.word))
7c562522 3261 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
0671a8e7
XG		 3262 if (!remote_flush && need_remote_flush(entry, *spte))
3263 remote_flush = true;
ac1b714e 3264 ++spte;
9b7a0325 3265 }
9b7a0325 3266 }
0671a8e7 3267 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
d98ba053 3268 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
8b1fe17c 3269 trace_kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
aaee2c94 3270 spin_unlock(&vcpu->kvm->mmu_lock);
da4a00f0
AK		 3271}
3272
a436036b
AK		 3273int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
3274{
10589a46
MT		 3275 gpa_t gpa;
3276 int r;
a436036b 3277
c5a78f2b 3278 if (vcpu->arch.mmu.direct_map)
60f24784
AK		 3279 return 0;
3280
1871c602 3281 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
10589a46 3282
aaee2c94 3283 spin_lock(&vcpu->kvm->mmu_lock);
10589a46 3284 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
aaee2c94 3285 spin_unlock(&vcpu->kvm->mmu_lock);
10589a46 3286 return r;
a436036b 3287}
577bdc49 3288EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
a436036b 3289
22d95b12 3290void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
ebeace86 3291{
d98ba053 3292 LIST_HEAD(invalid_list);
103ad25a 3293
e0df7b9f 3294 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
3b80fffe 3295 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
4db35314 3296 struct kvm_mmu_page *sp;
ebeace86 3297
f05e70ac 3298 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4db35314 3299 struct kvm_mmu_page, link);
e0df7b9f 3300 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
80b63faf 3301 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4cee5764 3302 ++vcpu->kvm->stat.mmu_recycled;
ebeace86
AK		 3303 }
3304}
ebeace86 3305
dc25e89e
AP		 3306int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
3307 void *insn, int insn_len)
3067714c
AK		 3308{
3309 int r;
3310 enum emulation_result er;
3311
56028d08 3312 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
3067714c
AK		 3313 if (r < 0)
3314 goto out;
3315
3316 if (!r) {
3317 r = 1;
3318 goto out;
3319 }
3320
b733bfb5
AK		 3321 r = mmu_topup_memory_caches(vcpu);
3322 if (r)
3323 goto out;
3324
dc25e89e 3325 er = x86_emulate_instruction(vcpu, cr2, 0, insn, insn_len);
3067714c
AK		 3326
3327 switch (er) {
3328 case EMULATE_DONE:
3329 return 1;
3330 case EMULATE_DO_MMIO:
3331 ++vcpu->stat.mmio_exits;
6d77dbfc 3332 /* fall through */
3067714c 3333 case EMULATE_FAIL:
3f5d18a9 3334 return 0;
3067714c
AK		 3335 default:
3336 BUG();
3337 }
3338out:
3067714c
AK		 3339 return r;
3340}
3341EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
3342
a7052897
MT		 3343void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
3344{
a7052897 3345 vcpu->arch.mmu.invlpg(vcpu, gva);
a7052897
MT		 3346 kvm_mmu_flush_tlb(vcpu);
3347 ++vcpu->stat.invlpg;
3348}
3349EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
3350
18552672
JR		 3351void kvm_enable_tdp(void)
3352{
3353 tdp_enabled = true;
3354}
3355EXPORT_SYMBOL_GPL(kvm_enable_tdp);
3356
5f4cb662
JR		 3357void kvm_disable_tdp(void)
3358{
3359 tdp_enabled = false;
3360}
3361EXPORT_SYMBOL_GPL(kvm_disable_tdp);
3362
6aa8b732
AK		 3363static void free_mmu_pages(struct kvm_vcpu *vcpu)
3364{
ad312c7c 3365 free_page((unsigned long)vcpu->arch.mmu.pae_root);
81407ca5
JR		 3366 if (vcpu->arch.mmu.lm_root != NULL)
3367 free_page((unsigned long)vcpu->arch.mmu.lm_root);
6aa8b732
AK		 3368}
3369
3370static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
3371{
17ac10ad 3372 struct page *page;
6aa8b732
AK		 3373 int i;
3374
3375 ASSERT(vcpu);
3376
17ac10ad
AK		 3377 /*
3378 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
3379 * Therefore we need to allocate shadow page tables in the first
3380 * 4GB of memory, which happens to fit the DMA32 zone.
3381 */
3382 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
3383 if (!page)
d7fa6ab2
WY		 3384 return -ENOMEM;
3385
ad312c7c 3386 vcpu->arch.mmu.pae_root = page_address(page);
17ac10ad 3387 for (i = 0; i < 4; ++i)
ad312c7c 3388 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 3389
6aa8b732 3390 return 0;
6aa8b732
AK		 3391}
3392
8018c27b 3393int kvm_mmu_create(struct kvm_vcpu *vcpu)
6aa8b732 3394{
6aa8b732 3395 ASSERT(vcpu);
ad312c7c 3396 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 3397
8018c27b
IM		 3398 return alloc_mmu_pages(vcpu);
3399}
6aa8b732 3400
8018c27b
IM		 3401int kvm_mmu_setup(struct kvm_vcpu *vcpu)
3402{
3403 ASSERT(vcpu);
ad312c7c 3404 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2c264957 3405
8018c27b 3406 return init_kvm_mmu(vcpu);
6aa8b732
AK		 3407}
3408
90cb0529 3409void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
6aa8b732 3410{
4db35314 3411 struct kvm_mmu_page *sp;
6aa8b732 3412
f05e70ac 3413 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
6aa8b732
AK		 3414 int i;
3415 u64 *pt;
3416
291f26bc 3417 if (!test_bit(slot, sp->slot_bitmap))
6aa8b732
AK		 3418 continue;
3419
4db35314 3420 pt = sp->spt;
8234b22e 3421 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
da8dc75f
XG		 3422 if (!is_shadow_present_pte(pt[i]) ||
3423 !is_last_spte(pt[i], sp->role.level))
3424 continue;
3425
3426 if (is_large_pte(pt[i])) {
8234b22e
AK		 3427 drop_spte(kvm, &pt[i],
3428 shadow_trap_nonpresent_pte);
3429 --kvm->stat.lpages;
da8dc75f 3430 continue;
8234b22e 3431 }
da8dc75f 3432
6aa8b732 3433 /* avoid RMW */
01c168ac 3434 if (is_writable_pte(pt[i]))
700e1b12 3435 update_spte(&pt[i], pt[i] & ~PT_WRITABLE_MASK);
8234b22e 3436 }
6aa8b732 3437 }
171d595d 3438 kvm_flush_remote_tlbs(kvm);
6aa8b732 3439}
37a7d8b0 3440
90cb0529 3441void kvm_mmu_zap_all(struct kvm *kvm)
e0fa826f 3442{
4db35314 3443 struct kvm_mmu_page *sp, *node;
d98ba053 3444 LIST_HEAD(invalid_list);
e0fa826f 3445
aaee2c94 3446 spin_lock(&kvm->mmu_lock);
3246af0e 3447restart:
f05e70ac 3448 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
d98ba053 3449 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
3246af0e
XG		 3450 goto restart;
3451
d98ba053 3452 kvm_mmu_commit_zap_page(kvm, &invalid_list);
aaee2c94 3453 spin_unlock(&kvm->mmu_lock);
e0fa826f
DL		 3454}
3455
d98ba053
XG		 3456static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
3457 struct list_head *invalid_list)
3ee16c81
IE		 3458{
3459 struct kvm_mmu_page *page;
3460
3461 page = container_of(kvm->arch.active_mmu_pages.prev,
3462 struct kvm_mmu_page, link);
d98ba053 3463 return kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
3ee16c81
IE		 3464}
3465
1495f230 3466static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
3ee16c81
IE		 3467{
3468 struct kvm *kvm;
3469 struct kvm *kvm_freed = NULL;
1495f230 3470 int nr_to_scan = sc->nr_to_scan;
45221ab6
DH		 3471
3472 if (nr_to_scan == 0)
3473 goto out;
3ee16c81 3474
e935b837 3475 raw_spin_lock(&kvm_lock);
3ee16c81
IE		 3476
3477 list_for_each_entry(kvm, &vm_list, vm_list) {
45221ab6 3478 int idx, freed_pages;
d98ba053 3479 LIST_HEAD(invalid_list);
3ee16c81 3480
f656ce01 3481 idx = srcu_read_lock(&kvm->srcu);
3ee16c81 3482 spin_lock(&kvm->mmu_lock);
45221ab6
DH		 3483 if (!kvm_freed && nr_to_scan > 0 &&
3484 kvm->arch.n_used_mmu_pages > 0) {
d98ba053
XG		 3485 freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm,
3486 &invalid_list);
3ee16c81
IE		 3487 kvm_freed = kvm;
3488 }
3489 nr_to_scan--;
3490
d98ba053 3491 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3ee16c81 3492 spin_unlock(&kvm->mmu_lock);
f656ce01 3493 srcu_read_unlock(&kvm->srcu, idx);
3ee16c81
IE		 3494 }
3495 if (kvm_freed)
3496 list_move_tail(&kvm_freed->vm_list, &vm_list);
3497
e935b837 3498 raw_spin_unlock(&kvm_lock);
3ee16c81 3499
45221ab6
DH		 3500out:
3501 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
3ee16c81
IE		 3502}
3503
3504static struct shrinker mmu_shrinker = {
3505 .shrink = mmu_shrink,
3506 .seeks = DEFAULT_SEEKS * 10,
3507};
3508
2ddfd20e 3509static void mmu_destroy_caches(void)
b5a33a75 3510{
53c07b18
XG		 3511 if (pte_list_desc_cache)
3512 kmem_cache_destroy(pte_list_desc_cache);
d3d25b04
AK		 3513 if (mmu_page_header_cache)
3514 kmem_cache_destroy(mmu_page_header_cache);
b5a33a75
AK		 3515}
3516
3517int kvm_mmu_module_init(void)
3518{
53c07b18
XG		 3519 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
3520 sizeof(struct pte_list_desc),
20c2df83 3521 0, 0, NULL);
53c07b18 3522 if (!pte_list_desc_cache)
b5a33a75
AK		 3523 goto nomem;
3524
d3d25b04
AK		 3525 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3526 sizeof(struct kvm_mmu_page),
20c2df83 3527 0, 0, NULL);
d3d25b04
AK		 3528 if (!mmu_page_header_cache)
3529 goto nomem;
3530
45bf21a8
WY		 3531 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
3532 goto nomem;
3533
3ee16c81
IE		 3534 register_shrinker(&mmu_shrinker);
3535
b5a33a75
AK		 3536 return 0;
3537
3538nomem:
3ee16c81 3539 mmu_destroy_caches();
b5a33a75
AK		 3540 return -ENOMEM;
3541}
3542
3ad82a7e
ZX		 3543/*
3544 * Caculate mmu pages needed for kvm.
3545 */
3546unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3547{
3548 int i;
3549 unsigned int nr_mmu_pages;
3550 unsigned int nr_pages = 0;
bc6678a3 3551 struct kvm_memslots *slots;
3ad82a7e 3552
90d83dc3
LJ		 3553 slots = kvm_memslots(kvm);
3554
bc6678a3
MT		 3555 for (i = 0; i < slots->nmemslots; i++)
3556 nr_pages += slots->memslots[i].npages;
3ad82a7e
ZX		 3557
3558 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3559 nr_mmu_pages = max(nr_mmu_pages,
3560 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3561
3562 return nr_mmu_pages;
3563}
3564
2f333bcb
MT		 3565static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3566 unsigned len)
3567{
3568 if (len > buffer->len)
3569 return NULL;
3570 return buffer->ptr;
3571}
3572
3573static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3574 unsigned len)
3575{
3576 void *ret;
3577
3578 ret = pv_mmu_peek_buffer(buffer, len);
3579 if (!ret)
3580 return ret;
3581 buffer->ptr += len;
3582 buffer->len -= len;
3583 buffer->processed += len;
3584 return ret;
3585}
3586
3587static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3588 gpa_t addr, gpa_t value)
3589{
3590 int bytes = 8;
3591 int r;
3592
3593 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3594 bytes = 4;
3595
3596 r = mmu_topup_memory_caches(vcpu);
3597 if (r)
3598 return r;
3599
3200f405 3600 if (!emulator_write_phys(vcpu, addr, &value, bytes))
2f333bcb
MT		 3601 return -EFAULT;
3602
3603 return 1;
3604}
3605
3606static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3607{
9f8fe504 3608 (void)kvm_set_cr3(vcpu, kvm_read_cr3(vcpu));
2f333bcb
MT		 3609 return 1;
3610}
3611
3612static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3613{
3614 spin_lock(&vcpu->kvm->mmu_lock);
3615 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3616 spin_unlock(&vcpu->kvm->mmu_lock);
3617 return 1;
3618}
3619
3620static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3621 struct kvm_pv_mmu_op_buffer *buffer)
3622{
3623 struct kvm_mmu_op_header *header;
3624
3625 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3626 if (!header)
3627 return 0;
3628 switch (header->op) {
3629 case KVM_MMU_OP_WRITE_PTE: {
3630 struct kvm_mmu_op_write_pte *wpte;
3631
3632 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3633 if (!wpte)
3634 return 0;
3635 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3636 wpte->pte_val);
3637 }
3638 case KVM_MMU_OP_FLUSH_TLB: {
3639 struct kvm_mmu_op_flush_tlb *ftlb;
3640
3641 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3642 if (!ftlb)
3643 return 0;
3644 return kvm_pv_mmu_flush_tlb(vcpu);
3645 }
3646 case KVM_MMU_OP_RELEASE_PT: {
3647 struct kvm_mmu_op_release_pt *rpt;
3648
3649 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3650 if (!rpt)
3651 return 0;
3652 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3653 }
3654 default: return 0;
3655 }
3656}
3657
3658int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3659 gpa_t addr, unsigned long *ret)
3660{
3661 int r;
6ad18fba 3662 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
2f333bcb 3663
6ad18fba
DH		 3664 buffer->ptr = buffer->buf;
3665 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3666 buffer->processed = 0;
2f333bcb 3667
6ad18fba 3668 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
2f333bcb
MT		 3669 if (r)
3670 goto out;
3671
6ad18fba
DH		 3672 while (buffer->len) {
3673 r = kvm_pv_mmu_op_one(vcpu, buffer);
2f333bcb
MT		 3674 if (r < 0)
3675 goto out;
3676 if (r == 0)
3677 break;
3678 }
3679
3680 r = 1;
3681out:
6ad18fba 3682 *ret = buffer->processed;
2f333bcb
MT		 3683 return r;
3684}
3685
94d8b056
MT		 3686int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3687{
3688 struct kvm_shadow_walk_iterator iterator;
3689 int nr_sptes = 0;
3690
3691 spin_lock(&vcpu->kvm->mmu_lock);
3692 for_each_shadow_entry(vcpu, addr, iterator) {
3693 sptes[iterator.level-1] = *iterator.sptep;
3694 nr_sptes++;
3695 if (!is_shadow_present_pte(*iterator.sptep))
3696 break;
3697 }
3698 spin_unlock(&vcpu->kvm->mmu_lock);
3699
3700 return nr_sptes;
3701}
3702EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3703
c42fffe3
XG		 3704void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
3705{
3706 ASSERT(vcpu);
3707
3708 destroy_kvm_mmu(vcpu);
3709 free_mmu_pages(vcpu);
3710 mmu_free_memory_caches(vcpu);
b034cf01
XG		 3711}
3712
3713#ifdef CONFIG_KVM_MMU_AUDIT
3714#include "mmu_audit.c"
3715#else
3716static void mmu_audit_disable(void) { }
3717#endif
3718
3719void kvm_mmu_module_exit(void)
3720{
3721 mmu_destroy_caches();
3722 percpu_counter_destroy(&kvm_total_used_mmu_pages);
3723 unregister_shrinker(&mmu_shrinker);
c42fffe3
XG		 3724 mmu_audit_disable();
3725}
Linux 6.x block layer and io_uring tree(s)