Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
10 | * | |
11 | * Authors: | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * | |
15 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
16 | * the COPYING file in the top-level directory. | |
17 | * | |
18 | */ | |
e495606d AK |
19 | |
20 | #include "vmx.h" | |
1d737c8a | 21 | #include "mmu.h" |
e495606d | 22 | |
edf88417 | 23 | #include <linux/kvm_host.h> |
6aa8b732 AK |
24 | #include <linux/types.h> |
25 | #include <linux/string.h> | |
6aa8b732 AK |
26 | #include <linux/mm.h> |
27 | #include <linux/highmem.h> | |
28 | #include <linux/module.h> | |
448353ca | 29 | #include <linux/swap.h> |
6aa8b732 | 30 | |
e495606d AK |
31 | #include <asm/page.h> |
32 | #include <asm/cmpxchg.h> | |
4e542370 | 33 | #include <asm/io.h> |
6aa8b732 | 34 | |
37a7d8b0 AK |
35 | #undef MMU_DEBUG |
36 | ||
37 | #undef AUDIT | |
38 | ||
39 | #ifdef AUDIT | |
40 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg); | |
41 | #else | |
42 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {} | |
43 | #endif | |
44 | ||
45 | #ifdef MMU_DEBUG | |
46 | ||
47 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
48 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
49 | ||
50 | #else | |
51 | ||
52 | #define pgprintk(x...) do { } while (0) | |
53 | #define rmap_printk(x...) do { } while (0) | |
54 | ||
55 | #endif | |
56 | ||
57 | #if defined(MMU_DEBUG) || defined(AUDIT) | |
58 | static int dbg = 1; | |
59 | #endif | |
6aa8b732 | 60 | |
d6c69ee9 YD |
61 | #ifndef MMU_DEBUG |
62 | #define ASSERT(x) do { } while (0) | |
63 | #else | |
6aa8b732 AK |
64 | #define ASSERT(x) \ |
65 | if (!(x)) { \ | |
66 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
67 | __FILE__, __LINE__, #x); \ | |
68 | } | |
d6c69ee9 | 69 | #endif |
6aa8b732 | 70 | |
cea0f0e7 AK |
71 | #define PT64_PT_BITS 9 |
72 | #define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS) | |
73 | #define PT32_PT_BITS 10 | |
74 | #define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS) | |
6aa8b732 AK |
75 | |
76 | #define PT_WRITABLE_SHIFT 1 | |
77 | ||
78 | #define PT_PRESENT_MASK (1ULL << 0) | |
79 | #define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT) | |
80 | #define PT_USER_MASK (1ULL << 2) | |
81 | #define PT_PWT_MASK (1ULL << 3) | |
82 | #define PT_PCD_MASK (1ULL << 4) | |
83 | #define PT_ACCESSED_MASK (1ULL << 5) | |
84 | #define PT_DIRTY_MASK (1ULL << 6) | |
85 | #define PT_PAGE_SIZE_MASK (1ULL << 7) | |
86 | #define PT_PAT_MASK (1ULL << 7) | |
87 | #define PT_GLOBAL_MASK (1ULL << 8) | |
fe135d2c AK |
88 | #define PT64_NX_SHIFT 63 |
89 | #define PT64_NX_MASK (1ULL << PT64_NX_SHIFT) | |
6aa8b732 AK |
90 | |
91 | #define PT_PAT_SHIFT 7 | |
92 | #define PT_DIR_PAT_SHIFT 12 | |
93 | #define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT) | |
94 | ||
95 | #define PT32_DIR_PSE36_SIZE 4 | |
96 | #define PT32_DIR_PSE36_SHIFT 13 | |
d77c26fc MD |
97 | #define PT32_DIR_PSE36_MASK \ |
98 | (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT) | |
6aa8b732 AK |
99 | |
100 | ||
6aa8b732 AK |
101 | #define PT_FIRST_AVAIL_BITS_SHIFT 9 |
102 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 | |
103 | ||
6aa8b732 AK |
104 | #define PT_SHADOW_IO_MARK (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
105 | ||
6aa8b732 AK |
106 | #define VALID_PAGE(x) ((x) != INVALID_PAGE) |
107 | ||
108 | #define PT64_LEVEL_BITS 9 | |
109 | ||
110 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 111 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 AK |
112 | |
113 | #define PT64_LEVEL_MASK(level) \ | |
114 | (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level)) | |
115 | ||
116 | #define PT64_INDEX(address, level)\ | |
117 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
118 | ||
119 | ||
120 | #define PT32_LEVEL_BITS 10 | |
121 | ||
122 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 123 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 AK |
124 | |
125 | #define PT32_LEVEL_MASK(level) \ | |
126 | (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level)) | |
127 | ||
128 | #define PT32_INDEX(address, level)\ | |
129 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
130 | ||
131 | ||
27aba766 | 132 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
133 | #define PT64_DIR_BASE_ADDR_MASK \ |
134 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
135 | ||
136 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
137 | #define PT32_DIR_BASE_ADDR_MASK \ | |
138 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
139 | ||
79539cec AK |
140 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
141 | | PT64_NX_MASK) | |
6aa8b732 AK |
142 | |
143 | #define PFERR_PRESENT_MASK (1U << 0) | |
144 | #define PFERR_WRITE_MASK (1U << 1) | |
145 | #define PFERR_USER_MASK (1U << 2) | |
73b1087e | 146 | #define PFERR_FETCH_MASK (1U << 4) |
6aa8b732 AK |
147 | |
148 | #define PT64_ROOT_LEVEL 4 | |
149 | #define PT32_ROOT_LEVEL 2 | |
150 | #define PT32E_ROOT_LEVEL 3 | |
151 | ||
152 | #define PT_DIRECTORY_LEVEL 2 | |
153 | #define PT_PAGE_TABLE_LEVEL 1 | |
154 | ||
cd4a4e53 AK |
155 | #define RMAP_EXT 4 |
156 | ||
fe135d2c AK |
157 | #define ACC_EXEC_MASK 1 |
158 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
159 | #define ACC_USER_MASK PT_USER_MASK | |
160 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
161 | ||
cd4a4e53 AK |
162 | struct kvm_rmap_desc { |
163 | u64 *shadow_ptes[RMAP_EXT]; | |
164 | struct kvm_rmap_desc *more; | |
165 | }; | |
166 | ||
b5a33a75 AK |
167 | static struct kmem_cache *pte_chain_cache; |
168 | static struct kmem_cache *rmap_desc_cache; | |
d3d25b04 | 169 | static struct kmem_cache *mmu_page_header_cache; |
b5a33a75 | 170 | |
c7addb90 AK |
171 | static u64 __read_mostly shadow_trap_nonpresent_pte; |
172 | static u64 __read_mostly shadow_notrap_nonpresent_pte; | |
173 | ||
174 | void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte) | |
175 | { | |
176 | shadow_trap_nonpresent_pte = trap_pte; | |
177 | shadow_notrap_nonpresent_pte = notrap_pte; | |
178 | } | |
179 | EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes); | |
180 | ||
6aa8b732 AK |
181 | static int is_write_protection(struct kvm_vcpu *vcpu) |
182 | { | |
ad312c7c | 183 | return vcpu->arch.cr0 & X86_CR0_WP; |
6aa8b732 AK |
184 | } |
185 | ||
186 | static int is_cpuid_PSE36(void) | |
187 | { | |
188 | return 1; | |
189 | } | |
190 | ||
73b1087e AK |
191 | static int is_nx(struct kvm_vcpu *vcpu) |
192 | { | |
ad312c7c | 193 | return vcpu->arch.shadow_efer & EFER_NX; |
73b1087e AK |
194 | } |
195 | ||
6aa8b732 AK |
196 | static int is_present_pte(unsigned long pte) |
197 | { | |
198 | return pte & PT_PRESENT_MASK; | |
199 | } | |
200 | ||
c7addb90 AK |
201 | static int is_shadow_present_pte(u64 pte) |
202 | { | |
203 | pte &= ~PT_SHADOW_IO_MARK; | |
204 | return pte != shadow_trap_nonpresent_pte | |
205 | && pte != shadow_notrap_nonpresent_pte; | |
206 | } | |
207 | ||
6aa8b732 AK |
208 | static int is_writeble_pte(unsigned long pte) |
209 | { | |
210 | return pte & PT_WRITABLE_MASK; | |
211 | } | |
212 | ||
e3c5e7ec AK |
213 | static int is_dirty_pte(unsigned long pte) |
214 | { | |
215 | return pte & PT_DIRTY_MASK; | |
216 | } | |
217 | ||
6aa8b732 AK |
218 | static int is_io_pte(unsigned long pte) |
219 | { | |
220 | return pte & PT_SHADOW_IO_MARK; | |
221 | } | |
222 | ||
cd4a4e53 AK |
223 | static int is_rmap_pte(u64 pte) |
224 | { | |
4b1a80fa | 225 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
226 | } |
227 | ||
da928521 AK |
228 | static gfn_t pse36_gfn_delta(u32 gpte) |
229 | { | |
230 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
231 | ||
232 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
233 | } | |
234 | ||
e663ee64 AK |
235 | static void set_shadow_pte(u64 *sptep, u64 spte) |
236 | { | |
237 | #ifdef CONFIG_X86_64 | |
238 | set_64bit((unsigned long *)sptep, spte); | |
239 | #else | |
240 | set_64bit((unsigned long long *)sptep, spte); | |
241 | #endif | |
242 | } | |
243 | ||
e2dec939 | 244 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 245 | struct kmem_cache *base_cache, int min) |
714b93da AK |
246 | { |
247 | void *obj; | |
248 | ||
249 | if (cache->nobjs >= min) | |
e2dec939 | 250 | return 0; |
714b93da | 251 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 252 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 253 | if (!obj) |
e2dec939 | 254 | return -ENOMEM; |
714b93da AK |
255 | cache->objects[cache->nobjs++] = obj; |
256 | } | |
e2dec939 | 257 | return 0; |
714b93da AK |
258 | } |
259 | ||
260 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc) | |
261 | { | |
262 | while (mc->nobjs) | |
263 | kfree(mc->objects[--mc->nobjs]); | |
264 | } | |
265 | ||
c1158e63 | 266 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 267 | int min) |
c1158e63 AK |
268 | { |
269 | struct page *page; | |
270 | ||
271 | if (cache->nobjs >= min) | |
272 | return 0; | |
273 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
2e3e5882 | 274 | page = alloc_page(GFP_KERNEL); |
c1158e63 AK |
275 | if (!page) |
276 | return -ENOMEM; | |
277 | set_page_private(page, 0); | |
278 | cache->objects[cache->nobjs++] = page_address(page); | |
279 | } | |
280 | return 0; | |
281 | } | |
282 | ||
283 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
284 | { | |
285 | while (mc->nobjs) | |
c4d198d5 | 286 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
287 | } |
288 | ||
2e3e5882 | 289 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 290 | { |
e2dec939 AK |
291 | int r; |
292 | ||
ad312c7c | 293 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache, |
2e3e5882 | 294 | pte_chain_cache, 4); |
e2dec939 AK |
295 | if (r) |
296 | goto out; | |
ad312c7c | 297 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, |
2e3e5882 | 298 | rmap_desc_cache, 1); |
d3d25b04 AK |
299 | if (r) |
300 | goto out; | |
ad312c7c | 301 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
302 | if (r) |
303 | goto out; | |
ad312c7c | 304 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 305 | mmu_page_header_cache, 4); |
e2dec939 AK |
306 | out: |
307 | return r; | |
714b93da AK |
308 | } |
309 | ||
310 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
311 | { | |
ad312c7c ZX |
312 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache); |
313 | mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache); | |
314 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); | |
315 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache); | |
714b93da AK |
316 | } |
317 | ||
318 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc, | |
319 | size_t size) | |
320 | { | |
321 | void *p; | |
322 | ||
323 | BUG_ON(!mc->nobjs); | |
324 | p = mc->objects[--mc->nobjs]; | |
325 | memset(p, 0, size); | |
326 | return p; | |
327 | } | |
328 | ||
714b93da AK |
329 | static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu) |
330 | { | |
ad312c7c | 331 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache, |
714b93da AK |
332 | sizeof(struct kvm_pte_chain)); |
333 | } | |
334 | ||
90cb0529 | 335 | static void mmu_free_pte_chain(struct kvm_pte_chain *pc) |
714b93da | 336 | { |
90cb0529 | 337 | kfree(pc); |
714b93da AK |
338 | } |
339 | ||
340 | static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu) | |
341 | { | |
ad312c7c | 342 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache, |
714b93da AK |
343 | sizeof(struct kvm_rmap_desc)); |
344 | } | |
345 | ||
90cb0529 | 346 | static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd) |
714b93da | 347 | { |
90cb0529 | 348 | kfree(rd); |
714b93da AK |
349 | } |
350 | ||
290fc38d IE |
351 | /* |
352 | * Take gfn and return the reverse mapping to it. | |
353 | * Note: gfn must be unaliased before this function get called | |
354 | */ | |
355 | ||
356 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn) | |
357 | { | |
358 | struct kvm_memory_slot *slot; | |
359 | ||
360 | slot = gfn_to_memslot(kvm, gfn); | |
361 | return &slot->rmap[gfn - slot->base_gfn]; | |
362 | } | |
363 | ||
cd4a4e53 AK |
364 | /* |
365 | * Reverse mapping data structures: | |
366 | * | |
290fc38d IE |
367 | * If rmapp bit zero is zero, then rmapp point to the shadw page table entry |
368 | * that points to page_address(page). | |
cd4a4e53 | 369 | * |
290fc38d IE |
370 | * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc |
371 | * containing more mappings. | |
cd4a4e53 | 372 | */ |
290fc38d | 373 | static void rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
cd4a4e53 | 374 | { |
4db35314 | 375 | struct kvm_mmu_page *sp; |
cd4a4e53 | 376 | struct kvm_rmap_desc *desc; |
290fc38d | 377 | unsigned long *rmapp; |
cd4a4e53 AK |
378 | int i; |
379 | ||
380 | if (!is_rmap_pte(*spte)) | |
381 | return; | |
290fc38d | 382 | gfn = unalias_gfn(vcpu->kvm, gfn); |
4db35314 AK |
383 | sp = page_header(__pa(spte)); |
384 | sp->gfns[spte - sp->spt] = gfn; | |
290fc38d IE |
385 | rmapp = gfn_to_rmap(vcpu->kvm, gfn); |
386 | if (!*rmapp) { | |
cd4a4e53 | 387 | rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte); |
290fc38d IE |
388 | *rmapp = (unsigned long)spte; |
389 | } else if (!(*rmapp & 1)) { | |
cd4a4e53 | 390 | rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte); |
714b93da | 391 | desc = mmu_alloc_rmap_desc(vcpu); |
290fc38d | 392 | desc->shadow_ptes[0] = (u64 *)*rmapp; |
cd4a4e53 | 393 | desc->shadow_ptes[1] = spte; |
290fc38d | 394 | *rmapp = (unsigned long)desc | 1; |
cd4a4e53 AK |
395 | } else { |
396 | rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte); | |
290fc38d | 397 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
cd4a4e53 AK |
398 | while (desc->shadow_ptes[RMAP_EXT-1] && desc->more) |
399 | desc = desc->more; | |
400 | if (desc->shadow_ptes[RMAP_EXT-1]) { | |
714b93da | 401 | desc->more = mmu_alloc_rmap_desc(vcpu); |
cd4a4e53 AK |
402 | desc = desc->more; |
403 | } | |
404 | for (i = 0; desc->shadow_ptes[i]; ++i) | |
405 | ; | |
406 | desc->shadow_ptes[i] = spte; | |
407 | } | |
408 | } | |
409 | ||
290fc38d | 410 | static void rmap_desc_remove_entry(unsigned long *rmapp, |
cd4a4e53 AK |
411 | struct kvm_rmap_desc *desc, |
412 | int i, | |
413 | struct kvm_rmap_desc *prev_desc) | |
414 | { | |
415 | int j; | |
416 | ||
417 | for (j = RMAP_EXT - 1; !desc->shadow_ptes[j] && j > i; --j) | |
418 | ; | |
419 | desc->shadow_ptes[i] = desc->shadow_ptes[j]; | |
11718b4d | 420 | desc->shadow_ptes[j] = NULL; |
cd4a4e53 AK |
421 | if (j != 0) |
422 | return; | |
423 | if (!prev_desc && !desc->more) | |
290fc38d | 424 | *rmapp = (unsigned long)desc->shadow_ptes[0]; |
cd4a4e53 AK |
425 | else |
426 | if (prev_desc) | |
427 | prev_desc->more = desc->more; | |
428 | else | |
290fc38d | 429 | *rmapp = (unsigned long)desc->more | 1; |
90cb0529 | 430 | mmu_free_rmap_desc(desc); |
cd4a4e53 AK |
431 | } |
432 | ||
290fc38d | 433 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
cd4a4e53 | 434 | { |
cd4a4e53 AK |
435 | struct kvm_rmap_desc *desc; |
436 | struct kvm_rmap_desc *prev_desc; | |
4db35314 | 437 | struct kvm_mmu_page *sp; |
76c35c6e | 438 | struct page *page; |
290fc38d | 439 | unsigned long *rmapp; |
cd4a4e53 AK |
440 | int i; |
441 | ||
442 | if (!is_rmap_pte(*spte)) | |
443 | return; | |
4db35314 | 444 | sp = page_header(__pa(spte)); |
76c35c6e | 445 | page = pfn_to_page((*spte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT); |
448353ca | 446 | mark_page_accessed(page); |
b4231d61 | 447 | if (is_writeble_pte(*spte)) |
76c35c6e | 448 | kvm_release_page_dirty(page); |
b4231d61 | 449 | else |
76c35c6e | 450 | kvm_release_page_clean(page); |
4db35314 | 451 | rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt]); |
290fc38d | 452 | if (!*rmapp) { |
cd4a4e53 AK |
453 | printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte); |
454 | BUG(); | |
290fc38d | 455 | } else if (!(*rmapp & 1)) { |
cd4a4e53 | 456 | rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte); |
290fc38d | 457 | if ((u64 *)*rmapp != spte) { |
cd4a4e53 AK |
458 | printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n", |
459 | spte, *spte); | |
460 | BUG(); | |
461 | } | |
290fc38d | 462 | *rmapp = 0; |
cd4a4e53 AK |
463 | } else { |
464 | rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte); | |
290fc38d | 465 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
cd4a4e53 AK |
466 | prev_desc = NULL; |
467 | while (desc) { | |
468 | for (i = 0; i < RMAP_EXT && desc->shadow_ptes[i]; ++i) | |
469 | if (desc->shadow_ptes[i] == spte) { | |
290fc38d | 470 | rmap_desc_remove_entry(rmapp, |
714b93da | 471 | desc, i, |
cd4a4e53 AK |
472 | prev_desc); |
473 | return; | |
474 | } | |
475 | prev_desc = desc; | |
476 | desc = desc->more; | |
477 | } | |
478 | BUG(); | |
479 | } | |
480 | } | |
481 | ||
98348e95 | 482 | static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte) |
374cbac0 | 483 | { |
374cbac0 | 484 | struct kvm_rmap_desc *desc; |
98348e95 IE |
485 | struct kvm_rmap_desc *prev_desc; |
486 | u64 *prev_spte; | |
487 | int i; | |
488 | ||
489 | if (!*rmapp) | |
490 | return NULL; | |
491 | else if (!(*rmapp & 1)) { | |
492 | if (!spte) | |
493 | return (u64 *)*rmapp; | |
494 | return NULL; | |
495 | } | |
496 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); | |
497 | prev_desc = NULL; | |
498 | prev_spte = NULL; | |
499 | while (desc) { | |
500 | for (i = 0; i < RMAP_EXT && desc->shadow_ptes[i]; ++i) { | |
501 | if (prev_spte == spte) | |
502 | return desc->shadow_ptes[i]; | |
503 | prev_spte = desc->shadow_ptes[i]; | |
504 | } | |
505 | desc = desc->more; | |
506 | } | |
507 | return NULL; | |
508 | } | |
509 | ||
510 | static void rmap_write_protect(struct kvm *kvm, u64 gfn) | |
511 | { | |
290fc38d | 512 | unsigned long *rmapp; |
374cbac0 | 513 | u64 *spte; |
caa5b8a5 | 514 | int write_protected = 0; |
374cbac0 | 515 | |
4a4c9924 AL |
516 | gfn = unalias_gfn(kvm, gfn); |
517 | rmapp = gfn_to_rmap(kvm, gfn); | |
374cbac0 | 518 | |
98348e95 IE |
519 | spte = rmap_next(kvm, rmapp, NULL); |
520 | while (spte) { | |
374cbac0 | 521 | BUG_ON(!spte); |
374cbac0 | 522 | BUG_ON(!(*spte & PT_PRESENT_MASK)); |
374cbac0 | 523 | rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte); |
caa5b8a5 | 524 | if (is_writeble_pte(*spte)) { |
9647c14c | 525 | set_shadow_pte(spte, *spte & ~PT_WRITABLE_MASK); |
caa5b8a5 ED |
526 | write_protected = 1; |
527 | } | |
9647c14c | 528 | spte = rmap_next(kvm, rmapp, spte); |
374cbac0 | 529 | } |
caa5b8a5 ED |
530 | if (write_protected) |
531 | kvm_flush_remote_tlbs(kvm); | |
374cbac0 AK |
532 | } |
533 | ||
d6c69ee9 | 534 | #ifdef MMU_DEBUG |
47ad8e68 | 535 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 536 | { |
139bdb2d AK |
537 | u64 *pos; |
538 | u64 *end; | |
539 | ||
47ad8e68 | 540 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
c7addb90 | 541 | if ((*pos & ~PT_SHADOW_IO_MARK) != shadow_trap_nonpresent_pte) { |
139bdb2d AK |
542 | printk(KERN_ERR "%s: %p %llx\n", __FUNCTION__, |
543 | pos, *pos); | |
6aa8b732 | 544 | return 0; |
139bdb2d | 545 | } |
6aa8b732 AK |
546 | return 1; |
547 | } | |
d6c69ee9 | 548 | #endif |
6aa8b732 | 549 | |
4db35314 | 550 | static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
260746c0 | 551 | { |
4db35314 AK |
552 | ASSERT(is_empty_shadow_page(sp->spt)); |
553 | list_del(&sp->link); | |
554 | __free_page(virt_to_page(sp->spt)); | |
555 | __free_page(virt_to_page(sp->gfns)); | |
556 | kfree(sp); | |
f05e70ac | 557 | ++kvm->arch.n_free_mmu_pages; |
260746c0 AK |
558 | } |
559 | ||
cea0f0e7 AK |
560 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
561 | { | |
562 | return gfn; | |
563 | } | |
564 | ||
25c0de2c AK |
565 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
566 | u64 *parent_pte) | |
6aa8b732 | 567 | { |
4db35314 | 568 | struct kvm_mmu_page *sp; |
6aa8b732 | 569 | |
ad312c7c ZX |
570 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp); |
571 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE); | |
572 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE); | |
4db35314 | 573 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
f05e70ac | 574 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
4db35314 AK |
575 | ASSERT(is_empty_shadow_page(sp->spt)); |
576 | sp->slot_bitmap = 0; | |
577 | sp->multimapped = 0; | |
578 | sp->parent_pte = parent_pte; | |
f05e70ac | 579 | --vcpu->kvm->arch.n_free_mmu_pages; |
4db35314 | 580 | return sp; |
6aa8b732 AK |
581 | } |
582 | ||
714b93da | 583 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 584 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 AK |
585 | { |
586 | struct kvm_pte_chain *pte_chain; | |
587 | struct hlist_node *node; | |
588 | int i; | |
589 | ||
590 | if (!parent_pte) | |
591 | return; | |
4db35314 AK |
592 | if (!sp->multimapped) { |
593 | u64 *old = sp->parent_pte; | |
cea0f0e7 AK |
594 | |
595 | if (!old) { | |
4db35314 | 596 | sp->parent_pte = parent_pte; |
cea0f0e7 AK |
597 | return; |
598 | } | |
4db35314 | 599 | sp->multimapped = 1; |
714b93da | 600 | pte_chain = mmu_alloc_pte_chain(vcpu); |
4db35314 AK |
601 | INIT_HLIST_HEAD(&sp->parent_ptes); |
602 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); | |
cea0f0e7 AK |
603 | pte_chain->parent_ptes[0] = old; |
604 | } | |
4db35314 | 605 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) { |
cea0f0e7 AK |
606 | if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1]) |
607 | continue; | |
608 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) | |
609 | if (!pte_chain->parent_ptes[i]) { | |
610 | pte_chain->parent_ptes[i] = parent_pte; | |
611 | return; | |
612 | } | |
613 | } | |
714b93da | 614 | pte_chain = mmu_alloc_pte_chain(vcpu); |
cea0f0e7 | 615 | BUG_ON(!pte_chain); |
4db35314 | 616 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); |
cea0f0e7 AK |
617 | pte_chain->parent_ptes[0] = parent_pte; |
618 | } | |
619 | ||
4db35314 | 620 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
621 | u64 *parent_pte) |
622 | { | |
623 | struct kvm_pte_chain *pte_chain; | |
624 | struct hlist_node *node; | |
625 | int i; | |
626 | ||
4db35314 AK |
627 | if (!sp->multimapped) { |
628 | BUG_ON(sp->parent_pte != parent_pte); | |
629 | sp->parent_pte = NULL; | |
cea0f0e7 AK |
630 | return; |
631 | } | |
4db35314 | 632 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) |
cea0f0e7 AK |
633 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { |
634 | if (!pte_chain->parent_ptes[i]) | |
635 | break; | |
636 | if (pte_chain->parent_ptes[i] != parent_pte) | |
637 | continue; | |
697fe2e2 AK |
638 | while (i + 1 < NR_PTE_CHAIN_ENTRIES |
639 | && pte_chain->parent_ptes[i + 1]) { | |
cea0f0e7 AK |
640 | pte_chain->parent_ptes[i] |
641 | = pte_chain->parent_ptes[i + 1]; | |
642 | ++i; | |
643 | } | |
644 | pte_chain->parent_ptes[i] = NULL; | |
697fe2e2 AK |
645 | if (i == 0) { |
646 | hlist_del(&pte_chain->link); | |
90cb0529 | 647 | mmu_free_pte_chain(pte_chain); |
4db35314 AK |
648 | if (hlist_empty(&sp->parent_ptes)) { |
649 | sp->multimapped = 0; | |
650 | sp->parent_pte = NULL; | |
697fe2e2 AK |
651 | } |
652 | } | |
cea0f0e7 AK |
653 | return; |
654 | } | |
655 | BUG(); | |
656 | } | |
657 | ||
4db35314 | 658 | static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn) |
cea0f0e7 AK |
659 | { |
660 | unsigned index; | |
661 | struct hlist_head *bucket; | |
4db35314 | 662 | struct kvm_mmu_page *sp; |
cea0f0e7 AK |
663 | struct hlist_node *node; |
664 | ||
665 | pgprintk("%s: looking for gfn %lx\n", __FUNCTION__, gfn); | |
666 | index = kvm_page_table_hashfn(gfn) % KVM_NUM_MMU_PAGES; | |
f05e70ac | 667 | bucket = &kvm->arch.mmu_page_hash[index]; |
4db35314 AK |
668 | hlist_for_each_entry(sp, node, bucket, hash_link) |
669 | if (sp->gfn == gfn && !sp->role.metaphysical) { | |
cea0f0e7 | 670 | pgprintk("%s: found role %x\n", |
4db35314 AK |
671 | __FUNCTION__, sp->role.word); |
672 | return sp; | |
cea0f0e7 AK |
673 | } |
674 | return NULL; | |
675 | } | |
676 | ||
677 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, | |
678 | gfn_t gfn, | |
679 | gva_t gaddr, | |
680 | unsigned level, | |
681 | int metaphysical, | |
41074d07 | 682 | unsigned access, |
f7d9c7b7 | 683 | u64 *parent_pte) |
cea0f0e7 AK |
684 | { |
685 | union kvm_mmu_page_role role; | |
686 | unsigned index; | |
687 | unsigned quadrant; | |
688 | struct hlist_head *bucket; | |
4db35314 | 689 | struct kvm_mmu_page *sp; |
cea0f0e7 AK |
690 | struct hlist_node *node; |
691 | ||
692 | role.word = 0; | |
ad312c7c | 693 | role.glevels = vcpu->arch.mmu.root_level; |
cea0f0e7 AK |
694 | role.level = level; |
695 | role.metaphysical = metaphysical; | |
41074d07 | 696 | role.access = access; |
ad312c7c | 697 | if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { |
cea0f0e7 AK |
698 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
699 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
700 | role.quadrant = quadrant; | |
701 | } | |
702 | pgprintk("%s: looking gfn %lx role %x\n", __FUNCTION__, | |
703 | gfn, role.word); | |
704 | index = kvm_page_table_hashfn(gfn) % KVM_NUM_MMU_PAGES; | |
f05e70ac | 705 | bucket = &vcpu->kvm->arch.mmu_page_hash[index]; |
4db35314 AK |
706 | hlist_for_each_entry(sp, node, bucket, hash_link) |
707 | if (sp->gfn == gfn && sp->role.word == role.word) { | |
708 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); | |
cea0f0e7 | 709 | pgprintk("%s: found\n", __FUNCTION__); |
4db35314 | 710 | return sp; |
cea0f0e7 | 711 | } |
dfc5aa00 | 712 | ++vcpu->kvm->stat.mmu_cache_miss; |
4db35314 AK |
713 | sp = kvm_mmu_alloc_page(vcpu, parent_pte); |
714 | if (!sp) | |
715 | return sp; | |
cea0f0e7 | 716 | pgprintk("%s: adding gfn %lx role %x\n", __FUNCTION__, gfn, role.word); |
4db35314 AK |
717 | sp->gfn = gfn; |
718 | sp->role = role; | |
719 | hlist_add_head(&sp->hash_link, bucket); | |
ad312c7c | 720 | vcpu->arch.mmu.prefetch_page(vcpu, sp); |
374cbac0 | 721 | if (!metaphysical) |
4a4c9924 | 722 | rmap_write_protect(vcpu->kvm, gfn); |
4db35314 | 723 | return sp; |
cea0f0e7 AK |
724 | } |
725 | ||
90cb0529 | 726 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 727 | struct kvm_mmu_page *sp) |
a436036b | 728 | { |
697fe2e2 AK |
729 | unsigned i; |
730 | u64 *pt; | |
731 | u64 ent; | |
732 | ||
4db35314 | 733 | pt = sp->spt; |
697fe2e2 | 734 | |
4db35314 | 735 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { |
697fe2e2 | 736 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { |
c7addb90 | 737 | if (is_shadow_present_pte(pt[i])) |
290fc38d | 738 | rmap_remove(kvm, &pt[i]); |
c7addb90 | 739 | pt[i] = shadow_trap_nonpresent_pte; |
697fe2e2 | 740 | } |
90cb0529 | 741 | kvm_flush_remote_tlbs(kvm); |
697fe2e2 AK |
742 | return; |
743 | } | |
744 | ||
745 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
746 | ent = pt[i]; | |
747 | ||
c7addb90 AK |
748 | pt[i] = shadow_trap_nonpresent_pte; |
749 | if (!is_shadow_present_pte(ent)) | |
697fe2e2 AK |
750 | continue; |
751 | ent &= PT64_BASE_ADDR_MASK; | |
90cb0529 | 752 | mmu_page_remove_parent_pte(page_header(ent), &pt[i]); |
697fe2e2 | 753 | } |
90cb0529 | 754 | kvm_flush_remote_tlbs(kvm); |
a436036b AK |
755 | } |
756 | ||
4db35314 | 757 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 758 | { |
4db35314 | 759 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
760 | } |
761 | ||
12b7d28f AK |
762 | static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm) |
763 | { | |
764 | int i; | |
765 | ||
766 | for (i = 0; i < KVM_MAX_VCPUS; ++i) | |
767 | if (kvm->vcpus[i]) | |
ad312c7c | 768 | kvm->vcpus[i]->arch.last_pte_updated = NULL; |
12b7d28f AK |
769 | } |
770 | ||
4db35314 | 771 | static void kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b AK |
772 | { |
773 | u64 *parent_pte; | |
774 | ||
4cee5764 | 775 | ++kvm->stat.mmu_shadow_zapped; |
4db35314 AK |
776 | while (sp->multimapped || sp->parent_pte) { |
777 | if (!sp->multimapped) | |
778 | parent_pte = sp->parent_pte; | |
a436036b AK |
779 | else { |
780 | struct kvm_pte_chain *chain; | |
781 | ||
4db35314 | 782 | chain = container_of(sp->parent_ptes.first, |
a436036b AK |
783 | struct kvm_pte_chain, link); |
784 | parent_pte = chain->parent_ptes[0]; | |
785 | } | |
697fe2e2 | 786 | BUG_ON(!parent_pte); |
4db35314 | 787 | kvm_mmu_put_page(sp, parent_pte); |
c7addb90 | 788 | set_shadow_pte(parent_pte, shadow_trap_nonpresent_pte); |
a436036b | 789 | } |
4db35314 AK |
790 | kvm_mmu_page_unlink_children(kvm, sp); |
791 | if (!sp->root_count) { | |
792 | hlist_del(&sp->hash_link); | |
793 | kvm_mmu_free_page(kvm, sp); | |
36868f7b | 794 | } else |
f05e70ac | 795 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
12b7d28f | 796 | kvm_mmu_reset_last_pte_updated(kvm); |
a436036b AK |
797 | } |
798 | ||
82ce2c96 IE |
799 | /* |
800 | * Changing the number of mmu pages allocated to the vm | |
801 | * Note: if kvm_nr_mmu_pages is too small, you will get dead lock | |
802 | */ | |
803 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages) | |
804 | { | |
805 | /* | |
806 | * If we set the number of mmu pages to be smaller be than the | |
807 | * number of actived pages , we must to free some mmu pages before we | |
808 | * change the value | |
809 | */ | |
810 | ||
f05e70ac | 811 | if ((kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages) > |
82ce2c96 | 812 | kvm_nr_mmu_pages) { |
f05e70ac ZX |
813 | int n_used_mmu_pages = kvm->arch.n_alloc_mmu_pages |
814 | - kvm->arch.n_free_mmu_pages; | |
82ce2c96 IE |
815 | |
816 | while (n_used_mmu_pages > kvm_nr_mmu_pages) { | |
817 | struct kvm_mmu_page *page; | |
818 | ||
f05e70ac | 819 | page = container_of(kvm->arch.active_mmu_pages.prev, |
82ce2c96 IE |
820 | struct kvm_mmu_page, link); |
821 | kvm_mmu_zap_page(kvm, page); | |
822 | n_used_mmu_pages--; | |
823 | } | |
f05e70ac | 824 | kvm->arch.n_free_mmu_pages = 0; |
82ce2c96 IE |
825 | } |
826 | else | |
f05e70ac ZX |
827 | kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages |
828 | - kvm->arch.n_alloc_mmu_pages; | |
82ce2c96 | 829 | |
f05e70ac | 830 | kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages; |
82ce2c96 IE |
831 | } |
832 | ||
f67a46f4 | 833 | static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b AK |
834 | { |
835 | unsigned index; | |
836 | struct hlist_head *bucket; | |
4db35314 | 837 | struct kvm_mmu_page *sp; |
a436036b AK |
838 | struct hlist_node *node, *n; |
839 | int r; | |
840 | ||
841 | pgprintk("%s: looking for gfn %lx\n", __FUNCTION__, gfn); | |
842 | r = 0; | |
843 | index = kvm_page_table_hashfn(gfn) % KVM_NUM_MMU_PAGES; | |
f05e70ac | 844 | bucket = &kvm->arch.mmu_page_hash[index]; |
4db35314 AK |
845 | hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) |
846 | if (sp->gfn == gfn && !sp->role.metaphysical) { | |
697fe2e2 | 847 | pgprintk("%s: gfn %lx role %x\n", __FUNCTION__, gfn, |
4db35314 AK |
848 | sp->role.word); |
849 | kvm_mmu_zap_page(kvm, sp); | |
a436036b AK |
850 | r = 1; |
851 | } | |
852 | return r; | |
cea0f0e7 AK |
853 | } |
854 | ||
f67a46f4 | 855 | static void mmu_unshadow(struct kvm *kvm, gfn_t gfn) |
97a0a01e | 856 | { |
4db35314 | 857 | struct kvm_mmu_page *sp; |
97a0a01e | 858 | |
4db35314 AK |
859 | while ((sp = kvm_mmu_lookup_page(kvm, gfn)) != NULL) { |
860 | pgprintk("%s: zap %lx %x\n", __FUNCTION__, gfn, sp->role.word); | |
861 | kvm_mmu_zap_page(kvm, sp); | |
97a0a01e AK |
862 | } |
863 | } | |
864 | ||
38c335f1 | 865 | static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn) |
6aa8b732 | 866 | { |
38c335f1 | 867 | int slot = memslot_id(kvm, gfn_to_memslot(kvm, gfn)); |
4db35314 | 868 | struct kvm_mmu_page *sp = page_header(__pa(pte)); |
6aa8b732 | 869 | |
4db35314 | 870 | __set_bit(slot, &sp->slot_bitmap); |
6aa8b732 AK |
871 | } |
872 | ||
039576c0 AK |
873 | struct page *gva_to_page(struct kvm_vcpu *vcpu, gva_t gva) |
874 | { | |
72dc67a6 IE |
875 | struct page *page; |
876 | ||
ad312c7c | 877 | gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva); |
039576c0 AK |
878 | |
879 | if (gpa == UNMAPPED_GVA) | |
880 | return NULL; | |
72dc67a6 IE |
881 | |
882 | down_read(¤t->mm->mmap_sem); | |
883 | page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); | |
884 | up_read(¤t->mm->mmap_sem); | |
885 | ||
886 | return page; | |
039576c0 AK |
887 | } |
888 | ||
1c4f1fd6 AK |
889 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *shadow_pte, |
890 | unsigned pt_access, unsigned pte_access, | |
891 | int user_fault, int write_fault, int dirty, | |
d7824fff | 892 | int *ptwrite, gfn_t gfn, struct page *page) |
1c4f1fd6 AK |
893 | { |
894 | u64 spte; | |
15aaa819 | 895 | int was_rmapped = 0; |
75e68e60 | 896 | int was_writeble = is_writeble_pte(*shadow_pte); |
15aaa819 | 897 | hfn_t host_pfn = (*shadow_pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
1c4f1fd6 | 898 | |
bc750ba8 | 899 | pgprintk("%s: spte %llx access %x write_fault %d" |
1c4f1fd6 | 900 | " user_fault %d gfn %lx\n", |
bc750ba8 | 901 | __FUNCTION__, *shadow_pte, pt_access, |
1c4f1fd6 AK |
902 | write_fault, user_fault, gfn); |
903 | ||
15aaa819 MT |
904 | if (is_rmap_pte(*shadow_pte)) { |
905 | if (host_pfn != page_to_pfn(page)) { | |
906 | pgprintk("hfn old %lx new %lx\n", | |
907 | host_pfn, page_to_pfn(page)); | |
908 | rmap_remove(vcpu->kvm, shadow_pte); | |
909 | } | |
910 | else | |
911 | was_rmapped = 1; | |
912 | } | |
913 | ||
1c4f1fd6 AK |
914 | /* |
915 | * We don't set the accessed bit, since we sometimes want to see | |
916 | * whether the guest actually used the pte (in order to detect | |
917 | * demand paging). | |
918 | */ | |
919 | spte = PT_PRESENT_MASK | PT_DIRTY_MASK; | |
920 | if (!dirty) | |
921 | pte_access &= ~ACC_WRITE_MASK; | |
922 | if (!(pte_access & ACC_EXEC_MASK)) | |
923 | spte |= PT64_NX_MASK; | |
924 | ||
1c4f1fd6 AK |
925 | spte |= PT_PRESENT_MASK; |
926 | if (pte_access & ACC_USER_MASK) | |
927 | spte |= PT_USER_MASK; | |
928 | ||
929 | if (is_error_page(page)) { | |
930 | set_shadow_pte(shadow_pte, | |
931 | shadow_trap_nonpresent_pte | PT_SHADOW_IO_MARK); | |
932 | kvm_release_page_clean(page); | |
933 | return; | |
934 | } | |
935 | ||
936 | spte |= page_to_phys(page); | |
937 | ||
938 | if ((pte_access & ACC_WRITE_MASK) | |
939 | || (write_fault && !is_write_protection(vcpu) && !user_fault)) { | |
940 | struct kvm_mmu_page *shadow; | |
941 | ||
942 | spte |= PT_WRITABLE_MASK; | |
943 | if (user_fault) { | |
944 | mmu_unshadow(vcpu->kvm, gfn); | |
945 | goto unshadowed; | |
946 | } | |
947 | ||
948 | shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn); | |
949 | if (shadow) { | |
950 | pgprintk("%s: found shadow page for %lx, marking ro\n", | |
951 | __FUNCTION__, gfn); | |
952 | pte_access &= ~ACC_WRITE_MASK; | |
953 | if (is_writeble_pte(spte)) { | |
954 | spte &= ~PT_WRITABLE_MASK; | |
955 | kvm_x86_ops->tlb_flush(vcpu); | |
956 | } | |
957 | if (write_fault) | |
958 | *ptwrite = 1; | |
959 | } | |
960 | } | |
961 | ||
962 | unshadowed: | |
963 | ||
964 | if (pte_access & ACC_WRITE_MASK) | |
965 | mark_page_dirty(vcpu->kvm, gfn); | |
966 | ||
967 | pgprintk("%s: setting spte %llx\n", __FUNCTION__, spte); | |
968 | set_shadow_pte(shadow_pte, spte); | |
969 | page_header_update_slot(vcpu->kvm, shadow_pte, gfn); | |
970 | if (!was_rmapped) { | |
971 | rmap_add(vcpu, shadow_pte, gfn); | |
972 | if (!is_rmap_pte(*shadow_pte)) | |
973 | kvm_release_page_clean(page); | |
75e68e60 IE |
974 | } else { |
975 | if (was_writeble) | |
976 | kvm_release_page_dirty(page); | |
977 | else | |
978 | kvm_release_page_clean(page); | |
1c4f1fd6 | 979 | } |
1c4f1fd6 | 980 | if (!ptwrite || !*ptwrite) |
ad312c7c | 981 | vcpu->arch.last_pte_updated = shadow_pte; |
1c4f1fd6 AK |
982 | } |
983 | ||
6aa8b732 AK |
984 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
985 | { | |
986 | } | |
987 | ||
aaee2c94 MT |
988 | static int __nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, |
989 | gfn_t gfn, struct page *page) | |
6aa8b732 AK |
990 | { |
991 | int level = PT32E_ROOT_LEVEL; | |
ad312c7c | 992 | hpa_t table_addr = vcpu->arch.mmu.root_hpa; |
e833240f | 993 | int pt_write = 0; |
6aa8b732 AK |
994 | |
995 | for (; ; level--) { | |
996 | u32 index = PT64_INDEX(v, level); | |
997 | u64 *table; | |
998 | ||
999 | ASSERT(VALID_PAGE(table_addr)); | |
1000 | table = __va(table_addr); | |
1001 | ||
1002 | if (level == 1) { | |
e833240f | 1003 | mmu_set_spte(vcpu, &table[index], ACC_ALL, ACC_ALL, |
d7824fff | 1004 | 0, write, 1, &pt_write, gfn, page); |
e833240f | 1005 | return pt_write || is_io_pte(table[index]); |
6aa8b732 AK |
1006 | } |
1007 | ||
c7addb90 | 1008 | if (table[index] == shadow_trap_nonpresent_pte) { |
25c0de2c | 1009 | struct kvm_mmu_page *new_table; |
cea0f0e7 | 1010 | gfn_t pseudo_gfn; |
6aa8b732 | 1011 | |
cea0f0e7 AK |
1012 | pseudo_gfn = (v & PT64_DIR_BASE_ADDR_MASK) |
1013 | >> PAGE_SHIFT; | |
1014 | new_table = kvm_mmu_get_page(vcpu, pseudo_gfn, | |
1015 | v, level - 1, | |
f7d9c7b7 | 1016 | 1, ACC_ALL, &table[index]); |
25c0de2c | 1017 | if (!new_table) { |
6aa8b732 | 1018 | pgprintk("nonpaging_map: ENOMEM\n"); |
d7824fff | 1019 | kvm_release_page_clean(page); |
6aa8b732 AK |
1020 | return -ENOMEM; |
1021 | } | |
1022 | ||
47ad8e68 | 1023 | table[index] = __pa(new_table->spt) | PT_PRESENT_MASK |
25c0de2c | 1024 | | PT_WRITABLE_MASK | PT_USER_MASK; |
6aa8b732 AK |
1025 | } |
1026 | table_addr = table[index] & PT64_BASE_ADDR_MASK; | |
1027 | } | |
1028 | } | |
1029 | ||
10589a46 MT |
1030 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn) |
1031 | { | |
1032 | int r; | |
1033 | ||
aaee2c94 MT |
1034 | struct page *page; |
1035 | ||
72dc67a6 IE |
1036 | down_read(&vcpu->kvm->slots_lock); |
1037 | ||
aaee2c94 MT |
1038 | down_read(¤t->mm->mmap_sem); |
1039 | page = gfn_to_page(vcpu->kvm, gfn); | |
72dc67a6 | 1040 | up_read(¤t->mm->mmap_sem); |
aaee2c94 MT |
1041 | |
1042 | spin_lock(&vcpu->kvm->mmu_lock); | |
eb787d10 | 1043 | kvm_mmu_free_some_pages(vcpu); |
aaee2c94 MT |
1044 | r = __nonpaging_map(vcpu, v, write, gfn, page); |
1045 | spin_unlock(&vcpu->kvm->mmu_lock); | |
1046 | ||
72dc67a6 | 1047 | up_read(&vcpu->kvm->slots_lock); |
aaee2c94 | 1048 | |
10589a46 MT |
1049 | return r; |
1050 | } | |
1051 | ||
1052 | ||
c7addb90 AK |
1053 | static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu, |
1054 | struct kvm_mmu_page *sp) | |
1055 | { | |
1056 | int i; | |
1057 | ||
1058 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1059 | sp->spt[i] = shadow_trap_nonpresent_pte; | |
1060 | } | |
1061 | ||
17ac10ad AK |
1062 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
1063 | { | |
1064 | int i; | |
4db35314 | 1065 | struct kvm_mmu_page *sp; |
17ac10ad | 1066 | |
ad312c7c | 1067 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 1068 | return; |
aaee2c94 | 1069 | spin_lock(&vcpu->kvm->mmu_lock); |
17ac10ad | 1070 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
1071 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { |
1072 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
17ac10ad | 1073 | |
4db35314 AK |
1074 | sp = page_header(root); |
1075 | --sp->root_count; | |
ad312c7c | 1076 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
aaee2c94 | 1077 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad AK |
1078 | return; |
1079 | } | |
1080 | #endif | |
1081 | for (i = 0; i < 4; ++i) { | |
ad312c7c | 1082 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 1083 | |
417726a3 | 1084 | if (root) { |
417726a3 | 1085 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
1086 | sp = page_header(root); |
1087 | --sp->root_count; | |
417726a3 | 1088 | } |
ad312c7c | 1089 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 1090 | } |
aaee2c94 | 1091 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 1092 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
1093 | } |
1094 | ||
1095 | static void mmu_alloc_roots(struct kvm_vcpu *vcpu) | |
1096 | { | |
1097 | int i; | |
cea0f0e7 | 1098 | gfn_t root_gfn; |
4db35314 | 1099 | struct kvm_mmu_page *sp; |
3bb65a22 | 1100 | |
ad312c7c | 1101 | root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT; |
17ac10ad AK |
1102 | |
1103 | #ifdef CONFIG_X86_64 | |
ad312c7c ZX |
1104 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { |
1105 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
17ac10ad AK |
1106 | |
1107 | ASSERT(!VALID_PAGE(root)); | |
4db35314 | 1108 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, |
f7d9c7b7 | 1109 | PT64_ROOT_LEVEL, 0, ACC_ALL, NULL); |
4db35314 AK |
1110 | root = __pa(sp->spt); |
1111 | ++sp->root_count; | |
ad312c7c | 1112 | vcpu->arch.mmu.root_hpa = root; |
17ac10ad AK |
1113 | return; |
1114 | } | |
1115 | #endif | |
1116 | for (i = 0; i < 4; ++i) { | |
ad312c7c | 1117 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
1118 | |
1119 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c ZX |
1120 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
1121 | if (!is_present_pte(vcpu->arch.pdptrs[i])) { | |
1122 | vcpu->arch.mmu.pae_root[i] = 0; | |
417726a3 AK |
1123 | continue; |
1124 | } | |
ad312c7c ZX |
1125 | root_gfn = vcpu->arch.pdptrs[i] >> PAGE_SHIFT; |
1126 | } else if (vcpu->arch.mmu.root_level == 0) | |
cea0f0e7 | 1127 | root_gfn = 0; |
4db35314 AK |
1128 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
1129 | PT32_ROOT_LEVEL, !is_paging(vcpu), | |
f7d9c7b7 | 1130 | ACC_ALL, NULL); |
4db35314 AK |
1131 | root = __pa(sp->spt); |
1132 | ++sp->root_count; | |
ad312c7c | 1133 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; |
17ac10ad | 1134 | } |
ad312c7c | 1135 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
17ac10ad AK |
1136 | } |
1137 | ||
6aa8b732 AK |
1138 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr) |
1139 | { | |
1140 | return vaddr; | |
1141 | } | |
1142 | ||
1143 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, | |
3f3e7124 | 1144 | u32 error_code) |
6aa8b732 | 1145 | { |
e833240f | 1146 | gfn_t gfn; |
e2dec939 | 1147 | int r; |
6aa8b732 | 1148 | |
e833240f | 1149 | pgprintk("%s: gva %lx error %x\n", __FUNCTION__, gva, error_code); |
e2dec939 AK |
1150 | r = mmu_topup_memory_caches(vcpu); |
1151 | if (r) | |
1152 | return r; | |
714b93da | 1153 | |
6aa8b732 | 1154 | ASSERT(vcpu); |
ad312c7c | 1155 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 1156 | |
e833240f | 1157 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 1158 | |
e833240f AK |
1159 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
1160 | error_code & PFERR_WRITE_MASK, gfn); | |
6aa8b732 AK |
1161 | } |
1162 | ||
6aa8b732 AK |
1163 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
1164 | { | |
17ac10ad | 1165 | mmu_free_roots(vcpu); |
6aa8b732 AK |
1166 | } |
1167 | ||
1168 | static int nonpaging_init_context(struct kvm_vcpu *vcpu) | |
1169 | { | |
ad312c7c | 1170 | struct kvm_mmu *context = &vcpu->arch.mmu; |
6aa8b732 AK |
1171 | |
1172 | context->new_cr3 = nonpaging_new_cr3; | |
1173 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
1174 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
1175 | context->free = nonpaging_free; | |
c7addb90 | 1176 | context->prefetch_page = nonpaging_prefetch_page; |
cea0f0e7 | 1177 | context->root_level = 0; |
6aa8b732 | 1178 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 1179 | context->root_hpa = INVALID_PAGE; |
6aa8b732 AK |
1180 | return 0; |
1181 | } | |
1182 | ||
d835dfec | 1183 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 1184 | { |
1165f5fe | 1185 | ++vcpu->stat.tlb_flush; |
cbdd1bea | 1186 | kvm_x86_ops->tlb_flush(vcpu); |
6aa8b732 AK |
1187 | } |
1188 | ||
1189 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
1190 | { | |
24993d53 | 1191 | pgprintk("%s: cr3 %lx\n", __FUNCTION__, vcpu->arch.cr3); |
cea0f0e7 | 1192 | mmu_free_roots(vcpu); |
6aa8b732 AK |
1193 | } |
1194 | ||
6aa8b732 AK |
1195 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
1196 | u64 addr, | |
1197 | u32 err_code) | |
1198 | { | |
c3c91fee | 1199 | kvm_inject_page_fault(vcpu, addr, err_code); |
6aa8b732 AK |
1200 | } |
1201 | ||
6aa8b732 AK |
1202 | static void paging_free(struct kvm_vcpu *vcpu) |
1203 | { | |
1204 | nonpaging_free(vcpu); | |
1205 | } | |
1206 | ||
1207 | #define PTTYPE 64 | |
1208 | #include "paging_tmpl.h" | |
1209 | #undef PTTYPE | |
1210 | ||
1211 | #define PTTYPE 32 | |
1212 | #include "paging_tmpl.h" | |
1213 | #undef PTTYPE | |
1214 | ||
17ac10ad | 1215 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level) |
6aa8b732 | 1216 | { |
ad312c7c | 1217 | struct kvm_mmu *context = &vcpu->arch.mmu; |
6aa8b732 AK |
1218 | |
1219 | ASSERT(is_pae(vcpu)); | |
1220 | context->new_cr3 = paging_new_cr3; | |
1221 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 1222 | context->gva_to_gpa = paging64_gva_to_gpa; |
c7addb90 | 1223 | context->prefetch_page = paging64_prefetch_page; |
6aa8b732 | 1224 | context->free = paging_free; |
17ac10ad AK |
1225 | context->root_level = level; |
1226 | context->shadow_root_level = level; | |
17c3ba9d | 1227 | context->root_hpa = INVALID_PAGE; |
6aa8b732 AK |
1228 | return 0; |
1229 | } | |
1230 | ||
17ac10ad AK |
1231 | static int paging64_init_context(struct kvm_vcpu *vcpu) |
1232 | { | |
1233 | return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL); | |
1234 | } | |
1235 | ||
6aa8b732 AK |
1236 | static int paging32_init_context(struct kvm_vcpu *vcpu) |
1237 | { | |
ad312c7c | 1238 | struct kvm_mmu *context = &vcpu->arch.mmu; |
6aa8b732 AK |
1239 | |
1240 | context->new_cr3 = paging_new_cr3; | |
1241 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
1242 | context->gva_to_gpa = paging32_gva_to_gpa; |
1243 | context->free = paging_free; | |
c7addb90 | 1244 | context->prefetch_page = paging32_prefetch_page; |
6aa8b732 AK |
1245 | context->root_level = PT32_ROOT_LEVEL; |
1246 | context->shadow_root_level = PT32E_ROOT_LEVEL; | |
17c3ba9d | 1247 | context->root_hpa = INVALID_PAGE; |
6aa8b732 AK |
1248 | return 0; |
1249 | } | |
1250 | ||
1251 | static int paging32E_init_context(struct kvm_vcpu *vcpu) | |
1252 | { | |
17ac10ad | 1253 | return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
1254 | } |
1255 | ||
1256 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) | |
1257 | { | |
1258 | ASSERT(vcpu); | |
ad312c7c | 1259 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
1260 | |
1261 | if (!is_paging(vcpu)) | |
1262 | return nonpaging_init_context(vcpu); | |
a9058ecd | 1263 | else if (is_long_mode(vcpu)) |
6aa8b732 AK |
1264 | return paging64_init_context(vcpu); |
1265 | else if (is_pae(vcpu)) | |
1266 | return paging32E_init_context(vcpu); | |
1267 | else | |
1268 | return paging32_init_context(vcpu); | |
1269 | } | |
1270 | ||
1271 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) | |
1272 | { | |
1273 | ASSERT(vcpu); | |
ad312c7c ZX |
1274 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) { |
1275 | vcpu->arch.mmu.free(vcpu); | |
1276 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; | |
6aa8b732 AK |
1277 | } |
1278 | } | |
1279 | ||
1280 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
1281 | { |
1282 | destroy_kvm_mmu(vcpu); | |
1283 | return init_kvm_mmu(vcpu); | |
1284 | } | |
8668a3c4 | 1285 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
1286 | |
1287 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 1288 | { |
714b93da AK |
1289 | int r; |
1290 | ||
e2dec939 | 1291 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
1292 | if (r) |
1293 | goto out; | |
aaee2c94 | 1294 | spin_lock(&vcpu->kvm->mmu_lock); |
eb787d10 | 1295 | kvm_mmu_free_some_pages(vcpu); |
17c3ba9d | 1296 | mmu_alloc_roots(vcpu); |
aaee2c94 | 1297 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 1298 | kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
17c3ba9d | 1299 | kvm_mmu_flush_tlb(vcpu); |
714b93da AK |
1300 | out: |
1301 | return r; | |
6aa8b732 | 1302 | } |
17c3ba9d AK |
1303 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
1304 | ||
1305 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
1306 | { | |
1307 | mmu_free_roots(vcpu); | |
1308 | } | |
6aa8b732 | 1309 | |
09072daf | 1310 | static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1311 | struct kvm_mmu_page *sp, |
ac1b714e AK |
1312 | u64 *spte) |
1313 | { | |
1314 | u64 pte; | |
1315 | struct kvm_mmu_page *child; | |
1316 | ||
1317 | pte = *spte; | |
c7addb90 | 1318 | if (is_shadow_present_pte(pte)) { |
4db35314 | 1319 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) |
290fc38d | 1320 | rmap_remove(vcpu->kvm, spte); |
ac1b714e AK |
1321 | else { |
1322 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
90cb0529 | 1323 | mmu_page_remove_parent_pte(child, spte); |
ac1b714e AK |
1324 | } |
1325 | } | |
c7addb90 | 1326 | set_shadow_pte(spte, shadow_trap_nonpresent_pte); |
ac1b714e AK |
1327 | } |
1328 | ||
0028425f | 1329 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1330 | struct kvm_mmu_page *sp, |
0028425f | 1331 | u64 *spte, |
489f1d65 | 1332 | const void *new) |
0028425f | 1333 | { |
4db35314 | 1334 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
4cee5764 | 1335 | ++vcpu->kvm->stat.mmu_pde_zapped; |
0028425f | 1336 | return; |
4cee5764 | 1337 | } |
0028425f | 1338 | |
4cee5764 | 1339 | ++vcpu->kvm->stat.mmu_pte_updated; |
4db35314 | 1340 | if (sp->role.glevels == PT32_ROOT_LEVEL) |
489f1d65 | 1341 | paging32_update_pte(vcpu, sp, spte, new); |
0028425f | 1342 | else |
489f1d65 | 1343 | paging64_update_pte(vcpu, sp, spte, new); |
0028425f AK |
1344 | } |
1345 | ||
79539cec AK |
1346 | static bool need_remote_flush(u64 old, u64 new) |
1347 | { | |
1348 | if (!is_shadow_present_pte(old)) | |
1349 | return false; | |
1350 | if (!is_shadow_present_pte(new)) | |
1351 | return true; | |
1352 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
1353 | return true; | |
1354 | old ^= PT64_NX_MASK; | |
1355 | new ^= PT64_NX_MASK; | |
1356 | return (old & ~new & PT64_PERM_MASK) != 0; | |
1357 | } | |
1358 | ||
1359 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new) | |
1360 | { | |
1361 | if (need_remote_flush(old, new)) | |
1362 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1363 | else | |
1364 | kvm_mmu_flush_tlb(vcpu); | |
1365 | } | |
1366 | ||
12b7d28f AK |
1367 | static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu) |
1368 | { | |
ad312c7c | 1369 | u64 *spte = vcpu->arch.last_pte_updated; |
12b7d28f AK |
1370 | |
1371 | return !!(spte && (*spte & PT_ACCESSED_MASK)); | |
1372 | } | |
1373 | ||
d7824fff AK |
1374 | static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
1375 | const u8 *new, int bytes) | |
1376 | { | |
1377 | gfn_t gfn; | |
1378 | int r; | |
1379 | u64 gpte = 0; | |
72dc67a6 | 1380 | struct page *page; |
d7824fff AK |
1381 | |
1382 | if (bytes != 4 && bytes != 8) | |
1383 | return; | |
1384 | ||
1385 | /* | |
1386 | * Assume that the pte write on a page table of the same type | |
1387 | * as the current vcpu paging mode. This is nearly always true | |
1388 | * (might be false while changing modes). Note it is verified later | |
1389 | * by update_pte(). | |
1390 | */ | |
1391 | if (is_pae(vcpu)) { | |
1392 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ | |
1393 | if ((bytes == 4) && (gpa % 4 == 0)) { | |
1394 | r = kvm_read_guest(vcpu->kvm, gpa & ~(u64)7, &gpte, 8); | |
1395 | if (r) | |
1396 | return; | |
1397 | memcpy((void *)&gpte + (gpa % 8), new, 4); | |
1398 | } else if ((bytes == 8) && (gpa % 8 == 0)) { | |
1399 | memcpy((void *)&gpte, new, 8); | |
1400 | } | |
1401 | } else { | |
1402 | if ((bytes == 4) && (gpa % 4 == 0)) | |
1403 | memcpy((void *)&gpte, new, 4); | |
1404 | } | |
1405 | if (!is_present_pte(gpte)) | |
1406 | return; | |
1407 | gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; | |
72dc67a6 IE |
1408 | |
1409 | down_read(¤t->mm->mmap_sem); | |
1410 | page = gfn_to_page(vcpu->kvm, gfn); | |
1411 | up_read(¤t->mm->mmap_sem); | |
1412 | ||
d7824fff | 1413 | vcpu->arch.update_pte.gfn = gfn; |
e48bb497 | 1414 | vcpu->arch.update_pte.page = page; |
d7824fff AK |
1415 | } |
1416 | ||
09072daf | 1417 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
fe551881 | 1418 | const u8 *new, int bytes) |
da4a00f0 | 1419 | { |
9b7a0325 | 1420 | gfn_t gfn = gpa >> PAGE_SHIFT; |
4db35314 | 1421 | struct kvm_mmu_page *sp; |
0e7bc4b9 | 1422 | struct hlist_node *node, *n; |
9b7a0325 AK |
1423 | struct hlist_head *bucket; |
1424 | unsigned index; | |
489f1d65 | 1425 | u64 entry, gentry; |
9b7a0325 | 1426 | u64 *spte; |
9b7a0325 | 1427 | unsigned offset = offset_in_page(gpa); |
0e7bc4b9 | 1428 | unsigned pte_size; |
9b7a0325 | 1429 | unsigned page_offset; |
0e7bc4b9 | 1430 | unsigned misaligned; |
fce0657f | 1431 | unsigned quadrant; |
9b7a0325 | 1432 | int level; |
86a5ba02 | 1433 | int flooded = 0; |
ac1b714e | 1434 | int npte; |
489f1d65 | 1435 | int r; |
9b7a0325 | 1436 | |
da4a00f0 | 1437 | pgprintk("%s: gpa %llx bytes %d\n", __FUNCTION__, gpa, bytes); |
d7824fff | 1438 | mmu_guess_page_from_pte_write(vcpu, gpa, new, bytes); |
aaee2c94 | 1439 | spin_lock(&vcpu->kvm->mmu_lock); |
eb787d10 | 1440 | kvm_mmu_free_some_pages(vcpu); |
4cee5764 | 1441 | ++vcpu->kvm->stat.mmu_pte_write; |
c7addb90 | 1442 | kvm_mmu_audit(vcpu, "pre pte write"); |
ad312c7c | 1443 | if (gfn == vcpu->arch.last_pt_write_gfn |
12b7d28f | 1444 | && !last_updated_pte_accessed(vcpu)) { |
ad312c7c ZX |
1445 | ++vcpu->arch.last_pt_write_count; |
1446 | if (vcpu->arch.last_pt_write_count >= 3) | |
86a5ba02 AK |
1447 | flooded = 1; |
1448 | } else { | |
ad312c7c ZX |
1449 | vcpu->arch.last_pt_write_gfn = gfn; |
1450 | vcpu->arch.last_pt_write_count = 1; | |
1451 | vcpu->arch.last_pte_updated = NULL; | |
86a5ba02 | 1452 | } |
9b7a0325 | 1453 | index = kvm_page_table_hashfn(gfn) % KVM_NUM_MMU_PAGES; |
f05e70ac | 1454 | bucket = &vcpu->kvm->arch.mmu_page_hash[index]; |
4db35314 AK |
1455 | hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) { |
1456 | if (sp->gfn != gfn || sp->role.metaphysical) | |
9b7a0325 | 1457 | continue; |
4db35314 | 1458 | pte_size = sp->role.glevels == PT32_ROOT_LEVEL ? 4 : 8; |
0e7bc4b9 | 1459 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
e925c5ba | 1460 | misaligned |= bytes < 4; |
86a5ba02 | 1461 | if (misaligned || flooded) { |
0e7bc4b9 AK |
1462 | /* |
1463 | * Misaligned accesses are too much trouble to fix | |
1464 | * up; also, they usually indicate a page is not used | |
1465 | * as a page table. | |
86a5ba02 AK |
1466 | * |
1467 | * If we're seeing too many writes to a page, | |
1468 | * it may no longer be a page table, or we may be | |
1469 | * forking, in which case it is better to unmap the | |
1470 | * page. | |
0e7bc4b9 AK |
1471 | */ |
1472 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4db35314 AK |
1473 | gpa, bytes, sp->role.word); |
1474 | kvm_mmu_zap_page(vcpu->kvm, sp); | |
4cee5764 | 1475 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
1476 | continue; |
1477 | } | |
9b7a0325 | 1478 | page_offset = offset; |
4db35314 | 1479 | level = sp->role.level; |
ac1b714e | 1480 | npte = 1; |
4db35314 | 1481 | if (sp->role.glevels == PT32_ROOT_LEVEL) { |
ac1b714e AK |
1482 | page_offset <<= 1; /* 32->64 */ |
1483 | /* | |
1484 | * A 32-bit pde maps 4MB while the shadow pdes map | |
1485 | * only 2MB. So we need to double the offset again | |
1486 | * and zap two pdes instead of one. | |
1487 | */ | |
1488 | if (level == PT32_ROOT_LEVEL) { | |
6b8d0f9b | 1489 | page_offset &= ~7; /* kill rounding error */ |
ac1b714e AK |
1490 | page_offset <<= 1; |
1491 | npte = 2; | |
1492 | } | |
fce0657f | 1493 | quadrant = page_offset >> PAGE_SHIFT; |
9b7a0325 | 1494 | page_offset &= ~PAGE_MASK; |
4db35314 | 1495 | if (quadrant != sp->role.quadrant) |
fce0657f | 1496 | continue; |
9b7a0325 | 1497 | } |
4db35314 | 1498 | spte = &sp->spt[page_offset / sizeof(*spte)]; |
489f1d65 DE |
1499 | if ((gpa & (pte_size - 1)) || (bytes < pte_size)) { |
1500 | gentry = 0; | |
1501 | r = kvm_read_guest_atomic(vcpu->kvm, | |
1502 | gpa & ~(u64)(pte_size - 1), | |
1503 | &gentry, pte_size); | |
1504 | new = (const void *)&gentry; | |
1505 | if (r < 0) | |
1506 | new = NULL; | |
1507 | } | |
ac1b714e | 1508 | while (npte--) { |
79539cec | 1509 | entry = *spte; |
4db35314 | 1510 | mmu_pte_write_zap_pte(vcpu, sp, spte); |
489f1d65 DE |
1511 | if (new) |
1512 | mmu_pte_write_new_pte(vcpu, sp, spte, new); | |
79539cec | 1513 | mmu_pte_write_flush_tlb(vcpu, entry, *spte); |
ac1b714e | 1514 | ++spte; |
9b7a0325 | 1515 | } |
9b7a0325 | 1516 | } |
c7addb90 | 1517 | kvm_mmu_audit(vcpu, "post pte write"); |
aaee2c94 | 1518 | spin_unlock(&vcpu->kvm->mmu_lock); |
d7824fff AK |
1519 | if (vcpu->arch.update_pte.page) { |
1520 | kvm_release_page_clean(vcpu->arch.update_pte.page); | |
1521 | vcpu->arch.update_pte.page = NULL; | |
1522 | } | |
da4a00f0 AK |
1523 | } |
1524 | ||
a436036b AK |
1525 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
1526 | { | |
10589a46 MT |
1527 | gpa_t gpa; |
1528 | int r; | |
a436036b | 1529 | |
72dc67a6 | 1530 | down_read(&vcpu->kvm->slots_lock); |
10589a46 | 1531 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva); |
72dc67a6 | 1532 | up_read(&vcpu->kvm->slots_lock); |
10589a46 | 1533 | |
aaee2c94 | 1534 | spin_lock(&vcpu->kvm->mmu_lock); |
10589a46 | 1535 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
aaee2c94 | 1536 | spin_unlock(&vcpu->kvm->mmu_lock); |
10589a46 | 1537 | return r; |
a436036b AK |
1538 | } |
1539 | ||
22d95b12 | 1540 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu) |
ebeace86 | 1541 | { |
f05e70ac | 1542 | while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES) { |
4db35314 | 1543 | struct kvm_mmu_page *sp; |
ebeace86 | 1544 | |
f05e70ac | 1545 | sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev, |
4db35314 AK |
1546 | struct kvm_mmu_page, link); |
1547 | kvm_mmu_zap_page(vcpu->kvm, sp); | |
4cee5764 | 1548 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 AK |
1549 | } |
1550 | } | |
ebeace86 | 1551 | |
3067714c AK |
1552 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code) |
1553 | { | |
1554 | int r; | |
1555 | enum emulation_result er; | |
1556 | ||
ad312c7c | 1557 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code); |
3067714c AK |
1558 | if (r < 0) |
1559 | goto out; | |
1560 | ||
1561 | if (!r) { | |
1562 | r = 1; | |
1563 | goto out; | |
1564 | } | |
1565 | ||
b733bfb5 AK |
1566 | r = mmu_topup_memory_caches(vcpu); |
1567 | if (r) | |
1568 | goto out; | |
1569 | ||
3067714c | 1570 | er = emulate_instruction(vcpu, vcpu->run, cr2, error_code, 0); |
3067714c AK |
1571 | |
1572 | switch (er) { | |
1573 | case EMULATE_DONE: | |
1574 | return 1; | |
1575 | case EMULATE_DO_MMIO: | |
1576 | ++vcpu->stat.mmio_exits; | |
1577 | return 0; | |
1578 | case EMULATE_FAIL: | |
1579 | kvm_report_emulation_failure(vcpu, "pagetable"); | |
1580 | return 1; | |
1581 | default: | |
1582 | BUG(); | |
1583 | } | |
1584 | out: | |
3067714c AK |
1585 | return r; |
1586 | } | |
1587 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
1588 | ||
6aa8b732 AK |
1589 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
1590 | { | |
4db35314 | 1591 | struct kvm_mmu_page *sp; |
6aa8b732 | 1592 | |
f05e70ac ZX |
1593 | while (!list_empty(&vcpu->kvm->arch.active_mmu_pages)) { |
1594 | sp = container_of(vcpu->kvm->arch.active_mmu_pages.next, | |
4db35314 AK |
1595 | struct kvm_mmu_page, link); |
1596 | kvm_mmu_zap_page(vcpu->kvm, sp); | |
f51234c2 | 1597 | } |
ad312c7c | 1598 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
6aa8b732 AK |
1599 | } |
1600 | ||
1601 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
1602 | { | |
17ac10ad | 1603 | struct page *page; |
6aa8b732 AK |
1604 | int i; |
1605 | ||
1606 | ASSERT(vcpu); | |
1607 | ||
f05e70ac ZX |
1608 | if (vcpu->kvm->arch.n_requested_mmu_pages) |
1609 | vcpu->kvm->arch.n_free_mmu_pages = | |
1610 | vcpu->kvm->arch.n_requested_mmu_pages; | |
82ce2c96 | 1611 | else |
f05e70ac ZX |
1612 | vcpu->kvm->arch.n_free_mmu_pages = |
1613 | vcpu->kvm->arch.n_alloc_mmu_pages; | |
17ac10ad AK |
1614 | /* |
1615 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
1616 | * Therefore we need to allocate shadow page tables in the first | |
1617 | * 4GB of memory, which happens to fit the DMA32 zone. | |
1618 | */ | |
1619 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
1620 | if (!page) | |
1621 | goto error_1; | |
ad312c7c | 1622 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 1623 | for (i = 0; i < 4; ++i) |
ad312c7c | 1624 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 1625 | |
6aa8b732 AK |
1626 | return 0; |
1627 | ||
1628 | error_1: | |
1629 | free_mmu_pages(vcpu); | |
1630 | return -ENOMEM; | |
1631 | } | |
1632 | ||
8018c27b | 1633 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 1634 | { |
6aa8b732 | 1635 | ASSERT(vcpu); |
ad312c7c | 1636 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 1637 | |
8018c27b IM |
1638 | return alloc_mmu_pages(vcpu); |
1639 | } | |
6aa8b732 | 1640 | |
8018c27b IM |
1641 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
1642 | { | |
1643 | ASSERT(vcpu); | |
ad312c7c | 1644 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 1645 | |
8018c27b | 1646 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
1647 | } |
1648 | ||
1649 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) | |
1650 | { | |
1651 | ASSERT(vcpu); | |
1652 | ||
1653 | destroy_kvm_mmu(vcpu); | |
1654 | free_mmu_pages(vcpu); | |
714b93da | 1655 | mmu_free_memory_caches(vcpu); |
6aa8b732 AK |
1656 | } |
1657 | ||
90cb0529 | 1658 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 1659 | { |
4db35314 | 1660 | struct kvm_mmu_page *sp; |
6aa8b732 | 1661 | |
f05e70ac | 1662 | list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) { |
6aa8b732 AK |
1663 | int i; |
1664 | u64 *pt; | |
1665 | ||
4db35314 | 1666 | if (!test_bit(slot, &sp->slot_bitmap)) |
6aa8b732 AK |
1667 | continue; |
1668 | ||
4db35314 | 1669 | pt = sp->spt; |
6aa8b732 AK |
1670 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
1671 | /* avoid RMW */ | |
9647c14c | 1672 | if (pt[i] & PT_WRITABLE_MASK) |
6aa8b732 | 1673 | pt[i] &= ~PT_WRITABLE_MASK; |
6aa8b732 AK |
1674 | } |
1675 | } | |
37a7d8b0 | 1676 | |
90cb0529 | 1677 | void kvm_mmu_zap_all(struct kvm *kvm) |
e0fa826f | 1678 | { |
4db35314 | 1679 | struct kvm_mmu_page *sp, *node; |
e0fa826f | 1680 | |
aaee2c94 | 1681 | spin_lock(&kvm->mmu_lock); |
f05e70ac | 1682 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) |
4db35314 | 1683 | kvm_mmu_zap_page(kvm, sp); |
aaee2c94 | 1684 | spin_unlock(&kvm->mmu_lock); |
e0fa826f | 1685 | |
90cb0529 | 1686 | kvm_flush_remote_tlbs(kvm); |
e0fa826f DL |
1687 | } |
1688 | ||
b5a33a75 AK |
1689 | void kvm_mmu_module_exit(void) |
1690 | { | |
1691 | if (pte_chain_cache) | |
1692 | kmem_cache_destroy(pte_chain_cache); | |
1693 | if (rmap_desc_cache) | |
1694 | kmem_cache_destroy(rmap_desc_cache); | |
d3d25b04 AK |
1695 | if (mmu_page_header_cache) |
1696 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
1697 | } |
1698 | ||
1699 | int kvm_mmu_module_init(void) | |
1700 | { | |
1701 | pte_chain_cache = kmem_cache_create("kvm_pte_chain", | |
1702 | sizeof(struct kvm_pte_chain), | |
20c2df83 | 1703 | 0, 0, NULL); |
b5a33a75 AK |
1704 | if (!pte_chain_cache) |
1705 | goto nomem; | |
1706 | rmap_desc_cache = kmem_cache_create("kvm_rmap_desc", | |
1707 | sizeof(struct kvm_rmap_desc), | |
20c2df83 | 1708 | 0, 0, NULL); |
b5a33a75 AK |
1709 | if (!rmap_desc_cache) |
1710 | goto nomem; | |
1711 | ||
d3d25b04 AK |
1712 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
1713 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 1714 | 0, 0, NULL); |
d3d25b04 AK |
1715 | if (!mmu_page_header_cache) |
1716 | goto nomem; | |
1717 | ||
b5a33a75 AK |
1718 | return 0; |
1719 | ||
1720 | nomem: | |
1721 | kvm_mmu_module_exit(); | |
1722 | return -ENOMEM; | |
1723 | } | |
1724 | ||
3ad82a7e ZX |
1725 | /* |
1726 | * Caculate mmu pages needed for kvm. | |
1727 | */ | |
1728 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
1729 | { | |
1730 | int i; | |
1731 | unsigned int nr_mmu_pages; | |
1732 | unsigned int nr_pages = 0; | |
1733 | ||
1734 | for (i = 0; i < kvm->nmemslots; i++) | |
1735 | nr_pages += kvm->memslots[i].npages; | |
1736 | ||
1737 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
1738 | nr_mmu_pages = max(nr_mmu_pages, | |
1739 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
1740 | ||
1741 | return nr_mmu_pages; | |
1742 | } | |
1743 | ||
37a7d8b0 AK |
1744 | #ifdef AUDIT |
1745 | ||
1746 | static const char *audit_msg; | |
1747 | ||
1748 | static gva_t canonicalize(gva_t gva) | |
1749 | { | |
1750 | #ifdef CONFIG_X86_64 | |
1751 | gva = (long long)(gva << 16) >> 16; | |
1752 | #endif | |
1753 | return gva; | |
1754 | } | |
1755 | ||
1756 | static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte, | |
1757 | gva_t va, int level) | |
1758 | { | |
1759 | u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK); | |
1760 | int i; | |
1761 | gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1)); | |
1762 | ||
1763 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) { | |
1764 | u64 ent = pt[i]; | |
1765 | ||
c7addb90 | 1766 | if (ent == shadow_trap_nonpresent_pte) |
37a7d8b0 AK |
1767 | continue; |
1768 | ||
1769 | va = canonicalize(va); | |
c7addb90 AK |
1770 | if (level > 1) { |
1771 | if (ent == shadow_notrap_nonpresent_pte) | |
1772 | printk(KERN_ERR "audit: (%s) nontrapping pte" | |
1773 | " in nonleaf level: levels %d gva %lx" | |
1774 | " level %d pte %llx\n", audit_msg, | |
ad312c7c | 1775 | vcpu->arch.mmu.root_level, va, level, ent); |
c7addb90 | 1776 | |
37a7d8b0 | 1777 | audit_mappings_page(vcpu, ent, va, level - 1); |
c7addb90 | 1778 | } else { |
ad312c7c | 1779 | gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, va); |
1d28f5f4 AK |
1780 | struct page *page = gpa_to_page(vcpu, gpa); |
1781 | hpa_t hpa = page_to_phys(page); | |
37a7d8b0 | 1782 | |
c7addb90 | 1783 | if (is_shadow_present_pte(ent) |
37a7d8b0 | 1784 | && (ent & PT64_BASE_ADDR_MASK) != hpa) |
c7addb90 AK |
1785 | printk(KERN_ERR "xx audit error: (%s) levels %d" |
1786 | " gva %lx gpa %llx hpa %llx ent %llx %d\n", | |
ad312c7c | 1787 | audit_msg, vcpu->arch.mmu.root_level, |
d77c26fc MD |
1788 | va, gpa, hpa, ent, |
1789 | is_shadow_present_pte(ent)); | |
c7addb90 AK |
1790 | else if (ent == shadow_notrap_nonpresent_pte |
1791 | && !is_error_hpa(hpa)) | |
1792 | printk(KERN_ERR "audit: (%s) notrap shadow," | |
1793 | " valid guest gva %lx\n", audit_msg, va); | |
b4231d61 | 1794 | kvm_release_page_clean(page); |
c7addb90 | 1795 | |
37a7d8b0 AK |
1796 | } |
1797 | } | |
1798 | } | |
1799 | ||
1800 | static void audit_mappings(struct kvm_vcpu *vcpu) | |
1801 | { | |
1ea252af | 1802 | unsigned i; |
37a7d8b0 | 1803 | |
ad312c7c ZX |
1804 | if (vcpu->arch.mmu.root_level == 4) |
1805 | audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4); | |
37a7d8b0 AK |
1806 | else |
1807 | for (i = 0; i < 4; ++i) | |
ad312c7c | 1808 | if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK) |
37a7d8b0 | 1809 | audit_mappings_page(vcpu, |
ad312c7c | 1810 | vcpu->arch.mmu.pae_root[i], |
37a7d8b0 AK |
1811 | i << 30, |
1812 | 2); | |
1813 | } | |
1814 | ||
1815 | static int count_rmaps(struct kvm_vcpu *vcpu) | |
1816 | { | |
1817 | int nmaps = 0; | |
1818 | int i, j, k; | |
1819 | ||
1820 | for (i = 0; i < KVM_MEMORY_SLOTS; ++i) { | |
1821 | struct kvm_memory_slot *m = &vcpu->kvm->memslots[i]; | |
1822 | struct kvm_rmap_desc *d; | |
1823 | ||
1824 | for (j = 0; j < m->npages; ++j) { | |
290fc38d | 1825 | unsigned long *rmapp = &m->rmap[j]; |
37a7d8b0 | 1826 | |
290fc38d | 1827 | if (!*rmapp) |
37a7d8b0 | 1828 | continue; |
290fc38d | 1829 | if (!(*rmapp & 1)) { |
37a7d8b0 AK |
1830 | ++nmaps; |
1831 | continue; | |
1832 | } | |
290fc38d | 1833 | d = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
37a7d8b0 AK |
1834 | while (d) { |
1835 | for (k = 0; k < RMAP_EXT; ++k) | |
1836 | if (d->shadow_ptes[k]) | |
1837 | ++nmaps; | |
1838 | else | |
1839 | break; | |
1840 | d = d->more; | |
1841 | } | |
1842 | } | |
1843 | } | |
1844 | return nmaps; | |
1845 | } | |
1846 | ||
1847 | static int count_writable_mappings(struct kvm_vcpu *vcpu) | |
1848 | { | |
1849 | int nmaps = 0; | |
4db35314 | 1850 | struct kvm_mmu_page *sp; |
37a7d8b0 AK |
1851 | int i; |
1852 | ||
f05e70ac | 1853 | list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) { |
4db35314 | 1854 | u64 *pt = sp->spt; |
37a7d8b0 | 1855 | |
4db35314 | 1856 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) |
37a7d8b0 AK |
1857 | continue; |
1858 | ||
1859 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
1860 | u64 ent = pt[i]; | |
1861 | ||
1862 | if (!(ent & PT_PRESENT_MASK)) | |
1863 | continue; | |
1864 | if (!(ent & PT_WRITABLE_MASK)) | |
1865 | continue; | |
1866 | ++nmaps; | |
1867 | } | |
1868 | } | |
1869 | return nmaps; | |
1870 | } | |
1871 | ||
1872 | static void audit_rmap(struct kvm_vcpu *vcpu) | |
1873 | { | |
1874 | int n_rmap = count_rmaps(vcpu); | |
1875 | int n_actual = count_writable_mappings(vcpu); | |
1876 | ||
1877 | if (n_rmap != n_actual) | |
1878 | printk(KERN_ERR "%s: (%s) rmap %d actual %d\n", | |
1879 | __FUNCTION__, audit_msg, n_rmap, n_actual); | |
1880 | } | |
1881 | ||
1882 | static void audit_write_protection(struct kvm_vcpu *vcpu) | |
1883 | { | |
4db35314 | 1884 | struct kvm_mmu_page *sp; |
290fc38d IE |
1885 | struct kvm_memory_slot *slot; |
1886 | unsigned long *rmapp; | |
1887 | gfn_t gfn; | |
37a7d8b0 | 1888 | |
f05e70ac | 1889 | list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) { |
4db35314 | 1890 | if (sp->role.metaphysical) |
37a7d8b0 AK |
1891 | continue; |
1892 | ||
4db35314 AK |
1893 | slot = gfn_to_memslot(vcpu->kvm, sp->gfn); |
1894 | gfn = unalias_gfn(vcpu->kvm, sp->gfn); | |
290fc38d IE |
1895 | rmapp = &slot->rmap[gfn - slot->base_gfn]; |
1896 | if (*rmapp) | |
37a7d8b0 AK |
1897 | printk(KERN_ERR "%s: (%s) shadow page has writable" |
1898 | " mappings: gfn %lx role %x\n", | |
4db35314 AK |
1899 | __FUNCTION__, audit_msg, sp->gfn, |
1900 | sp->role.word); | |
37a7d8b0 AK |
1901 | } |
1902 | } | |
1903 | ||
1904 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) | |
1905 | { | |
1906 | int olddbg = dbg; | |
1907 | ||
1908 | dbg = 0; | |
1909 | audit_msg = msg; | |
1910 | audit_rmap(vcpu); | |
1911 | audit_write_protection(vcpu); | |
1912 | audit_mappings(vcpu); | |
1913 | dbg = olddbg; | |
1914 | } | |
1915 | ||
1916 | #endif |