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KVM: MMU: Add link_shadow_page() helper
[linux-block.git] / arch / x86 / kvm / mmu.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
221d059d 10 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 11 *
12 * Authors:
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
e495606d 20
1d737c8a 21#include "mmu.h"
836a1b3c 22#include "x86.h"
6de4f3ad 23#include "kvm_cache_regs.h"
e495606d 24
edf88417 25#include <linux/kvm_host.h>
6aa8b732
AK		 26#include <linux/types.h>
27#include <linux/string.h>
6aa8b732
AK		 28#include <linux/mm.h>
29#include <linux/highmem.h>
30#include <linux/module.h>
448353ca 31#include <linux/swap.h>
05da4558 32#include <linux/hugetlb.h>
2f333bcb 33#include <linux/compiler.h>
bc6678a3 34#include <linux/srcu.h>
5a0e3ad6 35#include <linux/slab.h>
bf998156 36#include <linux/uaccess.h>
6aa8b732 37
e495606d
AK		 38#include <asm/page.h>
39#include <asm/cmpxchg.h>
4e542370 40#include <asm/io.h>
13673a90 41#include <asm/vmx.h>
6aa8b732 42
18552672
JR		 43/*
44 * When setting this variable to true it enables Two-Dimensional-Paging
45 * where the hardware walks 2 page tables:
46 * 1. the guest-virtual to guest-physical
47 * 2. while doing 1. it walks guest-physical to host-physical
48 * If the hardware supports that we don't need to do shadow paging.
49 */
2f333bcb 50bool tdp_enabled = false;
18552672 51
37a7d8b0
AK		 52#undef MMU_DEBUG
53
54#undef AUDIT
55
56#ifdef AUDIT
57static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg);
58#else
59static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {}
60#endif
61
62#ifdef MMU_DEBUG
63
64#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
65#define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
66
67#else
68
69#define pgprintk(x...) do { } while (0)
70#define rmap_printk(x...) do { } while (0)
71
72#endif
73
74#if defined(MMU_DEBUG) || defined(AUDIT)
6ada8cca
AK		 75static int dbg = 0;
76module_param(dbg, bool, 0644);
37a7d8b0 77#endif
6aa8b732 78
582801a9
MT		 79static int oos_shadow = 1;
80module_param(oos_shadow, bool, 0644);
81
d6c69ee9
YD		 82#ifndef MMU_DEBUG
83#define ASSERT(x) do { } while (0)
84#else
6aa8b732
AK		 85#define ASSERT(x) \
86 if (!(x)) { \
87 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
88 __FILE__, __LINE__, #x); \
89 }
d6c69ee9 90#endif
6aa8b732 91
6aa8b732
AK		 92#define PT_FIRST_AVAIL_BITS_SHIFT 9
93#define PT64_SECOND_AVAIL_BITS_SHIFT 52
94
6aa8b732
AK		 95#define PT64_LEVEL_BITS 9
96
97#define PT64_LEVEL_SHIFT(level) \
d77c26fc 98 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
6aa8b732
AK		 99
100#define PT64_LEVEL_MASK(level) \
101 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
102
103#define PT64_INDEX(address, level)\
104 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
105
106
107#define PT32_LEVEL_BITS 10
108
109#define PT32_LEVEL_SHIFT(level) \
d77c26fc 110 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
6aa8b732
AK		 111
112#define PT32_LEVEL_MASK(level) \
113 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
e04da980
JR		 114#define PT32_LVL_OFFSET_MASK(level) \
115 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
116 * PT32_LEVEL_BITS))) - 1))
6aa8b732
AK		 117
118#define PT32_INDEX(address, level)\
119 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
120
121
27aba766 122#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
6aa8b732
AK		 123#define PT64_DIR_BASE_ADDR_MASK \
124 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
e04da980
JR		 125#define PT64_LVL_ADDR_MASK(level) \
126 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
127 * PT64_LEVEL_BITS))) - 1))
128#define PT64_LVL_OFFSET_MASK(level) \
129 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
130 * PT64_LEVEL_BITS))) - 1))
6aa8b732
AK		 131
132#define PT32_BASE_ADDR_MASK PAGE_MASK
133#define PT32_DIR_BASE_ADDR_MASK \
134 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
e04da980
JR		 135#define PT32_LVL_ADDR_MASK(level) \
136 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
137 * PT32_LEVEL_BITS))) - 1))
6aa8b732 138
79539cec
AK		 139#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
140 | PT64_NX_MASK)
6aa8b732 141
cd4a4e53
AK		 142#define RMAP_EXT 4
143
fe135d2c
AK		 144#define ACC_EXEC_MASK 1
145#define ACC_WRITE_MASK PT_WRITABLE_MASK
146#define ACC_USER_MASK PT_USER_MASK
147#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
148
90bb6fc5
AK		 149#include <trace/events/kvm.h>
150
07420171
AK		 151#define CREATE_TRACE_POINTS
152#include "mmutrace.h"
153
1403283a
IE		 154#define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
155
135f8c2b
AK		 156#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
157
cd4a4e53 158struct kvm_rmap_desc {
d555c333 159 u64 *sptes[RMAP_EXT];
cd4a4e53
AK		 160 struct kvm_rmap_desc *more;
161};
162
2d11123a
AK		 163struct kvm_shadow_walk_iterator {
164 u64 addr;
165 hpa_t shadow_addr;
166 int level;
167 u64 *sptep;
168 unsigned index;
169};
170
171#define for_each_shadow_entry(_vcpu, _addr, _walker) \
172 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
173 shadow_walk_okay(&(_walker)); \
174 shadow_walk_next(&(_walker)))
175
1047df1f 176typedef void (*mmu_parent_walk_fn) (struct kvm_mmu_page *sp, u64 *spte);
ad8cfbe3 177
b5a33a75
AK		 178static struct kmem_cache *pte_chain_cache;
179static struct kmem_cache *rmap_desc_cache;
d3d25b04 180static struct kmem_cache *mmu_page_header_cache;
b5a33a75 181
c7addb90
AK		 182static u64 __read_mostly shadow_trap_nonpresent_pte;
183static u64 __read_mostly shadow_notrap_nonpresent_pte;
7b52345e
SY		 184static u64 __read_mostly shadow_base_present_pte;
185static u64 __read_mostly shadow_nx_mask;
186static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
187static u64 __read_mostly shadow_user_mask;
188static u64 __read_mostly shadow_accessed_mask;
189static u64 __read_mostly shadow_dirty_mask;
c7addb90 190
82725b20
DE		 191static inline u64 rsvd_bits(int s, int e)
192{
193 return ((1ULL << (e - s + 1)) - 1) << s;
194}
195
c7addb90
AK		 196void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
197{
198 shadow_trap_nonpresent_pte = trap_pte;
199 shadow_notrap_nonpresent_pte = notrap_pte;
200}
201EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
202
7b52345e
SY		 203void kvm_mmu_set_base_ptes(u64 base_pte)
204{
205 shadow_base_present_pte = base_pte;
206}
207EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes);
208
209void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
4b12f0de 210 u64 dirty_mask, u64 nx_mask, u64 x_mask)
7b52345e
SY		 211{
212 shadow_user_mask = user_mask;
213 shadow_accessed_mask = accessed_mask;
214 shadow_dirty_mask = dirty_mask;
215 shadow_nx_mask = nx_mask;
216 shadow_x_mask = x_mask;
217}
218EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
219
3dbe1415 220static bool is_write_protection(struct kvm_vcpu *vcpu)
6aa8b732 221{
4d4ec087 222 return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
6aa8b732
AK		 223}
224
225static int is_cpuid_PSE36(void)
226{
227 return 1;
228}
229
73b1087e
AK		 230static int is_nx(struct kvm_vcpu *vcpu)
231{
f6801dff 232 return vcpu->arch.efer & EFER_NX;
73b1087e
AK		 233}
234
c7addb90
AK		 235static int is_shadow_present_pte(u64 pte)
236{
c7addb90
AK		 237 return pte != shadow_trap_nonpresent_pte
238 && pte != shadow_notrap_nonpresent_pte;
239}
240
05da4558
MT		 241static int is_large_pte(u64 pte)
242{
243 return pte & PT_PAGE_SIZE_MASK;
244}
245
8dae4445 246static int is_writable_pte(unsigned long pte)
6aa8b732
AK		 247{
248 return pte & PT_WRITABLE_MASK;
249}
250
43a3795a 251static int is_dirty_gpte(unsigned long pte)
e3c5e7ec 252{
439e218a 253 return pte & PT_DIRTY_MASK;
e3c5e7ec
AK		 254}
255
43a3795a 256static int is_rmap_spte(u64 pte)
cd4a4e53 257{
4b1a80fa 258 return is_shadow_present_pte(pte);
cd4a4e53
AK		 259}
260
776e6633
MT		 261static int is_last_spte(u64 pte, int level)
262{
263 if (level == PT_PAGE_TABLE_LEVEL)
264 return 1;
852e3c19 265 if (is_large_pte(pte))
776e6633
MT		 266 return 1;
267 return 0;
268}
269
35149e21 270static pfn_t spte_to_pfn(u64 pte)
0b49ea86 271{
35149e21 272 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
0b49ea86
AK		 273}
274
da928521
AK		 275static gfn_t pse36_gfn_delta(u32 gpte)
276{
277 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
278
279 return (gpte & PT32_DIR_PSE36_MASK) << shift;
280}
281
d555c333 282static void __set_spte(u64 *sptep, u64 spte)
e663ee64
AK		 283{
284#ifdef CONFIG_X86_64
285 set_64bit((unsigned long *)sptep, spte);
286#else
287 set_64bit((unsigned long long *)sptep, spte);
288#endif
289}
290
a9221dd5
AK		 291static u64 __xchg_spte(u64 *sptep, u64 new_spte)
292{
293#ifdef CONFIG_X86_64
294 return xchg(sptep, new_spte);
295#else
296 u64 old_spte;
297
298 do {
299 old_spte = *sptep;
300 } while (cmpxchg64(sptep, old_spte, new_spte) != old_spte);
301
302 return old_spte;
303#endif
304}
305
b79b93f9
AK		 306static void update_spte(u64 *sptep, u64 new_spte)
307{
308 u64 old_spte;
309
310 if (!shadow_accessed_mask || (new_spte & shadow_accessed_mask)) {
311 __set_spte(sptep, new_spte);
312 } else {
313 old_spte = __xchg_spte(sptep, new_spte);
314 if (old_spte & shadow_accessed_mask)
315 mark_page_accessed(pfn_to_page(spte_to_pfn(old_spte)));
316 }
317}
318
e2dec939 319static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
2e3e5882 320 struct kmem_cache *base_cache, int min)
714b93da
AK		 321{
322 void *obj;
323
324 if (cache->nobjs >= min)
e2dec939 325 return 0;
714b93da 326 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 327 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
714b93da 328 if (!obj)
e2dec939 329 return -ENOMEM;
714b93da
AK		 330 cache->objects[cache->nobjs++] = obj;
331 }
e2dec939 332 return 0;
714b93da
AK		 333}
334
e8ad9a70
XG		 335static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
336 struct kmem_cache *cache)
714b93da
AK		 337{
338 while (mc->nobjs)
e8ad9a70 339 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
714b93da
AK		 340}
341
c1158e63 342static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
2e3e5882 343 int min)
c1158e63
AK		 344{
345 struct page *page;
346
347 if (cache->nobjs >= min)
348 return 0;
349 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 350 page = alloc_page(GFP_KERNEL);
c1158e63
AK		 351 if (!page)
352 return -ENOMEM;
c1158e63
AK		 353 cache->objects[cache->nobjs++] = page_address(page);
354 }
355 return 0;
356}
357
358static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
359{
360 while (mc->nobjs)
c4d198d5 361 free_page((unsigned long)mc->objects[--mc->nobjs]);
c1158e63
AK		 362}
363
2e3e5882 364static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
714b93da 365{
e2dec939
AK		 366 int r;
367
ad312c7c 368 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
2e3e5882 369 pte_chain_cache, 4);
e2dec939
AK		 370 if (r)
371 goto out;
ad312c7c 372 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
c41ef344 373 rmap_desc_cache, 4);
d3d25b04
AK		 374 if (r)
375 goto out;
ad312c7c 376 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
d3d25b04
AK		 377 if (r)
378 goto out;
ad312c7c 379 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
2e3e5882 380 mmu_page_header_cache, 4);
e2dec939
AK		 381out:
382 return r;
714b93da
AK		 383}
384
385static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
386{
e8ad9a70
XG		 387 mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache, pte_chain_cache);
388 mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, rmap_desc_cache);
ad312c7c 389 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
e8ad9a70
XG		 390 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
391 mmu_page_header_cache);
714b93da
AK		 392}
393
394static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
395 size_t size)
396{
397 void *p;
398
399 BUG_ON(!mc->nobjs);
400 p = mc->objects[--mc->nobjs];
714b93da
AK		 401 return p;
402}
403
714b93da
AK		 404static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
405{
ad312c7c 406 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
714b93da
AK		 407 sizeof(struct kvm_pte_chain));
408}
409
90cb0529 410static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
714b93da 411{
e8ad9a70 412 kmem_cache_free(pte_chain_cache, pc);
714b93da
AK		 413}
414
415static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
416{
ad312c7c 417 return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
714b93da
AK		 418 sizeof(struct kvm_rmap_desc));
419}
420
90cb0529 421static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
714b93da 422{
e8ad9a70 423 kmem_cache_free(rmap_desc_cache, rd);
714b93da
AK		 424}
425
2032a93d
LJ		 426static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
427{
428 if (!sp->role.direct)
429 return sp->gfns[index];
430
431 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
432}
433
434static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
435{
436 if (sp->role.direct)
437 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
438 else
439 sp->gfns[index] = gfn;
440}
441
05da4558
MT		 442/*
443 * Return the pointer to the largepage write count for a given
444 * gfn, handling slots that are not large page aligned.
445 */
d25797b2
JR		 446static int *slot_largepage_idx(gfn_t gfn,
447 struct kvm_memory_slot *slot,
448 int level)
05da4558
MT		 449{
450 unsigned long idx;
451
82855413
JR		 452 idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
453 (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
d25797b2 454 return &slot->lpage_info[level - 2][idx].write_count;
05da4558
MT		 455}
456
457static void account_shadowed(struct kvm *kvm, gfn_t gfn)
458{
d25797b2 459 struct kvm_memory_slot *slot;
05da4558 460 int *write_count;
d25797b2 461 int i;
05da4558 462
a1f4d395 463 slot = gfn_to_memslot(kvm, gfn);
d25797b2
JR		 464 for (i = PT_DIRECTORY_LEVEL;
465 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
466 write_count = slot_largepage_idx(gfn, slot, i);
467 *write_count += 1;
468 }
05da4558
MT		 469}
470
471static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
472{
d25797b2 473 struct kvm_memory_slot *slot;
05da4558 474 int *write_count;
d25797b2 475 int i;
05da4558 476
a1f4d395 477 slot = gfn_to_memslot(kvm, gfn);
d25797b2
JR		 478 for (i = PT_DIRECTORY_LEVEL;
479 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
d25797b2
JR		 480 write_count = slot_largepage_idx(gfn, slot, i);
481 *write_count -= 1;
482 WARN_ON(*write_count < 0);
483 }
05da4558
MT		 484}
485
d25797b2
JR		 486static int has_wrprotected_page(struct kvm *kvm,
487 gfn_t gfn,
488 int level)
05da4558 489{
2843099f 490 struct kvm_memory_slot *slot;
05da4558
MT		 491 int *largepage_idx;
492
a1f4d395 493 slot = gfn_to_memslot(kvm, gfn);
05da4558 494 if (slot) {
d25797b2 495 largepage_idx = slot_largepage_idx(gfn, slot, level);
05da4558
MT		 496 return *largepage_idx;
497 }
498
499 return 1;
500}
501
d25797b2 502static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
05da4558 503{
8f0b1ab6 504 unsigned long page_size;
d25797b2 505 int i, ret = 0;
05da4558 506
8f0b1ab6 507 page_size = kvm_host_page_size(kvm, gfn);
05da4558 508
d25797b2
JR		 509 for (i = PT_PAGE_TABLE_LEVEL;
510 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
511 if (page_size >= KVM_HPAGE_SIZE(i))
512 ret = i;
513 else
514 break;
515 }
516
4c2155ce 517 return ret;
05da4558
MT		 518}
519
d25797b2 520static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
05da4558
MT		 521{
522 struct kvm_memory_slot *slot;
878403b7 523 int host_level, level, max_level;
05da4558
MT		 524
525 slot = gfn_to_memslot(vcpu->kvm, large_gfn);
526 if (slot && slot->dirty_bitmap)
d25797b2 527 return PT_PAGE_TABLE_LEVEL;
05da4558 528
d25797b2
JR		 529 host_level = host_mapping_level(vcpu->kvm, large_gfn);
530
531 if (host_level == PT_PAGE_TABLE_LEVEL)
532 return host_level;
533
878403b7
SY		 534 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
535 kvm_x86_ops->get_lpage_level() : host_level;
536
537 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
d25797b2
JR		 538 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
539 break;
d25797b2
JR		 540
541 return level - 1;
05da4558
MT		 542}
543
290fc38d
IE		 544/*
545 * Take gfn and return the reverse mapping to it.
290fc38d
IE		 546 */
547
44ad9944 548static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
290fc38d
IE		 549{
550 struct kvm_memory_slot *slot;
05da4558 551 unsigned long idx;
290fc38d
IE		 552
553 slot = gfn_to_memslot(kvm, gfn);
44ad9944 554 if (likely(level == PT_PAGE_TABLE_LEVEL))
05da4558
MT		 555 return &slot->rmap[gfn - slot->base_gfn];
556
82855413
JR		 557 idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
558 (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
05da4558 559
44ad9944 560 return &slot->lpage_info[level - 2][idx].rmap_pde;
290fc38d
IE		 561}
562
cd4a4e53
AK		 563/*
564 * Reverse mapping data structures:
565 *
290fc38d
IE		 566 * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
567 * that points to page_address(page).
cd4a4e53 568 *
290fc38d
IE		 569 * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
570 * containing more mappings.
53a27b39
MT		 571 *
572 * Returns the number of rmap entries before the spte was added or zero if
573 * the spte was not added.
574 *
cd4a4e53 575 */
44ad9944 576static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
cd4a4e53 577{
4db35314 578 struct kvm_mmu_page *sp;
cd4a4e53 579 struct kvm_rmap_desc *desc;
290fc38d 580 unsigned long *rmapp;
53a27b39 581 int i, count = 0;
cd4a4e53 582
43a3795a 583 if (!is_rmap_spte(*spte))
53a27b39 584 return count;
4db35314 585 sp = page_header(__pa(spte));
2032a93d 586 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
44ad9944 587 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
290fc38d 588 if (!*rmapp) {
cd4a4e53 589 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
290fc38d
IE		 590 *rmapp = (unsigned long)spte;
591 } else if (!(*rmapp & 1)) {
cd4a4e53 592 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
714b93da 593 desc = mmu_alloc_rmap_desc(vcpu);
d555c333
AK		 594 desc->sptes[0] = (u64 *)*rmapp;
595 desc->sptes[1] = spte;
290fc38d 596 *rmapp = (unsigned long)desc | 1;
cd4a4e53
AK		 597 } else {
598 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
290fc38d 599 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
d555c333 600 while (desc->sptes[RMAP_EXT-1] && desc->more) {
cd4a4e53 601 desc = desc->more;
53a27b39
MT		 602 count += RMAP_EXT;
603 }
d555c333 604 if (desc->sptes[RMAP_EXT-1]) {
714b93da 605 desc->more = mmu_alloc_rmap_desc(vcpu);
cd4a4e53
AK		 606 desc = desc->more;
607 }
d555c333 608 for (i = 0; desc->sptes[i]; ++i)
cd4a4e53 609 ;
d555c333 610 desc->sptes[i] = spte;
cd4a4e53 611 }
53a27b39 612 return count;
cd4a4e53
AK		 613}
614
290fc38d 615static void rmap_desc_remove_entry(unsigned long *rmapp,
cd4a4e53
AK		 616 struct kvm_rmap_desc *desc,
617 int i,
618 struct kvm_rmap_desc *prev_desc)
619{
620 int j;
621
d555c333 622 for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j)
cd4a4e53 623 ;
d555c333
AK		 624 desc->sptes[i] = desc->sptes[j];
625 desc->sptes[j] = NULL;
cd4a4e53
AK		 626 if (j != 0)
627 return;
628 if (!prev_desc && !desc->more)
d555c333 629 *rmapp = (unsigned long)desc->sptes[0];
cd4a4e53
AK		 630 else
631 if (prev_desc)
632 prev_desc->more = desc->more;
633 else
290fc38d 634 *rmapp = (unsigned long)desc->more | 1;
90cb0529 635 mmu_free_rmap_desc(desc);
cd4a4e53
AK		 636}
637
290fc38d 638static void rmap_remove(struct kvm *kvm, u64 *spte)
cd4a4e53 639{
cd4a4e53
AK		 640 struct kvm_rmap_desc *desc;
641 struct kvm_rmap_desc *prev_desc;
4db35314 642 struct kvm_mmu_page *sp;
2032a93d 643 gfn_t gfn;
290fc38d 644 unsigned long *rmapp;
cd4a4e53
AK		 645 int i;
646
4db35314 647 sp = page_header(__pa(spte));
2032a93d
LJ		 648 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
649 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
290fc38d 650 if (!*rmapp) {
cd4a4e53
AK		 651 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
652 BUG();
290fc38d 653 } else if (!(*rmapp & 1)) {
cd4a4e53 654 rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte);
290fc38d 655 if ((u64 *)*rmapp != spte) {
cd4a4e53
AK		 656 printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n",
657 spte, *spte);
658 BUG();
659 }
290fc38d 660 *rmapp = 0;
cd4a4e53
AK		 661 } else {
662 rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte);
290fc38d 663 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
cd4a4e53
AK		 664 prev_desc = NULL;
665 while (desc) {
d555c333
AK		 666 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i)
667 if (desc->sptes[i] == spte) {
290fc38d 668 rmap_desc_remove_entry(rmapp,
714b93da 669 desc, i,
cd4a4e53
AK		 670 prev_desc);
671 return;
672 }
673 prev_desc = desc;
674 desc = desc->more;
675 }
186a3e52 676 pr_err("rmap_remove: %p %llx many->many\n", spte, *spte);
cd4a4e53
AK		 677 BUG();
678 }
679}
680
be38d276
AK		 681static void drop_spte(struct kvm *kvm, u64 *sptep, u64 new_spte)
682{
ce061867 683 pfn_t pfn;
a9221dd5 684 u64 old_spte;
ce061867 685
a9221dd5
AK		 686 old_spte = __xchg_spte(sptep, new_spte);
687 if (!is_rmap_spte(old_spte))
ce061867 688 return;
a9221dd5
AK		 689 pfn = spte_to_pfn(old_spte);
690 if (old_spte & shadow_accessed_mask)
ce061867 691 kvm_set_pfn_accessed(pfn);
a9221dd5 692 if (is_writable_pte(old_spte))
ce061867 693 kvm_set_pfn_dirty(pfn);
be38d276 694 rmap_remove(kvm, sptep);
be38d276
AK		 695}
696
98348e95 697static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
374cbac0 698{
374cbac0 699 struct kvm_rmap_desc *desc;
98348e95
IE		 700 u64 *prev_spte;
701 int i;
702
703 if (!*rmapp)
704 return NULL;
705 else if (!(*rmapp & 1)) {
706 if (!spte)
707 return (u64 *)*rmapp;
708 return NULL;
709 }
710 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
98348e95
IE		 711 prev_spte = NULL;
712 while (desc) {
d555c333 713 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) {
98348e95 714 if (prev_spte == spte)
d555c333
AK		 715 return desc->sptes[i];
716 prev_spte = desc->sptes[i];
98348e95
IE		 717 }
718 desc = desc->more;
719 }
720 return NULL;
721}
722
b1a36821 723static int rmap_write_protect(struct kvm *kvm, u64 gfn)
98348e95 724{
290fc38d 725 unsigned long *rmapp;
374cbac0 726 u64 *spte;
44ad9944 727 int i, write_protected = 0;
374cbac0 728
44ad9944 729 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
374cbac0 730
98348e95
IE		 731 spte = rmap_next(kvm, rmapp, NULL);
732 while (spte) {
374cbac0 733 BUG_ON(!spte);
374cbac0 734 BUG_ON(!(*spte & PT_PRESENT_MASK));
374cbac0 735 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
8dae4445 736 if (is_writable_pte(*spte)) {
b79b93f9 737 update_spte(spte, *spte & ~PT_WRITABLE_MASK);
caa5b8a5
ED		 738 write_protected = 1;
739 }
9647c14c 740 spte = rmap_next(kvm, rmapp, spte);
374cbac0 741 }
855149aa 742 if (write_protected) {
35149e21 743 pfn_t pfn;
855149aa
IE		 744
745 spte = rmap_next(kvm, rmapp, NULL);
35149e21
AL		 746 pfn = spte_to_pfn(*spte);
747 kvm_set_pfn_dirty(pfn);
855149aa
IE		 748 }
749
05da4558 750 /* check for huge page mappings */
44ad9944
JR		 751 for (i = PT_DIRECTORY_LEVEL;
752 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
753 rmapp = gfn_to_rmap(kvm, gfn, i);
754 spte = rmap_next(kvm, rmapp, NULL);
755 while (spte) {
756 BUG_ON(!spte);
757 BUG_ON(!(*spte & PT_PRESENT_MASK));
758 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
759 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
8dae4445 760 if (is_writable_pte(*spte)) {
be38d276
AK		 761 drop_spte(kvm, spte,
762 shadow_trap_nonpresent_pte);
44ad9944 763 --kvm->stat.lpages;
44ad9944
JR		 764 spte = NULL;
765 write_protected = 1;
766 }
767 spte = rmap_next(kvm, rmapp, spte);
05da4558 768 }
05da4558
MT		 769 }
770
b1a36821 771 return write_protected;
374cbac0
AK		 772}
773
8a8365c5
FD		 774static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
775 unsigned long data)
e930bffe
AA		 776{
777 u64 *spte;
778 int need_tlb_flush = 0;
779
780 while ((spte = rmap_next(kvm, rmapp, NULL))) {
781 BUG_ON(!(*spte & PT_PRESENT_MASK));
782 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
be38d276 783 drop_spte(kvm, spte, shadow_trap_nonpresent_pte);
e930bffe
AA		 784 need_tlb_flush = 1;
785 }
786 return need_tlb_flush;
787}
788
8a8365c5
FD		 789static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
790 unsigned long data)
3da0dd43
IE		 791{
792 int need_flush = 0;
b79b93f9 793 u64 *spte, new_spte, old_spte;
3da0dd43
IE		 794 pte_t *ptep = (pte_t *)data;
795 pfn_t new_pfn;
796
797 WARN_ON(pte_huge(*ptep));
798 new_pfn = pte_pfn(*ptep);
799 spte = rmap_next(kvm, rmapp, NULL);
800 while (spte) {
801 BUG_ON(!is_shadow_present_pte(*spte));
802 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
803 need_flush = 1;
804 if (pte_write(*ptep)) {
be38d276 805 drop_spte(kvm, spte, shadow_trap_nonpresent_pte);
3da0dd43
IE		 806 spte = rmap_next(kvm, rmapp, NULL);
807 } else {
808 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
809 new_spte |= (u64)new_pfn << PAGE_SHIFT;
810
811 new_spte &= ~PT_WRITABLE_MASK;
812 new_spte &= ~SPTE_HOST_WRITEABLE;
b79b93f9 813 new_spte &= ~shadow_accessed_mask;
8dae4445 814 if (is_writable_pte(*spte))
3da0dd43 815 kvm_set_pfn_dirty(spte_to_pfn(*spte));
b79b93f9
AK		 816 old_spte = __xchg_spte(spte, new_spte);
817 if (is_shadow_present_pte(old_spte)
818 && (old_spte & shadow_accessed_mask))
819 mark_page_accessed(pfn_to_page(spte_to_pfn(old_spte)));
3da0dd43
IE		 820 spte = rmap_next(kvm, rmapp, spte);
821 }
822 }
823 if (need_flush)
824 kvm_flush_remote_tlbs(kvm);
825
826 return 0;
827}
828
8a8365c5
FD		 829static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
830 unsigned long data,
3da0dd43 831 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
8a8365c5 832 unsigned long data))
e930bffe 833{
852e3c19 834 int i, j;
90bb6fc5 835 int ret;
e930bffe 836 int retval = 0;
bc6678a3
MT		 837 struct kvm_memslots *slots;
838
90d83dc3 839 slots = kvm_memslots(kvm);
e930bffe 840
46a26bf5
MT		 841 for (i = 0; i < slots->nmemslots; i++) {
842 struct kvm_memory_slot *memslot = &slots->memslots[i];
e930bffe
AA		 843 unsigned long start = memslot->userspace_addr;
844 unsigned long end;
845
e930bffe
AA		 846 end = start + (memslot->npages << PAGE_SHIFT);
847 if (hva >= start && hva < end) {
848 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
852e3c19 849
90bb6fc5 850 ret = handler(kvm, &memslot->rmap[gfn_offset], data);
852e3c19
JR		 851
852 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
853 int idx = gfn_offset;
854 idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j);
90bb6fc5 855 ret |= handler(kvm,
3da0dd43
IE		 856 &memslot->lpage_info[j][idx].rmap_pde,
857 data);
852e3c19 858 }
90bb6fc5
AK		 859 trace_kvm_age_page(hva, memslot, ret);
860 retval |= ret;
e930bffe
AA		 861 }
862 }
863
864 return retval;
865}
866
867int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
868{
3da0dd43
IE		 869 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
870}
871
872void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
873{
8a8365c5 874 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
e930bffe
AA		 875}
876
8a8365c5
FD		 877static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
878 unsigned long data)
e930bffe
AA		 879{
880 u64 *spte;
881 int young = 0;
882
6316e1c8
RR		 883 /*
884 * Emulate the accessed bit for EPT, by checking if this page has
885 * an EPT mapping, and clearing it if it does. On the next access,
886 * a new EPT mapping will be established.
887 * This has some overhead, but not as much as the cost of swapping
888 * out actively used pages or breaking up actively used hugepages.
889 */
534e38b4 890 if (!shadow_accessed_mask)
6316e1c8 891 return kvm_unmap_rmapp(kvm, rmapp, data);
534e38b4 892
e930bffe
AA		 893 spte = rmap_next(kvm, rmapp, NULL);
894 while (spte) {
895 int _young;
896 u64 _spte = *spte;
897 BUG_ON(!(_spte & PT_PRESENT_MASK));
898 _young = _spte & PT_ACCESSED_MASK;
899 if (_young) {
900 young = 1;
901 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
902 }
903 spte = rmap_next(kvm, rmapp, spte);
904 }
905 return young;
906}
907
53a27b39
MT		 908#define RMAP_RECYCLE_THRESHOLD 1000
909
852e3c19 910static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
53a27b39
MT		 911{
912 unsigned long *rmapp;
852e3c19
JR		 913 struct kvm_mmu_page *sp;
914
915 sp = page_header(__pa(spte));
53a27b39 916
852e3c19 917 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
53a27b39 918
3da0dd43 919 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
53a27b39
MT		 920 kvm_flush_remote_tlbs(vcpu->kvm);
921}
922
e930bffe
AA		 923int kvm_age_hva(struct kvm *kvm, unsigned long hva)
924{
3da0dd43 925 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
e930bffe
AA		 926}
927
d6c69ee9 928#ifdef MMU_DEBUG
47ad8e68 929static int is_empty_shadow_page(u64 *spt)
6aa8b732 930{
139bdb2d
AK		 931 u64 *pos;
932 u64 *end;
933
47ad8e68 934 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
3c915510 935 if (is_shadow_present_pte(*pos)) {
b8688d51 936 printk(KERN_ERR "%s: %p %llx\n", __func__,
139bdb2d 937 pos, *pos);
6aa8b732 938 return 0;
139bdb2d 939 }
6aa8b732
AK		 940 return 1;
941}
d6c69ee9 942#endif
6aa8b732 943
4db35314 944static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
260746c0 945{
4db35314 946 ASSERT(is_empty_shadow_page(sp->spt));
7775834a 947 hlist_del(&sp->hash_link);
4db35314
AK		 948 list_del(&sp->link);
949 __free_page(virt_to_page(sp->spt));
2032a93d
LJ		 950 if (!sp->role.direct)
951 __free_page(virt_to_page(sp->gfns));
e8ad9a70 952 kmem_cache_free(mmu_page_header_cache, sp);
f05e70ac 953 ++kvm->arch.n_free_mmu_pages;
260746c0
AK		 954}
955
cea0f0e7
AK		 956static unsigned kvm_page_table_hashfn(gfn_t gfn)
957{
1ae0a13d 958 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
cea0f0e7
AK		 959}
960
25c0de2c 961static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
2032a93d 962 u64 *parent_pte, int direct)
6aa8b732 963{
4db35314 964 struct kvm_mmu_page *sp;
6aa8b732 965
ad312c7c
ZX		 966 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
967 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
2032a93d
LJ		 968 if (!direct)
969 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache,
970 PAGE_SIZE);
4db35314 971 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
f05e70ac 972 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
291f26bc 973 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
4db35314
AK		 974 sp->multimapped = 0;
975 sp->parent_pte = parent_pte;
f05e70ac 976 --vcpu->kvm->arch.n_free_mmu_pages;
4db35314 977 return sp;
6aa8b732
AK		 978}
979
714b93da 980static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
4db35314 981 struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7
AK		 982{
983 struct kvm_pte_chain *pte_chain;
984 struct hlist_node *node;
985 int i;
986
987 if (!parent_pte)
988 return;
4db35314
AK		 989 if (!sp->multimapped) {
990 u64 *old = sp->parent_pte;
cea0f0e7
AK		 991
992 if (!old) {
4db35314 993 sp->parent_pte = parent_pte;
cea0f0e7
AK		 994 return;
995 }
4db35314 996 sp->multimapped = 1;
714b93da 997 pte_chain = mmu_alloc_pte_chain(vcpu);
4db35314
AK		 998 INIT_HLIST_HEAD(&sp->parent_ptes);
999 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 1000 pte_chain->parent_ptes[0] = old;
1001 }
4db35314 1002 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
cea0f0e7
AK		 1003 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
1004 continue;
1005 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
1006 if (!pte_chain->parent_ptes[i]) {
1007 pte_chain->parent_ptes[i] = parent_pte;
1008 return;
1009 }
1010 }
714b93da 1011 pte_chain = mmu_alloc_pte_chain(vcpu);
cea0f0e7 1012 BUG_ON(!pte_chain);
4db35314 1013 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 1014 pte_chain->parent_ptes[0] = parent_pte;
1015}
1016
4db35314 1017static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
cea0f0e7
AK		 1018 u64 *parent_pte)
1019{
1020 struct kvm_pte_chain *pte_chain;
1021 struct hlist_node *node;
1022 int i;
1023
4db35314
AK		 1024 if (!sp->multimapped) {
1025 BUG_ON(sp->parent_pte != parent_pte);
1026 sp->parent_pte = NULL;
cea0f0e7
AK		 1027 return;
1028 }
4db35314 1029 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
cea0f0e7
AK		 1030 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1031 if (!pte_chain->parent_ptes[i])
1032 break;
1033 if (pte_chain->parent_ptes[i] != parent_pte)
1034 continue;
697fe2e2
AK		 1035 while (i + 1 < NR_PTE_CHAIN_ENTRIES
1036 && pte_chain->parent_ptes[i + 1]) {
cea0f0e7
AK		 1037 pte_chain->parent_ptes[i]
1038 = pte_chain->parent_ptes[i + 1];
1039 ++i;
1040 }
1041 pte_chain->parent_ptes[i] = NULL;
697fe2e2
AK		 1042 if (i == 0) {
1043 hlist_del(&pte_chain->link);
90cb0529 1044 mmu_free_pte_chain(pte_chain);
4db35314
AK		 1045 if (hlist_empty(&sp->parent_ptes)) {
1046 sp->multimapped = 0;
1047 sp->parent_pte = NULL;
697fe2e2
AK		 1048 }
1049 }
cea0f0e7
AK		 1050 return;
1051 }
1052 BUG();
1053}
1054
6b18493d 1055static void mmu_parent_walk(struct kvm_mmu_page *sp, mmu_parent_walk_fn fn)
ad8cfbe3
MT		 1056{
1057 struct kvm_pte_chain *pte_chain;
1058 struct hlist_node *node;
1059 struct kvm_mmu_page *parent_sp;
1060 int i;
1061
1062 if (!sp->multimapped && sp->parent_pte) {
1063 parent_sp = page_header(__pa(sp->parent_pte));
1047df1f 1064 fn(parent_sp, sp->parent_pte);
ad8cfbe3
MT		 1065 return;
1066 }
1047df1f 1067
ad8cfbe3
MT		 1068 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1069 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1047df1f
XG		 1070 u64 *spte = pte_chain->parent_ptes[i];
1071
1072 if (!spte)
ad8cfbe3 1073 break;
1047df1f
XG		 1074 parent_sp = page_header(__pa(spte));
1075 fn(parent_sp, spte);
ad8cfbe3
MT		 1076 }
1077}
1078
1047df1f
XG		 1079static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte);
1080static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
0074ff63 1081{
1047df1f 1082 mmu_parent_walk(sp, mark_unsync);
0074ff63
MT		 1083}
1084
1047df1f 1085static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte)
0074ff63 1086{
1047df1f 1087 unsigned int index;
0074ff63 1088
1047df1f
XG		 1089 index = spte - sp->spt;
1090 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
0074ff63 1091 return;
1047df1f 1092 if (sp->unsync_children++)
0074ff63 1093 return;
1047df1f 1094 kvm_mmu_mark_parents_unsync(sp);
0074ff63
MT		 1095}
1096
d761a501
AK		 1097static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1098 struct kvm_mmu_page *sp)
1099{
1100 int i;
1101
1102 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1103 sp->spt[i] = shadow_trap_nonpresent_pte;
1104}
1105
e8bc217a 1106static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
be71e061 1107 struct kvm_mmu_page *sp, bool clear_unsync)
e8bc217a
MT		 1108{
1109 return 1;
1110}
1111
a7052897
MT		 1112static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1113{
1114}
1115
60c8aec6
MT		 1116#define KVM_PAGE_ARRAY_NR 16
1117
1118struct kvm_mmu_pages {
1119 struct mmu_page_and_offset {
1120 struct kvm_mmu_page *sp;
1121 unsigned int idx;
1122 } page[KVM_PAGE_ARRAY_NR];
1123 unsigned int nr;
1124};
1125
0074ff63
MT		 1126#define for_each_unsync_children(bitmap, idx) \
1127 for (idx = find_first_bit(bitmap, 512); \
1128 idx < 512; \
1129 idx = find_next_bit(bitmap, 512, idx+1))
1130
cded19f3
HE		 1131static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1132 int idx)
4731d4c7 1133{
60c8aec6 1134 int i;
4731d4c7 1135
60c8aec6
MT		 1136 if (sp->unsync)
1137 for (i=0; i < pvec->nr; i++)
1138 if (pvec->page[i].sp == sp)
1139 return 0;
1140
1141 pvec->page[pvec->nr].sp = sp;
1142 pvec->page[pvec->nr].idx = idx;
1143 pvec->nr++;
1144 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1145}
1146
1147static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1148 struct kvm_mmu_pages *pvec)
1149{
1150 int i, ret, nr_unsync_leaf = 0;
4731d4c7 1151
0074ff63 1152 for_each_unsync_children(sp->unsync_child_bitmap, i) {
7a8f1a74 1153 struct kvm_mmu_page *child;
4731d4c7
MT		 1154 u64 ent = sp->spt[i];
1155
7a8f1a74
XG		 1156 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1157 goto clear_child_bitmap;
1158
1159 child = page_header(ent & PT64_BASE_ADDR_MASK);
1160
1161 if (child->unsync_children) {
1162 if (mmu_pages_add(pvec, child, i))
1163 return -ENOSPC;
1164
1165 ret = __mmu_unsync_walk(child, pvec);
1166 if (!ret)
1167 goto clear_child_bitmap;
1168 else if (ret > 0)
1169 nr_unsync_leaf += ret;
1170 else
1171 return ret;
1172 } else if (child->unsync) {
1173 nr_unsync_leaf++;
1174 if (mmu_pages_add(pvec, child, i))
1175 return -ENOSPC;
1176 } else
1177 goto clear_child_bitmap;
1178
1179 continue;
1180
1181clear_child_bitmap:
1182 __clear_bit(i, sp->unsync_child_bitmap);
1183 sp->unsync_children--;
1184 WARN_ON((int)sp->unsync_children < 0);
4731d4c7
MT		 1185 }
1186
4731d4c7 1187
60c8aec6
MT		 1188 return nr_unsync_leaf;
1189}
1190
1191static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1192 struct kvm_mmu_pages *pvec)
1193{
1194 if (!sp->unsync_children)
1195 return 0;
1196
1197 mmu_pages_add(pvec, sp, 0);
1198 return __mmu_unsync_walk(sp, pvec);
4731d4c7
MT		 1199}
1200
4731d4c7
MT		 1201static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1202{
1203 WARN_ON(!sp->unsync);
5e1b3ddb 1204 trace_kvm_mmu_sync_page(sp);
4731d4c7
MT		 1205 sp->unsync = 0;
1206 --kvm->stat.mmu_unsync;
1207}
1208
7775834a
XG		 1209static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1210 struct list_head *invalid_list);
1211static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1212 struct list_head *invalid_list);
4731d4c7 1213
f41d335a
XG		 1214#define for_each_gfn_sp(kvm, sp, gfn, pos) \
1215 hlist_for_each_entry(sp, pos, \
7ae680eb
XG		 1216 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1217 if ((sp)->gfn != (gfn)) {} else
1218
f41d335a
XG		 1219#define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \
1220 hlist_for_each_entry(sp, pos, \
7ae680eb
XG		 1221 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1222 if ((sp)->gfn != (gfn) || (sp)->role.direct || \
1223 (sp)->role.invalid) {} else
1224
f918b443 1225/* @sp->gfn should be write-protected at the call site */
1d9dc7e0 1226static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
d98ba053 1227 struct list_head *invalid_list, bool clear_unsync)
4731d4c7 1228{
5b7e0102 1229 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
d98ba053 1230 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
4731d4c7
MT		 1231 return 1;
1232 }
1233
f918b443 1234 if (clear_unsync)
1d9dc7e0 1235 kvm_unlink_unsync_page(vcpu->kvm, sp);
1d9dc7e0 1236
be71e061 1237 if (vcpu->arch.mmu.sync_page(vcpu, sp, clear_unsync)) {
d98ba053 1238 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
4731d4c7
MT		 1239 return 1;
1240 }
1241
1242 kvm_mmu_flush_tlb(vcpu);
4731d4c7
MT		 1243 return 0;
1244}
1245
1d9dc7e0
XG		 1246static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1247 struct kvm_mmu_page *sp)
1248{
d98ba053 1249 LIST_HEAD(invalid_list);
1d9dc7e0
XG		 1250 int ret;
1251
d98ba053 1252 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
be71e061 1253 if (ret)
d98ba053
XG		 1254 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1255
1d9dc7e0
XG		 1256 return ret;
1257}
1258
d98ba053
XG		 1259static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1260 struct list_head *invalid_list)
1d9dc7e0 1261{
d98ba053 1262 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1d9dc7e0
XG		 1263}
1264
9f1a122f
XG		 1265/* @gfn should be write-protected at the call site */
1266static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1267{
9f1a122f 1268 struct kvm_mmu_page *s;
f41d335a 1269 struct hlist_node *node;
d98ba053 1270 LIST_HEAD(invalid_list);
9f1a122f
XG		 1271 bool flush = false;
1272
f41d335a 1273 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
7ae680eb 1274 if (!s->unsync)
9f1a122f
XG		 1275 continue;
1276
1277 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1278 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
be71e061 1279 (vcpu->arch.mmu.sync_page(vcpu, s, true))) {
d98ba053 1280 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
9f1a122f
XG		 1281 continue;
1282 }
1283 kvm_unlink_unsync_page(vcpu->kvm, s);
1284 flush = true;
1285 }
1286
d98ba053 1287 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
9f1a122f
XG		 1288 if (flush)
1289 kvm_mmu_flush_tlb(vcpu);
1290}
1291
60c8aec6
MT		 1292struct mmu_page_path {
1293 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1294 unsigned int idx[PT64_ROOT_LEVEL-1];
4731d4c7
MT		 1295};
1296
60c8aec6
MT		 1297#define for_each_sp(pvec, sp, parents, i) \
1298 for (i = mmu_pages_next(&pvec, &parents, -1), \
1299 sp = pvec.page[i].sp; \
1300 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1301 i = mmu_pages_next(&pvec, &parents, i))
1302
cded19f3
HE		 1303static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1304 struct mmu_page_path *parents,
1305 int i)
60c8aec6
MT		 1306{
1307 int n;
1308
1309 for (n = i+1; n < pvec->nr; n++) {
1310 struct kvm_mmu_page *sp = pvec->page[n].sp;
1311
1312 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1313 parents->idx[0] = pvec->page[n].idx;
1314 return n;
1315 }
1316
1317 parents->parent[sp->role.level-2] = sp;
1318 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1319 }
1320
1321 return n;
1322}
1323
cded19f3 1324static void mmu_pages_clear_parents(struct mmu_page_path *parents)
4731d4c7 1325{
60c8aec6
MT		 1326 struct kvm_mmu_page *sp;
1327 unsigned int level = 0;
1328
1329 do {
1330 unsigned int idx = parents->idx[level];
4731d4c7 1331
60c8aec6
MT		 1332 sp = parents->parent[level];
1333 if (!sp)
1334 return;
1335
1336 --sp->unsync_children;
1337 WARN_ON((int)sp->unsync_children < 0);
1338 __clear_bit(idx, sp->unsync_child_bitmap);
1339 level++;
1340 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
4731d4c7
MT		 1341}
1342
60c8aec6
MT		 1343static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1344 struct mmu_page_path *parents,
1345 struct kvm_mmu_pages *pvec)
4731d4c7 1346{
60c8aec6
MT		 1347 parents->parent[parent->role.level-1] = NULL;
1348 pvec->nr = 0;
1349}
4731d4c7 1350
60c8aec6
MT		 1351static void mmu_sync_children(struct kvm_vcpu *vcpu,
1352 struct kvm_mmu_page *parent)
1353{
1354 int i;
1355 struct kvm_mmu_page *sp;
1356 struct mmu_page_path parents;
1357 struct kvm_mmu_pages pages;
d98ba053 1358 LIST_HEAD(invalid_list);
60c8aec6
MT		 1359
1360 kvm_mmu_pages_init(parent, &parents, &pages);
1361 while (mmu_unsync_walk(parent, &pages)) {
b1a36821
MT		 1362 int protected = 0;
1363
1364 for_each_sp(pages, sp, parents, i)
1365 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1366
1367 if (protected)
1368 kvm_flush_remote_tlbs(vcpu->kvm);
1369
60c8aec6 1370 for_each_sp(pages, sp, parents, i) {
d98ba053 1371 kvm_sync_page(vcpu, sp, &invalid_list);
60c8aec6
MT		 1372 mmu_pages_clear_parents(&parents);
1373 }
d98ba053 1374 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4731d4c7 1375 cond_resched_lock(&vcpu->kvm->mmu_lock);
60c8aec6
MT		 1376 kvm_mmu_pages_init(parent, &parents, &pages);
1377 }
4731d4c7
MT		 1378}
1379
cea0f0e7
AK		 1380static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1381 gfn_t gfn,
1382 gva_t gaddr,
1383 unsigned level,
f6e2c02b 1384 int direct,
41074d07 1385 unsigned access,
f7d9c7b7 1386 u64 *parent_pte)
cea0f0e7
AK		 1387{
1388 union kvm_mmu_page_role role;
cea0f0e7 1389 unsigned quadrant;
9f1a122f 1390 struct kvm_mmu_page *sp;
f41d335a 1391 struct hlist_node *node;
9f1a122f 1392 bool need_sync = false;
cea0f0e7 1393
a770f6f2 1394 role = vcpu->arch.mmu.base_role;
cea0f0e7 1395 role.level = level;
f6e2c02b 1396 role.direct = direct;
84b0c8c6 1397 if (role.direct)
5b7e0102 1398 role.cr4_pae = 0;
41074d07 1399 role.access = access;
b66d8000 1400 if (!tdp_enabled && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
cea0f0e7
AK		 1401 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1402 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1403 role.quadrant = quadrant;
1404 }
f41d335a 1405 for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
7ae680eb
XG		 1406 if (!need_sync && sp->unsync)
1407 need_sync = true;
4731d4c7 1408
7ae680eb
XG		 1409 if (sp->role.word != role.word)
1410 continue;
4731d4c7 1411
7ae680eb
XG		 1412 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1413 break;
e02aa901 1414
7ae680eb
XG		 1415 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1416 if (sp->unsync_children) {
a8eeb04a 1417 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
7ae680eb
XG		 1418 kvm_mmu_mark_parents_unsync(sp);
1419 } else if (sp->unsync)
1420 kvm_mmu_mark_parents_unsync(sp);
e02aa901 1421
7ae680eb
XG		 1422 trace_kvm_mmu_get_page(sp, false);
1423 return sp;
1424 }
dfc5aa00 1425 ++vcpu->kvm->stat.mmu_cache_miss;
2032a93d 1426 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
4db35314
AK		 1427 if (!sp)
1428 return sp;
4db35314
AK		 1429 sp->gfn = gfn;
1430 sp->role = role;
7ae680eb
XG		 1431 hlist_add_head(&sp->hash_link,
1432 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
f6e2c02b 1433 if (!direct) {
b1a36821
MT		 1434 if (rmap_write_protect(vcpu->kvm, gfn))
1435 kvm_flush_remote_tlbs(vcpu->kvm);
9f1a122f
XG		 1436 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1437 kvm_sync_pages(vcpu, gfn);
1438
4731d4c7
MT		 1439 account_shadowed(vcpu->kvm, gfn);
1440 }
131d8279
AK		 1441 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1442 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1443 else
1444 nonpaging_prefetch_page(vcpu, sp);
f691fe1d 1445 trace_kvm_mmu_get_page(sp, true);
4db35314 1446 return sp;
cea0f0e7
AK		 1447}
1448
2d11123a
AK		 1449static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1450 struct kvm_vcpu *vcpu, u64 addr)
1451{
1452 iterator->addr = addr;
1453 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1454 iterator->level = vcpu->arch.mmu.shadow_root_level;
1455 if (iterator->level == PT32E_ROOT_LEVEL) {
1456 iterator->shadow_addr
1457 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1458 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1459 --iterator->level;
1460 if (!iterator->shadow_addr)
1461 iterator->level = 0;
1462 }
1463}
1464
1465static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1466{
1467 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1468 return false;
4d88954d
MT		 1469
1470 if (iterator->level == PT_PAGE_TABLE_LEVEL)
1471 if (is_large_pte(*iterator->sptep))
1472 return false;
1473
2d11123a
AK		 1474 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1475 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1476 return true;
1477}
1478
1479static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1480{
1481 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1482 --iterator->level;
1483}
1484
32ef26a3
AK		 1485static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1486{
1487 u64 spte;
1488
1489 spte = __pa(sp->spt)
1490 | PT_PRESENT_MASK | PT_ACCESSED_MASK
1491 | PT_WRITABLE_MASK | PT_USER_MASK;
1492 *sptep = spte;
1493}
1494
90cb0529 1495static void kvm_mmu_page_unlink_children(struct kvm *kvm,
4db35314 1496 struct kvm_mmu_page *sp)
a436036b 1497{
697fe2e2
AK		 1498 unsigned i;
1499 u64 *pt;
1500 u64 ent;
1501
4db35314 1502 pt = sp->spt;
697fe2e2 1503
697fe2e2
AK		 1504 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1505 ent = pt[i];
1506
05da4558 1507 if (is_shadow_present_pte(ent)) {
776e6633 1508 if (!is_last_spte(ent, sp->role.level)) {
05da4558
MT		 1509 ent &= PT64_BASE_ADDR_MASK;
1510 mmu_page_remove_parent_pte(page_header(ent),
1511 &pt[i]);
1512 } else {
776e6633
MT		 1513 if (is_large_pte(ent))
1514 --kvm->stat.lpages;
be38d276
AK		 1515 drop_spte(kvm, &pt[i],
1516 shadow_trap_nonpresent_pte);
05da4558
MT		 1517 }
1518 }
c7addb90 1519 pt[i] = shadow_trap_nonpresent_pte;
697fe2e2 1520 }
a436036b
AK		 1521}
1522
4db35314 1523static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 1524{
4db35314 1525 mmu_page_remove_parent_pte(sp, parent_pte);
a436036b
AK		 1526}
1527
12b7d28f
AK		 1528static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1529{
1530 int i;
988a2cae 1531 struct kvm_vcpu *vcpu;
12b7d28f 1532
988a2cae
GN		 1533 kvm_for_each_vcpu(i, vcpu, kvm)
1534 vcpu->arch.last_pte_updated = NULL;
12b7d28f
AK		 1535}
1536
31aa2b44 1537static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
a436036b
AK		 1538{
1539 u64 *parent_pte;
1540
4db35314
AK		 1541 while (sp->multimapped || sp->parent_pte) {
1542 if (!sp->multimapped)
1543 parent_pte = sp->parent_pte;
a436036b
AK		 1544 else {
1545 struct kvm_pte_chain *chain;
1546
4db35314 1547 chain = container_of(sp->parent_ptes.first,
a436036b
AK		 1548 struct kvm_pte_chain, link);
1549 parent_pte = chain->parent_ptes[0];
1550 }
697fe2e2 1551 BUG_ON(!parent_pte);
4db35314 1552 kvm_mmu_put_page(sp, parent_pte);
d555c333 1553 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
a436036b 1554 }
31aa2b44
AK		 1555}
1556
60c8aec6 1557static int mmu_zap_unsync_children(struct kvm *kvm,
7775834a
XG		 1558 struct kvm_mmu_page *parent,
1559 struct list_head *invalid_list)
4731d4c7 1560{
60c8aec6
MT		 1561 int i, zapped = 0;
1562 struct mmu_page_path parents;
1563 struct kvm_mmu_pages pages;
4731d4c7 1564
60c8aec6 1565 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
4731d4c7 1566 return 0;
60c8aec6
MT		 1567
1568 kvm_mmu_pages_init(parent, &parents, &pages);
1569 while (mmu_unsync_walk(parent, &pages)) {
1570 struct kvm_mmu_page *sp;
1571
1572 for_each_sp(pages, sp, parents, i) {
7775834a 1573 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
60c8aec6 1574 mmu_pages_clear_parents(&parents);
77662e00 1575 zapped++;
60c8aec6 1576 }
60c8aec6
MT		 1577 kvm_mmu_pages_init(parent, &parents, &pages);
1578 }
1579
1580 return zapped;
4731d4c7
MT		 1581}
1582
7775834a
XG		 1583static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1584 struct list_head *invalid_list)
31aa2b44 1585{
4731d4c7 1586 int ret;
f691fe1d 1587
7775834a 1588 trace_kvm_mmu_prepare_zap_page(sp);
31aa2b44 1589 ++kvm->stat.mmu_shadow_zapped;
7775834a 1590 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
4db35314 1591 kvm_mmu_page_unlink_children(kvm, sp);
31aa2b44 1592 kvm_mmu_unlink_parents(kvm, sp);
f6e2c02b 1593 if (!sp->role.invalid && !sp->role.direct)
5b5c6a5a 1594 unaccount_shadowed(kvm, sp->gfn);
4731d4c7
MT		 1595 if (sp->unsync)
1596 kvm_unlink_unsync_page(kvm, sp);
4db35314 1597 if (!sp->root_count) {
54a4f023
GJ		 1598 /* Count self */
1599 ret++;
7775834a 1600 list_move(&sp->link, invalid_list);
2e53d63a 1601 } else {
5b5c6a5a 1602 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2e53d63a
MT		 1603 kvm_reload_remote_mmus(kvm);
1604 }
7775834a
XG		 1605
1606 sp->role.invalid = 1;
12b7d28f 1607 kvm_mmu_reset_last_pte_updated(kvm);
4731d4c7 1608 return ret;
a436036b
AK		 1609}
1610
7775834a
XG		 1611static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1612 struct list_head *invalid_list)
1613{
1614 struct kvm_mmu_page *sp;
1615
1616 if (list_empty(invalid_list))
1617 return;
1618
1619 kvm_flush_remote_tlbs(kvm);
1620
1621 do {
1622 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1623 WARN_ON(!sp->role.invalid || sp->root_count);
1624 kvm_mmu_free_page(kvm, sp);
1625 } while (!list_empty(invalid_list));
1626
1627}
1628
82ce2c96
IE		 1629/*
1630 * Changing the number of mmu pages allocated to the vm
1631 * Note: if kvm_nr_mmu_pages is too small, you will get dead lock
1632 */
1633void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
1634{
025dbbf3 1635 int used_pages;
d98ba053 1636 LIST_HEAD(invalid_list);
025dbbf3
MT		 1637
1638 used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages;
1639 used_pages = max(0, used_pages);
1640
82ce2c96
IE		 1641 /*
1642 * If we set the number of mmu pages to be smaller be than the
1643 * number of actived pages , we must to free some mmu pages before we
1644 * change the value
1645 */
1646
025dbbf3 1647 if (used_pages > kvm_nr_mmu_pages) {
77662e00
XG		 1648 while (used_pages > kvm_nr_mmu_pages &&
1649 !list_empty(&kvm->arch.active_mmu_pages)) {
82ce2c96
IE		 1650 struct kvm_mmu_page *page;
1651
f05e70ac 1652 page = container_of(kvm->arch.active_mmu_pages.prev,
82ce2c96 1653 struct kvm_mmu_page, link);
d98ba053
XG		 1654 used_pages -= kvm_mmu_prepare_zap_page(kvm, page,
1655 &invalid_list);
82ce2c96 1656 }
d98ba053 1657 kvm_mmu_commit_zap_page(kvm, &invalid_list);
77662e00 1658 kvm_nr_mmu_pages = used_pages;
f05e70ac 1659 kvm->arch.n_free_mmu_pages = 0;
82ce2c96
IE		 1660 }
1661 else
f05e70ac
ZX		 1662 kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages
1663 - kvm->arch.n_alloc_mmu_pages;
82ce2c96 1664
f05e70ac 1665 kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages;
82ce2c96
IE		 1666}
1667
f67a46f4 1668static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
a436036b 1669{
4db35314 1670 struct kvm_mmu_page *sp;
f41d335a 1671 struct hlist_node *node;
d98ba053 1672 LIST_HEAD(invalid_list);
a436036b
AK		 1673 int r;
1674
b8688d51 1675 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
a436036b 1676 r = 0;
f41d335a
XG		 1677
1678 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
7ae680eb
XG		 1679 pgprintk("%s: gfn %lx role %x\n", __func__, gfn,
1680 sp->role.word);
1681 r = 1;
f41d335a 1682 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
7ae680eb 1683 }
d98ba053 1684 kvm_mmu_commit_zap_page(kvm, &invalid_list);
a436036b 1685 return r;
cea0f0e7
AK		 1686}
1687
f67a46f4 1688static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
97a0a01e 1689{
4db35314 1690 struct kvm_mmu_page *sp;
f41d335a 1691 struct hlist_node *node;
d98ba053 1692 LIST_HEAD(invalid_list);
97a0a01e 1693
f41d335a 1694 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
7ae680eb
XG		 1695 pgprintk("%s: zap %lx %x\n",
1696 __func__, gfn, sp->role.word);
f41d335a 1697 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
97a0a01e 1698 }
d98ba053 1699 kvm_mmu_commit_zap_page(kvm, &invalid_list);
97a0a01e
AK		 1700}
1701
38c335f1 1702static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
6aa8b732 1703{
bc6678a3 1704 int slot = memslot_id(kvm, gfn);
4db35314 1705 struct kvm_mmu_page *sp = page_header(__pa(pte));
6aa8b732 1706
291f26bc 1707 __set_bit(slot, sp->slot_bitmap);
6aa8b732
AK		 1708}
1709
6844dec6
MT		 1710static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1711{
1712 int i;
1713 u64 *pt = sp->spt;
1714
1715 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1716 return;
1717
1718 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1719 if (pt[i] == shadow_notrap_nonpresent_pte)
d555c333 1720 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
6844dec6
MT		 1721 }
1722}
1723
74be52e3
SY		 1724/*
1725 * The function is based on mtrr_type_lookup() in
1726 * arch/x86/kernel/cpu/mtrr/generic.c
1727 */
1728static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1729 u64 start, u64 end)
1730{
1731 int i;
1732 u64 base, mask;
1733 u8 prev_match, curr_match;
1734 int num_var_ranges = KVM_NR_VAR_MTRR;
1735
1736 if (!mtrr_state->enabled)
1737 return 0xFF;
1738
1739 /* Make end inclusive end, instead of exclusive */
1740 end--;
1741
1742 /* Look in fixed ranges. Just return the type as per start */
1743 if (mtrr_state->have_fixed && (start < 0x100000)) {
1744 int idx;
1745
1746 if (start < 0x80000) {
1747 idx = 0;
1748 idx += (start >> 16);
1749 return mtrr_state->fixed_ranges[idx];
1750 } else if (start < 0xC0000) {
1751 idx = 1 * 8;
1752 idx += ((start - 0x80000) >> 14);
1753 return mtrr_state->fixed_ranges[idx];
1754 } else if (start < 0x1000000) {
1755 idx = 3 * 8;
1756 idx += ((start - 0xC0000) >> 12);
1757 return mtrr_state->fixed_ranges[idx];
1758 }
1759 }
1760
1761 /*
1762 * Look in variable ranges
1763 * Look of multiple ranges matching this address and pick type
1764 * as per MTRR precedence
1765 */
1766 if (!(mtrr_state->enabled & 2))
1767 return mtrr_state->def_type;
1768
1769 prev_match = 0xFF;
1770 for (i = 0; i < num_var_ranges; ++i) {
1771 unsigned short start_state, end_state;
1772
1773 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1774 continue;
1775
1776 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1777 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1778 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1779 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1780
1781 start_state = ((start & mask) == (base & mask));
1782 end_state = ((end & mask) == (base & mask));
1783 if (start_state != end_state)
1784 return 0xFE;
1785
1786 if ((start & mask) != (base & mask))
1787 continue;
1788
1789 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1790 if (prev_match == 0xFF) {
1791 prev_match = curr_match;
1792 continue;
1793 }
1794
1795 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1796 curr_match == MTRR_TYPE_UNCACHABLE)
1797 return MTRR_TYPE_UNCACHABLE;
1798
1799 if ((prev_match == MTRR_TYPE_WRBACK &&
1800 curr_match == MTRR_TYPE_WRTHROUGH) ||
1801 (prev_match == MTRR_TYPE_WRTHROUGH &&
1802 curr_match == MTRR_TYPE_WRBACK)) {
1803 prev_match = MTRR_TYPE_WRTHROUGH;
1804 curr_match = MTRR_TYPE_WRTHROUGH;
1805 }
1806
1807 if (prev_match != curr_match)
1808 return MTRR_TYPE_UNCACHABLE;
1809 }
1810
1811 if (prev_match != 0xFF)
1812 return prev_match;
1813
1814 return mtrr_state->def_type;
1815}
1816
4b12f0de 1817u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
74be52e3
SY		 1818{
1819 u8 mtrr;
1820
1821 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1822 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1823 if (mtrr == 0xfe || mtrr == 0xff)
1824 mtrr = MTRR_TYPE_WRBACK;
1825 return mtrr;
1826}
4b12f0de 1827EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
74be52e3 1828
9cf5cf5a
XG		 1829static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1830{
1831 trace_kvm_mmu_unsync_page(sp);
1832 ++vcpu->kvm->stat.mmu_unsync;
1833 sp->unsync = 1;
1834
1835 kvm_mmu_mark_parents_unsync(sp);
1836 mmu_convert_notrap(sp);
1837}
1838
1839static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
4731d4c7 1840{
4731d4c7 1841 struct kvm_mmu_page *s;
f41d335a 1842 struct hlist_node *node;
9cf5cf5a 1843
f41d335a 1844 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
7ae680eb 1845 if (s->unsync)
4731d4c7 1846 continue;
9cf5cf5a
XG		 1847 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1848 __kvm_unsync_page(vcpu, s);
4731d4c7 1849 }
4731d4c7
MT		 1850}
1851
1852static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1853 bool can_unsync)
1854{
9cf5cf5a 1855 struct kvm_mmu_page *s;
f41d335a 1856 struct hlist_node *node;
9cf5cf5a
XG		 1857 bool need_unsync = false;
1858
f41d335a 1859 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
36a2e677
XG		 1860 if (!can_unsync)
1861 return 1;
1862
9cf5cf5a 1863 if (s->role.level != PT_PAGE_TABLE_LEVEL)
4731d4c7 1864 return 1;
9cf5cf5a
XG		 1865
1866 if (!need_unsync && !s->unsync) {
36a2e677 1867 if (!oos_shadow)
9cf5cf5a
XG		 1868 return 1;
1869 need_unsync = true;
1870 }
4731d4c7 1871 }
9cf5cf5a
XG		 1872 if (need_unsync)
1873 kvm_unsync_pages(vcpu, gfn);
4731d4c7
MT		 1874 return 0;
1875}
1876
d555c333 1877static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd 1878 unsigned pte_access, int user_fault,
852e3c19 1879 int write_fault, int dirty, int level,
c2d0ee46 1880 gfn_t gfn, pfn_t pfn, bool speculative,
1403283a 1881 bool can_unsync, bool reset_host_protection)
1c4f1fd6
AK		 1882{
1883 u64 spte;
1e73f9dd 1884 int ret = 0;
64d4d521 1885
1c4f1fd6
AK		 1886 /*
1887 * We don't set the accessed bit, since we sometimes want to see
1888 * whether the guest actually used the pte (in order to detect
1889 * demand paging).
1890 */
7b52345e 1891 spte = shadow_base_present_pte | shadow_dirty_mask;
947da538 1892 if (!speculative)
3201b5d9 1893 spte |= shadow_accessed_mask;
1c4f1fd6
AK		 1894 if (!dirty)
1895 pte_access &= ~ACC_WRITE_MASK;
7b52345e
SY		 1896 if (pte_access & ACC_EXEC_MASK)
1897 spte |= shadow_x_mask;
1898 else
1899 spte |= shadow_nx_mask;
1c4f1fd6 1900 if (pte_access & ACC_USER_MASK)
7b52345e 1901 spte |= shadow_user_mask;
852e3c19 1902 if (level > PT_PAGE_TABLE_LEVEL)
05da4558 1903 spte |= PT_PAGE_SIZE_MASK;
4b12f0de
SY		 1904 if (tdp_enabled)
1905 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1906 kvm_is_mmio_pfn(pfn));
1c4f1fd6 1907
1403283a
IE		 1908 if (reset_host_protection)
1909 spte |= SPTE_HOST_WRITEABLE;
1910
35149e21 1911 spte |= (u64)pfn << PAGE_SHIFT;
1c4f1fd6
AK		 1912
1913 if ((pte_access & ACC_WRITE_MASK)
8184dd38
AK		 1914 || (!tdp_enabled && write_fault && !is_write_protection(vcpu)
1915 && !user_fault)) {
1c4f1fd6 1916
852e3c19
JR		 1917 if (level > PT_PAGE_TABLE_LEVEL &&
1918 has_wrprotected_page(vcpu->kvm, gfn, level)) {
38187c83 1919 ret = 1;
be38d276
AK		 1920 drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte);
1921 goto done;
38187c83
MT		 1922 }
1923
1c4f1fd6 1924 spte |= PT_WRITABLE_MASK;
1c4f1fd6 1925
69325a12
AK		 1926 if (!tdp_enabled && !(pte_access & ACC_WRITE_MASK))
1927 spte &= ~PT_USER_MASK;
1928
ecc5589f
MT		 1929 /*
1930 * Optimization: for pte sync, if spte was writable the hash
1931 * lookup is unnecessary (and expensive). Write protection
1932 * is responsibility of mmu_get_page / kvm_sync_page.
1933 * Same reasoning can be applied to dirty page accounting.
1934 */
8dae4445 1935 if (!can_unsync && is_writable_pte(*sptep))
ecc5589f
MT		 1936 goto set_pte;
1937
4731d4c7 1938 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
1c4f1fd6 1939 pgprintk("%s: found shadow page for %lx, marking ro\n",
b8688d51 1940 __func__, gfn);
1e73f9dd 1941 ret = 1;
1c4f1fd6 1942 pte_access &= ~ACC_WRITE_MASK;
8dae4445 1943 if (is_writable_pte(spte))
1c4f1fd6 1944 spte &= ~PT_WRITABLE_MASK;
1c4f1fd6
AK		 1945 }
1946 }
1947
1c4f1fd6
AK		 1948 if (pte_access & ACC_WRITE_MASK)
1949 mark_page_dirty(vcpu->kvm, gfn);
1950
38187c83 1951set_pte:
b79b93f9 1952 update_spte(sptep, spte);
be38d276 1953done:
1e73f9dd
MT		 1954 return ret;
1955}
1956
d555c333 1957static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd
MT		 1958 unsigned pt_access, unsigned pte_access,
1959 int user_fault, int write_fault, int dirty,
852e3c19 1960 int *ptwrite, int level, gfn_t gfn,
1403283a
IE		 1961 pfn_t pfn, bool speculative,
1962 bool reset_host_protection)
1e73f9dd
MT		 1963{
1964 int was_rmapped = 0;
8dae4445 1965 int was_writable = is_writable_pte(*sptep);
53a27b39 1966 int rmap_count;
1e73f9dd
MT		 1967
1968 pgprintk("%s: spte %llx access %x write_fault %d"
1969 " user_fault %d gfn %lx\n",
d555c333 1970 __func__, *sptep, pt_access,
1e73f9dd
MT		 1971 write_fault, user_fault, gfn);
1972
d555c333 1973 if (is_rmap_spte(*sptep)) {
1e73f9dd
MT		 1974 /*
1975 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
1976 * the parent of the now unreachable PTE.
1977 */
852e3c19
JR		 1978 if (level > PT_PAGE_TABLE_LEVEL &&
1979 !is_large_pte(*sptep)) {
1e73f9dd 1980 struct kvm_mmu_page *child;
d555c333 1981 u64 pte = *sptep;
1e73f9dd
MT		 1982
1983 child = page_header(pte & PT64_BASE_ADDR_MASK);
d555c333 1984 mmu_page_remove_parent_pte(child, sptep);
3be2264b
MT		 1985 __set_spte(sptep, shadow_trap_nonpresent_pte);
1986 kvm_flush_remote_tlbs(vcpu->kvm);
d555c333 1987 } else if (pfn != spte_to_pfn(*sptep)) {
1e73f9dd 1988 pgprintk("hfn old %lx new %lx\n",
d555c333 1989 spte_to_pfn(*sptep), pfn);
be38d276 1990 drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte);
91546356 1991 kvm_flush_remote_tlbs(vcpu->kvm);
6bed6b9e
JR		 1992 } else
1993 was_rmapped = 1;
1e73f9dd 1994 }
852e3c19 1995
d555c333 1996 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
1403283a
IE		 1997 dirty, level, gfn, pfn, speculative, true,
1998 reset_host_protection)) {
1e73f9dd
MT		 1999 if (write_fault)
2000 *ptwrite = 1;
5304efde 2001 kvm_mmu_flush_tlb(vcpu);
a378b4e6 2002 }
1e73f9dd 2003
d555c333 2004 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
1e73f9dd 2005 pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n",
d555c333 2006 is_large_pte(*sptep)? "2MB" : "4kB",
a205bc19
JR		 2007 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2008 *sptep, sptep);
d555c333 2009 if (!was_rmapped && is_large_pte(*sptep))
05da4558
MT		 2010 ++vcpu->kvm->stat.lpages;
2011
d555c333 2012 page_header_update_slot(vcpu->kvm, sptep, gfn);
1c4f1fd6 2013 if (!was_rmapped) {
44ad9944 2014 rmap_count = rmap_add(vcpu, sptep, gfn);
acb66dd0 2015 kvm_release_pfn_clean(pfn);
53a27b39 2016 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
852e3c19 2017 rmap_recycle(vcpu, sptep, gfn);
75e68e60 2018 } else {
8dae4445 2019 if (was_writable)
35149e21 2020 kvm_release_pfn_dirty(pfn);
75e68e60 2021 else
35149e21 2022 kvm_release_pfn_clean(pfn);
1c4f1fd6 2023 }
1b7fcd32 2024 if (speculative) {
d555c333 2025 vcpu->arch.last_pte_updated = sptep;
1b7fcd32
AK		 2026 vcpu->arch.last_pte_gfn = gfn;
2027 }
1c4f1fd6
AK		 2028}
2029
6aa8b732
AK		 2030static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2031{
2032}
2033
9f652d21 2034static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
852e3c19 2035 int level, gfn_t gfn, pfn_t pfn)
140754bc 2036{
9f652d21 2037 struct kvm_shadow_walk_iterator iterator;
140754bc 2038 struct kvm_mmu_page *sp;
9f652d21 2039 int pt_write = 0;
140754bc 2040 gfn_t pseudo_gfn;
6aa8b732 2041
9f652d21 2042 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
852e3c19 2043 if (iterator.level == level) {
9f652d21
AK		 2044 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
2045 0, write, 1, &pt_write,
1403283a 2046 level, gfn, pfn, false, true);
9f652d21
AK		 2047 ++vcpu->stat.pf_fixed;
2048 break;
6aa8b732
AK		 2049 }
2050
9f652d21 2051 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
c9fa0b3b
LJ		 2052 u64 base_addr = iterator.addr;
2053
2054 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2055 pseudo_gfn = base_addr >> PAGE_SHIFT;
9f652d21
AK		 2056 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2057 iterator.level - 1,
2058 1, ACC_ALL, iterator.sptep);
2059 if (!sp) {
2060 pgprintk("nonpaging_map: ENOMEM\n");
2061 kvm_release_pfn_clean(pfn);
2062 return -ENOMEM;
2063 }
140754bc 2064
d555c333
AK		 2065 __set_spte(iterator.sptep,
2066 __pa(sp->spt)
2067 | PT_PRESENT_MASK | PT_WRITABLE_MASK
2068 | shadow_user_mask | shadow_x_mask);
9f652d21
AK		 2069 }
2070 }
2071 return pt_write;
6aa8b732
AK		 2072}
2073
bf998156
HY		 2074static void kvm_send_hwpoison_signal(struct kvm *kvm, gfn_t gfn)
2075{
2076 char buf[1];
2077 void __user *hva;
2078 int r;
2079
2080 /* Touch the page, so send SIGBUS */
2081 hva = (void __user *)gfn_to_hva(kvm, gfn);
2082 r = copy_from_user(buf, hva, 1);
2083}
2084
2085static int kvm_handle_bad_page(struct kvm *kvm, gfn_t gfn, pfn_t pfn)
2086{
2087 kvm_release_pfn_clean(pfn);
2088 if (is_hwpoison_pfn(pfn)) {
2089 kvm_send_hwpoison_signal(kvm, gfn);
2090 return 0;
edba23e5
GN		 2091 } else if (is_fault_pfn(pfn))
2092 return -EFAULT;
2093
bf998156
HY		 2094 return 1;
2095}
2096
10589a46
MT		 2097static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
2098{
2099 int r;
852e3c19 2100 int level;
35149e21 2101 pfn_t pfn;
e930bffe 2102 unsigned long mmu_seq;
aaee2c94 2103
852e3c19
JR		 2104 level = mapping_level(vcpu, gfn);
2105
2106 /*
2107 * This path builds a PAE pagetable - so we can map 2mb pages at
2108 * maximum. Therefore check if the level is larger than that.
2109 */
2110 if (level > PT_DIRECTORY_LEVEL)
2111 level = PT_DIRECTORY_LEVEL;
2112
2113 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
05da4558 2114
e930bffe 2115 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2116 smp_rmb();
35149e21 2117 pfn = gfn_to_pfn(vcpu->kvm, gfn);
aaee2c94 2118
d196e343 2119 /* mmio */
bf998156
HY		 2120 if (is_error_pfn(pfn))
2121 return kvm_handle_bad_page(vcpu->kvm, gfn, pfn);
d196e343 2122
aaee2c94 2123 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2124 if (mmu_notifier_retry(vcpu, mmu_seq))
2125 goto out_unlock;
eb787d10 2126 kvm_mmu_free_some_pages(vcpu);
852e3c19 2127 r = __direct_map(vcpu, v, write, level, gfn, pfn);
aaee2c94
MT		 2128 spin_unlock(&vcpu->kvm->mmu_lock);
2129
aaee2c94 2130
10589a46 2131 return r;
e930bffe
AA		 2132
2133out_unlock:
2134 spin_unlock(&vcpu->kvm->mmu_lock);
2135 kvm_release_pfn_clean(pfn);
2136 return 0;
10589a46
MT		 2137}
2138
2139
17ac10ad
AK		 2140static void mmu_free_roots(struct kvm_vcpu *vcpu)
2141{
2142 int i;
4db35314 2143 struct kvm_mmu_page *sp;
d98ba053 2144 LIST_HEAD(invalid_list);
17ac10ad 2145
ad312c7c 2146 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
7b53aa56 2147 return;
aaee2c94 2148 spin_lock(&vcpu->kvm->mmu_lock);
ad312c7c
ZX		 2149 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2150 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad 2151
4db35314
AK		 2152 sp = page_header(root);
2153 --sp->root_count;
d98ba053
XG		 2154 if (!sp->root_count && sp->role.invalid) {
2155 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2156 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2157 }
ad312c7c 2158 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
aaee2c94 2159 spin_unlock(&vcpu->kvm->mmu_lock);
17ac10ad
AK		 2160 return;
2161 }
17ac10ad 2162 for (i = 0; i < 4; ++i) {
ad312c7c 2163 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad 2164
417726a3 2165 if (root) {
417726a3 2166 root &= PT64_BASE_ADDR_MASK;
4db35314
AK		 2167 sp = page_header(root);
2168 --sp->root_count;
2e53d63a 2169 if (!sp->root_count && sp->role.invalid)
d98ba053
XG		 2170 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2171 &invalid_list);
417726a3 2172 }
ad312c7c 2173 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2174 }
d98ba053 2175 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
aaee2c94 2176 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2177 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
17ac10ad
AK		 2178}
2179
8986ecc0
MT		 2180static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2181{
2182 int ret = 0;
2183
2184 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
a8eeb04a 2185 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
8986ecc0
MT		 2186 ret = 1;
2187 }
2188
2189 return ret;
2190}
2191
2192static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
17ac10ad
AK		 2193{
2194 int i;
cea0f0e7 2195 gfn_t root_gfn;
4db35314 2196 struct kvm_mmu_page *sp;
f6e2c02b 2197 int direct = 0;
6de4f3ad 2198 u64 pdptr;
3bb65a22 2199
ad312c7c 2200 root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
17ac10ad 2201
ad312c7c
ZX		 2202 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2203 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad
AK		 2204
2205 ASSERT(!VALID_PAGE(root));
8986ecc0
MT		 2206 if (mmu_check_root(vcpu, root_gfn))
2207 return 1;
5a7388c2
EN		 2208 if (tdp_enabled) {
2209 direct = 1;
2210 root_gfn = 0;
2211 }
8facbbff 2212 spin_lock(&vcpu->kvm->mmu_lock);
24955b6c 2213 kvm_mmu_free_some_pages(vcpu);
4db35314 2214 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
f6e2c02b 2215 PT64_ROOT_LEVEL, direct,
fb72d167 2216 ACC_ALL, NULL);
4db35314
AK		 2217 root = __pa(sp->spt);
2218 ++sp->root_count;
8facbbff 2219 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2220 vcpu->arch.mmu.root_hpa = root;
8986ecc0 2221 return 0;
17ac10ad 2222 }
f6e2c02b 2223 direct = !is_paging(vcpu);
17ac10ad 2224 for (i = 0; i < 4; ++i) {
ad312c7c 2225 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad
AK		 2226
2227 ASSERT(!VALID_PAGE(root));
ad312c7c 2228 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
6de4f3ad 2229 pdptr = kvm_pdptr_read(vcpu, i);
43a3795a 2230 if (!is_present_gpte(pdptr)) {
ad312c7c 2231 vcpu->arch.mmu.pae_root[i] = 0;
417726a3
AK		 2232 continue;
2233 }
6de4f3ad 2234 root_gfn = pdptr >> PAGE_SHIFT;
ad312c7c 2235 } else if (vcpu->arch.mmu.root_level == 0)
cea0f0e7 2236 root_gfn = 0;
8986ecc0
MT		 2237 if (mmu_check_root(vcpu, root_gfn))
2238 return 1;
5a7388c2
EN		 2239 if (tdp_enabled) {
2240 direct = 1;
2241 root_gfn = i << 30;
2242 }
8facbbff 2243 spin_lock(&vcpu->kvm->mmu_lock);
24955b6c 2244 kvm_mmu_free_some_pages(vcpu);
4db35314 2245 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
f6e2c02b 2246 PT32_ROOT_LEVEL, direct,
f7d9c7b7 2247 ACC_ALL, NULL);
4db35314
AK		 2248 root = __pa(sp->spt);
2249 ++sp->root_count;
8facbbff
AK		 2250 spin_unlock(&vcpu->kvm->mmu_lock);
2251
ad312c7c 2252 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
17ac10ad 2253 }
ad312c7c 2254 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
8986ecc0 2255 return 0;
17ac10ad
AK		 2256}
2257
0ba73cda
MT		 2258static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2259{
2260 int i;
2261 struct kvm_mmu_page *sp;
2262
2263 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2264 return;
2265 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2266 hpa_t root = vcpu->arch.mmu.root_hpa;
2267 sp = page_header(root);
2268 mmu_sync_children(vcpu, sp);
2269 return;
2270 }
2271 for (i = 0; i < 4; ++i) {
2272 hpa_t root = vcpu->arch.mmu.pae_root[i];
2273
8986ecc0 2274 if (root && VALID_PAGE(root)) {
0ba73cda
MT		 2275 root &= PT64_BASE_ADDR_MASK;
2276 sp = page_header(root);
2277 mmu_sync_children(vcpu, sp);
2278 }
2279 }
2280}
2281
2282void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2283{
2284 spin_lock(&vcpu->kvm->mmu_lock);
2285 mmu_sync_roots(vcpu);
6cffe8ca 2286 spin_unlock(&vcpu->kvm->mmu_lock);
0ba73cda
MT		 2287}
2288
1871c602
GN		 2289static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2290 u32 access, u32 *error)
6aa8b732 2291{
1871c602
GN		 2292 if (error)
2293 *error = 0;
6aa8b732
AK		 2294 return vaddr;
2295}
2296
2297static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3f3e7124 2298 u32 error_code)
6aa8b732 2299{
e833240f 2300 gfn_t gfn;
e2dec939 2301 int r;
6aa8b732 2302
b8688d51 2303 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
e2dec939
AK		 2304 r = mmu_topup_memory_caches(vcpu);
2305 if (r)
2306 return r;
714b93da 2307
6aa8b732 2308 ASSERT(vcpu);
ad312c7c 2309 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2310
e833240f 2311 gfn = gva >> PAGE_SHIFT;
6aa8b732 2312
e833240f
AK		 2313 return nonpaging_map(vcpu, gva & PAGE_MASK,
2314 error_code & PFERR_WRITE_MASK, gfn);
6aa8b732
AK		 2315}
2316
fb72d167
JR		 2317static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
2318 u32 error_code)
2319{
35149e21 2320 pfn_t pfn;
fb72d167 2321 int r;
852e3c19 2322 int level;
05da4558 2323 gfn_t gfn = gpa >> PAGE_SHIFT;
e930bffe 2324 unsigned long mmu_seq;
fb72d167
JR		 2325
2326 ASSERT(vcpu);
2327 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2328
2329 r = mmu_topup_memory_caches(vcpu);
2330 if (r)
2331 return r;
2332
852e3c19
JR		 2333 level = mapping_level(vcpu, gfn);
2334
2335 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2336
e930bffe 2337 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2338 smp_rmb();
35149e21 2339 pfn = gfn_to_pfn(vcpu->kvm, gfn);
bf998156
HY		 2340 if (is_error_pfn(pfn))
2341 return kvm_handle_bad_page(vcpu->kvm, gfn, pfn);
fb72d167 2342 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2343 if (mmu_notifier_retry(vcpu, mmu_seq))
2344 goto out_unlock;
fb72d167
JR		 2345 kvm_mmu_free_some_pages(vcpu);
2346 r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
852e3c19 2347 level, gfn, pfn);
fb72d167 2348 spin_unlock(&vcpu->kvm->mmu_lock);
fb72d167
JR		 2349
2350 return r;
e930bffe
AA		 2351
2352out_unlock:
2353 spin_unlock(&vcpu->kvm->mmu_lock);
2354 kvm_release_pfn_clean(pfn);
2355 return 0;
fb72d167
JR		 2356}
2357
6aa8b732
AK		 2358static void nonpaging_free(struct kvm_vcpu *vcpu)
2359{
17ac10ad 2360 mmu_free_roots(vcpu);
6aa8b732
AK		 2361}
2362
2363static int nonpaging_init_context(struct kvm_vcpu *vcpu)
2364{
ad312c7c 2365 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2366
2367 context->new_cr3 = nonpaging_new_cr3;
2368 context->page_fault = nonpaging_page_fault;
6aa8b732
AK		 2369 context->gva_to_gpa = nonpaging_gva_to_gpa;
2370 context->free = nonpaging_free;
c7addb90 2371 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2372 context->sync_page = nonpaging_sync_page;
a7052897 2373 context->invlpg = nonpaging_invlpg;
cea0f0e7 2374 context->root_level = 0;
6aa8b732 2375 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2376 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2377 return 0;
2378}
2379
d835dfec 2380void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
6aa8b732 2381{
1165f5fe 2382 ++vcpu->stat.tlb_flush;
a8eeb04a 2383 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
6aa8b732
AK		 2384}
2385
2386static void paging_new_cr3(struct kvm_vcpu *vcpu)
2387{
b8688d51 2388 pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3);
cea0f0e7 2389 mmu_free_roots(vcpu);
6aa8b732
AK		 2390}
2391
6aa8b732
AK		 2392static void inject_page_fault(struct kvm_vcpu *vcpu,
2393 u64 addr,
2394 u32 err_code)
2395{
c3c91fee 2396 kvm_inject_page_fault(vcpu, addr, err_code);
6aa8b732
AK		 2397}
2398
6aa8b732
AK		 2399static void paging_free(struct kvm_vcpu *vcpu)
2400{
2401 nonpaging_free(vcpu);
2402}
2403
82725b20
DE		 2404static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level)
2405{
2406 int bit7;
2407
2408 bit7 = (gpte >> 7) & 1;
2409 return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0;
2410}
2411
6aa8b732
AK		 2412#define PTTYPE 64
2413#include "paging_tmpl.h"
2414#undef PTTYPE
2415
2416#define PTTYPE 32
2417#include "paging_tmpl.h"
2418#undef PTTYPE
2419
82725b20
DE		 2420static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
2421{
2422 struct kvm_mmu *context = &vcpu->arch.mmu;
2423 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2424 u64 exb_bit_rsvd = 0;
2425
2426 if (!is_nx(vcpu))
2427 exb_bit_rsvd = rsvd_bits(63, 63);
2428 switch (level) {
2429 case PT32_ROOT_LEVEL:
2430 /* no rsvd bits for 2 level 4K page table entries */
2431 context->rsvd_bits_mask[0][1] = 0;
2432 context->rsvd_bits_mask[0][0] = 0;
f815bce8
XG		 2433 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
2434
2435 if (!is_pse(vcpu)) {
2436 context->rsvd_bits_mask[1][1] = 0;
2437 break;
2438 }
2439
82725b20
DE		 2440 if (is_cpuid_PSE36())
2441 /* 36bits PSE 4MB page */
2442 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2443 else
2444 /* 32 bits PSE 4MB page */
2445 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
82725b20
DE		 2446 break;
2447 case PT32E_ROOT_LEVEL:
20c466b5
DE		 2448 context->rsvd_bits_mask[0][2] =
2449 rsvd_bits(maxphyaddr, 63) |
2450 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
82725b20 2451 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2452 rsvd_bits(maxphyaddr, 62); /* PDE */
82725b20
DE		 2453 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2454 rsvd_bits(maxphyaddr, 62); /* PTE */
2455 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2456 rsvd_bits(maxphyaddr, 62) |
2457 rsvd_bits(13, 20); /* large page */
f815bce8 2458 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
82725b20
DE		 2459 break;
2460 case PT64_ROOT_LEVEL:
2461 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2462 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2463 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2464 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2465 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2466 rsvd_bits(maxphyaddr, 51);
82725b20
DE		 2467 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2468 rsvd_bits(maxphyaddr, 51);
2469 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
e04da980
JR		 2470 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
2471 rsvd_bits(maxphyaddr, 51) |
2472 rsvd_bits(13, 29);
82725b20 2473 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4c26b4cd
SY		 2474 rsvd_bits(maxphyaddr, 51) |
2475 rsvd_bits(13, 20); /* large page */
f815bce8 2476 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
82725b20
DE		 2477 break;
2478 }
2479}
2480
17ac10ad 2481static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level)
6aa8b732 2482{
ad312c7c 2483 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2484
2485 ASSERT(is_pae(vcpu));
2486 context->new_cr3 = paging_new_cr3;
2487 context->page_fault = paging64_page_fault;
6aa8b732 2488 context->gva_to_gpa = paging64_gva_to_gpa;
c7addb90 2489 context->prefetch_page = paging64_prefetch_page;
e8bc217a 2490 context->sync_page = paging64_sync_page;
a7052897 2491 context->invlpg = paging64_invlpg;
6aa8b732 2492 context->free = paging_free;
17ac10ad
AK		 2493 context->root_level = level;
2494 context->shadow_root_level = level;
17c3ba9d 2495 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2496 return 0;
2497}
2498
17ac10ad
AK		 2499static int paging64_init_context(struct kvm_vcpu *vcpu)
2500{
82725b20 2501 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
17ac10ad
AK		 2502 return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL);
2503}
2504
6aa8b732
AK		 2505static int paging32_init_context(struct kvm_vcpu *vcpu)
2506{
ad312c7c 2507 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732 2508
82725b20 2509 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
6aa8b732
AK		 2510 context->new_cr3 = paging_new_cr3;
2511 context->page_fault = paging32_page_fault;
6aa8b732
AK		 2512 context->gva_to_gpa = paging32_gva_to_gpa;
2513 context->free = paging_free;
c7addb90 2514 context->prefetch_page = paging32_prefetch_page;
e8bc217a 2515 context->sync_page = paging32_sync_page;
a7052897 2516 context->invlpg = paging32_invlpg;
6aa8b732
AK		 2517 context->root_level = PT32_ROOT_LEVEL;
2518 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2519 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2520 return 0;
2521}
2522
2523static int paging32E_init_context(struct kvm_vcpu *vcpu)
2524{
82725b20 2525 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
17ac10ad 2526 return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
6aa8b732
AK		 2527}
2528
fb72d167
JR		 2529static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2530{
2531 struct kvm_mmu *context = &vcpu->arch.mmu;
2532
2533 context->new_cr3 = nonpaging_new_cr3;
2534 context->page_fault = tdp_page_fault;
2535 context->free = nonpaging_free;
2536 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2537 context->sync_page = nonpaging_sync_page;
a7052897 2538 context->invlpg = nonpaging_invlpg;
67253af5 2539 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
fb72d167
JR		 2540 context->root_hpa = INVALID_PAGE;
2541
2542 if (!is_paging(vcpu)) {
2543 context->gva_to_gpa = nonpaging_gva_to_gpa;
2544 context->root_level = 0;
2545 } else if (is_long_mode(vcpu)) {
82725b20 2546 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
fb72d167
JR		 2547 context->gva_to_gpa = paging64_gva_to_gpa;
2548 context->root_level = PT64_ROOT_LEVEL;
2549 } else if (is_pae(vcpu)) {
82725b20 2550 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
fb72d167
JR		 2551 context->gva_to_gpa = paging64_gva_to_gpa;
2552 context->root_level = PT32E_ROOT_LEVEL;
2553 } else {
82725b20 2554 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
fb72d167
JR		 2555 context->gva_to_gpa = paging32_gva_to_gpa;
2556 context->root_level = PT32_ROOT_LEVEL;
2557 }
2558
2559 return 0;
2560}
2561
2562static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
6aa8b732 2563{
a770f6f2
AK		 2564 int r;
2565
6aa8b732 2566 ASSERT(vcpu);
ad312c7c 2567 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732
AK		 2568
2569 if (!is_paging(vcpu))
a770f6f2 2570 r = nonpaging_init_context(vcpu);
a9058ecd 2571 else if (is_long_mode(vcpu))
a770f6f2 2572 r = paging64_init_context(vcpu);
6aa8b732 2573 else if (is_pae(vcpu))
a770f6f2 2574 r = paging32E_init_context(vcpu);
6aa8b732 2575 else
a770f6f2
AK		 2576 r = paging32_init_context(vcpu);
2577
5b7e0102 2578 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3dbe1415 2579 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
a770f6f2
AK		 2580
2581 return r;
6aa8b732
AK		 2582}
2583
fb72d167
JR		 2584static int init_kvm_mmu(struct kvm_vcpu *vcpu)
2585{
35149e21
AL		 2586 vcpu->arch.update_pte.pfn = bad_pfn;
2587
fb72d167
JR		 2588 if (tdp_enabled)
2589 return init_kvm_tdp_mmu(vcpu);
2590 else
2591 return init_kvm_softmmu(vcpu);
2592}
2593
6aa8b732
AK		 2594static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
2595{
2596 ASSERT(vcpu);
62ad0755
SY		 2597 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
2598 /* mmu.free() should set root_hpa = INVALID_PAGE */
ad312c7c 2599 vcpu->arch.mmu.free(vcpu);
6aa8b732
AK		 2600}
2601
2602int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
17c3ba9d
AK		 2603{
2604 destroy_kvm_mmu(vcpu);
2605 return init_kvm_mmu(vcpu);
2606}
8668a3c4 2607EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
17c3ba9d
AK		 2608
2609int kvm_mmu_load(struct kvm_vcpu *vcpu)
6aa8b732 2610{
714b93da
AK		 2611 int r;
2612
e2dec939 2613 r = mmu_topup_memory_caches(vcpu);
17c3ba9d
AK		 2614 if (r)
2615 goto out;
8986ecc0 2616 r = mmu_alloc_roots(vcpu);
8facbbff 2617 spin_lock(&vcpu->kvm->mmu_lock);
0ba73cda 2618 mmu_sync_roots(vcpu);
aaee2c94 2619 spin_unlock(&vcpu->kvm->mmu_lock);
8986ecc0
MT		 2620 if (r)
2621 goto out;
3662cb1c 2622 /* set_cr3() should ensure TLB has been flushed */
ad312c7c 2623 kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
714b93da
AK		 2624out:
2625 return r;
6aa8b732 2626}
17c3ba9d
AK		 2627EXPORT_SYMBOL_GPL(kvm_mmu_load);
2628
2629void kvm_mmu_unload(struct kvm_vcpu *vcpu)
2630{
2631 mmu_free_roots(vcpu);
2632}
6aa8b732 2633
09072daf 2634static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
4db35314 2635 struct kvm_mmu_page *sp,
ac1b714e
AK		 2636 u64 *spte)
2637{
2638 u64 pte;
2639 struct kvm_mmu_page *child;
2640
2641 pte = *spte;
c7addb90 2642 if (is_shadow_present_pte(pte)) {
776e6633 2643 if (is_last_spte(pte, sp->role.level))
be38d276 2644 drop_spte(vcpu->kvm, spte, shadow_trap_nonpresent_pte);
ac1b714e
AK		 2645 else {
2646 child = page_header(pte & PT64_BASE_ADDR_MASK);
90cb0529 2647 mmu_page_remove_parent_pte(child, spte);
ac1b714e
AK		 2648 }
2649 }
d555c333 2650 __set_spte(spte, shadow_trap_nonpresent_pte);
05da4558
MT		 2651 if (is_large_pte(pte))
2652 --vcpu->kvm->stat.lpages;
ac1b714e
AK		 2653}
2654
0028425f 2655static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4db35314 2656 struct kvm_mmu_page *sp,
0028425f 2657 u64 *spte,
489f1d65 2658 const void *new)
0028425f 2659{
30945387 2660 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
7e4e4056
JR		 2661 ++vcpu->kvm->stat.mmu_pde_zapped;
2662 return;
30945387 2663 }
0028425f 2664
4cee5764 2665 ++vcpu->kvm->stat.mmu_pte_updated;
5b7e0102 2666 if (!sp->role.cr4_pae)
489f1d65 2667 paging32_update_pte(vcpu, sp, spte, new);
0028425f 2668 else
489f1d65 2669 paging64_update_pte(vcpu, sp, spte, new);
0028425f
AK		 2670}
2671
79539cec
AK		 2672static bool need_remote_flush(u64 old, u64 new)
2673{
2674 if (!is_shadow_present_pte(old))
2675 return false;
2676 if (!is_shadow_present_pte(new))
2677 return true;
2678 if ((old ^ new) & PT64_BASE_ADDR_MASK)
2679 return true;
2680 old ^= PT64_NX_MASK;
2681 new ^= PT64_NX_MASK;
2682 return (old & ~new & PT64_PERM_MASK) != 0;
2683}
2684
0671a8e7
XG		 2685static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
2686 bool remote_flush, bool local_flush)
79539cec 2687{
0671a8e7
XG		 2688 if (zap_page)
2689 return;
2690
2691 if (remote_flush)
79539cec 2692 kvm_flush_remote_tlbs(vcpu->kvm);
0671a8e7 2693 else if (local_flush)
79539cec
AK		 2694 kvm_mmu_flush_tlb(vcpu);
2695}
2696
12b7d28f
AK		 2697static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
2698{
ad312c7c 2699 u64 *spte = vcpu->arch.last_pte_updated;
12b7d28f 2700
7b52345e 2701 return !!(spte && (*spte & shadow_accessed_mask));
12b7d28f
AK		 2702}
2703
d7824fff 2704static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
72016f3a 2705 u64 gpte)
d7824fff
AK		 2706{
2707 gfn_t gfn;
35149e21 2708 pfn_t pfn;
d7824fff 2709
43a3795a 2710 if (!is_present_gpte(gpte))
d7824fff
AK		 2711 return;
2712 gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
72dc67a6 2713
e930bffe 2714 vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2715 smp_rmb();
35149e21 2716 pfn = gfn_to_pfn(vcpu->kvm, gfn);
72dc67a6 2717
35149e21
AL		 2718 if (is_error_pfn(pfn)) {
2719 kvm_release_pfn_clean(pfn);
d196e343
AK		 2720 return;
2721 }
d7824fff 2722 vcpu->arch.update_pte.gfn = gfn;
35149e21 2723 vcpu->arch.update_pte.pfn = pfn;
d7824fff
AK		 2724}
2725
1b7fcd32
AK		 2726static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
2727{
2728 u64 *spte = vcpu->arch.last_pte_updated;
2729
2730 if (spte
2731 && vcpu->arch.last_pte_gfn == gfn
2732 && shadow_accessed_mask
2733 && !(*spte & shadow_accessed_mask)
2734 && is_shadow_present_pte(*spte))
2735 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
2736}
2737
09072daf 2738void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
ad218f85
MT		 2739 const u8 *new, int bytes,
2740 bool guest_initiated)
da4a00f0 2741{
9b7a0325 2742 gfn_t gfn = gpa >> PAGE_SHIFT;
4db35314 2743 struct kvm_mmu_page *sp;
f41d335a 2744 struct hlist_node *node;
d98ba053 2745 LIST_HEAD(invalid_list);
489f1d65 2746 u64 entry, gentry;
9b7a0325 2747 u64 *spte;
9b7a0325 2748 unsigned offset = offset_in_page(gpa);
0e7bc4b9 2749 unsigned pte_size;
9b7a0325 2750 unsigned page_offset;
0e7bc4b9 2751 unsigned misaligned;
fce0657f 2752 unsigned quadrant;
9b7a0325 2753 int level;
86a5ba02 2754 int flooded = 0;
ac1b714e 2755 int npte;
489f1d65 2756 int r;
08e850c6 2757 int invlpg_counter;
0671a8e7
XG		 2758 bool remote_flush, local_flush, zap_page;
2759
2760 zap_page = remote_flush = local_flush = false;
9b7a0325 2761
b8688d51 2762 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
72016f3a 2763
08e850c6 2764 invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter);
72016f3a
AK		 2765
2766 /*
2767 * Assume that the pte write on a page table of the same type
2768 * as the current vcpu paging mode. This is nearly always true
2769 * (might be false while changing modes). Note it is verified later
2770 * by update_pte().
2771 */
08e850c6 2772 if ((is_pae(vcpu) && bytes == 4) || !new) {
72016f3a 2773 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
08e850c6
AK		 2774 if (is_pae(vcpu)) {
2775 gpa &= ~(gpa_t)7;
2776 bytes = 8;
2777 }
2778 r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8));
72016f3a
AK		 2779 if (r)
2780 gentry = 0;
08e850c6
AK		 2781 new = (const u8 *)&gentry;
2782 }
2783
2784 switch (bytes) {
2785 case 4:
2786 gentry = *(const u32 *)new;
2787 break;
2788 case 8:
2789 gentry = *(const u64 *)new;
2790 break;
2791 default:
2792 gentry = 0;
2793 break;
72016f3a
AK		 2794 }
2795
2796 mmu_guess_page_from_pte_write(vcpu, gpa, gentry);
aaee2c94 2797 spin_lock(&vcpu->kvm->mmu_lock);
08e850c6
AK		 2798 if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter)
2799 gentry = 0;
1b7fcd32 2800 kvm_mmu_access_page(vcpu, gfn);
eb787d10 2801 kvm_mmu_free_some_pages(vcpu);
4cee5764 2802 ++vcpu->kvm->stat.mmu_pte_write;
c7addb90 2803 kvm_mmu_audit(vcpu, "pre pte write");
ad218f85
MT		 2804 if (guest_initiated) {
2805 if (gfn == vcpu->arch.last_pt_write_gfn
2806 && !last_updated_pte_accessed(vcpu)) {
2807 ++vcpu->arch.last_pt_write_count;
2808 if (vcpu->arch.last_pt_write_count >= 3)
2809 flooded = 1;
2810 } else {
2811 vcpu->arch.last_pt_write_gfn = gfn;
2812 vcpu->arch.last_pt_write_count = 1;
2813 vcpu->arch.last_pte_updated = NULL;
2814 }
86a5ba02 2815 }
3246af0e 2816
f41d335a 2817 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
5b7e0102 2818 pte_size = sp->role.cr4_pae ? 8 : 4;
0e7bc4b9 2819 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
e925c5ba 2820 misaligned |= bytes < 4;
86a5ba02 2821 if (misaligned || flooded) {
0e7bc4b9
AK		 2822 /*
2823 * Misaligned accesses are too much trouble to fix
2824 * up; also, they usually indicate a page is not used
2825 * as a page table.
86a5ba02
AK		 2826 *
2827 * If we're seeing too many writes to a page,
2828 * it may no longer be a page table, or we may be
2829 * forking, in which case it is better to unmap the
2830 * page.
0e7bc4b9
AK		 2831 */
2832 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4db35314 2833 gpa, bytes, sp->role.word);
0671a8e7 2834 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
f41d335a 2835 &invalid_list);
4cee5764 2836 ++vcpu->kvm->stat.mmu_flooded;
0e7bc4b9
AK		 2837 continue;
2838 }
9b7a0325 2839 page_offset = offset;
4db35314 2840 level = sp->role.level;
ac1b714e 2841 npte = 1;
5b7e0102 2842 if (!sp->role.cr4_pae) {
ac1b714e
AK		 2843 page_offset <<= 1; /* 32->64 */
2844 /*
2845 * A 32-bit pde maps 4MB while the shadow pdes map
2846 * only 2MB. So we need to double the offset again
2847 * and zap two pdes instead of one.
2848 */
2849 if (level == PT32_ROOT_LEVEL) {
6b8d0f9b 2850 page_offset &= ~7; /* kill rounding error */
ac1b714e
AK		 2851 page_offset <<= 1;
2852 npte = 2;
2853 }
fce0657f 2854 quadrant = page_offset >> PAGE_SHIFT;
9b7a0325 2855 page_offset &= ~PAGE_MASK;
4db35314 2856 if (quadrant != sp->role.quadrant)
fce0657f 2857 continue;
9b7a0325 2858 }
0671a8e7 2859 local_flush = true;
4db35314 2860 spte = &sp->spt[page_offset / sizeof(*spte)];
ac1b714e 2861 while (npte--) {
79539cec 2862 entry = *spte;
4db35314 2863 mmu_pte_write_zap_pte(vcpu, sp, spte);
72016f3a
AK		 2864 if (gentry)
2865 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
0671a8e7
XG		 2866 if (!remote_flush && need_remote_flush(entry, *spte))
2867 remote_flush = true;
ac1b714e 2868 ++spte;
9b7a0325 2869 }
9b7a0325 2870 }
0671a8e7 2871 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
d98ba053 2872 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
c7addb90 2873 kvm_mmu_audit(vcpu, "post pte write");
aaee2c94 2874 spin_unlock(&vcpu->kvm->mmu_lock);
35149e21
AL		 2875 if (!is_error_pfn(vcpu->arch.update_pte.pfn)) {
2876 kvm_release_pfn_clean(vcpu->arch.update_pte.pfn);
2877 vcpu->arch.update_pte.pfn = bad_pfn;
d7824fff 2878 }
da4a00f0
AK		 2879}
2880
a436036b
AK		 2881int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2882{
10589a46
MT		 2883 gpa_t gpa;
2884 int r;
a436036b 2885
60f24784
AK		 2886 if (tdp_enabled)
2887 return 0;
2888
1871c602 2889 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
10589a46 2890
aaee2c94 2891 spin_lock(&vcpu->kvm->mmu_lock);
10589a46 2892 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
aaee2c94 2893 spin_unlock(&vcpu->kvm->mmu_lock);
10589a46 2894 return r;
a436036b 2895}
577bdc49 2896EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
a436036b 2897
22d95b12 2898void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
ebeace86 2899{
103ad25a 2900 int free_pages;
d98ba053 2901 LIST_HEAD(invalid_list);
103ad25a
XG		 2902
2903 free_pages = vcpu->kvm->arch.n_free_mmu_pages;
2904 while (free_pages < KVM_REFILL_PAGES &&
3b80fffe 2905 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
4db35314 2906 struct kvm_mmu_page *sp;
ebeace86 2907
f05e70ac 2908 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4db35314 2909 struct kvm_mmu_page, link);
d98ba053
XG		 2910 free_pages += kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2911 &invalid_list);
4cee5764 2912 ++vcpu->kvm->stat.mmu_recycled;
ebeace86 2913 }
d98ba053 2914 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
ebeace86 2915}
ebeace86 2916
3067714c
AK		 2917int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
2918{
2919 int r;
2920 enum emulation_result er;
2921
ad312c7c 2922 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code);
3067714c
AK		 2923 if (r < 0)
2924 goto out;
2925
2926 if (!r) {
2927 r = 1;
2928 goto out;
2929 }
2930
b733bfb5
AK		 2931 r = mmu_topup_memory_caches(vcpu);
2932 if (r)
2933 goto out;
2934
851ba692 2935 er = emulate_instruction(vcpu, cr2, error_code, 0);
3067714c
AK		 2936
2937 switch (er) {
2938 case EMULATE_DONE:
2939 return 1;
2940 case EMULATE_DO_MMIO:
2941 ++vcpu->stat.mmio_exits;
6d77dbfc 2942 /* fall through */
3067714c 2943 case EMULATE_FAIL:
3f5d18a9 2944 return 0;
3067714c
AK		 2945 default:
2946 BUG();
2947 }
2948out:
3067714c
AK		 2949 return r;
2950}
2951EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
2952
a7052897
MT		 2953void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
2954{
a7052897 2955 vcpu->arch.mmu.invlpg(vcpu, gva);
a7052897
MT		 2956 kvm_mmu_flush_tlb(vcpu);
2957 ++vcpu->stat.invlpg;
2958}
2959EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
2960
18552672
JR		 2961void kvm_enable_tdp(void)
2962{
2963 tdp_enabled = true;
2964}
2965EXPORT_SYMBOL_GPL(kvm_enable_tdp);
2966
5f4cb662
JR		 2967void kvm_disable_tdp(void)
2968{
2969 tdp_enabled = false;
2970}
2971EXPORT_SYMBOL_GPL(kvm_disable_tdp);
2972
6aa8b732
AK		 2973static void free_mmu_pages(struct kvm_vcpu *vcpu)
2974{
ad312c7c 2975 free_page((unsigned long)vcpu->arch.mmu.pae_root);
6aa8b732
AK		 2976}
2977
2978static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
2979{
17ac10ad 2980 struct page *page;
6aa8b732
AK		 2981 int i;
2982
2983 ASSERT(vcpu);
2984
17ac10ad
AK		 2985 /*
2986 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
2987 * Therefore we need to allocate shadow page tables in the first
2988 * 4GB of memory, which happens to fit the DMA32 zone.
2989 */
2990 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
2991 if (!page)
d7fa6ab2
WY		 2992 return -ENOMEM;
2993
ad312c7c 2994 vcpu->arch.mmu.pae_root = page_address(page);
17ac10ad 2995 for (i = 0; i < 4; ++i)
ad312c7c 2996 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2997
6aa8b732 2998 return 0;
6aa8b732
AK		 2999}
3000
8018c27b 3001int kvm_mmu_create(struct kvm_vcpu *vcpu)
6aa8b732 3002{
6aa8b732 3003 ASSERT(vcpu);
ad312c7c 3004 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 3005
8018c27b
IM		 3006 return alloc_mmu_pages(vcpu);
3007}
6aa8b732 3008
8018c27b
IM		 3009int kvm_mmu_setup(struct kvm_vcpu *vcpu)
3010{
3011 ASSERT(vcpu);
ad312c7c 3012 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2c264957 3013
8018c27b 3014 return init_kvm_mmu(vcpu);
6aa8b732
AK		 3015}
3016
3017void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
3018{
3019 ASSERT(vcpu);
3020
3021 destroy_kvm_mmu(vcpu);
3022 free_mmu_pages(vcpu);
714b93da 3023 mmu_free_memory_caches(vcpu);
6aa8b732
AK		 3024}
3025
90cb0529 3026void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
6aa8b732 3027{
4db35314 3028 struct kvm_mmu_page *sp;
6aa8b732 3029
f05e70ac 3030 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
6aa8b732
AK		 3031 int i;
3032 u64 *pt;
3033
291f26bc 3034 if (!test_bit(slot, sp->slot_bitmap))
6aa8b732
AK		 3035 continue;
3036
4db35314 3037 pt = sp->spt;
6aa8b732
AK		 3038 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
3039 /* avoid RMW */
01c168ac 3040 if (is_writable_pte(pt[i]))
6aa8b732 3041 pt[i] &= ~PT_WRITABLE_MASK;
6aa8b732 3042 }
171d595d 3043 kvm_flush_remote_tlbs(kvm);
6aa8b732 3044}
37a7d8b0 3045
90cb0529 3046void kvm_mmu_zap_all(struct kvm *kvm)
e0fa826f 3047{
4db35314 3048 struct kvm_mmu_page *sp, *node;
d98ba053 3049 LIST_HEAD(invalid_list);
e0fa826f 3050
aaee2c94 3051 spin_lock(&kvm->mmu_lock);
3246af0e 3052restart:
f05e70ac 3053 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
d98ba053 3054 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
3246af0e
XG		 3055 goto restart;
3056
d98ba053 3057 kvm_mmu_commit_zap_page(kvm, &invalid_list);
aaee2c94 3058 spin_unlock(&kvm->mmu_lock);
e0fa826f
DL		 3059}
3060
d98ba053
XG		 3061static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
3062 struct list_head *invalid_list)
3ee16c81
IE		 3063{
3064 struct kvm_mmu_page *page;
3065
3066 page = container_of(kvm->arch.active_mmu_pages.prev,
3067 struct kvm_mmu_page, link);
d98ba053 3068 return kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
3ee16c81
IE		 3069}
3070
7f8275d0 3071static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
3ee16c81
IE		 3072{
3073 struct kvm *kvm;
3074 struct kvm *kvm_freed = NULL;
3075 int cache_count = 0;
3076
3077 spin_lock(&kvm_lock);
3078
3079 list_for_each_entry(kvm, &vm_list, vm_list) {
d35b8dd9 3080 int npages, idx, freed_pages;
d98ba053 3081 LIST_HEAD(invalid_list);
3ee16c81 3082
f656ce01 3083 idx = srcu_read_lock(&kvm->srcu);
3ee16c81
IE		 3084 spin_lock(&kvm->mmu_lock);
3085 npages = kvm->arch.n_alloc_mmu_pages -
3086 kvm->arch.n_free_mmu_pages;
3087 cache_count += npages;
3088 if (!kvm_freed && nr_to_scan > 0 && npages > 0) {
d98ba053
XG		 3089 freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm,
3090 &invalid_list);
d35b8dd9 3091 cache_count -= freed_pages;
3ee16c81
IE		 3092 kvm_freed = kvm;
3093 }
3094 nr_to_scan--;
3095
d98ba053 3096 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3ee16c81 3097 spin_unlock(&kvm->mmu_lock);
f656ce01 3098 srcu_read_unlock(&kvm->srcu, idx);
3ee16c81
IE		 3099 }
3100 if (kvm_freed)
3101 list_move_tail(&kvm_freed->vm_list, &vm_list);
3102
3103 spin_unlock(&kvm_lock);
3104
3105 return cache_count;
3106}
3107
3108static struct shrinker mmu_shrinker = {
3109 .shrink = mmu_shrink,
3110 .seeks = DEFAULT_SEEKS * 10,
3111};
3112
2ddfd20e 3113static void mmu_destroy_caches(void)
b5a33a75
AK		 3114{
3115 if (pte_chain_cache)
3116 kmem_cache_destroy(pte_chain_cache);
3117 if (rmap_desc_cache)
3118 kmem_cache_destroy(rmap_desc_cache);
d3d25b04
AK		 3119 if (mmu_page_header_cache)
3120 kmem_cache_destroy(mmu_page_header_cache);
b5a33a75
AK		 3121}
3122
3ee16c81
IE		 3123void kvm_mmu_module_exit(void)
3124{
3125 mmu_destroy_caches();
3126 unregister_shrinker(&mmu_shrinker);
3127}
3128
b5a33a75
AK		 3129int kvm_mmu_module_init(void)
3130{
3131 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
3132 sizeof(struct kvm_pte_chain),
20c2df83 3133 0, 0, NULL);
b5a33a75
AK		 3134 if (!pte_chain_cache)
3135 goto nomem;
3136 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
3137 sizeof(struct kvm_rmap_desc),
20c2df83 3138 0, 0, NULL);
b5a33a75
AK		 3139 if (!rmap_desc_cache)
3140 goto nomem;
3141
d3d25b04
AK		 3142 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3143 sizeof(struct kvm_mmu_page),
20c2df83 3144 0, 0, NULL);
d3d25b04
AK		 3145 if (!mmu_page_header_cache)
3146 goto nomem;
3147
3ee16c81
IE		 3148 register_shrinker(&mmu_shrinker);
3149
b5a33a75
AK		 3150 return 0;
3151
3152nomem:
3ee16c81 3153 mmu_destroy_caches();
b5a33a75
AK		 3154 return -ENOMEM;
3155}
3156
3ad82a7e
ZX		 3157/*
3158 * Caculate mmu pages needed for kvm.
3159 */
3160unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3161{
3162 int i;
3163 unsigned int nr_mmu_pages;
3164 unsigned int nr_pages = 0;
bc6678a3 3165 struct kvm_memslots *slots;
3ad82a7e 3166
90d83dc3
LJ		 3167 slots = kvm_memslots(kvm);
3168
bc6678a3
MT		 3169 for (i = 0; i < slots->nmemslots; i++)
3170 nr_pages += slots->memslots[i].npages;
3ad82a7e
ZX		 3171
3172 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3173 nr_mmu_pages = max(nr_mmu_pages,
3174 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3175
3176 return nr_mmu_pages;
3177}
3178
2f333bcb
MT		 3179static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3180 unsigned len)
3181{
3182 if (len > buffer->len)
3183 return NULL;
3184 return buffer->ptr;
3185}
3186
3187static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3188 unsigned len)
3189{
3190 void *ret;
3191
3192 ret = pv_mmu_peek_buffer(buffer, len);
3193 if (!ret)
3194 return ret;
3195 buffer->ptr += len;
3196 buffer->len -= len;
3197 buffer->processed += len;
3198 return ret;
3199}
3200
3201static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3202 gpa_t addr, gpa_t value)
3203{
3204 int bytes = 8;
3205 int r;
3206
3207 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3208 bytes = 4;
3209
3210 r = mmu_topup_memory_caches(vcpu);
3211 if (r)
3212 return r;
3213
3200f405 3214 if (!emulator_write_phys(vcpu, addr, &value, bytes))
2f333bcb
MT		 3215 return -EFAULT;
3216
3217 return 1;
3218}
3219
3220static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3221{
2390218b 3222 (void)kvm_set_cr3(vcpu, vcpu->arch.cr3);
2f333bcb
MT		 3223 return 1;
3224}
3225
3226static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3227{
3228 spin_lock(&vcpu->kvm->mmu_lock);
3229 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3230 spin_unlock(&vcpu->kvm->mmu_lock);
3231 return 1;
3232}
3233
3234static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3235 struct kvm_pv_mmu_op_buffer *buffer)
3236{
3237 struct kvm_mmu_op_header *header;
3238
3239 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3240 if (!header)
3241 return 0;
3242 switch (header->op) {
3243 case KVM_MMU_OP_WRITE_PTE: {
3244 struct kvm_mmu_op_write_pte *wpte;
3245
3246 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3247 if (!wpte)
3248 return 0;
3249 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3250 wpte->pte_val);
3251 }
3252 case KVM_MMU_OP_FLUSH_TLB: {
3253 struct kvm_mmu_op_flush_tlb *ftlb;
3254
3255 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3256 if (!ftlb)
3257 return 0;
3258 return kvm_pv_mmu_flush_tlb(vcpu);
3259 }
3260 case KVM_MMU_OP_RELEASE_PT: {
3261 struct kvm_mmu_op_release_pt *rpt;
3262
3263 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3264 if (!rpt)
3265 return 0;
3266 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3267 }
3268 default: return 0;
3269 }
3270}
3271
3272int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3273 gpa_t addr, unsigned long *ret)
3274{
3275 int r;
6ad18fba 3276 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
2f333bcb 3277
6ad18fba
DH		 3278 buffer->ptr = buffer->buf;
3279 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3280 buffer->processed = 0;
2f333bcb 3281
6ad18fba 3282 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
2f333bcb
MT		 3283 if (r)
3284 goto out;
3285
6ad18fba
DH		 3286 while (buffer->len) {
3287 r = kvm_pv_mmu_op_one(vcpu, buffer);
2f333bcb
MT		 3288 if (r < 0)
3289 goto out;
3290 if (r == 0)
3291 break;
3292 }
3293
3294 r = 1;
3295out:
6ad18fba 3296 *ret = buffer->processed;
2f333bcb
MT		 3297 return r;
3298}
3299
94d8b056
MT		 3300int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3301{
3302 struct kvm_shadow_walk_iterator iterator;
3303 int nr_sptes = 0;
3304
3305 spin_lock(&vcpu->kvm->mmu_lock);
3306 for_each_shadow_entry(vcpu, addr, iterator) {
3307 sptes[iterator.level-1] = *iterator.sptep;
3308 nr_sptes++;
3309 if (!is_shadow_present_pte(*iterator.sptep))
3310 break;
3311 }
3312 spin_unlock(&vcpu->kvm->mmu_lock);
3313
3314 return nr_sptes;
3315}
3316EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3317
37a7d8b0
AK		 3318#ifdef AUDIT
3319
3320static const char *audit_msg;
3321
3322static gva_t canonicalize(gva_t gva)
3323{
3324#ifdef CONFIG_X86_64
3325 gva = (long long)(gva << 16) >> 16;
3326#endif
3327 return gva;
3328}
3329
08a3732b 3330
805d32de 3331typedef void (*inspect_spte_fn) (struct kvm *kvm, u64 *sptep);
08a3732b
MT		 3332
3333static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp,
3334 inspect_spte_fn fn)
3335{
3336 int i;
3337
3338 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3339 u64 ent = sp->spt[i];
3340
3341 if (is_shadow_present_pte(ent)) {
2920d728 3342 if (!is_last_spte(ent, sp->role.level)) {
08a3732b
MT		 3343 struct kvm_mmu_page *child;
3344 child = page_header(ent & PT64_BASE_ADDR_MASK);
3345 __mmu_spte_walk(kvm, child, fn);
2920d728 3346 } else
805d32de 3347 fn(kvm, &sp->spt[i]);
08a3732b
MT		 3348 }
3349 }
3350}
3351
3352static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn)
3353{
3354 int i;
3355 struct kvm_mmu_page *sp;
3356
3357 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3358 return;
3359 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3360 hpa_t root = vcpu->arch.mmu.root_hpa;
3361 sp = page_header(root);
3362 __mmu_spte_walk(vcpu->kvm, sp, fn);
3363 return;
3364 }
3365 for (i = 0; i < 4; ++i) {
3366 hpa_t root = vcpu->arch.mmu.pae_root[i];
3367
3368 if (root && VALID_PAGE(root)) {
3369 root &= PT64_BASE_ADDR_MASK;
3370 sp = page_header(root);
3371 __mmu_spte_walk(vcpu->kvm, sp, fn);
3372 }
3373 }
3374 return;
3375}
3376
37a7d8b0
AK		 3377static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
3378 gva_t va, int level)
3379{
3380 u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK);
3381 int i;
3382 gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1));
3383
3384 for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) {
3385 u64 ent = pt[i];
3386
c7addb90 3387 if (ent == shadow_trap_nonpresent_pte)
37a7d8b0
AK		 3388 continue;
3389
3390 va = canonicalize(va);
2920d728
MT		 3391 if (is_shadow_present_pte(ent) && !is_last_spte(ent, level))
3392 audit_mappings_page(vcpu, ent, va, level - 1);
3393 else {
1871c602 3394 gpa_t gpa = kvm_mmu_gva_to_gpa_read(vcpu, va, NULL);
34382539
JK		 3395 gfn_t gfn = gpa >> PAGE_SHIFT;
3396 pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn);
3397 hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT;
37a7d8b0 3398
2aaf65e8
MT		 3399 if (is_error_pfn(pfn)) {
3400 kvm_release_pfn_clean(pfn);
3401 continue;
3402 }
3403
c7addb90 3404 if (is_shadow_present_pte(ent)
37a7d8b0 3405 && (ent & PT64_BASE_ADDR_MASK) != hpa)
c7addb90
AK		 3406 printk(KERN_ERR "xx audit error: (%s) levels %d"
3407 " gva %lx gpa %llx hpa %llx ent %llx %d\n",
ad312c7c 3408 audit_msg, vcpu->arch.mmu.root_level,
d77c26fc
MD		 3409 va, gpa, hpa, ent,
3410 is_shadow_present_pte(ent));
c7addb90
AK		 3411 else if (ent == shadow_notrap_nonpresent_pte
3412 && !is_error_hpa(hpa))
3413 printk(KERN_ERR "audit: (%s) notrap shadow,"
3414 " valid guest gva %lx\n", audit_msg, va);
35149e21 3415 kvm_release_pfn_clean(pfn);
c7addb90 3416
37a7d8b0
AK		 3417 }
3418 }
3419}
3420
3421static void audit_mappings(struct kvm_vcpu *vcpu)
3422{
1ea252af 3423 unsigned i;
37a7d8b0 3424
ad312c7c
ZX		 3425 if (vcpu->arch.mmu.root_level == 4)
3426 audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4);
37a7d8b0
AK		 3427 else
3428 for (i = 0; i < 4; ++i)
ad312c7c 3429 if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK)
37a7d8b0 3430 audit_mappings_page(vcpu,
ad312c7c 3431 vcpu->arch.mmu.pae_root[i],
37a7d8b0
AK		 3432 i << 30,
3433 2);
3434}
3435
3436static int count_rmaps(struct kvm_vcpu *vcpu)
3437{
805d32de
XG		 3438 struct kvm *kvm = vcpu->kvm;
3439 struct kvm_memslots *slots;
37a7d8b0 3440 int nmaps = 0;
bc6678a3 3441 int i, j, k, idx;
37a7d8b0 3442
bc6678a3 3443 idx = srcu_read_lock(&kvm->srcu);
90d83dc3 3444 slots = kvm_memslots(kvm);
37a7d8b0 3445 for (i = 0; i < KVM_MEMORY_SLOTS; ++i) {
bc6678a3 3446 struct kvm_memory_slot *m = &slots->memslots[i];
37a7d8b0
AK		 3447 struct kvm_rmap_desc *d;
3448
3449 for (j = 0; j < m->npages; ++j) {
290fc38d 3450 unsigned long *rmapp = &m->rmap[j];
37a7d8b0 3451
290fc38d 3452 if (!*rmapp)
37a7d8b0 3453 continue;
290fc38d 3454 if (!(*rmapp & 1)) {
37a7d8b0
AK		 3455 ++nmaps;
3456 continue;
3457 }
290fc38d 3458 d = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
37a7d8b0
AK		 3459 while (d) {
3460 for (k = 0; k < RMAP_EXT; ++k)
d555c333 3461 if (d->sptes[k])
37a7d8b0
AK		 3462 ++nmaps;
3463 else
3464 break;
3465 d = d->more;
3466 }
3467 }
3468 }
bc6678a3 3469 srcu_read_unlock(&kvm->srcu, idx);
37a7d8b0
AK		 3470 return nmaps;
3471}
3472
805d32de 3473void inspect_spte_has_rmap(struct kvm *kvm, u64 *sptep)
08a3732b
MT		 3474{
3475 unsigned long *rmapp;
3476 struct kvm_mmu_page *rev_sp;
3477 gfn_t gfn;
3478
01c168ac 3479 if (is_writable_pte(*sptep)) {
08a3732b 3480 rev_sp = page_header(__pa(sptep));
2032a93d 3481 gfn = kvm_mmu_page_get_gfn(rev_sp, sptep - rev_sp->spt);
08a3732b
MT		 3482
3483 if (!gfn_to_memslot(kvm, gfn)) {
3484 if (!printk_ratelimit())
3485 return;
3486 printk(KERN_ERR "%s: no memslot for gfn %ld\n",
3487 audit_msg, gfn);
3488 printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n",
805d32de 3489 audit_msg, (long int)(sptep - rev_sp->spt),
08a3732b
MT		 3490 rev_sp->gfn);
3491 dump_stack();
3492 return;
3493 }
3494
2032a93d 3495 rmapp = gfn_to_rmap(kvm, gfn, rev_sp->role.level);
08a3732b
MT		 3496 if (!*rmapp) {
3497 if (!printk_ratelimit())
3498 return;
3499 printk(KERN_ERR "%s: no rmap for writable spte %llx\n",
3500 audit_msg, *sptep);
3501 dump_stack();
3502 }
3503 }
3504
3505}
3506
3507void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu)
3508{
3509 mmu_spte_walk(vcpu, inspect_spte_has_rmap);
3510}
3511
3512static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu)
37a7d8b0 3513{
4db35314 3514 struct kvm_mmu_page *sp;
37a7d8b0
AK		 3515 int i;
3516
f05e70ac 3517 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
4db35314 3518 u64 *pt = sp->spt;
37a7d8b0 3519
4db35314 3520 if (sp->role.level != PT_PAGE_TABLE_LEVEL)
37a7d8b0
AK		 3521 continue;
3522
3523 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3524 u64 ent = pt[i];
3525
3526 if (!(ent & PT_PRESENT_MASK))
3527 continue;
01c168ac 3528 if (!is_writable_pte(ent))
37a7d8b0 3529 continue;
805d32de 3530 inspect_spte_has_rmap(vcpu->kvm, &pt[i]);
37a7d8b0
AK		 3531 }
3532 }
08a3732b 3533 return;
37a7d8b0
AK		 3534}
3535
3536static void audit_rmap(struct kvm_vcpu *vcpu)
3537{
08a3732b
MT		 3538 check_writable_mappings_rmap(vcpu);
3539 count_rmaps(vcpu);
37a7d8b0
AK		 3540}
3541
3542static void audit_write_protection(struct kvm_vcpu *vcpu)
3543{
4db35314 3544 struct kvm_mmu_page *sp;
290fc38d
IE		 3545 struct kvm_memory_slot *slot;
3546 unsigned long *rmapp;
e58b0f9e 3547 u64 *spte;
290fc38d 3548 gfn_t gfn;
37a7d8b0 3549
f05e70ac 3550 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
f6e2c02b 3551 if (sp->role.direct)
37a7d8b0 3552 continue;
e58b0f9e
MT		 3553 if (sp->unsync)
3554 continue;
37a7d8b0 3555
a1f4d395 3556 slot = gfn_to_memslot(vcpu->kvm, sp->gfn);
290fc38d 3557 rmapp = &slot->rmap[gfn - slot->base_gfn];
e58b0f9e
MT		 3558
3559 spte = rmap_next(vcpu->kvm, rmapp, NULL);
3560 while (spte) {
01c168ac 3561 if (is_writable_pte(*spte))
e58b0f9e
MT		 3562 printk(KERN_ERR "%s: (%s) shadow page has "
3563 "writable mappings: gfn %lx role %x\n",
b8688d51 3564 __func__, audit_msg, sp->gfn,
4db35314 3565 sp->role.word);
e58b0f9e
MT		 3566 spte = rmap_next(vcpu->kvm, rmapp, spte);
3567 }
37a7d8b0
AK		 3568 }
3569}
3570
3571static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
3572{
3573 int olddbg = dbg;
3574
3575 dbg = 0;
3576 audit_msg = msg;
3577 audit_rmap(vcpu);
3578 audit_write_protection(vcpu);
2aaf65e8
MT		 3579 if (strcmp("pre pte write", audit_msg) != 0)
3580 audit_mappings(vcpu);
08a3732b 3581 audit_writable_sptes_have_rmaps(vcpu);
37a7d8b0
AK		 3582 dbg = olddbg;
3583}
3584
3585#endif
Linux 6.x block layer and io_uring tree(s)