Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
10 | * | |
11 | * Authors: | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * | |
15 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
16 | * the COPYING file in the top-level directory. | |
17 | * | |
18 | */ | |
e495606d | 19 | |
1d737c8a | 20 | #include "mmu.h" |
836a1b3c | 21 | #include "x86.h" |
6de4f3ad | 22 | #include "kvm_cache_regs.h" |
e495606d | 23 | |
edf88417 | 24 | #include <linux/kvm_host.h> |
6aa8b732 AK |
25 | #include <linux/types.h> |
26 | #include <linux/string.h> | |
6aa8b732 AK |
27 | #include <linux/mm.h> |
28 | #include <linux/highmem.h> | |
29 | #include <linux/module.h> | |
448353ca | 30 | #include <linux/swap.h> |
05da4558 | 31 | #include <linux/hugetlb.h> |
2f333bcb | 32 | #include <linux/compiler.h> |
bc6678a3 | 33 | #include <linux/srcu.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
6aa8b732 | 35 | |
e495606d AK |
36 | #include <asm/page.h> |
37 | #include <asm/cmpxchg.h> | |
4e542370 | 38 | #include <asm/io.h> |
13673a90 | 39 | #include <asm/vmx.h> |
6aa8b732 | 40 | |
18552672 JR |
41 | /* |
42 | * When setting this variable to true it enables Two-Dimensional-Paging | |
43 | * where the hardware walks 2 page tables: | |
44 | * 1. the guest-virtual to guest-physical | |
45 | * 2. while doing 1. it walks guest-physical to host-physical | |
46 | * If the hardware supports that we don't need to do shadow paging. | |
47 | */ | |
2f333bcb | 48 | bool tdp_enabled = false; |
18552672 | 49 | |
37a7d8b0 AK |
50 | #undef MMU_DEBUG |
51 | ||
52 | #undef AUDIT | |
53 | ||
54 | #ifdef AUDIT | |
55 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg); | |
56 | #else | |
57 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {} | |
58 | #endif | |
59 | ||
60 | #ifdef MMU_DEBUG | |
61 | ||
62 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
63 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
64 | ||
65 | #else | |
66 | ||
67 | #define pgprintk(x...) do { } while (0) | |
68 | #define rmap_printk(x...) do { } while (0) | |
69 | ||
70 | #endif | |
71 | ||
72 | #if defined(MMU_DEBUG) || defined(AUDIT) | |
6ada8cca AK |
73 | static int dbg = 0; |
74 | module_param(dbg, bool, 0644); | |
37a7d8b0 | 75 | #endif |
6aa8b732 | 76 | |
582801a9 MT |
77 | static int oos_shadow = 1; |
78 | module_param(oos_shadow, bool, 0644); | |
79 | ||
d6c69ee9 YD |
80 | #ifndef MMU_DEBUG |
81 | #define ASSERT(x) do { } while (0) | |
82 | #else | |
6aa8b732 AK |
83 | #define ASSERT(x) \ |
84 | if (!(x)) { \ | |
85 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
86 | __FILE__, __LINE__, #x); \ | |
87 | } | |
d6c69ee9 | 88 | #endif |
6aa8b732 | 89 | |
6aa8b732 AK |
90 | #define PT_FIRST_AVAIL_BITS_SHIFT 9 |
91 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 | |
92 | ||
6aa8b732 AK |
93 | #define VALID_PAGE(x) ((x) != INVALID_PAGE) |
94 | ||
95 | #define PT64_LEVEL_BITS 9 | |
96 | ||
97 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 98 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 AK |
99 | |
100 | #define PT64_LEVEL_MASK(level) \ | |
101 | (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level)) | |
102 | ||
103 | #define PT64_INDEX(address, level)\ | |
104 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
105 | ||
106 | ||
107 | #define PT32_LEVEL_BITS 10 | |
108 | ||
109 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 110 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 AK |
111 | |
112 | #define PT32_LEVEL_MASK(level) \ | |
113 | (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level)) | |
e04da980 JR |
114 | #define PT32_LVL_OFFSET_MASK(level) \ |
115 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
116 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
117 | |
118 | #define PT32_INDEX(address, level)\ | |
119 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
120 | ||
121 | ||
27aba766 | 122 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
123 | #define PT64_DIR_BASE_ADDR_MASK \ |
124 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
125 | #define PT64_LVL_ADDR_MASK(level) \ |
126 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
127 | * PT64_LEVEL_BITS))) - 1)) | |
128 | #define PT64_LVL_OFFSET_MASK(level) \ | |
129 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
130 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
131 | |
132 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
133 | #define PT32_DIR_BASE_ADDR_MASK \ | |
134 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
135 | #define PT32_LVL_ADDR_MASK(level) \ |
136 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
137 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 138 | |
79539cec AK |
139 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
140 | | PT64_NX_MASK) | |
6aa8b732 | 141 | |
cd4a4e53 AK |
142 | #define RMAP_EXT 4 |
143 | ||
fe135d2c AK |
144 | #define ACC_EXEC_MASK 1 |
145 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
146 | #define ACC_USER_MASK PT_USER_MASK | |
147 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
148 | ||
90bb6fc5 AK |
149 | #include <trace/events/kvm.h> |
150 | ||
07420171 AK |
151 | #define CREATE_TRACE_POINTS |
152 | #include "mmutrace.h" | |
153 | ||
1403283a IE |
154 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
155 | ||
135f8c2b AK |
156 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
157 | ||
cd4a4e53 | 158 | struct kvm_rmap_desc { |
d555c333 | 159 | u64 *sptes[RMAP_EXT]; |
cd4a4e53 AK |
160 | struct kvm_rmap_desc *more; |
161 | }; | |
162 | ||
2d11123a AK |
163 | struct kvm_shadow_walk_iterator { |
164 | u64 addr; | |
165 | hpa_t shadow_addr; | |
166 | int level; | |
167 | u64 *sptep; | |
168 | unsigned index; | |
169 | }; | |
170 | ||
171 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
172 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
173 | shadow_walk_okay(&(_walker)); \ | |
174 | shadow_walk_next(&(_walker))) | |
175 | ||
176 | ||
4731d4c7 MT |
177 | struct kvm_unsync_walk { |
178 | int (*entry) (struct kvm_mmu_page *sp, struct kvm_unsync_walk *walk); | |
179 | }; | |
180 | ||
ad8cfbe3 MT |
181 | typedef int (*mmu_parent_walk_fn) (struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp); |
182 | ||
b5a33a75 AK |
183 | static struct kmem_cache *pte_chain_cache; |
184 | static struct kmem_cache *rmap_desc_cache; | |
d3d25b04 | 185 | static struct kmem_cache *mmu_page_header_cache; |
b5a33a75 | 186 | |
c7addb90 AK |
187 | static u64 __read_mostly shadow_trap_nonpresent_pte; |
188 | static u64 __read_mostly shadow_notrap_nonpresent_pte; | |
7b52345e SY |
189 | static u64 __read_mostly shadow_base_present_pte; |
190 | static u64 __read_mostly shadow_nx_mask; | |
191 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
192 | static u64 __read_mostly shadow_user_mask; | |
193 | static u64 __read_mostly shadow_accessed_mask; | |
194 | static u64 __read_mostly shadow_dirty_mask; | |
c7addb90 | 195 | |
82725b20 DE |
196 | static inline u64 rsvd_bits(int s, int e) |
197 | { | |
198 | return ((1ULL << (e - s + 1)) - 1) << s; | |
199 | } | |
200 | ||
c7addb90 AK |
201 | void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte) |
202 | { | |
203 | shadow_trap_nonpresent_pte = trap_pte; | |
204 | shadow_notrap_nonpresent_pte = notrap_pte; | |
205 | } | |
206 | EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes); | |
207 | ||
7b52345e SY |
208 | void kvm_mmu_set_base_ptes(u64 base_pte) |
209 | { | |
210 | shadow_base_present_pte = base_pte; | |
211 | } | |
212 | EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes); | |
213 | ||
214 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, | |
4b12f0de | 215 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
216 | { |
217 | shadow_user_mask = user_mask; | |
218 | shadow_accessed_mask = accessed_mask; | |
219 | shadow_dirty_mask = dirty_mask; | |
220 | shadow_nx_mask = nx_mask; | |
221 | shadow_x_mask = x_mask; | |
222 | } | |
223 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
224 | ||
6aa8b732 AK |
225 | static int is_write_protection(struct kvm_vcpu *vcpu) |
226 | { | |
4d4ec087 | 227 | return kvm_read_cr0_bits(vcpu, X86_CR0_WP); |
6aa8b732 AK |
228 | } |
229 | ||
230 | static int is_cpuid_PSE36(void) | |
231 | { | |
232 | return 1; | |
233 | } | |
234 | ||
73b1087e AK |
235 | static int is_nx(struct kvm_vcpu *vcpu) |
236 | { | |
f6801dff | 237 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
238 | } |
239 | ||
c7addb90 AK |
240 | static int is_shadow_present_pte(u64 pte) |
241 | { | |
c7addb90 AK |
242 | return pte != shadow_trap_nonpresent_pte |
243 | && pte != shadow_notrap_nonpresent_pte; | |
244 | } | |
245 | ||
05da4558 MT |
246 | static int is_large_pte(u64 pte) |
247 | { | |
248 | return pte & PT_PAGE_SIZE_MASK; | |
249 | } | |
250 | ||
8dae4445 | 251 | static int is_writable_pte(unsigned long pte) |
6aa8b732 AK |
252 | { |
253 | return pte & PT_WRITABLE_MASK; | |
254 | } | |
255 | ||
43a3795a | 256 | static int is_dirty_gpte(unsigned long pte) |
e3c5e7ec | 257 | { |
439e218a | 258 | return pte & PT_DIRTY_MASK; |
e3c5e7ec AK |
259 | } |
260 | ||
43a3795a | 261 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 262 | { |
4b1a80fa | 263 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
264 | } |
265 | ||
776e6633 MT |
266 | static int is_last_spte(u64 pte, int level) |
267 | { | |
268 | if (level == PT_PAGE_TABLE_LEVEL) | |
269 | return 1; | |
852e3c19 | 270 | if (is_large_pte(pte)) |
776e6633 MT |
271 | return 1; |
272 | return 0; | |
273 | } | |
274 | ||
35149e21 | 275 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 276 | { |
35149e21 | 277 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
278 | } |
279 | ||
da928521 AK |
280 | static gfn_t pse36_gfn_delta(u32 gpte) |
281 | { | |
282 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
283 | ||
284 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
285 | } | |
286 | ||
d555c333 | 287 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 AK |
288 | { |
289 | #ifdef CONFIG_X86_64 | |
290 | set_64bit((unsigned long *)sptep, spte); | |
291 | #else | |
292 | set_64bit((unsigned long long *)sptep, spte); | |
293 | #endif | |
294 | } | |
295 | ||
e2dec939 | 296 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 297 | struct kmem_cache *base_cache, int min) |
714b93da AK |
298 | { |
299 | void *obj; | |
300 | ||
301 | if (cache->nobjs >= min) | |
e2dec939 | 302 | return 0; |
714b93da | 303 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 304 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 305 | if (!obj) |
e2dec939 | 306 | return -ENOMEM; |
714b93da AK |
307 | cache->objects[cache->nobjs++] = obj; |
308 | } | |
e2dec939 | 309 | return 0; |
714b93da AK |
310 | } |
311 | ||
312 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc) | |
313 | { | |
314 | while (mc->nobjs) | |
315 | kfree(mc->objects[--mc->nobjs]); | |
316 | } | |
317 | ||
c1158e63 | 318 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 319 | int min) |
c1158e63 AK |
320 | { |
321 | struct page *page; | |
322 | ||
323 | if (cache->nobjs >= min) | |
324 | return 0; | |
325 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
2e3e5882 | 326 | page = alloc_page(GFP_KERNEL); |
c1158e63 AK |
327 | if (!page) |
328 | return -ENOMEM; | |
c1158e63 AK |
329 | cache->objects[cache->nobjs++] = page_address(page); |
330 | } | |
331 | return 0; | |
332 | } | |
333 | ||
334 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
335 | { | |
336 | while (mc->nobjs) | |
c4d198d5 | 337 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
338 | } |
339 | ||
2e3e5882 | 340 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 341 | { |
e2dec939 AK |
342 | int r; |
343 | ||
ad312c7c | 344 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache, |
2e3e5882 | 345 | pte_chain_cache, 4); |
e2dec939 AK |
346 | if (r) |
347 | goto out; | |
ad312c7c | 348 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, |
c41ef344 | 349 | rmap_desc_cache, 4); |
d3d25b04 AK |
350 | if (r) |
351 | goto out; | |
ad312c7c | 352 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
353 | if (r) |
354 | goto out; | |
ad312c7c | 355 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 356 | mmu_page_header_cache, 4); |
e2dec939 AK |
357 | out: |
358 | return r; | |
714b93da AK |
359 | } |
360 | ||
361 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
362 | { | |
ad312c7c ZX |
363 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache); |
364 | mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache); | |
365 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); | |
366 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache); | |
714b93da AK |
367 | } |
368 | ||
369 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc, | |
370 | size_t size) | |
371 | { | |
372 | void *p; | |
373 | ||
374 | BUG_ON(!mc->nobjs); | |
375 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
376 | return p; |
377 | } | |
378 | ||
714b93da AK |
379 | static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu) |
380 | { | |
ad312c7c | 381 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache, |
714b93da AK |
382 | sizeof(struct kvm_pte_chain)); |
383 | } | |
384 | ||
90cb0529 | 385 | static void mmu_free_pte_chain(struct kvm_pte_chain *pc) |
714b93da | 386 | { |
90cb0529 | 387 | kfree(pc); |
714b93da AK |
388 | } |
389 | ||
390 | static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu) | |
391 | { | |
ad312c7c | 392 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache, |
714b93da AK |
393 | sizeof(struct kvm_rmap_desc)); |
394 | } | |
395 | ||
90cb0529 | 396 | static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd) |
714b93da | 397 | { |
90cb0529 | 398 | kfree(rd); |
714b93da AK |
399 | } |
400 | ||
05da4558 MT |
401 | /* |
402 | * Return the pointer to the largepage write count for a given | |
403 | * gfn, handling slots that are not large page aligned. | |
404 | */ | |
d25797b2 JR |
405 | static int *slot_largepage_idx(gfn_t gfn, |
406 | struct kvm_memory_slot *slot, | |
407 | int level) | |
05da4558 MT |
408 | { |
409 | unsigned long idx; | |
410 | ||
d25797b2 JR |
411 | idx = (gfn / KVM_PAGES_PER_HPAGE(level)) - |
412 | (slot->base_gfn / KVM_PAGES_PER_HPAGE(level)); | |
413 | return &slot->lpage_info[level - 2][idx].write_count; | |
05da4558 MT |
414 | } |
415 | ||
416 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
417 | { | |
d25797b2 | 418 | struct kvm_memory_slot *slot; |
05da4558 | 419 | int *write_count; |
d25797b2 | 420 | int i; |
05da4558 | 421 | |
2843099f | 422 | gfn = unalias_gfn(kvm, gfn); |
d25797b2 JR |
423 | |
424 | slot = gfn_to_memslot_unaliased(kvm, gfn); | |
425 | for (i = PT_DIRECTORY_LEVEL; | |
426 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
427 | write_count = slot_largepage_idx(gfn, slot, i); | |
428 | *write_count += 1; | |
429 | } | |
05da4558 MT |
430 | } |
431 | ||
432 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
433 | { | |
d25797b2 | 434 | struct kvm_memory_slot *slot; |
05da4558 | 435 | int *write_count; |
d25797b2 | 436 | int i; |
05da4558 | 437 | |
2843099f | 438 | gfn = unalias_gfn(kvm, gfn); |
d25797b2 JR |
439 | for (i = PT_DIRECTORY_LEVEL; |
440 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
441 | slot = gfn_to_memslot_unaliased(kvm, gfn); | |
442 | write_count = slot_largepage_idx(gfn, slot, i); | |
443 | *write_count -= 1; | |
444 | WARN_ON(*write_count < 0); | |
445 | } | |
05da4558 MT |
446 | } |
447 | ||
d25797b2 JR |
448 | static int has_wrprotected_page(struct kvm *kvm, |
449 | gfn_t gfn, | |
450 | int level) | |
05da4558 | 451 | { |
2843099f | 452 | struct kvm_memory_slot *slot; |
05da4558 MT |
453 | int *largepage_idx; |
454 | ||
2843099f IE |
455 | gfn = unalias_gfn(kvm, gfn); |
456 | slot = gfn_to_memslot_unaliased(kvm, gfn); | |
05da4558 | 457 | if (slot) { |
d25797b2 | 458 | largepage_idx = slot_largepage_idx(gfn, slot, level); |
05da4558 MT |
459 | return *largepage_idx; |
460 | } | |
461 | ||
462 | return 1; | |
463 | } | |
464 | ||
d25797b2 | 465 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 466 | { |
8f0b1ab6 | 467 | unsigned long page_size; |
d25797b2 | 468 | int i, ret = 0; |
05da4558 | 469 | |
8f0b1ab6 | 470 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 471 | |
d25797b2 JR |
472 | for (i = PT_PAGE_TABLE_LEVEL; |
473 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
474 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
475 | ret = i; | |
476 | else | |
477 | break; | |
478 | } | |
479 | ||
4c2155ce | 480 | return ret; |
05da4558 MT |
481 | } |
482 | ||
d25797b2 | 483 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) |
05da4558 MT |
484 | { |
485 | struct kvm_memory_slot *slot; | |
878403b7 | 486 | int host_level, level, max_level; |
05da4558 MT |
487 | |
488 | slot = gfn_to_memslot(vcpu->kvm, large_gfn); | |
489 | if (slot && slot->dirty_bitmap) | |
d25797b2 | 490 | return PT_PAGE_TABLE_LEVEL; |
05da4558 | 491 | |
d25797b2 JR |
492 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
493 | ||
494 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
495 | return host_level; | |
496 | ||
878403b7 SY |
497 | max_level = kvm_x86_ops->get_lpage_level() < host_level ? |
498 | kvm_x86_ops->get_lpage_level() : host_level; | |
499 | ||
500 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
501 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
502 | break; | |
d25797b2 JR |
503 | |
504 | return level - 1; | |
05da4558 MT |
505 | } |
506 | ||
290fc38d IE |
507 | /* |
508 | * Take gfn and return the reverse mapping to it. | |
509 | * Note: gfn must be unaliased before this function get called | |
510 | */ | |
511 | ||
44ad9944 | 512 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) |
290fc38d IE |
513 | { |
514 | struct kvm_memory_slot *slot; | |
05da4558 | 515 | unsigned long idx; |
290fc38d IE |
516 | |
517 | slot = gfn_to_memslot(kvm, gfn); | |
44ad9944 | 518 | if (likely(level == PT_PAGE_TABLE_LEVEL)) |
05da4558 MT |
519 | return &slot->rmap[gfn - slot->base_gfn]; |
520 | ||
44ad9944 JR |
521 | idx = (gfn / KVM_PAGES_PER_HPAGE(level)) - |
522 | (slot->base_gfn / KVM_PAGES_PER_HPAGE(level)); | |
05da4558 | 523 | |
44ad9944 | 524 | return &slot->lpage_info[level - 2][idx].rmap_pde; |
290fc38d IE |
525 | } |
526 | ||
cd4a4e53 AK |
527 | /* |
528 | * Reverse mapping data structures: | |
529 | * | |
290fc38d IE |
530 | * If rmapp bit zero is zero, then rmapp point to the shadw page table entry |
531 | * that points to page_address(page). | |
cd4a4e53 | 532 | * |
290fc38d IE |
533 | * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc |
534 | * containing more mappings. | |
53a27b39 MT |
535 | * |
536 | * Returns the number of rmap entries before the spte was added or zero if | |
537 | * the spte was not added. | |
538 | * | |
cd4a4e53 | 539 | */ |
44ad9944 | 540 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
cd4a4e53 | 541 | { |
4db35314 | 542 | struct kvm_mmu_page *sp; |
cd4a4e53 | 543 | struct kvm_rmap_desc *desc; |
290fc38d | 544 | unsigned long *rmapp; |
53a27b39 | 545 | int i, count = 0; |
cd4a4e53 | 546 | |
43a3795a | 547 | if (!is_rmap_spte(*spte)) |
53a27b39 | 548 | return count; |
290fc38d | 549 | gfn = unalias_gfn(vcpu->kvm, gfn); |
4db35314 AK |
550 | sp = page_header(__pa(spte)); |
551 | sp->gfns[spte - sp->spt] = gfn; | |
44ad9944 | 552 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
290fc38d | 553 | if (!*rmapp) { |
cd4a4e53 | 554 | rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte); |
290fc38d IE |
555 | *rmapp = (unsigned long)spte; |
556 | } else if (!(*rmapp & 1)) { | |
cd4a4e53 | 557 | rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte); |
714b93da | 558 | desc = mmu_alloc_rmap_desc(vcpu); |
d555c333 AK |
559 | desc->sptes[0] = (u64 *)*rmapp; |
560 | desc->sptes[1] = spte; | |
290fc38d | 561 | *rmapp = (unsigned long)desc | 1; |
cd4a4e53 AK |
562 | } else { |
563 | rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte); | |
290fc38d | 564 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
d555c333 | 565 | while (desc->sptes[RMAP_EXT-1] && desc->more) { |
cd4a4e53 | 566 | desc = desc->more; |
53a27b39 MT |
567 | count += RMAP_EXT; |
568 | } | |
d555c333 | 569 | if (desc->sptes[RMAP_EXT-1]) { |
714b93da | 570 | desc->more = mmu_alloc_rmap_desc(vcpu); |
cd4a4e53 AK |
571 | desc = desc->more; |
572 | } | |
d555c333 | 573 | for (i = 0; desc->sptes[i]; ++i) |
cd4a4e53 | 574 | ; |
d555c333 | 575 | desc->sptes[i] = spte; |
cd4a4e53 | 576 | } |
53a27b39 | 577 | return count; |
cd4a4e53 AK |
578 | } |
579 | ||
290fc38d | 580 | static void rmap_desc_remove_entry(unsigned long *rmapp, |
cd4a4e53 AK |
581 | struct kvm_rmap_desc *desc, |
582 | int i, | |
583 | struct kvm_rmap_desc *prev_desc) | |
584 | { | |
585 | int j; | |
586 | ||
d555c333 | 587 | for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 588 | ; |
d555c333 AK |
589 | desc->sptes[i] = desc->sptes[j]; |
590 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
591 | if (j != 0) |
592 | return; | |
593 | if (!prev_desc && !desc->more) | |
d555c333 | 594 | *rmapp = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
595 | else |
596 | if (prev_desc) | |
597 | prev_desc->more = desc->more; | |
598 | else | |
290fc38d | 599 | *rmapp = (unsigned long)desc->more | 1; |
90cb0529 | 600 | mmu_free_rmap_desc(desc); |
cd4a4e53 AK |
601 | } |
602 | ||
290fc38d | 603 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
cd4a4e53 | 604 | { |
cd4a4e53 AK |
605 | struct kvm_rmap_desc *desc; |
606 | struct kvm_rmap_desc *prev_desc; | |
4db35314 | 607 | struct kvm_mmu_page *sp; |
35149e21 | 608 | pfn_t pfn; |
290fc38d | 609 | unsigned long *rmapp; |
cd4a4e53 AK |
610 | int i; |
611 | ||
43a3795a | 612 | if (!is_rmap_spte(*spte)) |
cd4a4e53 | 613 | return; |
4db35314 | 614 | sp = page_header(__pa(spte)); |
35149e21 | 615 | pfn = spte_to_pfn(*spte); |
7b52345e | 616 | if (*spte & shadow_accessed_mask) |
35149e21 | 617 | kvm_set_pfn_accessed(pfn); |
8dae4445 | 618 | if (is_writable_pte(*spte)) |
acb66dd0 | 619 | kvm_set_pfn_dirty(pfn); |
44ad9944 | 620 | rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], sp->role.level); |
290fc38d | 621 | if (!*rmapp) { |
cd4a4e53 AK |
622 | printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte); |
623 | BUG(); | |
290fc38d | 624 | } else if (!(*rmapp & 1)) { |
cd4a4e53 | 625 | rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte); |
290fc38d | 626 | if ((u64 *)*rmapp != spte) { |
cd4a4e53 AK |
627 | printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n", |
628 | spte, *spte); | |
629 | BUG(); | |
630 | } | |
290fc38d | 631 | *rmapp = 0; |
cd4a4e53 AK |
632 | } else { |
633 | rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte); | |
290fc38d | 634 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
cd4a4e53 AK |
635 | prev_desc = NULL; |
636 | while (desc) { | |
d555c333 AK |
637 | for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) |
638 | if (desc->sptes[i] == spte) { | |
290fc38d | 639 | rmap_desc_remove_entry(rmapp, |
714b93da | 640 | desc, i, |
cd4a4e53 AK |
641 | prev_desc); |
642 | return; | |
643 | } | |
644 | prev_desc = desc; | |
645 | desc = desc->more; | |
646 | } | |
186a3e52 | 647 | pr_err("rmap_remove: %p %llx many->many\n", spte, *spte); |
cd4a4e53 AK |
648 | BUG(); |
649 | } | |
650 | } | |
651 | ||
98348e95 | 652 | static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte) |
374cbac0 | 653 | { |
374cbac0 | 654 | struct kvm_rmap_desc *desc; |
98348e95 IE |
655 | struct kvm_rmap_desc *prev_desc; |
656 | u64 *prev_spte; | |
657 | int i; | |
658 | ||
659 | if (!*rmapp) | |
660 | return NULL; | |
661 | else if (!(*rmapp & 1)) { | |
662 | if (!spte) | |
663 | return (u64 *)*rmapp; | |
664 | return NULL; | |
665 | } | |
666 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); | |
667 | prev_desc = NULL; | |
668 | prev_spte = NULL; | |
669 | while (desc) { | |
d555c333 | 670 | for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) { |
98348e95 | 671 | if (prev_spte == spte) |
d555c333 AK |
672 | return desc->sptes[i]; |
673 | prev_spte = desc->sptes[i]; | |
98348e95 IE |
674 | } |
675 | desc = desc->more; | |
676 | } | |
677 | return NULL; | |
678 | } | |
679 | ||
b1a36821 | 680 | static int rmap_write_protect(struct kvm *kvm, u64 gfn) |
98348e95 | 681 | { |
290fc38d | 682 | unsigned long *rmapp; |
374cbac0 | 683 | u64 *spte; |
44ad9944 | 684 | int i, write_protected = 0; |
374cbac0 | 685 | |
4a4c9924 | 686 | gfn = unalias_gfn(kvm, gfn); |
44ad9944 | 687 | rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL); |
374cbac0 | 688 | |
98348e95 IE |
689 | spte = rmap_next(kvm, rmapp, NULL); |
690 | while (spte) { | |
374cbac0 | 691 | BUG_ON(!spte); |
374cbac0 | 692 | BUG_ON(!(*spte & PT_PRESENT_MASK)); |
374cbac0 | 693 | rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte); |
8dae4445 | 694 | if (is_writable_pte(*spte)) { |
d555c333 | 695 | __set_spte(spte, *spte & ~PT_WRITABLE_MASK); |
caa5b8a5 ED |
696 | write_protected = 1; |
697 | } | |
9647c14c | 698 | spte = rmap_next(kvm, rmapp, spte); |
374cbac0 | 699 | } |
855149aa | 700 | if (write_protected) { |
35149e21 | 701 | pfn_t pfn; |
855149aa IE |
702 | |
703 | spte = rmap_next(kvm, rmapp, NULL); | |
35149e21 AL |
704 | pfn = spte_to_pfn(*spte); |
705 | kvm_set_pfn_dirty(pfn); | |
855149aa IE |
706 | } |
707 | ||
05da4558 | 708 | /* check for huge page mappings */ |
44ad9944 JR |
709 | for (i = PT_DIRECTORY_LEVEL; |
710 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
711 | rmapp = gfn_to_rmap(kvm, gfn, i); | |
712 | spte = rmap_next(kvm, rmapp, NULL); | |
713 | while (spte) { | |
714 | BUG_ON(!spte); | |
715 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
716 | BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)); | |
717 | pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn); | |
8dae4445 | 718 | if (is_writable_pte(*spte)) { |
44ad9944 JR |
719 | rmap_remove(kvm, spte); |
720 | --kvm->stat.lpages; | |
721 | __set_spte(spte, shadow_trap_nonpresent_pte); | |
722 | spte = NULL; | |
723 | write_protected = 1; | |
724 | } | |
725 | spte = rmap_next(kvm, rmapp, spte); | |
05da4558 | 726 | } |
05da4558 MT |
727 | } |
728 | ||
b1a36821 | 729 | return write_protected; |
374cbac0 AK |
730 | } |
731 | ||
8a8365c5 FD |
732 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
733 | unsigned long data) | |
e930bffe AA |
734 | { |
735 | u64 *spte; | |
736 | int need_tlb_flush = 0; | |
737 | ||
738 | while ((spte = rmap_next(kvm, rmapp, NULL))) { | |
739 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
740 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte); | |
741 | rmap_remove(kvm, spte); | |
d555c333 | 742 | __set_spte(spte, shadow_trap_nonpresent_pte); |
e930bffe AA |
743 | need_tlb_flush = 1; |
744 | } | |
745 | return need_tlb_flush; | |
746 | } | |
747 | ||
8a8365c5 FD |
748 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
749 | unsigned long data) | |
3da0dd43 IE |
750 | { |
751 | int need_flush = 0; | |
752 | u64 *spte, new_spte; | |
753 | pte_t *ptep = (pte_t *)data; | |
754 | pfn_t new_pfn; | |
755 | ||
756 | WARN_ON(pte_huge(*ptep)); | |
757 | new_pfn = pte_pfn(*ptep); | |
758 | spte = rmap_next(kvm, rmapp, NULL); | |
759 | while (spte) { | |
760 | BUG_ON(!is_shadow_present_pte(*spte)); | |
761 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte); | |
762 | need_flush = 1; | |
763 | if (pte_write(*ptep)) { | |
764 | rmap_remove(kvm, spte); | |
765 | __set_spte(spte, shadow_trap_nonpresent_pte); | |
766 | spte = rmap_next(kvm, rmapp, NULL); | |
767 | } else { | |
768 | new_spte = *spte &~ (PT64_BASE_ADDR_MASK); | |
769 | new_spte |= (u64)new_pfn << PAGE_SHIFT; | |
770 | ||
771 | new_spte &= ~PT_WRITABLE_MASK; | |
772 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
8dae4445 | 773 | if (is_writable_pte(*spte)) |
3da0dd43 IE |
774 | kvm_set_pfn_dirty(spte_to_pfn(*spte)); |
775 | __set_spte(spte, new_spte); | |
776 | spte = rmap_next(kvm, rmapp, spte); | |
777 | } | |
778 | } | |
779 | if (need_flush) | |
780 | kvm_flush_remote_tlbs(kvm); | |
781 | ||
782 | return 0; | |
783 | } | |
784 | ||
8a8365c5 FD |
785 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
786 | unsigned long data, | |
3da0dd43 | 787 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, |
8a8365c5 | 788 | unsigned long data)) |
e930bffe | 789 | { |
852e3c19 | 790 | int i, j; |
90bb6fc5 | 791 | int ret; |
e930bffe | 792 | int retval = 0; |
bc6678a3 MT |
793 | struct kvm_memslots *slots; |
794 | ||
795 | slots = rcu_dereference(kvm->memslots); | |
e930bffe | 796 | |
46a26bf5 MT |
797 | for (i = 0; i < slots->nmemslots; i++) { |
798 | struct kvm_memory_slot *memslot = &slots->memslots[i]; | |
e930bffe AA |
799 | unsigned long start = memslot->userspace_addr; |
800 | unsigned long end; | |
801 | ||
e930bffe AA |
802 | end = start + (memslot->npages << PAGE_SHIFT); |
803 | if (hva >= start && hva < end) { | |
804 | gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT; | |
852e3c19 | 805 | |
90bb6fc5 | 806 | ret = handler(kvm, &memslot->rmap[gfn_offset], data); |
852e3c19 JR |
807 | |
808 | for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) { | |
809 | int idx = gfn_offset; | |
810 | idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j); | |
90bb6fc5 | 811 | ret |= handler(kvm, |
3da0dd43 IE |
812 | &memslot->lpage_info[j][idx].rmap_pde, |
813 | data); | |
852e3c19 | 814 | } |
90bb6fc5 AK |
815 | trace_kvm_age_page(hva, memslot, ret); |
816 | retval |= ret; | |
e930bffe AA |
817 | } |
818 | } | |
819 | ||
820 | return retval; | |
821 | } | |
822 | ||
823 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
824 | { | |
3da0dd43 IE |
825 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
826 | } | |
827 | ||
828 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) | |
829 | { | |
8a8365c5 | 830 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
831 | } |
832 | ||
8a8365c5 FD |
833 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
834 | unsigned long data) | |
e930bffe AA |
835 | { |
836 | u64 *spte; | |
837 | int young = 0; | |
838 | ||
6316e1c8 RR |
839 | /* |
840 | * Emulate the accessed bit for EPT, by checking if this page has | |
841 | * an EPT mapping, and clearing it if it does. On the next access, | |
842 | * a new EPT mapping will be established. | |
843 | * This has some overhead, but not as much as the cost of swapping | |
844 | * out actively used pages or breaking up actively used hugepages. | |
845 | */ | |
534e38b4 | 846 | if (!shadow_accessed_mask) |
6316e1c8 | 847 | return kvm_unmap_rmapp(kvm, rmapp, data); |
534e38b4 | 848 | |
e930bffe AA |
849 | spte = rmap_next(kvm, rmapp, NULL); |
850 | while (spte) { | |
851 | int _young; | |
852 | u64 _spte = *spte; | |
853 | BUG_ON(!(_spte & PT_PRESENT_MASK)); | |
854 | _young = _spte & PT_ACCESSED_MASK; | |
855 | if (_young) { | |
856 | young = 1; | |
857 | clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
858 | } | |
859 | spte = rmap_next(kvm, rmapp, spte); | |
860 | } | |
861 | return young; | |
862 | } | |
863 | ||
53a27b39 MT |
864 | #define RMAP_RECYCLE_THRESHOLD 1000 |
865 | ||
852e3c19 | 866 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
867 | { |
868 | unsigned long *rmapp; | |
852e3c19 JR |
869 | struct kvm_mmu_page *sp; |
870 | ||
871 | sp = page_header(__pa(spte)); | |
53a27b39 MT |
872 | |
873 | gfn = unalias_gfn(vcpu->kvm, gfn); | |
852e3c19 | 874 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 875 | |
3da0dd43 | 876 | kvm_unmap_rmapp(vcpu->kvm, rmapp, 0); |
53a27b39 MT |
877 | kvm_flush_remote_tlbs(vcpu->kvm); |
878 | } | |
879 | ||
e930bffe AA |
880 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
881 | { | |
3da0dd43 | 882 | return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp); |
e930bffe AA |
883 | } |
884 | ||
d6c69ee9 | 885 | #ifdef MMU_DEBUG |
47ad8e68 | 886 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 887 | { |
139bdb2d AK |
888 | u64 *pos; |
889 | u64 *end; | |
890 | ||
47ad8e68 | 891 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 892 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 893 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 894 | pos, *pos); |
6aa8b732 | 895 | return 0; |
139bdb2d | 896 | } |
6aa8b732 AK |
897 | return 1; |
898 | } | |
d6c69ee9 | 899 | #endif |
6aa8b732 | 900 | |
4db35314 | 901 | static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
260746c0 | 902 | { |
4db35314 AK |
903 | ASSERT(is_empty_shadow_page(sp->spt)); |
904 | list_del(&sp->link); | |
905 | __free_page(virt_to_page(sp->spt)); | |
906 | __free_page(virt_to_page(sp->gfns)); | |
907 | kfree(sp); | |
f05e70ac | 908 | ++kvm->arch.n_free_mmu_pages; |
260746c0 AK |
909 | } |
910 | ||
cea0f0e7 AK |
911 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
912 | { | |
1ae0a13d | 913 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
914 | } |
915 | ||
25c0de2c AK |
916 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
917 | u64 *parent_pte) | |
6aa8b732 | 918 | { |
4db35314 | 919 | struct kvm_mmu_page *sp; |
6aa8b732 | 920 | |
ad312c7c ZX |
921 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp); |
922 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE); | |
923 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE); | |
4db35314 | 924 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
f05e70ac | 925 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
6cffe8ca | 926 | INIT_LIST_HEAD(&sp->oos_link); |
291f26bc | 927 | bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS); |
4db35314 AK |
928 | sp->multimapped = 0; |
929 | sp->parent_pte = parent_pte; | |
f05e70ac | 930 | --vcpu->kvm->arch.n_free_mmu_pages; |
4db35314 | 931 | return sp; |
6aa8b732 AK |
932 | } |
933 | ||
714b93da | 934 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 935 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 AK |
936 | { |
937 | struct kvm_pte_chain *pte_chain; | |
938 | struct hlist_node *node; | |
939 | int i; | |
940 | ||
941 | if (!parent_pte) | |
942 | return; | |
4db35314 AK |
943 | if (!sp->multimapped) { |
944 | u64 *old = sp->parent_pte; | |
cea0f0e7 AK |
945 | |
946 | if (!old) { | |
4db35314 | 947 | sp->parent_pte = parent_pte; |
cea0f0e7 AK |
948 | return; |
949 | } | |
4db35314 | 950 | sp->multimapped = 1; |
714b93da | 951 | pte_chain = mmu_alloc_pte_chain(vcpu); |
4db35314 AK |
952 | INIT_HLIST_HEAD(&sp->parent_ptes); |
953 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); | |
cea0f0e7 AK |
954 | pte_chain->parent_ptes[0] = old; |
955 | } | |
4db35314 | 956 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) { |
cea0f0e7 AK |
957 | if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1]) |
958 | continue; | |
959 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) | |
960 | if (!pte_chain->parent_ptes[i]) { | |
961 | pte_chain->parent_ptes[i] = parent_pte; | |
962 | return; | |
963 | } | |
964 | } | |
714b93da | 965 | pte_chain = mmu_alloc_pte_chain(vcpu); |
cea0f0e7 | 966 | BUG_ON(!pte_chain); |
4db35314 | 967 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); |
cea0f0e7 AK |
968 | pte_chain->parent_ptes[0] = parent_pte; |
969 | } | |
970 | ||
4db35314 | 971 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
972 | u64 *parent_pte) |
973 | { | |
974 | struct kvm_pte_chain *pte_chain; | |
975 | struct hlist_node *node; | |
976 | int i; | |
977 | ||
4db35314 AK |
978 | if (!sp->multimapped) { |
979 | BUG_ON(sp->parent_pte != parent_pte); | |
980 | sp->parent_pte = NULL; | |
cea0f0e7 AK |
981 | return; |
982 | } | |
4db35314 | 983 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) |
cea0f0e7 AK |
984 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { |
985 | if (!pte_chain->parent_ptes[i]) | |
986 | break; | |
987 | if (pte_chain->parent_ptes[i] != parent_pte) | |
988 | continue; | |
697fe2e2 AK |
989 | while (i + 1 < NR_PTE_CHAIN_ENTRIES |
990 | && pte_chain->parent_ptes[i + 1]) { | |
cea0f0e7 AK |
991 | pte_chain->parent_ptes[i] |
992 | = pte_chain->parent_ptes[i + 1]; | |
993 | ++i; | |
994 | } | |
995 | pte_chain->parent_ptes[i] = NULL; | |
697fe2e2 AK |
996 | if (i == 0) { |
997 | hlist_del(&pte_chain->link); | |
90cb0529 | 998 | mmu_free_pte_chain(pte_chain); |
4db35314 AK |
999 | if (hlist_empty(&sp->parent_ptes)) { |
1000 | sp->multimapped = 0; | |
1001 | sp->parent_pte = NULL; | |
697fe2e2 AK |
1002 | } |
1003 | } | |
cea0f0e7 AK |
1004 | return; |
1005 | } | |
1006 | BUG(); | |
1007 | } | |
1008 | ||
ad8cfbe3 MT |
1009 | |
1010 | static void mmu_parent_walk(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
1011 | mmu_parent_walk_fn fn) | |
1012 | { | |
1013 | struct kvm_pte_chain *pte_chain; | |
1014 | struct hlist_node *node; | |
1015 | struct kvm_mmu_page *parent_sp; | |
1016 | int i; | |
1017 | ||
1018 | if (!sp->multimapped && sp->parent_pte) { | |
1019 | parent_sp = page_header(__pa(sp->parent_pte)); | |
1020 | fn(vcpu, parent_sp); | |
1021 | mmu_parent_walk(vcpu, parent_sp, fn); | |
1022 | return; | |
1023 | } | |
1024 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) | |
1025 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { | |
1026 | if (!pte_chain->parent_ptes[i]) | |
1027 | break; | |
1028 | parent_sp = page_header(__pa(pte_chain->parent_ptes[i])); | |
1029 | fn(vcpu, parent_sp); | |
1030 | mmu_parent_walk(vcpu, parent_sp, fn); | |
1031 | } | |
1032 | } | |
1033 | ||
0074ff63 MT |
1034 | static void kvm_mmu_update_unsync_bitmap(u64 *spte) |
1035 | { | |
1036 | unsigned int index; | |
1037 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
1038 | ||
1039 | index = spte - sp->spt; | |
60c8aec6 MT |
1040 | if (!__test_and_set_bit(index, sp->unsync_child_bitmap)) |
1041 | sp->unsync_children++; | |
1042 | WARN_ON(!sp->unsync_children); | |
0074ff63 MT |
1043 | } |
1044 | ||
1045 | static void kvm_mmu_update_parents_unsync(struct kvm_mmu_page *sp) | |
1046 | { | |
1047 | struct kvm_pte_chain *pte_chain; | |
1048 | struct hlist_node *node; | |
1049 | int i; | |
1050 | ||
1051 | if (!sp->parent_pte) | |
1052 | return; | |
1053 | ||
1054 | if (!sp->multimapped) { | |
1055 | kvm_mmu_update_unsync_bitmap(sp->parent_pte); | |
1056 | return; | |
1057 | } | |
1058 | ||
1059 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) | |
1060 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { | |
1061 | if (!pte_chain->parent_ptes[i]) | |
1062 | break; | |
1063 | kvm_mmu_update_unsync_bitmap(pte_chain->parent_ptes[i]); | |
1064 | } | |
1065 | } | |
1066 | ||
1067 | static int unsync_walk_fn(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) | |
1068 | { | |
0074ff63 MT |
1069 | kvm_mmu_update_parents_unsync(sp); |
1070 | return 1; | |
1071 | } | |
1072 | ||
1073 | static void kvm_mmu_mark_parents_unsync(struct kvm_vcpu *vcpu, | |
1074 | struct kvm_mmu_page *sp) | |
1075 | { | |
1076 | mmu_parent_walk(vcpu, sp, unsync_walk_fn); | |
1077 | kvm_mmu_update_parents_unsync(sp); | |
1078 | } | |
1079 | ||
d761a501 AK |
1080 | static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu, |
1081 | struct kvm_mmu_page *sp) | |
1082 | { | |
1083 | int i; | |
1084 | ||
1085 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1086 | sp->spt[i] = shadow_trap_nonpresent_pte; | |
1087 | } | |
1088 | ||
e8bc217a MT |
1089 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
1090 | struct kvm_mmu_page *sp) | |
1091 | { | |
1092 | return 1; | |
1093 | } | |
1094 | ||
a7052897 MT |
1095 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1096 | { | |
1097 | } | |
1098 | ||
60c8aec6 MT |
1099 | #define KVM_PAGE_ARRAY_NR 16 |
1100 | ||
1101 | struct kvm_mmu_pages { | |
1102 | struct mmu_page_and_offset { | |
1103 | struct kvm_mmu_page *sp; | |
1104 | unsigned int idx; | |
1105 | } page[KVM_PAGE_ARRAY_NR]; | |
1106 | unsigned int nr; | |
1107 | }; | |
1108 | ||
0074ff63 MT |
1109 | #define for_each_unsync_children(bitmap, idx) \ |
1110 | for (idx = find_first_bit(bitmap, 512); \ | |
1111 | idx < 512; \ | |
1112 | idx = find_next_bit(bitmap, 512, idx+1)) | |
1113 | ||
cded19f3 HE |
1114 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1115 | int idx) | |
4731d4c7 | 1116 | { |
60c8aec6 | 1117 | int i; |
4731d4c7 | 1118 | |
60c8aec6 MT |
1119 | if (sp->unsync) |
1120 | for (i=0; i < pvec->nr; i++) | |
1121 | if (pvec->page[i].sp == sp) | |
1122 | return 0; | |
1123 | ||
1124 | pvec->page[pvec->nr].sp = sp; | |
1125 | pvec->page[pvec->nr].idx = idx; | |
1126 | pvec->nr++; | |
1127 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1128 | } | |
1129 | ||
1130 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1131 | struct kvm_mmu_pages *pvec) | |
1132 | { | |
1133 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1134 | |
0074ff63 | 1135 | for_each_unsync_children(sp->unsync_child_bitmap, i) { |
4731d4c7 MT |
1136 | u64 ent = sp->spt[i]; |
1137 | ||
87917239 | 1138 | if (is_shadow_present_pte(ent) && !is_large_pte(ent)) { |
4731d4c7 MT |
1139 | struct kvm_mmu_page *child; |
1140 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1141 | ||
1142 | if (child->unsync_children) { | |
60c8aec6 MT |
1143 | if (mmu_pages_add(pvec, child, i)) |
1144 | return -ENOSPC; | |
1145 | ||
1146 | ret = __mmu_unsync_walk(child, pvec); | |
1147 | if (!ret) | |
1148 | __clear_bit(i, sp->unsync_child_bitmap); | |
1149 | else if (ret > 0) | |
1150 | nr_unsync_leaf += ret; | |
1151 | else | |
4731d4c7 MT |
1152 | return ret; |
1153 | } | |
1154 | ||
1155 | if (child->unsync) { | |
60c8aec6 MT |
1156 | nr_unsync_leaf++; |
1157 | if (mmu_pages_add(pvec, child, i)) | |
1158 | return -ENOSPC; | |
4731d4c7 MT |
1159 | } |
1160 | } | |
1161 | } | |
1162 | ||
0074ff63 | 1163 | if (find_first_bit(sp->unsync_child_bitmap, 512) == 512) |
4731d4c7 MT |
1164 | sp->unsync_children = 0; |
1165 | ||
60c8aec6 MT |
1166 | return nr_unsync_leaf; |
1167 | } | |
1168 | ||
1169 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1170 | struct kvm_mmu_pages *pvec) | |
1171 | { | |
1172 | if (!sp->unsync_children) | |
1173 | return 0; | |
1174 | ||
1175 | mmu_pages_add(pvec, sp, 0); | |
1176 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1177 | } |
1178 | ||
4db35314 | 1179 | static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn) |
cea0f0e7 AK |
1180 | { |
1181 | unsigned index; | |
1182 | struct hlist_head *bucket; | |
4db35314 | 1183 | struct kvm_mmu_page *sp; |
cea0f0e7 AK |
1184 | struct hlist_node *node; |
1185 | ||
b8688d51 | 1186 | pgprintk("%s: looking for gfn %lx\n", __func__, gfn); |
1ae0a13d | 1187 | index = kvm_page_table_hashfn(gfn); |
f05e70ac | 1188 | bucket = &kvm->arch.mmu_page_hash[index]; |
4db35314 | 1189 | hlist_for_each_entry(sp, node, bucket, hash_link) |
f6e2c02b | 1190 | if (sp->gfn == gfn && !sp->role.direct |
2e53d63a | 1191 | && !sp->role.invalid) { |
cea0f0e7 | 1192 | pgprintk("%s: found role %x\n", |
b8688d51 | 1193 | __func__, sp->role.word); |
4db35314 | 1194 | return sp; |
cea0f0e7 AK |
1195 | } |
1196 | return NULL; | |
1197 | } | |
1198 | ||
4731d4c7 MT |
1199 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1200 | { | |
1201 | WARN_ON(!sp->unsync); | |
1202 | sp->unsync = 0; | |
1203 | --kvm->stat.mmu_unsync; | |
1204 | } | |
1205 | ||
1206 | static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp); | |
1207 | ||
1208 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) | |
1209 | { | |
1210 | if (sp->role.glevels != vcpu->arch.mmu.root_level) { | |
1211 | kvm_mmu_zap_page(vcpu->kvm, sp); | |
1212 | return 1; | |
1213 | } | |
1214 | ||
f691fe1d | 1215 | trace_kvm_mmu_sync_page(sp); |
b1a36821 MT |
1216 | if (rmap_write_protect(vcpu->kvm, sp->gfn)) |
1217 | kvm_flush_remote_tlbs(vcpu->kvm); | |
0c0f40bd | 1218 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
4731d4c7 MT |
1219 | if (vcpu->arch.mmu.sync_page(vcpu, sp)) { |
1220 | kvm_mmu_zap_page(vcpu->kvm, sp); | |
1221 | return 1; | |
1222 | } | |
1223 | ||
1224 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1225 | return 0; |
1226 | } | |
1227 | ||
60c8aec6 MT |
1228 | struct mmu_page_path { |
1229 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1230 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1231 | }; |
1232 | ||
60c8aec6 MT |
1233 | #define for_each_sp(pvec, sp, parents, i) \ |
1234 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1235 | sp = pvec.page[i].sp; \ | |
1236 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1237 | i = mmu_pages_next(&pvec, &parents, i)) | |
1238 | ||
cded19f3 HE |
1239 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1240 | struct mmu_page_path *parents, | |
1241 | int i) | |
60c8aec6 MT |
1242 | { |
1243 | int n; | |
1244 | ||
1245 | for (n = i+1; n < pvec->nr; n++) { | |
1246 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1247 | ||
1248 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1249 | parents->idx[0] = pvec->page[n].idx; | |
1250 | return n; | |
1251 | } | |
1252 | ||
1253 | parents->parent[sp->role.level-2] = sp; | |
1254 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1255 | } | |
1256 | ||
1257 | return n; | |
1258 | } | |
1259 | ||
cded19f3 | 1260 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1261 | { |
60c8aec6 MT |
1262 | struct kvm_mmu_page *sp; |
1263 | unsigned int level = 0; | |
1264 | ||
1265 | do { | |
1266 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1267 | |
60c8aec6 MT |
1268 | sp = parents->parent[level]; |
1269 | if (!sp) | |
1270 | return; | |
1271 | ||
1272 | --sp->unsync_children; | |
1273 | WARN_ON((int)sp->unsync_children < 0); | |
1274 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1275 | level++; | |
1276 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1277 | } |
1278 | ||
60c8aec6 MT |
1279 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1280 | struct mmu_page_path *parents, | |
1281 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1282 | { |
60c8aec6 MT |
1283 | parents->parent[parent->role.level-1] = NULL; |
1284 | pvec->nr = 0; | |
1285 | } | |
4731d4c7 | 1286 | |
60c8aec6 MT |
1287 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1288 | struct kvm_mmu_page *parent) | |
1289 | { | |
1290 | int i; | |
1291 | struct kvm_mmu_page *sp; | |
1292 | struct mmu_page_path parents; | |
1293 | struct kvm_mmu_pages pages; | |
1294 | ||
1295 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1296 | while (mmu_unsync_walk(parent, &pages)) { | |
b1a36821 MT |
1297 | int protected = 0; |
1298 | ||
1299 | for_each_sp(pages, sp, parents, i) | |
1300 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1301 | ||
1302 | if (protected) | |
1303 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1304 | ||
60c8aec6 MT |
1305 | for_each_sp(pages, sp, parents, i) { |
1306 | kvm_sync_page(vcpu, sp); | |
1307 | mmu_pages_clear_parents(&parents); | |
1308 | } | |
4731d4c7 | 1309 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1310 | kvm_mmu_pages_init(parent, &parents, &pages); |
1311 | } | |
4731d4c7 MT |
1312 | } |
1313 | ||
cea0f0e7 AK |
1314 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1315 | gfn_t gfn, | |
1316 | gva_t gaddr, | |
1317 | unsigned level, | |
f6e2c02b | 1318 | int direct, |
41074d07 | 1319 | unsigned access, |
f7d9c7b7 | 1320 | u64 *parent_pte) |
cea0f0e7 AK |
1321 | { |
1322 | union kvm_mmu_page_role role; | |
1323 | unsigned index; | |
1324 | unsigned quadrant; | |
1325 | struct hlist_head *bucket; | |
4db35314 | 1326 | struct kvm_mmu_page *sp; |
4731d4c7 | 1327 | struct hlist_node *node, *tmp; |
cea0f0e7 | 1328 | |
a770f6f2 | 1329 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1330 | role.level = level; |
f6e2c02b | 1331 | role.direct = direct; |
84b0c8c6 AK |
1332 | if (role.direct) |
1333 | role.glevels = 0; | |
41074d07 | 1334 | role.access = access; |
ad312c7c | 1335 | if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { |
cea0f0e7 AK |
1336 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1337 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1338 | role.quadrant = quadrant; | |
1339 | } | |
1ae0a13d | 1340 | index = kvm_page_table_hashfn(gfn); |
f05e70ac | 1341 | bucket = &vcpu->kvm->arch.mmu_page_hash[index]; |
4731d4c7 MT |
1342 | hlist_for_each_entry_safe(sp, node, tmp, bucket, hash_link) |
1343 | if (sp->gfn == gfn) { | |
1344 | if (sp->unsync) | |
1345 | if (kvm_sync_page(vcpu, sp)) | |
1346 | continue; | |
1347 | ||
1348 | if (sp->role.word != role.word) | |
1349 | continue; | |
1350 | ||
4db35314 | 1351 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
0074ff63 MT |
1352 | if (sp->unsync_children) { |
1353 | set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests); | |
1354 | kvm_mmu_mark_parents_unsync(vcpu, sp); | |
1355 | } | |
f691fe1d | 1356 | trace_kvm_mmu_get_page(sp, false); |
4db35314 | 1357 | return sp; |
cea0f0e7 | 1358 | } |
dfc5aa00 | 1359 | ++vcpu->kvm->stat.mmu_cache_miss; |
4db35314 AK |
1360 | sp = kvm_mmu_alloc_page(vcpu, parent_pte); |
1361 | if (!sp) | |
1362 | return sp; | |
4db35314 AK |
1363 | sp->gfn = gfn; |
1364 | sp->role = role; | |
1365 | hlist_add_head(&sp->hash_link, bucket); | |
f6e2c02b | 1366 | if (!direct) { |
b1a36821 MT |
1367 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1368 | kvm_flush_remote_tlbs(vcpu->kvm); | |
4731d4c7 MT |
1369 | account_shadowed(vcpu->kvm, gfn); |
1370 | } | |
131d8279 AK |
1371 | if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte) |
1372 | vcpu->arch.mmu.prefetch_page(vcpu, sp); | |
1373 | else | |
1374 | nonpaging_prefetch_page(vcpu, sp); | |
f691fe1d | 1375 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1376 | return sp; |
cea0f0e7 AK |
1377 | } |
1378 | ||
2d11123a AK |
1379 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1380 | struct kvm_vcpu *vcpu, u64 addr) | |
1381 | { | |
1382 | iterator->addr = addr; | |
1383 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1384 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
1385 | if (iterator->level == PT32E_ROOT_LEVEL) { | |
1386 | iterator->shadow_addr | |
1387 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
1388 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
1389 | --iterator->level; | |
1390 | if (!iterator->shadow_addr) | |
1391 | iterator->level = 0; | |
1392 | } | |
1393 | } | |
1394 | ||
1395 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
1396 | { | |
1397 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
1398 | return false; | |
4d88954d MT |
1399 | |
1400 | if (iterator->level == PT_PAGE_TABLE_LEVEL) | |
1401 | if (is_large_pte(*iterator->sptep)) | |
1402 | return false; | |
1403 | ||
2d11123a AK |
1404 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
1405 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
1406 | return true; | |
1407 | } | |
1408 | ||
1409 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) | |
1410 | { | |
1411 | iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK; | |
1412 | --iterator->level; | |
1413 | } | |
1414 | ||
90cb0529 | 1415 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 1416 | struct kvm_mmu_page *sp) |
a436036b | 1417 | { |
697fe2e2 AK |
1418 | unsigned i; |
1419 | u64 *pt; | |
1420 | u64 ent; | |
1421 | ||
4db35314 | 1422 | pt = sp->spt; |
697fe2e2 | 1423 | |
697fe2e2 AK |
1424 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { |
1425 | ent = pt[i]; | |
1426 | ||
05da4558 | 1427 | if (is_shadow_present_pte(ent)) { |
776e6633 | 1428 | if (!is_last_spte(ent, sp->role.level)) { |
05da4558 MT |
1429 | ent &= PT64_BASE_ADDR_MASK; |
1430 | mmu_page_remove_parent_pte(page_header(ent), | |
1431 | &pt[i]); | |
1432 | } else { | |
776e6633 MT |
1433 | if (is_large_pte(ent)) |
1434 | --kvm->stat.lpages; | |
05da4558 MT |
1435 | rmap_remove(kvm, &pt[i]); |
1436 | } | |
1437 | } | |
c7addb90 | 1438 | pt[i] = shadow_trap_nonpresent_pte; |
697fe2e2 | 1439 | } |
a436036b AK |
1440 | } |
1441 | ||
4db35314 | 1442 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1443 | { |
4db35314 | 1444 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
1445 | } |
1446 | ||
12b7d28f AK |
1447 | static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm) |
1448 | { | |
1449 | int i; | |
988a2cae | 1450 | struct kvm_vcpu *vcpu; |
12b7d28f | 1451 | |
988a2cae GN |
1452 | kvm_for_each_vcpu(i, vcpu, kvm) |
1453 | vcpu->arch.last_pte_updated = NULL; | |
12b7d28f AK |
1454 | } |
1455 | ||
31aa2b44 | 1456 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b AK |
1457 | { |
1458 | u64 *parent_pte; | |
1459 | ||
4db35314 AK |
1460 | while (sp->multimapped || sp->parent_pte) { |
1461 | if (!sp->multimapped) | |
1462 | parent_pte = sp->parent_pte; | |
a436036b AK |
1463 | else { |
1464 | struct kvm_pte_chain *chain; | |
1465 | ||
4db35314 | 1466 | chain = container_of(sp->parent_ptes.first, |
a436036b AK |
1467 | struct kvm_pte_chain, link); |
1468 | parent_pte = chain->parent_ptes[0]; | |
1469 | } | |
697fe2e2 | 1470 | BUG_ON(!parent_pte); |
4db35314 | 1471 | kvm_mmu_put_page(sp, parent_pte); |
d555c333 | 1472 | __set_spte(parent_pte, shadow_trap_nonpresent_pte); |
a436036b | 1473 | } |
31aa2b44 AK |
1474 | } |
1475 | ||
60c8aec6 MT |
1476 | static int mmu_zap_unsync_children(struct kvm *kvm, |
1477 | struct kvm_mmu_page *parent) | |
4731d4c7 | 1478 | { |
60c8aec6 MT |
1479 | int i, zapped = 0; |
1480 | struct mmu_page_path parents; | |
1481 | struct kvm_mmu_pages pages; | |
4731d4c7 | 1482 | |
60c8aec6 | 1483 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1484 | return 0; |
60c8aec6 MT |
1485 | |
1486 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1487 | while (mmu_unsync_walk(parent, &pages)) { | |
1488 | struct kvm_mmu_page *sp; | |
1489 | ||
1490 | for_each_sp(pages, sp, parents, i) { | |
1491 | kvm_mmu_zap_page(kvm, sp); | |
1492 | mmu_pages_clear_parents(&parents); | |
77662e00 | 1493 | zapped++; |
60c8aec6 | 1494 | } |
60c8aec6 MT |
1495 | kvm_mmu_pages_init(parent, &parents, &pages); |
1496 | } | |
1497 | ||
1498 | return zapped; | |
4731d4c7 MT |
1499 | } |
1500 | ||
07385413 | 1501 | static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
31aa2b44 | 1502 | { |
4731d4c7 | 1503 | int ret; |
f691fe1d AK |
1504 | |
1505 | trace_kvm_mmu_zap_page(sp); | |
31aa2b44 | 1506 | ++kvm->stat.mmu_shadow_zapped; |
4731d4c7 | 1507 | ret = mmu_zap_unsync_children(kvm, sp); |
4db35314 | 1508 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 1509 | kvm_mmu_unlink_parents(kvm, sp); |
5b5c6a5a | 1510 | kvm_flush_remote_tlbs(kvm); |
f6e2c02b | 1511 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 1512 | unaccount_shadowed(kvm, sp->gfn); |
4731d4c7 MT |
1513 | if (sp->unsync) |
1514 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 AK |
1515 | if (!sp->root_count) { |
1516 | hlist_del(&sp->hash_link); | |
1517 | kvm_mmu_free_page(kvm, sp); | |
2e53d63a | 1518 | } else { |
2e53d63a | 1519 | sp->role.invalid = 1; |
5b5c6a5a | 1520 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
2e53d63a MT |
1521 | kvm_reload_remote_mmus(kvm); |
1522 | } | |
12b7d28f | 1523 | kvm_mmu_reset_last_pte_updated(kvm); |
4731d4c7 | 1524 | return ret; |
a436036b AK |
1525 | } |
1526 | ||
82ce2c96 IE |
1527 | /* |
1528 | * Changing the number of mmu pages allocated to the vm | |
1529 | * Note: if kvm_nr_mmu_pages is too small, you will get dead lock | |
1530 | */ | |
1531 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages) | |
1532 | { | |
025dbbf3 MT |
1533 | int used_pages; |
1534 | ||
1535 | used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages; | |
1536 | used_pages = max(0, used_pages); | |
1537 | ||
82ce2c96 IE |
1538 | /* |
1539 | * If we set the number of mmu pages to be smaller be than the | |
1540 | * number of actived pages , we must to free some mmu pages before we | |
1541 | * change the value | |
1542 | */ | |
1543 | ||
025dbbf3 | 1544 | if (used_pages > kvm_nr_mmu_pages) { |
77662e00 XG |
1545 | while (used_pages > kvm_nr_mmu_pages && |
1546 | !list_empty(&kvm->arch.active_mmu_pages)) { | |
82ce2c96 IE |
1547 | struct kvm_mmu_page *page; |
1548 | ||
f05e70ac | 1549 | page = container_of(kvm->arch.active_mmu_pages.prev, |
82ce2c96 | 1550 | struct kvm_mmu_page, link); |
77662e00 | 1551 | used_pages -= kvm_mmu_zap_page(kvm, page); |
025dbbf3 | 1552 | used_pages--; |
82ce2c96 | 1553 | } |
77662e00 | 1554 | kvm_nr_mmu_pages = used_pages; |
f05e70ac | 1555 | kvm->arch.n_free_mmu_pages = 0; |
82ce2c96 IE |
1556 | } |
1557 | else | |
f05e70ac ZX |
1558 | kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages |
1559 | - kvm->arch.n_alloc_mmu_pages; | |
82ce2c96 | 1560 | |
f05e70ac | 1561 | kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages; |
82ce2c96 IE |
1562 | } |
1563 | ||
f67a46f4 | 1564 | static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b AK |
1565 | { |
1566 | unsigned index; | |
1567 | struct hlist_head *bucket; | |
4db35314 | 1568 | struct kvm_mmu_page *sp; |
a436036b AK |
1569 | struct hlist_node *node, *n; |
1570 | int r; | |
1571 | ||
b8688d51 | 1572 | pgprintk("%s: looking for gfn %lx\n", __func__, gfn); |
a436036b | 1573 | r = 0; |
1ae0a13d | 1574 | index = kvm_page_table_hashfn(gfn); |
f05e70ac | 1575 | bucket = &kvm->arch.mmu_page_hash[index]; |
4db35314 | 1576 | hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) |
f6e2c02b | 1577 | if (sp->gfn == gfn && !sp->role.direct) { |
b8688d51 | 1578 | pgprintk("%s: gfn %lx role %x\n", __func__, gfn, |
4db35314 | 1579 | sp->role.word); |
a436036b | 1580 | r = 1; |
07385413 MT |
1581 | if (kvm_mmu_zap_page(kvm, sp)) |
1582 | n = bucket->first; | |
a436036b AK |
1583 | } |
1584 | return r; | |
cea0f0e7 AK |
1585 | } |
1586 | ||
f67a46f4 | 1587 | static void mmu_unshadow(struct kvm *kvm, gfn_t gfn) |
97a0a01e | 1588 | { |
4677a3b6 AK |
1589 | unsigned index; |
1590 | struct hlist_head *bucket; | |
4db35314 | 1591 | struct kvm_mmu_page *sp; |
4677a3b6 | 1592 | struct hlist_node *node, *nn; |
97a0a01e | 1593 | |
4677a3b6 AK |
1594 | index = kvm_page_table_hashfn(gfn); |
1595 | bucket = &kvm->arch.mmu_page_hash[index]; | |
1596 | hlist_for_each_entry_safe(sp, node, nn, bucket, hash_link) { | |
f6e2c02b | 1597 | if (sp->gfn == gfn && !sp->role.direct |
4677a3b6 AK |
1598 | && !sp->role.invalid) { |
1599 | pgprintk("%s: zap %lx %x\n", | |
1600 | __func__, gfn, sp->role.word); | |
77662e00 XG |
1601 | if (kvm_mmu_zap_page(kvm, sp)) |
1602 | nn = bucket->first; | |
4677a3b6 | 1603 | } |
97a0a01e AK |
1604 | } |
1605 | } | |
1606 | ||
38c335f1 | 1607 | static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn) |
6aa8b732 | 1608 | { |
bc6678a3 | 1609 | int slot = memslot_id(kvm, gfn); |
4db35314 | 1610 | struct kvm_mmu_page *sp = page_header(__pa(pte)); |
6aa8b732 | 1611 | |
291f26bc | 1612 | __set_bit(slot, sp->slot_bitmap); |
6aa8b732 AK |
1613 | } |
1614 | ||
6844dec6 MT |
1615 | static void mmu_convert_notrap(struct kvm_mmu_page *sp) |
1616 | { | |
1617 | int i; | |
1618 | u64 *pt = sp->spt; | |
1619 | ||
1620 | if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte) | |
1621 | return; | |
1622 | ||
1623 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
1624 | if (pt[i] == shadow_notrap_nonpresent_pte) | |
d555c333 | 1625 | __set_spte(&pt[i], shadow_trap_nonpresent_pte); |
6844dec6 MT |
1626 | } |
1627 | } | |
1628 | ||
039576c0 AK |
1629 | struct page *gva_to_page(struct kvm_vcpu *vcpu, gva_t gva) |
1630 | { | |
72dc67a6 IE |
1631 | struct page *page; |
1632 | ||
1871c602 | 1633 | gpa_t gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
039576c0 AK |
1634 | |
1635 | if (gpa == UNMAPPED_GVA) | |
1636 | return NULL; | |
72dc67a6 | 1637 | |
72dc67a6 | 1638 | page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
72dc67a6 IE |
1639 | |
1640 | return page; | |
039576c0 AK |
1641 | } |
1642 | ||
74be52e3 SY |
1643 | /* |
1644 | * The function is based on mtrr_type_lookup() in | |
1645 | * arch/x86/kernel/cpu/mtrr/generic.c | |
1646 | */ | |
1647 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
1648 | u64 start, u64 end) | |
1649 | { | |
1650 | int i; | |
1651 | u64 base, mask; | |
1652 | u8 prev_match, curr_match; | |
1653 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
1654 | ||
1655 | if (!mtrr_state->enabled) | |
1656 | return 0xFF; | |
1657 | ||
1658 | /* Make end inclusive end, instead of exclusive */ | |
1659 | end--; | |
1660 | ||
1661 | /* Look in fixed ranges. Just return the type as per start */ | |
1662 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
1663 | int idx; | |
1664 | ||
1665 | if (start < 0x80000) { | |
1666 | idx = 0; | |
1667 | idx += (start >> 16); | |
1668 | return mtrr_state->fixed_ranges[idx]; | |
1669 | } else if (start < 0xC0000) { | |
1670 | idx = 1 * 8; | |
1671 | idx += ((start - 0x80000) >> 14); | |
1672 | return mtrr_state->fixed_ranges[idx]; | |
1673 | } else if (start < 0x1000000) { | |
1674 | idx = 3 * 8; | |
1675 | idx += ((start - 0xC0000) >> 12); | |
1676 | return mtrr_state->fixed_ranges[idx]; | |
1677 | } | |
1678 | } | |
1679 | ||
1680 | /* | |
1681 | * Look in variable ranges | |
1682 | * Look of multiple ranges matching this address and pick type | |
1683 | * as per MTRR precedence | |
1684 | */ | |
1685 | if (!(mtrr_state->enabled & 2)) | |
1686 | return mtrr_state->def_type; | |
1687 | ||
1688 | prev_match = 0xFF; | |
1689 | for (i = 0; i < num_var_ranges; ++i) { | |
1690 | unsigned short start_state, end_state; | |
1691 | ||
1692 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
1693 | continue; | |
1694 | ||
1695 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
1696 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
1697 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
1698 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
1699 | ||
1700 | start_state = ((start & mask) == (base & mask)); | |
1701 | end_state = ((end & mask) == (base & mask)); | |
1702 | if (start_state != end_state) | |
1703 | return 0xFE; | |
1704 | ||
1705 | if ((start & mask) != (base & mask)) | |
1706 | continue; | |
1707 | ||
1708 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
1709 | if (prev_match == 0xFF) { | |
1710 | prev_match = curr_match; | |
1711 | continue; | |
1712 | } | |
1713 | ||
1714 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
1715 | curr_match == MTRR_TYPE_UNCACHABLE) | |
1716 | return MTRR_TYPE_UNCACHABLE; | |
1717 | ||
1718 | if ((prev_match == MTRR_TYPE_WRBACK && | |
1719 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
1720 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
1721 | curr_match == MTRR_TYPE_WRBACK)) { | |
1722 | prev_match = MTRR_TYPE_WRTHROUGH; | |
1723 | curr_match = MTRR_TYPE_WRTHROUGH; | |
1724 | } | |
1725 | ||
1726 | if (prev_match != curr_match) | |
1727 | return MTRR_TYPE_UNCACHABLE; | |
1728 | } | |
1729 | ||
1730 | if (prev_match != 0xFF) | |
1731 | return prev_match; | |
1732 | ||
1733 | return mtrr_state->def_type; | |
1734 | } | |
1735 | ||
4b12f0de | 1736 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
1737 | { |
1738 | u8 mtrr; | |
1739 | ||
1740 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
1741 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
1742 | if (mtrr == 0xfe || mtrr == 0xff) | |
1743 | mtrr = MTRR_TYPE_WRBACK; | |
1744 | return mtrr; | |
1745 | } | |
4b12f0de | 1746 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 1747 | |
4731d4c7 MT |
1748 | static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
1749 | { | |
1750 | unsigned index; | |
1751 | struct hlist_head *bucket; | |
1752 | struct kvm_mmu_page *s; | |
1753 | struct hlist_node *node, *n; | |
1754 | ||
f691fe1d | 1755 | trace_kvm_mmu_unsync_page(sp); |
4731d4c7 MT |
1756 | index = kvm_page_table_hashfn(sp->gfn); |
1757 | bucket = &vcpu->kvm->arch.mmu_page_hash[index]; | |
1758 | /* don't unsync if pagetable is shadowed with multiple roles */ | |
1759 | hlist_for_each_entry_safe(s, node, n, bucket, hash_link) { | |
f6e2c02b | 1760 | if (s->gfn != sp->gfn || s->role.direct) |
4731d4c7 MT |
1761 | continue; |
1762 | if (s->role.word != sp->role.word) | |
1763 | return 1; | |
1764 | } | |
4731d4c7 MT |
1765 | ++vcpu->kvm->stat.mmu_unsync; |
1766 | sp->unsync = 1; | |
6cffe8ca | 1767 | |
c2d0ee46 | 1768 | kvm_mmu_mark_parents_unsync(vcpu, sp); |
6cffe8ca | 1769 | |
4731d4c7 MT |
1770 | mmu_convert_notrap(sp); |
1771 | return 0; | |
1772 | } | |
1773 | ||
1774 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
1775 | bool can_unsync) | |
1776 | { | |
1777 | struct kvm_mmu_page *shadow; | |
1778 | ||
1779 | shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn); | |
1780 | if (shadow) { | |
1781 | if (shadow->role.level != PT_PAGE_TABLE_LEVEL) | |
1782 | return 1; | |
1783 | if (shadow->unsync) | |
1784 | return 0; | |
582801a9 | 1785 | if (can_unsync && oos_shadow) |
4731d4c7 MT |
1786 | return kvm_unsync_page(vcpu, shadow); |
1787 | return 1; | |
1788 | } | |
1789 | return 0; | |
1790 | } | |
1791 | ||
d555c333 | 1792 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd | 1793 | unsigned pte_access, int user_fault, |
852e3c19 | 1794 | int write_fault, int dirty, int level, |
c2d0ee46 | 1795 | gfn_t gfn, pfn_t pfn, bool speculative, |
1403283a | 1796 | bool can_unsync, bool reset_host_protection) |
1c4f1fd6 AK |
1797 | { |
1798 | u64 spte; | |
1e73f9dd | 1799 | int ret = 0; |
64d4d521 | 1800 | |
1c4f1fd6 AK |
1801 | /* |
1802 | * We don't set the accessed bit, since we sometimes want to see | |
1803 | * whether the guest actually used the pte (in order to detect | |
1804 | * demand paging). | |
1805 | */ | |
7b52345e | 1806 | spte = shadow_base_present_pte | shadow_dirty_mask; |
947da538 | 1807 | if (!speculative) |
3201b5d9 | 1808 | spte |= shadow_accessed_mask; |
1c4f1fd6 AK |
1809 | if (!dirty) |
1810 | pte_access &= ~ACC_WRITE_MASK; | |
7b52345e SY |
1811 | if (pte_access & ACC_EXEC_MASK) |
1812 | spte |= shadow_x_mask; | |
1813 | else | |
1814 | spte |= shadow_nx_mask; | |
1c4f1fd6 | 1815 | if (pte_access & ACC_USER_MASK) |
7b52345e | 1816 | spte |= shadow_user_mask; |
852e3c19 | 1817 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 1818 | spte |= PT_PAGE_SIZE_MASK; |
4b12f0de SY |
1819 | if (tdp_enabled) |
1820 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, | |
1821 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 1822 | |
1403283a IE |
1823 | if (reset_host_protection) |
1824 | spte |= SPTE_HOST_WRITEABLE; | |
1825 | ||
35149e21 | 1826 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 AK |
1827 | |
1828 | if ((pte_access & ACC_WRITE_MASK) | |
1829 | || (write_fault && !is_write_protection(vcpu) && !user_fault)) { | |
1c4f1fd6 | 1830 | |
852e3c19 JR |
1831 | if (level > PT_PAGE_TABLE_LEVEL && |
1832 | has_wrprotected_page(vcpu->kvm, gfn, level)) { | |
38187c83 MT |
1833 | ret = 1; |
1834 | spte = shadow_trap_nonpresent_pte; | |
1835 | goto set_pte; | |
1836 | } | |
1837 | ||
1c4f1fd6 | 1838 | spte |= PT_WRITABLE_MASK; |
1c4f1fd6 | 1839 | |
ecc5589f MT |
1840 | /* |
1841 | * Optimization: for pte sync, if spte was writable the hash | |
1842 | * lookup is unnecessary (and expensive). Write protection | |
1843 | * is responsibility of mmu_get_page / kvm_sync_page. | |
1844 | * Same reasoning can be applied to dirty page accounting. | |
1845 | */ | |
8dae4445 | 1846 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
1847 | goto set_pte; |
1848 | ||
4731d4c7 | 1849 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
1c4f1fd6 | 1850 | pgprintk("%s: found shadow page for %lx, marking ro\n", |
b8688d51 | 1851 | __func__, gfn); |
1e73f9dd | 1852 | ret = 1; |
1c4f1fd6 | 1853 | pte_access &= ~ACC_WRITE_MASK; |
8dae4445 | 1854 | if (is_writable_pte(spte)) |
1c4f1fd6 | 1855 | spte &= ~PT_WRITABLE_MASK; |
1c4f1fd6 AK |
1856 | } |
1857 | } | |
1858 | ||
1c4f1fd6 AK |
1859 | if (pte_access & ACC_WRITE_MASK) |
1860 | mark_page_dirty(vcpu->kvm, gfn); | |
1861 | ||
38187c83 | 1862 | set_pte: |
d555c333 | 1863 | __set_spte(sptep, spte); |
1e73f9dd MT |
1864 | return ret; |
1865 | } | |
1866 | ||
d555c333 | 1867 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd MT |
1868 | unsigned pt_access, unsigned pte_access, |
1869 | int user_fault, int write_fault, int dirty, | |
852e3c19 | 1870 | int *ptwrite, int level, gfn_t gfn, |
1403283a IE |
1871 | pfn_t pfn, bool speculative, |
1872 | bool reset_host_protection) | |
1e73f9dd MT |
1873 | { |
1874 | int was_rmapped = 0; | |
8dae4445 | 1875 | int was_writable = is_writable_pte(*sptep); |
53a27b39 | 1876 | int rmap_count; |
1e73f9dd MT |
1877 | |
1878 | pgprintk("%s: spte %llx access %x write_fault %d" | |
1879 | " user_fault %d gfn %lx\n", | |
d555c333 | 1880 | __func__, *sptep, pt_access, |
1e73f9dd MT |
1881 | write_fault, user_fault, gfn); |
1882 | ||
d555c333 | 1883 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
1884 | /* |
1885 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
1886 | * the parent of the now unreachable PTE. | |
1887 | */ | |
852e3c19 JR |
1888 | if (level > PT_PAGE_TABLE_LEVEL && |
1889 | !is_large_pte(*sptep)) { | |
1e73f9dd | 1890 | struct kvm_mmu_page *child; |
d555c333 | 1891 | u64 pte = *sptep; |
1e73f9dd MT |
1892 | |
1893 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
d555c333 AK |
1894 | mmu_page_remove_parent_pte(child, sptep); |
1895 | } else if (pfn != spte_to_pfn(*sptep)) { | |
1e73f9dd | 1896 | pgprintk("hfn old %lx new %lx\n", |
d555c333 AK |
1897 | spte_to_pfn(*sptep), pfn); |
1898 | rmap_remove(vcpu->kvm, sptep); | |
6bed6b9e JR |
1899 | } else |
1900 | was_rmapped = 1; | |
1e73f9dd | 1901 | } |
852e3c19 | 1902 | |
d555c333 | 1903 | if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault, |
1403283a IE |
1904 | dirty, level, gfn, pfn, speculative, true, |
1905 | reset_host_protection)) { | |
1e73f9dd MT |
1906 | if (write_fault) |
1907 | *ptwrite = 1; | |
a378b4e6 MT |
1908 | kvm_x86_ops->tlb_flush(vcpu); |
1909 | } | |
1e73f9dd | 1910 | |
d555c333 | 1911 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
1e73f9dd | 1912 | pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n", |
d555c333 | 1913 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
1914 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
1915 | *sptep, sptep); | |
d555c333 | 1916 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
1917 | ++vcpu->kvm->stat.lpages; |
1918 | ||
d555c333 | 1919 | page_header_update_slot(vcpu->kvm, sptep, gfn); |
1c4f1fd6 | 1920 | if (!was_rmapped) { |
44ad9944 | 1921 | rmap_count = rmap_add(vcpu, sptep, gfn); |
acb66dd0 | 1922 | kvm_release_pfn_clean(pfn); |
53a27b39 | 1923 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) |
852e3c19 | 1924 | rmap_recycle(vcpu, sptep, gfn); |
75e68e60 | 1925 | } else { |
8dae4445 | 1926 | if (was_writable) |
35149e21 | 1927 | kvm_release_pfn_dirty(pfn); |
75e68e60 | 1928 | else |
35149e21 | 1929 | kvm_release_pfn_clean(pfn); |
1c4f1fd6 | 1930 | } |
1b7fcd32 | 1931 | if (speculative) { |
d555c333 | 1932 | vcpu->arch.last_pte_updated = sptep; |
1b7fcd32 AK |
1933 | vcpu->arch.last_pte_gfn = gfn; |
1934 | } | |
1c4f1fd6 AK |
1935 | } |
1936 | ||
6aa8b732 AK |
1937 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
1938 | { | |
1939 | } | |
1940 | ||
9f652d21 | 1941 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
852e3c19 | 1942 | int level, gfn_t gfn, pfn_t pfn) |
140754bc | 1943 | { |
9f652d21 | 1944 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 1945 | struct kvm_mmu_page *sp; |
9f652d21 | 1946 | int pt_write = 0; |
140754bc | 1947 | gfn_t pseudo_gfn; |
6aa8b732 | 1948 | |
9f652d21 | 1949 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 1950 | if (iterator.level == level) { |
9f652d21 AK |
1951 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL, |
1952 | 0, write, 1, &pt_write, | |
1403283a | 1953 | level, gfn, pfn, false, true); |
9f652d21 AK |
1954 | ++vcpu->stat.pf_fixed; |
1955 | break; | |
6aa8b732 AK |
1956 | } |
1957 | ||
9f652d21 AK |
1958 | if (*iterator.sptep == shadow_trap_nonpresent_pte) { |
1959 | pseudo_gfn = (iterator.addr & PT64_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT; | |
1960 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, | |
1961 | iterator.level - 1, | |
1962 | 1, ACC_ALL, iterator.sptep); | |
1963 | if (!sp) { | |
1964 | pgprintk("nonpaging_map: ENOMEM\n"); | |
1965 | kvm_release_pfn_clean(pfn); | |
1966 | return -ENOMEM; | |
1967 | } | |
140754bc | 1968 | |
d555c333 AK |
1969 | __set_spte(iterator.sptep, |
1970 | __pa(sp->spt) | |
1971 | | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
1972 | | shadow_user_mask | shadow_x_mask); | |
9f652d21 AK |
1973 | } |
1974 | } | |
1975 | return pt_write; | |
6aa8b732 AK |
1976 | } |
1977 | ||
10589a46 MT |
1978 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn) |
1979 | { | |
1980 | int r; | |
852e3c19 | 1981 | int level; |
35149e21 | 1982 | pfn_t pfn; |
e930bffe | 1983 | unsigned long mmu_seq; |
aaee2c94 | 1984 | |
852e3c19 JR |
1985 | level = mapping_level(vcpu, gfn); |
1986 | ||
1987 | /* | |
1988 | * This path builds a PAE pagetable - so we can map 2mb pages at | |
1989 | * maximum. Therefore check if the level is larger than that. | |
1990 | */ | |
1991 | if (level > PT_DIRECTORY_LEVEL) | |
1992 | level = PT_DIRECTORY_LEVEL; | |
1993 | ||
1994 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 1995 | |
e930bffe | 1996 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 1997 | smp_rmb(); |
35149e21 | 1998 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
aaee2c94 | 1999 | |
d196e343 | 2000 | /* mmio */ |
35149e21 AL |
2001 | if (is_error_pfn(pfn)) { |
2002 | kvm_release_pfn_clean(pfn); | |
d196e343 AK |
2003 | return 1; |
2004 | } | |
2005 | ||
aaee2c94 | 2006 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2007 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2008 | goto out_unlock; | |
eb787d10 | 2009 | kvm_mmu_free_some_pages(vcpu); |
852e3c19 | 2010 | r = __direct_map(vcpu, v, write, level, gfn, pfn); |
aaee2c94 MT |
2011 | spin_unlock(&vcpu->kvm->mmu_lock); |
2012 | ||
aaee2c94 | 2013 | |
10589a46 | 2014 | return r; |
e930bffe AA |
2015 | |
2016 | out_unlock: | |
2017 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2018 | kvm_release_pfn_clean(pfn); | |
2019 | return 0; | |
10589a46 MT |
2020 | } |
2021 | ||
2022 | ||
17ac10ad AK |
2023 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
2024 | { | |
2025 | int i; | |
4db35314 | 2026 | struct kvm_mmu_page *sp; |
17ac10ad | 2027 | |
ad312c7c | 2028 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 2029 | return; |
aaee2c94 | 2030 | spin_lock(&vcpu->kvm->mmu_lock); |
ad312c7c ZX |
2031 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { |
2032 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
17ac10ad | 2033 | |
4db35314 AK |
2034 | sp = page_header(root); |
2035 | --sp->root_count; | |
2e53d63a MT |
2036 | if (!sp->root_count && sp->role.invalid) |
2037 | kvm_mmu_zap_page(vcpu->kvm, sp); | |
ad312c7c | 2038 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
aaee2c94 | 2039 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad AK |
2040 | return; |
2041 | } | |
17ac10ad | 2042 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2043 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2044 | |
417726a3 | 2045 | if (root) { |
417726a3 | 2046 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2047 | sp = page_header(root); |
2048 | --sp->root_count; | |
2e53d63a MT |
2049 | if (!sp->root_count && sp->role.invalid) |
2050 | kvm_mmu_zap_page(vcpu->kvm, sp); | |
417726a3 | 2051 | } |
ad312c7c | 2052 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2053 | } |
aaee2c94 | 2054 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2055 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2056 | } |
2057 | ||
8986ecc0 MT |
2058 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2059 | { | |
2060 | int ret = 0; | |
2061 | ||
2062 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
2063 | set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests); | |
2064 | ret = 1; | |
2065 | } | |
2066 | ||
2067 | return ret; | |
2068 | } | |
2069 | ||
2070 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) | |
17ac10ad AK |
2071 | { |
2072 | int i; | |
cea0f0e7 | 2073 | gfn_t root_gfn; |
4db35314 | 2074 | struct kvm_mmu_page *sp; |
f6e2c02b | 2075 | int direct = 0; |
6de4f3ad | 2076 | u64 pdptr; |
3bb65a22 | 2077 | |
ad312c7c | 2078 | root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT; |
17ac10ad | 2079 | |
ad312c7c ZX |
2080 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { |
2081 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
17ac10ad AK |
2082 | |
2083 | ASSERT(!VALID_PAGE(root)); | |
fb72d167 | 2084 | if (tdp_enabled) |
f6e2c02b | 2085 | direct = 1; |
8986ecc0 MT |
2086 | if (mmu_check_root(vcpu, root_gfn)) |
2087 | return 1; | |
4db35314 | 2088 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, |
f6e2c02b | 2089 | PT64_ROOT_LEVEL, direct, |
fb72d167 | 2090 | ACC_ALL, NULL); |
4db35314 AK |
2091 | root = __pa(sp->spt); |
2092 | ++sp->root_count; | |
ad312c7c | 2093 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 2094 | return 0; |
17ac10ad | 2095 | } |
f6e2c02b | 2096 | direct = !is_paging(vcpu); |
fb72d167 | 2097 | if (tdp_enabled) |
f6e2c02b | 2098 | direct = 1; |
17ac10ad | 2099 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2100 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
2101 | |
2102 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 2103 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
6de4f3ad | 2104 | pdptr = kvm_pdptr_read(vcpu, i); |
43a3795a | 2105 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 2106 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
2107 | continue; |
2108 | } | |
6de4f3ad | 2109 | root_gfn = pdptr >> PAGE_SHIFT; |
ad312c7c | 2110 | } else if (vcpu->arch.mmu.root_level == 0) |
cea0f0e7 | 2111 | root_gfn = 0; |
8986ecc0 MT |
2112 | if (mmu_check_root(vcpu, root_gfn)) |
2113 | return 1; | |
4db35314 | 2114 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
f6e2c02b | 2115 | PT32_ROOT_LEVEL, direct, |
f7d9c7b7 | 2116 | ACC_ALL, NULL); |
4db35314 AK |
2117 | root = __pa(sp->spt); |
2118 | ++sp->root_count; | |
ad312c7c | 2119 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; |
17ac10ad | 2120 | } |
ad312c7c | 2121 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
8986ecc0 | 2122 | return 0; |
17ac10ad AK |
2123 | } |
2124 | ||
0ba73cda MT |
2125 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
2126 | { | |
2127 | int i; | |
2128 | struct kvm_mmu_page *sp; | |
2129 | ||
2130 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
2131 | return; | |
2132 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2133 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
2134 | sp = page_header(root); | |
2135 | mmu_sync_children(vcpu, sp); | |
2136 | return; | |
2137 | } | |
2138 | for (i = 0; i < 4; ++i) { | |
2139 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2140 | ||
8986ecc0 | 2141 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
2142 | root &= PT64_BASE_ADDR_MASK; |
2143 | sp = page_header(root); | |
2144 | mmu_sync_children(vcpu, sp); | |
2145 | } | |
2146 | } | |
2147 | } | |
2148 | ||
2149 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
2150 | { | |
2151 | spin_lock(&vcpu->kvm->mmu_lock); | |
2152 | mmu_sync_roots(vcpu); | |
6cffe8ca | 2153 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
2154 | } |
2155 | ||
1871c602 GN |
2156 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
2157 | u32 access, u32 *error) | |
6aa8b732 | 2158 | { |
1871c602 GN |
2159 | if (error) |
2160 | *error = 0; | |
6aa8b732 AK |
2161 | return vaddr; |
2162 | } | |
2163 | ||
2164 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, | |
3f3e7124 | 2165 | u32 error_code) |
6aa8b732 | 2166 | { |
e833240f | 2167 | gfn_t gfn; |
e2dec939 | 2168 | int r; |
6aa8b732 | 2169 | |
b8688d51 | 2170 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
e2dec939 AK |
2171 | r = mmu_topup_memory_caches(vcpu); |
2172 | if (r) | |
2173 | return r; | |
714b93da | 2174 | |
6aa8b732 | 2175 | ASSERT(vcpu); |
ad312c7c | 2176 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 2177 | |
e833240f | 2178 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 2179 | |
e833240f AK |
2180 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
2181 | error_code & PFERR_WRITE_MASK, gfn); | |
6aa8b732 AK |
2182 | } |
2183 | ||
fb72d167 JR |
2184 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, |
2185 | u32 error_code) | |
2186 | { | |
35149e21 | 2187 | pfn_t pfn; |
fb72d167 | 2188 | int r; |
852e3c19 | 2189 | int level; |
05da4558 | 2190 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 2191 | unsigned long mmu_seq; |
fb72d167 JR |
2192 | |
2193 | ASSERT(vcpu); | |
2194 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
2195 | ||
2196 | r = mmu_topup_memory_caches(vcpu); | |
2197 | if (r) | |
2198 | return r; | |
2199 | ||
852e3c19 JR |
2200 | level = mapping_level(vcpu, gfn); |
2201 | ||
2202 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
2203 | ||
e930bffe | 2204 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2205 | smp_rmb(); |
35149e21 | 2206 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
35149e21 AL |
2207 | if (is_error_pfn(pfn)) { |
2208 | kvm_release_pfn_clean(pfn); | |
fb72d167 JR |
2209 | return 1; |
2210 | } | |
2211 | spin_lock(&vcpu->kvm->mmu_lock); | |
e930bffe AA |
2212 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2213 | goto out_unlock; | |
fb72d167 JR |
2214 | kvm_mmu_free_some_pages(vcpu); |
2215 | r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK, | |
852e3c19 | 2216 | level, gfn, pfn); |
fb72d167 | 2217 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
2218 | |
2219 | return r; | |
e930bffe AA |
2220 | |
2221 | out_unlock: | |
2222 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2223 | kvm_release_pfn_clean(pfn); | |
2224 | return 0; | |
fb72d167 JR |
2225 | } |
2226 | ||
6aa8b732 AK |
2227 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
2228 | { | |
17ac10ad | 2229 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2230 | } |
2231 | ||
2232 | static int nonpaging_init_context(struct kvm_vcpu *vcpu) | |
2233 | { | |
ad312c7c | 2234 | struct kvm_mmu *context = &vcpu->arch.mmu; |
6aa8b732 AK |
2235 | |
2236 | context->new_cr3 = nonpaging_new_cr3; | |
2237 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
2238 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
2239 | context->free = nonpaging_free; | |
c7addb90 | 2240 | context->prefetch_page = nonpaging_prefetch_page; |
e8bc217a | 2241 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2242 | context->invlpg = nonpaging_invlpg; |
cea0f0e7 | 2243 | context->root_level = 0; |
6aa8b732 | 2244 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 2245 | context->root_hpa = INVALID_PAGE; |
6aa8b732 AK |
2246 | return 0; |
2247 | } | |
2248 | ||
d835dfec | 2249 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 2250 | { |
1165f5fe | 2251 | ++vcpu->stat.tlb_flush; |
cbdd1bea | 2252 | kvm_x86_ops->tlb_flush(vcpu); |
6aa8b732 AK |
2253 | } |
2254 | ||
2255 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
2256 | { | |
b8688d51 | 2257 | pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3); |
cea0f0e7 | 2258 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2259 | } |
2260 | ||
6aa8b732 AK |
2261 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
2262 | u64 addr, | |
2263 | u32 err_code) | |
2264 | { | |
c3c91fee | 2265 | kvm_inject_page_fault(vcpu, addr, err_code); |
6aa8b732 AK |
2266 | } |
2267 | ||
6aa8b732 AK |
2268 | static void paging_free(struct kvm_vcpu *vcpu) |
2269 | { | |
2270 | nonpaging_free(vcpu); | |
2271 | } | |
2272 | ||
82725b20 DE |
2273 | static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level) |
2274 | { | |
2275 | int bit7; | |
2276 | ||
2277 | bit7 = (gpte >> 7) & 1; | |
2278 | return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0; | |
2279 | } | |
2280 | ||
6aa8b732 AK |
2281 | #define PTTYPE 64 |
2282 | #include "paging_tmpl.h" | |
2283 | #undef PTTYPE | |
2284 | ||
2285 | #define PTTYPE 32 | |
2286 | #include "paging_tmpl.h" | |
2287 | #undef PTTYPE | |
2288 | ||
82725b20 DE |
2289 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level) |
2290 | { | |
2291 | struct kvm_mmu *context = &vcpu->arch.mmu; | |
2292 | int maxphyaddr = cpuid_maxphyaddr(vcpu); | |
2293 | u64 exb_bit_rsvd = 0; | |
2294 | ||
2295 | if (!is_nx(vcpu)) | |
2296 | exb_bit_rsvd = rsvd_bits(63, 63); | |
2297 | switch (level) { | |
2298 | case PT32_ROOT_LEVEL: | |
2299 | /* no rsvd bits for 2 level 4K page table entries */ | |
2300 | context->rsvd_bits_mask[0][1] = 0; | |
2301 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
2302 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
2303 | ||
2304 | if (!is_pse(vcpu)) { | |
2305 | context->rsvd_bits_mask[1][1] = 0; | |
2306 | break; | |
2307 | } | |
2308 | ||
82725b20 DE |
2309 | if (is_cpuid_PSE36()) |
2310 | /* 36bits PSE 4MB page */ | |
2311 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
2312 | else | |
2313 | /* 32 bits PSE 4MB page */ | |
2314 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
2315 | break; |
2316 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
2317 | context->rsvd_bits_mask[0][2] = |
2318 | rsvd_bits(maxphyaddr, 63) | | |
2319 | rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ | |
82725b20 | 2320 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 2321 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
2322 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2323 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
2324 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
2325 | rsvd_bits(maxphyaddr, 62) | | |
2326 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2327 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2328 | break; |
2329 | case PT64_ROOT_LEVEL: | |
2330 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
2331 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2332 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | | |
2333 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2334 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | | |
4c26b4cd | 2335 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
2336 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2337 | rsvd_bits(maxphyaddr, 51); | |
2338 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 JR |
2339 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
2340 | rsvd_bits(maxphyaddr, 51) | | |
2341 | rsvd_bits(13, 29); | |
82725b20 | 2342 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
2343 | rsvd_bits(maxphyaddr, 51) | |
2344 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2345 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2346 | break; |
2347 | } | |
2348 | } | |
2349 | ||
17ac10ad | 2350 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level) |
6aa8b732 | 2351 | { |
ad312c7c | 2352 | struct kvm_mmu *context = &vcpu->arch.mmu; |
6aa8b732 AK |
2353 | |
2354 | ASSERT(is_pae(vcpu)); | |
2355 | context->new_cr3 = paging_new_cr3; | |
2356 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 2357 | context->gva_to_gpa = paging64_gva_to_gpa; |
c7addb90 | 2358 | context->prefetch_page = paging64_prefetch_page; |
e8bc217a | 2359 | context->sync_page = paging64_sync_page; |
a7052897 | 2360 | context->invlpg = paging64_invlpg; |
6aa8b732 | 2361 | context->free = paging_free; |
17ac10ad AK |
2362 | context->root_level = level; |
2363 | context->shadow_root_level = level; | |
17c3ba9d | 2364 | context->root_hpa = INVALID_PAGE; |
6aa8b732 AK |
2365 | return 0; |
2366 | } | |
2367 | ||
17ac10ad AK |
2368 | static int paging64_init_context(struct kvm_vcpu *vcpu) |
2369 | { | |
82725b20 | 2370 | reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL); |
17ac10ad AK |
2371 | return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL); |
2372 | } | |
2373 | ||
6aa8b732 AK |
2374 | static int paging32_init_context(struct kvm_vcpu *vcpu) |
2375 | { | |
ad312c7c | 2376 | struct kvm_mmu *context = &vcpu->arch.mmu; |
6aa8b732 | 2377 | |
82725b20 | 2378 | reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL); |
6aa8b732 AK |
2379 | context->new_cr3 = paging_new_cr3; |
2380 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
2381 | context->gva_to_gpa = paging32_gva_to_gpa; |
2382 | context->free = paging_free; | |
c7addb90 | 2383 | context->prefetch_page = paging32_prefetch_page; |
e8bc217a | 2384 | context->sync_page = paging32_sync_page; |
a7052897 | 2385 | context->invlpg = paging32_invlpg; |
6aa8b732 AK |
2386 | context->root_level = PT32_ROOT_LEVEL; |
2387 | context->shadow_root_level = PT32E_ROOT_LEVEL; | |
17c3ba9d | 2388 | context->root_hpa = INVALID_PAGE; |
6aa8b732 AK |
2389 | return 0; |
2390 | } | |
2391 | ||
2392 | static int paging32E_init_context(struct kvm_vcpu *vcpu) | |
2393 | { | |
82725b20 | 2394 | reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL); |
17ac10ad | 2395 | return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
2396 | } |
2397 | ||
fb72d167 JR |
2398 | static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
2399 | { | |
2400 | struct kvm_mmu *context = &vcpu->arch.mmu; | |
2401 | ||
2402 | context->new_cr3 = nonpaging_new_cr3; | |
2403 | context->page_fault = tdp_page_fault; | |
2404 | context->free = nonpaging_free; | |
2405 | context->prefetch_page = nonpaging_prefetch_page; | |
e8bc217a | 2406 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2407 | context->invlpg = nonpaging_invlpg; |
67253af5 | 2408 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 JR |
2409 | context->root_hpa = INVALID_PAGE; |
2410 | ||
2411 | if (!is_paging(vcpu)) { | |
2412 | context->gva_to_gpa = nonpaging_gva_to_gpa; | |
2413 | context->root_level = 0; | |
2414 | } else if (is_long_mode(vcpu)) { | |
82725b20 | 2415 | reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL); |
fb72d167 JR |
2416 | context->gva_to_gpa = paging64_gva_to_gpa; |
2417 | context->root_level = PT64_ROOT_LEVEL; | |
2418 | } else if (is_pae(vcpu)) { | |
82725b20 | 2419 | reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL); |
fb72d167 JR |
2420 | context->gva_to_gpa = paging64_gva_to_gpa; |
2421 | context->root_level = PT32E_ROOT_LEVEL; | |
2422 | } else { | |
82725b20 | 2423 | reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL); |
fb72d167 JR |
2424 | context->gva_to_gpa = paging32_gva_to_gpa; |
2425 | context->root_level = PT32_ROOT_LEVEL; | |
2426 | } | |
2427 | ||
2428 | return 0; | |
2429 | } | |
2430 | ||
2431 | static int init_kvm_softmmu(struct kvm_vcpu *vcpu) | |
6aa8b732 | 2432 | { |
a770f6f2 AK |
2433 | int r; |
2434 | ||
6aa8b732 | 2435 | ASSERT(vcpu); |
ad312c7c | 2436 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
2437 | |
2438 | if (!is_paging(vcpu)) | |
a770f6f2 | 2439 | r = nonpaging_init_context(vcpu); |
a9058ecd | 2440 | else if (is_long_mode(vcpu)) |
a770f6f2 | 2441 | r = paging64_init_context(vcpu); |
6aa8b732 | 2442 | else if (is_pae(vcpu)) |
a770f6f2 | 2443 | r = paging32E_init_context(vcpu); |
6aa8b732 | 2444 | else |
a770f6f2 AK |
2445 | r = paging32_init_context(vcpu); |
2446 | ||
2447 | vcpu->arch.mmu.base_role.glevels = vcpu->arch.mmu.root_level; | |
2448 | ||
2449 | return r; | |
6aa8b732 AK |
2450 | } |
2451 | ||
fb72d167 JR |
2452 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) |
2453 | { | |
35149e21 AL |
2454 | vcpu->arch.update_pte.pfn = bad_pfn; |
2455 | ||
fb72d167 JR |
2456 | if (tdp_enabled) |
2457 | return init_kvm_tdp_mmu(vcpu); | |
2458 | else | |
2459 | return init_kvm_softmmu(vcpu); | |
2460 | } | |
2461 | ||
6aa8b732 AK |
2462 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) |
2463 | { | |
2464 | ASSERT(vcpu); | |
ad312c7c ZX |
2465 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) { |
2466 | vcpu->arch.mmu.free(vcpu); | |
2467 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; | |
6aa8b732 AK |
2468 | } |
2469 | } | |
2470 | ||
2471 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
2472 | { |
2473 | destroy_kvm_mmu(vcpu); | |
2474 | return init_kvm_mmu(vcpu); | |
2475 | } | |
8668a3c4 | 2476 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
2477 | |
2478 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 2479 | { |
714b93da AK |
2480 | int r; |
2481 | ||
e2dec939 | 2482 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
2483 | if (r) |
2484 | goto out; | |
aaee2c94 | 2485 | spin_lock(&vcpu->kvm->mmu_lock); |
eb787d10 | 2486 | kvm_mmu_free_some_pages(vcpu); |
8986ecc0 | 2487 | r = mmu_alloc_roots(vcpu); |
0ba73cda | 2488 | mmu_sync_roots(vcpu); |
aaee2c94 | 2489 | spin_unlock(&vcpu->kvm->mmu_lock); |
8986ecc0 MT |
2490 | if (r) |
2491 | goto out; | |
3662cb1c | 2492 | /* set_cr3() should ensure TLB has been flushed */ |
ad312c7c | 2493 | kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
2494 | out: |
2495 | return r; | |
6aa8b732 | 2496 | } |
17c3ba9d AK |
2497 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
2498 | ||
2499 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
2500 | { | |
2501 | mmu_free_roots(vcpu); | |
2502 | } | |
6aa8b732 | 2503 | |
09072daf | 2504 | static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu, |
4db35314 | 2505 | struct kvm_mmu_page *sp, |
ac1b714e AK |
2506 | u64 *spte) |
2507 | { | |
2508 | u64 pte; | |
2509 | struct kvm_mmu_page *child; | |
2510 | ||
2511 | pte = *spte; | |
c7addb90 | 2512 | if (is_shadow_present_pte(pte)) { |
776e6633 | 2513 | if (is_last_spte(pte, sp->role.level)) |
290fc38d | 2514 | rmap_remove(vcpu->kvm, spte); |
ac1b714e AK |
2515 | else { |
2516 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
90cb0529 | 2517 | mmu_page_remove_parent_pte(child, spte); |
ac1b714e AK |
2518 | } |
2519 | } | |
d555c333 | 2520 | __set_spte(spte, shadow_trap_nonpresent_pte); |
05da4558 MT |
2521 | if (is_large_pte(pte)) |
2522 | --vcpu->kvm->stat.lpages; | |
ac1b714e AK |
2523 | } |
2524 | ||
0028425f | 2525 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
4db35314 | 2526 | struct kvm_mmu_page *sp, |
0028425f | 2527 | u64 *spte, |
489f1d65 | 2528 | const void *new) |
0028425f | 2529 | { |
30945387 | 2530 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
2531 | ++vcpu->kvm->stat.mmu_pde_zapped; |
2532 | return; | |
30945387 | 2533 | } |
0028425f | 2534 | |
4cee5764 | 2535 | ++vcpu->kvm->stat.mmu_pte_updated; |
4db35314 | 2536 | if (sp->role.glevels == PT32_ROOT_LEVEL) |
489f1d65 | 2537 | paging32_update_pte(vcpu, sp, spte, new); |
0028425f | 2538 | else |
489f1d65 | 2539 | paging64_update_pte(vcpu, sp, spte, new); |
0028425f AK |
2540 | } |
2541 | ||
79539cec AK |
2542 | static bool need_remote_flush(u64 old, u64 new) |
2543 | { | |
2544 | if (!is_shadow_present_pte(old)) | |
2545 | return false; | |
2546 | if (!is_shadow_present_pte(new)) | |
2547 | return true; | |
2548 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
2549 | return true; | |
2550 | old ^= PT64_NX_MASK; | |
2551 | new ^= PT64_NX_MASK; | |
2552 | return (old & ~new & PT64_PERM_MASK) != 0; | |
2553 | } | |
2554 | ||
2555 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new) | |
2556 | { | |
2557 | if (need_remote_flush(old, new)) | |
2558 | kvm_flush_remote_tlbs(vcpu->kvm); | |
2559 | else | |
2560 | kvm_mmu_flush_tlb(vcpu); | |
2561 | } | |
2562 | ||
12b7d28f AK |
2563 | static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu) |
2564 | { | |
ad312c7c | 2565 | u64 *spte = vcpu->arch.last_pte_updated; |
12b7d28f | 2566 | |
7b52345e | 2567 | return !!(spte && (*spte & shadow_accessed_mask)); |
12b7d28f AK |
2568 | } |
2569 | ||
d7824fff | 2570 | static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
72016f3a | 2571 | u64 gpte) |
d7824fff AK |
2572 | { |
2573 | gfn_t gfn; | |
35149e21 | 2574 | pfn_t pfn; |
d7824fff | 2575 | |
43a3795a | 2576 | if (!is_present_gpte(gpte)) |
d7824fff AK |
2577 | return; |
2578 | gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; | |
72dc67a6 | 2579 | |
e930bffe | 2580 | vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2581 | smp_rmb(); |
35149e21 | 2582 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
72dc67a6 | 2583 | |
35149e21 AL |
2584 | if (is_error_pfn(pfn)) { |
2585 | kvm_release_pfn_clean(pfn); | |
d196e343 AK |
2586 | return; |
2587 | } | |
d7824fff | 2588 | vcpu->arch.update_pte.gfn = gfn; |
35149e21 | 2589 | vcpu->arch.update_pte.pfn = pfn; |
d7824fff AK |
2590 | } |
2591 | ||
1b7fcd32 AK |
2592 | static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn) |
2593 | { | |
2594 | u64 *spte = vcpu->arch.last_pte_updated; | |
2595 | ||
2596 | if (spte | |
2597 | && vcpu->arch.last_pte_gfn == gfn | |
2598 | && shadow_accessed_mask | |
2599 | && !(*spte & shadow_accessed_mask) | |
2600 | && is_shadow_present_pte(*spte)) | |
2601 | set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
2602 | } | |
2603 | ||
09072daf | 2604 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
ad218f85 MT |
2605 | const u8 *new, int bytes, |
2606 | bool guest_initiated) | |
da4a00f0 | 2607 | { |
9b7a0325 | 2608 | gfn_t gfn = gpa >> PAGE_SHIFT; |
4db35314 | 2609 | struct kvm_mmu_page *sp; |
0e7bc4b9 | 2610 | struct hlist_node *node, *n; |
9b7a0325 AK |
2611 | struct hlist_head *bucket; |
2612 | unsigned index; | |
489f1d65 | 2613 | u64 entry, gentry; |
9b7a0325 | 2614 | u64 *spte; |
9b7a0325 | 2615 | unsigned offset = offset_in_page(gpa); |
0e7bc4b9 | 2616 | unsigned pte_size; |
9b7a0325 | 2617 | unsigned page_offset; |
0e7bc4b9 | 2618 | unsigned misaligned; |
fce0657f | 2619 | unsigned quadrant; |
9b7a0325 | 2620 | int level; |
86a5ba02 | 2621 | int flooded = 0; |
ac1b714e | 2622 | int npte; |
489f1d65 | 2623 | int r; |
08e850c6 | 2624 | int invlpg_counter; |
9b7a0325 | 2625 | |
b8688d51 | 2626 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); |
72016f3a | 2627 | |
08e850c6 | 2628 | invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter); |
72016f3a AK |
2629 | |
2630 | /* | |
2631 | * Assume that the pte write on a page table of the same type | |
2632 | * as the current vcpu paging mode. This is nearly always true | |
2633 | * (might be false while changing modes). Note it is verified later | |
2634 | * by update_pte(). | |
2635 | */ | |
08e850c6 | 2636 | if ((is_pae(vcpu) && bytes == 4) || !new) { |
72016f3a | 2637 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
08e850c6 AK |
2638 | if (is_pae(vcpu)) { |
2639 | gpa &= ~(gpa_t)7; | |
2640 | bytes = 8; | |
2641 | } | |
2642 | r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8)); | |
72016f3a AK |
2643 | if (r) |
2644 | gentry = 0; | |
08e850c6 AK |
2645 | new = (const u8 *)&gentry; |
2646 | } | |
2647 | ||
2648 | switch (bytes) { | |
2649 | case 4: | |
2650 | gentry = *(const u32 *)new; | |
2651 | break; | |
2652 | case 8: | |
2653 | gentry = *(const u64 *)new; | |
2654 | break; | |
2655 | default: | |
2656 | gentry = 0; | |
2657 | break; | |
72016f3a AK |
2658 | } |
2659 | ||
2660 | mmu_guess_page_from_pte_write(vcpu, gpa, gentry); | |
aaee2c94 | 2661 | spin_lock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
2662 | if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter) |
2663 | gentry = 0; | |
1b7fcd32 | 2664 | kvm_mmu_access_page(vcpu, gfn); |
eb787d10 | 2665 | kvm_mmu_free_some_pages(vcpu); |
4cee5764 | 2666 | ++vcpu->kvm->stat.mmu_pte_write; |
c7addb90 | 2667 | kvm_mmu_audit(vcpu, "pre pte write"); |
ad218f85 MT |
2668 | if (guest_initiated) { |
2669 | if (gfn == vcpu->arch.last_pt_write_gfn | |
2670 | && !last_updated_pte_accessed(vcpu)) { | |
2671 | ++vcpu->arch.last_pt_write_count; | |
2672 | if (vcpu->arch.last_pt_write_count >= 3) | |
2673 | flooded = 1; | |
2674 | } else { | |
2675 | vcpu->arch.last_pt_write_gfn = gfn; | |
2676 | vcpu->arch.last_pt_write_count = 1; | |
2677 | vcpu->arch.last_pte_updated = NULL; | |
2678 | } | |
86a5ba02 | 2679 | } |
1ae0a13d | 2680 | index = kvm_page_table_hashfn(gfn); |
f05e70ac | 2681 | bucket = &vcpu->kvm->arch.mmu_page_hash[index]; |
4db35314 | 2682 | hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) { |
f6e2c02b | 2683 | if (sp->gfn != gfn || sp->role.direct || sp->role.invalid) |
9b7a0325 | 2684 | continue; |
4db35314 | 2685 | pte_size = sp->role.glevels == PT32_ROOT_LEVEL ? 4 : 8; |
0e7bc4b9 | 2686 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
e925c5ba | 2687 | misaligned |= bytes < 4; |
86a5ba02 | 2688 | if (misaligned || flooded) { |
0e7bc4b9 AK |
2689 | /* |
2690 | * Misaligned accesses are too much trouble to fix | |
2691 | * up; also, they usually indicate a page is not used | |
2692 | * as a page table. | |
86a5ba02 AK |
2693 | * |
2694 | * If we're seeing too many writes to a page, | |
2695 | * it may no longer be a page table, or we may be | |
2696 | * forking, in which case it is better to unmap the | |
2697 | * page. | |
0e7bc4b9 AK |
2698 | */ |
2699 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4db35314 | 2700 | gpa, bytes, sp->role.word); |
07385413 MT |
2701 | if (kvm_mmu_zap_page(vcpu->kvm, sp)) |
2702 | n = bucket->first; | |
4cee5764 | 2703 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
2704 | continue; |
2705 | } | |
9b7a0325 | 2706 | page_offset = offset; |
4db35314 | 2707 | level = sp->role.level; |
ac1b714e | 2708 | npte = 1; |
4db35314 | 2709 | if (sp->role.glevels == PT32_ROOT_LEVEL) { |
ac1b714e AK |
2710 | page_offset <<= 1; /* 32->64 */ |
2711 | /* | |
2712 | * A 32-bit pde maps 4MB while the shadow pdes map | |
2713 | * only 2MB. So we need to double the offset again | |
2714 | * and zap two pdes instead of one. | |
2715 | */ | |
2716 | if (level == PT32_ROOT_LEVEL) { | |
6b8d0f9b | 2717 | page_offset &= ~7; /* kill rounding error */ |
ac1b714e AK |
2718 | page_offset <<= 1; |
2719 | npte = 2; | |
2720 | } | |
fce0657f | 2721 | quadrant = page_offset >> PAGE_SHIFT; |
9b7a0325 | 2722 | page_offset &= ~PAGE_MASK; |
4db35314 | 2723 | if (quadrant != sp->role.quadrant) |
fce0657f | 2724 | continue; |
9b7a0325 | 2725 | } |
4db35314 | 2726 | spte = &sp->spt[page_offset / sizeof(*spte)]; |
ac1b714e | 2727 | while (npte--) { |
79539cec | 2728 | entry = *spte; |
4db35314 | 2729 | mmu_pte_write_zap_pte(vcpu, sp, spte); |
72016f3a AK |
2730 | if (gentry) |
2731 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); | |
79539cec | 2732 | mmu_pte_write_flush_tlb(vcpu, entry, *spte); |
ac1b714e | 2733 | ++spte; |
9b7a0325 | 2734 | } |
9b7a0325 | 2735 | } |
c7addb90 | 2736 | kvm_mmu_audit(vcpu, "post pte write"); |
aaee2c94 | 2737 | spin_unlock(&vcpu->kvm->mmu_lock); |
35149e21 AL |
2738 | if (!is_error_pfn(vcpu->arch.update_pte.pfn)) { |
2739 | kvm_release_pfn_clean(vcpu->arch.update_pte.pfn); | |
2740 | vcpu->arch.update_pte.pfn = bad_pfn; | |
d7824fff | 2741 | } |
da4a00f0 AK |
2742 | } |
2743 | ||
a436036b AK |
2744 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
2745 | { | |
10589a46 MT |
2746 | gpa_t gpa; |
2747 | int r; | |
a436036b | 2748 | |
60f24784 AK |
2749 | if (tdp_enabled) |
2750 | return 0; | |
2751 | ||
1871c602 | 2752 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 2753 | |
aaee2c94 | 2754 | spin_lock(&vcpu->kvm->mmu_lock); |
10589a46 | 2755 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
aaee2c94 | 2756 | spin_unlock(&vcpu->kvm->mmu_lock); |
10589a46 | 2757 | return r; |
a436036b | 2758 | } |
577bdc49 | 2759 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 2760 | |
22d95b12 | 2761 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu) |
ebeace86 | 2762 | { |
3b80fffe IE |
2763 | while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES && |
2764 | !list_empty(&vcpu->kvm->arch.active_mmu_pages)) { | |
4db35314 | 2765 | struct kvm_mmu_page *sp; |
ebeace86 | 2766 | |
f05e70ac | 2767 | sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev, |
4db35314 AK |
2768 | struct kvm_mmu_page, link); |
2769 | kvm_mmu_zap_page(vcpu->kvm, sp); | |
4cee5764 | 2770 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 AK |
2771 | } |
2772 | } | |
ebeace86 | 2773 | |
3067714c AK |
2774 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code) |
2775 | { | |
2776 | int r; | |
2777 | enum emulation_result er; | |
2778 | ||
ad312c7c | 2779 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code); |
3067714c AK |
2780 | if (r < 0) |
2781 | goto out; | |
2782 | ||
2783 | if (!r) { | |
2784 | r = 1; | |
2785 | goto out; | |
2786 | } | |
2787 | ||
b733bfb5 AK |
2788 | r = mmu_topup_memory_caches(vcpu); |
2789 | if (r) | |
2790 | goto out; | |
2791 | ||
851ba692 | 2792 | er = emulate_instruction(vcpu, cr2, error_code, 0); |
3067714c AK |
2793 | |
2794 | switch (er) { | |
2795 | case EMULATE_DONE: | |
2796 | return 1; | |
2797 | case EMULATE_DO_MMIO: | |
2798 | ++vcpu->stat.mmio_exits; | |
2799 | return 0; | |
2800 | case EMULATE_FAIL: | |
3f5d18a9 AK |
2801 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
2802 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
a9c7399d | 2803 | vcpu->run->internal.ndata = 0; |
3f5d18a9 | 2804 | return 0; |
3067714c AK |
2805 | default: |
2806 | BUG(); | |
2807 | } | |
2808 | out: | |
3067714c AK |
2809 | return r; |
2810 | } | |
2811 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
2812 | ||
a7052897 MT |
2813 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
2814 | { | |
a7052897 | 2815 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
2816 | kvm_mmu_flush_tlb(vcpu); |
2817 | ++vcpu->stat.invlpg; | |
2818 | } | |
2819 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
2820 | ||
18552672 JR |
2821 | void kvm_enable_tdp(void) |
2822 | { | |
2823 | tdp_enabled = true; | |
2824 | } | |
2825 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
2826 | ||
5f4cb662 JR |
2827 | void kvm_disable_tdp(void) |
2828 | { | |
2829 | tdp_enabled = false; | |
2830 | } | |
2831 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
2832 | ||
6aa8b732 AK |
2833 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
2834 | { | |
ad312c7c | 2835 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
6aa8b732 AK |
2836 | } |
2837 | ||
2838 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
2839 | { | |
17ac10ad | 2840 | struct page *page; |
6aa8b732 AK |
2841 | int i; |
2842 | ||
2843 | ASSERT(vcpu); | |
2844 | ||
17ac10ad AK |
2845 | /* |
2846 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
2847 | * Therefore we need to allocate shadow page tables in the first | |
2848 | * 4GB of memory, which happens to fit the DMA32 zone. | |
2849 | */ | |
2850 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
2851 | if (!page) | |
d7fa6ab2 WY |
2852 | return -ENOMEM; |
2853 | ||
ad312c7c | 2854 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 2855 | for (i = 0; i < 4; ++i) |
ad312c7c | 2856 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2857 | |
6aa8b732 | 2858 | return 0; |
6aa8b732 AK |
2859 | } |
2860 | ||
8018c27b | 2861 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 2862 | { |
6aa8b732 | 2863 | ASSERT(vcpu); |
ad312c7c | 2864 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 2865 | |
8018c27b IM |
2866 | return alloc_mmu_pages(vcpu); |
2867 | } | |
6aa8b732 | 2868 | |
8018c27b IM |
2869 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
2870 | { | |
2871 | ASSERT(vcpu); | |
ad312c7c | 2872 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 2873 | |
8018c27b | 2874 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
2875 | } |
2876 | ||
2877 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) | |
2878 | { | |
2879 | ASSERT(vcpu); | |
2880 | ||
2881 | destroy_kvm_mmu(vcpu); | |
2882 | free_mmu_pages(vcpu); | |
714b93da | 2883 | mmu_free_memory_caches(vcpu); |
6aa8b732 AK |
2884 | } |
2885 | ||
90cb0529 | 2886 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 2887 | { |
4db35314 | 2888 | struct kvm_mmu_page *sp; |
6aa8b732 | 2889 | |
f05e70ac | 2890 | list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) { |
6aa8b732 AK |
2891 | int i; |
2892 | u64 *pt; | |
2893 | ||
291f26bc | 2894 | if (!test_bit(slot, sp->slot_bitmap)) |
6aa8b732 AK |
2895 | continue; |
2896 | ||
4db35314 | 2897 | pt = sp->spt; |
6aa8b732 AK |
2898 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2899 | /* avoid RMW */ | |
9647c14c | 2900 | if (pt[i] & PT_WRITABLE_MASK) |
6aa8b732 | 2901 | pt[i] &= ~PT_WRITABLE_MASK; |
6aa8b732 | 2902 | } |
171d595d | 2903 | kvm_flush_remote_tlbs(kvm); |
6aa8b732 | 2904 | } |
37a7d8b0 | 2905 | |
90cb0529 | 2906 | void kvm_mmu_zap_all(struct kvm *kvm) |
e0fa826f | 2907 | { |
4db35314 | 2908 | struct kvm_mmu_page *sp, *node; |
e0fa826f | 2909 | |
aaee2c94 | 2910 | spin_lock(&kvm->mmu_lock); |
f05e70ac | 2911 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) |
07385413 MT |
2912 | if (kvm_mmu_zap_page(kvm, sp)) |
2913 | node = container_of(kvm->arch.active_mmu_pages.next, | |
2914 | struct kvm_mmu_page, link); | |
aaee2c94 | 2915 | spin_unlock(&kvm->mmu_lock); |
e0fa826f | 2916 | |
90cb0529 | 2917 | kvm_flush_remote_tlbs(kvm); |
e0fa826f DL |
2918 | } |
2919 | ||
8b2cf73c | 2920 | static void kvm_mmu_remove_one_alloc_mmu_page(struct kvm *kvm) |
3ee16c81 IE |
2921 | { |
2922 | struct kvm_mmu_page *page; | |
2923 | ||
2924 | page = container_of(kvm->arch.active_mmu_pages.prev, | |
2925 | struct kvm_mmu_page, link); | |
2926 | kvm_mmu_zap_page(kvm, page); | |
2927 | } | |
2928 | ||
2929 | static int mmu_shrink(int nr_to_scan, gfp_t gfp_mask) | |
2930 | { | |
2931 | struct kvm *kvm; | |
2932 | struct kvm *kvm_freed = NULL; | |
2933 | int cache_count = 0; | |
2934 | ||
2935 | spin_lock(&kvm_lock); | |
2936 | ||
2937 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
f656ce01 | 2938 | int npages, idx; |
3ee16c81 | 2939 | |
f656ce01 | 2940 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 IE |
2941 | spin_lock(&kvm->mmu_lock); |
2942 | npages = kvm->arch.n_alloc_mmu_pages - | |
2943 | kvm->arch.n_free_mmu_pages; | |
2944 | cache_count += npages; | |
2945 | if (!kvm_freed && nr_to_scan > 0 && npages > 0) { | |
2946 | kvm_mmu_remove_one_alloc_mmu_page(kvm); | |
2947 | cache_count--; | |
2948 | kvm_freed = kvm; | |
2949 | } | |
2950 | nr_to_scan--; | |
2951 | ||
2952 | spin_unlock(&kvm->mmu_lock); | |
f656ce01 | 2953 | srcu_read_unlock(&kvm->srcu, idx); |
3ee16c81 IE |
2954 | } |
2955 | if (kvm_freed) | |
2956 | list_move_tail(&kvm_freed->vm_list, &vm_list); | |
2957 | ||
2958 | spin_unlock(&kvm_lock); | |
2959 | ||
2960 | return cache_count; | |
2961 | } | |
2962 | ||
2963 | static struct shrinker mmu_shrinker = { | |
2964 | .shrink = mmu_shrink, | |
2965 | .seeks = DEFAULT_SEEKS * 10, | |
2966 | }; | |
2967 | ||
2ddfd20e | 2968 | static void mmu_destroy_caches(void) |
b5a33a75 AK |
2969 | { |
2970 | if (pte_chain_cache) | |
2971 | kmem_cache_destroy(pte_chain_cache); | |
2972 | if (rmap_desc_cache) | |
2973 | kmem_cache_destroy(rmap_desc_cache); | |
d3d25b04 AK |
2974 | if (mmu_page_header_cache) |
2975 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
2976 | } |
2977 | ||
3ee16c81 IE |
2978 | void kvm_mmu_module_exit(void) |
2979 | { | |
2980 | mmu_destroy_caches(); | |
2981 | unregister_shrinker(&mmu_shrinker); | |
2982 | } | |
2983 | ||
b5a33a75 AK |
2984 | int kvm_mmu_module_init(void) |
2985 | { | |
2986 | pte_chain_cache = kmem_cache_create("kvm_pte_chain", | |
2987 | sizeof(struct kvm_pte_chain), | |
20c2df83 | 2988 | 0, 0, NULL); |
b5a33a75 AK |
2989 | if (!pte_chain_cache) |
2990 | goto nomem; | |
2991 | rmap_desc_cache = kmem_cache_create("kvm_rmap_desc", | |
2992 | sizeof(struct kvm_rmap_desc), | |
20c2df83 | 2993 | 0, 0, NULL); |
b5a33a75 AK |
2994 | if (!rmap_desc_cache) |
2995 | goto nomem; | |
2996 | ||
d3d25b04 AK |
2997 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
2998 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 2999 | 0, 0, NULL); |
d3d25b04 AK |
3000 | if (!mmu_page_header_cache) |
3001 | goto nomem; | |
3002 | ||
3ee16c81 IE |
3003 | register_shrinker(&mmu_shrinker); |
3004 | ||
b5a33a75 AK |
3005 | return 0; |
3006 | ||
3007 | nomem: | |
3ee16c81 | 3008 | mmu_destroy_caches(); |
b5a33a75 AK |
3009 | return -ENOMEM; |
3010 | } | |
3011 | ||
3ad82a7e ZX |
3012 | /* |
3013 | * Caculate mmu pages needed for kvm. | |
3014 | */ | |
3015 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
3016 | { | |
3017 | int i; | |
3018 | unsigned int nr_mmu_pages; | |
3019 | unsigned int nr_pages = 0; | |
bc6678a3 | 3020 | struct kvm_memslots *slots; |
3ad82a7e | 3021 | |
bc6678a3 MT |
3022 | slots = rcu_dereference(kvm->memslots); |
3023 | for (i = 0; i < slots->nmemslots; i++) | |
3024 | nr_pages += slots->memslots[i].npages; | |
3ad82a7e ZX |
3025 | |
3026 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
3027 | nr_mmu_pages = max(nr_mmu_pages, | |
3028 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
3029 | ||
3030 | return nr_mmu_pages; | |
3031 | } | |
3032 | ||
2f333bcb MT |
3033 | static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer, |
3034 | unsigned len) | |
3035 | { | |
3036 | if (len > buffer->len) | |
3037 | return NULL; | |
3038 | return buffer->ptr; | |
3039 | } | |
3040 | ||
3041 | static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer, | |
3042 | unsigned len) | |
3043 | { | |
3044 | void *ret; | |
3045 | ||
3046 | ret = pv_mmu_peek_buffer(buffer, len); | |
3047 | if (!ret) | |
3048 | return ret; | |
3049 | buffer->ptr += len; | |
3050 | buffer->len -= len; | |
3051 | buffer->processed += len; | |
3052 | return ret; | |
3053 | } | |
3054 | ||
3055 | static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu, | |
3056 | gpa_t addr, gpa_t value) | |
3057 | { | |
3058 | int bytes = 8; | |
3059 | int r; | |
3060 | ||
3061 | if (!is_long_mode(vcpu) && !is_pae(vcpu)) | |
3062 | bytes = 4; | |
3063 | ||
3064 | r = mmu_topup_memory_caches(vcpu); | |
3065 | if (r) | |
3066 | return r; | |
3067 | ||
3200f405 | 3068 | if (!emulator_write_phys(vcpu, addr, &value, bytes)) |
2f333bcb MT |
3069 | return -EFAULT; |
3070 | ||
3071 | return 1; | |
3072 | } | |
3073 | ||
3074 | static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu) | |
3075 | { | |
a8cd0244 | 3076 | kvm_set_cr3(vcpu, vcpu->arch.cr3); |
2f333bcb MT |
3077 | return 1; |
3078 | } | |
3079 | ||
3080 | static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr) | |
3081 | { | |
3082 | spin_lock(&vcpu->kvm->mmu_lock); | |
3083 | mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT); | |
3084 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3085 | return 1; | |
3086 | } | |
3087 | ||
3088 | static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu, | |
3089 | struct kvm_pv_mmu_op_buffer *buffer) | |
3090 | { | |
3091 | struct kvm_mmu_op_header *header; | |
3092 | ||
3093 | header = pv_mmu_peek_buffer(buffer, sizeof *header); | |
3094 | if (!header) | |
3095 | return 0; | |
3096 | switch (header->op) { | |
3097 | case KVM_MMU_OP_WRITE_PTE: { | |
3098 | struct kvm_mmu_op_write_pte *wpte; | |
3099 | ||
3100 | wpte = pv_mmu_read_buffer(buffer, sizeof *wpte); | |
3101 | if (!wpte) | |
3102 | return 0; | |
3103 | return kvm_pv_mmu_write(vcpu, wpte->pte_phys, | |
3104 | wpte->pte_val); | |
3105 | } | |
3106 | case KVM_MMU_OP_FLUSH_TLB: { | |
3107 | struct kvm_mmu_op_flush_tlb *ftlb; | |
3108 | ||
3109 | ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb); | |
3110 | if (!ftlb) | |
3111 | return 0; | |
3112 | return kvm_pv_mmu_flush_tlb(vcpu); | |
3113 | } | |
3114 | case KVM_MMU_OP_RELEASE_PT: { | |
3115 | struct kvm_mmu_op_release_pt *rpt; | |
3116 | ||
3117 | rpt = pv_mmu_read_buffer(buffer, sizeof *rpt); | |
3118 | if (!rpt) | |
3119 | return 0; | |
3120 | return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys); | |
3121 | } | |
3122 | default: return 0; | |
3123 | } | |
3124 | } | |
3125 | ||
3126 | int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes, | |
3127 | gpa_t addr, unsigned long *ret) | |
3128 | { | |
3129 | int r; | |
6ad18fba | 3130 | struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer; |
2f333bcb | 3131 | |
6ad18fba DH |
3132 | buffer->ptr = buffer->buf; |
3133 | buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf); | |
3134 | buffer->processed = 0; | |
2f333bcb | 3135 | |
6ad18fba | 3136 | r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len); |
2f333bcb MT |
3137 | if (r) |
3138 | goto out; | |
3139 | ||
6ad18fba DH |
3140 | while (buffer->len) { |
3141 | r = kvm_pv_mmu_op_one(vcpu, buffer); | |
2f333bcb MT |
3142 | if (r < 0) |
3143 | goto out; | |
3144 | if (r == 0) | |
3145 | break; | |
3146 | } | |
3147 | ||
3148 | r = 1; | |
3149 | out: | |
6ad18fba | 3150 | *ret = buffer->processed; |
2f333bcb MT |
3151 | return r; |
3152 | } | |
3153 | ||
94d8b056 MT |
3154 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
3155 | { | |
3156 | struct kvm_shadow_walk_iterator iterator; | |
3157 | int nr_sptes = 0; | |
3158 | ||
3159 | spin_lock(&vcpu->kvm->mmu_lock); | |
3160 | for_each_shadow_entry(vcpu, addr, iterator) { | |
3161 | sptes[iterator.level-1] = *iterator.sptep; | |
3162 | nr_sptes++; | |
3163 | if (!is_shadow_present_pte(*iterator.sptep)) | |
3164 | break; | |
3165 | } | |
3166 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3167 | ||
3168 | return nr_sptes; | |
3169 | } | |
3170 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
3171 | ||
37a7d8b0 AK |
3172 | #ifdef AUDIT |
3173 | ||
3174 | static const char *audit_msg; | |
3175 | ||
3176 | static gva_t canonicalize(gva_t gva) | |
3177 | { | |
3178 | #ifdef CONFIG_X86_64 | |
3179 | gva = (long long)(gva << 16) >> 16; | |
3180 | #endif | |
3181 | return gva; | |
3182 | } | |
3183 | ||
08a3732b MT |
3184 | |
3185 | typedef void (*inspect_spte_fn) (struct kvm *kvm, struct kvm_mmu_page *sp, | |
3186 | u64 *sptep); | |
3187 | ||
3188 | static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp, | |
3189 | inspect_spte_fn fn) | |
3190 | { | |
3191 | int i; | |
3192 | ||
3193 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
3194 | u64 ent = sp->spt[i]; | |
3195 | ||
3196 | if (is_shadow_present_pte(ent)) { | |
2920d728 | 3197 | if (!is_last_spte(ent, sp->role.level)) { |
08a3732b MT |
3198 | struct kvm_mmu_page *child; |
3199 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
3200 | __mmu_spte_walk(kvm, child, fn); | |
2920d728 | 3201 | } else |
08a3732b MT |
3202 | fn(kvm, sp, &sp->spt[i]); |
3203 | } | |
3204 | } | |
3205 | } | |
3206 | ||
3207 | static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn) | |
3208 | { | |
3209 | int i; | |
3210 | struct kvm_mmu_page *sp; | |
3211 | ||
3212 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
3213 | return; | |
3214 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3215 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
3216 | sp = page_header(root); | |
3217 | __mmu_spte_walk(vcpu->kvm, sp, fn); | |
3218 | return; | |
3219 | } | |
3220 | for (i = 0; i < 4; ++i) { | |
3221 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3222 | ||
3223 | if (root && VALID_PAGE(root)) { | |
3224 | root &= PT64_BASE_ADDR_MASK; | |
3225 | sp = page_header(root); | |
3226 | __mmu_spte_walk(vcpu->kvm, sp, fn); | |
3227 | } | |
3228 | } | |
3229 | return; | |
3230 | } | |
3231 | ||
37a7d8b0 AK |
3232 | static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte, |
3233 | gva_t va, int level) | |
3234 | { | |
3235 | u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK); | |
3236 | int i; | |
3237 | gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1)); | |
3238 | ||
3239 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) { | |
3240 | u64 ent = pt[i]; | |
3241 | ||
c7addb90 | 3242 | if (ent == shadow_trap_nonpresent_pte) |
37a7d8b0 AK |
3243 | continue; |
3244 | ||
3245 | va = canonicalize(va); | |
2920d728 MT |
3246 | if (is_shadow_present_pte(ent) && !is_last_spte(ent, level)) |
3247 | audit_mappings_page(vcpu, ent, va, level - 1); | |
3248 | else { | |
1871c602 | 3249 | gpa_t gpa = kvm_mmu_gva_to_gpa_read(vcpu, va, NULL); |
34382539 JK |
3250 | gfn_t gfn = gpa >> PAGE_SHIFT; |
3251 | pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn); | |
3252 | hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT; | |
37a7d8b0 | 3253 | |
2aaf65e8 MT |
3254 | if (is_error_pfn(pfn)) { |
3255 | kvm_release_pfn_clean(pfn); | |
3256 | continue; | |
3257 | } | |
3258 | ||
c7addb90 | 3259 | if (is_shadow_present_pte(ent) |
37a7d8b0 | 3260 | && (ent & PT64_BASE_ADDR_MASK) != hpa) |
c7addb90 AK |
3261 | printk(KERN_ERR "xx audit error: (%s) levels %d" |
3262 | " gva %lx gpa %llx hpa %llx ent %llx %d\n", | |
ad312c7c | 3263 | audit_msg, vcpu->arch.mmu.root_level, |
d77c26fc MD |
3264 | va, gpa, hpa, ent, |
3265 | is_shadow_present_pte(ent)); | |
c7addb90 AK |
3266 | else if (ent == shadow_notrap_nonpresent_pte |
3267 | && !is_error_hpa(hpa)) | |
3268 | printk(KERN_ERR "audit: (%s) notrap shadow," | |
3269 | " valid guest gva %lx\n", audit_msg, va); | |
35149e21 | 3270 | kvm_release_pfn_clean(pfn); |
c7addb90 | 3271 | |
37a7d8b0 AK |
3272 | } |
3273 | } | |
3274 | } | |
3275 | ||
3276 | static void audit_mappings(struct kvm_vcpu *vcpu) | |
3277 | { | |
1ea252af | 3278 | unsigned i; |
37a7d8b0 | 3279 | |
ad312c7c ZX |
3280 | if (vcpu->arch.mmu.root_level == 4) |
3281 | audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4); | |
37a7d8b0 AK |
3282 | else |
3283 | for (i = 0; i < 4; ++i) | |
ad312c7c | 3284 | if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK) |
37a7d8b0 | 3285 | audit_mappings_page(vcpu, |
ad312c7c | 3286 | vcpu->arch.mmu.pae_root[i], |
37a7d8b0 AK |
3287 | i << 30, |
3288 | 2); | |
3289 | } | |
3290 | ||
3291 | static int count_rmaps(struct kvm_vcpu *vcpu) | |
3292 | { | |
3293 | int nmaps = 0; | |
bc6678a3 | 3294 | int i, j, k, idx; |
37a7d8b0 | 3295 | |
bc6678a3 MT |
3296 | idx = srcu_read_lock(&kvm->srcu); |
3297 | slots = rcu_dereference(kvm->memslots); | |
37a7d8b0 | 3298 | for (i = 0; i < KVM_MEMORY_SLOTS; ++i) { |
bc6678a3 | 3299 | struct kvm_memory_slot *m = &slots->memslots[i]; |
37a7d8b0 AK |
3300 | struct kvm_rmap_desc *d; |
3301 | ||
3302 | for (j = 0; j < m->npages; ++j) { | |
290fc38d | 3303 | unsigned long *rmapp = &m->rmap[j]; |
37a7d8b0 | 3304 | |
290fc38d | 3305 | if (!*rmapp) |
37a7d8b0 | 3306 | continue; |
290fc38d | 3307 | if (!(*rmapp & 1)) { |
37a7d8b0 AK |
3308 | ++nmaps; |
3309 | continue; | |
3310 | } | |
290fc38d | 3311 | d = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
37a7d8b0 AK |
3312 | while (d) { |
3313 | for (k = 0; k < RMAP_EXT; ++k) | |
d555c333 | 3314 | if (d->sptes[k]) |
37a7d8b0 AK |
3315 | ++nmaps; |
3316 | else | |
3317 | break; | |
3318 | d = d->more; | |
3319 | } | |
3320 | } | |
3321 | } | |
bc6678a3 | 3322 | srcu_read_unlock(&kvm->srcu, idx); |
37a7d8b0 AK |
3323 | return nmaps; |
3324 | } | |
3325 | ||
08a3732b MT |
3326 | void inspect_spte_has_rmap(struct kvm *kvm, struct kvm_mmu_page *sp, u64 *sptep) |
3327 | { | |
3328 | unsigned long *rmapp; | |
3329 | struct kvm_mmu_page *rev_sp; | |
3330 | gfn_t gfn; | |
3331 | ||
3332 | if (*sptep & PT_WRITABLE_MASK) { | |
3333 | rev_sp = page_header(__pa(sptep)); | |
3334 | gfn = rev_sp->gfns[sptep - rev_sp->spt]; | |
3335 | ||
3336 | if (!gfn_to_memslot(kvm, gfn)) { | |
3337 | if (!printk_ratelimit()) | |
3338 | return; | |
3339 | printk(KERN_ERR "%s: no memslot for gfn %ld\n", | |
3340 | audit_msg, gfn); | |
3341 | printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n", | |
3342 | audit_msg, sptep - rev_sp->spt, | |
3343 | rev_sp->gfn); | |
3344 | dump_stack(); | |
3345 | return; | |
3346 | } | |
3347 | ||
2920d728 MT |
3348 | rmapp = gfn_to_rmap(kvm, rev_sp->gfns[sptep - rev_sp->spt], |
3349 | is_large_pte(*sptep)); | |
08a3732b MT |
3350 | if (!*rmapp) { |
3351 | if (!printk_ratelimit()) | |
3352 | return; | |
3353 | printk(KERN_ERR "%s: no rmap for writable spte %llx\n", | |
3354 | audit_msg, *sptep); | |
3355 | dump_stack(); | |
3356 | } | |
3357 | } | |
3358 | ||
3359 | } | |
3360 | ||
3361 | void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu) | |
3362 | { | |
3363 | mmu_spte_walk(vcpu, inspect_spte_has_rmap); | |
3364 | } | |
3365 | ||
3366 | static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu) | |
37a7d8b0 | 3367 | { |
4db35314 | 3368 | struct kvm_mmu_page *sp; |
37a7d8b0 AK |
3369 | int i; |
3370 | ||
f05e70ac | 3371 | list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) { |
4db35314 | 3372 | u64 *pt = sp->spt; |
37a7d8b0 | 3373 | |
4db35314 | 3374 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) |
37a7d8b0 AK |
3375 | continue; |
3376 | ||
3377 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
3378 | u64 ent = pt[i]; | |
3379 | ||
3380 | if (!(ent & PT_PRESENT_MASK)) | |
3381 | continue; | |
3382 | if (!(ent & PT_WRITABLE_MASK)) | |
3383 | continue; | |
08a3732b | 3384 | inspect_spte_has_rmap(vcpu->kvm, sp, &pt[i]); |
37a7d8b0 AK |
3385 | } |
3386 | } | |
08a3732b | 3387 | return; |
37a7d8b0 AK |
3388 | } |
3389 | ||
3390 | static void audit_rmap(struct kvm_vcpu *vcpu) | |
3391 | { | |
08a3732b MT |
3392 | check_writable_mappings_rmap(vcpu); |
3393 | count_rmaps(vcpu); | |
37a7d8b0 AK |
3394 | } |
3395 | ||
3396 | static void audit_write_protection(struct kvm_vcpu *vcpu) | |
3397 | { | |
4db35314 | 3398 | struct kvm_mmu_page *sp; |
290fc38d IE |
3399 | struct kvm_memory_slot *slot; |
3400 | unsigned long *rmapp; | |
e58b0f9e | 3401 | u64 *spte; |
290fc38d | 3402 | gfn_t gfn; |
37a7d8b0 | 3403 | |
f05e70ac | 3404 | list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) { |
f6e2c02b | 3405 | if (sp->role.direct) |
37a7d8b0 | 3406 | continue; |
e58b0f9e MT |
3407 | if (sp->unsync) |
3408 | continue; | |
37a7d8b0 | 3409 | |
4db35314 | 3410 | gfn = unalias_gfn(vcpu->kvm, sp->gfn); |
2843099f | 3411 | slot = gfn_to_memslot_unaliased(vcpu->kvm, sp->gfn); |
290fc38d | 3412 | rmapp = &slot->rmap[gfn - slot->base_gfn]; |
e58b0f9e MT |
3413 | |
3414 | spte = rmap_next(vcpu->kvm, rmapp, NULL); | |
3415 | while (spte) { | |
3416 | if (*spte & PT_WRITABLE_MASK) | |
3417 | printk(KERN_ERR "%s: (%s) shadow page has " | |
3418 | "writable mappings: gfn %lx role %x\n", | |
b8688d51 | 3419 | __func__, audit_msg, sp->gfn, |
4db35314 | 3420 | sp->role.word); |
e58b0f9e MT |
3421 | spte = rmap_next(vcpu->kvm, rmapp, spte); |
3422 | } | |
37a7d8b0 AK |
3423 | } |
3424 | } | |
3425 | ||
3426 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) | |
3427 | { | |
3428 | int olddbg = dbg; | |
3429 | ||
3430 | dbg = 0; | |
3431 | audit_msg = msg; | |
3432 | audit_rmap(vcpu); | |
3433 | audit_write_protection(vcpu); | |
2aaf65e8 MT |
3434 | if (strcmp("pre pte write", audit_msg) != 0) |
3435 | audit_mappings(vcpu); | |
08a3732b | 3436 | audit_writable_sptes_have_rmaps(vcpu); |
37a7d8b0 AK |
3437 | dbg = olddbg; |
3438 | } | |
3439 | ||
3440 | #endif |