Commit | Line | Data |
---|---|---|
6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
221d059d | 10 | * Copyright 2010 Red Hat, Inc. and/or its affilates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
1d737c8a | 21 | #include "mmu.h" |
836a1b3c | 22 | #include "x86.h" |
6de4f3ad | 23 | #include "kvm_cache_regs.h" |
e495606d | 24 | |
edf88417 | 25 | #include <linux/kvm_host.h> |
6aa8b732 AK |
26 | #include <linux/types.h> |
27 | #include <linux/string.h> | |
6aa8b732 AK |
28 | #include <linux/mm.h> |
29 | #include <linux/highmem.h> | |
30 | #include <linux/module.h> | |
448353ca | 31 | #include <linux/swap.h> |
05da4558 | 32 | #include <linux/hugetlb.h> |
2f333bcb | 33 | #include <linux/compiler.h> |
bc6678a3 | 34 | #include <linux/srcu.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
bf998156 | 36 | #include <linux/uaccess.h> |
6aa8b732 | 37 | |
e495606d AK |
38 | #include <asm/page.h> |
39 | #include <asm/cmpxchg.h> | |
4e542370 | 40 | #include <asm/io.h> |
13673a90 | 41 | #include <asm/vmx.h> |
6aa8b732 | 42 | |
18552672 JR |
43 | /* |
44 | * When setting this variable to true it enables Two-Dimensional-Paging | |
45 | * where the hardware walks 2 page tables: | |
46 | * 1. the guest-virtual to guest-physical | |
47 | * 2. while doing 1. it walks guest-physical to host-physical | |
48 | * If the hardware supports that we don't need to do shadow paging. | |
49 | */ | |
2f333bcb | 50 | bool tdp_enabled = false; |
18552672 | 51 | |
37a7d8b0 AK |
52 | #undef MMU_DEBUG |
53 | ||
54 | #undef AUDIT | |
55 | ||
56 | #ifdef AUDIT | |
57 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg); | |
58 | #else | |
59 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {} | |
60 | #endif | |
61 | ||
62 | #ifdef MMU_DEBUG | |
63 | ||
64 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
65 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
66 | ||
67 | #else | |
68 | ||
69 | #define pgprintk(x...) do { } while (0) | |
70 | #define rmap_printk(x...) do { } while (0) | |
71 | ||
72 | #endif | |
73 | ||
74 | #if defined(MMU_DEBUG) || defined(AUDIT) | |
6ada8cca AK |
75 | static int dbg = 0; |
76 | module_param(dbg, bool, 0644); | |
37a7d8b0 | 77 | #endif |
6aa8b732 | 78 | |
582801a9 MT |
79 | static int oos_shadow = 1; |
80 | module_param(oos_shadow, bool, 0644); | |
81 | ||
d6c69ee9 YD |
82 | #ifndef MMU_DEBUG |
83 | #define ASSERT(x) do { } while (0) | |
84 | #else | |
6aa8b732 AK |
85 | #define ASSERT(x) \ |
86 | if (!(x)) { \ | |
87 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
88 | __FILE__, __LINE__, #x); \ | |
89 | } | |
d6c69ee9 | 90 | #endif |
6aa8b732 | 91 | |
957ed9ef XG |
92 | #define PTE_PREFETCH_NUM 8 |
93 | ||
6aa8b732 AK |
94 | #define PT_FIRST_AVAIL_BITS_SHIFT 9 |
95 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 | |
96 | ||
6aa8b732 AK |
97 | #define PT64_LEVEL_BITS 9 |
98 | ||
99 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 100 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 AK |
101 | |
102 | #define PT64_LEVEL_MASK(level) \ | |
103 | (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level)) | |
104 | ||
105 | #define PT64_INDEX(address, level)\ | |
106 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
107 | ||
108 | ||
109 | #define PT32_LEVEL_BITS 10 | |
110 | ||
111 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 112 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 AK |
113 | |
114 | #define PT32_LEVEL_MASK(level) \ | |
115 | (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level)) | |
e04da980 JR |
116 | #define PT32_LVL_OFFSET_MASK(level) \ |
117 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
118 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
119 | |
120 | #define PT32_INDEX(address, level)\ | |
121 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
122 | ||
123 | ||
27aba766 | 124 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
125 | #define PT64_DIR_BASE_ADDR_MASK \ |
126 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
127 | #define PT64_LVL_ADDR_MASK(level) \ |
128 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
129 | * PT64_LEVEL_BITS))) - 1)) | |
130 | #define PT64_LVL_OFFSET_MASK(level) \ | |
131 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
132 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
133 | |
134 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
135 | #define PT32_DIR_BASE_ADDR_MASK \ | |
136 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
137 | #define PT32_LVL_ADDR_MASK(level) \ |
138 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
139 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 140 | |
79539cec AK |
141 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
142 | | PT64_NX_MASK) | |
6aa8b732 | 143 | |
cd4a4e53 AK |
144 | #define RMAP_EXT 4 |
145 | ||
fe135d2c AK |
146 | #define ACC_EXEC_MASK 1 |
147 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
148 | #define ACC_USER_MASK PT_USER_MASK | |
149 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
150 | ||
90bb6fc5 AK |
151 | #include <trace/events/kvm.h> |
152 | ||
07420171 AK |
153 | #define CREATE_TRACE_POINTS |
154 | #include "mmutrace.h" | |
155 | ||
1403283a IE |
156 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
157 | ||
135f8c2b AK |
158 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
159 | ||
cd4a4e53 | 160 | struct kvm_rmap_desc { |
d555c333 | 161 | u64 *sptes[RMAP_EXT]; |
cd4a4e53 AK |
162 | struct kvm_rmap_desc *more; |
163 | }; | |
164 | ||
2d11123a AK |
165 | struct kvm_shadow_walk_iterator { |
166 | u64 addr; | |
167 | hpa_t shadow_addr; | |
168 | int level; | |
169 | u64 *sptep; | |
170 | unsigned index; | |
171 | }; | |
172 | ||
173 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
174 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
175 | shadow_walk_okay(&(_walker)); \ | |
176 | shadow_walk_next(&(_walker))) | |
177 | ||
1047df1f | 178 | typedef void (*mmu_parent_walk_fn) (struct kvm_mmu_page *sp, u64 *spte); |
ad8cfbe3 | 179 | |
b5a33a75 AK |
180 | static struct kmem_cache *pte_chain_cache; |
181 | static struct kmem_cache *rmap_desc_cache; | |
d3d25b04 | 182 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 183 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 184 | |
c7addb90 AK |
185 | static u64 __read_mostly shadow_trap_nonpresent_pte; |
186 | static u64 __read_mostly shadow_notrap_nonpresent_pte; | |
7b52345e SY |
187 | static u64 __read_mostly shadow_base_present_pte; |
188 | static u64 __read_mostly shadow_nx_mask; | |
189 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
190 | static u64 __read_mostly shadow_user_mask; | |
191 | static u64 __read_mostly shadow_accessed_mask; | |
192 | static u64 __read_mostly shadow_dirty_mask; | |
c7addb90 | 193 | |
82725b20 DE |
194 | static inline u64 rsvd_bits(int s, int e) |
195 | { | |
196 | return ((1ULL << (e - s + 1)) - 1) << s; | |
197 | } | |
198 | ||
c7addb90 AK |
199 | void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte) |
200 | { | |
201 | shadow_trap_nonpresent_pte = trap_pte; | |
202 | shadow_notrap_nonpresent_pte = notrap_pte; | |
203 | } | |
204 | EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes); | |
205 | ||
7b52345e SY |
206 | void kvm_mmu_set_base_ptes(u64 base_pte) |
207 | { | |
208 | shadow_base_present_pte = base_pte; | |
209 | } | |
210 | EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes); | |
211 | ||
212 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, | |
4b12f0de | 213 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
214 | { |
215 | shadow_user_mask = user_mask; | |
216 | shadow_accessed_mask = accessed_mask; | |
217 | shadow_dirty_mask = dirty_mask; | |
218 | shadow_nx_mask = nx_mask; | |
219 | shadow_x_mask = x_mask; | |
220 | } | |
221 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
222 | ||
3dbe1415 | 223 | static bool is_write_protection(struct kvm_vcpu *vcpu) |
6aa8b732 | 224 | { |
4d4ec087 | 225 | return kvm_read_cr0_bits(vcpu, X86_CR0_WP); |
6aa8b732 AK |
226 | } |
227 | ||
228 | static int is_cpuid_PSE36(void) | |
229 | { | |
230 | return 1; | |
231 | } | |
232 | ||
73b1087e AK |
233 | static int is_nx(struct kvm_vcpu *vcpu) |
234 | { | |
f6801dff | 235 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
236 | } |
237 | ||
c7addb90 AK |
238 | static int is_shadow_present_pte(u64 pte) |
239 | { | |
c7addb90 AK |
240 | return pte != shadow_trap_nonpresent_pte |
241 | && pte != shadow_notrap_nonpresent_pte; | |
242 | } | |
243 | ||
05da4558 MT |
244 | static int is_large_pte(u64 pte) |
245 | { | |
246 | return pte & PT_PAGE_SIZE_MASK; | |
247 | } | |
248 | ||
8dae4445 | 249 | static int is_writable_pte(unsigned long pte) |
6aa8b732 AK |
250 | { |
251 | return pte & PT_WRITABLE_MASK; | |
252 | } | |
253 | ||
43a3795a | 254 | static int is_dirty_gpte(unsigned long pte) |
e3c5e7ec | 255 | { |
439e218a | 256 | return pte & PT_DIRTY_MASK; |
e3c5e7ec AK |
257 | } |
258 | ||
43a3795a | 259 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 260 | { |
4b1a80fa | 261 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
262 | } |
263 | ||
776e6633 MT |
264 | static int is_last_spte(u64 pte, int level) |
265 | { | |
266 | if (level == PT_PAGE_TABLE_LEVEL) | |
267 | return 1; | |
852e3c19 | 268 | if (is_large_pte(pte)) |
776e6633 MT |
269 | return 1; |
270 | return 0; | |
271 | } | |
272 | ||
35149e21 | 273 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 274 | { |
35149e21 | 275 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
276 | } |
277 | ||
da928521 AK |
278 | static gfn_t pse36_gfn_delta(u32 gpte) |
279 | { | |
280 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
281 | ||
282 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
283 | } | |
284 | ||
d555c333 | 285 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 286 | { |
7645e432 | 287 | set_64bit(sptep, spte); |
e663ee64 AK |
288 | } |
289 | ||
a9221dd5 AK |
290 | static u64 __xchg_spte(u64 *sptep, u64 new_spte) |
291 | { | |
292 | #ifdef CONFIG_X86_64 | |
293 | return xchg(sptep, new_spte); | |
294 | #else | |
295 | u64 old_spte; | |
296 | ||
297 | do { | |
298 | old_spte = *sptep; | |
299 | } while (cmpxchg64(sptep, old_spte, new_spte) != old_spte); | |
300 | ||
301 | return old_spte; | |
302 | #endif | |
303 | } | |
304 | ||
8672b721 XG |
305 | static bool spte_has_volatile_bits(u64 spte) |
306 | { | |
307 | if (!shadow_accessed_mask) | |
308 | return false; | |
309 | ||
310 | if (!is_shadow_present_pte(spte)) | |
311 | return false; | |
312 | ||
4132779b XG |
313 | if ((spte & shadow_accessed_mask) && |
314 | (!is_writable_pte(spte) || (spte & shadow_dirty_mask))) | |
8672b721 XG |
315 | return false; |
316 | ||
317 | return true; | |
318 | } | |
319 | ||
4132779b XG |
320 | static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask) |
321 | { | |
322 | return (old_spte & bit_mask) && !(new_spte & bit_mask); | |
323 | } | |
324 | ||
b79b93f9 AK |
325 | static void update_spte(u64 *sptep, u64 new_spte) |
326 | { | |
4132779b XG |
327 | u64 mask, old_spte = *sptep; |
328 | ||
329 | WARN_ON(!is_rmap_spte(new_spte)); | |
b79b93f9 | 330 | |
4132779b XG |
331 | new_spte |= old_spte & shadow_dirty_mask; |
332 | ||
333 | mask = shadow_accessed_mask; | |
334 | if (is_writable_pte(old_spte)) | |
335 | mask |= shadow_dirty_mask; | |
336 | ||
337 | if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask) | |
b79b93f9 | 338 | __set_spte(sptep, new_spte); |
4132779b | 339 | else |
b79b93f9 | 340 | old_spte = __xchg_spte(sptep, new_spte); |
4132779b XG |
341 | |
342 | if (!shadow_accessed_mask) | |
343 | return; | |
344 | ||
345 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask)) | |
346 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); | |
347 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask)) | |
348 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); | |
b79b93f9 AK |
349 | } |
350 | ||
e2dec939 | 351 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 352 | struct kmem_cache *base_cache, int min) |
714b93da AK |
353 | { |
354 | void *obj; | |
355 | ||
356 | if (cache->nobjs >= min) | |
e2dec939 | 357 | return 0; |
714b93da | 358 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 359 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 360 | if (!obj) |
e2dec939 | 361 | return -ENOMEM; |
714b93da AK |
362 | cache->objects[cache->nobjs++] = obj; |
363 | } | |
e2dec939 | 364 | return 0; |
714b93da AK |
365 | } |
366 | ||
e8ad9a70 XG |
367 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
368 | struct kmem_cache *cache) | |
714b93da AK |
369 | { |
370 | while (mc->nobjs) | |
e8ad9a70 | 371 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
372 | } |
373 | ||
c1158e63 | 374 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 375 | int min) |
c1158e63 AK |
376 | { |
377 | struct page *page; | |
378 | ||
379 | if (cache->nobjs >= min) | |
380 | return 0; | |
381 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
2e3e5882 | 382 | page = alloc_page(GFP_KERNEL); |
c1158e63 AK |
383 | if (!page) |
384 | return -ENOMEM; | |
c1158e63 AK |
385 | cache->objects[cache->nobjs++] = page_address(page); |
386 | } | |
387 | return 0; | |
388 | } | |
389 | ||
390 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
391 | { | |
392 | while (mc->nobjs) | |
c4d198d5 | 393 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
394 | } |
395 | ||
2e3e5882 | 396 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 397 | { |
e2dec939 AK |
398 | int r; |
399 | ||
ad312c7c | 400 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache, |
2e3e5882 | 401 | pte_chain_cache, 4); |
e2dec939 AK |
402 | if (r) |
403 | goto out; | |
ad312c7c | 404 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, |
957ed9ef | 405 | rmap_desc_cache, 4 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
406 | if (r) |
407 | goto out; | |
ad312c7c | 408 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
409 | if (r) |
410 | goto out; | |
ad312c7c | 411 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 412 | mmu_page_header_cache, 4); |
e2dec939 AK |
413 | out: |
414 | return r; | |
714b93da AK |
415 | } |
416 | ||
417 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
418 | { | |
e8ad9a70 XG |
419 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache, pte_chain_cache); |
420 | mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, rmap_desc_cache); | |
ad312c7c | 421 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
422 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
423 | mmu_page_header_cache); | |
714b93da AK |
424 | } |
425 | ||
426 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc, | |
427 | size_t size) | |
428 | { | |
429 | void *p; | |
430 | ||
431 | BUG_ON(!mc->nobjs); | |
432 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
433 | return p; |
434 | } | |
435 | ||
714b93da AK |
436 | static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu) |
437 | { | |
ad312c7c | 438 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache, |
714b93da AK |
439 | sizeof(struct kvm_pte_chain)); |
440 | } | |
441 | ||
90cb0529 | 442 | static void mmu_free_pte_chain(struct kvm_pte_chain *pc) |
714b93da | 443 | { |
e8ad9a70 | 444 | kmem_cache_free(pte_chain_cache, pc); |
714b93da AK |
445 | } |
446 | ||
447 | static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu) | |
448 | { | |
ad312c7c | 449 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache, |
714b93da AK |
450 | sizeof(struct kvm_rmap_desc)); |
451 | } | |
452 | ||
90cb0529 | 453 | static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd) |
714b93da | 454 | { |
e8ad9a70 | 455 | kmem_cache_free(rmap_desc_cache, rd); |
714b93da AK |
456 | } |
457 | ||
2032a93d LJ |
458 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
459 | { | |
460 | if (!sp->role.direct) | |
461 | return sp->gfns[index]; | |
462 | ||
463 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
464 | } | |
465 | ||
466 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
467 | { | |
468 | if (sp->role.direct) | |
469 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
470 | else | |
471 | sp->gfns[index] = gfn; | |
472 | } | |
473 | ||
05da4558 MT |
474 | /* |
475 | * Return the pointer to the largepage write count for a given | |
476 | * gfn, handling slots that are not large page aligned. | |
477 | */ | |
d25797b2 JR |
478 | static int *slot_largepage_idx(gfn_t gfn, |
479 | struct kvm_memory_slot *slot, | |
480 | int level) | |
05da4558 MT |
481 | { |
482 | unsigned long idx; | |
483 | ||
82855413 JR |
484 | idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - |
485 | (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
d25797b2 | 486 | return &slot->lpage_info[level - 2][idx].write_count; |
05da4558 MT |
487 | } |
488 | ||
489 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
490 | { | |
d25797b2 | 491 | struct kvm_memory_slot *slot; |
05da4558 | 492 | int *write_count; |
d25797b2 | 493 | int i; |
05da4558 | 494 | |
a1f4d395 | 495 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
496 | for (i = PT_DIRECTORY_LEVEL; |
497 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
498 | write_count = slot_largepage_idx(gfn, slot, i); | |
499 | *write_count += 1; | |
500 | } | |
05da4558 MT |
501 | } |
502 | ||
503 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
504 | { | |
d25797b2 | 505 | struct kvm_memory_slot *slot; |
05da4558 | 506 | int *write_count; |
d25797b2 | 507 | int i; |
05da4558 | 508 | |
a1f4d395 | 509 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
510 | for (i = PT_DIRECTORY_LEVEL; |
511 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d25797b2 JR |
512 | write_count = slot_largepage_idx(gfn, slot, i); |
513 | *write_count -= 1; | |
514 | WARN_ON(*write_count < 0); | |
515 | } | |
05da4558 MT |
516 | } |
517 | ||
d25797b2 JR |
518 | static int has_wrprotected_page(struct kvm *kvm, |
519 | gfn_t gfn, | |
520 | int level) | |
05da4558 | 521 | { |
2843099f | 522 | struct kvm_memory_slot *slot; |
05da4558 MT |
523 | int *largepage_idx; |
524 | ||
a1f4d395 | 525 | slot = gfn_to_memslot(kvm, gfn); |
05da4558 | 526 | if (slot) { |
d25797b2 | 527 | largepage_idx = slot_largepage_idx(gfn, slot, level); |
05da4558 MT |
528 | return *largepage_idx; |
529 | } | |
530 | ||
531 | return 1; | |
532 | } | |
533 | ||
d25797b2 | 534 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 535 | { |
8f0b1ab6 | 536 | unsigned long page_size; |
d25797b2 | 537 | int i, ret = 0; |
05da4558 | 538 | |
8f0b1ab6 | 539 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 540 | |
d25797b2 JR |
541 | for (i = PT_PAGE_TABLE_LEVEL; |
542 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
543 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
544 | ret = i; | |
545 | else | |
546 | break; | |
547 | } | |
548 | ||
4c2155ce | 549 | return ret; |
05da4558 MT |
550 | } |
551 | ||
d25797b2 | 552 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) |
05da4558 MT |
553 | { |
554 | struct kvm_memory_slot *slot; | |
878403b7 | 555 | int host_level, level, max_level; |
05da4558 MT |
556 | |
557 | slot = gfn_to_memslot(vcpu->kvm, large_gfn); | |
558 | if (slot && slot->dirty_bitmap) | |
d25797b2 | 559 | return PT_PAGE_TABLE_LEVEL; |
05da4558 | 560 | |
d25797b2 JR |
561 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
562 | ||
563 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
564 | return host_level; | |
565 | ||
878403b7 SY |
566 | max_level = kvm_x86_ops->get_lpage_level() < host_level ? |
567 | kvm_x86_ops->get_lpage_level() : host_level; | |
568 | ||
569 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
570 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
571 | break; | |
d25797b2 JR |
572 | |
573 | return level - 1; | |
05da4558 MT |
574 | } |
575 | ||
290fc38d IE |
576 | /* |
577 | * Take gfn and return the reverse mapping to it. | |
290fc38d IE |
578 | */ |
579 | ||
44ad9944 | 580 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) |
290fc38d IE |
581 | { |
582 | struct kvm_memory_slot *slot; | |
05da4558 | 583 | unsigned long idx; |
290fc38d IE |
584 | |
585 | slot = gfn_to_memslot(kvm, gfn); | |
44ad9944 | 586 | if (likely(level == PT_PAGE_TABLE_LEVEL)) |
05da4558 MT |
587 | return &slot->rmap[gfn - slot->base_gfn]; |
588 | ||
82855413 JR |
589 | idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - |
590 | (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
05da4558 | 591 | |
44ad9944 | 592 | return &slot->lpage_info[level - 2][idx].rmap_pde; |
290fc38d IE |
593 | } |
594 | ||
cd4a4e53 AK |
595 | /* |
596 | * Reverse mapping data structures: | |
597 | * | |
290fc38d IE |
598 | * If rmapp bit zero is zero, then rmapp point to the shadw page table entry |
599 | * that points to page_address(page). | |
cd4a4e53 | 600 | * |
290fc38d IE |
601 | * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc |
602 | * containing more mappings. | |
53a27b39 MT |
603 | * |
604 | * Returns the number of rmap entries before the spte was added or zero if | |
605 | * the spte was not added. | |
606 | * | |
cd4a4e53 | 607 | */ |
44ad9944 | 608 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
cd4a4e53 | 609 | { |
4db35314 | 610 | struct kvm_mmu_page *sp; |
cd4a4e53 | 611 | struct kvm_rmap_desc *desc; |
290fc38d | 612 | unsigned long *rmapp; |
53a27b39 | 613 | int i, count = 0; |
cd4a4e53 | 614 | |
43a3795a | 615 | if (!is_rmap_spte(*spte)) |
53a27b39 | 616 | return count; |
4db35314 | 617 | sp = page_header(__pa(spte)); |
2032a93d | 618 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); |
44ad9944 | 619 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
290fc38d | 620 | if (!*rmapp) { |
cd4a4e53 | 621 | rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte); |
290fc38d IE |
622 | *rmapp = (unsigned long)spte; |
623 | } else if (!(*rmapp & 1)) { | |
cd4a4e53 | 624 | rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte); |
714b93da | 625 | desc = mmu_alloc_rmap_desc(vcpu); |
d555c333 AK |
626 | desc->sptes[0] = (u64 *)*rmapp; |
627 | desc->sptes[1] = spte; | |
290fc38d | 628 | *rmapp = (unsigned long)desc | 1; |
cd4a4e53 AK |
629 | } else { |
630 | rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte); | |
290fc38d | 631 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
d555c333 | 632 | while (desc->sptes[RMAP_EXT-1] && desc->more) { |
cd4a4e53 | 633 | desc = desc->more; |
53a27b39 MT |
634 | count += RMAP_EXT; |
635 | } | |
d555c333 | 636 | if (desc->sptes[RMAP_EXT-1]) { |
714b93da | 637 | desc->more = mmu_alloc_rmap_desc(vcpu); |
cd4a4e53 AK |
638 | desc = desc->more; |
639 | } | |
d555c333 | 640 | for (i = 0; desc->sptes[i]; ++i) |
cd4a4e53 | 641 | ; |
d555c333 | 642 | desc->sptes[i] = spte; |
cd4a4e53 | 643 | } |
53a27b39 | 644 | return count; |
cd4a4e53 AK |
645 | } |
646 | ||
290fc38d | 647 | static void rmap_desc_remove_entry(unsigned long *rmapp, |
cd4a4e53 AK |
648 | struct kvm_rmap_desc *desc, |
649 | int i, | |
650 | struct kvm_rmap_desc *prev_desc) | |
651 | { | |
652 | int j; | |
653 | ||
d555c333 | 654 | for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 655 | ; |
d555c333 AK |
656 | desc->sptes[i] = desc->sptes[j]; |
657 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
658 | if (j != 0) |
659 | return; | |
660 | if (!prev_desc && !desc->more) | |
d555c333 | 661 | *rmapp = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
662 | else |
663 | if (prev_desc) | |
664 | prev_desc->more = desc->more; | |
665 | else | |
290fc38d | 666 | *rmapp = (unsigned long)desc->more | 1; |
90cb0529 | 667 | mmu_free_rmap_desc(desc); |
cd4a4e53 AK |
668 | } |
669 | ||
290fc38d | 670 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
cd4a4e53 | 671 | { |
cd4a4e53 AK |
672 | struct kvm_rmap_desc *desc; |
673 | struct kvm_rmap_desc *prev_desc; | |
4db35314 | 674 | struct kvm_mmu_page *sp; |
2032a93d | 675 | gfn_t gfn; |
290fc38d | 676 | unsigned long *rmapp; |
cd4a4e53 AK |
677 | int i; |
678 | ||
4db35314 | 679 | sp = page_header(__pa(spte)); |
2032a93d LJ |
680 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); |
681 | rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); | |
290fc38d | 682 | if (!*rmapp) { |
19ada5c4 | 683 | printk(KERN_ERR "rmap_remove: %p 0->BUG\n", spte); |
cd4a4e53 | 684 | BUG(); |
290fc38d | 685 | } else if (!(*rmapp & 1)) { |
19ada5c4 | 686 | rmap_printk("rmap_remove: %p 1->0\n", spte); |
290fc38d | 687 | if ((u64 *)*rmapp != spte) { |
19ada5c4 | 688 | printk(KERN_ERR "rmap_remove: %p 1->BUG\n", spte); |
cd4a4e53 AK |
689 | BUG(); |
690 | } | |
290fc38d | 691 | *rmapp = 0; |
cd4a4e53 | 692 | } else { |
19ada5c4 | 693 | rmap_printk("rmap_remove: %p many->many\n", spte); |
290fc38d | 694 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
cd4a4e53 AK |
695 | prev_desc = NULL; |
696 | while (desc) { | |
d555c333 AK |
697 | for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) |
698 | if (desc->sptes[i] == spte) { | |
290fc38d | 699 | rmap_desc_remove_entry(rmapp, |
714b93da | 700 | desc, i, |
cd4a4e53 AK |
701 | prev_desc); |
702 | return; | |
703 | } | |
704 | prev_desc = desc; | |
705 | desc = desc->more; | |
706 | } | |
19ada5c4 | 707 | pr_err("rmap_remove: %p many->many\n", spte); |
cd4a4e53 AK |
708 | BUG(); |
709 | } | |
710 | } | |
711 | ||
e4b502ea | 712 | static void set_spte_track_bits(u64 *sptep, u64 new_spte) |
be38d276 | 713 | { |
ce061867 | 714 | pfn_t pfn; |
9a3aad70 XG |
715 | u64 old_spte = *sptep; |
716 | ||
8672b721 | 717 | if (!spte_has_volatile_bits(old_spte)) |
9a3aad70 | 718 | __set_spte(sptep, new_spte); |
8672b721 | 719 | else |
9a3aad70 | 720 | old_spte = __xchg_spte(sptep, new_spte); |
ce061867 | 721 | |
a9221dd5 | 722 | if (!is_rmap_spte(old_spte)) |
ce061867 | 723 | return; |
8672b721 | 724 | |
a9221dd5 | 725 | pfn = spte_to_pfn(old_spte); |
daa3db69 | 726 | if (!shadow_accessed_mask || old_spte & shadow_accessed_mask) |
ce061867 | 727 | kvm_set_pfn_accessed(pfn); |
4132779b | 728 | if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask)) |
ce061867 | 729 | kvm_set_pfn_dirty(pfn); |
e4b502ea XG |
730 | } |
731 | ||
732 | static void drop_spte(struct kvm *kvm, u64 *sptep, u64 new_spte) | |
733 | { | |
734 | set_spte_track_bits(sptep, new_spte); | |
be38d276 | 735 | rmap_remove(kvm, sptep); |
be38d276 AK |
736 | } |
737 | ||
98348e95 | 738 | static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte) |
374cbac0 | 739 | { |
374cbac0 | 740 | struct kvm_rmap_desc *desc; |
98348e95 IE |
741 | u64 *prev_spte; |
742 | int i; | |
743 | ||
744 | if (!*rmapp) | |
745 | return NULL; | |
746 | else if (!(*rmapp & 1)) { | |
747 | if (!spte) | |
748 | return (u64 *)*rmapp; | |
749 | return NULL; | |
750 | } | |
751 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); | |
98348e95 IE |
752 | prev_spte = NULL; |
753 | while (desc) { | |
d555c333 | 754 | for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) { |
98348e95 | 755 | if (prev_spte == spte) |
d555c333 AK |
756 | return desc->sptes[i]; |
757 | prev_spte = desc->sptes[i]; | |
98348e95 IE |
758 | } |
759 | desc = desc->more; | |
760 | } | |
761 | return NULL; | |
762 | } | |
763 | ||
b1a36821 | 764 | static int rmap_write_protect(struct kvm *kvm, u64 gfn) |
98348e95 | 765 | { |
290fc38d | 766 | unsigned long *rmapp; |
374cbac0 | 767 | u64 *spte; |
44ad9944 | 768 | int i, write_protected = 0; |
374cbac0 | 769 | |
44ad9944 | 770 | rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL); |
374cbac0 | 771 | |
98348e95 IE |
772 | spte = rmap_next(kvm, rmapp, NULL); |
773 | while (spte) { | |
374cbac0 | 774 | BUG_ON(!spte); |
374cbac0 | 775 | BUG_ON(!(*spte & PT_PRESENT_MASK)); |
374cbac0 | 776 | rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte); |
8dae4445 | 777 | if (is_writable_pte(*spte)) { |
b79b93f9 | 778 | update_spte(spte, *spte & ~PT_WRITABLE_MASK); |
caa5b8a5 ED |
779 | write_protected = 1; |
780 | } | |
9647c14c | 781 | spte = rmap_next(kvm, rmapp, spte); |
374cbac0 | 782 | } |
855149aa | 783 | |
05da4558 | 784 | /* check for huge page mappings */ |
44ad9944 JR |
785 | for (i = PT_DIRECTORY_LEVEL; |
786 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
787 | rmapp = gfn_to_rmap(kvm, gfn, i); | |
788 | spte = rmap_next(kvm, rmapp, NULL); | |
789 | while (spte) { | |
790 | BUG_ON(!spte); | |
791 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
792 | BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)); | |
793 | pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn); | |
8dae4445 | 794 | if (is_writable_pte(*spte)) { |
be38d276 AK |
795 | drop_spte(kvm, spte, |
796 | shadow_trap_nonpresent_pte); | |
44ad9944 | 797 | --kvm->stat.lpages; |
44ad9944 JR |
798 | spte = NULL; |
799 | write_protected = 1; | |
800 | } | |
801 | spte = rmap_next(kvm, rmapp, spte); | |
05da4558 | 802 | } |
05da4558 MT |
803 | } |
804 | ||
b1a36821 | 805 | return write_protected; |
374cbac0 AK |
806 | } |
807 | ||
8a8365c5 FD |
808 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
809 | unsigned long data) | |
e930bffe AA |
810 | { |
811 | u64 *spte; | |
812 | int need_tlb_flush = 0; | |
813 | ||
814 | while ((spte = rmap_next(kvm, rmapp, NULL))) { | |
815 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
816 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte); | |
be38d276 | 817 | drop_spte(kvm, spte, shadow_trap_nonpresent_pte); |
e930bffe AA |
818 | need_tlb_flush = 1; |
819 | } | |
820 | return need_tlb_flush; | |
821 | } | |
822 | ||
8a8365c5 FD |
823 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
824 | unsigned long data) | |
3da0dd43 IE |
825 | { |
826 | int need_flush = 0; | |
e4b502ea | 827 | u64 *spte, new_spte; |
3da0dd43 IE |
828 | pte_t *ptep = (pte_t *)data; |
829 | pfn_t new_pfn; | |
830 | ||
831 | WARN_ON(pte_huge(*ptep)); | |
832 | new_pfn = pte_pfn(*ptep); | |
833 | spte = rmap_next(kvm, rmapp, NULL); | |
834 | while (spte) { | |
835 | BUG_ON(!is_shadow_present_pte(*spte)); | |
836 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte); | |
837 | need_flush = 1; | |
838 | if (pte_write(*ptep)) { | |
be38d276 | 839 | drop_spte(kvm, spte, shadow_trap_nonpresent_pte); |
3da0dd43 IE |
840 | spte = rmap_next(kvm, rmapp, NULL); |
841 | } else { | |
842 | new_spte = *spte &~ (PT64_BASE_ADDR_MASK); | |
843 | new_spte |= (u64)new_pfn << PAGE_SHIFT; | |
844 | ||
845 | new_spte &= ~PT_WRITABLE_MASK; | |
846 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 847 | new_spte &= ~shadow_accessed_mask; |
e4b502ea | 848 | set_spte_track_bits(spte, new_spte); |
3da0dd43 IE |
849 | spte = rmap_next(kvm, rmapp, spte); |
850 | } | |
851 | } | |
852 | if (need_flush) | |
853 | kvm_flush_remote_tlbs(kvm); | |
854 | ||
855 | return 0; | |
856 | } | |
857 | ||
8a8365c5 FD |
858 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
859 | unsigned long data, | |
3da0dd43 | 860 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, |
8a8365c5 | 861 | unsigned long data)) |
e930bffe | 862 | { |
852e3c19 | 863 | int i, j; |
90bb6fc5 | 864 | int ret; |
e930bffe | 865 | int retval = 0; |
bc6678a3 MT |
866 | struct kvm_memslots *slots; |
867 | ||
90d83dc3 | 868 | slots = kvm_memslots(kvm); |
e930bffe | 869 | |
46a26bf5 MT |
870 | for (i = 0; i < slots->nmemslots; i++) { |
871 | struct kvm_memory_slot *memslot = &slots->memslots[i]; | |
e930bffe AA |
872 | unsigned long start = memslot->userspace_addr; |
873 | unsigned long end; | |
874 | ||
e930bffe AA |
875 | end = start + (memslot->npages << PAGE_SHIFT); |
876 | if (hva >= start && hva < end) { | |
877 | gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT; | |
852e3c19 | 878 | |
90bb6fc5 | 879 | ret = handler(kvm, &memslot->rmap[gfn_offset], data); |
852e3c19 JR |
880 | |
881 | for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) { | |
6e3e243c AA |
882 | unsigned long idx; |
883 | int sh; | |
884 | ||
885 | sh = KVM_HPAGE_GFN_SHIFT(PT_DIRECTORY_LEVEL+j); | |
886 | idx = ((memslot->base_gfn+gfn_offset) >> sh) - | |
887 | (memslot->base_gfn >> sh); | |
90bb6fc5 | 888 | ret |= handler(kvm, |
3da0dd43 IE |
889 | &memslot->lpage_info[j][idx].rmap_pde, |
890 | data); | |
852e3c19 | 891 | } |
90bb6fc5 AK |
892 | trace_kvm_age_page(hva, memslot, ret); |
893 | retval |= ret; | |
e930bffe AA |
894 | } |
895 | } | |
896 | ||
897 | return retval; | |
898 | } | |
899 | ||
900 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
901 | { | |
3da0dd43 IE |
902 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
903 | } | |
904 | ||
905 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) | |
906 | { | |
8a8365c5 | 907 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
908 | } |
909 | ||
8a8365c5 FD |
910 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
911 | unsigned long data) | |
e930bffe AA |
912 | { |
913 | u64 *spte; | |
914 | int young = 0; | |
915 | ||
6316e1c8 RR |
916 | /* |
917 | * Emulate the accessed bit for EPT, by checking if this page has | |
918 | * an EPT mapping, and clearing it if it does. On the next access, | |
919 | * a new EPT mapping will be established. | |
920 | * This has some overhead, but not as much as the cost of swapping | |
921 | * out actively used pages or breaking up actively used hugepages. | |
922 | */ | |
534e38b4 | 923 | if (!shadow_accessed_mask) |
6316e1c8 | 924 | return kvm_unmap_rmapp(kvm, rmapp, data); |
534e38b4 | 925 | |
e930bffe AA |
926 | spte = rmap_next(kvm, rmapp, NULL); |
927 | while (spte) { | |
928 | int _young; | |
929 | u64 _spte = *spte; | |
930 | BUG_ON(!(_spte & PT_PRESENT_MASK)); | |
931 | _young = _spte & PT_ACCESSED_MASK; | |
932 | if (_young) { | |
933 | young = 1; | |
934 | clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
935 | } | |
936 | spte = rmap_next(kvm, rmapp, spte); | |
937 | } | |
938 | return young; | |
939 | } | |
940 | ||
53a27b39 MT |
941 | #define RMAP_RECYCLE_THRESHOLD 1000 |
942 | ||
852e3c19 | 943 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
944 | { |
945 | unsigned long *rmapp; | |
852e3c19 JR |
946 | struct kvm_mmu_page *sp; |
947 | ||
948 | sp = page_header(__pa(spte)); | |
53a27b39 | 949 | |
852e3c19 | 950 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 951 | |
3da0dd43 | 952 | kvm_unmap_rmapp(vcpu->kvm, rmapp, 0); |
53a27b39 MT |
953 | kvm_flush_remote_tlbs(vcpu->kvm); |
954 | } | |
955 | ||
e930bffe AA |
956 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
957 | { | |
3da0dd43 | 958 | return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp); |
e930bffe AA |
959 | } |
960 | ||
d6c69ee9 | 961 | #ifdef MMU_DEBUG |
47ad8e68 | 962 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 963 | { |
139bdb2d AK |
964 | u64 *pos; |
965 | u64 *end; | |
966 | ||
47ad8e68 | 967 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 968 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 969 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 970 | pos, *pos); |
6aa8b732 | 971 | return 0; |
139bdb2d | 972 | } |
6aa8b732 AK |
973 | return 1; |
974 | } | |
d6c69ee9 | 975 | #endif |
6aa8b732 | 976 | |
45221ab6 DH |
977 | /* |
978 | * This value is the sum of all of the kvm instances's | |
979 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
980 | * aggregate version in order to make the slab shrinker | |
981 | * faster | |
982 | */ | |
983 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
984 | { | |
985 | kvm->arch.n_used_mmu_pages += nr; | |
986 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
987 | } | |
988 | ||
4db35314 | 989 | static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
260746c0 | 990 | { |
4db35314 | 991 | ASSERT(is_empty_shadow_page(sp->spt)); |
7775834a | 992 | hlist_del(&sp->hash_link); |
4db35314 AK |
993 | list_del(&sp->link); |
994 | __free_page(virt_to_page(sp->spt)); | |
2032a93d LJ |
995 | if (!sp->role.direct) |
996 | __free_page(virt_to_page(sp->gfns)); | |
e8ad9a70 | 997 | kmem_cache_free(mmu_page_header_cache, sp); |
45221ab6 | 998 | kvm_mod_used_mmu_pages(kvm, -1); |
260746c0 AK |
999 | } |
1000 | ||
cea0f0e7 AK |
1001 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1002 | { | |
1ae0a13d | 1003 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
1004 | } |
1005 | ||
25c0de2c | 1006 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
2032a93d | 1007 | u64 *parent_pte, int direct) |
6aa8b732 | 1008 | { |
4db35314 | 1009 | struct kvm_mmu_page *sp; |
6aa8b732 | 1010 | |
ad312c7c ZX |
1011 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp); |
1012 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE); | |
2032a93d LJ |
1013 | if (!direct) |
1014 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, | |
1015 | PAGE_SIZE); | |
4db35314 | 1016 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
f05e70ac | 1017 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
291f26bc | 1018 | bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS); |
4db35314 AK |
1019 | sp->multimapped = 0; |
1020 | sp->parent_pte = parent_pte; | |
45221ab6 | 1021 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
4db35314 | 1022 | return sp; |
6aa8b732 AK |
1023 | } |
1024 | ||
714b93da | 1025 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1026 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 AK |
1027 | { |
1028 | struct kvm_pte_chain *pte_chain; | |
1029 | struct hlist_node *node; | |
1030 | int i; | |
1031 | ||
1032 | if (!parent_pte) | |
1033 | return; | |
4db35314 AK |
1034 | if (!sp->multimapped) { |
1035 | u64 *old = sp->parent_pte; | |
cea0f0e7 AK |
1036 | |
1037 | if (!old) { | |
4db35314 | 1038 | sp->parent_pte = parent_pte; |
cea0f0e7 AK |
1039 | return; |
1040 | } | |
4db35314 | 1041 | sp->multimapped = 1; |
714b93da | 1042 | pte_chain = mmu_alloc_pte_chain(vcpu); |
4db35314 AK |
1043 | INIT_HLIST_HEAD(&sp->parent_ptes); |
1044 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); | |
cea0f0e7 AK |
1045 | pte_chain->parent_ptes[0] = old; |
1046 | } | |
4db35314 | 1047 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) { |
cea0f0e7 AK |
1048 | if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1]) |
1049 | continue; | |
1050 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) | |
1051 | if (!pte_chain->parent_ptes[i]) { | |
1052 | pte_chain->parent_ptes[i] = parent_pte; | |
1053 | return; | |
1054 | } | |
1055 | } | |
714b93da | 1056 | pte_chain = mmu_alloc_pte_chain(vcpu); |
cea0f0e7 | 1057 | BUG_ON(!pte_chain); |
4db35314 | 1058 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); |
cea0f0e7 AK |
1059 | pte_chain->parent_ptes[0] = parent_pte; |
1060 | } | |
1061 | ||
4db35314 | 1062 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1063 | u64 *parent_pte) |
1064 | { | |
1065 | struct kvm_pte_chain *pte_chain; | |
1066 | struct hlist_node *node; | |
1067 | int i; | |
1068 | ||
4db35314 AK |
1069 | if (!sp->multimapped) { |
1070 | BUG_ON(sp->parent_pte != parent_pte); | |
1071 | sp->parent_pte = NULL; | |
cea0f0e7 AK |
1072 | return; |
1073 | } | |
4db35314 | 1074 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) |
cea0f0e7 AK |
1075 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { |
1076 | if (!pte_chain->parent_ptes[i]) | |
1077 | break; | |
1078 | if (pte_chain->parent_ptes[i] != parent_pte) | |
1079 | continue; | |
697fe2e2 AK |
1080 | while (i + 1 < NR_PTE_CHAIN_ENTRIES |
1081 | && pte_chain->parent_ptes[i + 1]) { | |
cea0f0e7 AK |
1082 | pte_chain->parent_ptes[i] |
1083 | = pte_chain->parent_ptes[i + 1]; | |
1084 | ++i; | |
1085 | } | |
1086 | pte_chain->parent_ptes[i] = NULL; | |
697fe2e2 AK |
1087 | if (i == 0) { |
1088 | hlist_del(&pte_chain->link); | |
90cb0529 | 1089 | mmu_free_pte_chain(pte_chain); |
4db35314 AK |
1090 | if (hlist_empty(&sp->parent_ptes)) { |
1091 | sp->multimapped = 0; | |
1092 | sp->parent_pte = NULL; | |
697fe2e2 AK |
1093 | } |
1094 | } | |
cea0f0e7 AK |
1095 | return; |
1096 | } | |
1097 | BUG(); | |
1098 | } | |
1099 | ||
6b18493d | 1100 | static void mmu_parent_walk(struct kvm_mmu_page *sp, mmu_parent_walk_fn fn) |
ad8cfbe3 MT |
1101 | { |
1102 | struct kvm_pte_chain *pte_chain; | |
1103 | struct hlist_node *node; | |
1104 | struct kvm_mmu_page *parent_sp; | |
1105 | int i; | |
1106 | ||
1107 | if (!sp->multimapped && sp->parent_pte) { | |
1108 | parent_sp = page_header(__pa(sp->parent_pte)); | |
1047df1f | 1109 | fn(parent_sp, sp->parent_pte); |
ad8cfbe3 MT |
1110 | return; |
1111 | } | |
1047df1f | 1112 | |
ad8cfbe3 MT |
1113 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) |
1114 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { | |
1047df1f XG |
1115 | u64 *spte = pte_chain->parent_ptes[i]; |
1116 | ||
1117 | if (!spte) | |
ad8cfbe3 | 1118 | break; |
1047df1f XG |
1119 | parent_sp = page_header(__pa(spte)); |
1120 | fn(parent_sp, spte); | |
ad8cfbe3 MT |
1121 | } |
1122 | } | |
1123 | ||
1047df1f XG |
1124 | static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte); |
1125 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) | |
0074ff63 | 1126 | { |
1047df1f | 1127 | mmu_parent_walk(sp, mark_unsync); |
0074ff63 MT |
1128 | } |
1129 | ||
1047df1f | 1130 | static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte) |
0074ff63 | 1131 | { |
1047df1f | 1132 | unsigned int index; |
0074ff63 | 1133 | |
1047df1f XG |
1134 | index = spte - sp->spt; |
1135 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1136 | return; |
1047df1f | 1137 | if (sp->unsync_children++) |
0074ff63 | 1138 | return; |
1047df1f | 1139 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1140 | } |
1141 | ||
d761a501 AK |
1142 | static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu, |
1143 | struct kvm_mmu_page *sp) | |
1144 | { | |
1145 | int i; | |
1146 | ||
1147 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1148 | sp->spt[i] = shadow_trap_nonpresent_pte; | |
1149 | } | |
1150 | ||
e8bc217a | 1151 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
be71e061 | 1152 | struct kvm_mmu_page *sp, bool clear_unsync) |
e8bc217a MT |
1153 | { |
1154 | return 1; | |
1155 | } | |
1156 | ||
a7052897 MT |
1157 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1158 | { | |
1159 | } | |
1160 | ||
60c8aec6 MT |
1161 | #define KVM_PAGE_ARRAY_NR 16 |
1162 | ||
1163 | struct kvm_mmu_pages { | |
1164 | struct mmu_page_and_offset { | |
1165 | struct kvm_mmu_page *sp; | |
1166 | unsigned int idx; | |
1167 | } page[KVM_PAGE_ARRAY_NR]; | |
1168 | unsigned int nr; | |
1169 | }; | |
1170 | ||
0074ff63 MT |
1171 | #define for_each_unsync_children(bitmap, idx) \ |
1172 | for (idx = find_first_bit(bitmap, 512); \ | |
1173 | idx < 512; \ | |
1174 | idx = find_next_bit(bitmap, 512, idx+1)) | |
1175 | ||
cded19f3 HE |
1176 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1177 | int idx) | |
4731d4c7 | 1178 | { |
60c8aec6 | 1179 | int i; |
4731d4c7 | 1180 | |
60c8aec6 MT |
1181 | if (sp->unsync) |
1182 | for (i=0; i < pvec->nr; i++) | |
1183 | if (pvec->page[i].sp == sp) | |
1184 | return 0; | |
1185 | ||
1186 | pvec->page[pvec->nr].sp = sp; | |
1187 | pvec->page[pvec->nr].idx = idx; | |
1188 | pvec->nr++; | |
1189 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1190 | } | |
1191 | ||
1192 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1193 | struct kvm_mmu_pages *pvec) | |
1194 | { | |
1195 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1196 | |
0074ff63 | 1197 | for_each_unsync_children(sp->unsync_child_bitmap, i) { |
7a8f1a74 | 1198 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1199 | u64 ent = sp->spt[i]; |
1200 | ||
7a8f1a74 XG |
1201 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) |
1202 | goto clear_child_bitmap; | |
1203 | ||
1204 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1205 | ||
1206 | if (child->unsync_children) { | |
1207 | if (mmu_pages_add(pvec, child, i)) | |
1208 | return -ENOSPC; | |
1209 | ||
1210 | ret = __mmu_unsync_walk(child, pvec); | |
1211 | if (!ret) | |
1212 | goto clear_child_bitmap; | |
1213 | else if (ret > 0) | |
1214 | nr_unsync_leaf += ret; | |
1215 | else | |
1216 | return ret; | |
1217 | } else if (child->unsync) { | |
1218 | nr_unsync_leaf++; | |
1219 | if (mmu_pages_add(pvec, child, i)) | |
1220 | return -ENOSPC; | |
1221 | } else | |
1222 | goto clear_child_bitmap; | |
1223 | ||
1224 | continue; | |
1225 | ||
1226 | clear_child_bitmap: | |
1227 | __clear_bit(i, sp->unsync_child_bitmap); | |
1228 | sp->unsync_children--; | |
1229 | WARN_ON((int)sp->unsync_children < 0); | |
4731d4c7 MT |
1230 | } |
1231 | ||
4731d4c7 | 1232 | |
60c8aec6 MT |
1233 | return nr_unsync_leaf; |
1234 | } | |
1235 | ||
1236 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1237 | struct kvm_mmu_pages *pvec) | |
1238 | { | |
1239 | if (!sp->unsync_children) | |
1240 | return 0; | |
1241 | ||
1242 | mmu_pages_add(pvec, sp, 0); | |
1243 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1244 | } |
1245 | ||
4731d4c7 MT |
1246 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1247 | { | |
1248 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1249 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1250 | sp->unsync = 0; |
1251 | --kvm->stat.mmu_unsync; | |
1252 | } | |
1253 | ||
7775834a XG |
1254 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1255 | struct list_head *invalid_list); | |
1256 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1257 | struct list_head *invalid_list); | |
4731d4c7 | 1258 | |
f41d335a XG |
1259 | #define for_each_gfn_sp(kvm, sp, gfn, pos) \ |
1260 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1261 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1262 | if ((sp)->gfn != (gfn)) {} else | |
1263 | ||
f41d335a XG |
1264 | #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \ |
1265 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1266 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1267 | if ((sp)->gfn != (gfn) || (sp)->role.direct || \ | |
1268 | (sp)->role.invalid) {} else | |
1269 | ||
f918b443 | 1270 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1271 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1272 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1273 | { |
5b7e0102 | 1274 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1275 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1276 | return 1; |
1277 | } | |
1278 | ||
f918b443 | 1279 | if (clear_unsync) |
1d9dc7e0 | 1280 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1281 | |
be71e061 | 1282 | if (vcpu->arch.mmu.sync_page(vcpu, sp, clear_unsync)) { |
d98ba053 | 1283 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1284 | return 1; |
1285 | } | |
1286 | ||
1287 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1288 | return 0; |
1289 | } | |
1290 | ||
1d9dc7e0 XG |
1291 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1292 | struct kvm_mmu_page *sp) | |
1293 | { | |
d98ba053 | 1294 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1295 | int ret; |
1296 | ||
d98ba053 | 1297 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1298 | if (ret) |
d98ba053 XG |
1299 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1300 | ||
1d9dc7e0 XG |
1301 | return ret; |
1302 | } | |
1303 | ||
d98ba053 XG |
1304 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1305 | struct list_head *invalid_list) | |
1d9dc7e0 | 1306 | { |
d98ba053 | 1307 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1308 | } |
1309 | ||
9f1a122f XG |
1310 | /* @gfn should be write-protected at the call site */ |
1311 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1312 | { | |
9f1a122f | 1313 | struct kvm_mmu_page *s; |
f41d335a | 1314 | struct hlist_node *node; |
d98ba053 | 1315 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1316 | bool flush = false; |
1317 | ||
f41d335a | 1318 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1319 | if (!s->unsync) |
9f1a122f XG |
1320 | continue; |
1321 | ||
1322 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
1323 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || | |
be71e061 | 1324 | (vcpu->arch.mmu.sync_page(vcpu, s, true))) { |
d98ba053 | 1325 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1326 | continue; |
1327 | } | |
1328 | kvm_unlink_unsync_page(vcpu->kvm, s); | |
1329 | flush = true; | |
1330 | } | |
1331 | ||
d98ba053 | 1332 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f XG |
1333 | if (flush) |
1334 | kvm_mmu_flush_tlb(vcpu); | |
1335 | } | |
1336 | ||
60c8aec6 MT |
1337 | struct mmu_page_path { |
1338 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1339 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1340 | }; |
1341 | ||
60c8aec6 MT |
1342 | #define for_each_sp(pvec, sp, parents, i) \ |
1343 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1344 | sp = pvec.page[i].sp; \ | |
1345 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1346 | i = mmu_pages_next(&pvec, &parents, i)) | |
1347 | ||
cded19f3 HE |
1348 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1349 | struct mmu_page_path *parents, | |
1350 | int i) | |
60c8aec6 MT |
1351 | { |
1352 | int n; | |
1353 | ||
1354 | for (n = i+1; n < pvec->nr; n++) { | |
1355 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1356 | ||
1357 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1358 | parents->idx[0] = pvec->page[n].idx; | |
1359 | return n; | |
1360 | } | |
1361 | ||
1362 | parents->parent[sp->role.level-2] = sp; | |
1363 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1364 | } | |
1365 | ||
1366 | return n; | |
1367 | } | |
1368 | ||
cded19f3 | 1369 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1370 | { |
60c8aec6 MT |
1371 | struct kvm_mmu_page *sp; |
1372 | unsigned int level = 0; | |
1373 | ||
1374 | do { | |
1375 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1376 | |
60c8aec6 MT |
1377 | sp = parents->parent[level]; |
1378 | if (!sp) | |
1379 | return; | |
1380 | ||
1381 | --sp->unsync_children; | |
1382 | WARN_ON((int)sp->unsync_children < 0); | |
1383 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1384 | level++; | |
1385 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1386 | } |
1387 | ||
60c8aec6 MT |
1388 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1389 | struct mmu_page_path *parents, | |
1390 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1391 | { |
60c8aec6 MT |
1392 | parents->parent[parent->role.level-1] = NULL; |
1393 | pvec->nr = 0; | |
1394 | } | |
4731d4c7 | 1395 | |
60c8aec6 MT |
1396 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1397 | struct kvm_mmu_page *parent) | |
1398 | { | |
1399 | int i; | |
1400 | struct kvm_mmu_page *sp; | |
1401 | struct mmu_page_path parents; | |
1402 | struct kvm_mmu_pages pages; | |
d98ba053 | 1403 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
1404 | |
1405 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1406 | while (mmu_unsync_walk(parent, &pages)) { | |
b1a36821 MT |
1407 | int protected = 0; |
1408 | ||
1409 | for_each_sp(pages, sp, parents, i) | |
1410 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1411 | ||
1412 | if (protected) | |
1413 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1414 | ||
60c8aec6 | 1415 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 1416 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1417 | mmu_pages_clear_parents(&parents); |
1418 | } | |
d98ba053 | 1419 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 1420 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1421 | kvm_mmu_pages_init(parent, &parents, &pages); |
1422 | } | |
4731d4c7 MT |
1423 | } |
1424 | ||
cea0f0e7 AK |
1425 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1426 | gfn_t gfn, | |
1427 | gva_t gaddr, | |
1428 | unsigned level, | |
f6e2c02b | 1429 | int direct, |
41074d07 | 1430 | unsigned access, |
f7d9c7b7 | 1431 | u64 *parent_pte) |
cea0f0e7 AK |
1432 | { |
1433 | union kvm_mmu_page_role role; | |
cea0f0e7 | 1434 | unsigned quadrant; |
9f1a122f | 1435 | struct kvm_mmu_page *sp; |
f41d335a | 1436 | struct hlist_node *node; |
9f1a122f | 1437 | bool need_sync = false; |
cea0f0e7 | 1438 | |
a770f6f2 | 1439 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1440 | role.level = level; |
f6e2c02b | 1441 | role.direct = direct; |
84b0c8c6 | 1442 | if (role.direct) |
5b7e0102 | 1443 | role.cr4_pae = 0; |
41074d07 | 1444 | role.access = access; |
b66d8000 | 1445 | if (!tdp_enabled && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { |
cea0f0e7 AK |
1446 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1447 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1448 | role.quadrant = quadrant; | |
1449 | } | |
f41d335a | 1450 | for_each_gfn_sp(vcpu->kvm, sp, gfn, node) { |
7ae680eb XG |
1451 | if (!need_sync && sp->unsync) |
1452 | need_sync = true; | |
4731d4c7 | 1453 | |
7ae680eb XG |
1454 | if (sp->role.word != role.word) |
1455 | continue; | |
4731d4c7 | 1456 | |
7ae680eb XG |
1457 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
1458 | break; | |
e02aa901 | 1459 | |
7ae680eb XG |
1460 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
1461 | if (sp->unsync_children) { | |
a8eeb04a | 1462 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
7ae680eb XG |
1463 | kvm_mmu_mark_parents_unsync(sp); |
1464 | } else if (sp->unsync) | |
1465 | kvm_mmu_mark_parents_unsync(sp); | |
e02aa901 | 1466 | |
7ae680eb XG |
1467 | trace_kvm_mmu_get_page(sp, false); |
1468 | return sp; | |
1469 | } | |
dfc5aa00 | 1470 | ++vcpu->kvm->stat.mmu_cache_miss; |
2032a93d | 1471 | sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct); |
4db35314 AK |
1472 | if (!sp) |
1473 | return sp; | |
4db35314 AK |
1474 | sp->gfn = gfn; |
1475 | sp->role = role; | |
7ae680eb XG |
1476 | hlist_add_head(&sp->hash_link, |
1477 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 1478 | if (!direct) { |
b1a36821 MT |
1479 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1480 | kvm_flush_remote_tlbs(vcpu->kvm); | |
9f1a122f XG |
1481 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
1482 | kvm_sync_pages(vcpu, gfn); | |
1483 | ||
4731d4c7 MT |
1484 | account_shadowed(vcpu->kvm, gfn); |
1485 | } | |
131d8279 AK |
1486 | if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte) |
1487 | vcpu->arch.mmu.prefetch_page(vcpu, sp); | |
1488 | else | |
1489 | nonpaging_prefetch_page(vcpu, sp); | |
f691fe1d | 1490 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1491 | return sp; |
cea0f0e7 AK |
1492 | } |
1493 | ||
2d11123a AK |
1494 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1495 | struct kvm_vcpu *vcpu, u64 addr) | |
1496 | { | |
1497 | iterator->addr = addr; | |
1498 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1499 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
1500 | if (iterator->level == PT32E_ROOT_LEVEL) { | |
1501 | iterator->shadow_addr | |
1502 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
1503 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
1504 | --iterator->level; | |
1505 | if (!iterator->shadow_addr) | |
1506 | iterator->level = 0; | |
1507 | } | |
1508 | } | |
1509 | ||
1510 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
1511 | { | |
1512 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
1513 | return false; | |
4d88954d MT |
1514 | |
1515 | if (iterator->level == PT_PAGE_TABLE_LEVEL) | |
1516 | if (is_large_pte(*iterator->sptep)) | |
1517 | return false; | |
1518 | ||
2d11123a AK |
1519 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
1520 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
1521 | return true; | |
1522 | } | |
1523 | ||
1524 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) | |
1525 | { | |
1526 | iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK; | |
1527 | --iterator->level; | |
1528 | } | |
1529 | ||
32ef26a3 AK |
1530 | static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp) |
1531 | { | |
1532 | u64 spte; | |
1533 | ||
1534 | spte = __pa(sp->spt) | |
1535 | | PT_PRESENT_MASK | PT_ACCESSED_MASK | |
1536 | | PT_WRITABLE_MASK | PT_USER_MASK; | |
121eee97 | 1537 | __set_spte(sptep, spte); |
32ef26a3 AK |
1538 | } |
1539 | ||
a3aa51cf AK |
1540 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) |
1541 | { | |
1542 | if (is_large_pte(*sptep)) { | |
1543 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); | |
1544 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1545 | } | |
1546 | } | |
1547 | ||
a357bd22 AK |
1548 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1549 | unsigned direct_access) | |
1550 | { | |
1551 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
1552 | struct kvm_mmu_page *child; | |
1553 | ||
1554 | /* | |
1555 | * For the direct sp, if the guest pte's dirty bit | |
1556 | * changed form clean to dirty, it will corrupt the | |
1557 | * sp's access: allow writable in the read-only sp, | |
1558 | * so we should update the spte at this point to get | |
1559 | * a new sp with the correct access. | |
1560 | */ | |
1561 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
1562 | if (child->role.access == direct_access) | |
1563 | return; | |
1564 | ||
1565 | mmu_page_remove_parent_pte(child, sptep); | |
1566 | __set_spte(sptep, shadow_trap_nonpresent_pte); | |
1567 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1568 | } | |
1569 | } | |
1570 | ||
90cb0529 | 1571 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 1572 | struct kvm_mmu_page *sp) |
a436036b | 1573 | { |
697fe2e2 AK |
1574 | unsigned i; |
1575 | u64 *pt; | |
1576 | u64 ent; | |
1577 | ||
4db35314 | 1578 | pt = sp->spt; |
697fe2e2 | 1579 | |
697fe2e2 AK |
1580 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { |
1581 | ent = pt[i]; | |
1582 | ||
05da4558 | 1583 | if (is_shadow_present_pte(ent)) { |
776e6633 | 1584 | if (!is_last_spte(ent, sp->role.level)) { |
05da4558 MT |
1585 | ent &= PT64_BASE_ADDR_MASK; |
1586 | mmu_page_remove_parent_pte(page_header(ent), | |
1587 | &pt[i]); | |
1588 | } else { | |
776e6633 MT |
1589 | if (is_large_pte(ent)) |
1590 | --kvm->stat.lpages; | |
be38d276 AK |
1591 | drop_spte(kvm, &pt[i], |
1592 | shadow_trap_nonpresent_pte); | |
05da4558 MT |
1593 | } |
1594 | } | |
c7addb90 | 1595 | pt[i] = shadow_trap_nonpresent_pte; |
697fe2e2 | 1596 | } |
a436036b AK |
1597 | } |
1598 | ||
4db35314 | 1599 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1600 | { |
4db35314 | 1601 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
1602 | } |
1603 | ||
12b7d28f AK |
1604 | static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm) |
1605 | { | |
1606 | int i; | |
988a2cae | 1607 | struct kvm_vcpu *vcpu; |
12b7d28f | 1608 | |
988a2cae GN |
1609 | kvm_for_each_vcpu(i, vcpu, kvm) |
1610 | vcpu->arch.last_pte_updated = NULL; | |
12b7d28f AK |
1611 | } |
1612 | ||
31aa2b44 | 1613 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b AK |
1614 | { |
1615 | u64 *parent_pte; | |
1616 | ||
4db35314 AK |
1617 | while (sp->multimapped || sp->parent_pte) { |
1618 | if (!sp->multimapped) | |
1619 | parent_pte = sp->parent_pte; | |
a436036b AK |
1620 | else { |
1621 | struct kvm_pte_chain *chain; | |
1622 | ||
4db35314 | 1623 | chain = container_of(sp->parent_ptes.first, |
a436036b AK |
1624 | struct kvm_pte_chain, link); |
1625 | parent_pte = chain->parent_ptes[0]; | |
1626 | } | |
697fe2e2 | 1627 | BUG_ON(!parent_pte); |
4db35314 | 1628 | kvm_mmu_put_page(sp, parent_pte); |
d555c333 | 1629 | __set_spte(parent_pte, shadow_trap_nonpresent_pte); |
a436036b | 1630 | } |
31aa2b44 AK |
1631 | } |
1632 | ||
60c8aec6 | 1633 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
1634 | struct kvm_mmu_page *parent, |
1635 | struct list_head *invalid_list) | |
4731d4c7 | 1636 | { |
60c8aec6 MT |
1637 | int i, zapped = 0; |
1638 | struct mmu_page_path parents; | |
1639 | struct kvm_mmu_pages pages; | |
4731d4c7 | 1640 | |
60c8aec6 | 1641 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1642 | return 0; |
60c8aec6 MT |
1643 | |
1644 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1645 | while (mmu_unsync_walk(parent, &pages)) { | |
1646 | struct kvm_mmu_page *sp; | |
1647 | ||
1648 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 1649 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 1650 | mmu_pages_clear_parents(&parents); |
77662e00 | 1651 | zapped++; |
60c8aec6 | 1652 | } |
60c8aec6 MT |
1653 | kvm_mmu_pages_init(parent, &parents, &pages); |
1654 | } | |
1655 | ||
1656 | return zapped; | |
4731d4c7 MT |
1657 | } |
1658 | ||
7775834a XG |
1659 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1660 | struct list_head *invalid_list) | |
31aa2b44 | 1661 | { |
4731d4c7 | 1662 | int ret; |
f691fe1d | 1663 | |
7775834a | 1664 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 1665 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 1666 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 1667 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 1668 | kvm_mmu_unlink_parents(kvm, sp); |
f6e2c02b | 1669 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 1670 | unaccount_shadowed(kvm, sp->gfn); |
4731d4c7 MT |
1671 | if (sp->unsync) |
1672 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 1673 | if (!sp->root_count) { |
54a4f023 GJ |
1674 | /* Count self */ |
1675 | ret++; | |
7775834a | 1676 | list_move(&sp->link, invalid_list); |
2e53d63a | 1677 | } else { |
5b5c6a5a | 1678 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
2e53d63a MT |
1679 | kvm_reload_remote_mmus(kvm); |
1680 | } | |
7775834a XG |
1681 | |
1682 | sp->role.invalid = 1; | |
12b7d28f | 1683 | kvm_mmu_reset_last_pte_updated(kvm); |
4731d4c7 | 1684 | return ret; |
a436036b AK |
1685 | } |
1686 | ||
7775834a XG |
1687 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
1688 | struct list_head *invalid_list) | |
1689 | { | |
1690 | struct kvm_mmu_page *sp; | |
1691 | ||
1692 | if (list_empty(invalid_list)) | |
1693 | return; | |
1694 | ||
1695 | kvm_flush_remote_tlbs(kvm); | |
1696 | ||
1697 | do { | |
1698 | sp = list_first_entry(invalid_list, struct kvm_mmu_page, link); | |
1699 | WARN_ON(!sp->role.invalid || sp->root_count); | |
1700 | kvm_mmu_free_page(kvm, sp); | |
1701 | } while (!list_empty(invalid_list)); | |
1702 | ||
1703 | } | |
1704 | ||
82ce2c96 IE |
1705 | /* |
1706 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 1707 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 1708 | */ |
49d5ca26 | 1709 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 1710 | { |
d98ba053 | 1711 | LIST_HEAD(invalid_list); |
82ce2c96 IE |
1712 | /* |
1713 | * If we set the number of mmu pages to be smaller be than the | |
1714 | * number of actived pages , we must to free some mmu pages before we | |
1715 | * change the value | |
1716 | */ | |
1717 | ||
49d5ca26 DH |
1718 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
1719 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages && | |
77662e00 | 1720 | !list_empty(&kvm->arch.active_mmu_pages)) { |
82ce2c96 IE |
1721 | struct kvm_mmu_page *page; |
1722 | ||
f05e70ac | 1723 | page = container_of(kvm->arch.active_mmu_pages.prev, |
82ce2c96 | 1724 | struct kvm_mmu_page, link); |
80b63faf XF |
1725 | kvm_mmu_prepare_zap_page(kvm, page, &invalid_list); |
1726 | kvm_mmu_commit_zap_page(kvm, &invalid_list); | |
82ce2c96 | 1727 | } |
49d5ca26 | 1728 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 1729 | } |
82ce2c96 | 1730 | |
49d5ca26 | 1731 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
82ce2c96 IE |
1732 | } |
1733 | ||
f67a46f4 | 1734 | static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 1735 | { |
4db35314 | 1736 | struct kvm_mmu_page *sp; |
f41d335a | 1737 | struct hlist_node *node; |
d98ba053 | 1738 | LIST_HEAD(invalid_list); |
a436036b AK |
1739 | int r; |
1740 | ||
b8688d51 | 1741 | pgprintk("%s: looking for gfn %lx\n", __func__, gfn); |
a436036b | 1742 | r = 0; |
f41d335a XG |
1743 | |
1744 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { | |
7ae680eb XG |
1745 | pgprintk("%s: gfn %lx role %x\n", __func__, gfn, |
1746 | sp->role.word); | |
1747 | r = 1; | |
f41d335a | 1748 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 1749 | } |
d98ba053 | 1750 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
a436036b | 1751 | return r; |
cea0f0e7 AK |
1752 | } |
1753 | ||
f67a46f4 | 1754 | static void mmu_unshadow(struct kvm *kvm, gfn_t gfn) |
97a0a01e | 1755 | { |
4db35314 | 1756 | struct kvm_mmu_page *sp; |
f41d335a | 1757 | struct hlist_node *node; |
d98ba053 | 1758 | LIST_HEAD(invalid_list); |
97a0a01e | 1759 | |
f41d335a | 1760 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { |
7ae680eb XG |
1761 | pgprintk("%s: zap %lx %x\n", |
1762 | __func__, gfn, sp->role.word); | |
f41d335a | 1763 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
97a0a01e | 1764 | } |
d98ba053 | 1765 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
97a0a01e AK |
1766 | } |
1767 | ||
38c335f1 | 1768 | static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn) |
6aa8b732 | 1769 | { |
bc6678a3 | 1770 | int slot = memslot_id(kvm, gfn); |
4db35314 | 1771 | struct kvm_mmu_page *sp = page_header(__pa(pte)); |
6aa8b732 | 1772 | |
291f26bc | 1773 | __set_bit(slot, sp->slot_bitmap); |
6aa8b732 AK |
1774 | } |
1775 | ||
6844dec6 MT |
1776 | static void mmu_convert_notrap(struct kvm_mmu_page *sp) |
1777 | { | |
1778 | int i; | |
1779 | u64 *pt = sp->spt; | |
1780 | ||
1781 | if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte) | |
1782 | return; | |
1783 | ||
1784 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
1785 | if (pt[i] == shadow_notrap_nonpresent_pte) | |
d555c333 | 1786 | __set_spte(&pt[i], shadow_trap_nonpresent_pte); |
6844dec6 MT |
1787 | } |
1788 | } | |
1789 | ||
74be52e3 SY |
1790 | /* |
1791 | * The function is based on mtrr_type_lookup() in | |
1792 | * arch/x86/kernel/cpu/mtrr/generic.c | |
1793 | */ | |
1794 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
1795 | u64 start, u64 end) | |
1796 | { | |
1797 | int i; | |
1798 | u64 base, mask; | |
1799 | u8 prev_match, curr_match; | |
1800 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
1801 | ||
1802 | if (!mtrr_state->enabled) | |
1803 | return 0xFF; | |
1804 | ||
1805 | /* Make end inclusive end, instead of exclusive */ | |
1806 | end--; | |
1807 | ||
1808 | /* Look in fixed ranges. Just return the type as per start */ | |
1809 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
1810 | int idx; | |
1811 | ||
1812 | if (start < 0x80000) { | |
1813 | idx = 0; | |
1814 | idx += (start >> 16); | |
1815 | return mtrr_state->fixed_ranges[idx]; | |
1816 | } else if (start < 0xC0000) { | |
1817 | idx = 1 * 8; | |
1818 | idx += ((start - 0x80000) >> 14); | |
1819 | return mtrr_state->fixed_ranges[idx]; | |
1820 | } else if (start < 0x1000000) { | |
1821 | idx = 3 * 8; | |
1822 | idx += ((start - 0xC0000) >> 12); | |
1823 | return mtrr_state->fixed_ranges[idx]; | |
1824 | } | |
1825 | } | |
1826 | ||
1827 | /* | |
1828 | * Look in variable ranges | |
1829 | * Look of multiple ranges matching this address and pick type | |
1830 | * as per MTRR precedence | |
1831 | */ | |
1832 | if (!(mtrr_state->enabled & 2)) | |
1833 | return mtrr_state->def_type; | |
1834 | ||
1835 | prev_match = 0xFF; | |
1836 | for (i = 0; i < num_var_ranges; ++i) { | |
1837 | unsigned short start_state, end_state; | |
1838 | ||
1839 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
1840 | continue; | |
1841 | ||
1842 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
1843 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
1844 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
1845 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
1846 | ||
1847 | start_state = ((start & mask) == (base & mask)); | |
1848 | end_state = ((end & mask) == (base & mask)); | |
1849 | if (start_state != end_state) | |
1850 | return 0xFE; | |
1851 | ||
1852 | if ((start & mask) != (base & mask)) | |
1853 | continue; | |
1854 | ||
1855 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
1856 | if (prev_match == 0xFF) { | |
1857 | prev_match = curr_match; | |
1858 | continue; | |
1859 | } | |
1860 | ||
1861 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
1862 | curr_match == MTRR_TYPE_UNCACHABLE) | |
1863 | return MTRR_TYPE_UNCACHABLE; | |
1864 | ||
1865 | if ((prev_match == MTRR_TYPE_WRBACK && | |
1866 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
1867 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
1868 | curr_match == MTRR_TYPE_WRBACK)) { | |
1869 | prev_match = MTRR_TYPE_WRTHROUGH; | |
1870 | curr_match = MTRR_TYPE_WRTHROUGH; | |
1871 | } | |
1872 | ||
1873 | if (prev_match != curr_match) | |
1874 | return MTRR_TYPE_UNCACHABLE; | |
1875 | } | |
1876 | ||
1877 | if (prev_match != 0xFF) | |
1878 | return prev_match; | |
1879 | ||
1880 | return mtrr_state->def_type; | |
1881 | } | |
1882 | ||
4b12f0de | 1883 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
1884 | { |
1885 | u8 mtrr; | |
1886 | ||
1887 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
1888 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
1889 | if (mtrr == 0xfe || mtrr == 0xff) | |
1890 | mtrr = MTRR_TYPE_WRBACK; | |
1891 | return mtrr; | |
1892 | } | |
4b12f0de | 1893 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 1894 | |
9cf5cf5a XG |
1895 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
1896 | { | |
1897 | trace_kvm_mmu_unsync_page(sp); | |
1898 | ++vcpu->kvm->stat.mmu_unsync; | |
1899 | sp->unsync = 1; | |
1900 | ||
1901 | kvm_mmu_mark_parents_unsync(sp); | |
1902 | mmu_convert_notrap(sp); | |
1903 | } | |
1904 | ||
1905 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 1906 | { |
4731d4c7 | 1907 | struct kvm_mmu_page *s; |
f41d335a | 1908 | struct hlist_node *node; |
9cf5cf5a | 1909 | |
f41d335a | 1910 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1911 | if (s->unsync) |
4731d4c7 | 1912 | continue; |
9cf5cf5a XG |
1913 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
1914 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 1915 | } |
4731d4c7 MT |
1916 | } |
1917 | ||
1918 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
1919 | bool can_unsync) | |
1920 | { | |
9cf5cf5a | 1921 | struct kvm_mmu_page *s; |
f41d335a | 1922 | struct hlist_node *node; |
9cf5cf5a XG |
1923 | bool need_unsync = false; |
1924 | ||
f41d335a | 1925 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
36a2e677 XG |
1926 | if (!can_unsync) |
1927 | return 1; | |
1928 | ||
9cf5cf5a | 1929 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1930 | return 1; |
9cf5cf5a XG |
1931 | |
1932 | if (!need_unsync && !s->unsync) { | |
36a2e677 | 1933 | if (!oos_shadow) |
9cf5cf5a XG |
1934 | return 1; |
1935 | need_unsync = true; | |
1936 | } | |
4731d4c7 | 1937 | } |
9cf5cf5a XG |
1938 | if (need_unsync) |
1939 | kvm_unsync_pages(vcpu, gfn); | |
4731d4c7 MT |
1940 | return 0; |
1941 | } | |
1942 | ||
d555c333 | 1943 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd | 1944 | unsigned pte_access, int user_fault, |
852e3c19 | 1945 | int write_fault, int dirty, int level, |
c2d0ee46 | 1946 | gfn_t gfn, pfn_t pfn, bool speculative, |
1403283a | 1947 | bool can_unsync, bool reset_host_protection) |
1c4f1fd6 AK |
1948 | { |
1949 | u64 spte; | |
1e73f9dd | 1950 | int ret = 0; |
64d4d521 | 1951 | |
1c4f1fd6 AK |
1952 | /* |
1953 | * We don't set the accessed bit, since we sometimes want to see | |
1954 | * whether the guest actually used the pte (in order to detect | |
1955 | * demand paging). | |
1956 | */ | |
4132779b | 1957 | spte = shadow_base_present_pte; |
947da538 | 1958 | if (!speculative) |
3201b5d9 | 1959 | spte |= shadow_accessed_mask; |
1c4f1fd6 AK |
1960 | if (!dirty) |
1961 | pte_access &= ~ACC_WRITE_MASK; | |
7b52345e SY |
1962 | if (pte_access & ACC_EXEC_MASK) |
1963 | spte |= shadow_x_mask; | |
1964 | else | |
1965 | spte |= shadow_nx_mask; | |
1c4f1fd6 | 1966 | if (pte_access & ACC_USER_MASK) |
7b52345e | 1967 | spte |= shadow_user_mask; |
852e3c19 | 1968 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 1969 | spte |= PT_PAGE_SIZE_MASK; |
4b12f0de SY |
1970 | if (tdp_enabled) |
1971 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, | |
1972 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 1973 | |
1403283a IE |
1974 | if (reset_host_protection) |
1975 | spte |= SPTE_HOST_WRITEABLE; | |
1976 | ||
35149e21 | 1977 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 AK |
1978 | |
1979 | if ((pte_access & ACC_WRITE_MASK) | |
8184dd38 AK |
1980 | || (!tdp_enabled && write_fault && !is_write_protection(vcpu) |
1981 | && !user_fault)) { | |
1c4f1fd6 | 1982 | |
852e3c19 JR |
1983 | if (level > PT_PAGE_TABLE_LEVEL && |
1984 | has_wrprotected_page(vcpu->kvm, gfn, level)) { | |
38187c83 | 1985 | ret = 1; |
be38d276 AK |
1986 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); |
1987 | goto done; | |
38187c83 MT |
1988 | } |
1989 | ||
1c4f1fd6 | 1990 | spte |= PT_WRITABLE_MASK; |
1c4f1fd6 | 1991 | |
69325a12 AK |
1992 | if (!tdp_enabled && !(pte_access & ACC_WRITE_MASK)) |
1993 | spte &= ~PT_USER_MASK; | |
1994 | ||
ecc5589f MT |
1995 | /* |
1996 | * Optimization: for pte sync, if spte was writable the hash | |
1997 | * lookup is unnecessary (and expensive). Write protection | |
1998 | * is responsibility of mmu_get_page / kvm_sync_page. | |
1999 | * Same reasoning can be applied to dirty page accounting. | |
2000 | */ | |
8dae4445 | 2001 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2002 | goto set_pte; |
2003 | ||
4731d4c7 | 2004 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
1c4f1fd6 | 2005 | pgprintk("%s: found shadow page for %lx, marking ro\n", |
b8688d51 | 2006 | __func__, gfn); |
1e73f9dd | 2007 | ret = 1; |
1c4f1fd6 | 2008 | pte_access &= ~ACC_WRITE_MASK; |
8dae4445 | 2009 | if (is_writable_pte(spte)) |
1c4f1fd6 | 2010 | spte &= ~PT_WRITABLE_MASK; |
1c4f1fd6 AK |
2011 | } |
2012 | } | |
2013 | ||
1c4f1fd6 AK |
2014 | if (pte_access & ACC_WRITE_MASK) |
2015 | mark_page_dirty(vcpu->kvm, gfn); | |
2016 | ||
38187c83 | 2017 | set_pte: |
b79b93f9 | 2018 | update_spte(sptep, spte); |
be38d276 | 2019 | done: |
1e73f9dd MT |
2020 | return ret; |
2021 | } | |
2022 | ||
d555c333 | 2023 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd MT |
2024 | unsigned pt_access, unsigned pte_access, |
2025 | int user_fault, int write_fault, int dirty, | |
852e3c19 | 2026 | int *ptwrite, int level, gfn_t gfn, |
1403283a IE |
2027 | pfn_t pfn, bool speculative, |
2028 | bool reset_host_protection) | |
1e73f9dd MT |
2029 | { |
2030 | int was_rmapped = 0; | |
53a27b39 | 2031 | int rmap_count; |
1e73f9dd MT |
2032 | |
2033 | pgprintk("%s: spte %llx access %x write_fault %d" | |
2034 | " user_fault %d gfn %lx\n", | |
d555c333 | 2035 | __func__, *sptep, pt_access, |
1e73f9dd MT |
2036 | write_fault, user_fault, gfn); |
2037 | ||
d555c333 | 2038 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
2039 | /* |
2040 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2041 | * the parent of the now unreachable PTE. | |
2042 | */ | |
852e3c19 JR |
2043 | if (level > PT_PAGE_TABLE_LEVEL && |
2044 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2045 | struct kvm_mmu_page *child; |
d555c333 | 2046 | u64 pte = *sptep; |
1e73f9dd MT |
2047 | |
2048 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
d555c333 | 2049 | mmu_page_remove_parent_pte(child, sptep); |
3be2264b MT |
2050 | __set_spte(sptep, shadow_trap_nonpresent_pte); |
2051 | kvm_flush_remote_tlbs(vcpu->kvm); | |
d555c333 | 2052 | } else if (pfn != spte_to_pfn(*sptep)) { |
1e73f9dd | 2053 | pgprintk("hfn old %lx new %lx\n", |
d555c333 | 2054 | spte_to_pfn(*sptep), pfn); |
be38d276 | 2055 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); |
91546356 | 2056 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2057 | } else |
2058 | was_rmapped = 1; | |
1e73f9dd | 2059 | } |
852e3c19 | 2060 | |
d555c333 | 2061 | if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault, |
1403283a IE |
2062 | dirty, level, gfn, pfn, speculative, true, |
2063 | reset_host_protection)) { | |
1e73f9dd MT |
2064 | if (write_fault) |
2065 | *ptwrite = 1; | |
5304efde | 2066 | kvm_mmu_flush_tlb(vcpu); |
a378b4e6 | 2067 | } |
1e73f9dd | 2068 | |
d555c333 | 2069 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
1e73f9dd | 2070 | pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n", |
d555c333 | 2071 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
2072 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
2073 | *sptep, sptep); | |
d555c333 | 2074 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2075 | ++vcpu->kvm->stat.lpages; |
2076 | ||
d555c333 | 2077 | page_header_update_slot(vcpu->kvm, sptep, gfn); |
1c4f1fd6 | 2078 | if (!was_rmapped) { |
44ad9944 | 2079 | rmap_count = rmap_add(vcpu, sptep, gfn); |
53a27b39 | 2080 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) |
852e3c19 | 2081 | rmap_recycle(vcpu, sptep, gfn); |
1c4f1fd6 | 2082 | } |
9ed5520d | 2083 | kvm_release_pfn_clean(pfn); |
1b7fcd32 | 2084 | if (speculative) { |
d555c333 | 2085 | vcpu->arch.last_pte_updated = sptep; |
1b7fcd32 AK |
2086 | vcpu->arch.last_pte_gfn = gfn; |
2087 | } | |
1c4f1fd6 AK |
2088 | } |
2089 | ||
6aa8b732 AK |
2090 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
2091 | { | |
2092 | } | |
2093 | ||
957ed9ef XG |
2094 | static struct kvm_memory_slot * |
2095 | pte_prefetch_gfn_to_memslot(struct kvm_vcpu *vcpu, gfn_t gfn, bool no_dirty_log) | |
2096 | { | |
2097 | struct kvm_memory_slot *slot; | |
2098 | ||
2099 | slot = gfn_to_memslot(vcpu->kvm, gfn); | |
2100 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID || | |
2101 | (no_dirty_log && slot->dirty_bitmap)) | |
2102 | slot = NULL; | |
2103 | ||
2104 | return slot; | |
2105 | } | |
2106 | ||
2107 | static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, | |
2108 | bool no_dirty_log) | |
2109 | { | |
2110 | struct kvm_memory_slot *slot; | |
2111 | unsigned long hva; | |
2112 | ||
2113 | slot = pte_prefetch_gfn_to_memslot(vcpu, gfn, no_dirty_log); | |
2114 | if (!slot) { | |
2115 | get_page(bad_page); | |
2116 | return page_to_pfn(bad_page); | |
2117 | } | |
2118 | ||
2119 | hva = gfn_to_hva_memslot(slot, gfn); | |
2120 | ||
2121 | return hva_to_pfn_atomic(vcpu->kvm, hva); | |
2122 | } | |
2123 | ||
2124 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2125 | struct kvm_mmu_page *sp, | |
2126 | u64 *start, u64 *end) | |
2127 | { | |
2128 | struct page *pages[PTE_PREFETCH_NUM]; | |
2129 | unsigned access = sp->role.access; | |
2130 | int i, ret; | |
2131 | gfn_t gfn; | |
2132 | ||
2133 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
2134 | if (!pte_prefetch_gfn_to_memslot(vcpu, gfn, access & ACC_WRITE_MASK)) | |
2135 | return -1; | |
2136 | ||
2137 | ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start); | |
2138 | if (ret <= 0) | |
2139 | return -1; | |
2140 | ||
2141 | for (i = 0; i < ret; i++, gfn++, start++) | |
2142 | mmu_set_spte(vcpu, start, ACC_ALL, | |
2143 | access, 0, 0, 1, NULL, | |
2144 | sp->role.level, gfn, | |
2145 | page_to_pfn(pages[i]), true, true); | |
2146 | ||
2147 | return 0; | |
2148 | } | |
2149 | ||
2150 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2151 | struct kvm_mmu_page *sp, u64 *sptep) | |
2152 | { | |
2153 | u64 *spte, *start = NULL; | |
2154 | int i; | |
2155 | ||
2156 | WARN_ON(!sp->role.direct); | |
2157 | ||
2158 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2159 | spte = sp->spt + i; | |
2160 | ||
2161 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
2162 | if (*spte != shadow_trap_nonpresent_pte || spte == sptep) { | |
2163 | if (!start) | |
2164 | continue; | |
2165 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2166 | break; | |
2167 | start = NULL; | |
2168 | } else if (!start) | |
2169 | start = spte; | |
2170 | } | |
2171 | } | |
2172 | ||
2173 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2174 | { | |
2175 | struct kvm_mmu_page *sp; | |
2176 | ||
2177 | /* | |
2178 | * Since it's no accessed bit on EPT, it's no way to | |
2179 | * distinguish between actually accessed translations | |
2180 | * and prefetched, so disable pte prefetch if EPT is | |
2181 | * enabled. | |
2182 | */ | |
2183 | if (!shadow_accessed_mask) | |
2184 | return; | |
2185 | ||
2186 | sp = page_header(__pa(sptep)); | |
2187 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2188 | return; | |
2189 | ||
2190 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2191 | } | |
2192 | ||
9f652d21 | 2193 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
852e3c19 | 2194 | int level, gfn_t gfn, pfn_t pfn) |
140754bc | 2195 | { |
9f652d21 | 2196 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2197 | struct kvm_mmu_page *sp; |
9f652d21 | 2198 | int pt_write = 0; |
140754bc | 2199 | gfn_t pseudo_gfn; |
6aa8b732 | 2200 | |
9f652d21 | 2201 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2202 | if (iterator.level == level) { |
9f652d21 AK |
2203 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL, |
2204 | 0, write, 1, &pt_write, | |
1403283a | 2205 | level, gfn, pfn, false, true); |
957ed9ef | 2206 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2207 | ++vcpu->stat.pf_fixed; |
2208 | break; | |
6aa8b732 AK |
2209 | } |
2210 | ||
9f652d21 | 2211 | if (*iterator.sptep == shadow_trap_nonpresent_pte) { |
c9fa0b3b LJ |
2212 | u64 base_addr = iterator.addr; |
2213 | ||
2214 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2215 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 AK |
2216 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
2217 | iterator.level - 1, | |
2218 | 1, ACC_ALL, iterator.sptep); | |
2219 | if (!sp) { | |
2220 | pgprintk("nonpaging_map: ENOMEM\n"); | |
2221 | kvm_release_pfn_clean(pfn); | |
2222 | return -ENOMEM; | |
2223 | } | |
140754bc | 2224 | |
d555c333 AK |
2225 | __set_spte(iterator.sptep, |
2226 | __pa(sp->spt) | |
2227 | | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
2228 | | shadow_user_mask | shadow_x_mask); | |
9f652d21 AK |
2229 | } |
2230 | } | |
2231 | return pt_write; | |
6aa8b732 AK |
2232 | } |
2233 | ||
bf998156 HY |
2234 | static void kvm_send_hwpoison_signal(struct kvm *kvm, gfn_t gfn) |
2235 | { | |
2236 | char buf[1]; | |
2237 | void __user *hva; | |
2238 | int r; | |
2239 | ||
2240 | /* Touch the page, so send SIGBUS */ | |
2241 | hva = (void __user *)gfn_to_hva(kvm, gfn); | |
2242 | r = copy_from_user(buf, hva, 1); | |
2243 | } | |
2244 | ||
2245 | static int kvm_handle_bad_page(struct kvm *kvm, gfn_t gfn, pfn_t pfn) | |
2246 | { | |
2247 | kvm_release_pfn_clean(pfn); | |
2248 | if (is_hwpoison_pfn(pfn)) { | |
2249 | kvm_send_hwpoison_signal(kvm, gfn); | |
2250 | return 0; | |
edba23e5 GN |
2251 | } else if (is_fault_pfn(pfn)) |
2252 | return -EFAULT; | |
2253 | ||
bf998156 HY |
2254 | return 1; |
2255 | } | |
2256 | ||
10589a46 MT |
2257 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn) |
2258 | { | |
2259 | int r; | |
852e3c19 | 2260 | int level; |
35149e21 | 2261 | pfn_t pfn; |
e930bffe | 2262 | unsigned long mmu_seq; |
aaee2c94 | 2263 | |
852e3c19 JR |
2264 | level = mapping_level(vcpu, gfn); |
2265 | ||
2266 | /* | |
2267 | * This path builds a PAE pagetable - so we can map 2mb pages at | |
2268 | * maximum. Therefore check if the level is larger than that. | |
2269 | */ | |
2270 | if (level > PT_DIRECTORY_LEVEL) | |
2271 | level = PT_DIRECTORY_LEVEL; | |
2272 | ||
2273 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 2274 | |
e930bffe | 2275 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2276 | smp_rmb(); |
35149e21 | 2277 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
aaee2c94 | 2278 | |
d196e343 | 2279 | /* mmio */ |
bf998156 HY |
2280 | if (is_error_pfn(pfn)) |
2281 | return kvm_handle_bad_page(vcpu->kvm, gfn, pfn); | |
d196e343 | 2282 | |
aaee2c94 | 2283 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2284 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2285 | goto out_unlock; | |
eb787d10 | 2286 | kvm_mmu_free_some_pages(vcpu); |
852e3c19 | 2287 | r = __direct_map(vcpu, v, write, level, gfn, pfn); |
aaee2c94 MT |
2288 | spin_unlock(&vcpu->kvm->mmu_lock); |
2289 | ||
aaee2c94 | 2290 | |
10589a46 | 2291 | return r; |
e930bffe AA |
2292 | |
2293 | out_unlock: | |
2294 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2295 | kvm_release_pfn_clean(pfn); | |
2296 | return 0; | |
10589a46 MT |
2297 | } |
2298 | ||
2299 | ||
17ac10ad AK |
2300 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
2301 | { | |
2302 | int i; | |
4db35314 | 2303 | struct kvm_mmu_page *sp; |
d98ba053 | 2304 | LIST_HEAD(invalid_list); |
17ac10ad | 2305 | |
ad312c7c | 2306 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 2307 | return; |
aaee2c94 | 2308 | spin_lock(&vcpu->kvm->mmu_lock); |
ad312c7c ZX |
2309 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { |
2310 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
17ac10ad | 2311 | |
4db35314 AK |
2312 | sp = page_header(root); |
2313 | --sp->root_count; | |
d98ba053 XG |
2314 | if (!sp->root_count && sp->role.invalid) { |
2315 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
2316 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
2317 | } | |
ad312c7c | 2318 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
aaee2c94 | 2319 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad AK |
2320 | return; |
2321 | } | |
17ac10ad | 2322 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2323 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2324 | |
417726a3 | 2325 | if (root) { |
417726a3 | 2326 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2327 | sp = page_header(root); |
2328 | --sp->root_count; | |
2e53d63a | 2329 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
2330 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2331 | &invalid_list); | |
417726a3 | 2332 | } |
ad312c7c | 2333 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2334 | } |
d98ba053 | 2335 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 2336 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2337 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2338 | } |
2339 | ||
8986ecc0 MT |
2340 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2341 | { | |
2342 | int ret = 0; | |
2343 | ||
2344 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 2345 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
2346 | ret = 1; |
2347 | } | |
2348 | ||
2349 | return ret; | |
2350 | } | |
2351 | ||
2352 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) | |
17ac10ad AK |
2353 | { |
2354 | int i; | |
cea0f0e7 | 2355 | gfn_t root_gfn; |
4db35314 | 2356 | struct kvm_mmu_page *sp; |
f6e2c02b | 2357 | int direct = 0; |
6de4f3ad | 2358 | u64 pdptr; |
3bb65a22 | 2359 | |
ad312c7c | 2360 | root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT; |
17ac10ad | 2361 | |
ad312c7c ZX |
2362 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { |
2363 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
17ac10ad AK |
2364 | |
2365 | ASSERT(!VALID_PAGE(root)); | |
8986ecc0 MT |
2366 | if (mmu_check_root(vcpu, root_gfn)) |
2367 | return 1; | |
5a7388c2 EN |
2368 | if (tdp_enabled) { |
2369 | direct = 1; | |
2370 | root_gfn = 0; | |
2371 | } | |
8facbbff | 2372 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2373 | kvm_mmu_free_some_pages(vcpu); |
4db35314 | 2374 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, |
f6e2c02b | 2375 | PT64_ROOT_LEVEL, direct, |
fb72d167 | 2376 | ACC_ALL, NULL); |
4db35314 AK |
2377 | root = __pa(sp->spt); |
2378 | ++sp->root_count; | |
8facbbff | 2379 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2380 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 2381 | return 0; |
17ac10ad | 2382 | } |
f6e2c02b | 2383 | direct = !is_paging(vcpu); |
17ac10ad | 2384 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2385 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
2386 | |
2387 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 2388 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
6de4f3ad | 2389 | pdptr = kvm_pdptr_read(vcpu, i); |
43a3795a | 2390 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 2391 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
2392 | continue; |
2393 | } | |
6de4f3ad | 2394 | root_gfn = pdptr >> PAGE_SHIFT; |
ad312c7c | 2395 | } else if (vcpu->arch.mmu.root_level == 0) |
cea0f0e7 | 2396 | root_gfn = 0; |
8986ecc0 MT |
2397 | if (mmu_check_root(vcpu, root_gfn)) |
2398 | return 1; | |
5a7388c2 EN |
2399 | if (tdp_enabled) { |
2400 | direct = 1; | |
2401 | root_gfn = i << 30; | |
2402 | } | |
8facbbff | 2403 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2404 | kvm_mmu_free_some_pages(vcpu); |
4db35314 | 2405 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
f6e2c02b | 2406 | PT32_ROOT_LEVEL, direct, |
f7d9c7b7 | 2407 | ACC_ALL, NULL); |
4db35314 AK |
2408 | root = __pa(sp->spt); |
2409 | ++sp->root_count; | |
8facbbff AK |
2410 | spin_unlock(&vcpu->kvm->mmu_lock); |
2411 | ||
ad312c7c | 2412 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; |
17ac10ad | 2413 | } |
ad312c7c | 2414 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
8986ecc0 | 2415 | return 0; |
17ac10ad AK |
2416 | } |
2417 | ||
0ba73cda MT |
2418 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
2419 | { | |
2420 | int i; | |
2421 | struct kvm_mmu_page *sp; | |
2422 | ||
2423 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
2424 | return; | |
2425 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2426 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
2427 | sp = page_header(root); | |
2428 | mmu_sync_children(vcpu, sp); | |
2429 | return; | |
2430 | } | |
2431 | for (i = 0; i < 4; ++i) { | |
2432 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2433 | ||
8986ecc0 | 2434 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
2435 | root &= PT64_BASE_ADDR_MASK; |
2436 | sp = page_header(root); | |
2437 | mmu_sync_children(vcpu, sp); | |
2438 | } | |
2439 | } | |
2440 | } | |
2441 | ||
2442 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
2443 | { | |
2444 | spin_lock(&vcpu->kvm->mmu_lock); | |
2445 | mmu_sync_roots(vcpu); | |
6cffe8ca | 2446 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
2447 | } |
2448 | ||
1871c602 GN |
2449 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
2450 | u32 access, u32 *error) | |
6aa8b732 | 2451 | { |
1871c602 GN |
2452 | if (error) |
2453 | *error = 0; | |
6aa8b732 AK |
2454 | return vaddr; |
2455 | } | |
2456 | ||
2457 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, | |
3f3e7124 | 2458 | u32 error_code) |
6aa8b732 | 2459 | { |
e833240f | 2460 | gfn_t gfn; |
e2dec939 | 2461 | int r; |
6aa8b732 | 2462 | |
b8688d51 | 2463 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
e2dec939 AK |
2464 | r = mmu_topup_memory_caches(vcpu); |
2465 | if (r) | |
2466 | return r; | |
714b93da | 2467 | |
6aa8b732 | 2468 | ASSERT(vcpu); |
ad312c7c | 2469 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 2470 | |
e833240f | 2471 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 2472 | |
e833240f AK |
2473 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
2474 | error_code & PFERR_WRITE_MASK, gfn); | |
6aa8b732 AK |
2475 | } |
2476 | ||
fb72d167 JR |
2477 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, |
2478 | u32 error_code) | |
2479 | { | |
35149e21 | 2480 | pfn_t pfn; |
fb72d167 | 2481 | int r; |
852e3c19 | 2482 | int level; |
05da4558 | 2483 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 2484 | unsigned long mmu_seq; |
fb72d167 JR |
2485 | |
2486 | ASSERT(vcpu); | |
2487 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
2488 | ||
2489 | r = mmu_topup_memory_caches(vcpu); | |
2490 | if (r) | |
2491 | return r; | |
2492 | ||
852e3c19 JR |
2493 | level = mapping_level(vcpu, gfn); |
2494 | ||
2495 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
2496 | ||
e930bffe | 2497 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2498 | smp_rmb(); |
35149e21 | 2499 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
bf998156 HY |
2500 | if (is_error_pfn(pfn)) |
2501 | return kvm_handle_bad_page(vcpu->kvm, gfn, pfn); | |
fb72d167 | 2502 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2503 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2504 | goto out_unlock; | |
fb72d167 JR |
2505 | kvm_mmu_free_some_pages(vcpu); |
2506 | r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK, | |
852e3c19 | 2507 | level, gfn, pfn); |
fb72d167 | 2508 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
2509 | |
2510 | return r; | |
e930bffe AA |
2511 | |
2512 | out_unlock: | |
2513 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2514 | kvm_release_pfn_clean(pfn); | |
2515 | return 0; | |
fb72d167 JR |
2516 | } |
2517 | ||
6aa8b732 AK |
2518 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
2519 | { | |
17ac10ad | 2520 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2521 | } |
2522 | ||
2523 | static int nonpaging_init_context(struct kvm_vcpu *vcpu) | |
2524 | { | |
ad312c7c | 2525 | struct kvm_mmu *context = &vcpu->arch.mmu; |
6aa8b732 AK |
2526 | |
2527 | context->new_cr3 = nonpaging_new_cr3; | |
2528 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
2529 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
2530 | context->free = nonpaging_free; | |
c7addb90 | 2531 | context->prefetch_page = nonpaging_prefetch_page; |
e8bc217a | 2532 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2533 | context->invlpg = nonpaging_invlpg; |
cea0f0e7 | 2534 | context->root_level = 0; |
6aa8b732 | 2535 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 2536 | context->root_hpa = INVALID_PAGE; |
6aa8b732 AK |
2537 | return 0; |
2538 | } | |
2539 | ||
d835dfec | 2540 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 2541 | { |
1165f5fe | 2542 | ++vcpu->stat.tlb_flush; |
a8eeb04a | 2543 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
6aa8b732 AK |
2544 | } |
2545 | ||
2546 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
2547 | { | |
b8688d51 | 2548 | pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3); |
cea0f0e7 | 2549 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2550 | } |
2551 | ||
6aa8b732 AK |
2552 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
2553 | u64 addr, | |
2554 | u32 err_code) | |
2555 | { | |
c3c91fee | 2556 | kvm_inject_page_fault(vcpu, addr, err_code); |
6aa8b732 AK |
2557 | } |
2558 | ||
6aa8b732 AK |
2559 | static void paging_free(struct kvm_vcpu *vcpu) |
2560 | { | |
2561 | nonpaging_free(vcpu); | |
2562 | } | |
2563 | ||
82725b20 DE |
2564 | static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level) |
2565 | { | |
2566 | int bit7; | |
2567 | ||
2568 | bit7 = (gpte >> 7) & 1; | |
2569 | return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0; | |
2570 | } | |
2571 | ||
6aa8b732 AK |
2572 | #define PTTYPE 64 |
2573 | #include "paging_tmpl.h" | |
2574 | #undef PTTYPE | |
2575 | ||
2576 | #define PTTYPE 32 | |
2577 | #include "paging_tmpl.h" | |
2578 | #undef PTTYPE | |
2579 | ||
82725b20 DE |
2580 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level) |
2581 | { | |
2582 | struct kvm_mmu *context = &vcpu->arch.mmu; | |
2583 | int maxphyaddr = cpuid_maxphyaddr(vcpu); | |
2584 | u64 exb_bit_rsvd = 0; | |
2585 | ||
2586 | if (!is_nx(vcpu)) | |
2587 | exb_bit_rsvd = rsvd_bits(63, 63); | |
2588 | switch (level) { | |
2589 | case PT32_ROOT_LEVEL: | |
2590 | /* no rsvd bits for 2 level 4K page table entries */ | |
2591 | context->rsvd_bits_mask[0][1] = 0; | |
2592 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
2593 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
2594 | ||
2595 | if (!is_pse(vcpu)) { | |
2596 | context->rsvd_bits_mask[1][1] = 0; | |
2597 | break; | |
2598 | } | |
2599 | ||
82725b20 DE |
2600 | if (is_cpuid_PSE36()) |
2601 | /* 36bits PSE 4MB page */ | |
2602 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
2603 | else | |
2604 | /* 32 bits PSE 4MB page */ | |
2605 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
2606 | break; |
2607 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
2608 | context->rsvd_bits_mask[0][2] = |
2609 | rsvd_bits(maxphyaddr, 63) | | |
2610 | rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ | |
82725b20 | 2611 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 2612 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
2613 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2614 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
2615 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
2616 | rsvd_bits(maxphyaddr, 62) | | |
2617 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2618 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2619 | break; |
2620 | case PT64_ROOT_LEVEL: | |
2621 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
2622 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2623 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | | |
2624 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2625 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | | |
4c26b4cd | 2626 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
2627 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2628 | rsvd_bits(maxphyaddr, 51); | |
2629 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 JR |
2630 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
2631 | rsvd_bits(maxphyaddr, 51) | | |
2632 | rsvd_bits(13, 29); | |
82725b20 | 2633 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
2634 | rsvd_bits(maxphyaddr, 51) | |
2635 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2636 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2637 | break; |
2638 | } | |
2639 | } | |
2640 | ||
17ac10ad | 2641 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level) |
6aa8b732 | 2642 | { |
ad312c7c | 2643 | struct kvm_mmu *context = &vcpu->arch.mmu; |
6aa8b732 AK |
2644 | |
2645 | ASSERT(is_pae(vcpu)); | |
2646 | context->new_cr3 = paging_new_cr3; | |
2647 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 2648 | context->gva_to_gpa = paging64_gva_to_gpa; |
c7addb90 | 2649 | context->prefetch_page = paging64_prefetch_page; |
e8bc217a | 2650 | context->sync_page = paging64_sync_page; |
a7052897 | 2651 | context->invlpg = paging64_invlpg; |
6aa8b732 | 2652 | context->free = paging_free; |
17ac10ad AK |
2653 | context->root_level = level; |
2654 | context->shadow_root_level = level; | |
17c3ba9d | 2655 | context->root_hpa = INVALID_PAGE; |
6aa8b732 AK |
2656 | return 0; |
2657 | } | |
2658 | ||
17ac10ad AK |
2659 | static int paging64_init_context(struct kvm_vcpu *vcpu) |
2660 | { | |
82725b20 | 2661 | reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL); |
17ac10ad AK |
2662 | return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL); |
2663 | } | |
2664 | ||
6aa8b732 AK |
2665 | static int paging32_init_context(struct kvm_vcpu *vcpu) |
2666 | { | |
ad312c7c | 2667 | struct kvm_mmu *context = &vcpu->arch.mmu; |
6aa8b732 | 2668 | |
82725b20 | 2669 | reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL); |
6aa8b732 AK |
2670 | context->new_cr3 = paging_new_cr3; |
2671 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
2672 | context->gva_to_gpa = paging32_gva_to_gpa; |
2673 | context->free = paging_free; | |
c7addb90 | 2674 | context->prefetch_page = paging32_prefetch_page; |
e8bc217a | 2675 | context->sync_page = paging32_sync_page; |
a7052897 | 2676 | context->invlpg = paging32_invlpg; |
6aa8b732 AK |
2677 | context->root_level = PT32_ROOT_LEVEL; |
2678 | context->shadow_root_level = PT32E_ROOT_LEVEL; | |
17c3ba9d | 2679 | context->root_hpa = INVALID_PAGE; |
6aa8b732 AK |
2680 | return 0; |
2681 | } | |
2682 | ||
2683 | static int paging32E_init_context(struct kvm_vcpu *vcpu) | |
2684 | { | |
82725b20 | 2685 | reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL); |
17ac10ad | 2686 | return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
2687 | } |
2688 | ||
fb72d167 JR |
2689 | static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
2690 | { | |
2691 | struct kvm_mmu *context = &vcpu->arch.mmu; | |
2692 | ||
2693 | context->new_cr3 = nonpaging_new_cr3; | |
2694 | context->page_fault = tdp_page_fault; | |
2695 | context->free = nonpaging_free; | |
2696 | context->prefetch_page = nonpaging_prefetch_page; | |
e8bc217a | 2697 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2698 | context->invlpg = nonpaging_invlpg; |
67253af5 | 2699 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 JR |
2700 | context->root_hpa = INVALID_PAGE; |
2701 | ||
2702 | if (!is_paging(vcpu)) { | |
2703 | context->gva_to_gpa = nonpaging_gva_to_gpa; | |
2704 | context->root_level = 0; | |
2705 | } else if (is_long_mode(vcpu)) { | |
82725b20 | 2706 | reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL); |
fb72d167 JR |
2707 | context->gva_to_gpa = paging64_gva_to_gpa; |
2708 | context->root_level = PT64_ROOT_LEVEL; | |
2709 | } else if (is_pae(vcpu)) { | |
82725b20 | 2710 | reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL); |
fb72d167 JR |
2711 | context->gva_to_gpa = paging64_gva_to_gpa; |
2712 | context->root_level = PT32E_ROOT_LEVEL; | |
2713 | } else { | |
82725b20 | 2714 | reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL); |
fb72d167 JR |
2715 | context->gva_to_gpa = paging32_gva_to_gpa; |
2716 | context->root_level = PT32_ROOT_LEVEL; | |
2717 | } | |
2718 | ||
2719 | return 0; | |
2720 | } | |
2721 | ||
2722 | static int init_kvm_softmmu(struct kvm_vcpu *vcpu) | |
6aa8b732 | 2723 | { |
a770f6f2 AK |
2724 | int r; |
2725 | ||
6aa8b732 | 2726 | ASSERT(vcpu); |
ad312c7c | 2727 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
2728 | |
2729 | if (!is_paging(vcpu)) | |
a770f6f2 | 2730 | r = nonpaging_init_context(vcpu); |
a9058ecd | 2731 | else if (is_long_mode(vcpu)) |
a770f6f2 | 2732 | r = paging64_init_context(vcpu); |
6aa8b732 | 2733 | else if (is_pae(vcpu)) |
a770f6f2 | 2734 | r = paging32E_init_context(vcpu); |
6aa8b732 | 2735 | else |
a770f6f2 AK |
2736 | r = paging32_init_context(vcpu); |
2737 | ||
5b7e0102 | 2738 | vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu); |
3dbe1415 | 2739 | vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu); |
a770f6f2 AK |
2740 | |
2741 | return r; | |
6aa8b732 AK |
2742 | } |
2743 | ||
fb72d167 JR |
2744 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) |
2745 | { | |
35149e21 AL |
2746 | vcpu->arch.update_pte.pfn = bad_pfn; |
2747 | ||
fb72d167 JR |
2748 | if (tdp_enabled) |
2749 | return init_kvm_tdp_mmu(vcpu); | |
2750 | else | |
2751 | return init_kvm_softmmu(vcpu); | |
2752 | } | |
2753 | ||
6aa8b732 AK |
2754 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) |
2755 | { | |
2756 | ASSERT(vcpu); | |
62ad0755 SY |
2757 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2758 | /* mmu.free() should set root_hpa = INVALID_PAGE */ | |
ad312c7c | 2759 | vcpu->arch.mmu.free(vcpu); |
6aa8b732 AK |
2760 | } |
2761 | ||
2762 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
2763 | { |
2764 | destroy_kvm_mmu(vcpu); | |
2765 | return init_kvm_mmu(vcpu); | |
2766 | } | |
8668a3c4 | 2767 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
2768 | |
2769 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 2770 | { |
714b93da AK |
2771 | int r; |
2772 | ||
e2dec939 | 2773 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
2774 | if (r) |
2775 | goto out; | |
8986ecc0 | 2776 | r = mmu_alloc_roots(vcpu); |
8facbbff | 2777 | spin_lock(&vcpu->kvm->mmu_lock); |
0ba73cda | 2778 | mmu_sync_roots(vcpu); |
aaee2c94 | 2779 | spin_unlock(&vcpu->kvm->mmu_lock); |
8986ecc0 MT |
2780 | if (r) |
2781 | goto out; | |
3662cb1c | 2782 | /* set_cr3() should ensure TLB has been flushed */ |
ad312c7c | 2783 | kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
2784 | out: |
2785 | return r; | |
6aa8b732 | 2786 | } |
17c3ba9d AK |
2787 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
2788 | ||
2789 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
2790 | { | |
2791 | mmu_free_roots(vcpu); | |
2792 | } | |
6aa8b732 | 2793 | |
09072daf | 2794 | static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu, |
4db35314 | 2795 | struct kvm_mmu_page *sp, |
ac1b714e AK |
2796 | u64 *spte) |
2797 | { | |
2798 | u64 pte; | |
2799 | struct kvm_mmu_page *child; | |
2800 | ||
2801 | pte = *spte; | |
c7addb90 | 2802 | if (is_shadow_present_pte(pte)) { |
776e6633 | 2803 | if (is_last_spte(pte, sp->role.level)) |
be38d276 | 2804 | drop_spte(vcpu->kvm, spte, shadow_trap_nonpresent_pte); |
ac1b714e AK |
2805 | else { |
2806 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
90cb0529 | 2807 | mmu_page_remove_parent_pte(child, spte); |
ac1b714e AK |
2808 | } |
2809 | } | |
d555c333 | 2810 | __set_spte(spte, shadow_trap_nonpresent_pte); |
05da4558 MT |
2811 | if (is_large_pte(pte)) |
2812 | --vcpu->kvm->stat.lpages; | |
ac1b714e AK |
2813 | } |
2814 | ||
0028425f | 2815 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
4db35314 | 2816 | struct kvm_mmu_page *sp, |
0028425f | 2817 | u64 *spte, |
489f1d65 | 2818 | const void *new) |
0028425f | 2819 | { |
30945387 | 2820 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
2821 | ++vcpu->kvm->stat.mmu_pde_zapped; |
2822 | return; | |
30945387 | 2823 | } |
0028425f | 2824 | |
fa1de2bf XG |
2825 | if (is_rsvd_bits_set(vcpu, *(u64 *)new, PT_PAGE_TABLE_LEVEL)) |
2826 | return; | |
2827 | ||
4cee5764 | 2828 | ++vcpu->kvm->stat.mmu_pte_updated; |
5b7e0102 | 2829 | if (!sp->role.cr4_pae) |
489f1d65 | 2830 | paging32_update_pte(vcpu, sp, spte, new); |
0028425f | 2831 | else |
489f1d65 | 2832 | paging64_update_pte(vcpu, sp, spte, new); |
0028425f AK |
2833 | } |
2834 | ||
79539cec AK |
2835 | static bool need_remote_flush(u64 old, u64 new) |
2836 | { | |
2837 | if (!is_shadow_present_pte(old)) | |
2838 | return false; | |
2839 | if (!is_shadow_present_pte(new)) | |
2840 | return true; | |
2841 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
2842 | return true; | |
2843 | old ^= PT64_NX_MASK; | |
2844 | new ^= PT64_NX_MASK; | |
2845 | return (old & ~new & PT64_PERM_MASK) != 0; | |
2846 | } | |
2847 | ||
0671a8e7 XG |
2848 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
2849 | bool remote_flush, bool local_flush) | |
79539cec | 2850 | { |
0671a8e7 XG |
2851 | if (zap_page) |
2852 | return; | |
2853 | ||
2854 | if (remote_flush) | |
79539cec | 2855 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 2856 | else if (local_flush) |
79539cec AK |
2857 | kvm_mmu_flush_tlb(vcpu); |
2858 | } | |
2859 | ||
12b7d28f AK |
2860 | static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu) |
2861 | { | |
ad312c7c | 2862 | u64 *spte = vcpu->arch.last_pte_updated; |
12b7d28f | 2863 | |
7b52345e | 2864 | return !!(spte && (*spte & shadow_accessed_mask)); |
12b7d28f AK |
2865 | } |
2866 | ||
d7824fff | 2867 | static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
72016f3a | 2868 | u64 gpte) |
d7824fff AK |
2869 | { |
2870 | gfn_t gfn; | |
35149e21 | 2871 | pfn_t pfn; |
d7824fff | 2872 | |
43a3795a | 2873 | if (!is_present_gpte(gpte)) |
d7824fff AK |
2874 | return; |
2875 | gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; | |
72dc67a6 | 2876 | |
e930bffe | 2877 | vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2878 | smp_rmb(); |
35149e21 | 2879 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
72dc67a6 | 2880 | |
35149e21 AL |
2881 | if (is_error_pfn(pfn)) { |
2882 | kvm_release_pfn_clean(pfn); | |
d196e343 AK |
2883 | return; |
2884 | } | |
d7824fff | 2885 | vcpu->arch.update_pte.gfn = gfn; |
35149e21 | 2886 | vcpu->arch.update_pte.pfn = pfn; |
d7824fff AK |
2887 | } |
2888 | ||
1b7fcd32 AK |
2889 | static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn) |
2890 | { | |
2891 | u64 *spte = vcpu->arch.last_pte_updated; | |
2892 | ||
2893 | if (spte | |
2894 | && vcpu->arch.last_pte_gfn == gfn | |
2895 | && shadow_accessed_mask | |
2896 | && !(*spte & shadow_accessed_mask) | |
2897 | && is_shadow_present_pte(*spte)) | |
2898 | set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
2899 | } | |
2900 | ||
09072daf | 2901 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
ad218f85 MT |
2902 | const u8 *new, int bytes, |
2903 | bool guest_initiated) | |
da4a00f0 | 2904 | { |
9b7a0325 | 2905 | gfn_t gfn = gpa >> PAGE_SHIFT; |
fa1de2bf | 2906 | union kvm_mmu_page_role mask = { .word = 0 }; |
4db35314 | 2907 | struct kvm_mmu_page *sp; |
f41d335a | 2908 | struct hlist_node *node; |
d98ba053 | 2909 | LIST_HEAD(invalid_list); |
489f1d65 | 2910 | u64 entry, gentry; |
9b7a0325 | 2911 | u64 *spte; |
9b7a0325 | 2912 | unsigned offset = offset_in_page(gpa); |
0e7bc4b9 | 2913 | unsigned pte_size; |
9b7a0325 | 2914 | unsigned page_offset; |
0e7bc4b9 | 2915 | unsigned misaligned; |
fce0657f | 2916 | unsigned quadrant; |
9b7a0325 | 2917 | int level; |
86a5ba02 | 2918 | int flooded = 0; |
ac1b714e | 2919 | int npte; |
489f1d65 | 2920 | int r; |
08e850c6 | 2921 | int invlpg_counter; |
0671a8e7 XG |
2922 | bool remote_flush, local_flush, zap_page; |
2923 | ||
2924 | zap_page = remote_flush = local_flush = false; | |
9b7a0325 | 2925 | |
b8688d51 | 2926 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); |
72016f3a | 2927 | |
08e850c6 | 2928 | invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter); |
72016f3a AK |
2929 | |
2930 | /* | |
2931 | * Assume that the pte write on a page table of the same type | |
2932 | * as the current vcpu paging mode. This is nearly always true | |
2933 | * (might be false while changing modes). Note it is verified later | |
2934 | * by update_pte(). | |
2935 | */ | |
08e850c6 | 2936 | if ((is_pae(vcpu) && bytes == 4) || !new) { |
72016f3a | 2937 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
08e850c6 AK |
2938 | if (is_pae(vcpu)) { |
2939 | gpa &= ~(gpa_t)7; | |
2940 | bytes = 8; | |
2941 | } | |
2942 | r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8)); | |
72016f3a AK |
2943 | if (r) |
2944 | gentry = 0; | |
08e850c6 AK |
2945 | new = (const u8 *)&gentry; |
2946 | } | |
2947 | ||
2948 | switch (bytes) { | |
2949 | case 4: | |
2950 | gentry = *(const u32 *)new; | |
2951 | break; | |
2952 | case 8: | |
2953 | gentry = *(const u64 *)new; | |
2954 | break; | |
2955 | default: | |
2956 | gentry = 0; | |
2957 | break; | |
72016f3a AK |
2958 | } |
2959 | ||
2960 | mmu_guess_page_from_pte_write(vcpu, gpa, gentry); | |
aaee2c94 | 2961 | spin_lock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
2962 | if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter) |
2963 | gentry = 0; | |
1b7fcd32 | 2964 | kvm_mmu_access_page(vcpu, gfn); |
eb787d10 | 2965 | kvm_mmu_free_some_pages(vcpu); |
4cee5764 | 2966 | ++vcpu->kvm->stat.mmu_pte_write; |
c7addb90 | 2967 | kvm_mmu_audit(vcpu, "pre pte write"); |
ad218f85 MT |
2968 | if (guest_initiated) { |
2969 | if (gfn == vcpu->arch.last_pt_write_gfn | |
2970 | && !last_updated_pte_accessed(vcpu)) { | |
2971 | ++vcpu->arch.last_pt_write_count; | |
2972 | if (vcpu->arch.last_pt_write_count >= 3) | |
2973 | flooded = 1; | |
2974 | } else { | |
2975 | vcpu->arch.last_pt_write_gfn = gfn; | |
2976 | vcpu->arch.last_pt_write_count = 1; | |
2977 | vcpu->arch.last_pte_updated = NULL; | |
2978 | } | |
86a5ba02 | 2979 | } |
3246af0e | 2980 | |
fa1de2bf | 2981 | mask.cr0_wp = mask.cr4_pae = mask.nxe = 1; |
f41d335a | 2982 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) { |
5b7e0102 | 2983 | pte_size = sp->role.cr4_pae ? 8 : 4; |
0e7bc4b9 | 2984 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
e925c5ba | 2985 | misaligned |= bytes < 4; |
86a5ba02 | 2986 | if (misaligned || flooded) { |
0e7bc4b9 AK |
2987 | /* |
2988 | * Misaligned accesses are too much trouble to fix | |
2989 | * up; also, they usually indicate a page is not used | |
2990 | * as a page table. | |
86a5ba02 AK |
2991 | * |
2992 | * If we're seeing too many writes to a page, | |
2993 | * it may no longer be a page table, or we may be | |
2994 | * forking, in which case it is better to unmap the | |
2995 | * page. | |
0e7bc4b9 AK |
2996 | */ |
2997 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4db35314 | 2998 | gpa, bytes, sp->role.word); |
0671a8e7 | 2999 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 3000 | &invalid_list); |
4cee5764 | 3001 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
3002 | continue; |
3003 | } | |
9b7a0325 | 3004 | page_offset = offset; |
4db35314 | 3005 | level = sp->role.level; |
ac1b714e | 3006 | npte = 1; |
5b7e0102 | 3007 | if (!sp->role.cr4_pae) { |
ac1b714e AK |
3008 | page_offset <<= 1; /* 32->64 */ |
3009 | /* | |
3010 | * A 32-bit pde maps 4MB while the shadow pdes map | |
3011 | * only 2MB. So we need to double the offset again | |
3012 | * and zap two pdes instead of one. | |
3013 | */ | |
3014 | if (level == PT32_ROOT_LEVEL) { | |
6b8d0f9b | 3015 | page_offset &= ~7; /* kill rounding error */ |
ac1b714e AK |
3016 | page_offset <<= 1; |
3017 | npte = 2; | |
3018 | } | |
fce0657f | 3019 | quadrant = page_offset >> PAGE_SHIFT; |
9b7a0325 | 3020 | page_offset &= ~PAGE_MASK; |
4db35314 | 3021 | if (quadrant != sp->role.quadrant) |
fce0657f | 3022 | continue; |
9b7a0325 | 3023 | } |
0671a8e7 | 3024 | local_flush = true; |
4db35314 | 3025 | spte = &sp->spt[page_offset / sizeof(*spte)]; |
ac1b714e | 3026 | while (npte--) { |
79539cec | 3027 | entry = *spte; |
4db35314 | 3028 | mmu_pte_write_zap_pte(vcpu, sp, spte); |
fa1de2bf XG |
3029 | if (gentry && |
3030 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
3031 | & mask.word)) | |
72016f3a | 3032 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
0671a8e7 XG |
3033 | if (!remote_flush && need_remote_flush(entry, *spte)) |
3034 | remote_flush = true; | |
ac1b714e | 3035 | ++spte; |
9b7a0325 | 3036 | } |
9b7a0325 | 3037 | } |
0671a8e7 | 3038 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 3039 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
c7addb90 | 3040 | kvm_mmu_audit(vcpu, "post pte write"); |
aaee2c94 | 3041 | spin_unlock(&vcpu->kvm->mmu_lock); |
35149e21 AL |
3042 | if (!is_error_pfn(vcpu->arch.update_pte.pfn)) { |
3043 | kvm_release_pfn_clean(vcpu->arch.update_pte.pfn); | |
3044 | vcpu->arch.update_pte.pfn = bad_pfn; | |
d7824fff | 3045 | } |
da4a00f0 AK |
3046 | } |
3047 | ||
a436036b AK |
3048 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
3049 | { | |
10589a46 MT |
3050 | gpa_t gpa; |
3051 | int r; | |
a436036b | 3052 | |
60f24784 AK |
3053 | if (tdp_enabled) |
3054 | return 0; | |
3055 | ||
1871c602 | 3056 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 3057 | |
aaee2c94 | 3058 | spin_lock(&vcpu->kvm->mmu_lock); |
10589a46 | 3059 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
aaee2c94 | 3060 | spin_unlock(&vcpu->kvm->mmu_lock); |
10589a46 | 3061 | return r; |
a436036b | 3062 | } |
577bdc49 | 3063 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 3064 | |
22d95b12 | 3065 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu) |
ebeace86 | 3066 | { |
d98ba053 | 3067 | LIST_HEAD(invalid_list); |
103ad25a | 3068 | |
e0df7b9f | 3069 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES && |
3b80fffe | 3070 | !list_empty(&vcpu->kvm->arch.active_mmu_pages)) { |
4db35314 | 3071 | struct kvm_mmu_page *sp; |
ebeace86 | 3072 | |
f05e70ac | 3073 | sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev, |
4db35314 | 3074 | struct kvm_mmu_page, link); |
e0df7b9f | 3075 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
80b63faf | 3076 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4cee5764 | 3077 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 AK |
3078 | } |
3079 | } | |
ebeace86 | 3080 | |
3067714c AK |
3081 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code) |
3082 | { | |
3083 | int r; | |
3084 | enum emulation_result er; | |
3085 | ||
ad312c7c | 3086 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code); |
3067714c AK |
3087 | if (r < 0) |
3088 | goto out; | |
3089 | ||
3090 | if (!r) { | |
3091 | r = 1; | |
3092 | goto out; | |
3093 | } | |
3094 | ||
b733bfb5 AK |
3095 | r = mmu_topup_memory_caches(vcpu); |
3096 | if (r) | |
3097 | goto out; | |
3098 | ||
851ba692 | 3099 | er = emulate_instruction(vcpu, cr2, error_code, 0); |
3067714c AK |
3100 | |
3101 | switch (er) { | |
3102 | case EMULATE_DONE: | |
3103 | return 1; | |
3104 | case EMULATE_DO_MMIO: | |
3105 | ++vcpu->stat.mmio_exits; | |
6d77dbfc | 3106 | /* fall through */ |
3067714c | 3107 | case EMULATE_FAIL: |
3f5d18a9 | 3108 | return 0; |
3067714c AK |
3109 | default: |
3110 | BUG(); | |
3111 | } | |
3112 | out: | |
3067714c AK |
3113 | return r; |
3114 | } | |
3115 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
3116 | ||
a7052897 MT |
3117 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
3118 | { | |
a7052897 | 3119 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
3120 | kvm_mmu_flush_tlb(vcpu); |
3121 | ++vcpu->stat.invlpg; | |
3122 | } | |
3123 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
3124 | ||
18552672 JR |
3125 | void kvm_enable_tdp(void) |
3126 | { | |
3127 | tdp_enabled = true; | |
3128 | } | |
3129 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
3130 | ||
5f4cb662 JR |
3131 | void kvm_disable_tdp(void) |
3132 | { | |
3133 | tdp_enabled = false; | |
3134 | } | |
3135 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
3136 | ||
6aa8b732 AK |
3137 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
3138 | { | |
ad312c7c | 3139 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
6aa8b732 AK |
3140 | } |
3141 | ||
3142 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
3143 | { | |
17ac10ad | 3144 | struct page *page; |
6aa8b732 AK |
3145 | int i; |
3146 | ||
3147 | ASSERT(vcpu); | |
3148 | ||
17ac10ad AK |
3149 | /* |
3150 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
3151 | * Therefore we need to allocate shadow page tables in the first | |
3152 | * 4GB of memory, which happens to fit the DMA32 zone. | |
3153 | */ | |
3154 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
3155 | if (!page) | |
d7fa6ab2 WY |
3156 | return -ENOMEM; |
3157 | ||
ad312c7c | 3158 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 3159 | for (i = 0; i < 4; ++i) |
ad312c7c | 3160 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 3161 | |
6aa8b732 | 3162 | return 0; |
6aa8b732 AK |
3163 | } |
3164 | ||
8018c27b | 3165 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 3166 | { |
6aa8b732 | 3167 | ASSERT(vcpu); |
ad312c7c | 3168 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3169 | |
8018c27b IM |
3170 | return alloc_mmu_pages(vcpu); |
3171 | } | |
6aa8b732 | 3172 | |
8018c27b IM |
3173 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
3174 | { | |
3175 | ASSERT(vcpu); | |
ad312c7c | 3176 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 3177 | |
8018c27b | 3178 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
3179 | } |
3180 | ||
3181 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) | |
3182 | { | |
3183 | ASSERT(vcpu); | |
3184 | ||
3185 | destroy_kvm_mmu(vcpu); | |
3186 | free_mmu_pages(vcpu); | |
714b93da | 3187 | mmu_free_memory_caches(vcpu); |
6aa8b732 AK |
3188 | } |
3189 | ||
90cb0529 | 3190 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 3191 | { |
4db35314 | 3192 | struct kvm_mmu_page *sp; |
6aa8b732 | 3193 | |
f05e70ac | 3194 | list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) { |
6aa8b732 AK |
3195 | int i; |
3196 | u64 *pt; | |
3197 | ||
291f26bc | 3198 | if (!test_bit(slot, sp->slot_bitmap)) |
6aa8b732 AK |
3199 | continue; |
3200 | ||
4db35314 | 3201 | pt = sp->spt; |
6aa8b732 AK |
3202 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
3203 | /* avoid RMW */ | |
01c168ac | 3204 | if (is_writable_pte(pt[i])) |
6aa8b732 | 3205 | pt[i] &= ~PT_WRITABLE_MASK; |
6aa8b732 | 3206 | } |
171d595d | 3207 | kvm_flush_remote_tlbs(kvm); |
6aa8b732 | 3208 | } |
37a7d8b0 | 3209 | |
90cb0529 | 3210 | void kvm_mmu_zap_all(struct kvm *kvm) |
e0fa826f | 3211 | { |
4db35314 | 3212 | struct kvm_mmu_page *sp, *node; |
d98ba053 | 3213 | LIST_HEAD(invalid_list); |
e0fa826f | 3214 | |
aaee2c94 | 3215 | spin_lock(&kvm->mmu_lock); |
3246af0e | 3216 | restart: |
f05e70ac | 3217 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) |
d98ba053 | 3218 | if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list)) |
3246af0e XG |
3219 | goto restart; |
3220 | ||
d98ba053 | 3221 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
aaee2c94 | 3222 | spin_unlock(&kvm->mmu_lock); |
e0fa826f DL |
3223 | } |
3224 | ||
d98ba053 XG |
3225 | static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm, |
3226 | struct list_head *invalid_list) | |
3ee16c81 IE |
3227 | { |
3228 | struct kvm_mmu_page *page; | |
3229 | ||
3230 | page = container_of(kvm->arch.active_mmu_pages.prev, | |
3231 | struct kvm_mmu_page, link); | |
d98ba053 | 3232 | return kvm_mmu_prepare_zap_page(kvm, page, invalid_list); |
3ee16c81 IE |
3233 | } |
3234 | ||
7f8275d0 | 3235 | static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
3ee16c81 IE |
3236 | { |
3237 | struct kvm *kvm; | |
3238 | struct kvm *kvm_freed = NULL; | |
45221ab6 DH |
3239 | |
3240 | if (nr_to_scan == 0) | |
3241 | goto out; | |
3ee16c81 IE |
3242 | |
3243 | spin_lock(&kvm_lock); | |
3244 | ||
3245 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
45221ab6 | 3246 | int idx, freed_pages; |
d98ba053 | 3247 | LIST_HEAD(invalid_list); |
3ee16c81 | 3248 | |
f656ce01 | 3249 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 3250 | spin_lock(&kvm->mmu_lock); |
45221ab6 DH |
3251 | if (!kvm_freed && nr_to_scan > 0 && |
3252 | kvm->arch.n_used_mmu_pages > 0) { | |
d98ba053 XG |
3253 | freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm, |
3254 | &invalid_list); | |
3ee16c81 IE |
3255 | kvm_freed = kvm; |
3256 | } | |
3257 | nr_to_scan--; | |
3258 | ||
d98ba053 | 3259 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
3ee16c81 | 3260 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 3261 | srcu_read_unlock(&kvm->srcu, idx); |
3ee16c81 IE |
3262 | } |
3263 | if (kvm_freed) | |
3264 | list_move_tail(&kvm_freed->vm_list, &vm_list); | |
3265 | ||
3266 | spin_unlock(&kvm_lock); | |
3267 | ||
45221ab6 DH |
3268 | out: |
3269 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); | |
3ee16c81 IE |
3270 | } |
3271 | ||
3272 | static struct shrinker mmu_shrinker = { | |
3273 | .shrink = mmu_shrink, | |
3274 | .seeks = DEFAULT_SEEKS * 10, | |
3275 | }; | |
3276 | ||
2ddfd20e | 3277 | static void mmu_destroy_caches(void) |
b5a33a75 AK |
3278 | { |
3279 | if (pte_chain_cache) | |
3280 | kmem_cache_destroy(pte_chain_cache); | |
3281 | if (rmap_desc_cache) | |
3282 | kmem_cache_destroy(rmap_desc_cache); | |
d3d25b04 AK |
3283 | if (mmu_page_header_cache) |
3284 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
3285 | } |
3286 | ||
3ee16c81 IE |
3287 | void kvm_mmu_module_exit(void) |
3288 | { | |
3289 | mmu_destroy_caches(); | |
45bf21a8 | 3290 | percpu_counter_destroy(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
3291 | unregister_shrinker(&mmu_shrinker); |
3292 | } | |
3293 | ||
b5a33a75 AK |
3294 | int kvm_mmu_module_init(void) |
3295 | { | |
3296 | pte_chain_cache = kmem_cache_create("kvm_pte_chain", | |
3297 | sizeof(struct kvm_pte_chain), | |
20c2df83 | 3298 | 0, 0, NULL); |
b5a33a75 AK |
3299 | if (!pte_chain_cache) |
3300 | goto nomem; | |
3301 | rmap_desc_cache = kmem_cache_create("kvm_rmap_desc", | |
3302 | sizeof(struct kvm_rmap_desc), | |
20c2df83 | 3303 | 0, 0, NULL); |
b5a33a75 AK |
3304 | if (!rmap_desc_cache) |
3305 | goto nomem; | |
3306 | ||
d3d25b04 AK |
3307 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
3308 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 3309 | 0, 0, NULL); |
d3d25b04 AK |
3310 | if (!mmu_page_header_cache) |
3311 | goto nomem; | |
3312 | ||
45bf21a8 WY |
3313 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0)) |
3314 | goto nomem; | |
3315 | ||
3ee16c81 IE |
3316 | register_shrinker(&mmu_shrinker); |
3317 | ||
b5a33a75 AK |
3318 | return 0; |
3319 | ||
3320 | nomem: | |
3ee16c81 | 3321 | mmu_destroy_caches(); |
b5a33a75 AK |
3322 | return -ENOMEM; |
3323 | } | |
3324 | ||
3ad82a7e ZX |
3325 | /* |
3326 | * Caculate mmu pages needed for kvm. | |
3327 | */ | |
3328 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
3329 | { | |
3330 | int i; | |
3331 | unsigned int nr_mmu_pages; | |
3332 | unsigned int nr_pages = 0; | |
bc6678a3 | 3333 | struct kvm_memslots *slots; |
3ad82a7e | 3334 | |
90d83dc3 LJ |
3335 | slots = kvm_memslots(kvm); |
3336 | ||
bc6678a3 MT |
3337 | for (i = 0; i < slots->nmemslots; i++) |
3338 | nr_pages += slots->memslots[i].npages; | |
3ad82a7e ZX |
3339 | |
3340 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
3341 | nr_mmu_pages = max(nr_mmu_pages, | |
3342 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
3343 | ||
3344 | return nr_mmu_pages; | |
3345 | } | |
3346 | ||
2f333bcb MT |
3347 | static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer, |
3348 | unsigned len) | |
3349 | { | |
3350 | if (len > buffer->len) | |
3351 | return NULL; | |
3352 | return buffer->ptr; | |
3353 | } | |
3354 | ||
3355 | static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer, | |
3356 | unsigned len) | |
3357 | { | |
3358 | void *ret; | |
3359 | ||
3360 | ret = pv_mmu_peek_buffer(buffer, len); | |
3361 | if (!ret) | |
3362 | return ret; | |
3363 | buffer->ptr += len; | |
3364 | buffer->len -= len; | |
3365 | buffer->processed += len; | |
3366 | return ret; | |
3367 | } | |
3368 | ||
3369 | static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu, | |
3370 | gpa_t addr, gpa_t value) | |
3371 | { | |
3372 | int bytes = 8; | |
3373 | int r; | |
3374 | ||
3375 | if (!is_long_mode(vcpu) && !is_pae(vcpu)) | |
3376 | bytes = 4; | |
3377 | ||
3378 | r = mmu_topup_memory_caches(vcpu); | |
3379 | if (r) | |
3380 | return r; | |
3381 | ||
3200f405 | 3382 | if (!emulator_write_phys(vcpu, addr, &value, bytes)) |
2f333bcb MT |
3383 | return -EFAULT; |
3384 | ||
3385 | return 1; | |
3386 | } | |
3387 | ||
3388 | static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu) | |
3389 | { | |
2390218b | 3390 | (void)kvm_set_cr3(vcpu, vcpu->arch.cr3); |
2f333bcb MT |
3391 | return 1; |
3392 | } | |
3393 | ||
3394 | static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr) | |
3395 | { | |
3396 | spin_lock(&vcpu->kvm->mmu_lock); | |
3397 | mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT); | |
3398 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3399 | return 1; | |
3400 | } | |
3401 | ||
3402 | static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu, | |
3403 | struct kvm_pv_mmu_op_buffer *buffer) | |
3404 | { | |
3405 | struct kvm_mmu_op_header *header; | |
3406 | ||
3407 | header = pv_mmu_peek_buffer(buffer, sizeof *header); | |
3408 | if (!header) | |
3409 | return 0; | |
3410 | switch (header->op) { | |
3411 | case KVM_MMU_OP_WRITE_PTE: { | |
3412 | struct kvm_mmu_op_write_pte *wpte; | |
3413 | ||
3414 | wpte = pv_mmu_read_buffer(buffer, sizeof *wpte); | |
3415 | if (!wpte) | |
3416 | return 0; | |
3417 | return kvm_pv_mmu_write(vcpu, wpte->pte_phys, | |
3418 | wpte->pte_val); | |
3419 | } | |
3420 | case KVM_MMU_OP_FLUSH_TLB: { | |
3421 | struct kvm_mmu_op_flush_tlb *ftlb; | |
3422 | ||
3423 | ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb); | |
3424 | if (!ftlb) | |
3425 | return 0; | |
3426 | return kvm_pv_mmu_flush_tlb(vcpu); | |
3427 | } | |
3428 | case KVM_MMU_OP_RELEASE_PT: { | |
3429 | struct kvm_mmu_op_release_pt *rpt; | |
3430 | ||
3431 | rpt = pv_mmu_read_buffer(buffer, sizeof *rpt); | |
3432 | if (!rpt) | |
3433 | return 0; | |
3434 | return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys); | |
3435 | } | |
3436 | default: return 0; | |
3437 | } | |
3438 | } | |
3439 | ||
3440 | int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes, | |
3441 | gpa_t addr, unsigned long *ret) | |
3442 | { | |
3443 | int r; | |
6ad18fba | 3444 | struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer; |
2f333bcb | 3445 | |
6ad18fba DH |
3446 | buffer->ptr = buffer->buf; |
3447 | buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf); | |
3448 | buffer->processed = 0; | |
2f333bcb | 3449 | |
6ad18fba | 3450 | r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len); |
2f333bcb MT |
3451 | if (r) |
3452 | goto out; | |
3453 | ||
6ad18fba DH |
3454 | while (buffer->len) { |
3455 | r = kvm_pv_mmu_op_one(vcpu, buffer); | |
2f333bcb MT |
3456 | if (r < 0) |
3457 | goto out; | |
3458 | if (r == 0) | |
3459 | break; | |
3460 | } | |
3461 | ||
3462 | r = 1; | |
3463 | out: | |
6ad18fba | 3464 | *ret = buffer->processed; |
2f333bcb MT |
3465 | return r; |
3466 | } | |
3467 | ||
94d8b056 MT |
3468 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
3469 | { | |
3470 | struct kvm_shadow_walk_iterator iterator; | |
3471 | int nr_sptes = 0; | |
3472 | ||
3473 | spin_lock(&vcpu->kvm->mmu_lock); | |
3474 | for_each_shadow_entry(vcpu, addr, iterator) { | |
3475 | sptes[iterator.level-1] = *iterator.sptep; | |
3476 | nr_sptes++; | |
3477 | if (!is_shadow_present_pte(*iterator.sptep)) | |
3478 | break; | |
3479 | } | |
3480 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3481 | ||
3482 | return nr_sptes; | |
3483 | } | |
3484 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
3485 | ||
37a7d8b0 AK |
3486 | #ifdef AUDIT |
3487 | ||
3488 | static const char *audit_msg; | |
3489 | ||
3490 | static gva_t canonicalize(gva_t gva) | |
3491 | { | |
3492 | #ifdef CONFIG_X86_64 | |
3493 | gva = (long long)(gva << 16) >> 16; | |
3494 | #endif | |
3495 | return gva; | |
3496 | } | |
3497 | ||
08a3732b | 3498 | |
805d32de | 3499 | typedef void (*inspect_spte_fn) (struct kvm *kvm, u64 *sptep); |
08a3732b MT |
3500 | |
3501 | static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp, | |
3502 | inspect_spte_fn fn) | |
3503 | { | |
3504 | int i; | |
3505 | ||
3506 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
3507 | u64 ent = sp->spt[i]; | |
3508 | ||
3509 | if (is_shadow_present_pte(ent)) { | |
2920d728 | 3510 | if (!is_last_spte(ent, sp->role.level)) { |
08a3732b MT |
3511 | struct kvm_mmu_page *child; |
3512 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
3513 | __mmu_spte_walk(kvm, child, fn); | |
2920d728 | 3514 | } else |
805d32de | 3515 | fn(kvm, &sp->spt[i]); |
08a3732b MT |
3516 | } |
3517 | } | |
3518 | } | |
3519 | ||
3520 | static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn) | |
3521 | { | |
3522 | int i; | |
3523 | struct kvm_mmu_page *sp; | |
3524 | ||
3525 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
3526 | return; | |
3527 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3528 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
3529 | sp = page_header(root); | |
3530 | __mmu_spte_walk(vcpu->kvm, sp, fn); | |
3531 | return; | |
3532 | } | |
3533 | for (i = 0; i < 4; ++i) { | |
3534 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3535 | ||
3536 | if (root && VALID_PAGE(root)) { | |
3537 | root &= PT64_BASE_ADDR_MASK; | |
3538 | sp = page_header(root); | |
3539 | __mmu_spte_walk(vcpu->kvm, sp, fn); | |
3540 | } | |
3541 | } | |
3542 | return; | |
3543 | } | |
3544 | ||
37a7d8b0 AK |
3545 | static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte, |
3546 | gva_t va, int level) | |
3547 | { | |
3548 | u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK); | |
3549 | int i; | |
3550 | gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1)); | |
3551 | ||
3552 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) { | |
3553 | u64 ent = pt[i]; | |
3554 | ||
c7addb90 | 3555 | if (ent == shadow_trap_nonpresent_pte) |
37a7d8b0 AK |
3556 | continue; |
3557 | ||
3558 | va = canonicalize(va); | |
2920d728 MT |
3559 | if (is_shadow_present_pte(ent) && !is_last_spte(ent, level)) |
3560 | audit_mappings_page(vcpu, ent, va, level - 1); | |
3561 | else { | |
1871c602 | 3562 | gpa_t gpa = kvm_mmu_gva_to_gpa_read(vcpu, va, NULL); |
34382539 JK |
3563 | gfn_t gfn = gpa >> PAGE_SHIFT; |
3564 | pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn); | |
3565 | hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT; | |
37a7d8b0 | 3566 | |
2aaf65e8 MT |
3567 | if (is_error_pfn(pfn)) { |
3568 | kvm_release_pfn_clean(pfn); | |
3569 | continue; | |
3570 | } | |
3571 | ||
c7addb90 | 3572 | if (is_shadow_present_pte(ent) |
37a7d8b0 | 3573 | && (ent & PT64_BASE_ADDR_MASK) != hpa) |
c7addb90 AK |
3574 | printk(KERN_ERR "xx audit error: (%s) levels %d" |
3575 | " gva %lx gpa %llx hpa %llx ent %llx %d\n", | |
ad312c7c | 3576 | audit_msg, vcpu->arch.mmu.root_level, |
d77c26fc MD |
3577 | va, gpa, hpa, ent, |
3578 | is_shadow_present_pte(ent)); | |
c7addb90 AK |
3579 | else if (ent == shadow_notrap_nonpresent_pte |
3580 | && !is_error_hpa(hpa)) | |
3581 | printk(KERN_ERR "audit: (%s) notrap shadow," | |
3582 | " valid guest gva %lx\n", audit_msg, va); | |
35149e21 | 3583 | kvm_release_pfn_clean(pfn); |
c7addb90 | 3584 | |
37a7d8b0 AK |
3585 | } |
3586 | } | |
3587 | } | |
3588 | ||
3589 | static void audit_mappings(struct kvm_vcpu *vcpu) | |
3590 | { | |
1ea252af | 3591 | unsigned i; |
37a7d8b0 | 3592 | |
ad312c7c ZX |
3593 | if (vcpu->arch.mmu.root_level == 4) |
3594 | audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4); | |
37a7d8b0 AK |
3595 | else |
3596 | for (i = 0; i < 4; ++i) | |
ad312c7c | 3597 | if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK) |
37a7d8b0 | 3598 | audit_mappings_page(vcpu, |
ad312c7c | 3599 | vcpu->arch.mmu.pae_root[i], |
37a7d8b0 AK |
3600 | i << 30, |
3601 | 2); | |
3602 | } | |
3603 | ||
3604 | static int count_rmaps(struct kvm_vcpu *vcpu) | |
3605 | { | |
805d32de XG |
3606 | struct kvm *kvm = vcpu->kvm; |
3607 | struct kvm_memslots *slots; | |
37a7d8b0 | 3608 | int nmaps = 0; |
bc6678a3 | 3609 | int i, j, k, idx; |
37a7d8b0 | 3610 | |
bc6678a3 | 3611 | idx = srcu_read_lock(&kvm->srcu); |
90d83dc3 | 3612 | slots = kvm_memslots(kvm); |
37a7d8b0 | 3613 | for (i = 0; i < KVM_MEMORY_SLOTS; ++i) { |
bc6678a3 | 3614 | struct kvm_memory_slot *m = &slots->memslots[i]; |
37a7d8b0 AK |
3615 | struct kvm_rmap_desc *d; |
3616 | ||
3617 | for (j = 0; j < m->npages; ++j) { | |
290fc38d | 3618 | unsigned long *rmapp = &m->rmap[j]; |
37a7d8b0 | 3619 | |
290fc38d | 3620 | if (!*rmapp) |
37a7d8b0 | 3621 | continue; |
290fc38d | 3622 | if (!(*rmapp & 1)) { |
37a7d8b0 AK |
3623 | ++nmaps; |
3624 | continue; | |
3625 | } | |
290fc38d | 3626 | d = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
37a7d8b0 AK |
3627 | while (d) { |
3628 | for (k = 0; k < RMAP_EXT; ++k) | |
d555c333 | 3629 | if (d->sptes[k]) |
37a7d8b0 AK |
3630 | ++nmaps; |
3631 | else | |
3632 | break; | |
3633 | d = d->more; | |
3634 | } | |
3635 | } | |
3636 | } | |
bc6678a3 | 3637 | srcu_read_unlock(&kvm->srcu, idx); |
37a7d8b0 AK |
3638 | return nmaps; |
3639 | } | |
3640 | ||
805d32de | 3641 | void inspect_spte_has_rmap(struct kvm *kvm, u64 *sptep) |
08a3732b MT |
3642 | { |
3643 | unsigned long *rmapp; | |
3644 | struct kvm_mmu_page *rev_sp; | |
3645 | gfn_t gfn; | |
3646 | ||
01c168ac | 3647 | if (is_writable_pte(*sptep)) { |
08a3732b | 3648 | rev_sp = page_header(__pa(sptep)); |
2032a93d | 3649 | gfn = kvm_mmu_page_get_gfn(rev_sp, sptep - rev_sp->spt); |
08a3732b MT |
3650 | |
3651 | if (!gfn_to_memslot(kvm, gfn)) { | |
3652 | if (!printk_ratelimit()) | |
3653 | return; | |
3654 | printk(KERN_ERR "%s: no memslot for gfn %ld\n", | |
3655 | audit_msg, gfn); | |
3656 | printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n", | |
805d32de | 3657 | audit_msg, (long int)(sptep - rev_sp->spt), |
08a3732b MT |
3658 | rev_sp->gfn); |
3659 | dump_stack(); | |
3660 | return; | |
3661 | } | |
3662 | ||
2032a93d | 3663 | rmapp = gfn_to_rmap(kvm, gfn, rev_sp->role.level); |
08a3732b MT |
3664 | if (!*rmapp) { |
3665 | if (!printk_ratelimit()) | |
3666 | return; | |
3667 | printk(KERN_ERR "%s: no rmap for writable spte %llx\n", | |
3668 | audit_msg, *sptep); | |
3669 | dump_stack(); | |
3670 | } | |
3671 | } | |
3672 | ||
3673 | } | |
3674 | ||
3675 | void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu) | |
3676 | { | |
3677 | mmu_spte_walk(vcpu, inspect_spte_has_rmap); | |
3678 | } | |
3679 | ||
3680 | static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu) | |
37a7d8b0 | 3681 | { |
4db35314 | 3682 | struct kvm_mmu_page *sp; |
37a7d8b0 AK |
3683 | int i; |
3684 | ||
f05e70ac | 3685 | list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) { |
4db35314 | 3686 | u64 *pt = sp->spt; |
37a7d8b0 | 3687 | |
4db35314 | 3688 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) |
37a7d8b0 AK |
3689 | continue; |
3690 | ||
3691 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
3692 | u64 ent = pt[i]; | |
3693 | ||
3694 | if (!(ent & PT_PRESENT_MASK)) | |
3695 | continue; | |
01c168ac | 3696 | if (!is_writable_pte(ent)) |
37a7d8b0 | 3697 | continue; |
805d32de | 3698 | inspect_spte_has_rmap(vcpu->kvm, &pt[i]); |
37a7d8b0 AK |
3699 | } |
3700 | } | |
08a3732b | 3701 | return; |
37a7d8b0 AK |
3702 | } |
3703 | ||
3704 | static void audit_rmap(struct kvm_vcpu *vcpu) | |
3705 | { | |
08a3732b MT |
3706 | check_writable_mappings_rmap(vcpu); |
3707 | count_rmaps(vcpu); | |
37a7d8b0 AK |
3708 | } |
3709 | ||
3710 | static void audit_write_protection(struct kvm_vcpu *vcpu) | |
3711 | { | |
4db35314 | 3712 | struct kvm_mmu_page *sp; |
290fc38d IE |
3713 | struct kvm_memory_slot *slot; |
3714 | unsigned long *rmapp; | |
e58b0f9e | 3715 | u64 *spte; |
290fc38d | 3716 | gfn_t gfn; |
37a7d8b0 | 3717 | |
f05e70ac | 3718 | list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) { |
f6e2c02b | 3719 | if (sp->role.direct) |
37a7d8b0 | 3720 | continue; |
e58b0f9e MT |
3721 | if (sp->unsync) |
3722 | continue; | |
37a7d8b0 | 3723 | |
a1f4d395 | 3724 | slot = gfn_to_memslot(vcpu->kvm, sp->gfn); |
290fc38d | 3725 | rmapp = &slot->rmap[gfn - slot->base_gfn]; |
e58b0f9e MT |
3726 | |
3727 | spte = rmap_next(vcpu->kvm, rmapp, NULL); | |
3728 | while (spte) { | |
01c168ac | 3729 | if (is_writable_pte(*spte)) |
e58b0f9e MT |
3730 | printk(KERN_ERR "%s: (%s) shadow page has " |
3731 | "writable mappings: gfn %lx role %x\n", | |
b8688d51 | 3732 | __func__, audit_msg, sp->gfn, |
4db35314 | 3733 | sp->role.word); |
e58b0f9e MT |
3734 | spte = rmap_next(vcpu->kvm, rmapp, spte); |
3735 | } | |
37a7d8b0 AK |
3736 | } |
3737 | } | |
3738 | ||
3739 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) | |
3740 | { | |
3741 | int olddbg = dbg; | |
3742 | ||
3743 | dbg = 0; | |
3744 | audit_msg = msg; | |
3745 | audit_rmap(vcpu); | |
3746 | audit_write_protection(vcpu); | |
2aaf65e8 MT |
3747 | if (strcmp("pre pte write", audit_msg) != 0) |
3748 | audit_mappings(vcpu); | |
08a3732b | 3749 | audit_writable_sptes_have_rmaps(vcpu); |
37a7d8b0 AK |
3750 | dbg = olddbg; |
3751 | } | |
3752 | ||
3753 | #endif |