Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
5f7dde7b | 25 | #include "cpuid.h" |
e495606d | 26 | |
edf88417 | 27 | #include <linux/kvm_host.h> |
6aa8b732 AK |
28 | #include <linux/types.h> |
29 | #include <linux/string.h> | |
6aa8b732 AK |
30 | #include <linux/mm.h> |
31 | #include <linux/highmem.h> | |
32 | #include <linux/module.h> | |
448353ca | 33 | #include <linux/swap.h> |
05da4558 | 34 | #include <linux/hugetlb.h> |
2f333bcb | 35 | #include <linux/compiler.h> |
bc6678a3 | 36 | #include <linux/srcu.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
bf998156 | 38 | #include <linux/uaccess.h> |
6aa8b732 | 39 | |
e495606d AK |
40 | #include <asm/page.h> |
41 | #include <asm/cmpxchg.h> | |
4e542370 | 42 | #include <asm/io.h> |
13673a90 | 43 | #include <asm/vmx.h> |
3d0c27ad | 44 | #include <asm/kvm_page_track.h> |
6aa8b732 | 45 | |
18552672 JR |
46 | /* |
47 | * When setting this variable to true it enables Two-Dimensional-Paging | |
48 | * where the hardware walks 2 page tables: | |
49 | * 1. the guest-virtual to guest-physical | |
50 | * 2. while doing 1. it walks guest-physical to host-physical | |
51 | * If the hardware supports that we don't need to do shadow paging. | |
52 | */ | |
2f333bcb | 53 | bool tdp_enabled = false; |
18552672 | 54 | |
8b1fe17c XG |
55 | enum { |
56 | AUDIT_PRE_PAGE_FAULT, | |
57 | AUDIT_POST_PAGE_FAULT, | |
58 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
59 | AUDIT_POST_PTE_WRITE, |
60 | AUDIT_PRE_SYNC, | |
61 | AUDIT_POST_SYNC | |
8b1fe17c | 62 | }; |
37a7d8b0 | 63 | |
8b1fe17c | 64 | #undef MMU_DEBUG |
37a7d8b0 AK |
65 | |
66 | #ifdef MMU_DEBUG | |
fa4a2c08 PB |
67 | static bool dbg = 0; |
68 | module_param(dbg, bool, 0644); | |
37a7d8b0 AK |
69 | |
70 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
71 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
fa4a2c08 | 72 | #define MMU_WARN_ON(x) WARN_ON(x) |
37a7d8b0 | 73 | #else |
37a7d8b0 AK |
74 | #define pgprintk(x...) do { } while (0) |
75 | #define rmap_printk(x...) do { } while (0) | |
fa4a2c08 | 76 | #define MMU_WARN_ON(x) do { } while (0) |
d6c69ee9 | 77 | #endif |
6aa8b732 | 78 | |
957ed9ef XG |
79 | #define PTE_PREFETCH_NUM 8 |
80 | ||
00763e41 | 81 | #define PT_FIRST_AVAIL_BITS_SHIFT 10 |
6aa8b732 AK |
82 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 |
83 | ||
6aa8b732 AK |
84 | #define PT64_LEVEL_BITS 9 |
85 | ||
86 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 87 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 88 | |
6aa8b732 AK |
89 | #define PT64_INDEX(address, level)\ |
90 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
91 | ||
92 | ||
93 | #define PT32_LEVEL_BITS 10 | |
94 | ||
95 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 96 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 97 | |
e04da980 JR |
98 | #define PT32_LVL_OFFSET_MASK(level) \ |
99 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
100 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
101 | |
102 | #define PT32_INDEX(address, level)\ | |
103 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
104 | ||
105 | ||
27aba766 | 106 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
107 | #define PT64_DIR_BASE_ADDR_MASK \ |
108 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
109 | #define PT64_LVL_ADDR_MASK(level) \ |
110 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
111 | * PT64_LEVEL_BITS))) - 1)) | |
112 | #define PT64_LVL_OFFSET_MASK(level) \ | |
113 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
114 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
115 | |
116 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
117 | #define PT32_DIR_BASE_ADDR_MASK \ | |
118 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
119 | #define PT32_LVL_ADDR_MASK(level) \ |
120 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
121 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 122 | |
53166229 GN |
123 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \ |
124 | | shadow_x_mask | shadow_nx_mask) | |
6aa8b732 | 125 | |
fe135d2c AK |
126 | #define ACC_EXEC_MASK 1 |
127 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
128 | #define ACC_USER_MASK PT_USER_MASK | |
129 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
130 | ||
90bb6fc5 AK |
131 | #include <trace/events/kvm.h> |
132 | ||
07420171 AK |
133 | #define CREATE_TRACE_POINTS |
134 | #include "mmutrace.h" | |
135 | ||
49fde340 XG |
136 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
137 | #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1)) | |
1403283a | 138 | |
135f8c2b AK |
139 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
140 | ||
220f773a TY |
141 | /* make pte_list_desc fit well in cache line */ |
142 | #define PTE_LIST_EXT 3 | |
143 | ||
53c07b18 XG |
144 | struct pte_list_desc { |
145 | u64 *sptes[PTE_LIST_EXT]; | |
146 | struct pte_list_desc *more; | |
cd4a4e53 AK |
147 | }; |
148 | ||
2d11123a AK |
149 | struct kvm_shadow_walk_iterator { |
150 | u64 addr; | |
151 | hpa_t shadow_addr; | |
2d11123a | 152 | u64 *sptep; |
dd3bfd59 | 153 | int level; |
2d11123a AK |
154 | unsigned index; |
155 | }; | |
156 | ||
157 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
158 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
159 | shadow_walk_okay(&(_walker)); \ | |
160 | shadow_walk_next(&(_walker))) | |
161 | ||
c2a2ac2b XG |
162 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
163 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
164 | shadow_walk_okay(&(_walker)) && \ | |
165 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
166 | __shadow_walk_next(&(_walker), spte)) | |
167 | ||
53c07b18 | 168 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 169 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 170 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 171 | |
7b52345e SY |
172 | static u64 __read_mostly shadow_nx_mask; |
173 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
174 | static u64 __read_mostly shadow_user_mask; | |
175 | static u64 __read_mostly shadow_accessed_mask; | |
176 | static u64 __read_mostly shadow_dirty_mask; | |
ce88decf XG |
177 | static u64 __read_mostly shadow_mmio_mask; |
178 | ||
179 | static void mmu_spte_set(u64 *sptep, u64 spte); | |
e676505a | 180 | static void mmu_free_roots(struct kvm_vcpu *vcpu); |
ce88decf XG |
181 | |
182 | void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask) | |
183 | { | |
184 | shadow_mmio_mask = mmio_mask; | |
185 | } | |
186 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); | |
187 | ||
f2fd125d | 188 | /* |
ee3d1570 DM |
189 | * the low bit of the generation number is always presumed to be zero. |
190 | * This disables mmio caching during memslot updates. The concept is | |
191 | * similar to a seqcount but instead of retrying the access we just punt | |
192 | * and ignore the cache. | |
193 | * | |
194 | * spte bits 3-11 are used as bits 1-9 of the generation number, | |
195 | * the bits 52-61 are used as bits 10-19 of the generation number. | |
f2fd125d | 196 | */ |
ee3d1570 | 197 | #define MMIO_SPTE_GEN_LOW_SHIFT 2 |
f2fd125d XG |
198 | #define MMIO_SPTE_GEN_HIGH_SHIFT 52 |
199 | ||
ee3d1570 DM |
200 | #define MMIO_GEN_SHIFT 20 |
201 | #define MMIO_GEN_LOW_SHIFT 10 | |
202 | #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2) | |
f8f55942 | 203 | #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1) |
f2fd125d XG |
204 | |
205 | static u64 generation_mmio_spte_mask(unsigned int gen) | |
206 | { | |
207 | u64 mask; | |
208 | ||
842bb26a | 209 | WARN_ON(gen & ~MMIO_GEN_MASK); |
f2fd125d XG |
210 | |
211 | mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT; | |
212 | mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT; | |
213 | return mask; | |
214 | } | |
215 | ||
216 | static unsigned int get_mmio_spte_generation(u64 spte) | |
217 | { | |
218 | unsigned int gen; | |
219 | ||
220 | spte &= ~shadow_mmio_mask; | |
221 | ||
222 | gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK; | |
223 | gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT; | |
224 | return gen; | |
225 | } | |
226 | ||
54bf36aa | 227 | static unsigned int kvm_current_mmio_generation(struct kvm_vcpu *vcpu) |
f8f55942 | 228 | { |
54bf36aa | 229 | return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK; |
f8f55942 XG |
230 | } |
231 | ||
54bf36aa | 232 | static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn, |
f2fd125d | 233 | unsigned access) |
ce88decf | 234 | { |
54bf36aa | 235 | unsigned int gen = kvm_current_mmio_generation(vcpu); |
f8f55942 | 236 | u64 mask = generation_mmio_spte_mask(gen); |
95b0430d | 237 | |
ce88decf | 238 | access &= ACC_WRITE_MASK | ACC_USER_MASK; |
f2fd125d | 239 | mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT; |
f2fd125d | 240 | |
f8f55942 | 241 | trace_mark_mmio_spte(sptep, gfn, access, gen); |
f2fd125d | 242 | mmu_spte_set(sptep, mask); |
ce88decf XG |
243 | } |
244 | ||
245 | static bool is_mmio_spte(u64 spte) | |
246 | { | |
247 | return (spte & shadow_mmio_mask) == shadow_mmio_mask; | |
248 | } | |
249 | ||
250 | static gfn_t get_mmio_spte_gfn(u64 spte) | |
251 | { | |
842bb26a | 252 | u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask; |
f2fd125d | 253 | return (spte & ~mask) >> PAGE_SHIFT; |
ce88decf XG |
254 | } |
255 | ||
256 | static unsigned get_mmio_spte_access(u64 spte) | |
257 | { | |
842bb26a | 258 | u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask; |
f2fd125d | 259 | return (spte & ~mask) & ~PAGE_MASK; |
ce88decf XG |
260 | } |
261 | ||
54bf36aa | 262 | static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
ba049e93 | 263 | kvm_pfn_t pfn, unsigned access) |
ce88decf XG |
264 | { |
265 | if (unlikely(is_noslot_pfn(pfn))) { | |
54bf36aa | 266 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
267 | return true; |
268 | } | |
269 | ||
270 | return false; | |
271 | } | |
c7addb90 | 272 | |
54bf36aa | 273 | static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte) |
f8f55942 | 274 | { |
089504c0 XG |
275 | unsigned int kvm_gen, spte_gen; |
276 | ||
54bf36aa | 277 | kvm_gen = kvm_current_mmio_generation(vcpu); |
089504c0 XG |
278 | spte_gen = get_mmio_spte_generation(spte); |
279 | ||
280 | trace_check_mmio_spte(spte, kvm_gen, spte_gen); | |
281 | return likely(kvm_gen == spte_gen); | |
f8f55942 XG |
282 | } |
283 | ||
7b52345e | 284 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 285 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
286 | { |
287 | shadow_user_mask = user_mask; | |
288 | shadow_accessed_mask = accessed_mask; | |
289 | shadow_dirty_mask = dirty_mask; | |
290 | shadow_nx_mask = nx_mask; | |
291 | shadow_x_mask = x_mask; | |
292 | } | |
293 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
294 | ||
6aa8b732 AK |
295 | static int is_cpuid_PSE36(void) |
296 | { | |
297 | return 1; | |
298 | } | |
299 | ||
73b1087e AK |
300 | static int is_nx(struct kvm_vcpu *vcpu) |
301 | { | |
f6801dff | 302 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
303 | } |
304 | ||
c7addb90 AK |
305 | static int is_shadow_present_pte(u64 pte) |
306 | { | |
ce88decf | 307 | return pte & PT_PRESENT_MASK && !is_mmio_spte(pte); |
c7addb90 AK |
308 | } |
309 | ||
05da4558 MT |
310 | static int is_large_pte(u64 pte) |
311 | { | |
312 | return pte & PT_PAGE_SIZE_MASK; | |
313 | } | |
314 | ||
776e6633 MT |
315 | static int is_last_spte(u64 pte, int level) |
316 | { | |
317 | if (level == PT_PAGE_TABLE_LEVEL) | |
318 | return 1; | |
852e3c19 | 319 | if (is_large_pte(pte)) |
776e6633 MT |
320 | return 1; |
321 | return 0; | |
322 | } | |
323 | ||
ba049e93 | 324 | static kvm_pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 325 | { |
35149e21 | 326 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
327 | } |
328 | ||
da928521 AK |
329 | static gfn_t pse36_gfn_delta(u32 gpte) |
330 | { | |
331 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
332 | ||
333 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
334 | } | |
335 | ||
603e0651 | 336 | #ifdef CONFIG_X86_64 |
d555c333 | 337 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 338 | { |
603e0651 | 339 | *sptep = spte; |
e663ee64 AK |
340 | } |
341 | ||
603e0651 | 342 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 343 | { |
603e0651 XG |
344 | *sptep = spte; |
345 | } | |
346 | ||
347 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
348 | { | |
349 | return xchg(sptep, spte); | |
350 | } | |
c2a2ac2b XG |
351 | |
352 | static u64 __get_spte_lockless(u64 *sptep) | |
353 | { | |
354 | return ACCESS_ONCE(*sptep); | |
355 | } | |
a9221dd5 | 356 | #else |
603e0651 XG |
357 | union split_spte { |
358 | struct { | |
359 | u32 spte_low; | |
360 | u32 spte_high; | |
361 | }; | |
362 | u64 spte; | |
363 | }; | |
a9221dd5 | 364 | |
c2a2ac2b XG |
365 | static void count_spte_clear(u64 *sptep, u64 spte) |
366 | { | |
367 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
368 | ||
369 | if (is_shadow_present_pte(spte)) | |
370 | return; | |
371 | ||
372 | /* Ensure the spte is completely set before we increase the count */ | |
373 | smp_wmb(); | |
374 | sp->clear_spte_count++; | |
375 | } | |
376 | ||
603e0651 XG |
377 | static void __set_spte(u64 *sptep, u64 spte) |
378 | { | |
379 | union split_spte *ssptep, sspte; | |
a9221dd5 | 380 | |
603e0651 XG |
381 | ssptep = (union split_spte *)sptep; |
382 | sspte = (union split_spte)spte; | |
383 | ||
384 | ssptep->spte_high = sspte.spte_high; | |
385 | ||
386 | /* | |
387 | * If we map the spte from nonpresent to present, We should store | |
388 | * the high bits firstly, then set present bit, so cpu can not | |
389 | * fetch this spte while we are setting the spte. | |
390 | */ | |
391 | smp_wmb(); | |
392 | ||
393 | ssptep->spte_low = sspte.spte_low; | |
a9221dd5 AK |
394 | } |
395 | ||
603e0651 XG |
396 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
397 | { | |
398 | union split_spte *ssptep, sspte; | |
399 | ||
400 | ssptep = (union split_spte *)sptep; | |
401 | sspte = (union split_spte)spte; | |
402 | ||
403 | ssptep->spte_low = sspte.spte_low; | |
404 | ||
405 | /* | |
406 | * If we map the spte from present to nonpresent, we should clear | |
407 | * present bit firstly to avoid vcpu fetch the old high bits. | |
408 | */ | |
409 | smp_wmb(); | |
410 | ||
411 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 412 | count_spte_clear(sptep, spte); |
603e0651 XG |
413 | } |
414 | ||
415 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
416 | { | |
417 | union split_spte *ssptep, sspte, orig; | |
418 | ||
419 | ssptep = (union split_spte *)sptep; | |
420 | sspte = (union split_spte)spte; | |
421 | ||
422 | /* xchg acts as a barrier before the setting of the high bits */ | |
423 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
424 | orig.spte_high = ssptep->spte_high; |
425 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 426 | count_spte_clear(sptep, spte); |
603e0651 XG |
427 | |
428 | return orig.spte; | |
429 | } | |
c2a2ac2b XG |
430 | |
431 | /* | |
432 | * The idea using the light way get the spte on x86_32 guest is from | |
433 | * gup_get_pte(arch/x86/mm/gup.c). | |
accaefe0 XG |
434 | * |
435 | * An spte tlb flush may be pending, because kvm_set_pte_rmapp | |
436 | * coalesces them and we are running out of the MMU lock. Therefore | |
437 | * we need to protect against in-progress updates of the spte. | |
438 | * | |
439 | * Reading the spte while an update is in progress may get the old value | |
440 | * for the high part of the spte. The race is fine for a present->non-present | |
441 | * change (because the high part of the spte is ignored for non-present spte), | |
442 | * but for a present->present change we must reread the spte. | |
443 | * | |
444 | * All such changes are done in two steps (present->non-present and | |
445 | * non-present->present), hence it is enough to count the number of | |
446 | * present->non-present updates: if it changed while reading the spte, | |
447 | * we might have hit the race. This is done using clear_spte_count. | |
c2a2ac2b XG |
448 | */ |
449 | static u64 __get_spte_lockless(u64 *sptep) | |
450 | { | |
451 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
452 | union split_spte spte, *orig = (union split_spte *)sptep; | |
453 | int count; | |
454 | ||
455 | retry: | |
456 | count = sp->clear_spte_count; | |
457 | smp_rmb(); | |
458 | ||
459 | spte.spte_low = orig->spte_low; | |
460 | smp_rmb(); | |
461 | ||
462 | spte.spte_high = orig->spte_high; | |
463 | smp_rmb(); | |
464 | ||
465 | if (unlikely(spte.spte_low != orig->spte_low || | |
466 | count != sp->clear_spte_count)) | |
467 | goto retry; | |
468 | ||
469 | return spte.spte; | |
470 | } | |
603e0651 XG |
471 | #endif |
472 | ||
c7ba5b48 XG |
473 | static bool spte_is_locklessly_modifiable(u64 spte) |
474 | { | |
feb3eb70 GN |
475 | return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) == |
476 | (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE); | |
c7ba5b48 XG |
477 | } |
478 | ||
8672b721 XG |
479 | static bool spte_has_volatile_bits(u64 spte) |
480 | { | |
c7ba5b48 XG |
481 | /* |
482 | * Always atomicly update spte if it can be updated | |
483 | * out of mmu-lock, it can ensure dirty bit is not lost, | |
484 | * also, it can help us to get a stable is_writable_pte() | |
485 | * to ensure tlb flush is not missed. | |
486 | */ | |
487 | if (spte_is_locklessly_modifiable(spte)) | |
488 | return true; | |
489 | ||
8672b721 XG |
490 | if (!shadow_accessed_mask) |
491 | return false; | |
492 | ||
493 | if (!is_shadow_present_pte(spte)) | |
494 | return false; | |
495 | ||
4132779b XG |
496 | if ((spte & shadow_accessed_mask) && |
497 | (!is_writable_pte(spte) || (spte & shadow_dirty_mask))) | |
8672b721 XG |
498 | return false; |
499 | ||
500 | return true; | |
501 | } | |
502 | ||
4132779b XG |
503 | static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask) |
504 | { | |
505 | return (old_spte & bit_mask) && !(new_spte & bit_mask); | |
506 | } | |
507 | ||
7e71a59b KH |
508 | static bool spte_is_bit_changed(u64 old_spte, u64 new_spte, u64 bit_mask) |
509 | { | |
510 | return (old_spte & bit_mask) != (new_spte & bit_mask); | |
511 | } | |
512 | ||
1df9f2dc XG |
513 | /* Rules for using mmu_spte_set: |
514 | * Set the sptep from nonpresent to present. | |
515 | * Note: the sptep being assigned *must* be either not present | |
516 | * or in a state where the hardware will not attempt to update | |
517 | * the spte. | |
518 | */ | |
519 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
520 | { | |
521 | WARN_ON(is_shadow_present_pte(*sptep)); | |
522 | __set_spte(sptep, new_spte); | |
523 | } | |
524 | ||
525 | /* Rules for using mmu_spte_update: | |
526 | * Update the state bits, it means the mapped pfn is not changged. | |
6e7d0354 XG |
527 | * |
528 | * Whenever we overwrite a writable spte with a read-only one we | |
529 | * should flush remote TLBs. Otherwise rmap_write_protect | |
530 | * will find a read-only spte, even though the writable spte | |
531 | * might be cached on a CPU's TLB, the return value indicates this | |
532 | * case. | |
1df9f2dc | 533 | */ |
6e7d0354 | 534 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) |
b79b93f9 | 535 | { |
c7ba5b48 | 536 | u64 old_spte = *sptep; |
6e7d0354 | 537 | bool ret = false; |
4132779b | 538 | |
afd28fe1 | 539 | WARN_ON(!is_shadow_present_pte(new_spte)); |
b79b93f9 | 540 | |
6e7d0354 XG |
541 | if (!is_shadow_present_pte(old_spte)) { |
542 | mmu_spte_set(sptep, new_spte); | |
543 | return ret; | |
544 | } | |
4132779b | 545 | |
c7ba5b48 | 546 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 547 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 548 | else |
603e0651 | 549 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 550 | |
c7ba5b48 XG |
551 | /* |
552 | * For the spte updated out of mmu-lock is safe, since | |
553 | * we always atomicly update it, see the comments in | |
554 | * spte_has_volatile_bits(). | |
555 | */ | |
7f31c959 XG |
556 | if (spte_is_locklessly_modifiable(old_spte) && |
557 | !is_writable_pte(new_spte)) | |
6e7d0354 XG |
558 | ret = true; |
559 | ||
4132779b | 560 | if (!shadow_accessed_mask) |
6e7d0354 | 561 | return ret; |
4132779b | 562 | |
7e71a59b KH |
563 | /* |
564 | * Flush TLB when accessed/dirty bits are changed in the page tables, | |
565 | * to guarantee consistency between TLB and page tables. | |
566 | */ | |
567 | if (spte_is_bit_changed(old_spte, new_spte, | |
568 | shadow_accessed_mask | shadow_dirty_mask)) | |
569 | ret = true; | |
570 | ||
4132779b XG |
571 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask)) |
572 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); | |
573 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask)) | |
574 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); | |
6e7d0354 XG |
575 | |
576 | return ret; | |
b79b93f9 AK |
577 | } |
578 | ||
1df9f2dc XG |
579 | /* |
580 | * Rules for using mmu_spte_clear_track_bits: | |
581 | * It sets the sptep from present to nonpresent, and track the | |
582 | * state bits, it is used to clear the last level sptep. | |
583 | */ | |
584 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
585 | { | |
ba049e93 | 586 | kvm_pfn_t pfn; |
1df9f2dc XG |
587 | u64 old_spte = *sptep; |
588 | ||
589 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 590 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 591 | else |
603e0651 | 592 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc | 593 | |
afd28fe1 | 594 | if (!is_shadow_present_pte(old_spte)) |
1df9f2dc XG |
595 | return 0; |
596 | ||
597 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
598 | |
599 | /* | |
600 | * KVM does not hold the refcount of the page used by | |
601 | * kvm mmu, before reclaiming the page, we should | |
602 | * unmap it from mmu first. | |
603 | */ | |
bf4bea8e | 604 | WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn))); |
86fde74c | 605 | |
1df9f2dc XG |
606 | if (!shadow_accessed_mask || old_spte & shadow_accessed_mask) |
607 | kvm_set_pfn_accessed(pfn); | |
608 | if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask)) | |
609 | kvm_set_pfn_dirty(pfn); | |
610 | return 1; | |
611 | } | |
612 | ||
613 | /* | |
614 | * Rules for using mmu_spte_clear_no_track: | |
615 | * Directly clear spte without caring the state bits of sptep, | |
616 | * it is used to set the upper level spte. | |
617 | */ | |
618 | static void mmu_spte_clear_no_track(u64 *sptep) | |
619 | { | |
603e0651 | 620 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
621 | } |
622 | ||
c2a2ac2b XG |
623 | static u64 mmu_spte_get_lockless(u64 *sptep) |
624 | { | |
625 | return __get_spte_lockless(sptep); | |
626 | } | |
627 | ||
628 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) | |
629 | { | |
c142786c AK |
630 | /* |
631 | * Prevent page table teardown by making any free-er wait during | |
632 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
633 | */ | |
634 | local_irq_disable(); | |
635 | vcpu->mode = READING_SHADOW_PAGE_TABLES; | |
636 | /* | |
637 | * Make sure a following spte read is not reordered ahead of the write | |
638 | * to vcpu->mode. | |
639 | */ | |
640 | smp_mb(); | |
c2a2ac2b XG |
641 | } |
642 | ||
643 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
644 | { | |
c142786c AK |
645 | /* |
646 | * Make sure the write to vcpu->mode is not reordered in front of | |
647 | * reads to sptes. If it does, kvm_commit_zap_page() can see us | |
648 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. | |
649 | */ | |
650 | smp_mb(); | |
651 | vcpu->mode = OUTSIDE_GUEST_MODE; | |
652 | local_irq_enable(); | |
c2a2ac2b XG |
653 | } |
654 | ||
e2dec939 | 655 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 656 | struct kmem_cache *base_cache, int min) |
714b93da AK |
657 | { |
658 | void *obj; | |
659 | ||
660 | if (cache->nobjs >= min) | |
e2dec939 | 661 | return 0; |
714b93da | 662 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 663 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 664 | if (!obj) |
e2dec939 | 665 | return -ENOMEM; |
714b93da AK |
666 | cache->objects[cache->nobjs++] = obj; |
667 | } | |
e2dec939 | 668 | return 0; |
714b93da AK |
669 | } |
670 | ||
f759e2b4 XG |
671 | static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache) |
672 | { | |
673 | return cache->nobjs; | |
674 | } | |
675 | ||
e8ad9a70 XG |
676 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
677 | struct kmem_cache *cache) | |
714b93da AK |
678 | { |
679 | while (mc->nobjs) | |
e8ad9a70 | 680 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
681 | } |
682 | ||
c1158e63 | 683 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 684 | int min) |
c1158e63 | 685 | { |
842f22ed | 686 | void *page; |
c1158e63 AK |
687 | |
688 | if (cache->nobjs >= min) | |
689 | return 0; | |
690 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
842f22ed | 691 | page = (void *)__get_free_page(GFP_KERNEL); |
c1158e63 AK |
692 | if (!page) |
693 | return -ENOMEM; | |
842f22ed | 694 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
695 | } |
696 | return 0; | |
697 | } | |
698 | ||
699 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
700 | { | |
701 | while (mc->nobjs) | |
c4d198d5 | 702 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
703 | } |
704 | ||
2e3e5882 | 705 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 706 | { |
e2dec939 AK |
707 | int r; |
708 | ||
53c07b18 | 709 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 710 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
711 | if (r) |
712 | goto out; | |
ad312c7c | 713 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
714 | if (r) |
715 | goto out; | |
ad312c7c | 716 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 717 | mmu_page_header_cache, 4); |
e2dec939 AK |
718 | out: |
719 | return r; | |
714b93da AK |
720 | } |
721 | ||
722 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
723 | { | |
53c07b18 XG |
724 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
725 | pte_list_desc_cache); | |
ad312c7c | 726 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
727 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
728 | mmu_page_header_cache); | |
714b93da AK |
729 | } |
730 | ||
80feb89a | 731 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) |
714b93da AK |
732 | { |
733 | void *p; | |
734 | ||
735 | BUG_ON(!mc->nobjs); | |
736 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
737 | return p; |
738 | } | |
739 | ||
53c07b18 | 740 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 741 | { |
80feb89a | 742 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
743 | } |
744 | ||
53c07b18 | 745 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 746 | { |
53c07b18 | 747 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
748 | } |
749 | ||
2032a93d LJ |
750 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
751 | { | |
752 | if (!sp->role.direct) | |
753 | return sp->gfns[index]; | |
754 | ||
755 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
756 | } | |
757 | ||
758 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
759 | { | |
760 | if (sp->role.direct) | |
761 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
762 | else | |
763 | sp->gfns[index] = gfn; | |
764 | } | |
765 | ||
05da4558 | 766 | /* |
d4dbf470 TY |
767 | * Return the pointer to the large page information for a given gfn, |
768 | * handling slots that are not large page aligned. | |
05da4558 | 769 | */ |
d4dbf470 TY |
770 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
771 | struct kvm_memory_slot *slot, | |
772 | int level) | |
05da4558 MT |
773 | { |
774 | unsigned long idx; | |
775 | ||
fb03cb6f | 776 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 777 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
778 | } |
779 | ||
547ffaed XG |
780 | static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot, |
781 | gfn_t gfn, int count) | |
782 | { | |
783 | struct kvm_lpage_info *linfo; | |
784 | int i; | |
785 | ||
786 | for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { | |
787 | linfo = lpage_info_slot(gfn, slot, i); | |
788 | linfo->disallow_lpage += count; | |
789 | WARN_ON(linfo->disallow_lpage < 0); | |
790 | } | |
791 | } | |
792 | ||
793 | void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
794 | { | |
795 | update_gfn_disallow_lpage_count(slot, gfn, 1); | |
796 | } | |
797 | ||
798 | void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
799 | { | |
800 | update_gfn_disallow_lpage_count(slot, gfn, -1); | |
801 | } | |
802 | ||
3ed1a478 | 803 | static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 804 | { |
699023e2 | 805 | struct kvm_memslots *slots; |
d25797b2 | 806 | struct kvm_memory_slot *slot; |
3ed1a478 | 807 | gfn_t gfn; |
05da4558 | 808 | |
3ed1a478 | 809 | gfn = sp->gfn; |
699023e2 PB |
810 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
811 | slot = __gfn_to_memslot(slots, gfn); | |
547ffaed | 812 | kvm_mmu_gfn_disallow_lpage(slot, gfn); |
332b207d | 813 | kvm->arch.indirect_shadow_pages++; |
05da4558 MT |
814 | } |
815 | ||
3ed1a478 | 816 | static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 817 | { |
699023e2 | 818 | struct kvm_memslots *slots; |
d25797b2 | 819 | struct kvm_memory_slot *slot; |
3ed1a478 | 820 | gfn_t gfn; |
05da4558 | 821 | |
3ed1a478 | 822 | gfn = sp->gfn; |
699023e2 PB |
823 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
824 | slot = __gfn_to_memslot(slots, gfn); | |
547ffaed | 825 | kvm_mmu_gfn_allow_lpage(slot, gfn); |
332b207d | 826 | kvm->arch.indirect_shadow_pages--; |
05da4558 MT |
827 | } |
828 | ||
92f94f1e XG |
829 | static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level, |
830 | struct kvm_memory_slot *slot) | |
05da4558 | 831 | { |
d4dbf470 | 832 | struct kvm_lpage_info *linfo; |
05da4558 MT |
833 | |
834 | if (slot) { | |
d4dbf470 | 835 | linfo = lpage_info_slot(gfn, slot, level); |
92f94f1e | 836 | return !!linfo->disallow_lpage; |
05da4558 MT |
837 | } |
838 | ||
92f94f1e | 839 | return true; |
05da4558 MT |
840 | } |
841 | ||
92f94f1e XG |
842 | static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn, |
843 | int level) | |
5225fdf8 TY |
844 | { |
845 | struct kvm_memory_slot *slot; | |
846 | ||
847 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
92f94f1e | 848 | return __mmu_gfn_lpage_is_disallowed(gfn, level, slot); |
5225fdf8 TY |
849 | } |
850 | ||
d25797b2 | 851 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 852 | { |
8f0b1ab6 | 853 | unsigned long page_size; |
d25797b2 | 854 | int i, ret = 0; |
05da4558 | 855 | |
8f0b1ab6 | 856 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 857 | |
8a3d08f1 | 858 | for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { |
d25797b2 JR |
859 | if (page_size >= KVM_HPAGE_SIZE(i)) |
860 | ret = i; | |
861 | else | |
862 | break; | |
863 | } | |
864 | ||
4c2155ce | 865 | return ret; |
05da4558 MT |
866 | } |
867 | ||
d8aacf5d TY |
868 | static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot, |
869 | bool no_dirty_log) | |
870 | { | |
871 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID) | |
872 | return false; | |
873 | if (no_dirty_log && slot->dirty_bitmap) | |
874 | return false; | |
875 | ||
876 | return true; | |
877 | } | |
878 | ||
5d163b1c XG |
879 | static struct kvm_memory_slot * |
880 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
881 | bool no_dirty_log) | |
05da4558 MT |
882 | { |
883 | struct kvm_memory_slot *slot; | |
5d163b1c | 884 | |
54bf36aa | 885 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
d8aacf5d | 886 | if (!memslot_valid_for_gpte(slot, no_dirty_log)) |
5d163b1c XG |
887 | slot = NULL; |
888 | ||
889 | return slot; | |
890 | } | |
891 | ||
fd136902 TY |
892 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn, |
893 | bool *force_pt_level) | |
936a5fe6 AA |
894 | { |
895 | int host_level, level, max_level; | |
d8aacf5d TY |
896 | struct kvm_memory_slot *slot; |
897 | ||
8c85ac1c TY |
898 | if (unlikely(*force_pt_level)) |
899 | return PT_PAGE_TABLE_LEVEL; | |
05da4558 | 900 | |
8c85ac1c TY |
901 | slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn); |
902 | *force_pt_level = !memslot_valid_for_gpte(slot, true); | |
fd136902 TY |
903 | if (unlikely(*force_pt_level)) |
904 | return PT_PAGE_TABLE_LEVEL; | |
905 | ||
d25797b2 JR |
906 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
907 | ||
908 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
909 | return host_level; | |
910 | ||
55dd98c3 | 911 | max_level = min(kvm_x86_ops->get_lpage_level(), host_level); |
878403b7 SY |
912 | |
913 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
92f94f1e | 914 | if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot)) |
d25797b2 | 915 | break; |
d25797b2 JR |
916 | |
917 | return level - 1; | |
05da4558 MT |
918 | } |
919 | ||
290fc38d | 920 | /* |
018aabb5 | 921 | * About rmap_head encoding: |
cd4a4e53 | 922 | * |
018aabb5 TY |
923 | * If the bit zero of rmap_head->val is clear, then it points to the only spte |
924 | * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct | |
53c07b18 | 925 | * pte_list_desc containing more mappings. |
018aabb5 TY |
926 | */ |
927 | ||
928 | /* | |
929 | * Returns the number of pointers in the rmap chain, not counting the new one. | |
cd4a4e53 | 930 | */ |
53c07b18 | 931 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
018aabb5 | 932 | struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 933 | { |
53c07b18 | 934 | struct pte_list_desc *desc; |
53a27b39 | 935 | int i, count = 0; |
cd4a4e53 | 936 | |
018aabb5 | 937 | if (!rmap_head->val) { |
53c07b18 | 938 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); |
018aabb5 TY |
939 | rmap_head->val = (unsigned long)spte; |
940 | } else if (!(rmap_head->val & 1)) { | |
53c07b18 XG |
941 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); |
942 | desc = mmu_alloc_pte_list_desc(vcpu); | |
018aabb5 | 943 | desc->sptes[0] = (u64 *)rmap_head->val; |
d555c333 | 944 | desc->sptes[1] = spte; |
018aabb5 | 945 | rmap_head->val = (unsigned long)desc | 1; |
cb16a7b3 | 946 | ++count; |
cd4a4e53 | 947 | } else { |
53c07b18 | 948 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
018aabb5 | 949 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
53c07b18 | 950 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { |
cd4a4e53 | 951 | desc = desc->more; |
53c07b18 | 952 | count += PTE_LIST_EXT; |
53a27b39 | 953 | } |
53c07b18 XG |
954 | if (desc->sptes[PTE_LIST_EXT-1]) { |
955 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
956 | desc = desc->more; |
957 | } | |
d555c333 | 958 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 959 | ++count; |
d555c333 | 960 | desc->sptes[i] = spte; |
cd4a4e53 | 961 | } |
53a27b39 | 962 | return count; |
cd4a4e53 AK |
963 | } |
964 | ||
53c07b18 | 965 | static void |
018aabb5 TY |
966 | pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head, |
967 | struct pte_list_desc *desc, int i, | |
968 | struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
969 | { |
970 | int j; | |
971 | ||
53c07b18 | 972 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 973 | ; |
d555c333 AK |
974 | desc->sptes[i] = desc->sptes[j]; |
975 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
976 | if (j != 0) |
977 | return; | |
978 | if (!prev_desc && !desc->more) | |
018aabb5 | 979 | rmap_head->val = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
980 | else |
981 | if (prev_desc) | |
982 | prev_desc->more = desc->more; | |
983 | else | |
018aabb5 | 984 | rmap_head->val = (unsigned long)desc->more | 1; |
53c07b18 | 985 | mmu_free_pte_list_desc(desc); |
cd4a4e53 AK |
986 | } |
987 | ||
018aabb5 | 988 | static void pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 989 | { |
53c07b18 XG |
990 | struct pte_list_desc *desc; |
991 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
992 | int i; |
993 | ||
018aabb5 | 994 | if (!rmap_head->val) { |
53c07b18 | 995 | printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte); |
cd4a4e53 | 996 | BUG(); |
018aabb5 | 997 | } else if (!(rmap_head->val & 1)) { |
53c07b18 | 998 | rmap_printk("pte_list_remove: %p 1->0\n", spte); |
018aabb5 | 999 | if ((u64 *)rmap_head->val != spte) { |
53c07b18 | 1000 | printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte); |
cd4a4e53 AK |
1001 | BUG(); |
1002 | } | |
018aabb5 | 1003 | rmap_head->val = 0; |
cd4a4e53 | 1004 | } else { |
53c07b18 | 1005 | rmap_printk("pte_list_remove: %p many->many\n", spte); |
018aabb5 | 1006 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
cd4a4e53 AK |
1007 | prev_desc = NULL; |
1008 | while (desc) { | |
018aabb5 | 1009 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) { |
d555c333 | 1010 | if (desc->sptes[i] == spte) { |
018aabb5 TY |
1011 | pte_list_desc_remove_entry(rmap_head, |
1012 | desc, i, prev_desc); | |
cd4a4e53 AK |
1013 | return; |
1014 | } | |
018aabb5 | 1015 | } |
cd4a4e53 AK |
1016 | prev_desc = desc; |
1017 | desc = desc->more; | |
1018 | } | |
53c07b18 | 1019 | pr_err("pte_list_remove: %p many->many\n", spte); |
cd4a4e53 AK |
1020 | BUG(); |
1021 | } | |
1022 | } | |
1023 | ||
018aabb5 TY |
1024 | static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level, |
1025 | struct kvm_memory_slot *slot) | |
53c07b18 | 1026 | { |
77d11309 | 1027 | unsigned long idx; |
53c07b18 | 1028 | |
77d11309 | 1029 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
d89cc617 | 1030 | return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx]; |
53c07b18 XG |
1031 | } |
1032 | ||
018aabb5 TY |
1033 | static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, |
1034 | struct kvm_mmu_page *sp) | |
9b9b1492 | 1035 | { |
699023e2 | 1036 | struct kvm_memslots *slots; |
9b9b1492 TY |
1037 | struct kvm_memory_slot *slot; |
1038 | ||
699023e2 PB |
1039 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1040 | slot = __gfn_to_memslot(slots, gfn); | |
e4cd1da9 | 1041 | return __gfn_to_rmap(gfn, sp->role.level, slot); |
9b9b1492 TY |
1042 | } |
1043 | ||
f759e2b4 XG |
1044 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
1045 | { | |
1046 | struct kvm_mmu_memory_cache *cache; | |
1047 | ||
1048 | cache = &vcpu->arch.mmu_pte_list_desc_cache; | |
1049 | return mmu_memory_cache_free_objects(cache); | |
1050 | } | |
1051 | ||
53c07b18 XG |
1052 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
1053 | { | |
1054 | struct kvm_mmu_page *sp; | |
018aabb5 | 1055 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 1056 | |
53c07b18 XG |
1057 | sp = page_header(__pa(spte)); |
1058 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
018aabb5 TY |
1059 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
1060 | return pte_list_add(vcpu, spte, rmap_head); | |
53c07b18 XG |
1061 | } |
1062 | ||
53c07b18 XG |
1063 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
1064 | { | |
1065 | struct kvm_mmu_page *sp; | |
1066 | gfn_t gfn; | |
018aabb5 | 1067 | struct kvm_rmap_head *rmap_head; |
53c07b18 XG |
1068 | |
1069 | sp = page_header(__pa(spte)); | |
1070 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
018aabb5 TY |
1071 | rmap_head = gfn_to_rmap(kvm, gfn, sp); |
1072 | pte_list_remove(spte, rmap_head); | |
53c07b18 XG |
1073 | } |
1074 | ||
1e3f42f0 TY |
1075 | /* |
1076 | * Used by the following functions to iterate through the sptes linked by a | |
1077 | * rmap. All fields are private and not assumed to be used outside. | |
1078 | */ | |
1079 | struct rmap_iterator { | |
1080 | /* private fields */ | |
1081 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1082 | int pos; /* index of the sptep */ | |
1083 | }; | |
1084 | ||
1085 | /* | |
1086 | * Iteration must be started by this function. This should also be used after | |
1087 | * removing/dropping sptes from the rmap link because in such cases the | |
1088 | * information in the itererator may not be valid. | |
1089 | * | |
1090 | * Returns sptep if found, NULL otherwise. | |
1091 | */ | |
018aabb5 TY |
1092 | static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head, |
1093 | struct rmap_iterator *iter) | |
1e3f42f0 | 1094 | { |
77fbbbd2 TY |
1095 | u64 *sptep; |
1096 | ||
018aabb5 | 1097 | if (!rmap_head->val) |
1e3f42f0 TY |
1098 | return NULL; |
1099 | ||
018aabb5 | 1100 | if (!(rmap_head->val & 1)) { |
1e3f42f0 | 1101 | iter->desc = NULL; |
77fbbbd2 TY |
1102 | sptep = (u64 *)rmap_head->val; |
1103 | goto out; | |
1e3f42f0 TY |
1104 | } |
1105 | ||
018aabb5 | 1106 | iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
1e3f42f0 | 1107 | iter->pos = 0; |
77fbbbd2 TY |
1108 | sptep = iter->desc->sptes[iter->pos]; |
1109 | out: | |
1110 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1111 | return sptep; | |
1e3f42f0 TY |
1112 | } |
1113 | ||
1114 | /* | |
1115 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1116 | * | |
1117 | * Returns sptep if found, NULL otherwise. | |
1118 | */ | |
1119 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1120 | { | |
77fbbbd2 TY |
1121 | u64 *sptep; |
1122 | ||
1e3f42f0 TY |
1123 | if (iter->desc) { |
1124 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1e3f42f0 TY |
1125 | ++iter->pos; |
1126 | sptep = iter->desc->sptes[iter->pos]; | |
1127 | if (sptep) | |
77fbbbd2 | 1128 | goto out; |
1e3f42f0 TY |
1129 | } |
1130 | ||
1131 | iter->desc = iter->desc->more; | |
1132 | ||
1133 | if (iter->desc) { | |
1134 | iter->pos = 0; | |
1135 | /* desc->sptes[0] cannot be NULL */ | |
77fbbbd2 TY |
1136 | sptep = iter->desc->sptes[iter->pos]; |
1137 | goto out; | |
1e3f42f0 TY |
1138 | } |
1139 | } | |
1140 | ||
1141 | return NULL; | |
77fbbbd2 TY |
1142 | out: |
1143 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1144 | return sptep; | |
1e3f42f0 TY |
1145 | } |
1146 | ||
018aabb5 TY |
1147 | #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \ |
1148 | for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \ | |
77fbbbd2 | 1149 | _spte_; _spte_ = rmap_get_next(_iter_)) |
0d536790 | 1150 | |
c3707958 | 1151 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1152 | { |
1df9f2dc | 1153 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1154 | rmap_remove(kvm, sptep); |
be38d276 AK |
1155 | } |
1156 | ||
8e22f955 XG |
1157 | |
1158 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1159 | { | |
1160 | if (is_large_pte(*sptep)) { | |
1161 | WARN_ON(page_header(__pa(sptep))->role.level == | |
1162 | PT_PAGE_TABLE_LEVEL); | |
1163 | drop_spte(kvm, sptep); | |
1164 | --kvm->stat.lpages; | |
1165 | return true; | |
1166 | } | |
1167 | ||
1168 | return false; | |
1169 | } | |
1170 | ||
1171 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1172 | { | |
1173 | if (__drop_large_spte(vcpu->kvm, sptep)) | |
1174 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1175 | } | |
1176 | ||
1177 | /* | |
49fde340 | 1178 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
c126d94f | 1179 | * spte write-protection is caused by protecting shadow page table. |
49fde340 | 1180 | * |
b4619660 | 1181 | * Note: write protection is difference between dirty logging and spte |
49fde340 XG |
1182 | * protection: |
1183 | * - for dirty logging, the spte can be set to writable at anytime if | |
1184 | * its dirty bitmap is properly set. | |
1185 | * - for spte protection, the spte can be writable only after unsync-ing | |
1186 | * shadow page. | |
8e22f955 | 1187 | * |
c126d94f | 1188 | * Return true if tlb need be flushed. |
8e22f955 | 1189 | */ |
c126d94f | 1190 | static bool spte_write_protect(struct kvm *kvm, u64 *sptep, bool pt_protect) |
d13bc5b5 XG |
1191 | { |
1192 | u64 spte = *sptep; | |
1193 | ||
49fde340 XG |
1194 | if (!is_writable_pte(spte) && |
1195 | !(pt_protect && spte_is_locklessly_modifiable(spte))) | |
d13bc5b5 XG |
1196 | return false; |
1197 | ||
1198 | rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); | |
1199 | ||
49fde340 XG |
1200 | if (pt_protect) |
1201 | spte &= ~SPTE_MMU_WRITEABLE; | |
d13bc5b5 | 1202 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1203 | |
c126d94f | 1204 | return mmu_spte_update(sptep, spte); |
d13bc5b5 XG |
1205 | } |
1206 | ||
018aabb5 TY |
1207 | static bool __rmap_write_protect(struct kvm *kvm, |
1208 | struct kvm_rmap_head *rmap_head, | |
245c3912 | 1209 | bool pt_protect) |
98348e95 | 1210 | { |
1e3f42f0 TY |
1211 | u64 *sptep; |
1212 | struct rmap_iterator iter; | |
d13bc5b5 | 1213 | bool flush = false; |
374cbac0 | 1214 | |
018aabb5 | 1215 | for_each_rmap_spte(rmap_head, &iter, sptep) |
c126d94f | 1216 | flush |= spte_write_protect(kvm, sptep, pt_protect); |
855149aa | 1217 | |
d13bc5b5 | 1218 | return flush; |
a0ed4607 TY |
1219 | } |
1220 | ||
f4b4b180 KH |
1221 | static bool spte_clear_dirty(struct kvm *kvm, u64 *sptep) |
1222 | { | |
1223 | u64 spte = *sptep; | |
1224 | ||
1225 | rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep); | |
1226 | ||
1227 | spte &= ~shadow_dirty_mask; | |
1228 | ||
1229 | return mmu_spte_update(sptep, spte); | |
1230 | } | |
1231 | ||
018aabb5 | 1232 | static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1233 | { |
1234 | u64 *sptep; | |
1235 | struct rmap_iterator iter; | |
1236 | bool flush = false; | |
1237 | ||
018aabb5 | 1238 | for_each_rmap_spte(rmap_head, &iter, sptep) |
f4b4b180 | 1239 | flush |= spte_clear_dirty(kvm, sptep); |
f4b4b180 KH |
1240 | |
1241 | return flush; | |
1242 | } | |
1243 | ||
1244 | static bool spte_set_dirty(struct kvm *kvm, u64 *sptep) | |
1245 | { | |
1246 | u64 spte = *sptep; | |
1247 | ||
1248 | rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep); | |
1249 | ||
1250 | spte |= shadow_dirty_mask; | |
1251 | ||
1252 | return mmu_spte_update(sptep, spte); | |
1253 | } | |
1254 | ||
018aabb5 | 1255 | static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1256 | { |
1257 | u64 *sptep; | |
1258 | struct rmap_iterator iter; | |
1259 | bool flush = false; | |
1260 | ||
018aabb5 | 1261 | for_each_rmap_spte(rmap_head, &iter, sptep) |
f4b4b180 | 1262 | flush |= spte_set_dirty(kvm, sptep); |
f4b4b180 KH |
1263 | |
1264 | return flush; | |
1265 | } | |
1266 | ||
5dc99b23 | 1267 | /** |
3b0f1d01 | 1268 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages |
5dc99b23 TY |
1269 | * @kvm: kvm instance |
1270 | * @slot: slot to protect | |
1271 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1272 | * @mask: indicates which pages we should protect | |
1273 | * | |
1274 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1275 | * logging we do not have any such mappings. | |
1276 | */ | |
3b0f1d01 | 1277 | static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
5dc99b23 TY |
1278 | struct kvm_memory_slot *slot, |
1279 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 | 1280 | { |
018aabb5 | 1281 | struct kvm_rmap_head *rmap_head; |
a0ed4607 | 1282 | |
5dc99b23 | 1283 | while (mask) { |
018aabb5 TY |
1284 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1285 | PT_PAGE_TABLE_LEVEL, slot); | |
1286 | __rmap_write_protect(kvm, rmap_head, false); | |
05da4558 | 1287 | |
5dc99b23 TY |
1288 | /* clear the first set bit */ |
1289 | mask &= mask - 1; | |
1290 | } | |
374cbac0 AK |
1291 | } |
1292 | ||
f4b4b180 KH |
1293 | /** |
1294 | * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages | |
1295 | * @kvm: kvm instance | |
1296 | * @slot: slot to clear D-bit | |
1297 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1298 | * @mask: indicates which pages we should clear D-bit | |
1299 | * | |
1300 | * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap. | |
1301 | */ | |
1302 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
1303 | struct kvm_memory_slot *slot, | |
1304 | gfn_t gfn_offset, unsigned long mask) | |
1305 | { | |
018aabb5 | 1306 | struct kvm_rmap_head *rmap_head; |
f4b4b180 KH |
1307 | |
1308 | while (mask) { | |
018aabb5 TY |
1309 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1310 | PT_PAGE_TABLE_LEVEL, slot); | |
1311 | __rmap_clear_dirty(kvm, rmap_head); | |
f4b4b180 KH |
1312 | |
1313 | /* clear the first set bit */ | |
1314 | mask &= mask - 1; | |
1315 | } | |
1316 | } | |
1317 | EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked); | |
1318 | ||
3b0f1d01 KH |
1319 | /** |
1320 | * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected | |
1321 | * PT level pages. | |
1322 | * | |
1323 | * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to | |
1324 | * enable dirty logging for them. | |
1325 | * | |
1326 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1327 | * logging we do not have any such mappings. | |
1328 | */ | |
1329 | void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, | |
1330 | struct kvm_memory_slot *slot, | |
1331 | gfn_t gfn_offset, unsigned long mask) | |
1332 | { | |
88178fd4 KH |
1333 | if (kvm_x86_ops->enable_log_dirty_pt_masked) |
1334 | kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset, | |
1335 | mask); | |
1336 | else | |
1337 | kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); | |
3b0f1d01 KH |
1338 | } |
1339 | ||
aeecee2e XG |
1340 | bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm, |
1341 | struct kvm_memory_slot *slot, u64 gfn) | |
95d4c16c | 1342 | { |
018aabb5 | 1343 | struct kvm_rmap_head *rmap_head; |
5dc99b23 | 1344 | int i; |
2f84569f | 1345 | bool write_protected = false; |
95d4c16c | 1346 | |
8a3d08f1 | 1347 | for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { |
018aabb5 | 1348 | rmap_head = __gfn_to_rmap(gfn, i, slot); |
aeecee2e | 1349 | write_protected |= __rmap_write_protect(kvm, rmap_head, true); |
5dc99b23 TY |
1350 | } |
1351 | ||
1352 | return write_protected; | |
95d4c16c TY |
1353 | } |
1354 | ||
aeecee2e XG |
1355 | static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn) |
1356 | { | |
1357 | struct kvm_memory_slot *slot; | |
1358 | ||
1359 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
1360 | return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn); | |
1361 | } | |
1362 | ||
018aabb5 | 1363 | static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
e930bffe | 1364 | { |
1e3f42f0 TY |
1365 | u64 *sptep; |
1366 | struct rmap_iterator iter; | |
6a49f85c | 1367 | bool flush = false; |
e930bffe | 1368 | |
018aabb5 | 1369 | while ((sptep = rmap_get_first(rmap_head, &iter))) { |
6a49f85c | 1370 | rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep); |
1e3f42f0 TY |
1371 | |
1372 | drop_spte(kvm, sptep); | |
6a49f85c | 1373 | flush = true; |
e930bffe | 1374 | } |
1e3f42f0 | 1375 | |
6a49f85c XG |
1376 | return flush; |
1377 | } | |
1378 | ||
018aabb5 | 1379 | static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
6a49f85c XG |
1380 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1381 | unsigned long data) | |
1382 | { | |
018aabb5 | 1383 | return kvm_zap_rmapp(kvm, rmap_head); |
e930bffe AA |
1384 | } |
1385 | ||
018aabb5 | 1386 | static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1387 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1388 | unsigned long data) | |
3da0dd43 | 1389 | { |
1e3f42f0 TY |
1390 | u64 *sptep; |
1391 | struct rmap_iterator iter; | |
3da0dd43 | 1392 | int need_flush = 0; |
1e3f42f0 | 1393 | u64 new_spte; |
3da0dd43 | 1394 | pte_t *ptep = (pte_t *)data; |
ba049e93 | 1395 | kvm_pfn_t new_pfn; |
3da0dd43 IE |
1396 | |
1397 | WARN_ON(pte_huge(*ptep)); | |
1398 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 | 1399 | |
0d536790 | 1400 | restart: |
018aabb5 | 1401 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
8a9522d2 ALC |
1402 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n", |
1403 | sptep, *sptep, gfn, level); | |
1e3f42f0 | 1404 | |
3da0dd43 | 1405 | need_flush = 1; |
1e3f42f0 | 1406 | |
3da0dd43 | 1407 | if (pte_write(*ptep)) { |
1e3f42f0 | 1408 | drop_spte(kvm, sptep); |
0d536790 | 1409 | goto restart; |
3da0dd43 | 1410 | } else { |
1e3f42f0 | 1411 | new_spte = *sptep & ~PT64_BASE_ADDR_MASK; |
3da0dd43 IE |
1412 | new_spte |= (u64)new_pfn << PAGE_SHIFT; |
1413 | ||
1414 | new_spte &= ~PT_WRITABLE_MASK; | |
1415 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 1416 | new_spte &= ~shadow_accessed_mask; |
1e3f42f0 TY |
1417 | |
1418 | mmu_spte_clear_track_bits(sptep); | |
1419 | mmu_spte_set(sptep, new_spte); | |
3da0dd43 IE |
1420 | } |
1421 | } | |
1e3f42f0 | 1422 | |
3da0dd43 IE |
1423 | if (need_flush) |
1424 | kvm_flush_remote_tlbs(kvm); | |
1425 | ||
1426 | return 0; | |
1427 | } | |
1428 | ||
6ce1f4e2 XG |
1429 | struct slot_rmap_walk_iterator { |
1430 | /* input fields. */ | |
1431 | struct kvm_memory_slot *slot; | |
1432 | gfn_t start_gfn; | |
1433 | gfn_t end_gfn; | |
1434 | int start_level; | |
1435 | int end_level; | |
1436 | ||
1437 | /* output fields. */ | |
1438 | gfn_t gfn; | |
018aabb5 | 1439 | struct kvm_rmap_head *rmap; |
6ce1f4e2 XG |
1440 | int level; |
1441 | ||
1442 | /* private field. */ | |
018aabb5 | 1443 | struct kvm_rmap_head *end_rmap; |
6ce1f4e2 XG |
1444 | }; |
1445 | ||
1446 | static void | |
1447 | rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level) | |
1448 | { | |
1449 | iterator->level = level; | |
1450 | iterator->gfn = iterator->start_gfn; | |
1451 | iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot); | |
1452 | iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level, | |
1453 | iterator->slot); | |
1454 | } | |
1455 | ||
1456 | static void | |
1457 | slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator, | |
1458 | struct kvm_memory_slot *slot, int start_level, | |
1459 | int end_level, gfn_t start_gfn, gfn_t end_gfn) | |
1460 | { | |
1461 | iterator->slot = slot; | |
1462 | iterator->start_level = start_level; | |
1463 | iterator->end_level = end_level; | |
1464 | iterator->start_gfn = start_gfn; | |
1465 | iterator->end_gfn = end_gfn; | |
1466 | ||
1467 | rmap_walk_init_level(iterator, iterator->start_level); | |
1468 | } | |
1469 | ||
1470 | static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator) | |
1471 | { | |
1472 | return !!iterator->rmap; | |
1473 | } | |
1474 | ||
1475 | static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator) | |
1476 | { | |
1477 | if (++iterator->rmap <= iterator->end_rmap) { | |
1478 | iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level)); | |
1479 | return; | |
1480 | } | |
1481 | ||
1482 | if (++iterator->level > iterator->end_level) { | |
1483 | iterator->rmap = NULL; | |
1484 | return; | |
1485 | } | |
1486 | ||
1487 | rmap_walk_init_level(iterator, iterator->level); | |
1488 | } | |
1489 | ||
1490 | #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \ | |
1491 | _start_gfn, _end_gfn, _iter_) \ | |
1492 | for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \ | |
1493 | _end_level_, _start_gfn, _end_gfn); \ | |
1494 | slot_rmap_walk_okay(_iter_); \ | |
1495 | slot_rmap_walk_next(_iter_)) | |
1496 | ||
84504ef3 TY |
1497 | static int kvm_handle_hva_range(struct kvm *kvm, |
1498 | unsigned long start, | |
1499 | unsigned long end, | |
1500 | unsigned long data, | |
1501 | int (*handler)(struct kvm *kvm, | |
018aabb5 | 1502 | struct kvm_rmap_head *rmap_head, |
048212d0 | 1503 | struct kvm_memory_slot *slot, |
8a9522d2 ALC |
1504 | gfn_t gfn, |
1505 | int level, | |
84504ef3 | 1506 | unsigned long data)) |
e930bffe | 1507 | { |
bc6678a3 | 1508 | struct kvm_memslots *slots; |
be6ba0f0 | 1509 | struct kvm_memory_slot *memslot; |
6ce1f4e2 XG |
1510 | struct slot_rmap_walk_iterator iterator; |
1511 | int ret = 0; | |
9da0e4d5 | 1512 | int i; |
bc6678a3 | 1513 | |
9da0e4d5 PB |
1514 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1515 | slots = __kvm_memslots(kvm, i); | |
1516 | kvm_for_each_memslot(memslot, slots) { | |
1517 | unsigned long hva_start, hva_end; | |
1518 | gfn_t gfn_start, gfn_end; | |
e930bffe | 1519 | |
9da0e4d5 PB |
1520 | hva_start = max(start, memslot->userspace_addr); |
1521 | hva_end = min(end, memslot->userspace_addr + | |
1522 | (memslot->npages << PAGE_SHIFT)); | |
1523 | if (hva_start >= hva_end) | |
1524 | continue; | |
1525 | /* | |
1526 | * {gfn(page) | page intersects with [hva_start, hva_end)} = | |
1527 | * {gfn_start, gfn_start+1, ..., gfn_end-1}. | |
1528 | */ | |
1529 | gfn_start = hva_to_gfn_memslot(hva_start, memslot); | |
1530 | gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); | |
1531 | ||
1532 | for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL, | |
1533 | PT_MAX_HUGEPAGE_LEVEL, | |
1534 | gfn_start, gfn_end - 1, | |
1535 | &iterator) | |
1536 | ret |= handler(kvm, iterator.rmap, memslot, | |
1537 | iterator.gfn, iterator.level, data); | |
1538 | } | |
e930bffe AA |
1539 | } |
1540 | ||
f395302e | 1541 | return ret; |
e930bffe AA |
1542 | } |
1543 | ||
84504ef3 TY |
1544 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1545 | unsigned long data, | |
018aabb5 TY |
1546 | int (*handler)(struct kvm *kvm, |
1547 | struct kvm_rmap_head *rmap_head, | |
048212d0 | 1548 | struct kvm_memory_slot *slot, |
8a9522d2 | 1549 | gfn_t gfn, int level, |
84504ef3 TY |
1550 | unsigned long data)) |
1551 | { | |
1552 | return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler); | |
e930bffe AA |
1553 | } |
1554 | ||
1555 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
1556 | { | |
3da0dd43 IE |
1557 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
1558 | } | |
1559 | ||
b3ae2096 TY |
1560 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end) |
1561 | { | |
1562 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp); | |
1563 | } | |
1564 | ||
3da0dd43 IE |
1565 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
1566 | { | |
8a8365c5 | 1567 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1568 | } |
1569 | ||
018aabb5 | 1570 | static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1571 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1572 | unsigned long data) | |
e930bffe | 1573 | { |
1e3f42f0 | 1574 | u64 *sptep; |
79f702a6 | 1575 | struct rmap_iterator uninitialized_var(iter); |
e930bffe AA |
1576 | int young = 0; |
1577 | ||
57128468 | 1578 | BUG_ON(!shadow_accessed_mask); |
534e38b4 | 1579 | |
018aabb5 | 1580 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
3f6d8c8a | 1581 | if (*sptep & shadow_accessed_mask) { |
e930bffe | 1582 | young = 1; |
3f6d8c8a XH |
1583 | clear_bit((ffs(shadow_accessed_mask) - 1), |
1584 | (unsigned long *)sptep); | |
e930bffe | 1585 | } |
018aabb5 | 1586 | } |
0d536790 | 1587 | |
8a9522d2 | 1588 | trace_kvm_age_page(gfn, level, slot, young); |
e930bffe AA |
1589 | return young; |
1590 | } | |
1591 | ||
018aabb5 | 1592 | static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1593 | struct kvm_memory_slot *slot, gfn_t gfn, |
1594 | int level, unsigned long data) | |
8ee53820 | 1595 | { |
1e3f42f0 TY |
1596 | u64 *sptep; |
1597 | struct rmap_iterator iter; | |
8ee53820 AA |
1598 | int young = 0; |
1599 | ||
1600 | /* | |
1601 | * If there's no access bit in the secondary pte set by the | |
1602 | * hardware it's up to gup-fast/gup to set the access bit in | |
1603 | * the primary pte or in the page structure. | |
1604 | */ | |
1605 | if (!shadow_accessed_mask) | |
1606 | goto out; | |
1607 | ||
018aabb5 | 1608 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
3f6d8c8a | 1609 | if (*sptep & shadow_accessed_mask) { |
8ee53820 AA |
1610 | young = 1; |
1611 | break; | |
1612 | } | |
018aabb5 | 1613 | } |
8ee53820 AA |
1614 | out: |
1615 | return young; | |
1616 | } | |
1617 | ||
53a27b39 MT |
1618 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1619 | ||
852e3c19 | 1620 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 | 1621 | { |
018aabb5 | 1622 | struct kvm_rmap_head *rmap_head; |
852e3c19 JR |
1623 | struct kvm_mmu_page *sp; |
1624 | ||
1625 | sp = page_header(__pa(spte)); | |
53a27b39 | 1626 | |
018aabb5 | 1627 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
53a27b39 | 1628 | |
018aabb5 | 1629 | kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0); |
53a27b39 MT |
1630 | kvm_flush_remote_tlbs(vcpu->kvm); |
1631 | } | |
1632 | ||
57128468 | 1633 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end) |
e930bffe | 1634 | { |
57128468 ALC |
1635 | /* |
1636 | * In case of absence of EPT Access and Dirty Bits supports, | |
1637 | * emulate the accessed bit for EPT, by checking if this page has | |
1638 | * an EPT mapping, and clearing it if it does. On the next access, | |
1639 | * a new EPT mapping will be established. | |
1640 | * This has some overhead, but not as much as the cost of swapping | |
1641 | * out actively used pages or breaking up actively used hugepages. | |
1642 | */ | |
1643 | if (!shadow_accessed_mask) { | |
1644 | /* | |
1645 | * We are holding the kvm->mmu_lock, and we are blowing up | |
1646 | * shadow PTEs. MMU notifier consumers need to be kept at bay. | |
1647 | * This is correct as long as we don't decouple the mmu_lock | |
1648 | * protected regions (like invalidate_range_start|end does). | |
1649 | */ | |
1650 | kvm->mmu_notifier_seq++; | |
1651 | return kvm_handle_hva_range(kvm, start, end, 0, | |
1652 | kvm_unmap_rmapp); | |
1653 | } | |
1654 | ||
1655 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp); | |
e930bffe AA |
1656 | } |
1657 | ||
8ee53820 AA |
1658 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1659 | { | |
1660 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1661 | } | |
1662 | ||
d6c69ee9 | 1663 | #ifdef MMU_DEBUG |
47ad8e68 | 1664 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1665 | { |
139bdb2d AK |
1666 | u64 *pos; |
1667 | u64 *end; | |
1668 | ||
47ad8e68 | 1669 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1670 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1671 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1672 | pos, *pos); |
6aa8b732 | 1673 | return 0; |
139bdb2d | 1674 | } |
6aa8b732 AK |
1675 | return 1; |
1676 | } | |
d6c69ee9 | 1677 | #endif |
6aa8b732 | 1678 | |
45221ab6 DH |
1679 | /* |
1680 | * This value is the sum of all of the kvm instances's | |
1681 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1682 | * aggregate version in order to make the slab shrinker | |
1683 | * faster | |
1684 | */ | |
1685 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
1686 | { | |
1687 | kvm->arch.n_used_mmu_pages += nr; | |
1688 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1689 | } | |
1690 | ||
834be0d8 | 1691 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 1692 | { |
fa4a2c08 | 1693 | MMU_WARN_ON(!is_empty_shadow_page(sp->spt)); |
7775834a | 1694 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
1695 | list_del(&sp->link); |
1696 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
1697 | if (!sp->role.direct) |
1698 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 1699 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1700 | } |
1701 | ||
cea0f0e7 AK |
1702 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1703 | { | |
1ae0a13d | 1704 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
1705 | } |
1706 | ||
714b93da | 1707 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1708 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1709 | { |
cea0f0e7 AK |
1710 | if (!parent_pte) |
1711 | return; | |
cea0f0e7 | 1712 | |
67052b35 | 1713 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1714 | } |
1715 | ||
4db35314 | 1716 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1717 | u64 *parent_pte) |
1718 | { | |
67052b35 | 1719 | pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1720 | } |
1721 | ||
bcdd9a93 XG |
1722 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1723 | u64 *parent_pte) | |
1724 | { | |
1725 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1726 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1727 | } |
1728 | ||
47005792 | 1729 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct) |
ad8cfbe3 | 1730 | { |
67052b35 | 1731 | struct kvm_mmu_page *sp; |
7ddca7e4 | 1732 | |
80feb89a TY |
1733 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
1734 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); | |
67052b35 | 1735 | if (!direct) |
80feb89a | 1736 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); |
67052b35 | 1737 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
5304b8d3 XG |
1738 | |
1739 | /* | |
1740 | * The active_mmu_pages list is the FIFO list, do not move the | |
1741 | * page until it is zapped. kvm_zap_obsolete_pages depends on | |
1742 | * this feature. See the comments in kvm_zap_obsolete_pages(). | |
1743 | */ | |
67052b35 | 1744 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
67052b35 XG |
1745 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
1746 | return sp; | |
ad8cfbe3 MT |
1747 | } |
1748 | ||
67052b35 | 1749 | static void mark_unsync(u64 *spte); |
1047df1f | 1750 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1751 | { |
74c4e63a TY |
1752 | u64 *sptep; |
1753 | struct rmap_iterator iter; | |
1754 | ||
1755 | for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) { | |
1756 | mark_unsync(sptep); | |
1757 | } | |
0074ff63 MT |
1758 | } |
1759 | ||
67052b35 | 1760 | static void mark_unsync(u64 *spte) |
0074ff63 | 1761 | { |
67052b35 | 1762 | struct kvm_mmu_page *sp; |
1047df1f | 1763 | unsigned int index; |
0074ff63 | 1764 | |
67052b35 | 1765 | sp = page_header(__pa(spte)); |
1047df1f XG |
1766 | index = spte - sp->spt; |
1767 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1768 | return; |
1047df1f | 1769 | if (sp->unsync_children++) |
0074ff63 | 1770 | return; |
1047df1f | 1771 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1772 | } |
1773 | ||
e8bc217a | 1774 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1775 | struct kvm_mmu_page *sp) |
e8bc217a MT |
1776 | { |
1777 | return 1; | |
1778 | } | |
1779 | ||
a7052897 MT |
1780 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1781 | { | |
1782 | } | |
1783 | ||
0f53b5b1 XG |
1784 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1785 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 1786 | const void *pte) |
0f53b5b1 XG |
1787 | { |
1788 | WARN_ON(1); | |
1789 | } | |
1790 | ||
60c8aec6 MT |
1791 | #define KVM_PAGE_ARRAY_NR 16 |
1792 | ||
1793 | struct kvm_mmu_pages { | |
1794 | struct mmu_page_and_offset { | |
1795 | struct kvm_mmu_page *sp; | |
1796 | unsigned int idx; | |
1797 | } page[KVM_PAGE_ARRAY_NR]; | |
1798 | unsigned int nr; | |
1799 | }; | |
1800 | ||
cded19f3 HE |
1801 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1802 | int idx) | |
4731d4c7 | 1803 | { |
60c8aec6 | 1804 | int i; |
4731d4c7 | 1805 | |
60c8aec6 MT |
1806 | if (sp->unsync) |
1807 | for (i=0; i < pvec->nr; i++) | |
1808 | if (pvec->page[i].sp == sp) | |
1809 | return 0; | |
1810 | ||
1811 | pvec->page[pvec->nr].sp = sp; | |
1812 | pvec->page[pvec->nr].idx = idx; | |
1813 | pvec->nr++; | |
1814 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1815 | } | |
1816 | ||
fd951457 TY |
1817 | static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx) |
1818 | { | |
1819 | --sp->unsync_children; | |
1820 | WARN_ON((int)sp->unsync_children < 0); | |
1821 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1822 | } | |
1823 | ||
60c8aec6 MT |
1824 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, |
1825 | struct kvm_mmu_pages *pvec) | |
1826 | { | |
1827 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1828 | |
37178b8b | 1829 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 1830 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1831 | u64 ent = sp->spt[i]; |
1832 | ||
fd951457 TY |
1833 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) { |
1834 | clear_unsync_child_bit(sp, i); | |
1835 | continue; | |
1836 | } | |
7a8f1a74 XG |
1837 | |
1838 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1839 | ||
1840 | if (child->unsync_children) { | |
1841 | if (mmu_pages_add(pvec, child, i)) | |
1842 | return -ENOSPC; | |
1843 | ||
1844 | ret = __mmu_unsync_walk(child, pvec); | |
fd951457 TY |
1845 | if (!ret) { |
1846 | clear_unsync_child_bit(sp, i); | |
1847 | continue; | |
1848 | } else if (ret > 0) { | |
7a8f1a74 | 1849 | nr_unsync_leaf += ret; |
fd951457 | 1850 | } else |
7a8f1a74 XG |
1851 | return ret; |
1852 | } else if (child->unsync) { | |
1853 | nr_unsync_leaf++; | |
1854 | if (mmu_pages_add(pvec, child, i)) | |
1855 | return -ENOSPC; | |
1856 | } else | |
fd951457 | 1857 | clear_unsync_child_bit(sp, i); |
4731d4c7 MT |
1858 | } |
1859 | ||
60c8aec6 MT |
1860 | return nr_unsync_leaf; |
1861 | } | |
1862 | ||
1863 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1864 | struct kvm_mmu_pages *pvec) | |
1865 | { | |
1866 | if (!sp->unsync_children) | |
1867 | return 0; | |
1868 | ||
1869 | mmu_pages_add(pvec, sp, 0); | |
1870 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1871 | } |
1872 | ||
4731d4c7 MT |
1873 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1874 | { | |
1875 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1876 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1877 | sp->unsync = 0; |
1878 | --kvm->stat.mmu_unsync; | |
1879 | } | |
1880 | ||
7775834a XG |
1881 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1882 | struct list_head *invalid_list); | |
1883 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1884 | struct list_head *invalid_list); | |
4731d4c7 | 1885 | |
f34d251d XG |
1886 | /* |
1887 | * NOTE: we should pay more attention on the zapped-obsolete page | |
1888 | * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk | |
1889 | * since it has been deleted from active_mmu_pages but still can be found | |
1890 | * at hast list. | |
1891 | * | |
1892 | * for_each_gfn_indirect_valid_sp has skipped that kind of page and | |
1893 | * kvm_mmu_get_page(), the only user of for_each_gfn_sp(), has skipped | |
1894 | * all the obsolete pages. | |
1895 | */ | |
1044b030 TY |
1896 | #define for_each_gfn_sp(_kvm, _sp, _gfn) \ |
1897 | hlist_for_each_entry(_sp, \ | |
1898 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \ | |
1899 | if ((_sp)->gfn != (_gfn)) {} else | |
1900 | ||
1901 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
1902 | for_each_gfn_sp(_kvm, _sp, _gfn) \ | |
1903 | if ((_sp)->role.direct || (_sp)->role.invalid) {} else | |
7ae680eb | 1904 | |
f918b443 | 1905 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1906 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1907 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1908 | { |
5b7e0102 | 1909 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1910 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1911 | return 1; |
1912 | } | |
1913 | ||
f918b443 | 1914 | if (clear_unsync) |
1d9dc7e0 | 1915 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1916 | |
a4a8e6f7 | 1917 | if (vcpu->arch.mmu.sync_page(vcpu, sp)) { |
d98ba053 | 1918 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1919 | return 1; |
1920 | } | |
1921 | ||
77c3913b | 1922 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
4731d4c7 MT |
1923 | return 0; |
1924 | } | |
1925 | ||
1d9dc7e0 XG |
1926 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1927 | struct kvm_mmu_page *sp) | |
1928 | { | |
d98ba053 | 1929 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1930 | int ret; |
1931 | ||
d98ba053 | 1932 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1933 | if (ret) |
d98ba053 XG |
1934 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1935 | ||
1d9dc7e0 XG |
1936 | return ret; |
1937 | } | |
1938 | ||
e37fa785 XG |
1939 | #ifdef CONFIG_KVM_MMU_AUDIT |
1940 | #include "mmu_audit.c" | |
1941 | #else | |
1942 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
1943 | static void mmu_audit_disable(void) { } | |
1944 | #endif | |
1945 | ||
d98ba053 XG |
1946 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1947 | struct list_head *invalid_list) | |
1d9dc7e0 | 1948 | { |
d98ba053 | 1949 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1950 | } |
1951 | ||
9f1a122f XG |
1952 | /* @gfn should be write-protected at the call site */ |
1953 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1954 | { | |
9f1a122f | 1955 | struct kvm_mmu_page *s; |
d98ba053 | 1956 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1957 | bool flush = false; |
1958 | ||
b67bfe0d | 1959 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 1960 | if (!s->unsync) |
9f1a122f XG |
1961 | continue; |
1962 | ||
1963 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
a4a8e6f7 | 1964 | kvm_unlink_unsync_page(vcpu->kvm, s); |
9f1a122f | 1965 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || |
a4a8e6f7 | 1966 | (vcpu->arch.mmu.sync_page(vcpu, s))) { |
d98ba053 | 1967 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1968 | continue; |
1969 | } | |
9f1a122f XG |
1970 | flush = true; |
1971 | } | |
1972 | ||
d98ba053 | 1973 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f | 1974 | if (flush) |
77c3913b | 1975 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
9f1a122f XG |
1976 | } |
1977 | ||
60c8aec6 MT |
1978 | struct mmu_page_path { |
1979 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1980 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1981 | }; |
1982 | ||
60c8aec6 MT |
1983 | #define for_each_sp(pvec, sp, parents, i) \ |
1984 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1985 | sp = pvec.page[i].sp; \ | |
1986 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1987 | i = mmu_pages_next(&pvec, &parents, i)) | |
1988 | ||
cded19f3 HE |
1989 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1990 | struct mmu_page_path *parents, | |
1991 | int i) | |
60c8aec6 MT |
1992 | { |
1993 | int n; | |
1994 | ||
1995 | for (n = i+1; n < pvec->nr; n++) { | |
1996 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1997 | ||
1998 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1999 | parents->idx[0] = pvec->page[n].idx; | |
2000 | return n; | |
2001 | } | |
2002 | ||
2003 | parents->parent[sp->role.level-2] = sp; | |
2004 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
2005 | } | |
2006 | ||
2007 | return n; | |
2008 | } | |
2009 | ||
cded19f3 | 2010 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 2011 | { |
60c8aec6 MT |
2012 | struct kvm_mmu_page *sp; |
2013 | unsigned int level = 0; | |
2014 | ||
2015 | do { | |
2016 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 2017 | |
60c8aec6 MT |
2018 | sp = parents->parent[level]; |
2019 | if (!sp) | |
2020 | return; | |
2021 | ||
fd951457 | 2022 | clear_unsync_child_bit(sp, idx); |
60c8aec6 MT |
2023 | level++; |
2024 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
2025 | } |
2026 | ||
60c8aec6 MT |
2027 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
2028 | struct mmu_page_path *parents, | |
2029 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 2030 | { |
60c8aec6 MT |
2031 | parents->parent[parent->role.level-1] = NULL; |
2032 | pvec->nr = 0; | |
2033 | } | |
4731d4c7 | 2034 | |
60c8aec6 MT |
2035 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
2036 | struct kvm_mmu_page *parent) | |
2037 | { | |
2038 | int i; | |
2039 | struct kvm_mmu_page *sp; | |
2040 | struct mmu_page_path parents; | |
2041 | struct kvm_mmu_pages pages; | |
d98ba053 | 2042 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
2043 | |
2044 | kvm_mmu_pages_init(parent, &parents, &pages); | |
2045 | while (mmu_unsync_walk(parent, &pages)) { | |
2f84569f | 2046 | bool protected = false; |
b1a36821 MT |
2047 | |
2048 | for_each_sp(pages, sp, parents, i) | |
54bf36aa | 2049 | protected |= rmap_write_protect(vcpu, sp->gfn); |
b1a36821 MT |
2050 | |
2051 | if (protected) | |
2052 | kvm_flush_remote_tlbs(vcpu->kvm); | |
2053 | ||
60c8aec6 | 2054 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 2055 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
2056 | mmu_pages_clear_parents(&parents); |
2057 | } | |
d98ba053 | 2058 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 2059 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
2060 | kvm_mmu_pages_init(parent, &parents, &pages); |
2061 | } | |
4731d4c7 MT |
2062 | } |
2063 | ||
a30f47cb XG |
2064 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
2065 | { | |
e5691a81 | 2066 | atomic_set(&sp->write_flooding_count, 0); |
a30f47cb XG |
2067 | } |
2068 | ||
2069 | static void clear_sp_write_flooding_count(u64 *spte) | |
2070 | { | |
2071 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
2072 | ||
2073 | __clear_sp_write_flooding_count(sp); | |
2074 | } | |
2075 | ||
5304b8d3 XG |
2076 | static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) |
2077 | { | |
2078 | return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); | |
2079 | } | |
2080 | ||
cea0f0e7 AK |
2081 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
2082 | gfn_t gfn, | |
2083 | gva_t gaddr, | |
2084 | unsigned level, | |
f6e2c02b | 2085 | int direct, |
bb11c6c9 | 2086 | unsigned access) |
cea0f0e7 AK |
2087 | { |
2088 | union kvm_mmu_page_role role; | |
cea0f0e7 | 2089 | unsigned quadrant; |
9f1a122f | 2090 | struct kvm_mmu_page *sp; |
9f1a122f | 2091 | bool need_sync = false; |
cea0f0e7 | 2092 | |
a770f6f2 | 2093 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 2094 | role.level = level; |
f6e2c02b | 2095 | role.direct = direct; |
84b0c8c6 | 2096 | if (role.direct) |
5b7e0102 | 2097 | role.cr4_pae = 0; |
41074d07 | 2098 | role.access = access; |
c5a78f2b JR |
2099 | if (!vcpu->arch.mmu.direct_map |
2100 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
2101 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
2102 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
2103 | role.quadrant = quadrant; | |
2104 | } | |
b67bfe0d | 2105 | for_each_gfn_sp(vcpu->kvm, sp, gfn) { |
7f52af74 XG |
2106 | if (is_obsolete_sp(vcpu->kvm, sp)) |
2107 | continue; | |
2108 | ||
7ae680eb XG |
2109 | if (!need_sync && sp->unsync) |
2110 | need_sync = true; | |
4731d4c7 | 2111 | |
7ae680eb XG |
2112 | if (sp->role.word != role.word) |
2113 | continue; | |
4731d4c7 | 2114 | |
7ae680eb XG |
2115 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
2116 | break; | |
e02aa901 | 2117 | |
98bba238 | 2118 | if (sp->unsync_children) |
a8eeb04a | 2119 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
e02aa901 | 2120 | |
a30f47cb | 2121 | __clear_sp_write_flooding_count(sp); |
7ae680eb XG |
2122 | trace_kvm_mmu_get_page(sp, false); |
2123 | return sp; | |
2124 | } | |
47005792 | 2125 | |
dfc5aa00 | 2126 | ++vcpu->kvm->stat.mmu_cache_miss; |
47005792 TY |
2127 | |
2128 | sp = kvm_mmu_alloc_page(vcpu, direct); | |
2129 | ||
4db35314 AK |
2130 | sp->gfn = gfn; |
2131 | sp->role = role; | |
7ae680eb XG |
2132 | hlist_add_head(&sp->hash_link, |
2133 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 2134 | if (!direct) { |
54bf36aa | 2135 | if (rmap_write_protect(vcpu, gfn)) |
b1a36821 | 2136 | kvm_flush_remote_tlbs(vcpu->kvm); |
9f1a122f XG |
2137 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
2138 | kvm_sync_pages(vcpu, gfn); | |
2139 | ||
3ed1a478 | 2140 | account_shadowed(vcpu->kvm, sp); |
4731d4c7 | 2141 | } |
5304b8d3 | 2142 | sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen; |
77492664 | 2143 | clear_page(sp->spt); |
f691fe1d | 2144 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 2145 | return sp; |
cea0f0e7 AK |
2146 | } |
2147 | ||
2d11123a AK |
2148 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
2149 | struct kvm_vcpu *vcpu, u64 addr) | |
2150 | { | |
2151 | iterator->addr = addr; | |
2152 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
2153 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 JR |
2154 | |
2155 | if (iterator->level == PT64_ROOT_LEVEL && | |
2156 | vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL && | |
2157 | !vcpu->arch.mmu.direct_map) | |
2158 | --iterator->level; | |
2159 | ||
2d11123a AK |
2160 | if (iterator->level == PT32E_ROOT_LEVEL) { |
2161 | iterator->shadow_addr | |
2162 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
2163 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
2164 | --iterator->level; | |
2165 | if (!iterator->shadow_addr) | |
2166 | iterator->level = 0; | |
2167 | } | |
2168 | } | |
2169 | ||
2170 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
2171 | { | |
2172 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
2173 | return false; | |
4d88954d | 2174 | |
2d11123a AK |
2175 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
2176 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
2177 | return true; | |
2178 | } | |
2179 | ||
c2a2ac2b XG |
2180 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
2181 | u64 spte) | |
2d11123a | 2182 | { |
c2a2ac2b | 2183 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
2184 | iterator->level = 0; |
2185 | return; | |
2186 | } | |
2187 | ||
c2a2ac2b | 2188 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
2189 | --iterator->level; |
2190 | } | |
2191 | ||
c2a2ac2b XG |
2192 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
2193 | { | |
2194 | return __shadow_walk_next(iterator, *iterator->sptep); | |
2195 | } | |
2196 | ||
98bba238 TY |
2197 | static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep, |
2198 | struct kvm_mmu_page *sp) | |
32ef26a3 AK |
2199 | { |
2200 | u64 spte; | |
2201 | ||
7a1638ce YZ |
2202 | BUILD_BUG_ON(VMX_EPT_READABLE_MASK != PT_PRESENT_MASK || |
2203 | VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK); | |
2204 | ||
24db2734 | 2205 | spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
0e3d0648 | 2206 | shadow_user_mask | shadow_x_mask | shadow_accessed_mask; |
24db2734 | 2207 | |
1df9f2dc | 2208 | mmu_spte_set(sptep, spte); |
98bba238 TY |
2209 | |
2210 | mmu_page_add_parent_pte(vcpu, sp, sptep); | |
2211 | ||
2212 | if (sp->unsync_children || sp->unsync) | |
2213 | mark_unsync(sptep); | |
32ef26a3 AK |
2214 | } |
2215 | ||
a357bd22 AK |
2216 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2217 | unsigned direct_access) | |
2218 | { | |
2219 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
2220 | struct kvm_mmu_page *child; | |
2221 | ||
2222 | /* | |
2223 | * For the direct sp, if the guest pte's dirty bit | |
2224 | * changed form clean to dirty, it will corrupt the | |
2225 | * sp's access: allow writable in the read-only sp, | |
2226 | * so we should update the spte at this point to get | |
2227 | * a new sp with the correct access. | |
2228 | */ | |
2229 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
2230 | if (child->role.access == direct_access) | |
2231 | return; | |
2232 | ||
bcdd9a93 | 2233 | drop_parent_pte(child, sptep); |
a357bd22 AK |
2234 | kvm_flush_remote_tlbs(vcpu->kvm); |
2235 | } | |
2236 | } | |
2237 | ||
505aef8f | 2238 | static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
38e3b2b2 XG |
2239 | u64 *spte) |
2240 | { | |
2241 | u64 pte; | |
2242 | struct kvm_mmu_page *child; | |
2243 | ||
2244 | pte = *spte; | |
2245 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2246 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2247 | drop_spte(kvm, spte); |
505aef8f XG |
2248 | if (is_large_pte(pte)) |
2249 | --kvm->stat.lpages; | |
2250 | } else { | |
38e3b2b2 | 2251 | child = page_header(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2252 | drop_parent_pte(child, spte); |
38e3b2b2 | 2253 | } |
505aef8f XG |
2254 | return true; |
2255 | } | |
2256 | ||
2257 | if (is_mmio_spte(pte)) | |
ce88decf | 2258 | mmu_spte_clear_no_track(spte); |
c3707958 | 2259 | |
505aef8f | 2260 | return false; |
38e3b2b2 XG |
2261 | } |
2262 | ||
90cb0529 | 2263 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 2264 | struct kvm_mmu_page *sp) |
a436036b | 2265 | { |
697fe2e2 | 2266 | unsigned i; |
697fe2e2 | 2267 | |
38e3b2b2 XG |
2268 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2269 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
2270 | } |
2271 | ||
31aa2b44 | 2272 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2273 | { |
1e3f42f0 TY |
2274 | u64 *sptep; |
2275 | struct rmap_iterator iter; | |
a436036b | 2276 | |
018aabb5 | 2277 | while ((sptep = rmap_get_first(&sp->parent_ptes, &iter))) |
1e3f42f0 | 2278 | drop_parent_pte(sp, sptep); |
31aa2b44 AK |
2279 | } |
2280 | ||
60c8aec6 | 2281 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2282 | struct kvm_mmu_page *parent, |
2283 | struct list_head *invalid_list) | |
4731d4c7 | 2284 | { |
60c8aec6 MT |
2285 | int i, zapped = 0; |
2286 | struct mmu_page_path parents; | |
2287 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2288 | |
60c8aec6 | 2289 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2290 | return 0; |
60c8aec6 MT |
2291 | |
2292 | kvm_mmu_pages_init(parent, &parents, &pages); | |
2293 | while (mmu_unsync_walk(parent, &pages)) { | |
2294 | struct kvm_mmu_page *sp; | |
2295 | ||
2296 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2297 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2298 | mmu_pages_clear_parents(&parents); |
77662e00 | 2299 | zapped++; |
60c8aec6 | 2300 | } |
60c8aec6 MT |
2301 | kvm_mmu_pages_init(parent, &parents, &pages); |
2302 | } | |
2303 | ||
2304 | return zapped; | |
4731d4c7 MT |
2305 | } |
2306 | ||
7775834a XG |
2307 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2308 | struct list_head *invalid_list) | |
31aa2b44 | 2309 | { |
4731d4c7 | 2310 | int ret; |
f691fe1d | 2311 | |
7775834a | 2312 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2313 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 2314 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 2315 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 2316 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2317 | |
f6e2c02b | 2318 | if (!sp->role.invalid && !sp->role.direct) |
3ed1a478 | 2319 | unaccount_shadowed(kvm, sp); |
5304b8d3 | 2320 | |
4731d4c7 MT |
2321 | if (sp->unsync) |
2322 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2323 | if (!sp->root_count) { |
54a4f023 GJ |
2324 | /* Count self */ |
2325 | ret++; | |
7775834a | 2326 | list_move(&sp->link, invalid_list); |
aa6bd187 | 2327 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2328 | } else { |
5b5c6a5a | 2329 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
05988d72 GN |
2330 | |
2331 | /* | |
2332 | * The obsolete pages can not be used on any vcpus. | |
2333 | * See the comments in kvm_mmu_invalidate_zap_all_pages(). | |
2334 | */ | |
2335 | if (!sp->role.invalid && !is_obsolete_sp(kvm, sp)) | |
2336 | kvm_reload_remote_mmus(kvm); | |
2e53d63a | 2337 | } |
7775834a XG |
2338 | |
2339 | sp->role.invalid = 1; | |
4731d4c7 | 2340 | return ret; |
a436036b AK |
2341 | } |
2342 | ||
7775834a XG |
2343 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2344 | struct list_head *invalid_list) | |
2345 | { | |
945315b9 | 2346 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2347 | |
2348 | if (list_empty(invalid_list)) | |
2349 | return; | |
2350 | ||
c142786c AK |
2351 | /* |
2352 | * wmb: make sure everyone sees our modifications to the page tables | |
2353 | * rmb: make sure we see changes to vcpu->mode | |
2354 | */ | |
2355 | smp_mb(); | |
4f022648 | 2356 | |
c142786c AK |
2357 | /* |
2358 | * Wait for all vcpus to exit guest mode and/or lockless shadow | |
2359 | * page table walks. | |
2360 | */ | |
2361 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2362 | |
945315b9 | 2363 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2364 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2365 | kvm_mmu_free_page(sp); |
945315b9 | 2366 | } |
7775834a XG |
2367 | } |
2368 | ||
5da59607 TY |
2369 | static bool prepare_zap_oldest_mmu_page(struct kvm *kvm, |
2370 | struct list_head *invalid_list) | |
2371 | { | |
2372 | struct kvm_mmu_page *sp; | |
2373 | ||
2374 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
2375 | return false; | |
2376 | ||
d74c0e6b GT |
2377 | sp = list_last_entry(&kvm->arch.active_mmu_pages, |
2378 | struct kvm_mmu_page, link); | |
5da59607 TY |
2379 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
2380 | ||
2381 | return true; | |
2382 | } | |
2383 | ||
82ce2c96 IE |
2384 | /* |
2385 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2386 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2387 | */ |
49d5ca26 | 2388 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 2389 | { |
d98ba053 | 2390 | LIST_HEAD(invalid_list); |
82ce2c96 | 2391 | |
b34cb590 TY |
2392 | spin_lock(&kvm->mmu_lock); |
2393 | ||
49d5ca26 | 2394 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
5da59607 TY |
2395 | /* Need to free some mmu pages to achieve the goal. */ |
2396 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) | |
2397 | if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list)) | |
2398 | break; | |
82ce2c96 | 2399 | |
aa6bd187 | 2400 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 2401 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2402 | } |
82ce2c96 | 2403 | |
49d5ca26 | 2404 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 TY |
2405 | |
2406 | spin_unlock(&kvm->mmu_lock); | |
82ce2c96 IE |
2407 | } |
2408 | ||
1cb3f3ae | 2409 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2410 | { |
4db35314 | 2411 | struct kvm_mmu_page *sp; |
d98ba053 | 2412 | LIST_HEAD(invalid_list); |
a436036b AK |
2413 | int r; |
2414 | ||
9ad17b10 | 2415 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2416 | r = 0; |
1cb3f3ae | 2417 | spin_lock(&kvm->mmu_lock); |
b67bfe0d | 2418 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2419 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2420 | sp->role.word); |
2421 | r = 1; | |
f41d335a | 2422 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2423 | } |
d98ba053 | 2424 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2425 | spin_unlock(&kvm->mmu_lock); |
2426 | ||
a436036b | 2427 | return r; |
cea0f0e7 | 2428 | } |
1cb3f3ae | 2429 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2430 | |
9cf5cf5a XG |
2431 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
2432 | { | |
2433 | trace_kvm_mmu_unsync_page(sp); | |
2434 | ++vcpu->kvm->stat.mmu_unsync; | |
2435 | sp->unsync = 1; | |
2436 | ||
2437 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2438 | } |
2439 | ||
2440 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 2441 | { |
4731d4c7 | 2442 | struct kvm_mmu_page *s; |
9cf5cf5a | 2443 | |
b67bfe0d | 2444 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 2445 | if (s->unsync) |
4731d4c7 | 2446 | continue; |
9cf5cf5a XG |
2447 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
2448 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 2449 | } |
4731d4c7 MT |
2450 | } |
2451 | ||
3d0c27ad XG |
2452 | static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, |
2453 | bool can_unsync) | |
4731d4c7 | 2454 | { |
9cf5cf5a | 2455 | struct kvm_mmu_page *s; |
9cf5cf5a XG |
2456 | bool need_unsync = false; |
2457 | ||
3d0c27ad XG |
2458 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) |
2459 | return true; | |
2460 | ||
b67bfe0d | 2461 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
36a2e677 | 2462 | if (!can_unsync) |
3d0c27ad | 2463 | return true; |
36a2e677 | 2464 | |
9cf5cf5a | 2465 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
3d0c27ad | 2466 | return true; |
9cf5cf5a | 2467 | |
9bb4f6b1 | 2468 | if (!s->unsync) |
9cf5cf5a | 2469 | need_unsync = true; |
4731d4c7 | 2470 | } |
9cf5cf5a XG |
2471 | if (need_unsync) |
2472 | kvm_unsync_pages(vcpu, gfn); | |
3d0c27ad XG |
2473 | |
2474 | return false; | |
4731d4c7 MT |
2475 | } |
2476 | ||
ba049e93 | 2477 | static bool kvm_is_mmio_pfn(kvm_pfn_t pfn) |
d1fe9219 PB |
2478 | { |
2479 | if (pfn_valid(pfn)) | |
2480 | return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)); | |
2481 | ||
2482 | return true; | |
2483 | } | |
2484 | ||
d555c333 | 2485 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
c2288505 | 2486 | unsigned pte_access, int level, |
ba049e93 | 2487 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, |
9bdbba13 | 2488 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2489 | { |
6e7d0354 | 2490 | u64 spte; |
1e73f9dd | 2491 | int ret = 0; |
64d4d521 | 2492 | |
54bf36aa | 2493 | if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access)) |
ce88decf XG |
2494 | return 0; |
2495 | ||
982c2565 | 2496 | spte = PT_PRESENT_MASK; |
947da538 | 2497 | if (!speculative) |
3201b5d9 | 2498 | spte |= shadow_accessed_mask; |
640d9b0d | 2499 | |
7b52345e SY |
2500 | if (pte_access & ACC_EXEC_MASK) |
2501 | spte |= shadow_x_mask; | |
2502 | else | |
2503 | spte |= shadow_nx_mask; | |
49fde340 | 2504 | |
1c4f1fd6 | 2505 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2506 | spte |= shadow_user_mask; |
49fde340 | 2507 | |
852e3c19 | 2508 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2509 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2510 | if (tdp_enabled) |
4b12f0de | 2511 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
d1fe9219 | 2512 | kvm_is_mmio_pfn(pfn)); |
1c4f1fd6 | 2513 | |
9bdbba13 | 2514 | if (host_writable) |
1403283a | 2515 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2516 | else |
2517 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2518 | |
35149e21 | 2519 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 | 2520 | |
c2288505 | 2521 | if (pte_access & ACC_WRITE_MASK) { |
1c4f1fd6 | 2522 | |
c2193463 | 2523 | /* |
7751babd XG |
2524 | * Other vcpu creates new sp in the window between |
2525 | * mapping_level() and acquiring mmu-lock. We can | |
2526 | * allow guest to retry the access, the mapping can | |
2527 | * be fixed if guest refault. | |
c2193463 | 2528 | */ |
852e3c19 | 2529 | if (level > PT_PAGE_TABLE_LEVEL && |
92f94f1e | 2530 | mmu_gfn_lpage_is_disallowed(vcpu, gfn, level)) |
be38d276 | 2531 | goto done; |
38187c83 | 2532 | |
49fde340 | 2533 | spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE; |
1c4f1fd6 | 2534 | |
ecc5589f MT |
2535 | /* |
2536 | * Optimization: for pte sync, if spte was writable the hash | |
2537 | * lookup is unnecessary (and expensive). Write protection | |
2538 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2539 | * Same reasoning can be applied to dirty page accounting. | |
2540 | */ | |
8dae4445 | 2541 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2542 | goto set_pte; |
2543 | ||
4731d4c7 | 2544 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2545 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2546 | __func__, gfn); |
1e73f9dd | 2547 | ret = 1; |
1c4f1fd6 | 2548 | pte_access &= ~ACC_WRITE_MASK; |
49fde340 | 2549 | spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE); |
1c4f1fd6 AK |
2550 | } |
2551 | } | |
2552 | ||
9b51a630 | 2553 | if (pte_access & ACC_WRITE_MASK) { |
54bf36aa | 2554 | kvm_vcpu_mark_page_dirty(vcpu, gfn); |
9b51a630 KH |
2555 | spte |= shadow_dirty_mask; |
2556 | } | |
1c4f1fd6 | 2557 | |
38187c83 | 2558 | set_pte: |
6e7d0354 | 2559 | if (mmu_spte_update(sptep, spte)) |
b330aa0c | 2560 | kvm_flush_remote_tlbs(vcpu->kvm); |
be38d276 | 2561 | done: |
1e73f9dd MT |
2562 | return ret; |
2563 | } | |
2564 | ||
029499b4 | 2565 | static bool mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access, |
ba049e93 | 2566 | int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn, |
029499b4 | 2567 | bool speculative, bool host_writable) |
1e73f9dd MT |
2568 | { |
2569 | int was_rmapped = 0; | |
53a27b39 | 2570 | int rmap_count; |
029499b4 | 2571 | bool emulate = false; |
1e73f9dd | 2572 | |
f7616203 XG |
2573 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
2574 | *sptep, write_fault, gfn); | |
1e73f9dd | 2575 | |
afd28fe1 | 2576 | if (is_shadow_present_pte(*sptep)) { |
1e73f9dd MT |
2577 | /* |
2578 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2579 | * the parent of the now unreachable PTE. | |
2580 | */ | |
852e3c19 JR |
2581 | if (level > PT_PAGE_TABLE_LEVEL && |
2582 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2583 | struct kvm_mmu_page *child; |
d555c333 | 2584 | u64 pte = *sptep; |
1e73f9dd MT |
2585 | |
2586 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 2587 | drop_parent_pte(child, sptep); |
3be2264b | 2588 | kvm_flush_remote_tlbs(vcpu->kvm); |
d555c333 | 2589 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2590 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2591 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2592 | drop_spte(vcpu->kvm, sptep); |
91546356 | 2593 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2594 | } else |
2595 | was_rmapped = 1; | |
1e73f9dd | 2596 | } |
852e3c19 | 2597 | |
c2288505 XG |
2598 | if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative, |
2599 | true, host_writable)) { | |
1e73f9dd | 2600 | if (write_fault) |
029499b4 | 2601 | emulate = true; |
77c3913b | 2602 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
a378b4e6 | 2603 | } |
1e73f9dd | 2604 | |
029499b4 TY |
2605 | if (unlikely(is_mmio_spte(*sptep))) |
2606 | emulate = true; | |
ce88decf | 2607 | |
d555c333 | 2608 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2609 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2610 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
2611 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
2612 | *sptep, sptep); | |
d555c333 | 2613 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2614 | ++vcpu->kvm->stat.lpages; |
2615 | ||
ffb61bb3 | 2616 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
2617 | if (!was_rmapped) { |
2618 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2619 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2620 | rmap_recycle(vcpu, sptep, gfn); | |
2621 | } | |
1c4f1fd6 | 2622 | } |
cb9aaa30 | 2623 | |
f3ac1a4b | 2624 | kvm_release_pfn_clean(pfn); |
029499b4 TY |
2625 | |
2626 | return emulate; | |
1c4f1fd6 AK |
2627 | } |
2628 | ||
ba049e93 | 2629 | static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
957ed9ef XG |
2630 | bool no_dirty_log) |
2631 | { | |
2632 | struct kvm_memory_slot *slot; | |
957ed9ef | 2633 | |
5d163b1c | 2634 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 2635 | if (!slot) |
6c8ee57b | 2636 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 2637 | |
037d92dc | 2638 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
2639 | } |
2640 | ||
2641 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2642 | struct kvm_mmu_page *sp, | |
2643 | u64 *start, u64 *end) | |
2644 | { | |
2645 | struct page *pages[PTE_PREFETCH_NUM]; | |
d9ef13c2 | 2646 | struct kvm_memory_slot *slot; |
957ed9ef XG |
2647 | unsigned access = sp->role.access; |
2648 | int i, ret; | |
2649 | gfn_t gfn; | |
2650 | ||
2651 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
d9ef13c2 PB |
2652 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK); |
2653 | if (!slot) | |
957ed9ef XG |
2654 | return -1; |
2655 | ||
d9ef13c2 | 2656 | ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start); |
957ed9ef XG |
2657 | if (ret <= 0) |
2658 | return -1; | |
2659 | ||
2660 | for (i = 0; i < ret; i++, gfn++, start++) | |
029499b4 TY |
2661 | mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn, |
2662 | page_to_pfn(pages[i]), true, true); | |
957ed9ef XG |
2663 | |
2664 | return 0; | |
2665 | } | |
2666 | ||
2667 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2668 | struct kvm_mmu_page *sp, u64 *sptep) | |
2669 | { | |
2670 | u64 *spte, *start = NULL; | |
2671 | int i; | |
2672 | ||
2673 | WARN_ON(!sp->role.direct); | |
2674 | ||
2675 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2676 | spte = sp->spt + i; | |
2677 | ||
2678 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2679 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2680 | if (!start) |
2681 | continue; | |
2682 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2683 | break; | |
2684 | start = NULL; | |
2685 | } else if (!start) | |
2686 | start = spte; | |
2687 | } | |
2688 | } | |
2689 | ||
2690 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2691 | { | |
2692 | struct kvm_mmu_page *sp; | |
2693 | ||
2694 | /* | |
2695 | * Since it's no accessed bit on EPT, it's no way to | |
2696 | * distinguish between actually accessed translations | |
2697 | * and prefetched, so disable pte prefetch if EPT is | |
2698 | * enabled. | |
2699 | */ | |
2700 | if (!shadow_accessed_mask) | |
2701 | return; | |
2702 | ||
2703 | sp = page_header(__pa(sptep)); | |
2704 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2705 | return; | |
2706 | ||
2707 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2708 | } | |
2709 | ||
7ee0e5b2 | 2710 | static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable, |
ba049e93 | 2711 | int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault) |
140754bc | 2712 | { |
9f652d21 | 2713 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2714 | struct kvm_mmu_page *sp; |
b90a0e6c | 2715 | int emulate = 0; |
140754bc | 2716 | gfn_t pseudo_gfn; |
6aa8b732 | 2717 | |
989c6b34 MT |
2718 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2719 | return 0; | |
2720 | ||
9f652d21 | 2721 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2722 | if (iterator.level == level) { |
029499b4 TY |
2723 | emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, |
2724 | write, level, gfn, pfn, prefault, | |
2725 | map_writable); | |
957ed9ef | 2726 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2727 | ++vcpu->stat.pf_fixed; |
2728 | break; | |
6aa8b732 AK |
2729 | } |
2730 | ||
404381c5 | 2731 | drop_large_spte(vcpu, iterator.sptep); |
c3707958 | 2732 | if (!is_shadow_present_pte(*iterator.sptep)) { |
c9fa0b3b LJ |
2733 | u64 base_addr = iterator.addr; |
2734 | ||
2735 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2736 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 | 2737 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
bb11c6c9 | 2738 | iterator.level - 1, 1, ACC_ALL); |
140754bc | 2739 | |
98bba238 | 2740 | link_shadow_page(vcpu, iterator.sptep, sp); |
9f652d21 AK |
2741 | } |
2742 | } | |
b90a0e6c | 2743 | return emulate; |
6aa8b732 AK |
2744 | } |
2745 | ||
77db5cbd | 2746 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2747 | { |
77db5cbd HY |
2748 | siginfo_t info; |
2749 | ||
2750 | info.si_signo = SIGBUS; | |
2751 | info.si_errno = 0; | |
2752 | info.si_code = BUS_MCEERR_AR; | |
2753 | info.si_addr = (void __user *)address; | |
2754 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 2755 | |
77db5cbd | 2756 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
2757 | } |
2758 | ||
ba049e93 | 2759 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn) |
bf998156 | 2760 | { |
4d8b81ab XG |
2761 | /* |
2762 | * Do not cache the mmio info caused by writing the readonly gfn | |
2763 | * into the spte otherwise read access on readonly gfn also can | |
2764 | * caused mmio page fault and treat it as mmio access. | |
2765 | * Return 1 to tell kvm to emulate it. | |
2766 | */ | |
2767 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
2768 | return 1; | |
2769 | ||
e6c1502b | 2770 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
54bf36aa | 2771 | kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current); |
bf998156 | 2772 | return 0; |
d7c55201 | 2773 | } |
edba23e5 | 2774 | |
d7c55201 | 2775 | return -EFAULT; |
bf998156 HY |
2776 | } |
2777 | ||
936a5fe6 | 2778 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
ba049e93 DW |
2779 | gfn_t *gfnp, kvm_pfn_t *pfnp, |
2780 | int *levelp) | |
936a5fe6 | 2781 | { |
ba049e93 | 2782 | kvm_pfn_t pfn = *pfnp; |
936a5fe6 AA |
2783 | gfn_t gfn = *gfnp; |
2784 | int level = *levelp; | |
2785 | ||
2786 | /* | |
2787 | * Check if it's a transparent hugepage. If this would be an | |
2788 | * hugetlbfs page, level wouldn't be set to | |
2789 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
2790 | * here. | |
2791 | */ | |
bf4bea8e | 2792 | if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) && |
936a5fe6 AA |
2793 | level == PT_PAGE_TABLE_LEVEL && |
2794 | PageTransCompound(pfn_to_page(pfn)) && | |
92f94f1e | 2795 | !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) { |
936a5fe6 AA |
2796 | unsigned long mask; |
2797 | /* | |
2798 | * mmu_notifier_retry was successful and we hold the | |
2799 | * mmu_lock here, so the pmd can't become splitting | |
2800 | * from under us, and in turn | |
2801 | * __split_huge_page_refcount() can't run from under | |
2802 | * us and we can safely transfer the refcount from | |
2803 | * PG_tail to PG_head as we switch the pfn to tail to | |
2804 | * head. | |
2805 | */ | |
2806 | *levelp = level = PT_DIRECTORY_LEVEL; | |
2807 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
2808 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2809 | if (pfn & mask) { | |
2810 | gfn &= ~mask; | |
2811 | *gfnp = gfn; | |
2812 | kvm_release_pfn_clean(pfn); | |
2813 | pfn &= ~mask; | |
c3586667 | 2814 | kvm_get_pfn(pfn); |
936a5fe6 AA |
2815 | *pfnp = pfn; |
2816 | } | |
2817 | } | |
2818 | } | |
2819 | ||
d7c55201 | 2820 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
ba049e93 | 2821 | kvm_pfn_t pfn, unsigned access, int *ret_val) |
d7c55201 XG |
2822 | { |
2823 | bool ret = true; | |
2824 | ||
2825 | /* The pfn is invalid, report the error! */ | |
81c52c56 | 2826 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 XG |
2827 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
2828 | goto exit; | |
2829 | } | |
2830 | ||
ce88decf | 2831 | if (unlikely(is_noslot_pfn(pfn))) |
d7c55201 | 2832 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); |
d7c55201 XG |
2833 | |
2834 | ret = false; | |
2835 | exit: | |
2836 | return ret; | |
2837 | } | |
2838 | ||
e5552fd2 | 2839 | static bool page_fault_can_be_fast(u32 error_code) |
c7ba5b48 | 2840 | { |
1c118b82 XG |
2841 | /* |
2842 | * Do not fix the mmio spte with invalid generation number which | |
2843 | * need to be updated by slow page fault path. | |
2844 | */ | |
2845 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
2846 | return false; | |
2847 | ||
c7ba5b48 XG |
2848 | /* |
2849 | * #PF can be fast only if the shadow page table is present and it | |
2850 | * is caused by write-protect, that means we just need change the | |
2851 | * W bit of the spte which can be done out of mmu-lock. | |
2852 | */ | |
2853 | if (!(error_code & PFERR_PRESENT_MASK) || | |
2854 | !(error_code & PFERR_WRITE_MASK)) | |
2855 | return false; | |
2856 | ||
2857 | return true; | |
2858 | } | |
2859 | ||
2860 | static bool | |
92a476cb XG |
2861 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
2862 | u64 *sptep, u64 spte) | |
c7ba5b48 | 2863 | { |
c7ba5b48 XG |
2864 | gfn_t gfn; |
2865 | ||
2866 | WARN_ON(!sp->role.direct); | |
2867 | ||
2868 | /* | |
2869 | * The gfn of direct spte is stable since it is calculated | |
2870 | * by sp->gfn. | |
2871 | */ | |
2872 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
2873 | ||
9b51a630 KH |
2874 | /* |
2875 | * Theoretically we could also set dirty bit (and flush TLB) here in | |
2876 | * order to eliminate unnecessary PML logging. See comments in | |
2877 | * set_spte. But fast_page_fault is very unlikely to happen with PML | |
2878 | * enabled, so we do not do this. This might result in the same GPA | |
2879 | * to be logged in PML buffer again when the write really happens, and | |
2880 | * eventually to be called by mark_page_dirty twice. But it's also no | |
2881 | * harm. This also avoids the TLB flush needed after setting dirty bit | |
2882 | * so non-PML cases won't be impacted. | |
2883 | * | |
2884 | * Compare with set_spte where instead shadow_dirty_mask is set. | |
2885 | */ | |
c7ba5b48 | 2886 | if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte) |
54bf36aa | 2887 | kvm_vcpu_mark_page_dirty(vcpu, gfn); |
c7ba5b48 XG |
2888 | |
2889 | return true; | |
2890 | } | |
2891 | ||
2892 | /* | |
2893 | * Return value: | |
2894 | * - true: let the vcpu to access on the same address again. | |
2895 | * - false: let the real page fault path to fix it. | |
2896 | */ | |
2897 | static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, | |
2898 | u32 error_code) | |
2899 | { | |
2900 | struct kvm_shadow_walk_iterator iterator; | |
92a476cb | 2901 | struct kvm_mmu_page *sp; |
c7ba5b48 XG |
2902 | bool ret = false; |
2903 | u64 spte = 0ull; | |
2904 | ||
37f6a4e2 MT |
2905 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2906 | return false; | |
2907 | ||
e5552fd2 | 2908 | if (!page_fault_can_be_fast(error_code)) |
c7ba5b48 XG |
2909 | return false; |
2910 | ||
2911 | walk_shadow_page_lockless_begin(vcpu); | |
2912 | for_each_shadow_entry_lockless(vcpu, gva, iterator, spte) | |
2913 | if (!is_shadow_present_pte(spte) || iterator.level < level) | |
2914 | break; | |
2915 | ||
2916 | /* | |
2917 | * If the mapping has been changed, let the vcpu fault on the | |
2918 | * same address again. | |
2919 | */ | |
afd28fe1 | 2920 | if (!is_shadow_present_pte(spte)) { |
c7ba5b48 XG |
2921 | ret = true; |
2922 | goto exit; | |
2923 | } | |
2924 | ||
92a476cb XG |
2925 | sp = page_header(__pa(iterator.sptep)); |
2926 | if (!is_last_spte(spte, sp->role.level)) | |
c7ba5b48 XG |
2927 | goto exit; |
2928 | ||
2929 | /* | |
2930 | * Check if it is a spurious fault caused by TLB lazily flushed. | |
2931 | * | |
2932 | * Need not check the access of upper level table entries since | |
2933 | * they are always ACC_ALL. | |
2934 | */ | |
2935 | if (is_writable_pte(spte)) { | |
2936 | ret = true; | |
2937 | goto exit; | |
2938 | } | |
2939 | ||
2940 | /* | |
2941 | * Currently, to simplify the code, only the spte write-protected | |
2942 | * by dirty-log can be fast fixed. | |
2943 | */ | |
2944 | if (!spte_is_locklessly_modifiable(spte)) | |
2945 | goto exit; | |
2946 | ||
c126d94f XG |
2947 | /* |
2948 | * Do not fix write-permission on the large spte since we only dirty | |
2949 | * the first page into the dirty-bitmap in fast_pf_fix_direct_spte() | |
2950 | * that means other pages are missed if its slot is dirty-logged. | |
2951 | * | |
2952 | * Instead, we let the slow page fault path create a normal spte to | |
2953 | * fix the access. | |
2954 | * | |
2955 | * See the comments in kvm_arch_commit_memory_region(). | |
2956 | */ | |
2957 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2958 | goto exit; | |
2959 | ||
c7ba5b48 XG |
2960 | /* |
2961 | * Currently, fast page fault only works for direct mapping since | |
2962 | * the gfn is not stable for indirect shadow page. | |
2963 | * See Documentation/virtual/kvm/locking.txt to get more detail. | |
2964 | */ | |
92a476cb | 2965 | ret = fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte); |
c7ba5b48 | 2966 | exit: |
a72faf25 XG |
2967 | trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep, |
2968 | spte, ret); | |
c7ba5b48 XG |
2969 | walk_shadow_page_lockless_end(vcpu); |
2970 | ||
2971 | return ret; | |
2972 | } | |
2973 | ||
78b2c54a | 2974 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
ba049e93 | 2975 | gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable); |
450e0b41 | 2976 | static void make_mmu_pages_available(struct kvm_vcpu *vcpu); |
060c2abe | 2977 | |
c7ba5b48 XG |
2978 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code, |
2979 | gfn_t gfn, bool prefault) | |
10589a46 MT |
2980 | { |
2981 | int r; | |
852e3c19 | 2982 | int level; |
fd136902 | 2983 | bool force_pt_level = false; |
ba049e93 | 2984 | kvm_pfn_t pfn; |
e930bffe | 2985 | unsigned long mmu_seq; |
c7ba5b48 | 2986 | bool map_writable, write = error_code & PFERR_WRITE_MASK; |
aaee2c94 | 2987 | |
fd136902 | 2988 | level = mapping_level(vcpu, gfn, &force_pt_level); |
936a5fe6 | 2989 | if (likely(!force_pt_level)) { |
936a5fe6 AA |
2990 | /* |
2991 | * This path builds a PAE pagetable - so we can map | |
2992 | * 2mb pages at maximum. Therefore check if the level | |
2993 | * is larger than that. | |
2994 | */ | |
2995 | if (level > PT_DIRECTORY_LEVEL) | |
2996 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 2997 | |
936a5fe6 | 2998 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
fd136902 | 2999 | } |
05da4558 | 3000 | |
c7ba5b48 XG |
3001 | if (fast_page_fault(vcpu, v, level, error_code)) |
3002 | return 0; | |
3003 | ||
e930bffe | 3004 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3005 | smp_rmb(); |
060c2abe | 3006 | |
78b2c54a | 3007 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
060c2abe | 3008 | return 0; |
aaee2c94 | 3009 | |
d7c55201 XG |
3010 | if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r)) |
3011 | return r; | |
d196e343 | 3012 | |
aaee2c94 | 3013 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3014 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3015 | goto out_unlock; |
450e0b41 | 3016 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
3017 | if (likely(!force_pt_level)) |
3018 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
7ee0e5b2 | 3019 | r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault); |
aaee2c94 MT |
3020 | spin_unlock(&vcpu->kvm->mmu_lock); |
3021 | ||
10589a46 | 3022 | return r; |
e930bffe AA |
3023 | |
3024 | out_unlock: | |
3025 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3026 | kvm_release_pfn_clean(pfn); | |
3027 | return 0; | |
10589a46 MT |
3028 | } |
3029 | ||
3030 | ||
17ac10ad AK |
3031 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
3032 | { | |
3033 | int i; | |
4db35314 | 3034 | struct kvm_mmu_page *sp; |
d98ba053 | 3035 | LIST_HEAD(invalid_list); |
17ac10ad | 3036 | |
ad312c7c | 3037 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 3038 | return; |
35af577a | 3039 | |
81407ca5 JR |
3040 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL && |
3041 | (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL || | |
3042 | vcpu->arch.mmu.direct_map)) { | |
ad312c7c | 3043 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 3044 | |
35af577a | 3045 | spin_lock(&vcpu->kvm->mmu_lock); |
4db35314 AK |
3046 | sp = page_header(root); |
3047 | --sp->root_count; | |
d98ba053 XG |
3048 | if (!sp->root_count && sp->role.invalid) { |
3049 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
3050 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
3051 | } | |
aaee2c94 | 3052 | spin_unlock(&vcpu->kvm->mmu_lock); |
35af577a | 3053 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
3054 | return; |
3055 | } | |
35af577a GN |
3056 | |
3057 | spin_lock(&vcpu->kvm->mmu_lock); | |
17ac10ad | 3058 | for (i = 0; i < 4; ++i) { |
ad312c7c | 3059 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 3060 | |
417726a3 | 3061 | if (root) { |
417726a3 | 3062 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
3063 | sp = page_header(root); |
3064 | --sp->root_count; | |
2e53d63a | 3065 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
3066 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
3067 | &invalid_list); | |
417726a3 | 3068 | } |
ad312c7c | 3069 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 3070 | } |
d98ba053 | 3071 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 3072 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 3073 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
3074 | } |
3075 | ||
8986ecc0 MT |
3076 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
3077 | { | |
3078 | int ret = 0; | |
3079 | ||
3080 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 3081 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
3082 | ret = 1; |
3083 | } | |
3084 | ||
3085 | return ret; | |
3086 | } | |
3087 | ||
651dd37a JR |
3088 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
3089 | { | |
3090 | struct kvm_mmu_page *sp; | |
7ebaf15e | 3091 | unsigned i; |
651dd37a JR |
3092 | |
3093 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3094 | spin_lock(&vcpu->kvm->mmu_lock); | |
450e0b41 | 3095 | make_mmu_pages_available(vcpu); |
bb11c6c9 | 3096 | sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, 1, ACC_ALL); |
651dd37a JR |
3097 | ++sp->root_count; |
3098 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3099 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
3100 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
3101 | for (i = 0; i < 4; ++i) { | |
3102 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3103 | ||
fa4a2c08 | 3104 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3105 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3106 | make_mmu_pages_available(vcpu); |
649497d1 | 3107 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
bb11c6c9 | 3108 | i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL); |
651dd37a JR |
3109 | root = __pa(sp->spt); |
3110 | ++sp->root_count; | |
3111 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3112 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 3113 | } |
6292757f | 3114 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
3115 | } else |
3116 | BUG(); | |
3117 | ||
3118 | return 0; | |
3119 | } | |
3120 | ||
3121 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 3122 | { |
4db35314 | 3123 | struct kvm_mmu_page *sp; |
81407ca5 JR |
3124 | u64 pdptr, pm_mask; |
3125 | gfn_t root_gfn; | |
3126 | int i; | |
3bb65a22 | 3127 | |
5777ed34 | 3128 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 3129 | |
651dd37a JR |
3130 | if (mmu_check_root(vcpu, root_gfn)) |
3131 | return 1; | |
3132 | ||
3133 | /* | |
3134 | * Do we shadow a long mode page table? If so we need to | |
3135 | * write-protect the guests page table root. | |
3136 | */ | |
3137 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { | |
ad312c7c | 3138 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 3139 | |
fa4a2c08 | 3140 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3141 | |
8facbbff | 3142 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3143 | make_mmu_pages_available(vcpu); |
651dd37a | 3144 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, |
bb11c6c9 | 3145 | 0, ACC_ALL); |
4db35314 AK |
3146 | root = __pa(sp->spt); |
3147 | ++sp->root_count; | |
8facbbff | 3148 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 3149 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 3150 | return 0; |
17ac10ad | 3151 | } |
f87f9288 | 3152 | |
651dd37a JR |
3153 | /* |
3154 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3155 | * or a PAE 3-level page table. In either case we need to be aware that |
3156 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3157 | */ |
81407ca5 JR |
3158 | pm_mask = PT_PRESENT_MASK; |
3159 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) | |
3160 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; | |
3161 | ||
17ac10ad | 3162 | for (i = 0; i < 4; ++i) { |
ad312c7c | 3163 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 3164 | |
fa4a2c08 | 3165 | MMU_WARN_ON(VALID_PAGE(root)); |
ad312c7c | 3166 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 3167 | pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i); |
43a3795a | 3168 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 3169 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
3170 | continue; |
3171 | } | |
6de4f3ad | 3172 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
3173 | if (mmu_check_root(vcpu, root_gfn)) |
3174 | return 1; | |
5a7388c2 | 3175 | } |
8facbbff | 3176 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3177 | make_mmu_pages_available(vcpu); |
bb11c6c9 TY |
3178 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL, |
3179 | 0, ACC_ALL); | |
4db35314 AK |
3180 | root = __pa(sp->spt); |
3181 | ++sp->root_count; | |
8facbbff AK |
3182 | spin_unlock(&vcpu->kvm->mmu_lock); |
3183 | ||
81407ca5 | 3184 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 3185 | } |
6292757f | 3186 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3187 | |
3188 | /* | |
3189 | * If we shadow a 32 bit page table with a long mode page | |
3190 | * table we enter this path. | |
3191 | */ | |
3192 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3193 | if (vcpu->arch.mmu.lm_root == NULL) { | |
3194 | /* | |
3195 | * The additional page necessary for this is only | |
3196 | * allocated on demand. | |
3197 | */ | |
3198 | ||
3199 | u64 *lm_root; | |
3200 | ||
3201 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
3202 | if (lm_root == NULL) | |
3203 | return 1; | |
3204 | ||
3205 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
3206 | ||
3207 | vcpu->arch.mmu.lm_root = lm_root; | |
3208 | } | |
3209 | ||
3210 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
3211 | } | |
3212 | ||
8986ecc0 | 3213 | return 0; |
17ac10ad AK |
3214 | } |
3215 | ||
651dd37a JR |
3216 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
3217 | { | |
3218 | if (vcpu->arch.mmu.direct_map) | |
3219 | return mmu_alloc_direct_roots(vcpu); | |
3220 | else | |
3221 | return mmu_alloc_shadow_roots(vcpu); | |
3222 | } | |
3223 | ||
0ba73cda MT |
3224 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
3225 | { | |
3226 | int i; | |
3227 | struct kvm_mmu_page *sp; | |
3228 | ||
81407ca5 JR |
3229 | if (vcpu->arch.mmu.direct_map) |
3230 | return; | |
3231 | ||
0ba73cda MT |
3232 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3233 | return; | |
6903074c | 3234 | |
56f17dd3 | 3235 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); |
0375f7fa | 3236 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
81407ca5 | 3237 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { |
0ba73cda MT |
3238 | hpa_t root = vcpu->arch.mmu.root_hpa; |
3239 | sp = page_header(root); | |
3240 | mmu_sync_children(vcpu, sp); | |
0375f7fa | 3241 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3242 | return; |
3243 | } | |
3244 | for (i = 0; i < 4; ++i) { | |
3245 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3246 | ||
8986ecc0 | 3247 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
3248 | root &= PT64_BASE_ADDR_MASK; |
3249 | sp = page_header(root); | |
3250 | mmu_sync_children(vcpu, sp); | |
3251 | } | |
3252 | } | |
0375f7fa | 3253 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3254 | } |
3255 | ||
3256 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
3257 | { | |
3258 | spin_lock(&vcpu->kvm->mmu_lock); | |
3259 | mmu_sync_roots(vcpu); | |
6cffe8ca | 3260 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3261 | } |
bfd0a56b | 3262 | EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots); |
0ba73cda | 3263 | |
1871c602 | 3264 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 3265 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3266 | { |
ab9ae313 AK |
3267 | if (exception) |
3268 | exception->error_code = 0; | |
6aa8b732 AK |
3269 | return vaddr; |
3270 | } | |
3271 | ||
6539e738 | 3272 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
3273 | u32 access, |
3274 | struct x86_exception *exception) | |
6539e738 | 3275 | { |
ab9ae313 AK |
3276 | if (exception) |
3277 | exception->error_code = 0; | |
54987b7a | 3278 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception); |
6539e738 JR |
3279 | } |
3280 | ||
d625b155 XG |
3281 | static bool |
3282 | __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level) | |
3283 | { | |
3284 | int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f; | |
3285 | ||
3286 | return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) | | |
3287 | ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0); | |
3288 | } | |
3289 | ||
3290 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) | |
3291 | { | |
3292 | return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level); | |
3293 | } | |
3294 | ||
3295 | static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level) | |
3296 | { | |
3297 | return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level); | |
3298 | } | |
3299 | ||
ded58749 | 3300 | static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf XG |
3301 | { |
3302 | if (direct) | |
3303 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3304 | ||
3305 | return vcpu_match_mmio_gva(vcpu, addr); | |
3306 | } | |
3307 | ||
47ab8751 XG |
3308 | /* return true if reserved bit is detected on spte. */ |
3309 | static bool | |
3310 | walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep) | |
ce88decf XG |
3311 | { |
3312 | struct kvm_shadow_walk_iterator iterator; | |
47ab8751 XG |
3313 | u64 sptes[PT64_ROOT_LEVEL], spte = 0ull; |
3314 | int root, leaf; | |
3315 | bool reserved = false; | |
ce88decf | 3316 | |
37f6a4e2 | 3317 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
47ab8751 | 3318 | goto exit; |
37f6a4e2 | 3319 | |
ce88decf | 3320 | walk_shadow_page_lockless_begin(vcpu); |
47ab8751 | 3321 | |
29ecd660 PB |
3322 | for (shadow_walk_init(&iterator, vcpu, addr), |
3323 | leaf = root = iterator.level; | |
47ab8751 XG |
3324 | shadow_walk_okay(&iterator); |
3325 | __shadow_walk_next(&iterator, spte)) { | |
47ab8751 XG |
3326 | spte = mmu_spte_get_lockless(iterator.sptep); |
3327 | ||
3328 | sptes[leaf - 1] = spte; | |
29ecd660 | 3329 | leaf--; |
47ab8751 | 3330 | |
ce88decf XG |
3331 | if (!is_shadow_present_pte(spte)) |
3332 | break; | |
47ab8751 XG |
3333 | |
3334 | reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte, | |
58c95070 | 3335 | iterator.level); |
47ab8751 XG |
3336 | } |
3337 | ||
ce88decf XG |
3338 | walk_shadow_page_lockless_end(vcpu); |
3339 | ||
47ab8751 XG |
3340 | if (reserved) { |
3341 | pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n", | |
3342 | __func__, addr); | |
29ecd660 | 3343 | while (root > leaf) { |
47ab8751 XG |
3344 | pr_err("------ spte 0x%llx level %d.\n", |
3345 | sptes[root - 1], root); | |
3346 | root--; | |
3347 | } | |
3348 | } | |
3349 | exit: | |
3350 | *sptep = spte; | |
3351 | return reserved; | |
ce88decf XG |
3352 | } |
3353 | ||
450869d6 | 3354 | int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf XG |
3355 | { |
3356 | u64 spte; | |
47ab8751 | 3357 | bool reserved; |
ce88decf | 3358 | |
ded58749 | 3359 | if (mmio_info_in_cache(vcpu, addr, direct)) |
b37fbea6 | 3360 | return RET_MMIO_PF_EMULATE; |
ce88decf | 3361 | |
47ab8751 | 3362 | reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte); |
450869d6 | 3363 | if (WARN_ON(reserved)) |
47ab8751 | 3364 | return RET_MMIO_PF_BUG; |
ce88decf XG |
3365 | |
3366 | if (is_mmio_spte(spte)) { | |
3367 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
3368 | unsigned access = get_mmio_spte_access(spte); | |
3369 | ||
54bf36aa | 3370 | if (!check_mmio_spte(vcpu, spte)) |
f8f55942 XG |
3371 | return RET_MMIO_PF_INVALID; |
3372 | ||
ce88decf XG |
3373 | if (direct) |
3374 | addr = 0; | |
4f022648 XG |
3375 | |
3376 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf | 3377 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
b37fbea6 | 3378 | return RET_MMIO_PF_EMULATE; |
ce88decf XG |
3379 | } |
3380 | ||
ce88decf XG |
3381 | /* |
3382 | * If the page table is zapped by other cpus, let CPU fault again on | |
3383 | * the address. | |
3384 | */ | |
b37fbea6 | 3385 | return RET_MMIO_PF_RETRY; |
ce88decf | 3386 | } |
450869d6 | 3387 | EXPORT_SYMBOL_GPL(handle_mmio_page_fault); |
ce88decf | 3388 | |
3d0c27ad XG |
3389 | static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu, |
3390 | u32 error_code, gfn_t gfn) | |
3391 | { | |
3392 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3393 | return false; | |
3394 | ||
3395 | if (!(error_code & PFERR_PRESENT_MASK) || | |
3396 | !(error_code & PFERR_WRITE_MASK)) | |
3397 | return false; | |
3398 | ||
3399 | /* | |
3400 | * guest is writing the page which is write tracked which can | |
3401 | * not be fixed by page fault handler. | |
3402 | */ | |
3403 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) | |
3404 | return true; | |
3405 | ||
3406 | return false; | |
3407 | } | |
3408 | ||
e5691a81 XG |
3409 | static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr) |
3410 | { | |
3411 | struct kvm_shadow_walk_iterator iterator; | |
3412 | u64 spte; | |
3413 | ||
3414 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
3415 | return; | |
3416 | ||
3417 | walk_shadow_page_lockless_begin(vcpu); | |
3418 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
3419 | clear_sp_write_flooding_count(iterator.sptep); | |
3420 | if (!is_shadow_present_pte(spte)) | |
3421 | break; | |
3422 | } | |
3423 | walk_shadow_page_lockless_end(vcpu); | |
3424 | } | |
3425 | ||
6aa8b732 | 3426 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 3427 | u32 error_code, bool prefault) |
6aa8b732 | 3428 | { |
3d0c27ad | 3429 | gfn_t gfn = gva >> PAGE_SHIFT; |
e2dec939 | 3430 | int r; |
6aa8b732 | 3431 | |
b8688d51 | 3432 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
ce88decf | 3433 | |
3d0c27ad XG |
3434 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
3435 | return 1; | |
3436 | ||
e2dec939 AK |
3437 | r = mmu_topup_memory_caches(vcpu); |
3438 | if (r) | |
3439 | return r; | |
714b93da | 3440 | |
fa4a2c08 | 3441 | MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3442 | |
6aa8b732 | 3443 | |
e833240f | 3444 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
c7ba5b48 | 3445 | error_code, gfn, prefault); |
6aa8b732 AK |
3446 | } |
3447 | ||
7e1fbeac | 3448 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
3449 | { |
3450 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3451 | |
7c90705b | 3452 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3453 | arch.gfn = gfn; |
c4806acd | 3454 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 3455 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 | 3456 | |
54bf36aa | 3457 | return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch); |
af585b92 GN |
3458 | } |
3459 | ||
3460 | static bool can_do_async_pf(struct kvm_vcpu *vcpu) | |
3461 | { | |
35754c98 | 3462 | if (unlikely(!lapic_in_kernel(vcpu) || |
af585b92 GN |
3463 | kvm_event_needs_reinjection(vcpu))) |
3464 | return false; | |
3465 | ||
3466 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
3467 | } | |
3468 | ||
78b2c54a | 3469 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
ba049e93 | 3470 | gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable) |
af585b92 | 3471 | { |
3520469d | 3472 | struct kvm_memory_slot *slot; |
af585b92 GN |
3473 | bool async; |
3474 | ||
54bf36aa | 3475 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
3520469d PB |
3476 | async = false; |
3477 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable); | |
af585b92 GN |
3478 | if (!async) |
3479 | return false; /* *pfn has correct page already */ | |
3480 | ||
78b2c54a | 3481 | if (!prefault && can_do_async_pf(vcpu)) { |
c9b263d2 | 3482 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
3483 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
3484 | trace_kvm_async_pf_doublefault(gva, gfn); | |
3485 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
3486 | return true; | |
3487 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
3488 | return true; | |
3489 | } | |
3490 | ||
3520469d | 3491 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable); |
af585b92 GN |
3492 | return false; |
3493 | } | |
3494 | ||
6a39bbc5 XG |
3495 | static bool |
3496 | check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level) | |
3497 | { | |
3498 | int page_num = KVM_PAGES_PER_HPAGE(level); | |
3499 | ||
3500 | gfn &= ~(page_num - 1); | |
3501 | ||
3502 | return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num); | |
3503 | } | |
3504 | ||
56028d08 | 3505 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 3506 | bool prefault) |
fb72d167 | 3507 | { |
ba049e93 | 3508 | kvm_pfn_t pfn; |
fb72d167 | 3509 | int r; |
852e3c19 | 3510 | int level; |
cd1872f0 | 3511 | bool force_pt_level; |
05da4558 | 3512 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 3513 | unsigned long mmu_seq; |
612819c3 MT |
3514 | int write = error_code & PFERR_WRITE_MASK; |
3515 | bool map_writable; | |
fb72d167 | 3516 | |
fa4a2c08 | 3517 | MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
fb72d167 | 3518 | |
3d0c27ad XG |
3519 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
3520 | return 1; | |
3521 | ||
fb72d167 JR |
3522 | r = mmu_topup_memory_caches(vcpu); |
3523 | if (r) | |
3524 | return r; | |
3525 | ||
fd136902 TY |
3526 | force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn, |
3527 | PT_DIRECTORY_LEVEL); | |
3528 | level = mapping_level(vcpu, gfn, &force_pt_level); | |
936a5fe6 | 3529 | if (likely(!force_pt_level)) { |
6a39bbc5 XG |
3530 | if (level > PT_DIRECTORY_LEVEL && |
3531 | !check_hugepage_cache_consistency(vcpu, gfn, level)) | |
3532 | level = PT_DIRECTORY_LEVEL; | |
936a5fe6 | 3533 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
fd136902 | 3534 | } |
852e3c19 | 3535 | |
c7ba5b48 XG |
3536 | if (fast_page_fault(vcpu, gpa, level, error_code)) |
3537 | return 0; | |
3538 | ||
e930bffe | 3539 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3540 | smp_rmb(); |
af585b92 | 3541 | |
78b2c54a | 3542 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
af585b92 GN |
3543 | return 0; |
3544 | ||
d7c55201 XG |
3545 | if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r)) |
3546 | return r; | |
3547 | ||
fb72d167 | 3548 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3549 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3550 | goto out_unlock; |
450e0b41 | 3551 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
3552 | if (likely(!force_pt_level)) |
3553 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
7ee0e5b2 | 3554 | r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault); |
fb72d167 | 3555 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
3556 | |
3557 | return r; | |
e930bffe AA |
3558 | |
3559 | out_unlock: | |
3560 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3561 | kvm_release_pfn_clean(pfn); | |
3562 | return 0; | |
fb72d167 JR |
3563 | } |
3564 | ||
8a3c1a33 PB |
3565 | static void nonpaging_init_context(struct kvm_vcpu *vcpu, |
3566 | struct kvm_mmu *context) | |
6aa8b732 | 3567 | { |
6aa8b732 | 3568 | context->page_fault = nonpaging_page_fault; |
6aa8b732 | 3569 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
e8bc217a | 3570 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3571 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3572 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 3573 | context->root_level = 0; |
6aa8b732 | 3574 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3575 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3576 | context->direct_map = true; |
2d48a985 | 3577 | context->nx = false; |
6aa8b732 AK |
3578 | } |
3579 | ||
d8d173da | 3580 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu) |
6aa8b732 | 3581 | { |
cea0f0e7 | 3582 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3583 | } |
3584 | ||
5777ed34 JR |
3585 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
3586 | { | |
9f8fe504 | 3587 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
3588 | } |
3589 | ||
6389ee94 AK |
3590 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
3591 | struct x86_exception *fault) | |
6aa8b732 | 3592 | { |
6389ee94 | 3593 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
3594 | } |
3595 | ||
54bf36aa | 3596 | static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
f2fd125d | 3597 | unsigned access, int *nr_present) |
ce88decf XG |
3598 | { |
3599 | if (unlikely(is_mmio_spte(*sptep))) { | |
3600 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
3601 | mmu_spte_clear_no_track(sptep); | |
3602 | return true; | |
3603 | } | |
3604 | ||
3605 | (*nr_present)++; | |
54bf36aa | 3606 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
3607 | return true; |
3608 | } | |
3609 | ||
3610 | return false; | |
3611 | } | |
3612 | ||
6fd01b71 AK |
3613 | static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte) |
3614 | { | |
3615 | unsigned index; | |
3616 | ||
3617 | index = level - 1; | |
3618 | index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2); | |
3619 | return mmu->last_pte_bitmap & (1 << index); | |
3620 | } | |
3621 | ||
37406aaa NHE |
3622 | #define PTTYPE_EPT 18 /* arbitrary */ |
3623 | #define PTTYPE PTTYPE_EPT | |
3624 | #include "paging_tmpl.h" | |
3625 | #undef PTTYPE | |
3626 | ||
6aa8b732 AK |
3627 | #define PTTYPE 64 |
3628 | #include "paging_tmpl.h" | |
3629 | #undef PTTYPE | |
3630 | ||
3631 | #define PTTYPE 32 | |
3632 | #include "paging_tmpl.h" | |
3633 | #undef PTTYPE | |
3634 | ||
6dc98b86 XG |
3635 | static void |
3636 | __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, | |
3637 | struct rsvd_bits_validate *rsvd_check, | |
3638 | int maxphyaddr, int level, bool nx, bool gbpages, | |
6fec2144 | 3639 | bool pse, bool amd) |
82725b20 | 3640 | { |
82725b20 | 3641 | u64 exb_bit_rsvd = 0; |
5f7dde7b | 3642 | u64 gbpages_bit_rsvd = 0; |
a0c0feb5 | 3643 | u64 nonleaf_bit8_rsvd = 0; |
82725b20 | 3644 | |
a0a64f50 | 3645 | rsvd_check->bad_mt_xwr = 0; |
25d92081 | 3646 | |
6dc98b86 | 3647 | if (!nx) |
82725b20 | 3648 | exb_bit_rsvd = rsvd_bits(63, 63); |
6dc98b86 | 3649 | if (!gbpages) |
5f7dde7b | 3650 | gbpages_bit_rsvd = rsvd_bits(7, 7); |
a0c0feb5 PB |
3651 | |
3652 | /* | |
3653 | * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for | |
3654 | * leaf entries) on AMD CPUs only. | |
3655 | */ | |
6fec2144 | 3656 | if (amd) |
a0c0feb5 PB |
3657 | nonleaf_bit8_rsvd = rsvd_bits(8, 8); |
3658 | ||
6dc98b86 | 3659 | switch (level) { |
82725b20 DE |
3660 | case PT32_ROOT_LEVEL: |
3661 | /* no rsvd bits for 2 level 4K page table entries */ | |
a0a64f50 XG |
3662 | rsvd_check->rsvd_bits_mask[0][1] = 0; |
3663 | rsvd_check->rsvd_bits_mask[0][0] = 0; | |
3664 | rsvd_check->rsvd_bits_mask[1][0] = | |
3665 | rsvd_check->rsvd_bits_mask[0][0]; | |
f815bce8 | 3666 | |
6dc98b86 | 3667 | if (!pse) { |
a0a64f50 | 3668 | rsvd_check->rsvd_bits_mask[1][1] = 0; |
f815bce8 XG |
3669 | break; |
3670 | } | |
3671 | ||
82725b20 DE |
3672 | if (is_cpuid_PSE36()) |
3673 | /* 36bits PSE 4MB page */ | |
a0a64f50 | 3674 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); |
82725b20 DE |
3675 | else |
3676 | /* 32 bits PSE 4MB page */ | |
a0a64f50 | 3677 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); |
82725b20 DE |
3678 | break; |
3679 | case PT32E_ROOT_LEVEL: | |
a0a64f50 | 3680 | rsvd_check->rsvd_bits_mask[0][2] = |
20c466b5 | 3681 | rsvd_bits(maxphyaddr, 63) | |
cd9ae5fe | 3682 | rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */ |
a0a64f50 | 3683 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 3684 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
a0a64f50 | 3685 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
82725b20 | 3686 | rsvd_bits(maxphyaddr, 62); /* PTE */ |
a0a64f50 | 3687 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
82725b20 DE |
3688 | rsvd_bits(maxphyaddr, 62) | |
3689 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
3690 | rsvd_check->rsvd_bits_mask[1][0] = |
3691 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
3692 | break; |
3693 | case PT64_ROOT_LEVEL: | |
a0a64f50 XG |
3694 | rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd | |
3695 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | | |
4c26b4cd | 3696 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
3697 | rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd | |
3698 | nonleaf_bit8_rsvd | gbpages_bit_rsvd | | |
82725b20 | 3699 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
3700 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
3701 | rsvd_bits(maxphyaddr, 51); | |
3702 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | | |
3703 | rsvd_bits(maxphyaddr, 51); | |
3704 | rsvd_check->rsvd_bits_mask[1][3] = | |
3705 | rsvd_check->rsvd_bits_mask[0][3]; | |
3706 | rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd | | |
5f7dde7b | 3707 | gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) | |
e04da980 | 3708 | rsvd_bits(13, 29); |
a0a64f50 | 3709 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
3710 | rsvd_bits(maxphyaddr, 51) | |
3711 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
3712 | rsvd_check->rsvd_bits_mask[1][0] = |
3713 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
3714 | break; |
3715 | } | |
3716 | } | |
3717 | ||
6dc98b86 XG |
3718 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
3719 | struct kvm_mmu *context) | |
3720 | { | |
3721 | __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check, | |
3722 | cpuid_maxphyaddr(vcpu), context->root_level, | |
3723 | context->nx, guest_cpuid_has_gbpages(vcpu), | |
6fec2144 | 3724 | is_pse(vcpu), guest_cpuid_is_amd(vcpu)); |
6dc98b86 XG |
3725 | } |
3726 | ||
81b8eebb XG |
3727 | static void |
3728 | __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check, | |
3729 | int maxphyaddr, bool execonly) | |
25d92081 | 3730 | { |
951f9fd7 | 3731 | u64 bad_mt_xwr; |
25d92081 | 3732 | |
a0a64f50 | 3733 | rsvd_check->rsvd_bits_mask[0][3] = |
25d92081 | 3734 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); |
a0a64f50 | 3735 | rsvd_check->rsvd_bits_mask[0][2] = |
25d92081 | 3736 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 3737 | rsvd_check->rsvd_bits_mask[0][1] = |
25d92081 | 3738 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 3739 | rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51); |
25d92081 YZ |
3740 | |
3741 | /* large page */ | |
a0a64f50 XG |
3742 | rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3]; |
3743 | rsvd_check->rsvd_bits_mask[1][2] = | |
25d92081 | 3744 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29); |
a0a64f50 | 3745 | rsvd_check->rsvd_bits_mask[1][1] = |
25d92081 | 3746 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20); |
a0a64f50 | 3747 | rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0]; |
25d92081 | 3748 | |
951f9fd7 PB |
3749 | bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */ |
3750 | bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */ | |
3751 | bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */ | |
3752 | bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */ | |
3753 | bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */ | |
3754 | if (!execonly) { | |
3755 | /* bits 0..2 must not be 100 unless VMX capabilities allow it */ | |
3756 | bad_mt_xwr |= REPEAT_BYTE(1ull << 4); | |
25d92081 | 3757 | } |
951f9fd7 | 3758 | rsvd_check->bad_mt_xwr = bad_mt_xwr; |
25d92081 YZ |
3759 | } |
3760 | ||
81b8eebb XG |
3761 | static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, |
3762 | struct kvm_mmu *context, bool execonly) | |
3763 | { | |
3764 | __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check, | |
3765 | cpuid_maxphyaddr(vcpu), execonly); | |
3766 | } | |
3767 | ||
c258b62b XG |
3768 | /* |
3769 | * the page table on host is the shadow page table for the page | |
3770 | * table in guest or amd nested guest, its mmu features completely | |
3771 | * follow the features in guest. | |
3772 | */ | |
3773 | void | |
3774 | reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) | |
3775 | { | |
6fec2144 PB |
3776 | /* |
3777 | * Passing "true" to the last argument is okay; it adds a check | |
3778 | * on bit 8 of the SPTEs which KVM doesn't use anyway. | |
3779 | */ | |
c258b62b XG |
3780 | __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check, |
3781 | boot_cpu_data.x86_phys_bits, | |
3782 | context->shadow_root_level, context->nx, | |
6fec2144 PB |
3783 | guest_cpuid_has_gbpages(vcpu), is_pse(vcpu), |
3784 | true); | |
c258b62b XG |
3785 | } |
3786 | EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask); | |
3787 | ||
6fec2144 PB |
3788 | static inline bool boot_cpu_is_amd(void) |
3789 | { | |
3790 | WARN_ON_ONCE(!tdp_enabled); | |
3791 | return shadow_x_mask == 0; | |
3792 | } | |
3793 | ||
c258b62b XG |
3794 | /* |
3795 | * the direct page table on host, use as much mmu features as | |
3796 | * possible, however, kvm currently does not do execution-protection. | |
3797 | */ | |
3798 | static void | |
3799 | reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
3800 | struct kvm_mmu *context) | |
3801 | { | |
6fec2144 | 3802 | if (boot_cpu_is_amd()) |
c258b62b XG |
3803 | __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check, |
3804 | boot_cpu_data.x86_phys_bits, | |
3805 | context->shadow_root_level, false, | |
6fec2144 | 3806 | cpu_has_gbpages, true, true); |
c258b62b XG |
3807 | else |
3808 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
3809 | boot_cpu_data.x86_phys_bits, | |
3810 | false); | |
3811 | ||
3812 | } | |
3813 | ||
3814 | /* | |
3815 | * as the comments in reset_shadow_zero_bits_mask() except it | |
3816 | * is the shadow page table for intel nested guest. | |
3817 | */ | |
3818 | static void | |
3819 | reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
3820 | struct kvm_mmu *context, bool execonly) | |
3821 | { | |
3822 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
3823 | boot_cpu_data.x86_phys_bits, execonly); | |
3824 | } | |
3825 | ||
edc90b7d XG |
3826 | static void update_permission_bitmask(struct kvm_vcpu *vcpu, |
3827 | struct kvm_mmu *mmu, bool ept) | |
97d64b78 AK |
3828 | { |
3829 | unsigned bit, byte, pfec; | |
3830 | u8 map; | |
66386ade | 3831 | bool fault, x, w, u, wf, uf, ff, smapf, cr4_smap, cr4_smep, smap = 0; |
97d64b78 | 3832 | |
66386ade | 3833 | cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
97ec8c06 | 3834 | cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); |
97d64b78 AK |
3835 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { |
3836 | pfec = byte << 1; | |
3837 | map = 0; | |
3838 | wf = pfec & PFERR_WRITE_MASK; | |
3839 | uf = pfec & PFERR_USER_MASK; | |
3840 | ff = pfec & PFERR_FETCH_MASK; | |
97ec8c06 FW |
3841 | /* |
3842 | * PFERR_RSVD_MASK bit is set in PFEC if the access is not | |
3843 | * subject to SMAP restrictions, and cleared otherwise. The | |
3844 | * bit is only meaningful if the SMAP bit is set in CR4. | |
3845 | */ | |
3846 | smapf = !(pfec & PFERR_RSVD_MASK); | |
97d64b78 AK |
3847 | for (bit = 0; bit < 8; ++bit) { |
3848 | x = bit & ACC_EXEC_MASK; | |
3849 | w = bit & ACC_WRITE_MASK; | |
3850 | u = bit & ACC_USER_MASK; | |
3851 | ||
25d92081 YZ |
3852 | if (!ept) { |
3853 | /* Not really needed: !nx will cause pte.nx to fault */ | |
3854 | x |= !mmu->nx; | |
3855 | /* Allow supervisor writes if !cr0.wp */ | |
3856 | w |= !is_write_protection(vcpu) && !uf; | |
3857 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
66386ade | 3858 | x &= !(cr4_smep && u && !uf); |
97ec8c06 FW |
3859 | |
3860 | /* | |
3861 | * SMAP:kernel-mode data accesses from user-mode | |
3862 | * mappings should fault. A fault is considered | |
3863 | * as a SMAP violation if all of the following | |
3864 | * conditions are ture: | |
3865 | * - X86_CR4_SMAP is set in CR4 | |
3866 | * - An user page is accessed | |
3867 | * - Page fault in kernel mode | |
3868 | * - if CPL = 3 or X86_EFLAGS_AC is clear | |
3869 | * | |
3870 | * Here, we cover the first three conditions. | |
3871 | * The fourth is computed dynamically in | |
3872 | * permission_fault() and is in smapf. | |
3873 | * | |
3874 | * Also, SMAP does not affect instruction | |
3875 | * fetches, add the !ff check here to make it | |
3876 | * clearer. | |
3877 | */ | |
3878 | smap = cr4_smap && u && !uf && !ff; | |
25d92081 YZ |
3879 | } else |
3880 | /* Not really needed: no U/S accesses on ept */ | |
3881 | u = 1; | |
97d64b78 | 3882 | |
97ec8c06 FW |
3883 | fault = (ff && !x) || (uf && !u) || (wf && !w) || |
3884 | (smapf && smap); | |
97d64b78 AK |
3885 | map |= fault << bit; |
3886 | } | |
3887 | mmu->permissions[byte] = map; | |
3888 | } | |
3889 | } | |
3890 | ||
6fd01b71 AK |
3891 | static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
3892 | { | |
3893 | u8 map; | |
3894 | unsigned level, root_level = mmu->root_level; | |
3895 | const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */ | |
3896 | ||
3897 | if (root_level == PT32E_ROOT_LEVEL) | |
3898 | --root_level; | |
3899 | /* PT_PAGE_TABLE_LEVEL always terminates */ | |
3900 | map = 1 | (1 << ps_set_index); | |
3901 | for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) { | |
3902 | if (level <= PT_PDPE_LEVEL | |
3903 | && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu))) | |
3904 | map |= 1 << (ps_set_index | (level - 1)); | |
3905 | } | |
3906 | mmu->last_pte_bitmap = map; | |
3907 | } | |
3908 | ||
8a3c1a33 PB |
3909 | static void paging64_init_context_common(struct kvm_vcpu *vcpu, |
3910 | struct kvm_mmu *context, | |
3911 | int level) | |
6aa8b732 | 3912 | { |
2d48a985 | 3913 | context->nx = is_nx(vcpu); |
4d6931c3 | 3914 | context->root_level = level; |
2d48a985 | 3915 | |
4d6931c3 | 3916 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 3917 | update_permission_bitmask(vcpu, context, false); |
6fd01b71 | 3918 | update_last_pte_bitmap(vcpu, context); |
6aa8b732 | 3919 | |
fa4a2c08 | 3920 | MMU_WARN_ON(!is_pae(vcpu)); |
6aa8b732 | 3921 | context->page_fault = paging64_page_fault; |
6aa8b732 | 3922 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 3923 | context->sync_page = paging64_sync_page; |
a7052897 | 3924 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 3925 | context->update_pte = paging64_update_pte; |
17ac10ad | 3926 | context->shadow_root_level = level; |
17c3ba9d | 3927 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3928 | context->direct_map = false; |
6aa8b732 AK |
3929 | } |
3930 | ||
8a3c1a33 PB |
3931 | static void paging64_init_context(struct kvm_vcpu *vcpu, |
3932 | struct kvm_mmu *context) | |
17ac10ad | 3933 | { |
8a3c1a33 | 3934 | paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
3935 | } |
3936 | ||
8a3c1a33 PB |
3937 | static void paging32_init_context(struct kvm_vcpu *vcpu, |
3938 | struct kvm_mmu *context) | |
6aa8b732 | 3939 | { |
2d48a985 | 3940 | context->nx = false; |
4d6931c3 | 3941 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 3942 | |
4d6931c3 | 3943 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 3944 | update_permission_bitmask(vcpu, context, false); |
6fd01b71 | 3945 | update_last_pte_bitmap(vcpu, context); |
6aa8b732 | 3946 | |
6aa8b732 | 3947 | context->page_fault = paging32_page_fault; |
6aa8b732 | 3948 | context->gva_to_gpa = paging32_gva_to_gpa; |
e8bc217a | 3949 | context->sync_page = paging32_sync_page; |
a7052897 | 3950 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 3951 | context->update_pte = paging32_update_pte; |
6aa8b732 | 3952 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3953 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3954 | context->direct_map = false; |
6aa8b732 AK |
3955 | } |
3956 | ||
8a3c1a33 PB |
3957 | static void paging32E_init_context(struct kvm_vcpu *vcpu, |
3958 | struct kvm_mmu *context) | |
6aa8b732 | 3959 | { |
8a3c1a33 | 3960 | paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
3961 | } |
3962 | ||
8a3c1a33 | 3963 | static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 3964 | { |
ad896af0 | 3965 | struct kvm_mmu *context = &vcpu->arch.mmu; |
fb72d167 | 3966 | |
c445f8ef | 3967 | context->base_role.word = 0; |
699023e2 | 3968 | context->base_role.smm = is_smm(vcpu); |
fb72d167 | 3969 | context->page_fault = tdp_page_fault; |
e8bc217a | 3970 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3971 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3972 | context->update_pte = nonpaging_update_pte; |
67253af5 | 3973 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 3974 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3975 | context->direct_map = true; |
1c97f0a0 | 3976 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 3977 | context->get_cr3 = get_cr3; |
e4e517b4 | 3978 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 3979 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
3980 | |
3981 | if (!is_paging(vcpu)) { | |
2d48a985 | 3982 | context->nx = false; |
fb72d167 JR |
3983 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
3984 | context->root_level = 0; | |
3985 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3986 | context->nx = is_nx(vcpu); |
fb72d167 | 3987 | context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 DB |
3988 | reset_rsvds_bits_mask(vcpu, context); |
3989 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 3990 | } else if (is_pae(vcpu)) { |
2d48a985 | 3991 | context->nx = is_nx(vcpu); |
fb72d167 | 3992 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
3993 | reset_rsvds_bits_mask(vcpu, context); |
3994 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 3995 | } else { |
2d48a985 | 3996 | context->nx = false; |
fb72d167 | 3997 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
3998 | reset_rsvds_bits_mask(vcpu, context); |
3999 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
4000 | } |
4001 | ||
25d92081 | 4002 | update_permission_bitmask(vcpu, context, false); |
6fd01b71 | 4003 | update_last_pte_bitmap(vcpu, context); |
c258b62b | 4004 | reset_tdp_shadow_zero_bits_mask(vcpu, context); |
fb72d167 JR |
4005 | } |
4006 | ||
ad896af0 | 4007 | void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu) |
6aa8b732 | 4008 | { |
411c588d | 4009 | bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
edc90b7d | 4010 | bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); |
ad896af0 PB |
4011 | struct kvm_mmu *context = &vcpu->arch.mmu; |
4012 | ||
fa4a2c08 | 4013 | MMU_WARN_ON(VALID_PAGE(context->root_hpa)); |
6aa8b732 AK |
4014 | |
4015 | if (!is_paging(vcpu)) | |
8a3c1a33 | 4016 | nonpaging_init_context(vcpu, context); |
a9058ecd | 4017 | else if (is_long_mode(vcpu)) |
8a3c1a33 | 4018 | paging64_init_context(vcpu, context); |
6aa8b732 | 4019 | else if (is_pae(vcpu)) |
8a3c1a33 | 4020 | paging32E_init_context(vcpu, context); |
6aa8b732 | 4021 | else |
8a3c1a33 | 4022 | paging32_init_context(vcpu, context); |
a770f6f2 | 4023 | |
ad896af0 PB |
4024 | context->base_role.nxe = is_nx(vcpu); |
4025 | context->base_role.cr4_pae = !!is_pae(vcpu); | |
4026 | context->base_role.cr0_wp = is_write_protection(vcpu); | |
4027 | context->base_role.smep_andnot_wp | |
411c588d | 4028 | = smep && !is_write_protection(vcpu); |
edc90b7d XG |
4029 | context->base_role.smap_andnot_wp |
4030 | = smap && !is_write_protection(vcpu); | |
699023e2 | 4031 | context->base_role.smm = is_smm(vcpu); |
c258b62b | 4032 | reset_shadow_zero_bits_mask(vcpu, context); |
52fde8df JR |
4033 | } |
4034 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
4035 | ||
ad896af0 | 4036 | void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly) |
155a97a3 | 4037 | { |
ad896af0 PB |
4038 | struct kvm_mmu *context = &vcpu->arch.mmu; |
4039 | ||
fa4a2c08 | 4040 | MMU_WARN_ON(VALID_PAGE(context->root_hpa)); |
155a97a3 NHE |
4041 | |
4042 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); | |
4043 | ||
4044 | context->nx = true; | |
155a97a3 NHE |
4045 | context->page_fault = ept_page_fault; |
4046 | context->gva_to_gpa = ept_gva_to_gpa; | |
4047 | context->sync_page = ept_sync_page; | |
4048 | context->invlpg = ept_invlpg; | |
4049 | context->update_pte = ept_update_pte; | |
155a97a3 NHE |
4050 | context->root_level = context->shadow_root_level; |
4051 | context->root_hpa = INVALID_PAGE; | |
4052 | context->direct_map = false; | |
4053 | ||
4054 | update_permission_bitmask(vcpu, context, true); | |
4055 | reset_rsvds_bits_mask_ept(vcpu, context, execonly); | |
c258b62b | 4056 | reset_ept_shadow_zero_bits_mask(vcpu, context, execonly); |
155a97a3 NHE |
4057 | } |
4058 | EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu); | |
4059 | ||
8a3c1a33 | 4060 | static void init_kvm_softmmu(struct kvm_vcpu *vcpu) |
52fde8df | 4061 | { |
ad896af0 PB |
4062 | struct kvm_mmu *context = &vcpu->arch.mmu; |
4063 | ||
4064 | kvm_init_shadow_mmu(vcpu); | |
4065 | context->set_cr3 = kvm_x86_ops->set_cr3; | |
4066 | context->get_cr3 = get_cr3; | |
4067 | context->get_pdptr = kvm_pdptr_read; | |
4068 | context->inject_page_fault = kvm_inject_page_fault; | |
6aa8b732 AK |
4069 | } |
4070 | ||
8a3c1a33 | 4071 | static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
02f59dc9 JR |
4072 | { |
4073 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
4074 | ||
4075 | g_context->get_cr3 = get_cr3; | |
e4e517b4 | 4076 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
4077 | g_context->inject_page_fault = kvm_inject_page_fault; |
4078 | ||
4079 | /* | |
0af2593b DM |
4080 | * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using |
4081 | * L1's nested page tables (e.g. EPT12). The nested translation | |
4082 | * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using | |
4083 | * L2's page tables as the first level of translation and L1's | |
4084 | * nested page tables as the second level of translation. Basically | |
4085 | * the gva_to_gpa functions between mmu and nested_mmu are swapped. | |
02f59dc9 JR |
4086 | */ |
4087 | if (!is_paging(vcpu)) { | |
2d48a985 | 4088 | g_context->nx = false; |
02f59dc9 JR |
4089 | g_context->root_level = 0; |
4090 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
4091 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4092 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 4093 | g_context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 | 4094 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4095 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4096 | } else if (is_pae(vcpu)) { | |
2d48a985 | 4097 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 4098 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 4099 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4100 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4101 | } else { | |
2d48a985 | 4102 | g_context->nx = false; |
02f59dc9 | 4103 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 4104 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4105 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
4106 | } | |
4107 | ||
25d92081 | 4108 | update_permission_bitmask(vcpu, g_context, false); |
6fd01b71 | 4109 | update_last_pte_bitmap(vcpu, g_context); |
02f59dc9 JR |
4110 | } |
4111 | ||
8a3c1a33 | 4112 | static void init_kvm_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4113 | { |
02f59dc9 | 4114 | if (mmu_is_nested(vcpu)) |
e0c6db3e | 4115 | init_kvm_nested_mmu(vcpu); |
02f59dc9 | 4116 | else if (tdp_enabled) |
e0c6db3e | 4117 | init_kvm_tdp_mmu(vcpu); |
fb72d167 | 4118 | else |
e0c6db3e | 4119 | init_kvm_softmmu(vcpu); |
fb72d167 JR |
4120 | } |
4121 | ||
8a3c1a33 | 4122 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu) |
6aa8b732 | 4123 | { |
95f93af4 | 4124 | kvm_mmu_unload(vcpu); |
8a3c1a33 | 4125 | init_kvm_mmu(vcpu); |
17c3ba9d | 4126 | } |
8668a3c4 | 4127 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
4128 | |
4129 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 4130 | { |
714b93da AK |
4131 | int r; |
4132 | ||
e2dec939 | 4133 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
4134 | if (r) |
4135 | goto out; | |
8986ecc0 | 4136 | r = mmu_alloc_roots(vcpu); |
e2858b4a | 4137 | kvm_mmu_sync_roots(vcpu); |
8986ecc0 MT |
4138 | if (r) |
4139 | goto out; | |
3662cb1c | 4140 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 4141 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
4142 | out: |
4143 | return r; | |
6aa8b732 | 4144 | } |
17c3ba9d AK |
4145 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
4146 | ||
4147 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
4148 | { | |
4149 | mmu_free_roots(vcpu); | |
95f93af4 | 4150 | WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
17c3ba9d | 4151 | } |
4b16184c | 4152 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 4153 | |
0028425f | 4154 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
4155 | struct kvm_mmu_page *sp, u64 *spte, |
4156 | const void *new) | |
0028425f | 4157 | { |
30945387 | 4158 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
4159 | ++vcpu->kvm->stat.mmu_pde_zapped; |
4160 | return; | |
30945387 | 4161 | } |
0028425f | 4162 | |
4cee5764 | 4163 | ++vcpu->kvm->stat.mmu_pte_updated; |
7c562522 | 4164 | vcpu->arch.mmu.update_pte(vcpu, sp, spte, new); |
0028425f AK |
4165 | } |
4166 | ||
79539cec AK |
4167 | static bool need_remote_flush(u64 old, u64 new) |
4168 | { | |
4169 | if (!is_shadow_present_pte(old)) | |
4170 | return false; | |
4171 | if (!is_shadow_present_pte(new)) | |
4172 | return true; | |
4173 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
4174 | return true; | |
53166229 GN |
4175 | old ^= shadow_nx_mask; |
4176 | new ^= shadow_nx_mask; | |
79539cec AK |
4177 | return (old & ~new & PT64_PERM_MASK) != 0; |
4178 | } | |
4179 | ||
0671a8e7 XG |
4180 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
4181 | bool remote_flush, bool local_flush) | |
79539cec | 4182 | { |
0671a8e7 XG |
4183 | if (zap_page) |
4184 | return; | |
4185 | ||
4186 | if (remote_flush) | |
79539cec | 4187 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 4188 | else if (local_flush) |
77c3913b | 4189 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
79539cec AK |
4190 | } |
4191 | ||
889e5cbc XG |
4192 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
4193 | const u8 *new, int *bytes) | |
da4a00f0 | 4194 | { |
889e5cbc XG |
4195 | u64 gentry; |
4196 | int r; | |
72016f3a | 4197 | |
72016f3a AK |
4198 | /* |
4199 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
4200 | * as the current vcpu paging mode since we update the sptes only |
4201 | * when they have the same mode. | |
72016f3a | 4202 | */ |
889e5cbc | 4203 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 4204 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
4205 | *gpa &= ~(gpa_t)7; |
4206 | *bytes = 8; | |
54bf36aa | 4207 | r = kvm_vcpu_read_guest(vcpu, *gpa, &gentry, 8); |
72016f3a AK |
4208 | if (r) |
4209 | gentry = 0; | |
08e850c6 AK |
4210 | new = (const u8 *)&gentry; |
4211 | } | |
4212 | ||
889e5cbc | 4213 | switch (*bytes) { |
08e850c6 AK |
4214 | case 4: |
4215 | gentry = *(const u32 *)new; | |
4216 | break; | |
4217 | case 8: | |
4218 | gentry = *(const u64 *)new; | |
4219 | break; | |
4220 | default: | |
4221 | gentry = 0; | |
4222 | break; | |
72016f3a AK |
4223 | } |
4224 | ||
889e5cbc XG |
4225 | return gentry; |
4226 | } | |
4227 | ||
4228 | /* | |
4229 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
4230 | * or we may be forking, in which case it is better to unmap the page. | |
4231 | */ | |
a138fe75 | 4232 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 4233 | { |
a30f47cb XG |
4234 | /* |
4235 | * Skip write-flooding detected for the sp whose level is 1, because | |
4236 | * it can become unsync, then the guest page is not write-protected. | |
4237 | */ | |
f71fa31f | 4238 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) |
a30f47cb | 4239 | return false; |
3246af0e | 4240 | |
e5691a81 XG |
4241 | atomic_inc(&sp->write_flooding_count); |
4242 | return atomic_read(&sp->write_flooding_count) >= 3; | |
889e5cbc XG |
4243 | } |
4244 | ||
4245 | /* | |
4246 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
4247 | * indicate a page is not used as a page table. | |
4248 | */ | |
4249 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
4250 | int bytes) | |
4251 | { | |
4252 | unsigned offset, pte_size, misaligned; | |
4253 | ||
4254 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4255 | gpa, bytes, sp->role.word); | |
4256 | ||
4257 | offset = offset_in_page(gpa); | |
4258 | pte_size = sp->role.cr4_pae ? 8 : 4; | |
5d9ca30e XG |
4259 | |
4260 | /* | |
4261 | * Sometimes, the OS only writes the last one bytes to update status | |
4262 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
4263 | */ | |
4264 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
4265 | return false; | |
4266 | ||
889e5cbc XG |
4267 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
4268 | misaligned |= bytes < 4; | |
4269 | ||
4270 | return misaligned; | |
4271 | } | |
4272 | ||
4273 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
4274 | { | |
4275 | unsigned page_offset, quadrant; | |
4276 | u64 *spte; | |
4277 | int level; | |
4278 | ||
4279 | page_offset = offset_in_page(gpa); | |
4280 | level = sp->role.level; | |
4281 | *nspte = 1; | |
4282 | if (!sp->role.cr4_pae) { | |
4283 | page_offset <<= 1; /* 32->64 */ | |
4284 | /* | |
4285 | * A 32-bit pde maps 4MB while the shadow pdes map | |
4286 | * only 2MB. So we need to double the offset again | |
4287 | * and zap two pdes instead of one. | |
4288 | */ | |
4289 | if (level == PT32_ROOT_LEVEL) { | |
4290 | page_offset &= ~7; /* kill rounding error */ | |
4291 | page_offset <<= 1; | |
4292 | *nspte = 2; | |
4293 | } | |
4294 | quadrant = page_offset >> PAGE_SHIFT; | |
4295 | page_offset &= ~PAGE_MASK; | |
4296 | if (quadrant != sp->role.quadrant) | |
4297 | return NULL; | |
4298 | } | |
4299 | ||
4300 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
4301 | return spte; | |
4302 | } | |
4303 | ||
4304 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4305 | const u8 *new, int bytes) | |
4306 | { | |
4307 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
889e5cbc | 4308 | struct kvm_mmu_page *sp; |
889e5cbc XG |
4309 | LIST_HEAD(invalid_list); |
4310 | u64 entry, gentry, *spte; | |
4311 | int npte; | |
a30f47cb | 4312 | bool remote_flush, local_flush, zap_page; |
4141259b AM |
4313 | union kvm_mmu_page_role mask = { }; |
4314 | ||
4315 | mask.cr0_wp = 1; | |
4316 | mask.cr4_pae = 1; | |
4317 | mask.nxe = 1; | |
4318 | mask.smep_andnot_wp = 1; | |
4319 | mask.smap_andnot_wp = 1; | |
699023e2 | 4320 | mask.smm = 1; |
889e5cbc XG |
4321 | |
4322 | /* | |
4323 | * If we don't have indirect shadow pages, it means no page is | |
4324 | * write-protected, so we can exit simply. | |
4325 | */ | |
4326 | if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) | |
4327 | return; | |
4328 | ||
4329 | zap_page = remote_flush = local_flush = false; | |
4330 | ||
4331 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
4332 | ||
4333 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes); | |
4334 | ||
4335 | /* | |
4336 | * No need to care whether allocation memory is successful | |
4337 | * or not since pte prefetch is skiped if it does not have | |
4338 | * enough objects in the cache. | |
4339 | */ | |
4340 | mmu_topup_memory_caches(vcpu); | |
4341 | ||
4342 | spin_lock(&vcpu->kvm->mmu_lock); | |
4343 | ++vcpu->kvm->stat.mmu_pte_write; | |
0375f7fa | 4344 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 4345 | |
b67bfe0d | 4346 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 4347 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 4348 | detect_write_flooding(sp)) { |
0671a8e7 | 4349 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 4350 | &invalid_list); |
4cee5764 | 4351 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
4352 | continue; |
4353 | } | |
889e5cbc XG |
4354 | |
4355 | spte = get_written_sptes(sp, gpa, &npte); | |
4356 | if (!spte) | |
4357 | continue; | |
4358 | ||
0671a8e7 | 4359 | local_flush = true; |
ac1b714e | 4360 | while (npte--) { |
79539cec | 4361 | entry = *spte; |
38e3b2b2 | 4362 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf XG |
4363 | if (gentry && |
4364 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
f759e2b4 | 4365 | & mask.word) && rmap_can_add(vcpu)) |
7c562522 | 4366 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
9bb4f6b1 | 4367 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 4368 | remote_flush = true; |
ac1b714e | 4369 | ++spte; |
9b7a0325 | 4370 | } |
9b7a0325 | 4371 | } |
0671a8e7 | 4372 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 4373 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
0375f7fa | 4374 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 4375 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
4376 | } |
4377 | ||
a436036b AK |
4378 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
4379 | { | |
10589a46 MT |
4380 | gpa_t gpa; |
4381 | int r; | |
a436036b | 4382 | |
c5a78f2b | 4383 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
4384 | return 0; |
4385 | ||
1871c602 | 4386 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 4387 | |
10589a46 | 4388 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 4389 | |
10589a46 | 4390 | return r; |
a436036b | 4391 | } |
577bdc49 | 4392 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 4393 | |
81f4f76b | 4394 | static void make_mmu_pages_available(struct kvm_vcpu *vcpu) |
ebeace86 | 4395 | { |
d98ba053 | 4396 | LIST_HEAD(invalid_list); |
103ad25a | 4397 | |
81f4f76b TY |
4398 | if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES)) |
4399 | return; | |
4400 | ||
5da59607 TY |
4401 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) { |
4402 | if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list)) | |
4403 | break; | |
ebeace86 | 4404 | |
4cee5764 | 4405 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 4406 | } |
aa6bd187 | 4407 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
ebeace86 | 4408 | } |
ebeace86 | 4409 | |
dc25e89e AP |
4410 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code, |
4411 | void *insn, int insn_len) | |
3067714c | 4412 | { |
1cb3f3ae | 4413 | int r, emulation_type = EMULTYPE_RETRY; |
3067714c | 4414 | enum emulation_result er; |
ded58749 | 4415 | bool direct = vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu); |
3067714c | 4416 | |
e9ee956e TY |
4417 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
4418 | r = handle_mmio_page_fault(vcpu, cr2, direct); | |
4419 | if (r == RET_MMIO_PF_EMULATE) { | |
4420 | emulation_type = 0; | |
4421 | goto emulate; | |
4422 | } | |
4423 | if (r == RET_MMIO_PF_RETRY) | |
4424 | return 1; | |
4425 | if (r < 0) | |
4426 | return r; | |
4427 | } | |
4428 | ||
56028d08 | 4429 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false); |
3067714c | 4430 | if (r < 0) |
e9ee956e TY |
4431 | return r; |
4432 | if (!r) | |
4433 | return 1; | |
3067714c | 4434 | |
ded58749 | 4435 | if (mmio_info_in_cache(vcpu, cr2, direct)) |
1cb3f3ae | 4436 | emulation_type = 0; |
e9ee956e | 4437 | emulate: |
1cb3f3ae | 4438 | er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len); |
3067714c AK |
4439 | |
4440 | switch (er) { | |
4441 | case EMULATE_DONE: | |
4442 | return 1; | |
ac0a48c3 | 4443 | case EMULATE_USER_EXIT: |
3067714c | 4444 | ++vcpu->stat.mmio_exits; |
6d77dbfc | 4445 | /* fall through */ |
3067714c | 4446 | case EMULATE_FAIL: |
3f5d18a9 | 4447 | return 0; |
3067714c AK |
4448 | default: |
4449 | BUG(); | |
4450 | } | |
3067714c AK |
4451 | } |
4452 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
4453 | ||
a7052897 MT |
4454 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
4455 | { | |
a7052897 | 4456 | vcpu->arch.mmu.invlpg(vcpu, gva); |
77c3913b | 4457 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
a7052897 MT |
4458 | ++vcpu->stat.invlpg; |
4459 | } | |
4460 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
4461 | ||
18552672 JR |
4462 | void kvm_enable_tdp(void) |
4463 | { | |
4464 | tdp_enabled = true; | |
4465 | } | |
4466 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
4467 | ||
5f4cb662 JR |
4468 | void kvm_disable_tdp(void) |
4469 | { | |
4470 | tdp_enabled = false; | |
4471 | } | |
4472 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
4473 | ||
6aa8b732 AK |
4474 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
4475 | { | |
ad312c7c | 4476 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
81407ca5 JR |
4477 | if (vcpu->arch.mmu.lm_root != NULL) |
4478 | free_page((unsigned long)vcpu->arch.mmu.lm_root); | |
6aa8b732 AK |
4479 | } |
4480 | ||
4481 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
4482 | { | |
17ac10ad | 4483 | struct page *page; |
6aa8b732 AK |
4484 | int i; |
4485 | ||
17ac10ad AK |
4486 | /* |
4487 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
4488 | * Therefore we need to allocate shadow page tables in the first | |
4489 | * 4GB of memory, which happens to fit the DMA32 zone. | |
4490 | */ | |
4491 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
4492 | if (!page) | |
d7fa6ab2 WY |
4493 | return -ENOMEM; |
4494 | ||
ad312c7c | 4495 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 4496 | for (i = 0; i < 4; ++i) |
ad312c7c | 4497 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 4498 | |
6aa8b732 | 4499 | return 0; |
6aa8b732 AK |
4500 | } |
4501 | ||
8018c27b | 4502 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 4503 | { |
e459e322 XG |
4504 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; |
4505 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; | |
4506 | vcpu->arch.mmu.translate_gpa = translate_gpa; | |
4507 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; | |
6aa8b732 | 4508 | |
8018c27b IM |
4509 | return alloc_mmu_pages(vcpu); |
4510 | } | |
6aa8b732 | 4511 | |
8a3c1a33 | 4512 | void kvm_mmu_setup(struct kvm_vcpu *vcpu) |
8018c27b | 4513 | { |
fa4a2c08 | 4514 | MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 4515 | |
8a3c1a33 | 4516 | init_kvm_mmu(vcpu); |
6aa8b732 AK |
4517 | } |
4518 | ||
1bad2b2a | 4519 | /* The return value indicates if tlb flush on all vcpus is needed. */ |
018aabb5 | 4520 | typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head); |
1bad2b2a XG |
4521 | |
4522 | /* The caller should hold mmu-lock before calling this function. */ | |
4523 | static bool | |
4524 | slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
4525 | slot_level_handler fn, int start_level, int end_level, | |
4526 | gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb) | |
4527 | { | |
4528 | struct slot_rmap_walk_iterator iterator; | |
4529 | bool flush = false; | |
4530 | ||
4531 | for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn, | |
4532 | end_gfn, &iterator) { | |
4533 | if (iterator.rmap) | |
4534 | flush |= fn(kvm, iterator.rmap); | |
4535 | ||
4536 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { | |
4537 | if (flush && lock_flush_tlb) { | |
4538 | kvm_flush_remote_tlbs(kvm); | |
4539 | flush = false; | |
4540 | } | |
4541 | cond_resched_lock(&kvm->mmu_lock); | |
4542 | } | |
4543 | } | |
4544 | ||
4545 | if (flush && lock_flush_tlb) { | |
4546 | kvm_flush_remote_tlbs(kvm); | |
4547 | flush = false; | |
4548 | } | |
4549 | ||
4550 | return flush; | |
4551 | } | |
4552 | ||
4553 | static bool | |
4554 | slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
4555 | slot_level_handler fn, int start_level, int end_level, | |
4556 | bool lock_flush_tlb) | |
4557 | { | |
4558 | return slot_handle_level_range(kvm, memslot, fn, start_level, | |
4559 | end_level, memslot->base_gfn, | |
4560 | memslot->base_gfn + memslot->npages - 1, | |
4561 | lock_flush_tlb); | |
4562 | } | |
4563 | ||
4564 | static bool | |
4565 | slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
4566 | slot_level_handler fn, bool lock_flush_tlb) | |
4567 | { | |
4568 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL, | |
4569 | PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); | |
4570 | } | |
4571 | ||
4572 | static bool | |
4573 | slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
4574 | slot_level_handler fn, bool lock_flush_tlb) | |
4575 | { | |
4576 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1, | |
4577 | PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); | |
4578 | } | |
4579 | ||
4580 | static bool | |
4581 | slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
4582 | slot_level_handler fn, bool lock_flush_tlb) | |
4583 | { | |
4584 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL, | |
4585 | PT_PAGE_TABLE_LEVEL, lock_flush_tlb); | |
4586 | } | |
4587 | ||
efdfe536 XG |
4588 | void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end) |
4589 | { | |
4590 | struct kvm_memslots *slots; | |
4591 | struct kvm_memory_slot *memslot; | |
9da0e4d5 | 4592 | int i; |
efdfe536 XG |
4593 | |
4594 | spin_lock(&kvm->mmu_lock); | |
9da0e4d5 PB |
4595 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
4596 | slots = __kvm_memslots(kvm, i); | |
4597 | kvm_for_each_memslot(memslot, slots) { | |
4598 | gfn_t start, end; | |
4599 | ||
4600 | start = max(gfn_start, memslot->base_gfn); | |
4601 | end = min(gfn_end, memslot->base_gfn + memslot->npages); | |
4602 | if (start >= end) | |
4603 | continue; | |
efdfe536 | 4604 | |
9da0e4d5 PB |
4605 | slot_handle_level_range(kvm, memslot, kvm_zap_rmapp, |
4606 | PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL, | |
4607 | start, end - 1, true); | |
4608 | } | |
efdfe536 XG |
4609 | } |
4610 | ||
4611 | spin_unlock(&kvm->mmu_lock); | |
4612 | } | |
4613 | ||
018aabb5 TY |
4614 | static bool slot_rmap_write_protect(struct kvm *kvm, |
4615 | struct kvm_rmap_head *rmap_head) | |
d77aa73c | 4616 | { |
018aabb5 | 4617 | return __rmap_write_protect(kvm, rmap_head, false); |
d77aa73c XG |
4618 | } |
4619 | ||
1c91cad4 KH |
4620 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
4621 | struct kvm_memory_slot *memslot) | |
6aa8b732 | 4622 | { |
d77aa73c | 4623 | bool flush; |
6aa8b732 | 4624 | |
9d1beefb | 4625 | spin_lock(&kvm->mmu_lock); |
d77aa73c XG |
4626 | flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect, |
4627 | false); | |
9d1beefb | 4628 | spin_unlock(&kvm->mmu_lock); |
198c74f4 XG |
4629 | |
4630 | /* | |
4631 | * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log() | |
4632 | * which do tlb flush out of mmu-lock should be serialized by | |
4633 | * kvm->slots_lock otherwise tlb flush would be missed. | |
4634 | */ | |
4635 | lockdep_assert_held(&kvm->slots_lock); | |
4636 | ||
4637 | /* | |
4638 | * We can flush all the TLBs out of the mmu lock without TLB | |
4639 | * corruption since we just change the spte from writable to | |
4640 | * readonly so that we only need to care the case of changing | |
4641 | * spte from present to present (changing the spte from present | |
4642 | * to nonpresent will flush all the TLBs immediately), in other | |
4643 | * words, the only case we care is mmu_spte_update() where we | |
4644 | * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE | |
4645 | * instead of PT_WRITABLE_MASK, that means it does not depend | |
4646 | * on PT_WRITABLE_MASK anymore. | |
4647 | */ | |
d91ffee9 KH |
4648 | if (flush) |
4649 | kvm_flush_remote_tlbs(kvm); | |
6aa8b732 | 4650 | } |
37a7d8b0 | 4651 | |
3ea3b7fa | 4652 | static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm, |
018aabb5 | 4653 | struct kvm_rmap_head *rmap_head) |
3ea3b7fa WL |
4654 | { |
4655 | u64 *sptep; | |
4656 | struct rmap_iterator iter; | |
4657 | int need_tlb_flush = 0; | |
ba049e93 | 4658 | kvm_pfn_t pfn; |
3ea3b7fa WL |
4659 | struct kvm_mmu_page *sp; |
4660 | ||
0d536790 | 4661 | restart: |
018aabb5 | 4662 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
3ea3b7fa WL |
4663 | sp = page_header(__pa(sptep)); |
4664 | pfn = spte_to_pfn(*sptep); | |
4665 | ||
4666 | /* | |
decf6333 XG |
4667 | * We cannot do huge page mapping for indirect shadow pages, |
4668 | * which are found on the last rmap (level = 1) when not using | |
4669 | * tdp; such shadow pages are synced with the page table in | |
4670 | * the guest, and the guest page table is using 4K page size | |
4671 | * mapping if the indirect sp has level = 1. | |
3ea3b7fa WL |
4672 | */ |
4673 | if (sp->role.direct && | |
4674 | !kvm_is_reserved_pfn(pfn) && | |
4675 | PageTransCompound(pfn_to_page(pfn))) { | |
4676 | drop_spte(kvm, sptep); | |
3ea3b7fa | 4677 | need_tlb_flush = 1; |
0d536790 XG |
4678 | goto restart; |
4679 | } | |
3ea3b7fa WL |
4680 | } |
4681 | ||
4682 | return need_tlb_flush; | |
4683 | } | |
4684 | ||
4685 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, | |
f36f3f28 | 4686 | const struct kvm_memory_slot *memslot) |
3ea3b7fa | 4687 | { |
f36f3f28 | 4688 | /* FIXME: const-ify all uses of struct kvm_memory_slot. */ |
3ea3b7fa | 4689 | spin_lock(&kvm->mmu_lock); |
f36f3f28 PB |
4690 | slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot, |
4691 | kvm_mmu_zap_collapsible_spte, true); | |
3ea3b7fa WL |
4692 | spin_unlock(&kvm->mmu_lock); |
4693 | } | |
4694 | ||
f4b4b180 KH |
4695 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
4696 | struct kvm_memory_slot *memslot) | |
4697 | { | |
d77aa73c | 4698 | bool flush; |
f4b4b180 KH |
4699 | |
4700 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 4701 | flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false); |
f4b4b180 KH |
4702 | spin_unlock(&kvm->mmu_lock); |
4703 | ||
4704 | lockdep_assert_held(&kvm->slots_lock); | |
4705 | ||
4706 | /* | |
4707 | * It's also safe to flush TLBs out of mmu lock here as currently this | |
4708 | * function is only used for dirty logging, in which case flushing TLB | |
4709 | * out of mmu lock also guarantees no dirty pages will be lost in | |
4710 | * dirty_bitmap. | |
4711 | */ | |
4712 | if (flush) | |
4713 | kvm_flush_remote_tlbs(kvm); | |
4714 | } | |
4715 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty); | |
4716 | ||
4717 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
4718 | struct kvm_memory_slot *memslot) | |
4719 | { | |
d77aa73c | 4720 | bool flush; |
f4b4b180 KH |
4721 | |
4722 | spin_lock(&kvm->mmu_lock); | |
d77aa73c XG |
4723 | flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect, |
4724 | false); | |
f4b4b180 KH |
4725 | spin_unlock(&kvm->mmu_lock); |
4726 | ||
4727 | /* see kvm_mmu_slot_remove_write_access */ | |
4728 | lockdep_assert_held(&kvm->slots_lock); | |
4729 | ||
4730 | if (flush) | |
4731 | kvm_flush_remote_tlbs(kvm); | |
4732 | } | |
4733 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access); | |
4734 | ||
4735 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
4736 | struct kvm_memory_slot *memslot) | |
4737 | { | |
d77aa73c | 4738 | bool flush; |
f4b4b180 KH |
4739 | |
4740 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 4741 | flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false); |
f4b4b180 KH |
4742 | spin_unlock(&kvm->mmu_lock); |
4743 | ||
4744 | lockdep_assert_held(&kvm->slots_lock); | |
4745 | ||
4746 | /* see kvm_mmu_slot_leaf_clear_dirty */ | |
4747 | if (flush) | |
4748 | kvm_flush_remote_tlbs(kvm); | |
4749 | } | |
4750 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty); | |
4751 | ||
e7d11c7a | 4752 | #define BATCH_ZAP_PAGES 10 |
5304b8d3 XG |
4753 | static void kvm_zap_obsolete_pages(struct kvm *kvm) |
4754 | { | |
4755 | struct kvm_mmu_page *sp, *node; | |
e7d11c7a | 4756 | int batch = 0; |
5304b8d3 XG |
4757 | |
4758 | restart: | |
4759 | list_for_each_entry_safe_reverse(sp, node, | |
4760 | &kvm->arch.active_mmu_pages, link) { | |
e7d11c7a XG |
4761 | int ret; |
4762 | ||
5304b8d3 XG |
4763 | /* |
4764 | * No obsolete page exists before new created page since | |
4765 | * active_mmu_pages is the FIFO list. | |
4766 | */ | |
4767 | if (!is_obsolete_sp(kvm, sp)) | |
4768 | break; | |
4769 | ||
4770 | /* | |
5304b8d3 XG |
4771 | * Since we are reversely walking the list and the invalid |
4772 | * list will be moved to the head, skip the invalid page | |
4773 | * can help us to avoid the infinity list walking. | |
4774 | */ | |
4775 | if (sp->role.invalid) | |
4776 | continue; | |
4777 | ||
f34d251d XG |
4778 | /* |
4779 | * Need not flush tlb since we only zap the sp with invalid | |
4780 | * generation number. | |
4781 | */ | |
e7d11c7a | 4782 | if (batch >= BATCH_ZAP_PAGES && |
f34d251d | 4783 | cond_resched_lock(&kvm->mmu_lock)) { |
e7d11c7a | 4784 | batch = 0; |
5304b8d3 XG |
4785 | goto restart; |
4786 | } | |
4787 | ||
365c8868 XG |
4788 | ret = kvm_mmu_prepare_zap_page(kvm, sp, |
4789 | &kvm->arch.zapped_obsolete_pages); | |
e7d11c7a XG |
4790 | batch += ret; |
4791 | ||
4792 | if (ret) | |
5304b8d3 XG |
4793 | goto restart; |
4794 | } | |
4795 | ||
f34d251d XG |
4796 | /* |
4797 | * Should flush tlb before free page tables since lockless-walking | |
4798 | * may use the pages. | |
4799 | */ | |
365c8868 | 4800 | kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages); |
5304b8d3 XG |
4801 | } |
4802 | ||
4803 | /* | |
4804 | * Fast invalidate all shadow pages and use lock-break technique | |
4805 | * to zap obsolete pages. | |
4806 | * | |
4807 | * It's required when memslot is being deleted or VM is being | |
4808 | * destroyed, in these cases, we should ensure that KVM MMU does | |
4809 | * not use any resource of the being-deleted slot or all slots | |
4810 | * after calling the function. | |
4811 | */ | |
4812 | void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm) | |
4813 | { | |
4814 | spin_lock(&kvm->mmu_lock); | |
35006126 | 4815 | trace_kvm_mmu_invalidate_zap_all_pages(kvm); |
5304b8d3 XG |
4816 | kvm->arch.mmu_valid_gen++; |
4817 | ||
f34d251d XG |
4818 | /* |
4819 | * Notify all vcpus to reload its shadow page table | |
4820 | * and flush TLB. Then all vcpus will switch to new | |
4821 | * shadow page table with the new mmu_valid_gen. | |
4822 | * | |
4823 | * Note: we should do this under the protection of | |
4824 | * mmu-lock, otherwise, vcpu would purge shadow page | |
4825 | * but miss tlb flush. | |
4826 | */ | |
4827 | kvm_reload_remote_mmus(kvm); | |
4828 | ||
5304b8d3 XG |
4829 | kvm_zap_obsolete_pages(kvm); |
4830 | spin_unlock(&kvm->mmu_lock); | |
4831 | } | |
4832 | ||
365c8868 XG |
4833 | static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm) |
4834 | { | |
4835 | return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages)); | |
4836 | } | |
4837 | ||
54bf36aa | 4838 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots) |
f8f55942 XG |
4839 | { |
4840 | /* | |
4841 | * The very rare case: if the generation-number is round, | |
4842 | * zap all shadow pages. | |
f8f55942 | 4843 | */ |
54bf36aa | 4844 | if (unlikely((slots->generation & MMIO_GEN_MASK) == 0)) { |
a629df7e | 4845 | printk_ratelimited(KERN_DEBUG "kvm: zapping shadow pages for mmio generation wraparound\n"); |
a8eca9dc | 4846 | kvm_mmu_invalidate_zap_all_pages(kvm); |
7a2e8aaf | 4847 | } |
f8f55942 XG |
4848 | } |
4849 | ||
70534a73 DC |
4850 | static unsigned long |
4851 | mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) | |
3ee16c81 IE |
4852 | { |
4853 | struct kvm *kvm; | |
1495f230 | 4854 | int nr_to_scan = sc->nr_to_scan; |
70534a73 | 4855 | unsigned long freed = 0; |
3ee16c81 | 4856 | |
2f303b74 | 4857 | spin_lock(&kvm_lock); |
3ee16c81 IE |
4858 | |
4859 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 4860 | int idx; |
d98ba053 | 4861 | LIST_HEAD(invalid_list); |
3ee16c81 | 4862 | |
35f2d16b TY |
4863 | /* |
4864 | * Never scan more than sc->nr_to_scan VM instances. | |
4865 | * Will not hit this condition practically since we do not try | |
4866 | * to shrink more than one VM and it is very unlikely to see | |
4867 | * !n_used_mmu_pages so many times. | |
4868 | */ | |
4869 | if (!nr_to_scan--) | |
4870 | break; | |
19526396 GN |
4871 | /* |
4872 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
4873 | * here. We may skip a VM instance errorneosly, but we do not | |
4874 | * want to shrink a VM that only started to populate its MMU | |
4875 | * anyway. | |
4876 | */ | |
365c8868 XG |
4877 | if (!kvm->arch.n_used_mmu_pages && |
4878 | !kvm_has_zapped_obsolete_pages(kvm)) | |
19526396 | 4879 | continue; |
19526396 | 4880 | |
f656ce01 | 4881 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 4882 | spin_lock(&kvm->mmu_lock); |
3ee16c81 | 4883 | |
365c8868 XG |
4884 | if (kvm_has_zapped_obsolete_pages(kvm)) { |
4885 | kvm_mmu_commit_zap_page(kvm, | |
4886 | &kvm->arch.zapped_obsolete_pages); | |
4887 | goto unlock; | |
4888 | } | |
4889 | ||
70534a73 DC |
4890 | if (prepare_zap_oldest_mmu_page(kvm, &invalid_list)) |
4891 | freed++; | |
d98ba053 | 4892 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
19526396 | 4893 | |
365c8868 | 4894 | unlock: |
3ee16c81 | 4895 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 4896 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 | 4897 | |
70534a73 DC |
4898 | /* |
4899 | * unfair on small ones | |
4900 | * per-vm shrinkers cry out | |
4901 | * sadness comes quickly | |
4902 | */ | |
19526396 GN |
4903 | list_move_tail(&kvm->vm_list, &vm_list); |
4904 | break; | |
3ee16c81 | 4905 | } |
3ee16c81 | 4906 | |
2f303b74 | 4907 | spin_unlock(&kvm_lock); |
70534a73 | 4908 | return freed; |
70534a73 DC |
4909 | } |
4910 | ||
4911 | static unsigned long | |
4912 | mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc) | |
4913 | { | |
45221ab6 | 4914 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
4915 | } |
4916 | ||
4917 | static struct shrinker mmu_shrinker = { | |
70534a73 DC |
4918 | .count_objects = mmu_shrink_count, |
4919 | .scan_objects = mmu_shrink_scan, | |
3ee16c81 IE |
4920 | .seeks = DEFAULT_SEEKS * 10, |
4921 | }; | |
4922 | ||
2ddfd20e | 4923 | static void mmu_destroy_caches(void) |
b5a33a75 | 4924 | { |
53c07b18 XG |
4925 | if (pte_list_desc_cache) |
4926 | kmem_cache_destroy(pte_list_desc_cache); | |
d3d25b04 AK |
4927 | if (mmu_page_header_cache) |
4928 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
4929 | } |
4930 | ||
4931 | int kvm_mmu_module_init(void) | |
4932 | { | |
53c07b18 XG |
4933 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
4934 | sizeof(struct pte_list_desc), | |
20c2df83 | 4935 | 0, 0, NULL); |
53c07b18 | 4936 | if (!pte_list_desc_cache) |
b5a33a75 AK |
4937 | goto nomem; |
4938 | ||
d3d25b04 AK |
4939 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
4940 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 4941 | 0, 0, NULL); |
d3d25b04 AK |
4942 | if (!mmu_page_header_cache) |
4943 | goto nomem; | |
4944 | ||
908c7f19 | 4945 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL)) |
45bf21a8 WY |
4946 | goto nomem; |
4947 | ||
3ee16c81 IE |
4948 | register_shrinker(&mmu_shrinker); |
4949 | ||
b5a33a75 AK |
4950 | return 0; |
4951 | ||
4952 | nomem: | |
3ee16c81 | 4953 | mmu_destroy_caches(); |
b5a33a75 AK |
4954 | return -ENOMEM; |
4955 | } | |
4956 | ||
3ad82a7e ZX |
4957 | /* |
4958 | * Caculate mmu pages needed for kvm. | |
4959 | */ | |
4960 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
4961 | { | |
3ad82a7e ZX |
4962 | unsigned int nr_mmu_pages; |
4963 | unsigned int nr_pages = 0; | |
bc6678a3 | 4964 | struct kvm_memslots *slots; |
be6ba0f0 | 4965 | struct kvm_memory_slot *memslot; |
9da0e4d5 | 4966 | int i; |
3ad82a7e | 4967 | |
9da0e4d5 PB |
4968 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
4969 | slots = __kvm_memslots(kvm, i); | |
90d83dc3 | 4970 | |
9da0e4d5 PB |
4971 | kvm_for_each_memslot(memslot, slots) |
4972 | nr_pages += memslot->npages; | |
4973 | } | |
3ad82a7e ZX |
4974 | |
4975 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
4976 | nr_mmu_pages = max(nr_mmu_pages, | |
9da0e4d5 | 4977 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); |
3ad82a7e ZX |
4978 | |
4979 | return nr_mmu_pages; | |
4980 | } | |
4981 | ||
c42fffe3 XG |
4982 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
4983 | { | |
95f93af4 | 4984 | kvm_mmu_unload(vcpu); |
c42fffe3 XG |
4985 | free_mmu_pages(vcpu); |
4986 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
4987 | } |
4988 | ||
b034cf01 XG |
4989 | void kvm_mmu_module_exit(void) |
4990 | { | |
4991 | mmu_destroy_caches(); | |
4992 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
4993 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
4994 | mmu_audit_disable(); |
4995 | } |