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KVM: MMU: reduce 'struct kvm_mmu_page' size
[linux-2.6-block.git] / arch / x86 / kvm / mmu.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 *
11 * Authors:
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
14 *
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
17 *
18 */
e495606d 19
1d737c8a 20#include "mmu.h"
836a1b3c 21#include "x86.h"
6de4f3ad 22#include "kvm_cache_regs.h"
e495606d 23
edf88417 24#include <linux/kvm_host.h>
6aa8b732
AK		 25#include <linux/types.h>
26#include <linux/string.h>
6aa8b732
AK		 27#include <linux/mm.h>
28#include <linux/highmem.h>
29#include <linux/module.h>
448353ca 30#include <linux/swap.h>
05da4558 31#include <linux/hugetlb.h>
2f333bcb 32#include <linux/compiler.h>
bc6678a3 33#include <linux/srcu.h>
5a0e3ad6 34#include <linux/slab.h>
6aa8b732 35
e495606d
AK		 36#include <asm/page.h>
37#include <asm/cmpxchg.h>
4e542370 38#include <asm/io.h>
13673a90 39#include <asm/vmx.h>
6aa8b732 40
18552672
JR		 41/*
42 * When setting this variable to true it enables Two-Dimensional-Paging
43 * where the hardware walks 2 page tables:
44 * 1. the guest-virtual to guest-physical
45 * 2. while doing 1. it walks guest-physical to host-physical
46 * If the hardware supports that we don't need to do shadow paging.
47 */
2f333bcb 48bool tdp_enabled = false;
18552672 49
37a7d8b0
AK		 50#undef MMU_DEBUG
51
52#undef AUDIT
53
54#ifdef AUDIT
55static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg);
56#else
57static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {}
58#endif
59
60#ifdef MMU_DEBUG
61
62#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
63#define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
64
65#else
66
67#define pgprintk(x...) do { } while (0)
68#define rmap_printk(x...) do { } while (0)
69
70#endif
71
72#if defined(MMU_DEBUG) || defined(AUDIT)
6ada8cca
AK		 73static int dbg = 0;
74module_param(dbg, bool, 0644);
37a7d8b0 75#endif
6aa8b732 76
582801a9
MT		 77static int oos_shadow = 1;
78module_param(oos_shadow, bool, 0644);
79
d6c69ee9
YD		 80#ifndef MMU_DEBUG
81#define ASSERT(x) do { } while (0)
82#else
6aa8b732
AK		 83#define ASSERT(x) \
84 if (!(x)) { \
85 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
86 __FILE__, __LINE__, #x); \
87 }
d6c69ee9 88#endif
6aa8b732 89
6aa8b732
AK		 90#define PT_FIRST_AVAIL_BITS_SHIFT 9
91#define PT64_SECOND_AVAIL_BITS_SHIFT 52
92
6aa8b732
AK		 93#define VALID_PAGE(x) ((x) != INVALID_PAGE)
94
95#define PT64_LEVEL_BITS 9
96
97#define PT64_LEVEL_SHIFT(level) \
d77c26fc 98 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
6aa8b732
AK		 99
100#define PT64_LEVEL_MASK(level) \
101 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
102
103#define PT64_INDEX(address, level)\
104 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
105
106
107#define PT32_LEVEL_BITS 10
108
109#define PT32_LEVEL_SHIFT(level) \
d77c26fc 110 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
6aa8b732
AK		 111
112#define PT32_LEVEL_MASK(level) \
113 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
e04da980
JR		 114#define PT32_LVL_OFFSET_MASK(level) \
115 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
116 * PT32_LEVEL_BITS))) - 1))
6aa8b732
AK		 117
118#define PT32_INDEX(address, level)\
119 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
120
121
27aba766 122#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
6aa8b732
AK		 123#define PT64_DIR_BASE_ADDR_MASK \
124 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
e04da980
JR		 125#define PT64_LVL_ADDR_MASK(level) \
126 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
127 * PT64_LEVEL_BITS))) - 1))
128#define PT64_LVL_OFFSET_MASK(level) \
129 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
130 * PT64_LEVEL_BITS))) - 1))
6aa8b732
AK		 131
132#define PT32_BASE_ADDR_MASK PAGE_MASK
133#define PT32_DIR_BASE_ADDR_MASK \
134 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
e04da980
JR		 135#define PT32_LVL_ADDR_MASK(level) \
136 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
137 * PT32_LEVEL_BITS))) - 1))
6aa8b732 138
79539cec
AK		 139#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
140 | PT64_NX_MASK)
6aa8b732 141
cd4a4e53
AK		 142#define RMAP_EXT 4
143
fe135d2c
AK		 144#define ACC_EXEC_MASK 1
145#define ACC_WRITE_MASK PT_WRITABLE_MASK
146#define ACC_USER_MASK PT_USER_MASK
147#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
148
90bb6fc5
AK		 149#include <trace/events/kvm.h>
150
07420171
AK		 151#define CREATE_TRACE_POINTS
152#include "mmutrace.h"
153
1403283a
IE		 154#define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
155
135f8c2b
AK		 156#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
157
cd4a4e53 158struct kvm_rmap_desc {
d555c333 159 u64 *sptes[RMAP_EXT];
cd4a4e53
AK		 160 struct kvm_rmap_desc *more;
161};
162
2d11123a
AK		 163struct kvm_shadow_walk_iterator {
164 u64 addr;
165 hpa_t shadow_addr;
166 int level;
167 u64 *sptep;
168 unsigned index;
169};
170
171#define for_each_shadow_entry(_vcpu, _addr, _walker) \
172 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
173 shadow_walk_okay(&(_walker)); \
174 shadow_walk_next(&(_walker)))
175
ad8cfbe3
MT		 176typedef int (*mmu_parent_walk_fn) (struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp);
177
b5a33a75
AK		 178static struct kmem_cache *pte_chain_cache;
179static struct kmem_cache *rmap_desc_cache;
d3d25b04 180static struct kmem_cache *mmu_page_header_cache;
b5a33a75 181
c7addb90
AK		 182static u64 __read_mostly shadow_trap_nonpresent_pte;
183static u64 __read_mostly shadow_notrap_nonpresent_pte;
7b52345e
SY		 184static u64 __read_mostly shadow_base_present_pte;
185static u64 __read_mostly shadow_nx_mask;
186static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
187static u64 __read_mostly shadow_user_mask;
188static u64 __read_mostly shadow_accessed_mask;
189static u64 __read_mostly shadow_dirty_mask;
c7addb90 190
82725b20
DE		 191static inline u64 rsvd_bits(int s, int e)
192{
193 return ((1ULL << (e - s + 1)) - 1) << s;
194}
195
c7addb90
AK		 196void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
197{
198 shadow_trap_nonpresent_pte = trap_pte;
199 shadow_notrap_nonpresent_pte = notrap_pte;
200}
201EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
202
7b52345e
SY		 203void kvm_mmu_set_base_ptes(u64 base_pte)
204{
205 shadow_base_present_pte = base_pte;
206}
207EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes);
208
209void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
4b12f0de 210 u64 dirty_mask, u64 nx_mask, u64 x_mask)
7b52345e
SY		 211{
212 shadow_user_mask = user_mask;
213 shadow_accessed_mask = accessed_mask;
214 shadow_dirty_mask = dirty_mask;
215 shadow_nx_mask = nx_mask;
216 shadow_x_mask = x_mask;
217}
218EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
219
6aa8b732
AK		 220static int is_write_protection(struct kvm_vcpu *vcpu)
221{
4d4ec087 222 return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
6aa8b732
AK		 223}
224
225static int is_cpuid_PSE36(void)
226{
227 return 1;
228}
229
73b1087e
AK		 230static int is_nx(struct kvm_vcpu *vcpu)
231{
f6801dff 232 return vcpu->arch.efer & EFER_NX;
73b1087e
AK		 233}
234
c7addb90
AK		 235static int is_shadow_present_pte(u64 pte)
236{
c7addb90
AK		 237 return pte != shadow_trap_nonpresent_pte
238 && pte != shadow_notrap_nonpresent_pte;
239}
240
05da4558
MT		 241static int is_large_pte(u64 pte)
242{
243 return pte & PT_PAGE_SIZE_MASK;
244}
245
8dae4445 246static int is_writable_pte(unsigned long pte)
6aa8b732
AK		 247{
248 return pte & PT_WRITABLE_MASK;
249}
250
43a3795a 251static int is_dirty_gpte(unsigned long pte)
e3c5e7ec 252{
439e218a 253 return pte & PT_DIRTY_MASK;
e3c5e7ec
AK		 254}
255
43a3795a 256static int is_rmap_spte(u64 pte)
cd4a4e53 257{
4b1a80fa 258 return is_shadow_present_pte(pte);
cd4a4e53
AK		 259}
260
776e6633
MT		 261static int is_last_spte(u64 pte, int level)
262{
263 if (level == PT_PAGE_TABLE_LEVEL)
264 return 1;
852e3c19 265 if (is_large_pte(pte))
776e6633
MT		 266 return 1;
267 return 0;
268}
269
35149e21 270static pfn_t spte_to_pfn(u64 pte)
0b49ea86 271{
35149e21 272 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
0b49ea86
AK		 273}
274
da928521
AK		 275static gfn_t pse36_gfn_delta(u32 gpte)
276{
277 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
278
279 return (gpte & PT32_DIR_PSE36_MASK) << shift;
280}
281
d555c333 282static void __set_spte(u64 *sptep, u64 spte)
e663ee64
AK		 283{
284#ifdef CONFIG_X86_64
285 set_64bit((unsigned long *)sptep, spte);
286#else
287 set_64bit((unsigned long long *)sptep, spte);
288#endif
289}
290
e2dec939 291static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
2e3e5882 292 struct kmem_cache *base_cache, int min)
714b93da
AK		 293{
294 void *obj;
295
296 if (cache->nobjs >= min)
e2dec939 297 return 0;
714b93da 298 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 299 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
714b93da 300 if (!obj)
e2dec939 301 return -ENOMEM;
714b93da
AK		 302 cache->objects[cache->nobjs++] = obj;
303 }
e2dec939 304 return 0;
714b93da
AK		 305}
306
307static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc)
308{
309 while (mc->nobjs)
310 kfree(mc->objects[--mc->nobjs]);
311}
312
c1158e63 313static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
2e3e5882 314 int min)
c1158e63
AK		 315{
316 struct page *page;
317
318 if (cache->nobjs >= min)
319 return 0;
320 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 321 page = alloc_page(GFP_KERNEL);
c1158e63
AK		 322 if (!page)
323 return -ENOMEM;
c1158e63
AK		 324 cache->objects[cache->nobjs++] = page_address(page);
325 }
326 return 0;
327}
328
329static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
330{
331 while (mc->nobjs)
c4d198d5 332 free_page((unsigned long)mc->objects[--mc->nobjs]);
c1158e63
AK		 333}
334
2e3e5882 335static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
714b93da 336{
e2dec939
AK		 337 int r;
338
ad312c7c 339 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
2e3e5882 340 pte_chain_cache, 4);
e2dec939
AK		 341 if (r)
342 goto out;
ad312c7c 343 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
c41ef344 344 rmap_desc_cache, 4);
d3d25b04
AK		 345 if (r)
346 goto out;
ad312c7c 347 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
d3d25b04
AK		 348 if (r)
349 goto out;
ad312c7c 350 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
2e3e5882 351 mmu_page_header_cache, 4);
e2dec939
AK		 352out:
353 return r;
714b93da
AK		 354}
355
356static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
357{
ad312c7c
ZX		 358 mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache);
359 mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache);
360 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
361 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
714b93da
AK		 362}
363
364static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
365 size_t size)
366{
367 void *p;
368
369 BUG_ON(!mc->nobjs);
370 p = mc->objects[--mc->nobjs];
714b93da
AK		 371 return p;
372}
373
714b93da
AK		 374static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
375{
ad312c7c 376 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
714b93da
AK		 377 sizeof(struct kvm_pte_chain));
378}
379
90cb0529 380static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
714b93da 381{
90cb0529 382 kfree(pc);
714b93da
AK		 383}
384
385static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
386{
ad312c7c 387 return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
714b93da
AK		 388 sizeof(struct kvm_rmap_desc));
389}
390
90cb0529 391static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
714b93da 392{
90cb0529 393 kfree(rd);
714b93da
AK		 394}
395
05da4558
MT		 396/*
397 * Return the pointer to the largepage write count for a given
398 * gfn, handling slots that are not large page aligned.
399 */
d25797b2
JR		 400static int *slot_largepage_idx(gfn_t gfn,
401 struct kvm_memory_slot *slot,
402 int level)
05da4558
MT		 403{
404 unsigned long idx;
405
d25797b2
JR		 406 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
407 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
408 return &slot->lpage_info[level - 2][idx].write_count;
05da4558
MT		 409}
410
411static void account_shadowed(struct kvm *kvm, gfn_t gfn)
412{
d25797b2 413 struct kvm_memory_slot *slot;
05da4558 414 int *write_count;
d25797b2 415 int i;
05da4558 416
2843099f 417 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR		 418
419 slot = gfn_to_memslot_unaliased(kvm, gfn);
420 for (i = PT_DIRECTORY_LEVEL;
421 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
422 write_count = slot_largepage_idx(gfn, slot, i);
423 *write_count += 1;
424 }
05da4558
MT		 425}
426
427static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
428{
d25797b2 429 struct kvm_memory_slot *slot;
05da4558 430 int *write_count;
d25797b2 431 int i;
05da4558 432
2843099f 433 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR		 434 for (i = PT_DIRECTORY_LEVEL;
435 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
436 slot = gfn_to_memslot_unaliased(kvm, gfn);
437 write_count = slot_largepage_idx(gfn, slot, i);
438 *write_count -= 1;
439 WARN_ON(*write_count < 0);
440 }
05da4558
MT		 441}
442
d25797b2
JR		 443static int has_wrprotected_page(struct kvm *kvm,
444 gfn_t gfn,
445 int level)
05da4558 446{
2843099f 447 struct kvm_memory_slot *slot;
05da4558
MT		 448 int *largepage_idx;
449
2843099f
IE		 450 gfn = unalias_gfn(kvm, gfn);
451 slot = gfn_to_memslot_unaliased(kvm, gfn);
05da4558 452 if (slot) {
d25797b2 453 largepage_idx = slot_largepage_idx(gfn, slot, level);
05da4558
MT		 454 return *largepage_idx;
455 }
456
457 return 1;
458}
459
d25797b2 460static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
05da4558 461{
8f0b1ab6 462 unsigned long page_size;
d25797b2 463 int i, ret = 0;
05da4558 464
8f0b1ab6 465 page_size = kvm_host_page_size(kvm, gfn);
05da4558 466
d25797b2
JR		 467 for (i = PT_PAGE_TABLE_LEVEL;
468 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
469 if (page_size >= KVM_HPAGE_SIZE(i))
470 ret = i;
471 else
472 break;
473 }
474
4c2155ce 475 return ret;
05da4558
MT		 476}
477
d25797b2 478static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
05da4558
MT		 479{
480 struct kvm_memory_slot *slot;
878403b7 481 int host_level, level, max_level;
05da4558
MT		 482
483 slot = gfn_to_memslot(vcpu->kvm, large_gfn);
484 if (slot && slot->dirty_bitmap)
d25797b2 485 return PT_PAGE_TABLE_LEVEL;
05da4558 486
d25797b2
JR		 487 host_level = host_mapping_level(vcpu->kvm, large_gfn);
488
489 if (host_level == PT_PAGE_TABLE_LEVEL)
490 return host_level;
491
878403b7
SY		 492 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
493 kvm_x86_ops->get_lpage_level() : host_level;
494
495 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
d25797b2
JR		 496 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
497 break;
d25797b2
JR		 498
499 return level - 1;
05da4558
MT		 500}
501
290fc38d
IE		 502/*
503 * Take gfn and return the reverse mapping to it.
504 * Note: gfn must be unaliased before this function get called
505 */
506
44ad9944 507static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
290fc38d
IE		 508{
509 struct kvm_memory_slot *slot;
05da4558 510 unsigned long idx;
290fc38d
IE		 511
512 slot = gfn_to_memslot(kvm, gfn);
44ad9944 513 if (likely(level == PT_PAGE_TABLE_LEVEL))
05da4558
MT		 514 return &slot->rmap[gfn - slot->base_gfn];
515
44ad9944
JR		 516 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
517 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
05da4558 518
44ad9944 519 return &slot->lpage_info[level - 2][idx].rmap_pde;
290fc38d
IE		 520}
521
cd4a4e53
AK		 522/*
523 * Reverse mapping data structures:
524 *
290fc38d
IE		 525 * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
526 * that points to page_address(page).
cd4a4e53 527 *
290fc38d
IE		 528 * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
529 * containing more mappings.
53a27b39
MT		 530 *
531 * Returns the number of rmap entries before the spte was added or zero if
532 * the spte was not added.
533 *
cd4a4e53 534 */
44ad9944 535static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
cd4a4e53 536{
4db35314 537 struct kvm_mmu_page *sp;
cd4a4e53 538 struct kvm_rmap_desc *desc;
290fc38d 539 unsigned long *rmapp;
53a27b39 540 int i, count = 0;
cd4a4e53 541
43a3795a 542 if (!is_rmap_spte(*spte))
53a27b39 543 return count;
290fc38d 544 gfn = unalias_gfn(vcpu->kvm, gfn);
4db35314
AK		 545 sp = page_header(__pa(spte));
546 sp->gfns[spte - sp->spt] = gfn;
44ad9944 547 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
290fc38d 548 if (!*rmapp) {
cd4a4e53 549 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
290fc38d
IE		 550 *rmapp = (unsigned long)spte;
551 } else if (!(*rmapp & 1)) {
cd4a4e53 552 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
714b93da 553 desc = mmu_alloc_rmap_desc(vcpu);
d555c333
AK		 554 desc->sptes[0] = (u64 *)*rmapp;
555 desc->sptes[1] = spte;
290fc38d 556 *rmapp = (unsigned long)desc | 1;
cd4a4e53
AK		 557 } else {
558 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
290fc38d 559 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
d555c333 560 while (desc->sptes[RMAP_EXT-1] && desc->more) {
cd4a4e53 561 desc = desc->more;
53a27b39
MT		 562 count += RMAP_EXT;
563 }
d555c333 564 if (desc->sptes[RMAP_EXT-1]) {
714b93da 565 desc->more = mmu_alloc_rmap_desc(vcpu);
cd4a4e53
AK		 566 desc = desc->more;
567 }
d555c333 568 for (i = 0; desc->sptes[i]; ++i)
cd4a4e53 569 ;
d555c333 570 desc->sptes[i] = spte;
cd4a4e53 571 }
53a27b39 572 return count;
cd4a4e53
AK		 573}
574
290fc38d 575static void rmap_desc_remove_entry(unsigned long *rmapp,
cd4a4e53
AK		 576 struct kvm_rmap_desc *desc,
577 int i,
578 struct kvm_rmap_desc *prev_desc)
579{
580 int j;
581
d555c333 582 for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j)
cd4a4e53 583 ;
d555c333
AK		 584 desc->sptes[i] = desc->sptes[j];
585 desc->sptes[j] = NULL;
cd4a4e53
AK		 586 if (j != 0)
587 return;
588 if (!prev_desc && !desc->more)
d555c333 589 *rmapp = (unsigned long)desc->sptes[0];
cd4a4e53
AK		 590 else
591 if (prev_desc)
592 prev_desc->more = desc->more;
593 else
290fc38d 594 *rmapp = (unsigned long)desc->more | 1;
90cb0529 595 mmu_free_rmap_desc(desc);
cd4a4e53
AK		 596}
597
290fc38d 598static void rmap_remove(struct kvm *kvm, u64 *spte)
cd4a4e53 599{
cd4a4e53
AK		 600 struct kvm_rmap_desc *desc;
601 struct kvm_rmap_desc *prev_desc;
4db35314 602 struct kvm_mmu_page *sp;
35149e21 603 pfn_t pfn;
290fc38d 604 unsigned long *rmapp;
cd4a4e53
AK		 605 int i;
606
43a3795a 607 if (!is_rmap_spte(*spte))
cd4a4e53 608 return;
4db35314 609 sp = page_header(__pa(spte));
35149e21 610 pfn = spte_to_pfn(*spte);
7b52345e 611 if (*spte & shadow_accessed_mask)
35149e21 612 kvm_set_pfn_accessed(pfn);
8dae4445 613 if (is_writable_pte(*spte))
acb66dd0 614 kvm_set_pfn_dirty(pfn);
44ad9944 615 rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], sp->role.level);
290fc38d 616 if (!*rmapp) {
cd4a4e53
AK		 617 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
618 BUG();
290fc38d 619 } else if (!(*rmapp & 1)) {
cd4a4e53 620 rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte);
290fc38d 621 if ((u64 *)*rmapp != spte) {
cd4a4e53
AK		 622 printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n",
623 spte, *spte);
624 BUG();
625 }
290fc38d 626 *rmapp = 0;
cd4a4e53
AK		 627 } else {
628 rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte);
290fc38d 629 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
cd4a4e53
AK		 630 prev_desc = NULL;
631 while (desc) {
d555c333
AK		 632 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i)
633 if (desc->sptes[i] == spte) {
290fc38d 634 rmap_desc_remove_entry(rmapp,
714b93da 635 desc, i,
cd4a4e53
AK		 636 prev_desc);
637 return;
638 }
639 prev_desc = desc;
640 desc = desc->more;
641 }
186a3e52 642 pr_err("rmap_remove: %p %llx many->many\n", spte, *spte);
cd4a4e53
AK		 643 BUG();
644 }
645}
646
98348e95 647static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
374cbac0 648{
374cbac0 649 struct kvm_rmap_desc *desc;
98348e95
IE		 650 struct kvm_rmap_desc *prev_desc;
651 u64 *prev_spte;
652 int i;
653
654 if (!*rmapp)
655 return NULL;
656 else if (!(*rmapp & 1)) {
657 if (!spte)
658 return (u64 *)*rmapp;
659 return NULL;
660 }
661 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
662 prev_desc = NULL;
663 prev_spte = NULL;
664 while (desc) {
d555c333 665 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) {
98348e95 666 if (prev_spte == spte)
d555c333
AK		 667 return desc->sptes[i];
668 prev_spte = desc->sptes[i];
98348e95
IE		 669 }
670 desc = desc->more;
671 }
672 return NULL;
673}
674
b1a36821 675static int rmap_write_protect(struct kvm *kvm, u64 gfn)
98348e95 676{
290fc38d 677 unsigned long *rmapp;
374cbac0 678 u64 *spte;
44ad9944 679 int i, write_protected = 0;
374cbac0 680
4a4c9924 681 gfn = unalias_gfn(kvm, gfn);
44ad9944 682 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
374cbac0 683
98348e95
IE		 684 spte = rmap_next(kvm, rmapp, NULL);
685 while (spte) {
374cbac0 686 BUG_ON(!spte);
374cbac0 687 BUG_ON(!(*spte & PT_PRESENT_MASK));
374cbac0 688 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
8dae4445 689 if (is_writable_pte(*spte)) {
d555c333 690 __set_spte(spte, *spte & ~PT_WRITABLE_MASK);
caa5b8a5
ED		 691 write_protected = 1;
692 }
9647c14c 693 spte = rmap_next(kvm, rmapp, spte);
374cbac0 694 }
855149aa 695 if (write_protected) {
35149e21 696 pfn_t pfn;
855149aa
IE		 697
698 spte = rmap_next(kvm, rmapp, NULL);
35149e21
AL		 699 pfn = spte_to_pfn(*spte);
700 kvm_set_pfn_dirty(pfn);
855149aa
IE		 701 }
702
05da4558 703 /* check for huge page mappings */
44ad9944
JR		 704 for (i = PT_DIRECTORY_LEVEL;
705 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
706 rmapp = gfn_to_rmap(kvm, gfn, i);
707 spte = rmap_next(kvm, rmapp, NULL);
708 while (spte) {
709 BUG_ON(!spte);
710 BUG_ON(!(*spte & PT_PRESENT_MASK));
711 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
712 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
8dae4445 713 if (is_writable_pte(*spte)) {
44ad9944
JR		 714 rmap_remove(kvm, spte);
715 --kvm->stat.lpages;
716 __set_spte(spte, shadow_trap_nonpresent_pte);
717 spte = NULL;
718 write_protected = 1;
719 }
720 spte = rmap_next(kvm, rmapp, spte);
05da4558 721 }
05da4558
MT		 722 }
723
b1a36821 724 return write_protected;
374cbac0
AK		 725}
726
8a8365c5
FD		 727static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
728 unsigned long data)
e930bffe
AA		 729{
730 u64 *spte;
731 int need_tlb_flush = 0;
732
733 while ((spte = rmap_next(kvm, rmapp, NULL))) {
734 BUG_ON(!(*spte & PT_PRESENT_MASK));
735 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
736 rmap_remove(kvm, spte);
d555c333 737 __set_spte(spte, shadow_trap_nonpresent_pte);
e930bffe
AA		 738 need_tlb_flush = 1;
739 }
740 return need_tlb_flush;
741}
742
8a8365c5
FD		 743static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
744 unsigned long data)
3da0dd43
IE		 745{
746 int need_flush = 0;
747 u64 *spte, new_spte;
748 pte_t *ptep = (pte_t *)data;
749 pfn_t new_pfn;
750
751 WARN_ON(pte_huge(*ptep));
752 new_pfn = pte_pfn(*ptep);
753 spte = rmap_next(kvm, rmapp, NULL);
754 while (spte) {
755 BUG_ON(!is_shadow_present_pte(*spte));
756 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
757 need_flush = 1;
758 if (pte_write(*ptep)) {
759 rmap_remove(kvm, spte);
760 __set_spte(spte, shadow_trap_nonpresent_pte);
761 spte = rmap_next(kvm, rmapp, NULL);
762 } else {
763 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
764 new_spte |= (u64)new_pfn << PAGE_SHIFT;
765
766 new_spte &= ~PT_WRITABLE_MASK;
767 new_spte &= ~SPTE_HOST_WRITEABLE;
8dae4445 768 if (is_writable_pte(*spte))
3da0dd43
IE		 769 kvm_set_pfn_dirty(spte_to_pfn(*spte));
770 __set_spte(spte, new_spte);
771 spte = rmap_next(kvm, rmapp, spte);
772 }
773 }
774 if (need_flush)
775 kvm_flush_remote_tlbs(kvm);
776
777 return 0;
778}
779
8a8365c5
FD		 780static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
781 unsigned long data,
3da0dd43 782 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
8a8365c5 783 unsigned long data))
e930bffe 784{
852e3c19 785 int i, j;
90bb6fc5 786 int ret;
e930bffe 787 int retval = 0;
bc6678a3
MT		 788 struct kvm_memslots *slots;
789
790 slots = rcu_dereference(kvm->memslots);
e930bffe 791
46a26bf5
MT		 792 for (i = 0; i < slots->nmemslots; i++) {
793 struct kvm_memory_slot *memslot = &slots->memslots[i];
e930bffe
AA		 794 unsigned long start = memslot->userspace_addr;
795 unsigned long end;
796
e930bffe
AA		 797 end = start + (memslot->npages << PAGE_SHIFT);
798 if (hva >= start && hva < end) {
799 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
852e3c19 800
90bb6fc5 801 ret = handler(kvm, &memslot->rmap[gfn_offset], data);
852e3c19
JR		 802
803 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
804 int idx = gfn_offset;
805 idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j);
90bb6fc5 806 ret |= handler(kvm,
3da0dd43
IE		 807 &memslot->lpage_info[j][idx].rmap_pde,
808 data);
852e3c19 809 }
90bb6fc5
AK		 810 trace_kvm_age_page(hva, memslot, ret);
811 retval |= ret;
e930bffe
AA		 812 }
813 }
814
815 return retval;
816}
817
818int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
819{
3da0dd43
IE		 820 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
821}
822
823void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
824{
8a8365c5 825 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
e930bffe
AA		 826}
827
8a8365c5
FD		 828static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
829 unsigned long data)
e930bffe
AA		 830{
831 u64 *spte;
832 int young = 0;
833
6316e1c8
RR		 834 /*
835 * Emulate the accessed bit for EPT, by checking if this page has
836 * an EPT mapping, and clearing it if it does. On the next access,
837 * a new EPT mapping will be established.
838 * This has some overhead, but not as much as the cost of swapping
839 * out actively used pages or breaking up actively used hugepages.
840 */
534e38b4 841 if (!shadow_accessed_mask)
6316e1c8 842 return kvm_unmap_rmapp(kvm, rmapp, data);
534e38b4 843
e930bffe
AA		 844 spte = rmap_next(kvm, rmapp, NULL);
845 while (spte) {
846 int _young;
847 u64 _spte = *spte;
848 BUG_ON(!(_spte & PT_PRESENT_MASK));
849 _young = _spte & PT_ACCESSED_MASK;
850 if (_young) {
851 young = 1;
852 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
853 }
854 spte = rmap_next(kvm, rmapp, spte);
855 }
856 return young;
857}
858
53a27b39
MT		 859#define RMAP_RECYCLE_THRESHOLD 1000
860
852e3c19 861static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
53a27b39
MT		 862{
863 unsigned long *rmapp;
852e3c19
JR		 864 struct kvm_mmu_page *sp;
865
866 sp = page_header(__pa(spte));
53a27b39
MT		 867
868 gfn = unalias_gfn(vcpu->kvm, gfn);
852e3c19 869 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
53a27b39 870
3da0dd43 871 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
53a27b39
MT		 872 kvm_flush_remote_tlbs(vcpu->kvm);
873}
874
e930bffe
AA		 875int kvm_age_hva(struct kvm *kvm, unsigned long hva)
876{
3da0dd43 877 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
e930bffe
AA		 878}
879
d6c69ee9 880#ifdef MMU_DEBUG
47ad8e68 881static int is_empty_shadow_page(u64 *spt)
6aa8b732 882{
139bdb2d
AK		 883 u64 *pos;
884 u64 *end;
885
47ad8e68 886 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
3c915510 887 if (is_shadow_present_pte(*pos)) {
b8688d51 888 printk(KERN_ERR "%s: %p %llx\n", __func__,
139bdb2d 889 pos, *pos);
6aa8b732 890 return 0;
139bdb2d 891 }
6aa8b732
AK		 892 return 1;
893}
d6c69ee9 894#endif
6aa8b732 895
4db35314 896static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
260746c0 897{
4db35314
AK		 898 ASSERT(is_empty_shadow_page(sp->spt));
899 list_del(&sp->link);
900 __free_page(virt_to_page(sp->spt));
901 __free_page(virt_to_page(sp->gfns));
902 kfree(sp);
f05e70ac 903 ++kvm->arch.n_free_mmu_pages;
260746c0
AK		 904}
905
cea0f0e7
AK		 906static unsigned kvm_page_table_hashfn(gfn_t gfn)
907{
1ae0a13d 908 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
cea0f0e7
AK		 909}
910
25c0de2c
AK		 911static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
912 u64 *parent_pte)
6aa8b732 913{
4db35314 914 struct kvm_mmu_page *sp;
6aa8b732 915
ad312c7c
ZX		 916 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
917 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
918 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
4db35314 919 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
f05e70ac 920 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
291f26bc 921 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
4db35314
AK		 922 sp->multimapped = 0;
923 sp->parent_pte = parent_pte;
f05e70ac 924 --vcpu->kvm->arch.n_free_mmu_pages;
4db35314 925 return sp;
6aa8b732
AK		 926}
927
714b93da 928static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
4db35314 929 struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7
AK		 930{
931 struct kvm_pte_chain *pte_chain;
932 struct hlist_node *node;
933 int i;
934
935 if (!parent_pte)
936 return;
4db35314
AK		 937 if (!sp->multimapped) {
938 u64 *old = sp->parent_pte;
cea0f0e7
AK		 939
940 if (!old) {
4db35314 941 sp->parent_pte = parent_pte;
cea0f0e7
AK		 942 return;
943 }
4db35314 944 sp->multimapped = 1;
714b93da 945 pte_chain = mmu_alloc_pte_chain(vcpu);
4db35314
AK		 946 INIT_HLIST_HEAD(&sp->parent_ptes);
947 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 948 pte_chain->parent_ptes[0] = old;
949 }
4db35314 950 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
cea0f0e7
AK		 951 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
952 continue;
953 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
954 if (!pte_chain->parent_ptes[i]) {
955 pte_chain->parent_ptes[i] = parent_pte;
956 return;
957 }
958 }
714b93da 959 pte_chain = mmu_alloc_pte_chain(vcpu);
cea0f0e7 960 BUG_ON(!pte_chain);
4db35314 961 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 962 pte_chain->parent_ptes[0] = parent_pte;
963}
964
4db35314 965static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
cea0f0e7
AK		 966 u64 *parent_pte)
967{
968 struct kvm_pte_chain *pte_chain;
969 struct hlist_node *node;
970 int i;
971
4db35314
AK		 972 if (!sp->multimapped) {
973 BUG_ON(sp->parent_pte != parent_pte);
974 sp->parent_pte = NULL;
cea0f0e7
AK		 975 return;
976 }
4db35314 977 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
cea0f0e7
AK		 978 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
979 if (!pte_chain->parent_ptes[i])
980 break;
981 if (pte_chain->parent_ptes[i] != parent_pte)
982 continue;
697fe2e2
AK		 983 while (i + 1 < NR_PTE_CHAIN_ENTRIES
984 && pte_chain->parent_ptes[i + 1]) {
cea0f0e7
AK		 985 pte_chain->parent_ptes[i]
986 = pte_chain->parent_ptes[i + 1];
987 ++i;
988 }
989 pte_chain->parent_ptes[i] = NULL;
697fe2e2
AK		 990 if (i == 0) {
991 hlist_del(&pte_chain->link);
90cb0529 992 mmu_free_pte_chain(pte_chain);
4db35314
AK		 993 if (hlist_empty(&sp->parent_ptes)) {
994 sp->multimapped = 0;
995 sp->parent_pte = NULL;
697fe2e2
AK		 996 }
997 }
cea0f0e7
AK		 998 return;
999 }
1000 BUG();
1001}
1002
ad8cfbe3
MT		 1003
1004static void mmu_parent_walk(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1005 mmu_parent_walk_fn fn)
1006{
1007 struct kvm_pte_chain *pte_chain;
1008 struct hlist_node *node;
1009 struct kvm_mmu_page *parent_sp;
1010 int i;
1011
1012 if (!sp->multimapped && sp->parent_pte) {
1013 parent_sp = page_header(__pa(sp->parent_pte));
1014 fn(vcpu, parent_sp);
1015 mmu_parent_walk(vcpu, parent_sp, fn);
1016 return;
1017 }
1018 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1019 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1020 if (!pte_chain->parent_ptes[i])
1021 break;
1022 parent_sp = page_header(__pa(pte_chain->parent_ptes[i]));
1023 fn(vcpu, parent_sp);
1024 mmu_parent_walk(vcpu, parent_sp, fn);
1025 }
1026}
1027
0074ff63
MT		 1028static void kvm_mmu_update_unsync_bitmap(u64 *spte)
1029{
1030 unsigned int index;
1031 struct kvm_mmu_page *sp = page_header(__pa(spte));
1032
1033 index = spte - sp->spt;
60c8aec6
MT		 1034 if (!__test_and_set_bit(index, sp->unsync_child_bitmap))
1035 sp->unsync_children++;
1036 WARN_ON(!sp->unsync_children);
0074ff63
MT		 1037}
1038
1039static void kvm_mmu_update_parents_unsync(struct kvm_mmu_page *sp)
1040{
1041 struct kvm_pte_chain *pte_chain;
1042 struct hlist_node *node;
1043 int i;
1044
1045 if (!sp->parent_pte)
1046 return;
1047
1048 if (!sp->multimapped) {
1049 kvm_mmu_update_unsync_bitmap(sp->parent_pte);
1050 return;
1051 }
1052
1053 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1054 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1055 if (!pte_chain->parent_ptes[i])
1056 break;
1057 kvm_mmu_update_unsync_bitmap(pte_chain->parent_ptes[i]);
1058 }
1059}
1060
1061static int unsync_walk_fn(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1062{
0074ff63
MT		 1063 kvm_mmu_update_parents_unsync(sp);
1064 return 1;
1065}
1066
1067static void kvm_mmu_mark_parents_unsync(struct kvm_vcpu *vcpu,
1068 struct kvm_mmu_page *sp)
1069{
1070 mmu_parent_walk(vcpu, sp, unsync_walk_fn);
1071 kvm_mmu_update_parents_unsync(sp);
1072}
1073
d761a501
AK		 1074static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1075 struct kvm_mmu_page *sp)
1076{
1077 int i;
1078
1079 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1080 sp->spt[i] = shadow_trap_nonpresent_pte;
1081}
1082
e8bc217a
MT		 1083static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1084 struct kvm_mmu_page *sp)
1085{
1086 return 1;
1087}
1088
a7052897
MT		 1089static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1090{
1091}
1092
60c8aec6
MT		 1093#define KVM_PAGE_ARRAY_NR 16
1094
1095struct kvm_mmu_pages {
1096 struct mmu_page_and_offset {
1097 struct kvm_mmu_page *sp;
1098 unsigned int idx;
1099 } page[KVM_PAGE_ARRAY_NR];
1100 unsigned int nr;
1101};
1102
0074ff63
MT		 1103#define for_each_unsync_children(bitmap, idx) \
1104 for (idx = find_first_bit(bitmap, 512); \
1105 idx < 512; \
1106 idx = find_next_bit(bitmap, 512, idx+1))
1107
cded19f3
HE		 1108static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1109 int idx)
4731d4c7 1110{
60c8aec6 1111 int i;
4731d4c7 1112
60c8aec6
MT		 1113 if (sp->unsync)
1114 for (i=0; i < pvec->nr; i++)
1115 if (pvec->page[i].sp == sp)
1116 return 0;
1117
1118 pvec->page[pvec->nr].sp = sp;
1119 pvec->page[pvec->nr].idx = idx;
1120 pvec->nr++;
1121 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1122}
1123
1124static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1125 struct kvm_mmu_pages *pvec)
1126{
1127 int i, ret, nr_unsync_leaf = 0;
4731d4c7 1128
0074ff63 1129 for_each_unsync_children(sp->unsync_child_bitmap, i) {
4731d4c7
MT		 1130 u64 ent = sp->spt[i];
1131
87917239 1132 if (is_shadow_present_pte(ent) && !is_large_pte(ent)) {
4731d4c7
MT		 1133 struct kvm_mmu_page *child;
1134 child = page_header(ent & PT64_BASE_ADDR_MASK);
1135
1136 if (child->unsync_children) {
60c8aec6
MT		 1137 if (mmu_pages_add(pvec, child, i))
1138 return -ENOSPC;
1139
1140 ret = __mmu_unsync_walk(child, pvec);
1141 if (!ret)
1142 __clear_bit(i, sp->unsync_child_bitmap);
1143 else if (ret > 0)
1144 nr_unsync_leaf += ret;
1145 else
4731d4c7
MT		 1146 return ret;
1147 }
1148
1149 if (child->unsync) {
60c8aec6
MT		 1150 nr_unsync_leaf++;
1151 if (mmu_pages_add(pvec, child, i))
1152 return -ENOSPC;
4731d4c7
MT		 1153 }
1154 }
1155 }
1156
0074ff63 1157 if (find_first_bit(sp->unsync_child_bitmap, 512) == 512)
4731d4c7
MT		 1158 sp->unsync_children = 0;
1159
60c8aec6
MT		 1160 return nr_unsync_leaf;
1161}
1162
1163static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1164 struct kvm_mmu_pages *pvec)
1165{
1166 if (!sp->unsync_children)
1167 return 0;
1168
1169 mmu_pages_add(pvec, sp, 0);
1170 return __mmu_unsync_walk(sp, pvec);
4731d4c7
MT		 1171}
1172
4db35314 1173static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn)
cea0f0e7
AK		 1174{
1175 unsigned index;
1176 struct hlist_head *bucket;
4db35314 1177 struct kvm_mmu_page *sp;
cea0f0e7
AK		 1178 struct hlist_node *node;
1179
b8688d51 1180 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
1ae0a13d 1181 index = kvm_page_table_hashfn(gfn);
f05e70ac 1182 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1183 hlist_for_each_entry(sp, node, bucket, hash_link)
f6e2c02b 1184 if (sp->gfn == gfn && !sp->role.direct
2e53d63a 1185 && !sp->role.invalid) {
cea0f0e7 1186 pgprintk("%s: found role %x\n",
b8688d51 1187 __func__, sp->role.word);
4db35314 1188 return sp;
cea0f0e7
AK		 1189 }
1190 return NULL;
1191}
1192
4731d4c7
MT		 1193static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1194{
1195 WARN_ON(!sp->unsync);
1196 sp->unsync = 0;
1197 --kvm->stat.mmu_unsync;
1198}
1199
1200static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp);
1201
1202static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1203{
5b7e0102 1204 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
4731d4c7
MT		 1205 kvm_mmu_zap_page(vcpu->kvm, sp);
1206 return 1;
1207 }
1208
f691fe1d 1209 trace_kvm_mmu_sync_page(sp);
b1a36821
MT		 1210 if (rmap_write_protect(vcpu->kvm, sp->gfn))
1211 kvm_flush_remote_tlbs(vcpu->kvm);
0c0f40bd 1212 kvm_unlink_unsync_page(vcpu->kvm, sp);
4731d4c7
MT		 1213 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1214 kvm_mmu_zap_page(vcpu->kvm, sp);
1215 return 1;
1216 }
1217
1218 kvm_mmu_flush_tlb(vcpu);
4731d4c7
MT		 1219 return 0;
1220}
1221
60c8aec6
MT		 1222struct mmu_page_path {
1223 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1224 unsigned int idx[PT64_ROOT_LEVEL-1];
4731d4c7
MT		 1225};
1226
60c8aec6
MT		 1227#define for_each_sp(pvec, sp, parents, i) \
1228 for (i = mmu_pages_next(&pvec, &parents, -1), \
1229 sp = pvec.page[i].sp; \
1230 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1231 i = mmu_pages_next(&pvec, &parents, i))
1232
cded19f3
HE		 1233static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1234 struct mmu_page_path *parents,
1235 int i)
60c8aec6
MT		 1236{
1237 int n;
1238
1239 for (n = i+1; n < pvec->nr; n++) {
1240 struct kvm_mmu_page *sp = pvec->page[n].sp;
1241
1242 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1243 parents->idx[0] = pvec->page[n].idx;
1244 return n;
1245 }
1246
1247 parents->parent[sp->role.level-2] = sp;
1248 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1249 }
1250
1251 return n;
1252}
1253
cded19f3 1254static void mmu_pages_clear_parents(struct mmu_page_path *parents)
4731d4c7 1255{
60c8aec6
MT		 1256 struct kvm_mmu_page *sp;
1257 unsigned int level = 0;
1258
1259 do {
1260 unsigned int idx = parents->idx[level];
4731d4c7 1261
60c8aec6
MT		 1262 sp = parents->parent[level];
1263 if (!sp)
1264 return;
1265
1266 --sp->unsync_children;
1267 WARN_ON((int)sp->unsync_children < 0);
1268 __clear_bit(idx, sp->unsync_child_bitmap);
1269 level++;
1270 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
4731d4c7
MT		 1271}
1272
60c8aec6
MT		 1273static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1274 struct mmu_page_path *parents,
1275 struct kvm_mmu_pages *pvec)
4731d4c7 1276{
60c8aec6
MT		 1277 parents->parent[parent->role.level-1] = NULL;
1278 pvec->nr = 0;
1279}
4731d4c7 1280
60c8aec6
MT		 1281static void mmu_sync_children(struct kvm_vcpu *vcpu,
1282 struct kvm_mmu_page *parent)
1283{
1284 int i;
1285 struct kvm_mmu_page *sp;
1286 struct mmu_page_path parents;
1287 struct kvm_mmu_pages pages;
1288
1289 kvm_mmu_pages_init(parent, &parents, &pages);
1290 while (mmu_unsync_walk(parent, &pages)) {
b1a36821
MT		 1291 int protected = 0;
1292
1293 for_each_sp(pages, sp, parents, i)
1294 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1295
1296 if (protected)
1297 kvm_flush_remote_tlbs(vcpu->kvm);
1298
60c8aec6
MT		 1299 for_each_sp(pages, sp, parents, i) {
1300 kvm_sync_page(vcpu, sp);
1301 mmu_pages_clear_parents(&parents);
1302 }
4731d4c7 1303 cond_resched_lock(&vcpu->kvm->mmu_lock);
60c8aec6
MT		 1304 kvm_mmu_pages_init(parent, &parents, &pages);
1305 }
4731d4c7
MT		 1306}
1307
cea0f0e7
AK		 1308static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1309 gfn_t gfn,
1310 gva_t gaddr,
1311 unsigned level,
f6e2c02b 1312 int direct,
41074d07 1313 unsigned access,
f7d9c7b7 1314 u64 *parent_pte)
cea0f0e7
AK		 1315{
1316 union kvm_mmu_page_role role;
1317 unsigned index;
1318 unsigned quadrant;
1319 struct hlist_head *bucket;
4db35314 1320 struct kvm_mmu_page *sp;
4731d4c7 1321 struct hlist_node *node, *tmp;
cea0f0e7 1322
a770f6f2 1323 role = vcpu->arch.mmu.base_role;
cea0f0e7 1324 role.level = level;
f6e2c02b 1325 role.direct = direct;
84b0c8c6 1326 if (role.direct)
5b7e0102 1327 role.cr4_pae = 0;
41074d07 1328 role.access = access;
ad312c7c 1329 if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
cea0f0e7
AK		 1330 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1331 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1332 role.quadrant = quadrant;
1333 }
1ae0a13d 1334 index = kvm_page_table_hashfn(gfn);
f05e70ac 1335 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4731d4c7
MT		 1336 hlist_for_each_entry_safe(sp, node, tmp, bucket, hash_link)
1337 if (sp->gfn == gfn) {
1338 if (sp->unsync)
1339 if (kvm_sync_page(vcpu, sp))
1340 continue;
1341
1342 if (sp->role.word != role.word)
1343 continue;
1344
4db35314 1345 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
0074ff63
MT		 1346 if (sp->unsync_children) {
1347 set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests);
1348 kvm_mmu_mark_parents_unsync(vcpu, sp);
1349 }
f691fe1d 1350 trace_kvm_mmu_get_page(sp, false);
4db35314 1351 return sp;
cea0f0e7 1352 }
dfc5aa00 1353 ++vcpu->kvm->stat.mmu_cache_miss;
4db35314
AK		 1354 sp = kvm_mmu_alloc_page(vcpu, parent_pte);
1355 if (!sp)
1356 return sp;
4db35314
AK		 1357 sp->gfn = gfn;
1358 sp->role = role;
1359 hlist_add_head(&sp->hash_link, bucket);
f6e2c02b 1360 if (!direct) {
b1a36821
MT		 1361 if (rmap_write_protect(vcpu->kvm, gfn))
1362 kvm_flush_remote_tlbs(vcpu->kvm);
4731d4c7
MT		 1363 account_shadowed(vcpu->kvm, gfn);
1364 }
131d8279
AK		 1365 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1366 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1367 else
1368 nonpaging_prefetch_page(vcpu, sp);
f691fe1d 1369 trace_kvm_mmu_get_page(sp, true);
4db35314 1370 return sp;
cea0f0e7
AK		 1371}
1372
2d11123a
AK		 1373static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1374 struct kvm_vcpu *vcpu, u64 addr)
1375{
1376 iterator->addr = addr;
1377 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1378 iterator->level = vcpu->arch.mmu.shadow_root_level;
1379 if (iterator->level == PT32E_ROOT_LEVEL) {
1380 iterator->shadow_addr
1381 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1382 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1383 --iterator->level;
1384 if (!iterator->shadow_addr)
1385 iterator->level = 0;
1386 }
1387}
1388
1389static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1390{
1391 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1392 return false;
4d88954d
MT		 1393
1394 if (iterator->level == PT_PAGE_TABLE_LEVEL)
1395 if (is_large_pte(*iterator->sptep))
1396 return false;
1397
2d11123a
AK		 1398 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1399 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1400 return true;
1401}
1402
1403static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1404{
1405 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1406 --iterator->level;
1407}
1408
90cb0529 1409static void kvm_mmu_page_unlink_children(struct kvm *kvm,
4db35314 1410 struct kvm_mmu_page *sp)
a436036b 1411{
697fe2e2
AK		 1412 unsigned i;
1413 u64 *pt;
1414 u64 ent;
1415
4db35314 1416 pt = sp->spt;
697fe2e2 1417
697fe2e2
AK		 1418 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1419 ent = pt[i];
1420
05da4558 1421 if (is_shadow_present_pte(ent)) {
776e6633 1422 if (!is_last_spte(ent, sp->role.level)) {
05da4558
MT		 1423 ent &= PT64_BASE_ADDR_MASK;
1424 mmu_page_remove_parent_pte(page_header(ent),
1425 &pt[i]);
1426 } else {
776e6633
MT		 1427 if (is_large_pte(ent))
1428 --kvm->stat.lpages;
05da4558
MT		 1429 rmap_remove(kvm, &pt[i]);
1430 }
1431 }
c7addb90 1432 pt[i] = shadow_trap_nonpresent_pte;
697fe2e2 1433 }
a436036b
AK		 1434}
1435
4db35314 1436static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 1437{
4db35314 1438 mmu_page_remove_parent_pte(sp, parent_pte);
a436036b
AK		 1439}
1440
12b7d28f
AK		 1441static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1442{
1443 int i;
988a2cae 1444 struct kvm_vcpu *vcpu;
12b7d28f 1445
988a2cae
GN		 1446 kvm_for_each_vcpu(i, vcpu, kvm)
1447 vcpu->arch.last_pte_updated = NULL;
12b7d28f
AK		 1448}
1449
31aa2b44 1450static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
a436036b
AK		 1451{
1452 u64 *parent_pte;
1453
4db35314
AK		 1454 while (sp->multimapped || sp->parent_pte) {
1455 if (!sp->multimapped)
1456 parent_pte = sp->parent_pte;
a436036b
AK		 1457 else {
1458 struct kvm_pte_chain *chain;
1459
4db35314 1460 chain = container_of(sp->parent_ptes.first,
a436036b
AK		 1461 struct kvm_pte_chain, link);
1462 parent_pte = chain->parent_ptes[0];
1463 }
697fe2e2 1464 BUG_ON(!parent_pte);
4db35314 1465 kvm_mmu_put_page(sp, parent_pte);
d555c333 1466 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
a436036b 1467 }
31aa2b44
AK		 1468}
1469
60c8aec6
MT		 1470static int mmu_zap_unsync_children(struct kvm *kvm,
1471 struct kvm_mmu_page *parent)
4731d4c7 1472{
60c8aec6
MT		 1473 int i, zapped = 0;
1474 struct mmu_page_path parents;
1475 struct kvm_mmu_pages pages;
4731d4c7 1476
60c8aec6 1477 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
4731d4c7 1478 return 0;
60c8aec6
MT		 1479
1480 kvm_mmu_pages_init(parent, &parents, &pages);
1481 while (mmu_unsync_walk(parent, &pages)) {
1482 struct kvm_mmu_page *sp;
1483
1484 for_each_sp(pages, sp, parents, i) {
1485 kvm_mmu_zap_page(kvm, sp);
1486 mmu_pages_clear_parents(&parents);
77662e00 1487 zapped++;
60c8aec6 1488 }
60c8aec6
MT		 1489 kvm_mmu_pages_init(parent, &parents, &pages);
1490 }
1491
1492 return zapped;
4731d4c7
MT		 1493}
1494
07385413 1495static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp)
31aa2b44 1496{
4731d4c7 1497 int ret;
f691fe1d
AK		 1498
1499 trace_kvm_mmu_zap_page(sp);
31aa2b44 1500 ++kvm->stat.mmu_shadow_zapped;
4731d4c7 1501 ret = mmu_zap_unsync_children(kvm, sp);
4db35314 1502 kvm_mmu_page_unlink_children(kvm, sp);
31aa2b44 1503 kvm_mmu_unlink_parents(kvm, sp);
5b5c6a5a 1504 kvm_flush_remote_tlbs(kvm);
f6e2c02b 1505 if (!sp->role.invalid && !sp->role.direct)
5b5c6a5a 1506 unaccount_shadowed(kvm, sp->gfn);
4731d4c7
MT		 1507 if (sp->unsync)
1508 kvm_unlink_unsync_page(kvm, sp);
4db35314
AK		 1509 if (!sp->root_count) {
1510 hlist_del(&sp->hash_link);
1511 kvm_mmu_free_page(kvm, sp);
2e53d63a 1512 } else {
2e53d63a 1513 sp->role.invalid = 1;
5b5c6a5a 1514 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2e53d63a
MT		 1515 kvm_reload_remote_mmus(kvm);
1516 }
12b7d28f 1517 kvm_mmu_reset_last_pte_updated(kvm);
4731d4c7 1518 return ret;
a436036b
AK		 1519}
1520
82ce2c96
IE		 1521/*
1522 * Changing the number of mmu pages allocated to the vm
1523 * Note: if kvm_nr_mmu_pages is too small, you will get dead lock
1524 */
1525void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
1526{
025dbbf3
MT		 1527 int used_pages;
1528
1529 used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages;
1530 used_pages = max(0, used_pages);
1531
82ce2c96
IE		 1532 /*
1533 * If we set the number of mmu pages to be smaller be than the
1534 * number of actived pages , we must to free some mmu pages before we
1535 * change the value
1536 */
1537
025dbbf3 1538 if (used_pages > kvm_nr_mmu_pages) {
77662e00
XG		 1539 while (used_pages > kvm_nr_mmu_pages &&
1540 !list_empty(&kvm->arch.active_mmu_pages)) {
82ce2c96
IE		 1541 struct kvm_mmu_page *page;
1542
f05e70ac 1543 page = container_of(kvm->arch.active_mmu_pages.prev,
82ce2c96 1544 struct kvm_mmu_page, link);
77662e00 1545 used_pages -= kvm_mmu_zap_page(kvm, page);
025dbbf3 1546 used_pages--;
82ce2c96 1547 }
77662e00 1548 kvm_nr_mmu_pages = used_pages;
f05e70ac 1549 kvm->arch.n_free_mmu_pages = 0;
82ce2c96
IE		 1550 }
1551 else
f05e70ac
ZX		 1552 kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages
1553 - kvm->arch.n_alloc_mmu_pages;
82ce2c96 1554
f05e70ac 1555 kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages;
82ce2c96
IE		 1556}
1557
f67a46f4 1558static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
a436036b
AK		 1559{
1560 unsigned index;
1561 struct hlist_head *bucket;
4db35314 1562 struct kvm_mmu_page *sp;
a436036b
AK		 1563 struct hlist_node *node, *n;
1564 int r;
1565
b8688d51 1566 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
a436036b 1567 r = 0;
1ae0a13d 1568 index = kvm_page_table_hashfn(gfn);
f05e70ac 1569 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1570 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link)
f6e2c02b 1571 if (sp->gfn == gfn && !sp->role.direct) {
b8688d51 1572 pgprintk("%s: gfn %lx role %x\n", __func__, gfn,
4db35314 1573 sp->role.word);
a436036b 1574 r = 1;
07385413
MT		 1575 if (kvm_mmu_zap_page(kvm, sp))
1576 n = bucket->first;
a436036b
AK		 1577 }
1578 return r;
cea0f0e7
AK		 1579}
1580
f67a46f4 1581static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
97a0a01e 1582{
4677a3b6
AK		 1583 unsigned index;
1584 struct hlist_head *bucket;
4db35314 1585 struct kvm_mmu_page *sp;
4677a3b6 1586 struct hlist_node *node, *nn;
97a0a01e 1587
4677a3b6
AK		 1588 index = kvm_page_table_hashfn(gfn);
1589 bucket = &kvm->arch.mmu_page_hash[index];
1590 hlist_for_each_entry_safe(sp, node, nn, bucket, hash_link) {
f6e2c02b 1591 if (sp->gfn == gfn && !sp->role.direct
4677a3b6
AK		 1592 && !sp->role.invalid) {
1593 pgprintk("%s: zap %lx %x\n",
1594 __func__, gfn, sp->role.word);
77662e00
XG		 1595 if (kvm_mmu_zap_page(kvm, sp))
1596 nn = bucket->first;
4677a3b6 1597 }
97a0a01e
AK		 1598 }
1599}
1600
38c335f1 1601static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
6aa8b732 1602{
bc6678a3 1603 int slot = memslot_id(kvm, gfn);
4db35314 1604 struct kvm_mmu_page *sp = page_header(__pa(pte));
6aa8b732 1605
291f26bc 1606 __set_bit(slot, sp->slot_bitmap);
6aa8b732
AK		 1607}
1608
6844dec6
MT		 1609static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1610{
1611 int i;
1612 u64 *pt = sp->spt;
1613
1614 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1615 return;
1616
1617 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1618 if (pt[i] == shadow_notrap_nonpresent_pte)
d555c333 1619 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
6844dec6
MT		 1620 }
1621}
1622
039576c0
AK		 1623struct page *gva_to_page(struct kvm_vcpu *vcpu, gva_t gva)
1624{
72dc67a6
IE		 1625 struct page *page;
1626
1871c602 1627 gpa_t gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
039576c0
AK		 1628
1629 if (gpa == UNMAPPED_GVA)
1630 return NULL;
72dc67a6 1631
72dc67a6 1632 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6
IE		 1633
1634 return page;
039576c0
AK		 1635}
1636
74be52e3
SY		 1637/*
1638 * The function is based on mtrr_type_lookup() in
1639 * arch/x86/kernel/cpu/mtrr/generic.c
1640 */
1641static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1642 u64 start, u64 end)
1643{
1644 int i;
1645 u64 base, mask;
1646 u8 prev_match, curr_match;
1647 int num_var_ranges = KVM_NR_VAR_MTRR;
1648
1649 if (!mtrr_state->enabled)
1650 return 0xFF;
1651
1652 /* Make end inclusive end, instead of exclusive */
1653 end--;
1654
1655 /* Look in fixed ranges. Just return the type as per start */
1656 if (mtrr_state->have_fixed && (start < 0x100000)) {
1657 int idx;
1658
1659 if (start < 0x80000) {
1660 idx = 0;
1661 idx += (start >> 16);
1662 return mtrr_state->fixed_ranges[idx];
1663 } else if (start < 0xC0000) {
1664 idx = 1 * 8;
1665 idx += ((start - 0x80000) >> 14);
1666 return mtrr_state->fixed_ranges[idx];
1667 } else if (start < 0x1000000) {
1668 idx = 3 * 8;
1669 idx += ((start - 0xC0000) >> 12);
1670 return mtrr_state->fixed_ranges[idx];
1671 }
1672 }
1673
1674 /*
1675 * Look in variable ranges
1676 * Look of multiple ranges matching this address and pick type
1677 * as per MTRR precedence
1678 */
1679 if (!(mtrr_state->enabled & 2))
1680 return mtrr_state->def_type;
1681
1682 prev_match = 0xFF;
1683 for (i = 0; i < num_var_ranges; ++i) {
1684 unsigned short start_state, end_state;
1685
1686 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1687 continue;
1688
1689 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1690 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1691 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1692 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1693
1694 start_state = ((start & mask) == (base & mask));
1695 end_state = ((end & mask) == (base & mask));
1696 if (start_state != end_state)
1697 return 0xFE;
1698
1699 if ((start & mask) != (base & mask))
1700 continue;
1701
1702 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1703 if (prev_match == 0xFF) {
1704 prev_match = curr_match;
1705 continue;
1706 }
1707
1708 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1709 curr_match == MTRR_TYPE_UNCACHABLE)
1710 return MTRR_TYPE_UNCACHABLE;
1711
1712 if ((prev_match == MTRR_TYPE_WRBACK &&
1713 curr_match == MTRR_TYPE_WRTHROUGH) ||
1714 (prev_match == MTRR_TYPE_WRTHROUGH &&
1715 curr_match == MTRR_TYPE_WRBACK)) {
1716 prev_match = MTRR_TYPE_WRTHROUGH;
1717 curr_match = MTRR_TYPE_WRTHROUGH;
1718 }
1719
1720 if (prev_match != curr_match)
1721 return MTRR_TYPE_UNCACHABLE;
1722 }
1723
1724 if (prev_match != 0xFF)
1725 return prev_match;
1726
1727 return mtrr_state->def_type;
1728}
1729
4b12f0de 1730u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
74be52e3
SY		 1731{
1732 u8 mtrr;
1733
1734 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1735 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1736 if (mtrr == 0xfe || mtrr == 0xff)
1737 mtrr = MTRR_TYPE_WRBACK;
1738 return mtrr;
1739}
4b12f0de 1740EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
74be52e3 1741
4731d4c7
MT		 1742static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1743{
1744 unsigned index;
1745 struct hlist_head *bucket;
1746 struct kvm_mmu_page *s;
1747 struct hlist_node *node, *n;
1748
f691fe1d 1749 trace_kvm_mmu_unsync_page(sp);
4731d4c7
MT		 1750 index = kvm_page_table_hashfn(sp->gfn);
1751 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
1752 /* don't unsync if pagetable is shadowed with multiple roles */
1753 hlist_for_each_entry_safe(s, node, n, bucket, hash_link) {
f6e2c02b 1754 if (s->gfn != sp->gfn || s->role.direct)
4731d4c7
MT		 1755 continue;
1756 if (s->role.word != sp->role.word)
1757 return 1;
1758 }
4731d4c7
MT		 1759 ++vcpu->kvm->stat.mmu_unsync;
1760 sp->unsync = 1;
6cffe8ca 1761
c2d0ee46 1762 kvm_mmu_mark_parents_unsync(vcpu, sp);
6cffe8ca 1763
4731d4c7
MT		 1764 mmu_convert_notrap(sp);
1765 return 0;
1766}
1767
1768static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1769 bool can_unsync)
1770{
1771 struct kvm_mmu_page *shadow;
1772
1773 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
1774 if (shadow) {
1775 if (shadow->role.level != PT_PAGE_TABLE_LEVEL)
1776 return 1;
1777 if (shadow->unsync)
1778 return 0;
582801a9 1779 if (can_unsync && oos_shadow)
4731d4c7
MT		 1780 return kvm_unsync_page(vcpu, shadow);
1781 return 1;
1782 }
1783 return 0;
1784}
1785
d555c333 1786static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd 1787 unsigned pte_access, int user_fault,
852e3c19 1788 int write_fault, int dirty, int level,
c2d0ee46 1789 gfn_t gfn, pfn_t pfn, bool speculative,
1403283a 1790 bool can_unsync, bool reset_host_protection)
1c4f1fd6
AK		 1791{
1792 u64 spte;
1e73f9dd 1793 int ret = 0;
64d4d521 1794
1c4f1fd6
AK		 1795 /*
1796 * We don't set the accessed bit, since we sometimes want to see
1797 * whether the guest actually used the pte (in order to detect
1798 * demand paging).
1799 */
7b52345e 1800 spte = shadow_base_present_pte | shadow_dirty_mask;
947da538 1801 if (!speculative)
3201b5d9 1802 spte |= shadow_accessed_mask;
1c4f1fd6
AK		 1803 if (!dirty)
1804 pte_access &= ~ACC_WRITE_MASK;
7b52345e
SY		 1805 if (pte_access & ACC_EXEC_MASK)
1806 spte |= shadow_x_mask;
1807 else
1808 spte |= shadow_nx_mask;
1c4f1fd6 1809 if (pte_access & ACC_USER_MASK)
7b52345e 1810 spte |= shadow_user_mask;
852e3c19 1811 if (level > PT_PAGE_TABLE_LEVEL)
05da4558 1812 spte |= PT_PAGE_SIZE_MASK;
4b12f0de
SY		 1813 if (tdp_enabled)
1814 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1815 kvm_is_mmio_pfn(pfn));
1c4f1fd6 1816
1403283a
IE		 1817 if (reset_host_protection)
1818 spte |= SPTE_HOST_WRITEABLE;
1819
35149e21 1820 spte |= (u64)pfn << PAGE_SHIFT;
1c4f1fd6
AK		 1821
1822 if ((pte_access & ACC_WRITE_MASK)
1823 || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
1c4f1fd6 1824
852e3c19
JR		 1825 if (level > PT_PAGE_TABLE_LEVEL &&
1826 has_wrprotected_page(vcpu->kvm, gfn, level)) {
38187c83
MT		 1827 ret = 1;
1828 spte = shadow_trap_nonpresent_pte;
1829 goto set_pte;
1830 }
1831
1c4f1fd6 1832 spte |= PT_WRITABLE_MASK;
1c4f1fd6 1833
ecc5589f
MT		 1834 /*
1835 * Optimization: for pte sync, if spte was writable the hash
1836 * lookup is unnecessary (and expensive). Write protection
1837 * is responsibility of mmu_get_page / kvm_sync_page.
1838 * Same reasoning can be applied to dirty page accounting.
1839 */
8dae4445 1840 if (!can_unsync && is_writable_pte(*sptep))
ecc5589f
MT		 1841 goto set_pte;
1842
4731d4c7 1843 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
1c4f1fd6 1844 pgprintk("%s: found shadow page for %lx, marking ro\n",
b8688d51 1845 __func__, gfn);
1e73f9dd 1846 ret = 1;
1c4f1fd6 1847 pte_access &= ~ACC_WRITE_MASK;
8dae4445 1848 if (is_writable_pte(spte))
1c4f1fd6 1849 spte &= ~PT_WRITABLE_MASK;
1c4f1fd6
AK		 1850 }
1851 }
1852
1c4f1fd6
AK		 1853 if (pte_access & ACC_WRITE_MASK)
1854 mark_page_dirty(vcpu->kvm, gfn);
1855
38187c83 1856set_pte:
d555c333 1857 __set_spte(sptep, spte);
1e73f9dd
MT		 1858 return ret;
1859}
1860
d555c333 1861static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd
MT		 1862 unsigned pt_access, unsigned pte_access,
1863 int user_fault, int write_fault, int dirty,
852e3c19 1864 int *ptwrite, int level, gfn_t gfn,
1403283a
IE		 1865 pfn_t pfn, bool speculative,
1866 bool reset_host_protection)
1e73f9dd
MT		 1867{
1868 int was_rmapped = 0;
8dae4445 1869 int was_writable = is_writable_pte(*sptep);
53a27b39 1870 int rmap_count;
1e73f9dd
MT		 1871
1872 pgprintk("%s: spte %llx access %x write_fault %d"
1873 " user_fault %d gfn %lx\n",
d555c333 1874 __func__, *sptep, pt_access,
1e73f9dd
MT		 1875 write_fault, user_fault, gfn);
1876
d555c333 1877 if (is_rmap_spte(*sptep)) {
1e73f9dd
MT		 1878 /*
1879 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
1880 * the parent of the now unreachable PTE.
1881 */
852e3c19
JR		 1882 if (level > PT_PAGE_TABLE_LEVEL &&
1883 !is_large_pte(*sptep)) {
1e73f9dd 1884 struct kvm_mmu_page *child;
d555c333 1885 u64 pte = *sptep;
1e73f9dd
MT		 1886
1887 child = page_header(pte & PT64_BASE_ADDR_MASK);
d555c333
AK		 1888 mmu_page_remove_parent_pte(child, sptep);
1889 } else if (pfn != spte_to_pfn(*sptep)) {
1e73f9dd 1890 pgprintk("hfn old %lx new %lx\n",
d555c333
AK		 1891 spte_to_pfn(*sptep), pfn);
1892 rmap_remove(vcpu->kvm, sptep);
6bed6b9e
JR		 1893 } else
1894 was_rmapped = 1;
1e73f9dd 1895 }
852e3c19 1896
d555c333 1897 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
1403283a
IE		 1898 dirty, level, gfn, pfn, speculative, true,
1899 reset_host_protection)) {
1e73f9dd
MT		 1900 if (write_fault)
1901 *ptwrite = 1;
a378b4e6
MT		 1902 kvm_x86_ops->tlb_flush(vcpu);
1903 }
1e73f9dd 1904
d555c333 1905 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
1e73f9dd 1906 pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n",
d555c333 1907 is_large_pte(*sptep)? "2MB" : "4kB",
a205bc19
JR		 1908 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
1909 *sptep, sptep);
d555c333 1910 if (!was_rmapped && is_large_pte(*sptep))
05da4558
MT		 1911 ++vcpu->kvm->stat.lpages;
1912
d555c333 1913 page_header_update_slot(vcpu->kvm, sptep, gfn);
1c4f1fd6 1914 if (!was_rmapped) {
44ad9944 1915 rmap_count = rmap_add(vcpu, sptep, gfn);
acb66dd0 1916 kvm_release_pfn_clean(pfn);
53a27b39 1917 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
852e3c19 1918 rmap_recycle(vcpu, sptep, gfn);
75e68e60 1919 } else {
8dae4445 1920 if (was_writable)
35149e21 1921 kvm_release_pfn_dirty(pfn);
75e68e60 1922 else
35149e21 1923 kvm_release_pfn_clean(pfn);
1c4f1fd6 1924 }
1b7fcd32 1925 if (speculative) {
d555c333 1926 vcpu->arch.last_pte_updated = sptep;
1b7fcd32
AK		 1927 vcpu->arch.last_pte_gfn = gfn;
1928 }
1c4f1fd6
AK		 1929}
1930
6aa8b732
AK		 1931static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
1932{
1933}
1934
9f652d21 1935static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
852e3c19 1936 int level, gfn_t gfn, pfn_t pfn)
140754bc 1937{
9f652d21 1938 struct kvm_shadow_walk_iterator iterator;
140754bc 1939 struct kvm_mmu_page *sp;
9f652d21 1940 int pt_write = 0;
140754bc 1941 gfn_t pseudo_gfn;
6aa8b732 1942
9f652d21 1943 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
852e3c19 1944 if (iterator.level == level) {
9f652d21
AK		 1945 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
1946 0, write, 1, &pt_write,
1403283a 1947 level, gfn, pfn, false, true);
9f652d21
AK		 1948 ++vcpu->stat.pf_fixed;
1949 break;
6aa8b732
AK		 1950 }
1951
9f652d21
AK		 1952 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
1953 pseudo_gfn = (iterator.addr & PT64_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
1954 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
1955 iterator.level - 1,
1956 1, ACC_ALL, iterator.sptep);
1957 if (!sp) {
1958 pgprintk("nonpaging_map: ENOMEM\n");
1959 kvm_release_pfn_clean(pfn);
1960 return -ENOMEM;
1961 }
140754bc 1962
d555c333
AK		 1963 __set_spte(iterator.sptep,
1964 __pa(sp->spt)
1965 | PT_PRESENT_MASK | PT_WRITABLE_MASK
1966 | shadow_user_mask | shadow_x_mask);
9f652d21
AK		 1967 }
1968 }
1969 return pt_write;
6aa8b732
AK		 1970}
1971
10589a46
MT		 1972static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
1973{
1974 int r;
852e3c19 1975 int level;
35149e21 1976 pfn_t pfn;
e930bffe 1977 unsigned long mmu_seq;
aaee2c94 1978
852e3c19
JR		 1979 level = mapping_level(vcpu, gfn);
1980
1981 /*
1982 * This path builds a PAE pagetable - so we can map 2mb pages at
1983 * maximum. Therefore check if the level is larger than that.
1984 */
1985 if (level > PT_DIRECTORY_LEVEL)
1986 level = PT_DIRECTORY_LEVEL;
1987
1988 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
05da4558 1989
e930bffe 1990 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 1991 smp_rmb();
35149e21 1992 pfn = gfn_to_pfn(vcpu->kvm, gfn);
aaee2c94 1993
d196e343 1994 /* mmio */
35149e21
AL		 1995 if (is_error_pfn(pfn)) {
1996 kvm_release_pfn_clean(pfn);
d196e343
AK		 1997 return 1;
1998 }
1999
aaee2c94 2000 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2001 if (mmu_notifier_retry(vcpu, mmu_seq))
2002 goto out_unlock;
eb787d10 2003 kvm_mmu_free_some_pages(vcpu);
852e3c19 2004 r = __direct_map(vcpu, v, write, level, gfn, pfn);
aaee2c94
MT		 2005 spin_unlock(&vcpu->kvm->mmu_lock);
2006
aaee2c94 2007
10589a46 2008 return r;
e930bffe
AA		 2009
2010out_unlock:
2011 spin_unlock(&vcpu->kvm->mmu_lock);
2012 kvm_release_pfn_clean(pfn);
2013 return 0;
10589a46
MT		 2014}
2015
2016
17ac10ad
AK		 2017static void mmu_free_roots(struct kvm_vcpu *vcpu)
2018{
2019 int i;
4db35314 2020 struct kvm_mmu_page *sp;
17ac10ad 2021
ad312c7c 2022 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
7b53aa56 2023 return;
aaee2c94 2024 spin_lock(&vcpu->kvm->mmu_lock);
ad312c7c
ZX		 2025 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2026 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad 2027
4db35314
AK		 2028 sp = page_header(root);
2029 --sp->root_count;
2e53d63a
MT		 2030 if (!sp->root_count && sp->role.invalid)
2031 kvm_mmu_zap_page(vcpu->kvm, sp);
ad312c7c 2032 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
aaee2c94 2033 spin_unlock(&vcpu->kvm->mmu_lock);
17ac10ad
AK		 2034 return;
2035 }
17ac10ad 2036 for (i = 0; i < 4; ++i) {
ad312c7c 2037 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad 2038
417726a3 2039 if (root) {
417726a3 2040 root &= PT64_BASE_ADDR_MASK;
4db35314
AK		 2041 sp = page_header(root);
2042 --sp->root_count;
2e53d63a
MT		 2043 if (!sp->root_count && sp->role.invalid)
2044 kvm_mmu_zap_page(vcpu->kvm, sp);
417726a3 2045 }
ad312c7c 2046 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2047 }
aaee2c94 2048 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2049 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
17ac10ad
AK		 2050}
2051
8986ecc0
MT		 2052static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2053{
2054 int ret = 0;
2055
2056 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2057 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2058 ret = 1;
2059 }
2060
2061 return ret;
2062}
2063
2064static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
17ac10ad
AK		 2065{
2066 int i;
cea0f0e7 2067 gfn_t root_gfn;
4db35314 2068 struct kvm_mmu_page *sp;
f6e2c02b 2069 int direct = 0;
6de4f3ad 2070 u64 pdptr;
3bb65a22 2071
ad312c7c 2072 root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
17ac10ad 2073
ad312c7c
ZX		 2074 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2075 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad
AK		 2076
2077 ASSERT(!VALID_PAGE(root));
fb72d167 2078 if (tdp_enabled)
f6e2c02b 2079 direct = 1;
8986ecc0
MT		 2080 if (mmu_check_root(vcpu, root_gfn))
2081 return 1;
4db35314 2082 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
f6e2c02b 2083 PT64_ROOT_LEVEL, direct,
fb72d167 2084 ACC_ALL, NULL);
4db35314
AK		 2085 root = __pa(sp->spt);
2086 ++sp->root_count;
ad312c7c 2087 vcpu->arch.mmu.root_hpa = root;
8986ecc0 2088 return 0;
17ac10ad 2089 }
f6e2c02b 2090 direct = !is_paging(vcpu);
fb72d167 2091 if (tdp_enabled)
f6e2c02b 2092 direct = 1;
17ac10ad 2093 for (i = 0; i < 4; ++i) {
ad312c7c 2094 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad
AK		 2095
2096 ASSERT(!VALID_PAGE(root));
ad312c7c 2097 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
6de4f3ad 2098 pdptr = kvm_pdptr_read(vcpu, i);
43a3795a 2099 if (!is_present_gpte(pdptr)) {
ad312c7c 2100 vcpu->arch.mmu.pae_root[i] = 0;
417726a3
AK		 2101 continue;
2102 }
6de4f3ad 2103 root_gfn = pdptr >> PAGE_SHIFT;
ad312c7c 2104 } else if (vcpu->arch.mmu.root_level == 0)
cea0f0e7 2105 root_gfn = 0;
8986ecc0
MT		 2106 if (mmu_check_root(vcpu, root_gfn))
2107 return 1;
4db35314 2108 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
f6e2c02b 2109 PT32_ROOT_LEVEL, direct,
f7d9c7b7 2110 ACC_ALL, NULL);
4db35314
AK		 2111 root = __pa(sp->spt);
2112 ++sp->root_count;
ad312c7c 2113 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
17ac10ad 2114 }
ad312c7c 2115 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
8986ecc0 2116 return 0;
17ac10ad
AK		 2117}
2118
0ba73cda
MT		 2119static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2120{
2121 int i;
2122 struct kvm_mmu_page *sp;
2123
2124 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2125 return;
2126 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2127 hpa_t root = vcpu->arch.mmu.root_hpa;
2128 sp = page_header(root);
2129 mmu_sync_children(vcpu, sp);
2130 return;
2131 }
2132 for (i = 0; i < 4; ++i) {
2133 hpa_t root = vcpu->arch.mmu.pae_root[i];
2134
8986ecc0 2135 if (root && VALID_PAGE(root)) {
0ba73cda
MT		 2136 root &= PT64_BASE_ADDR_MASK;
2137 sp = page_header(root);
2138 mmu_sync_children(vcpu, sp);
2139 }
2140 }
2141}
2142
2143void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2144{
2145 spin_lock(&vcpu->kvm->mmu_lock);
2146 mmu_sync_roots(vcpu);
6cffe8ca 2147 spin_unlock(&vcpu->kvm->mmu_lock);
0ba73cda
MT		 2148}
2149
1871c602
GN		 2150static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2151 u32 access, u32 *error)
6aa8b732 2152{
1871c602
GN		 2153 if (error)
2154 *error = 0;
6aa8b732
AK		 2155 return vaddr;
2156}
2157
2158static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3f3e7124 2159 u32 error_code)
6aa8b732 2160{
e833240f 2161 gfn_t gfn;
e2dec939 2162 int r;
6aa8b732 2163
b8688d51 2164 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
e2dec939
AK		 2165 r = mmu_topup_memory_caches(vcpu);
2166 if (r)
2167 return r;
714b93da 2168
6aa8b732 2169 ASSERT(vcpu);
ad312c7c 2170 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2171
e833240f 2172 gfn = gva >> PAGE_SHIFT;
6aa8b732 2173
e833240f
AK		 2174 return nonpaging_map(vcpu, gva & PAGE_MASK,
2175 error_code & PFERR_WRITE_MASK, gfn);
6aa8b732
AK		 2176}
2177
fb72d167
JR		 2178static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
2179 u32 error_code)
2180{
35149e21 2181 pfn_t pfn;
fb72d167 2182 int r;
852e3c19 2183 int level;
05da4558 2184 gfn_t gfn = gpa >> PAGE_SHIFT;
e930bffe 2185 unsigned long mmu_seq;
fb72d167
JR		 2186
2187 ASSERT(vcpu);
2188 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2189
2190 r = mmu_topup_memory_caches(vcpu);
2191 if (r)
2192 return r;
2193
852e3c19
JR		 2194 level = mapping_level(vcpu, gfn);
2195
2196 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2197
e930bffe 2198 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2199 smp_rmb();
35149e21 2200 pfn = gfn_to_pfn(vcpu->kvm, gfn);
35149e21
AL		 2201 if (is_error_pfn(pfn)) {
2202 kvm_release_pfn_clean(pfn);
fb72d167
JR		 2203 return 1;
2204 }
2205 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2206 if (mmu_notifier_retry(vcpu, mmu_seq))
2207 goto out_unlock;
fb72d167
JR		 2208 kvm_mmu_free_some_pages(vcpu);
2209 r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
852e3c19 2210 level, gfn, pfn);
fb72d167 2211 spin_unlock(&vcpu->kvm->mmu_lock);
fb72d167
JR		 2212
2213 return r;
e930bffe
AA		 2214
2215out_unlock:
2216 spin_unlock(&vcpu->kvm->mmu_lock);
2217 kvm_release_pfn_clean(pfn);
2218 return 0;
fb72d167
JR		 2219}
2220
6aa8b732
AK		 2221static void nonpaging_free(struct kvm_vcpu *vcpu)
2222{
17ac10ad 2223 mmu_free_roots(vcpu);
6aa8b732
AK		 2224}
2225
2226static int nonpaging_init_context(struct kvm_vcpu *vcpu)
2227{
ad312c7c 2228 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2229
2230 context->new_cr3 = nonpaging_new_cr3;
2231 context->page_fault = nonpaging_page_fault;
6aa8b732
AK		 2232 context->gva_to_gpa = nonpaging_gva_to_gpa;
2233 context->free = nonpaging_free;
c7addb90 2234 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2235 context->sync_page = nonpaging_sync_page;
a7052897 2236 context->invlpg = nonpaging_invlpg;
cea0f0e7 2237 context->root_level = 0;
6aa8b732 2238 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2239 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2240 return 0;
2241}
2242
d835dfec 2243void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
6aa8b732 2244{
1165f5fe 2245 ++vcpu->stat.tlb_flush;
cbdd1bea 2246 kvm_x86_ops->tlb_flush(vcpu);
6aa8b732
AK		 2247}
2248
2249static void paging_new_cr3(struct kvm_vcpu *vcpu)
2250{
b8688d51 2251 pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3);
cea0f0e7 2252 mmu_free_roots(vcpu);
6aa8b732
AK		 2253}
2254
6aa8b732
AK		 2255static void inject_page_fault(struct kvm_vcpu *vcpu,
2256 u64 addr,
2257 u32 err_code)
2258{
c3c91fee 2259 kvm_inject_page_fault(vcpu, addr, err_code);
6aa8b732
AK		 2260}
2261
6aa8b732
AK		 2262static void paging_free(struct kvm_vcpu *vcpu)
2263{
2264 nonpaging_free(vcpu);
2265}
2266
82725b20
DE		 2267static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level)
2268{
2269 int bit7;
2270
2271 bit7 = (gpte >> 7) & 1;
2272 return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0;
2273}
2274
6aa8b732
AK		 2275#define PTTYPE 64
2276#include "paging_tmpl.h"
2277#undef PTTYPE
2278
2279#define PTTYPE 32
2280#include "paging_tmpl.h"
2281#undef PTTYPE
2282
82725b20
DE		 2283static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
2284{
2285 struct kvm_mmu *context = &vcpu->arch.mmu;
2286 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2287 u64 exb_bit_rsvd = 0;
2288
2289 if (!is_nx(vcpu))
2290 exb_bit_rsvd = rsvd_bits(63, 63);
2291 switch (level) {
2292 case PT32_ROOT_LEVEL:
2293 /* no rsvd bits for 2 level 4K page table entries */
2294 context->rsvd_bits_mask[0][1] = 0;
2295 context->rsvd_bits_mask[0][0] = 0;
f815bce8
XG		 2296 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
2297
2298 if (!is_pse(vcpu)) {
2299 context->rsvd_bits_mask[1][1] = 0;
2300 break;
2301 }
2302
82725b20
DE		 2303 if (is_cpuid_PSE36())
2304 /* 36bits PSE 4MB page */
2305 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2306 else
2307 /* 32 bits PSE 4MB page */
2308 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
82725b20
DE		 2309 break;
2310 case PT32E_ROOT_LEVEL:
20c466b5
DE		 2311 context->rsvd_bits_mask[0][2] =
2312 rsvd_bits(maxphyaddr, 63) |
2313 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
82725b20 2314 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2315 rsvd_bits(maxphyaddr, 62); /* PDE */
82725b20
DE		 2316 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2317 rsvd_bits(maxphyaddr, 62); /* PTE */
2318 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2319 rsvd_bits(maxphyaddr, 62) |
2320 rsvd_bits(13, 20); /* large page */
f815bce8 2321 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
82725b20
DE		 2322 break;
2323 case PT64_ROOT_LEVEL:
2324 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2325 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2326 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2327 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2328 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2329 rsvd_bits(maxphyaddr, 51);
82725b20
DE		 2330 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2331 rsvd_bits(maxphyaddr, 51);
2332 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
e04da980
JR		 2333 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
2334 rsvd_bits(maxphyaddr, 51) |
2335 rsvd_bits(13, 29);
82725b20 2336 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4c26b4cd
SY		 2337 rsvd_bits(maxphyaddr, 51) |
2338 rsvd_bits(13, 20); /* large page */
f815bce8 2339 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
82725b20
DE		 2340 break;
2341 }
2342}
2343
17ac10ad 2344static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level)
6aa8b732 2345{
ad312c7c 2346 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2347
2348 ASSERT(is_pae(vcpu));
2349 context->new_cr3 = paging_new_cr3;
2350 context->page_fault = paging64_page_fault;
6aa8b732 2351 context->gva_to_gpa = paging64_gva_to_gpa;
c7addb90 2352 context->prefetch_page = paging64_prefetch_page;
e8bc217a 2353 context->sync_page = paging64_sync_page;
a7052897 2354 context->invlpg = paging64_invlpg;
6aa8b732 2355 context->free = paging_free;
17ac10ad
AK		 2356 context->root_level = level;
2357 context->shadow_root_level = level;
17c3ba9d 2358 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2359 return 0;
2360}
2361
17ac10ad
AK		 2362static int paging64_init_context(struct kvm_vcpu *vcpu)
2363{
82725b20 2364 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
17ac10ad
AK		 2365 return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL);
2366}
2367
6aa8b732
AK		 2368static int paging32_init_context(struct kvm_vcpu *vcpu)
2369{
ad312c7c 2370 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732 2371
82725b20 2372 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
6aa8b732
AK		 2373 context->new_cr3 = paging_new_cr3;
2374 context->page_fault = paging32_page_fault;
6aa8b732
AK		 2375 context->gva_to_gpa = paging32_gva_to_gpa;
2376 context->free = paging_free;
c7addb90 2377 context->prefetch_page = paging32_prefetch_page;
e8bc217a 2378 context->sync_page = paging32_sync_page;
a7052897 2379 context->invlpg = paging32_invlpg;
6aa8b732
AK		 2380 context->root_level = PT32_ROOT_LEVEL;
2381 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2382 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2383 return 0;
2384}
2385
2386static int paging32E_init_context(struct kvm_vcpu *vcpu)
2387{
82725b20 2388 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
17ac10ad 2389 return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
6aa8b732
AK		 2390}
2391
fb72d167
JR		 2392static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2393{
2394 struct kvm_mmu *context = &vcpu->arch.mmu;
2395
2396 context->new_cr3 = nonpaging_new_cr3;
2397 context->page_fault = tdp_page_fault;
2398 context->free = nonpaging_free;
2399 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2400 context->sync_page = nonpaging_sync_page;
a7052897 2401 context->invlpg = nonpaging_invlpg;
67253af5 2402 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
fb72d167
JR		 2403 context->root_hpa = INVALID_PAGE;
2404
2405 if (!is_paging(vcpu)) {
2406 context->gva_to_gpa = nonpaging_gva_to_gpa;
2407 context->root_level = 0;
2408 } else if (is_long_mode(vcpu)) {
82725b20 2409 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
fb72d167
JR		 2410 context->gva_to_gpa = paging64_gva_to_gpa;
2411 context->root_level = PT64_ROOT_LEVEL;
2412 } else if (is_pae(vcpu)) {
82725b20 2413 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
fb72d167
JR		 2414 context->gva_to_gpa = paging64_gva_to_gpa;
2415 context->root_level = PT32E_ROOT_LEVEL;
2416 } else {
82725b20 2417 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
fb72d167
JR		 2418 context->gva_to_gpa = paging32_gva_to_gpa;
2419 context->root_level = PT32_ROOT_LEVEL;
2420 }
2421
2422 return 0;
2423}
2424
2425static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
6aa8b732 2426{
a770f6f2
AK		 2427 int r;
2428
6aa8b732 2429 ASSERT(vcpu);
ad312c7c 2430 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732
AK		 2431
2432 if (!is_paging(vcpu))
a770f6f2 2433 r = nonpaging_init_context(vcpu);
a9058ecd 2434 else if (is_long_mode(vcpu))
a770f6f2 2435 r = paging64_init_context(vcpu);
6aa8b732 2436 else if (is_pae(vcpu))
a770f6f2 2437 r = paging32E_init_context(vcpu);
6aa8b732 2438 else
a770f6f2
AK		 2439 r = paging32_init_context(vcpu);
2440
5b7e0102 2441 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
a770f6f2
AK		 2442
2443 return r;
6aa8b732
AK		 2444}
2445
fb72d167
JR		 2446static int init_kvm_mmu(struct kvm_vcpu *vcpu)
2447{
35149e21
AL		 2448 vcpu->arch.update_pte.pfn = bad_pfn;
2449
fb72d167
JR		 2450 if (tdp_enabled)
2451 return init_kvm_tdp_mmu(vcpu);
2452 else
2453 return init_kvm_softmmu(vcpu);
2454}
2455
6aa8b732
AK		 2456static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
2457{
2458 ASSERT(vcpu);
ad312c7c
ZX		 2459 if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
2460 vcpu->arch.mmu.free(vcpu);
2461 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
6aa8b732
AK		 2462 }
2463}
2464
2465int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
17c3ba9d
AK		 2466{
2467 destroy_kvm_mmu(vcpu);
2468 return init_kvm_mmu(vcpu);
2469}
8668a3c4 2470EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
17c3ba9d
AK		 2471
2472int kvm_mmu_load(struct kvm_vcpu *vcpu)
6aa8b732 2473{
714b93da
AK		 2474 int r;
2475
e2dec939 2476 r = mmu_topup_memory_caches(vcpu);
17c3ba9d
AK		 2477 if (r)
2478 goto out;
aaee2c94 2479 spin_lock(&vcpu->kvm->mmu_lock);
eb787d10 2480 kvm_mmu_free_some_pages(vcpu);
8986ecc0 2481 r = mmu_alloc_roots(vcpu);
0ba73cda 2482 mmu_sync_roots(vcpu);
aaee2c94 2483 spin_unlock(&vcpu->kvm->mmu_lock);
8986ecc0
MT		 2484 if (r)
2485 goto out;
3662cb1c 2486 /* set_cr3() should ensure TLB has been flushed */
ad312c7c 2487 kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
714b93da
AK		 2488out:
2489 return r;
6aa8b732 2490}
17c3ba9d
AK		 2491EXPORT_SYMBOL_GPL(kvm_mmu_load);
2492
2493void kvm_mmu_unload(struct kvm_vcpu *vcpu)
2494{
2495 mmu_free_roots(vcpu);
2496}
6aa8b732 2497
09072daf 2498static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
4db35314 2499 struct kvm_mmu_page *sp,
ac1b714e
AK		 2500 u64 *spte)
2501{
2502 u64 pte;
2503 struct kvm_mmu_page *child;
2504
2505 pte = *spte;
c7addb90 2506 if (is_shadow_present_pte(pte)) {
776e6633 2507 if (is_last_spte(pte, sp->role.level))
290fc38d 2508 rmap_remove(vcpu->kvm, spte);
ac1b714e
AK		 2509 else {
2510 child = page_header(pte & PT64_BASE_ADDR_MASK);
90cb0529 2511 mmu_page_remove_parent_pte(child, spte);
ac1b714e
AK		 2512 }
2513 }
d555c333 2514 __set_spte(spte, shadow_trap_nonpresent_pte);
05da4558
MT		 2515 if (is_large_pte(pte))
2516 --vcpu->kvm->stat.lpages;
ac1b714e
AK		 2517}
2518
0028425f 2519static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4db35314 2520 struct kvm_mmu_page *sp,
0028425f 2521 u64 *spte,
489f1d65 2522 const void *new)
0028425f 2523{
30945387 2524 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
7e4e4056
JR		 2525 ++vcpu->kvm->stat.mmu_pde_zapped;
2526 return;
30945387 2527 }
0028425f 2528
4cee5764 2529 ++vcpu->kvm->stat.mmu_pte_updated;
5b7e0102 2530 if (!sp->role.cr4_pae)
489f1d65 2531 paging32_update_pte(vcpu, sp, spte, new);
0028425f 2532 else
489f1d65 2533 paging64_update_pte(vcpu, sp, spte, new);
0028425f
AK		 2534}
2535
79539cec
AK		 2536static bool need_remote_flush(u64 old, u64 new)
2537{
2538 if (!is_shadow_present_pte(old))
2539 return false;
2540 if (!is_shadow_present_pte(new))
2541 return true;
2542 if ((old ^ new) & PT64_BASE_ADDR_MASK)
2543 return true;
2544 old ^= PT64_NX_MASK;
2545 new ^= PT64_NX_MASK;
2546 return (old & ~new & PT64_PERM_MASK) != 0;
2547}
2548
2549static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new)
2550{
2551 if (need_remote_flush(old, new))
2552 kvm_flush_remote_tlbs(vcpu->kvm);
2553 else
2554 kvm_mmu_flush_tlb(vcpu);
2555}
2556
12b7d28f
AK		 2557static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
2558{
ad312c7c 2559 u64 *spte = vcpu->arch.last_pte_updated;
12b7d28f 2560
7b52345e 2561 return !!(spte && (*spte & shadow_accessed_mask));
12b7d28f
AK		 2562}
2563
d7824fff 2564static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
72016f3a 2565 u64 gpte)
d7824fff
AK		 2566{
2567 gfn_t gfn;
35149e21 2568 pfn_t pfn;
d7824fff 2569
43a3795a 2570 if (!is_present_gpte(gpte))
d7824fff
AK		 2571 return;
2572 gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
72dc67a6 2573
e930bffe 2574 vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2575 smp_rmb();
35149e21 2576 pfn = gfn_to_pfn(vcpu->kvm, gfn);
72dc67a6 2577
35149e21
AL		 2578 if (is_error_pfn(pfn)) {
2579 kvm_release_pfn_clean(pfn);
d196e343
AK		 2580 return;
2581 }
d7824fff 2582 vcpu->arch.update_pte.gfn = gfn;
35149e21 2583 vcpu->arch.update_pte.pfn = pfn;
d7824fff
AK		 2584}
2585
1b7fcd32
AK		 2586static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
2587{
2588 u64 *spte = vcpu->arch.last_pte_updated;
2589
2590 if (spte
2591 && vcpu->arch.last_pte_gfn == gfn
2592 && shadow_accessed_mask
2593 && !(*spte & shadow_accessed_mask)
2594 && is_shadow_present_pte(*spte))
2595 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
2596}
2597
09072daf 2598void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
ad218f85
MT		 2599 const u8 *new, int bytes,
2600 bool guest_initiated)
da4a00f0 2601{
9b7a0325 2602 gfn_t gfn = gpa >> PAGE_SHIFT;
4db35314 2603 struct kvm_mmu_page *sp;
0e7bc4b9 2604 struct hlist_node *node, *n;
9b7a0325
AK		 2605 struct hlist_head *bucket;
2606 unsigned index;
489f1d65 2607 u64 entry, gentry;
9b7a0325 2608 u64 *spte;
9b7a0325 2609 unsigned offset = offset_in_page(gpa);
0e7bc4b9 2610 unsigned pte_size;
9b7a0325 2611 unsigned page_offset;
0e7bc4b9 2612 unsigned misaligned;
fce0657f 2613 unsigned quadrant;
9b7a0325 2614 int level;
86a5ba02 2615 int flooded = 0;
ac1b714e 2616 int npte;
489f1d65 2617 int r;
08e850c6 2618 int invlpg_counter;
9b7a0325 2619
b8688d51 2620 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
72016f3a 2621
08e850c6 2622 invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter);
72016f3a
AK		 2623
2624 /*
2625 * Assume that the pte write on a page table of the same type
2626 * as the current vcpu paging mode. This is nearly always true
2627 * (might be false while changing modes). Note it is verified later
2628 * by update_pte().
2629 */
08e850c6 2630 if ((is_pae(vcpu) && bytes == 4) || !new) {
72016f3a 2631 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
08e850c6
AK		 2632 if (is_pae(vcpu)) {
2633 gpa &= ~(gpa_t)7;
2634 bytes = 8;
2635 }
2636 r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8));
72016f3a
AK		 2637 if (r)
2638 gentry = 0;
08e850c6
AK		 2639 new = (const u8 *)&gentry;
2640 }
2641
2642 switch (bytes) {
2643 case 4:
2644 gentry = *(const u32 *)new;
2645 break;
2646 case 8:
2647 gentry = *(const u64 *)new;
2648 break;
2649 default:
2650 gentry = 0;
2651 break;
72016f3a
AK		 2652 }
2653
2654 mmu_guess_page_from_pte_write(vcpu, gpa, gentry);
aaee2c94 2655 spin_lock(&vcpu->kvm->mmu_lock);
08e850c6
AK		 2656 if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter)
2657 gentry = 0;
1b7fcd32 2658 kvm_mmu_access_page(vcpu, gfn);
eb787d10 2659 kvm_mmu_free_some_pages(vcpu);
4cee5764 2660 ++vcpu->kvm->stat.mmu_pte_write;
c7addb90 2661 kvm_mmu_audit(vcpu, "pre pte write");
ad218f85
MT		 2662 if (guest_initiated) {
2663 if (gfn == vcpu->arch.last_pt_write_gfn
2664 && !last_updated_pte_accessed(vcpu)) {
2665 ++vcpu->arch.last_pt_write_count;
2666 if (vcpu->arch.last_pt_write_count >= 3)
2667 flooded = 1;
2668 } else {
2669 vcpu->arch.last_pt_write_gfn = gfn;
2670 vcpu->arch.last_pt_write_count = 1;
2671 vcpu->arch.last_pte_updated = NULL;
2672 }
86a5ba02 2673 }
1ae0a13d 2674 index = kvm_page_table_hashfn(gfn);
f05e70ac 2675 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4db35314 2676 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) {
f6e2c02b 2677 if (sp->gfn != gfn || sp->role.direct || sp->role.invalid)
9b7a0325 2678 continue;
5b7e0102 2679 pte_size = sp->role.cr4_pae ? 8 : 4;
0e7bc4b9 2680 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
e925c5ba 2681 misaligned |= bytes < 4;
86a5ba02 2682 if (misaligned || flooded) {
0e7bc4b9
AK		 2683 /*
2684 * Misaligned accesses are too much trouble to fix
2685 * up; also, they usually indicate a page is not used
2686 * as a page table.
86a5ba02
AK		 2687 *
2688 * If we're seeing too many writes to a page,
2689 * it may no longer be a page table, or we may be
2690 * forking, in which case it is better to unmap the
2691 * page.
0e7bc4b9
AK		 2692 */
2693 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4db35314 2694 gpa, bytes, sp->role.word);
07385413
MT		 2695 if (kvm_mmu_zap_page(vcpu->kvm, sp))
2696 n = bucket->first;
4cee5764 2697 ++vcpu->kvm->stat.mmu_flooded;
0e7bc4b9
AK		 2698 continue;
2699 }
9b7a0325 2700 page_offset = offset;
4db35314 2701 level = sp->role.level;
ac1b714e 2702 npte = 1;
5b7e0102 2703 if (!sp->role.cr4_pae) {
ac1b714e
AK		 2704 page_offset <<= 1; /* 32->64 */
2705 /*
2706 * A 32-bit pde maps 4MB while the shadow pdes map
2707 * only 2MB. So we need to double the offset again
2708 * and zap two pdes instead of one.
2709 */
2710 if (level == PT32_ROOT_LEVEL) {
6b8d0f9b 2711 page_offset &= ~7; /* kill rounding error */
ac1b714e
AK		 2712 page_offset <<= 1;
2713 npte = 2;
2714 }
fce0657f 2715 quadrant = page_offset >> PAGE_SHIFT;
9b7a0325 2716 page_offset &= ~PAGE_MASK;
4db35314 2717 if (quadrant != sp->role.quadrant)
fce0657f 2718 continue;
9b7a0325 2719 }
4db35314 2720 spte = &sp->spt[page_offset / sizeof(*spte)];
ac1b714e 2721 while (npte--) {
79539cec 2722 entry = *spte;
4db35314 2723 mmu_pte_write_zap_pte(vcpu, sp, spte);
72016f3a
AK		 2724 if (gentry)
2725 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
79539cec 2726 mmu_pte_write_flush_tlb(vcpu, entry, *spte);
ac1b714e 2727 ++spte;
9b7a0325 2728 }
9b7a0325 2729 }
c7addb90 2730 kvm_mmu_audit(vcpu, "post pte write");
aaee2c94 2731 spin_unlock(&vcpu->kvm->mmu_lock);
35149e21
AL		 2732 if (!is_error_pfn(vcpu->arch.update_pte.pfn)) {
2733 kvm_release_pfn_clean(vcpu->arch.update_pte.pfn);
2734 vcpu->arch.update_pte.pfn = bad_pfn;
d7824fff 2735 }
da4a00f0
AK		 2736}
2737
a436036b
AK		 2738int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2739{
10589a46
MT		 2740 gpa_t gpa;
2741 int r;
a436036b 2742
60f24784
AK		 2743 if (tdp_enabled)
2744 return 0;
2745
1871c602 2746 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
10589a46 2747
aaee2c94 2748 spin_lock(&vcpu->kvm->mmu_lock);
10589a46 2749 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
aaee2c94 2750 spin_unlock(&vcpu->kvm->mmu_lock);
10589a46 2751 return r;
a436036b 2752}
577bdc49 2753EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
a436036b 2754
22d95b12 2755void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
ebeace86 2756{
3b80fffe
IE		 2757 while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES &&
2758 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
4db35314 2759 struct kvm_mmu_page *sp;
ebeace86 2760
f05e70ac 2761 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4db35314
AK		 2762 struct kvm_mmu_page, link);
2763 kvm_mmu_zap_page(vcpu->kvm, sp);
4cee5764 2764 ++vcpu->kvm->stat.mmu_recycled;
ebeace86
AK		 2765 }
2766}
ebeace86 2767
3067714c
AK		 2768int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
2769{
2770 int r;
2771 enum emulation_result er;
2772
ad312c7c 2773 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code);
3067714c
AK		 2774 if (r < 0)
2775 goto out;
2776
2777 if (!r) {
2778 r = 1;
2779 goto out;
2780 }
2781
b733bfb5
AK		 2782 r = mmu_topup_memory_caches(vcpu);
2783 if (r)
2784 goto out;
2785
851ba692 2786 er = emulate_instruction(vcpu, cr2, error_code, 0);
3067714c
AK		 2787
2788 switch (er) {
2789 case EMULATE_DONE:
2790 return 1;
2791 case EMULATE_DO_MMIO:
2792 ++vcpu->stat.mmio_exits;
2793 return 0;
2794 case EMULATE_FAIL:
3f5d18a9
AK		 2795 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2796 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
a9c7399d 2797 vcpu->run->internal.ndata = 0;
3f5d18a9 2798 return 0;
3067714c
AK		 2799 default:
2800 BUG();
2801 }
2802out:
3067714c
AK		 2803 return r;
2804}
2805EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
2806
a7052897
MT		 2807void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
2808{
a7052897 2809 vcpu->arch.mmu.invlpg(vcpu, gva);
a7052897
MT		 2810 kvm_mmu_flush_tlb(vcpu);
2811 ++vcpu->stat.invlpg;
2812}
2813EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
2814
18552672
JR		 2815void kvm_enable_tdp(void)
2816{
2817 tdp_enabled = true;
2818}
2819EXPORT_SYMBOL_GPL(kvm_enable_tdp);
2820
5f4cb662
JR		 2821void kvm_disable_tdp(void)
2822{
2823 tdp_enabled = false;
2824}
2825EXPORT_SYMBOL_GPL(kvm_disable_tdp);
2826
6aa8b732
AK		 2827static void free_mmu_pages(struct kvm_vcpu *vcpu)
2828{
ad312c7c 2829 free_page((unsigned long)vcpu->arch.mmu.pae_root);
6aa8b732
AK		 2830}
2831
2832static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
2833{
17ac10ad 2834 struct page *page;
6aa8b732
AK		 2835 int i;
2836
2837 ASSERT(vcpu);
2838
17ac10ad
AK		 2839 /*
2840 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
2841 * Therefore we need to allocate shadow page tables in the first
2842 * 4GB of memory, which happens to fit the DMA32 zone.
2843 */
2844 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
2845 if (!page)
d7fa6ab2
WY		 2846 return -ENOMEM;
2847
ad312c7c 2848 vcpu->arch.mmu.pae_root = page_address(page);
17ac10ad 2849 for (i = 0; i < 4; ++i)
ad312c7c 2850 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2851
6aa8b732 2852 return 0;
6aa8b732
AK		 2853}
2854
8018c27b 2855int kvm_mmu_create(struct kvm_vcpu *vcpu)
6aa8b732 2856{
6aa8b732 2857 ASSERT(vcpu);
ad312c7c 2858 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2859
8018c27b
IM		 2860 return alloc_mmu_pages(vcpu);
2861}
6aa8b732 2862
8018c27b
IM		 2863int kvm_mmu_setup(struct kvm_vcpu *vcpu)
2864{
2865 ASSERT(vcpu);
ad312c7c 2866 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2c264957 2867
8018c27b 2868 return init_kvm_mmu(vcpu);
6aa8b732
AK		 2869}
2870
2871void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
2872{
2873 ASSERT(vcpu);
2874
2875 destroy_kvm_mmu(vcpu);
2876 free_mmu_pages(vcpu);
714b93da 2877 mmu_free_memory_caches(vcpu);
6aa8b732
AK		 2878}
2879
90cb0529 2880void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
6aa8b732 2881{
4db35314 2882 struct kvm_mmu_page *sp;
6aa8b732 2883
f05e70ac 2884 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
6aa8b732
AK		 2885 int i;
2886 u64 *pt;
2887
291f26bc 2888 if (!test_bit(slot, sp->slot_bitmap))
6aa8b732
AK		 2889 continue;
2890
4db35314 2891 pt = sp->spt;
6aa8b732
AK		 2892 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2893 /* avoid RMW */
9647c14c 2894 if (pt[i] & PT_WRITABLE_MASK)
6aa8b732 2895 pt[i] &= ~PT_WRITABLE_MASK;
6aa8b732 2896 }
171d595d 2897 kvm_flush_remote_tlbs(kvm);
6aa8b732 2898}
37a7d8b0 2899
90cb0529 2900void kvm_mmu_zap_all(struct kvm *kvm)
e0fa826f 2901{
4db35314 2902 struct kvm_mmu_page *sp, *node;
e0fa826f 2903
aaee2c94 2904 spin_lock(&kvm->mmu_lock);
f05e70ac 2905 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
07385413
MT		 2906 if (kvm_mmu_zap_page(kvm, sp))
2907 node = container_of(kvm->arch.active_mmu_pages.next,
2908 struct kvm_mmu_page, link);
aaee2c94 2909 spin_unlock(&kvm->mmu_lock);
e0fa826f 2910
90cb0529 2911 kvm_flush_remote_tlbs(kvm);
e0fa826f
DL		 2912}
2913
8b2cf73c 2914static void kvm_mmu_remove_one_alloc_mmu_page(struct kvm *kvm)
3ee16c81
IE		 2915{
2916 struct kvm_mmu_page *page;
2917
2918 page = container_of(kvm->arch.active_mmu_pages.prev,
2919 struct kvm_mmu_page, link);
2920 kvm_mmu_zap_page(kvm, page);
2921}
2922
2923static int mmu_shrink(int nr_to_scan, gfp_t gfp_mask)
2924{
2925 struct kvm *kvm;
2926 struct kvm *kvm_freed = NULL;
2927 int cache_count = 0;
2928
2929 spin_lock(&kvm_lock);
2930
2931 list_for_each_entry(kvm, &vm_list, vm_list) {
f656ce01 2932 int npages, idx;
3ee16c81 2933
f656ce01 2934 idx = srcu_read_lock(&kvm->srcu);
3ee16c81
IE		 2935 spin_lock(&kvm->mmu_lock);
2936 npages = kvm->arch.n_alloc_mmu_pages -
2937 kvm->arch.n_free_mmu_pages;
2938 cache_count += npages;
2939 if (!kvm_freed && nr_to_scan > 0 && npages > 0) {
2940 kvm_mmu_remove_one_alloc_mmu_page(kvm);
2941 cache_count--;
2942 kvm_freed = kvm;
2943 }
2944 nr_to_scan--;
2945
2946 spin_unlock(&kvm->mmu_lock);
f656ce01 2947 srcu_read_unlock(&kvm->srcu, idx);
3ee16c81
IE		 2948 }
2949 if (kvm_freed)
2950 list_move_tail(&kvm_freed->vm_list, &vm_list);
2951
2952 spin_unlock(&kvm_lock);
2953
2954 return cache_count;
2955}
2956
2957static struct shrinker mmu_shrinker = {
2958 .shrink = mmu_shrink,
2959 .seeks = DEFAULT_SEEKS * 10,
2960};
2961
2ddfd20e 2962static void mmu_destroy_caches(void)
b5a33a75
AK		 2963{
2964 if (pte_chain_cache)
2965 kmem_cache_destroy(pte_chain_cache);
2966 if (rmap_desc_cache)
2967 kmem_cache_destroy(rmap_desc_cache);
d3d25b04
AK		 2968 if (mmu_page_header_cache)
2969 kmem_cache_destroy(mmu_page_header_cache);
b5a33a75
AK		 2970}
2971
3ee16c81
IE		 2972void kvm_mmu_module_exit(void)
2973{
2974 mmu_destroy_caches();
2975 unregister_shrinker(&mmu_shrinker);
2976}
2977
b5a33a75
AK		 2978int kvm_mmu_module_init(void)
2979{
2980 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
2981 sizeof(struct kvm_pte_chain),
20c2df83 2982 0, 0, NULL);
b5a33a75
AK		 2983 if (!pte_chain_cache)
2984 goto nomem;
2985 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
2986 sizeof(struct kvm_rmap_desc),
20c2df83 2987 0, 0, NULL);
b5a33a75
AK		 2988 if (!rmap_desc_cache)
2989 goto nomem;
2990
d3d25b04
AK		 2991 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
2992 sizeof(struct kvm_mmu_page),
20c2df83 2993 0, 0, NULL);
d3d25b04
AK		 2994 if (!mmu_page_header_cache)
2995 goto nomem;
2996
3ee16c81
IE		 2997 register_shrinker(&mmu_shrinker);
2998
b5a33a75
AK		 2999 return 0;
3000
3001nomem:
3ee16c81 3002 mmu_destroy_caches();
b5a33a75
AK		 3003 return -ENOMEM;
3004}
3005
3ad82a7e
ZX		 3006/*
3007 * Caculate mmu pages needed for kvm.
3008 */
3009unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3010{
3011 int i;
3012 unsigned int nr_mmu_pages;
3013 unsigned int nr_pages = 0;
bc6678a3 3014 struct kvm_memslots *slots;
3ad82a7e 3015
bc6678a3
MT		 3016 slots = rcu_dereference(kvm->memslots);
3017 for (i = 0; i < slots->nmemslots; i++)
3018 nr_pages += slots->memslots[i].npages;
3ad82a7e
ZX		 3019
3020 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3021 nr_mmu_pages = max(nr_mmu_pages,
3022 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3023
3024 return nr_mmu_pages;
3025}
3026
2f333bcb
MT		 3027static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3028 unsigned len)
3029{
3030 if (len > buffer->len)
3031 return NULL;
3032 return buffer->ptr;
3033}
3034
3035static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3036 unsigned len)
3037{
3038 void *ret;
3039
3040 ret = pv_mmu_peek_buffer(buffer, len);
3041 if (!ret)
3042 return ret;
3043 buffer->ptr += len;
3044 buffer->len -= len;
3045 buffer->processed += len;
3046 return ret;
3047}
3048
3049static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3050 gpa_t addr, gpa_t value)
3051{
3052 int bytes = 8;
3053 int r;
3054
3055 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3056 bytes = 4;
3057
3058 r = mmu_topup_memory_caches(vcpu);
3059 if (r)
3060 return r;
3061
3200f405 3062 if (!emulator_write_phys(vcpu, addr, &value, bytes))
2f333bcb
MT		 3063 return -EFAULT;
3064
3065 return 1;
3066}
3067
3068static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3069{
a8cd0244 3070 kvm_set_cr3(vcpu, vcpu->arch.cr3);
2f333bcb
MT		 3071 return 1;
3072}
3073
3074static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3075{
3076 spin_lock(&vcpu->kvm->mmu_lock);
3077 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3078 spin_unlock(&vcpu->kvm->mmu_lock);
3079 return 1;
3080}
3081
3082static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3083 struct kvm_pv_mmu_op_buffer *buffer)
3084{
3085 struct kvm_mmu_op_header *header;
3086
3087 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3088 if (!header)
3089 return 0;
3090 switch (header->op) {
3091 case KVM_MMU_OP_WRITE_PTE: {
3092 struct kvm_mmu_op_write_pte *wpte;
3093
3094 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3095 if (!wpte)
3096 return 0;
3097 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3098 wpte->pte_val);
3099 }
3100 case KVM_MMU_OP_FLUSH_TLB: {
3101 struct kvm_mmu_op_flush_tlb *ftlb;
3102
3103 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3104 if (!ftlb)
3105 return 0;
3106 return kvm_pv_mmu_flush_tlb(vcpu);
3107 }
3108 case KVM_MMU_OP_RELEASE_PT: {
3109 struct kvm_mmu_op_release_pt *rpt;
3110
3111 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3112 if (!rpt)
3113 return 0;
3114 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3115 }
3116 default: return 0;
3117 }
3118}
3119
3120int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3121 gpa_t addr, unsigned long *ret)
3122{
3123 int r;
6ad18fba 3124 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
2f333bcb 3125
6ad18fba
DH		 3126 buffer->ptr = buffer->buf;
3127 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3128 buffer->processed = 0;
2f333bcb 3129
6ad18fba 3130 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
2f333bcb
MT		 3131 if (r)
3132 goto out;
3133
6ad18fba
DH		 3134 while (buffer->len) {
3135 r = kvm_pv_mmu_op_one(vcpu, buffer);
2f333bcb
MT		 3136 if (r < 0)
3137 goto out;
3138 if (r == 0)
3139 break;
3140 }
3141
3142 r = 1;
3143out:
6ad18fba 3144 *ret = buffer->processed;
2f333bcb
MT		 3145 return r;
3146}
3147
94d8b056
MT		 3148int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3149{
3150 struct kvm_shadow_walk_iterator iterator;
3151 int nr_sptes = 0;
3152
3153 spin_lock(&vcpu->kvm->mmu_lock);
3154 for_each_shadow_entry(vcpu, addr, iterator) {
3155 sptes[iterator.level-1] = *iterator.sptep;
3156 nr_sptes++;
3157 if (!is_shadow_present_pte(*iterator.sptep))
3158 break;
3159 }
3160 spin_unlock(&vcpu->kvm->mmu_lock);
3161
3162 return nr_sptes;
3163}
3164EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3165
37a7d8b0
AK		 3166#ifdef AUDIT
3167
3168static const char *audit_msg;
3169
3170static gva_t canonicalize(gva_t gva)
3171{
3172#ifdef CONFIG_X86_64
3173 gva = (long long)(gva << 16) >> 16;
3174#endif
3175 return gva;
3176}
3177
08a3732b 3178
805d32de 3179typedef void (*inspect_spte_fn) (struct kvm *kvm, u64 *sptep);
08a3732b
MT		 3180
3181static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp,
3182 inspect_spte_fn fn)
3183{
3184 int i;
3185
3186 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3187 u64 ent = sp->spt[i];
3188
3189 if (is_shadow_present_pte(ent)) {
2920d728 3190 if (!is_last_spte(ent, sp->role.level)) {
08a3732b
MT		 3191 struct kvm_mmu_page *child;
3192 child = page_header(ent & PT64_BASE_ADDR_MASK);
3193 __mmu_spte_walk(kvm, child, fn);
2920d728 3194 } else
805d32de 3195 fn(kvm, &sp->spt[i]);
08a3732b
MT		 3196 }
3197 }
3198}
3199
3200static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn)
3201{
3202 int i;
3203 struct kvm_mmu_page *sp;
3204
3205 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3206 return;
3207 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3208 hpa_t root = vcpu->arch.mmu.root_hpa;
3209 sp = page_header(root);
3210 __mmu_spte_walk(vcpu->kvm, sp, fn);
3211 return;
3212 }
3213 for (i = 0; i < 4; ++i) {
3214 hpa_t root = vcpu->arch.mmu.pae_root[i];
3215
3216 if (root && VALID_PAGE(root)) {
3217 root &= PT64_BASE_ADDR_MASK;
3218 sp = page_header(root);
3219 __mmu_spte_walk(vcpu->kvm, sp, fn);
3220 }
3221 }
3222 return;
3223}
3224
37a7d8b0
AK		 3225static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
3226 gva_t va, int level)
3227{
3228 u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK);
3229 int i;
3230 gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1));
3231
3232 for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) {
3233 u64 ent = pt[i];
3234
c7addb90 3235 if (ent == shadow_trap_nonpresent_pte)
37a7d8b0
AK		 3236 continue;
3237
3238 va = canonicalize(va);
2920d728
MT		 3239 if (is_shadow_present_pte(ent) && !is_last_spte(ent, level))
3240 audit_mappings_page(vcpu, ent, va, level - 1);
3241 else {
1871c602 3242 gpa_t gpa = kvm_mmu_gva_to_gpa_read(vcpu, va, NULL);
34382539
JK		 3243 gfn_t gfn = gpa >> PAGE_SHIFT;
3244 pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn);
3245 hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT;
37a7d8b0 3246
2aaf65e8
MT		 3247 if (is_error_pfn(pfn)) {
3248 kvm_release_pfn_clean(pfn);
3249 continue;
3250 }
3251
c7addb90 3252 if (is_shadow_present_pte(ent)
37a7d8b0 3253 && (ent & PT64_BASE_ADDR_MASK) != hpa)
c7addb90
AK		 3254 printk(KERN_ERR "xx audit error: (%s) levels %d"
3255 " gva %lx gpa %llx hpa %llx ent %llx %d\n",
ad312c7c 3256 audit_msg, vcpu->arch.mmu.root_level,
d77c26fc
MD		 3257 va, gpa, hpa, ent,
3258 is_shadow_present_pte(ent));
c7addb90
AK		 3259 else if (ent == shadow_notrap_nonpresent_pte
3260 && !is_error_hpa(hpa))
3261 printk(KERN_ERR "audit: (%s) notrap shadow,"
3262 " valid guest gva %lx\n", audit_msg, va);
35149e21 3263 kvm_release_pfn_clean(pfn);
c7addb90 3264
37a7d8b0
AK		 3265 }
3266 }
3267}
3268
3269static void audit_mappings(struct kvm_vcpu *vcpu)
3270{
1ea252af 3271 unsigned i;
37a7d8b0 3272
ad312c7c
ZX		 3273 if (vcpu->arch.mmu.root_level == 4)
3274 audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4);
37a7d8b0
AK		 3275 else
3276 for (i = 0; i < 4; ++i)
ad312c7c 3277 if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK)
37a7d8b0 3278 audit_mappings_page(vcpu,
ad312c7c 3279 vcpu->arch.mmu.pae_root[i],
37a7d8b0
AK		 3280 i << 30,
3281 2);
3282}
3283
3284static int count_rmaps(struct kvm_vcpu *vcpu)
3285{
805d32de
XG		 3286 struct kvm *kvm = vcpu->kvm;
3287 struct kvm_memslots *slots;
37a7d8b0 3288 int nmaps = 0;
bc6678a3 3289 int i, j, k, idx;
37a7d8b0 3290
bc6678a3
MT		 3291 idx = srcu_read_lock(&kvm->srcu);
3292 slots = rcu_dereference(kvm->memslots);
37a7d8b0 3293 for (i = 0; i < KVM_MEMORY_SLOTS; ++i) {
bc6678a3 3294 struct kvm_memory_slot *m = &slots->memslots[i];
37a7d8b0
AK		 3295 struct kvm_rmap_desc *d;
3296
3297 for (j = 0; j < m->npages; ++j) {
290fc38d 3298 unsigned long *rmapp = &m->rmap[j];
37a7d8b0 3299
290fc38d 3300 if (!*rmapp)
37a7d8b0 3301 continue;
290fc38d 3302 if (!(*rmapp & 1)) {
37a7d8b0
AK		 3303 ++nmaps;
3304 continue;
3305 }
290fc38d 3306 d = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
37a7d8b0
AK		 3307 while (d) {
3308 for (k = 0; k < RMAP_EXT; ++k)
d555c333 3309 if (d->sptes[k])
37a7d8b0
AK		 3310 ++nmaps;
3311 else
3312 break;
3313 d = d->more;
3314 }
3315 }
3316 }
bc6678a3 3317 srcu_read_unlock(&kvm->srcu, idx);
37a7d8b0
AK		 3318 return nmaps;
3319}
3320
805d32de 3321void inspect_spte_has_rmap(struct kvm *kvm, u64 *sptep)
08a3732b
MT		 3322{
3323 unsigned long *rmapp;
3324 struct kvm_mmu_page *rev_sp;
3325 gfn_t gfn;
3326
3327 if (*sptep & PT_WRITABLE_MASK) {
3328 rev_sp = page_header(__pa(sptep));
3329 gfn = rev_sp->gfns[sptep - rev_sp->spt];
3330
3331 if (!gfn_to_memslot(kvm, gfn)) {
3332 if (!printk_ratelimit())
3333 return;
3334 printk(KERN_ERR "%s: no memslot for gfn %ld\n",
3335 audit_msg, gfn);
3336 printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n",
805d32de 3337 audit_msg, (long int)(sptep - rev_sp->spt),
08a3732b
MT		 3338 rev_sp->gfn);
3339 dump_stack();
3340 return;
3341 }
3342
2920d728 3343 rmapp = gfn_to_rmap(kvm, rev_sp->gfns[sptep - rev_sp->spt],
805d32de 3344 rev_sp->role.level);
08a3732b
MT		 3345 if (!*rmapp) {
3346 if (!printk_ratelimit())
3347 return;
3348 printk(KERN_ERR "%s: no rmap for writable spte %llx\n",
3349 audit_msg, *sptep);
3350 dump_stack();
3351 }
3352 }
3353
3354}
3355
3356void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu)
3357{
3358 mmu_spte_walk(vcpu, inspect_spte_has_rmap);
3359}
3360
3361static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu)
37a7d8b0 3362{
4db35314 3363 struct kvm_mmu_page *sp;
37a7d8b0
AK		 3364 int i;
3365
f05e70ac 3366 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
4db35314 3367 u64 *pt = sp->spt;
37a7d8b0 3368
4db35314 3369 if (sp->role.level != PT_PAGE_TABLE_LEVEL)
37a7d8b0
AK		 3370 continue;
3371
3372 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3373 u64 ent = pt[i];
3374
3375 if (!(ent & PT_PRESENT_MASK))
3376 continue;
3377 if (!(ent & PT_WRITABLE_MASK))
3378 continue;
805d32de 3379 inspect_spte_has_rmap(vcpu->kvm, &pt[i]);
37a7d8b0
AK		 3380 }
3381 }
08a3732b 3382 return;
37a7d8b0
AK		 3383}
3384
3385static void audit_rmap(struct kvm_vcpu *vcpu)
3386{
08a3732b
MT		 3387 check_writable_mappings_rmap(vcpu);
3388 count_rmaps(vcpu);
37a7d8b0
AK		 3389}
3390
3391static void audit_write_protection(struct kvm_vcpu *vcpu)
3392{
4db35314 3393 struct kvm_mmu_page *sp;
290fc38d
IE		 3394 struct kvm_memory_slot *slot;
3395 unsigned long *rmapp;
e58b0f9e 3396 u64 *spte;
290fc38d 3397 gfn_t gfn;
37a7d8b0 3398
f05e70ac 3399 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
f6e2c02b 3400 if (sp->role.direct)
37a7d8b0 3401 continue;
e58b0f9e
MT		 3402 if (sp->unsync)
3403 continue;
37a7d8b0 3404
4db35314 3405 gfn = unalias_gfn(vcpu->kvm, sp->gfn);
2843099f 3406 slot = gfn_to_memslot_unaliased(vcpu->kvm, sp->gfn);
290fc38d 3407 rmapp = &slot->rmap[gfn - slot->base_gfn];
e58b0f9e
MT		 3408
3409 spte = rmap_next(vcpu->kvm, rmapp, NULL);
3410 while (spte) {
3411 if (*spte & PT_WRITABLE_MASK)
3412 printk(KERN_ERR "%s: (%s) shadow page has "
3413 "writable mappings: gfn %lx role %x\n",
b8688d51 3414 __func__, audit_msg, sp->gfn,
4db35314 3415 sp->role.word);
e58b0f9e
MT		 3416 spte = rmap_next(vcpu->kvm, rmapp, spte);
3417 }
37a7d8b0
AK		 3418 }
3419}
3420
3421static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
3422{
3423 int olddbg = dbg;
3424
3425 dbg = 0;
3426 audit_msg = msg;
3427 audit_rmap(vcpu);
3428 audit_write_protection(vcpu);
2aaf65e8
MT		 3429 if (strcmp("pre pte write", audit_msg) != 0)
3430 audit_mappings(vcpu);
08a3732b 3431 audit_writable_sptes_have_rmaps(vcpu);
37a7d8b0
AK		 3432 dbg = olddbg;
3433}
3434
3435#endif
Linux 6.x block layer and io_uring tree(s)