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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
6aa8b732 AK |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * This module enables machines with Intel VT-x extensions to run virtual | |
6 | * machines without emulation or binary translation. | |
7 | * | |
8 | * MMU support | |
9 | * | |
10 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 11 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
12 | * |
13 | * Authors: | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
15 | * Avi Kivity <avi@qumranet.com> | |
6aa8b732 | 16 | */ |
e495606d | 17 | |
af585b92 | 18 | #include "irq.h" |
1d737c8a | 19 | #include "mmu.h" |
836a1b3c | 20 | #include "x86.h" |
6de4f3ad | 21 | #include "kvm_cache_regs.h" |
2f728d66 | 22 | #include "kvm_emulate.h" |
5f7dde7b | 23 | #include "cpuid.h" |
e495606d | 24 | |
edf88417 | 25 | #include <linux/kvm_host.h> |
6aa8b732 AK |
26 | #include <linux/types.h> |
27 | #include <linux/string.h> | |
6aa8b732 AK |
28 | #include <linux/mm.h> |
29 | #include <linux/highmem.h> | |
1767e931 PG |
30 | #include <linux/moduleparam.h> |
31 | #include <linux/export.h> | |
448353ca | 32 | #include <linux/swap.h> |
05da4558 | 33 | #include <linux/hugetlb.h> |
2f333bcb | 34 | #include <linux/compiler.h> |
bc6678a3 | 35 | #include <linux/srcu.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
3f07c014 | 37 | #include <linux/sched/signal.h> |
bf998156 | 38 | #include <linux/uaccess.h> |
114df303 | 39 | #include <linux/hash.h> |
f160c7b7 | 40 | #include <linux/kern_levels.h> |
1aa9b957 | 41 | #include <linux/kthread.h> |
6aa8b732 | 42 | |
e495606d | 43 | #include <asm/page.h> |
eb243d1d | 44 | #include <asm/memtype.h> |
e495606d | 45 | #include <asm/cmpxchg.h> |
0c55671f | 46 | #include <asm/e820/api.h> |
4e542370 | 47 | #include <asm/io.h> |
13673a90 | 48 | #include <asm/vmx.h> |
3d0c27ad | 49 | #include <asm/kvm_page_track.h> |
1261bfa3 | 50 | #include "trace.h" |
6aa8b732 | 51 | |
b8e8c830 PB |
52 | extern bool itlb_multihit_kvm_mitigation; |
53 | ||
54 | static int __read_mostly nx_huge_pages = -1; | |
13fb5927 PB |
55 | #ifdef CONFIG_PREEMPT_RT |
56 | /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */ | |
57 | static uint __read_mostly nx_huge_pages_recovery_ratio = 0; | |
58 | #else | |
1aa9b957 | 59 | static uint __read_mostly nx_huge_pages_recovery_ratio = 60; |
13fb5927 | 60 | #endif |
b8e8c830 PB |
61 | |
62 | static int set_nx_huge_pages(const char *val, const struct kernel_param *kp); | |
1aa9b957 | 63 | static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp); |
b8e8c830 PB |
64 | |
65 | static struct kernel_param_ops nx_huge_pages_ops = { | |
66 | .set = set_nx_huge_pages, | |
67 | .get = param_get_bool, | |
68 | }; | |
69 | ||
1aa9b957 JS |
70 | static struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = { |
71 | .set = set_nx_huge_pages_recovery_ratio, | |
72 | .get = param_get_uint, | |
73 | }; | |
74 | ||
b8e8c830 PB |
75 | module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644); |
76 | __MODULE_PARM_TYPE(nx_huge_pages, "bool"); | |
1aa9b957 JS |
77 | module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops, |
78 | &nx_huge_pages_recovery_ratio, 0644); | |
79 | __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint"); | |
b8e8c830 | 80 | |
18552672 JR |
81 | /* |
82 | * When setting this variable to true it enables Two-Dimensional-Paging | |
83 | * where the hardware walks 2 page tables: | |
84 | * 1. the guest-virtual to guest-physical | |
85 | * 2. while doing 1. it walks guest-physical to host-physical | |
86 | * If the hardware supports that we don't need to do shadow paging. | |
87 | */ | |
2f333bcb | 88 | bool tdp_enabled = false; |
18552672 | 89 | |
703c335d SC |
90 | static int max_page_level __read_mostly; |
91 | ||
8b1fe17c XG |
92 | enum { |
93 | AUDIT_PRE_PAGE_FAULT, | |
94 | AUDIT_POST_PAGE_FAULT, | |
95 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
96 | AUDIT_POST_PTE_WRITE, |
97 | AUDIT_PRE_SYNC, | |
98 | AUDIT_POST_SYNC | |
8b1fe17c | 99 | }; |
37a7d8b0 | 100 | |
8b1fe17c | 101 | #undef MMU_DEBUG |
37a7d8b0 AK |
102 | |
103 | #ifdef MMU_DEBUG | |
fa4a2c08 PB |
104 | static bool dbg = 0; |
105 | module_param(dbg, bool, 0644); | |
37a7d8b0 AK |
106 | |
107 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
108 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
fa4a2c08 | 109 | #define MMU_WARN_ON(x) WARN_ON(x) |
37a7d8b0 | 110 | #else |
37a7d8b0 AK |
111 | #define pgprintk(x...) do { } while (0) |
112 | #define rmap_printk(x...) do { } while (0) | |
fa4a2c08 | 113 | #define MMU_WARN_ON(x) do { } while (0) |
d6c69ee9 | 114 | #endif |
6aa8b732 | 115 | |
957ed9ef XG |
116 | #define PTE_PREFETCH_NUM 8 |
117 | ||
00763e41 | 118 | #define PT_FIRST_AVAIL_BITS_SHIFT 10 |
6eeb4ef0 PB |
119 | #define PT64_SECOND_AVAIL_BITS_SHIFT 54 |
120 | ||
121 | /* | |
122 | * The mask used to denote special SPTEs, which can be either MMIO SPTEs or | |
123 | * Access Tracking SPTEs. | |
124 | */ | |
125 | #define SPTE_SPECIAL_MASK (3ULL << 52) | |
126 | #define SPTE_AD_ENABLED_MASK (0ULL << 52) | |
127 | #define SPTE_AD_DISABLED_MASK (1ULL << 52) | |
1f4e5fc8 | 128 | #define SPTE_AD_WRPROT_ONLY_MASK (2ULL << 52) |
6eeb4ef0 | 129 | #define SPTE_MMIO_MASK (3ULL << 52) |
6aa8b732 | 130 | |
6aa8b732 AK |
131 | #define PT64_LEVEL_BITS 9 |
132 | ||
133 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 134 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 135 | |
6aa8b732 AK |
136 | #define PT64_INDEX(address, level)\ |
137 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
138 | ||
139 | ||
140 | #define PT32_LEVEL_BITS 10 | |
141 | ||
142 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 143 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 144 | |
e04da980 JR |
145 | #define PT32_LVL_OFFSET_MASK(level) \ |
146 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
147 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
148 | |
149 | #define PT32_INDEX(address, level)\ | |
150 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
151 | ||
152 | ||
8acc0993 KH |
153 | #ifdef CONFIG_DYNAMIC_PHYSICAL_MASK |
154 | #define PT64_BASE_ADDR_MASK (physical_mask & ~(u64)(PAGE_SIZE-1)) | |
155 | #else | |
156 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) | |
157 | #endif | |
e04da980 JR |
158 | #define PT64_LVL_ADDR_MASK(level) \ |
159 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
160 | * PT64_LEVEL_BITS))) - 1)) | |
161 | #define PT64_LVL_OFFSET_MASK(level) \ | |
162 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
163 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
164 | |
165 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
166 | #define PT32_DIR_BASE_ADDR_MASK \ | |
167 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
168 | #define PT32_LVL_ADDR_MASK(level) \ |
169 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
170 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 171 | |
53166229 | 172 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \ |
d0ec49d4 | 173 | | shadow_x_mask | shadow_nx_mask | shadow_me_mask) |
6aa8b732 | 174 | |
fe135d2c AK |
175 | #define ACC_EXEC_MASK 1 |
176 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
177 | #define ACC_USER_MASK PT_USER_MASK | |
178 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
179 | ||
f160c7b7 JS |
180 | /* The mask for the R/X bits in EPT PTEs */ |
181 | #define PT64_EPT_READABLE_MASK 0x1ull | |
182 | #define PT64_EPT_EXECUTABLE_MASK 0x4ull | |
183 | ||
90bb6fc5 AK |
184 | #include <trace/events/kvm.h> |
185 | ||
49fde340 XG |
186 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
187 | #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1)) | |
1403283a | 188 | |
135f8c2b AK |
189 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
190 | ||
220f773a TY |
191 | /* make pte_list_desc fit well in cache line */ |
192 | #define PTE_LIST_EXT 3 | |
193 | ||
9b8ebbdb PB |
194 | /* |
195 | * Return values of handle_mmio_page_fault and mmu.page_fault: | |
196 | * RET_PF_RETRY: let CPU fault again on the address. | |
197 | * RET_PF_EMULATE: mmio page fault, emulate the instruction directly. | |
198 | * | |
199 | * For handle_mmio_page_fault only: | |
200 | * RET_PF_INVALID: the spte is invalid, let the real page fault path update it. | |
201 | */ | |
202 | enum { | |
203 | RET_PF_RETRY = 0, | |
204 | RET_PF_EMULATE = 1, | |
205 | RET_PF_INVALID = 2, | |
206 | }; | |
207 | ||
53c07b18 XG |
208 | struct pte_list_desc { |
209 | u64 *sptes[PTE_LIST_EXT]; | |
210 | struct pte_list_desc *more; | |
cd4a4e53 AK |
211 | }; |
212 | ||
2d11123a AK |
213 | struct kvm_shadow_walk_iterator { |
214 | u64 addr; | |
215 | hpa_t shadow_addr; | |
2d11123a | 216 | u64 *sptep; |
dd3bfd59 | 217 | int level; |
2d11123a AK |
218 | unsigned index; |
219 | }; | |
220 | ||
7eb77e9f JS |
221 | #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \ |
222 | for (shadow_walk_init_using_root(&(_walker), (_vcpu), \ | |
223 | (_root), (_addr)); \ | |
224 | shadow_walk_okay(&(_walker)); \ | |
225 | shadow_walk_next(&(_walker))) | |
226 | ||
227 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
2d11123a AK |
228 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ |
229 | shadow_walk_okay(&(_walker)); \ | |
230 | shadow_walk_next(&(_walker))) | |
231 | ||
c2a2ac2b XG |
232 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
233 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
234 | shadow_walk_okay(&(_walker)) && \ | |
235 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
236 | __shadow_walk_next(&(_walker), spte)) | |
237 | ||
53c07b18 | 238 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 239 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 240 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 241 | |
7b52345e SY |
242 | static u64 __read_mostly shadow_nx_mask; |
243 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
244 | static u64 __read_mostly shadow_user_mask; | |
245 | static u64 __read_mostly shadow_accessed_mask; | |
246 | static u64 __read_mostly shadow_dirty_mask; | |
ce88decf | 247 | static u64 __read_mostly shadow_mmio_mask; |
dcdca5fe | 248 | static u64 __read_mostly shadow_mmio_value; |
4af77151 | 249 | static u64 __read_mostly shadow_mmio_access_mask; |
ffb128c8 | 250 | static u64 __read_mostly shadow_present_mask; |
d0ec49d4 | 251 | static u64 __read_mostly shadow_me_mask; |
ce88decf | 252 | |
f160c7b7 | 253 | /* |
6eeb4ef0 PB |
254 | * SPTEs used by MMUs without A/D bits are marked with SPTE_AD_DISABLED_MASK; |
255 | * shadow_acc_track_mask is the set of bits to be cleared in non-accessed | |
256 | * pages. | |
f160c7b7 JS |
257 | */ |
258 | static u64 __read_mostly shadow_acc_track_mask; | |
f160c7b7 JS |
259 | |
260 | /* | |
261 | * The mask/shift to use for saving the original R/X bits when marking the PTE | |
262 | * as not-present for access tracking purposes. We do not save the W bit as the | |
263 | * PTEs being access tracked also need to be dirty tracked, so the W bit will be | |
264 | * restored only when a write is attempted to the page. | |
265 | */ | |
266 | static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK | | |
267 | PT64_EPT_EXECUTABLE_MASK; | |
268 | static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT; | |
269 | ||
28a1f3ac JS |
270 | /* |
271 | * This mask must be set on all non-zero Non-Present or Reserved SPTEs in order | |
272 | * to guard against L1TF attacks. | |
273 | */ | |
274 | static u64 __read_mostly shadow_nonpresent_or_rsvd_mask; | |
275 | ||
276 | /* | |
277 | * The number of high-order 1 bits to use in the mask above. | |
278 | */ | |
279 | static const u64 shadow_nonpresent_or_rsvd_mask_len = 5; | |
280 | ||
daa07cbc SC |
281 | /* |
282 | * In some cases, we need to preserve the GFN of a non-present or reserved | |
283 | * SPTE when we usurp the upper five bits of the physical address space to | |
284 | * defend against L1TF, e.g. for MMIO SPTEs. To preserve the GFN, we'll | |
285 | * shift bits of the GFN that overlap with shadow_nonpresent_or_rsvd_mask | |
286 | * left into the reserved bits, i.e. the GFN in the SPTE will be split into | |
287 | * high and low parts. This mask covers the lower bits of the GFN. | |
288 | */ | |
289 | static u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask; | |
290 | ||
f3ecb59d KH |
291 | /* |
292 | * The number of non-reserved physical address bits irrespective of features | |
293 | * that repurpose legal bits, e.g. MKTME. | |
294 | */ | |
295 | static u8 __read_mostly shadow_phys_bits; | |
daa07cbc | 296 | |
ce88decf | 297 | static void mmu_spte_set(u64 *sptep, u64 spte); |
335e192a | 298 | static bool is_executable_pte(u64 spte); |
9fa72119 JS |
299 | static union kvm_mmu_page_role |
300 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu); | |
ce88decf | 301 | |
335e192a PB |
302 | #define CREATE_TRACE_POINTS |
303 | #include "mmutrace.h" | |
304 | ||
40ef75a7 LT |
305 | |
306 | static inline bool kvm_available_flush_tlb_with_range(void) | |
307 | { | |
afaf0b2f | 308 | return kvm_x86_ops.tlb_remote_flush_with_range; |
40ef75a7 LT |
309 | } |
310 | ||
311 | static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm, | |
312 | struct kvm_tlb_range *range) | |
313 | { | |
314 | int ret = -ENOTSUPP; | |
315 | ||
afaf0b2f SC |
316 | if (range && kvm_x86_ops.tlb_remote_flush_with_range) |
317 | ret = kvm_x86_ops.tlb_remote_flush_with_range(kvm, range); | |
40ef75a7 LT |
318 | |
319 | if (ret) | |
320 | kvm_flush_remote_tlbs(kvm); | |
321 | } | |
322 | ||
323 | static void kvm_flush_remote_tlbs_with_address(struct kvm *kvm, | |
324 | u64 start_gfn, u64 pages) | |
325 | { | |
326 | struct kvm_tlb_range range; | |
327 | ||
328 | range.start_gfn = start_gfn; | |
329 | range.pages = pages; | |
330 | ||
331 | kvm_flush_remote_tlbs_with_range(kvm, &range); | |
332 | } | |
333 | ||
4af77151 | 334 | void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value, u64 access_mask) |
ce88decf | 335 | { |
4af77151 | 336 | BUG_ON((u64)(unsigned)access_mask != access_mask); |
dcdca5fe | 337 | BUG_ON((mmio_mask & mmio_value) != mmio_value); |
6eeb4ef0 | 338 | shadow_mmio_value = mmio_value | SPTE_MMIO_MASK; |
312b616b | 339 | shadow_mmio_mask = mmio_mask | SPTE_SPECIAL_MASK; |
4af77151 | 340 | shadow_mmio_access_mask = access_mask; |
ce88decf XG |
341 | } |
342 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); | |
343 | ||
26c44a63 SC |
344 | static bool is_mmio_spte(u64 spte) |
345 | { | |
346 | return (spte & shadow_mmio_mask) == shadow_mmio_value; | |
347 | } | |
348 | ||
ac8d57e5 PF |
349 | static inline bool sp_ad_disabled(struct kvm_mmu_page *sp) |
350 | { | |
351 | return sp->role.ad_disabled; | |
352 | } | |
353 | ||
1f4e5fc8 PB |
354 | static inline bool kvm_vcpu_ad_need_write_protect(struct kvm_vcpu *vcpu) |
355 | { | |
356 | /* | |
357 | * When using the EPT page-modification log, the GPAs in the log | |
358 | * would come from L2 rather than L1. Therefore, we need to rely | |
359 | * on write protection to record dirty pages. This also bypasses | |
360 | * PML, since writes now result in a vmexit. | |
361 | */ | |
362 | return vcpu->arch.mmu == &vcpu->arch.guest_mmu; | |
363 | } | |
364 | ||
ac8d57e5 PF |
365 | static inline bool spte_ad_enabled(u64 spte) |
366 | { | |
26c44a63 | 367 | MMU_WARN_ON(is_mmio_spte(spte)); |
1f4e5fc8 PB |
368 | return (spte & SPTE_SPECIAL_MASK) != SPTE_AD_DISABLED_MASK; |
369 | } | |
370 | ||
371 | static inline bool spte_ad_need_write_protect(u64 spte) | |
372 | { | |
373 | MMU_WARN_ON(is_mmio_spte(spte)); | |
374 | return (spte & SPTE_SPECIAL_MASK) != SPTE_AD_ENABLED_MASK; | |
ac8d57e5 PF |
375 | } |
376 | ||
b8e8c830 PB |
377 | static bool is_nx_huge_page_enabled(void) |
378 | { | |
379 | return READ_ONCE(nx_huge_pages); | |
380 | } | |
381 | ||
ac8d57e5 PF |
382 | static inline u64 spte_shadow_accessed_mask(u64 spte) |
383 | { | |
26c44a63 | 384 | MMU_WARN_ON(is_mmio_spte(spte)); |
ac8d57e5 PF |
385 | return spte_ad_enabled(spte) ? shadow_accessed_mask : 0; |
386 | } | |
387 | ||
388 | static inline u64 spte_shadow_dirty_mask(u64 spte) | |
389 | { | |
26c44a63 | 390 | MMU_WARN_ON(is_mmio_spte(spte)); |
ac8d57e5 PF |
391 | return spte_ad_enabled(spte) ? shadow_dirty_mask : 0; |
392 | } | |
393 | ||
f160c7b7 JS |
394 | static inline bool is_access_track_spte(u64 spte) |
395 | { | |
ac8d57e5 | 396 | return !spte_ad_enabled(spte) && (spte & shadow_acc_track_mask) == 0; |
f160c7b7 JS |
397 | } |
398 | ||
f2fd125d | 399 | /* |
cae7ed3c SC |
400 | * Due to limited space in PTEs, the MMIO generation is a 19 bit subset of |
401 | * the memslots generation and is derived as follows: | |
ee3d1570 | 402 | * |
164bf7e5 SC |
403 | * Bits 0-8 of the MMIO generation are propagated to spte bits 3-11 |
404 | * Bits 9-18 of the MMIO generation are propagated to spte bits 52-61 | |
cae7ed3c | 405 | * |
164bf7e5 SC |
406 | * The KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS flag is intentionally not included in |
407 | * the MMIO generation number, as doing so would require stealing a bit from | |
408 | * the "real" generation number and thus effectively halve the maximum number | |
409 | * of MMIO generations that can be handled before encountering a wrap (which | |
410 | * requires a full MMU zap). The flag is instead explicitly queried when | |
411 | * checking for MMIO spte cache hits. | |
f2fd125d | 412 | */ |
56871d44 | 413 | #define MMIO_SPTE_GEN_MASK GENMASK_ULL(17, 0) |
f2fd125d | 414 | |
cae7ed3c SC |
415 | #define MMIO_SPTE_GEN_LOW_START 3 |
416 | #define MMIO_SPTE_GEN_LOW_END 11 | |
417 | #define MMIO_SPTE_GEN_LOW_MASK GENMASK_ULL(MMIO_SPTE_GEN_LOW_END, \ | |
418 | MMIO_SPTE_GEN_LOW_START) | |
f2fd125d | 419 | |
56871d44 PB |
420 | #define MMIO_SPTE_GEN_HIGH_START PT64_SECOND_AVAIL_BITS_SHIFT |
421 | #define MMIO_SPTE_GEN_HIGH_END 62 | |
cae7ed3c SC |
422 | #define MMIO_SPTE_GEN_HIGH_MASK GENMASK_ULL(MMIO_SPTE_GEN_HIGH_END, \ |
423 | MMIO_SPTE_GEN_HIGH_START) | |
56871d44 | 424 | |
5192f9b9 | 425 | static u64 generation_mmio_spte_mask(u64 gen) |
f2fd125d XG |
426 | { |
427 | u64 mask; | |
428 | ||
cae7ed3c | 429 | WARN_ON(gen & ~MMIO_SPTE_GEN_MASK); |
56871d44 | 430 | BUILD_BUG_ON((MMIO_SPTE_GEN_HIGH_MASK | MMIO_SPTE_GEN_LOW_MASK) & SPTE_SPECIAL_MASK); |
f2fd125d | 431 | |
cae7ed3c SC |
432 | mask = (gen << MMIO_SPTE_GEN_LOW_START) & MMIO_SPTE_GEN_LOW_MASK; |
433 | mask |= (gen << MMIO_SPTE_GEN_HIGH_START) & MMIO_SPTE_GEN_HIGH_MASK; | |
f2fd125d XG |
434 | return mask; |
435 | } | |
436 | ||
5192f9b9 | 437 | static u64 get_mmio_spte_generation(u64 spte) |
f2fd125d | 438 | { |
5192f9b9 | 439 | u64 gen; |
f2fd125d | 440 | |
cae7ed3c SC |
441 | gen = (spte & MMIO_SPTE_GEN_LOW_MASK) >> MMIO_SPTE_GEN_LOW_START; |
442 | gen |= (spte & MMIO_SPTE_GEN_HIGH_MASK) >> MMIO_SPTE_GEN_HIGH_START; | |
f2fd125d XG |
443 | return gen; |
444 | } | |
445 | ||
8f79b064 | 446 | static u64 make_mmio_spte(struct kvm_vcpu *vcpu, u64 gfn, unsigned int access) |
ce88decf | 447 | { |
8f79b064 | 448 | |
cae7ed3c | 449 | u64 gen = kvm_vcpu_memslots(vcpu)->generation & MMIO_SPTE_GEN_MASK; |
f8f55942 | 450 | u64 mask = generation_mmio_spte_mask(gen); |
28a1f3ac | 451 | u64 gpa = gfn << PAGE_SHIFT; |
95b0430d | 452 | |
4af77151 | 453 | access &= shadow_mmio_access_mask; |
28a1f3ac JS |
454 | mask |= shadow_mmio_value | access; |
455 | mask |= gpa | shadow_nonpresent_or_rsvd_mask; | |
456 | mask |= (gpa & shadow_nonpresent_or_rsvd_mask) | |
457 | << shadow_nonpresent_or_rsvd_mask_len; | |
f2fd125d | 458 | |
8f79b064 BG |
459 | return mask; |
460 | } | |
461 | ||
462 | static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn, | |
463 | unsigned int access) | |
464 | { | |
465 | u64 mask = make_mmio_spte(vcpu, gfn, access); | |
466 | unsigned int gen = get_mmio_spte_generation(mask); | |
467 | ||
468 | access = mask & ACC_ALL; | |
469 | ||
f8f55942 | 470 | trace_mark_mmio_spte(sptep, gfn, access, gen); |
f2fd125d | 471 | mmu_spte_set(sptep, mask); |
ce88decf XG |
472 | } |
473 | ||
ce88decf XG |
474 | static gfn_t get_mmio_spte_gfn(u64 spte) |
475 | { | |
daa07cbc | 476 | u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask; |
28a1f3ac JS |
477 | |
478 | gpa |= (spte >> shadow_nonpresent_or_rsvd_mask_len) | |
479 | & shadow_nonpresent_or_rsvd_mask; | |
480 | ||
481 | return gpa >> PAGE_SHIFT; | |
ce88decf XG |
482 | } |
483 | ||
484 | static unsigned get_mmio_spte_access(u64 spte) | |
485 | { | |
4af77151 | 486 | return spte & shadow_mmio_access_mask; |
ce88decf XG |
487 | } |
488 | ||
54bf36aa | 489 | static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
0a2b64c5 | 490 | kvm_pfn_t pfn, unsigned int access) |
ce88decf XG |
491 | { |
492 | if (unlikely(is_noslot_pfn(pfn))) { | |
54bf36aa | 493 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
494 | return true; |
495 | } | |
496 | ||
497 | return false; | |
498 | } | |
c7addb90 | 499 | |
54bf36aa | 500 | static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte) |
f8f55942 | 501 | { |
cae7ed3c | 502 | u64 kvm_gen, spte_gen, gen; |
089504c0 | 503 | |
cae7ed3c SC |
504 | gen = kvm_vcpu_memslots(vcpu)->generation; |
505 | if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS)) | |
506 | return false; | |
089504c0 | 507 | |
cae7ed3c | 508 | kvm_gen = gen & MMIO_SPTE_GEN_MASK; |
089504c0 XG |
509 | spte_gen = get_mmio_spte_generation(spte); |
510 | ||
511 | trace_check_mmio_spte(spte, kvm_gen, spte_gen); | |
512 | return likely(kvm_gen == spte_gen); | |
f8f55942 XG |
513 | } |
514 | ||
ce00053b PF |
515 | /* |
516 | * Sets the shadow PTE masks used by the MMU. | |
517 | * | |
518 | * Assumptions: | |
519 | * - Setting either @accessed_mask or @dirty_mask requires setting both | |
520 | * - At least one of @accessed_mask or @acc_track_mask must be set | |
521 | */ | |
7b52345e | 522 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
f160c7b7 | 523 | u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask, |
d0ec49d4 | 524 | u64 acc_track_mask, u64 me_mask) |
7b52345e | 525 | { |
ce00053b PF |
526 | BUG_ON(!dirty_mask != !accessed_mask); |
527 | BUG_ON(!accessed_mask && !acc_track_mask); | |
6eeb4ef0 | 528 | BUG_ON(acc_track_mask & SPTE_SPECIAL_MASK); |
312b616b | 529 | |
7b52345e SY |
530 | shadow_user_mask = user_mask; |
531 | shadow_accessed_mask = accessed_mask; | |
532 | shadow_dirty_mask = dirty_mask; | |
533 | shadow_nx_mask = nx_mask; | |
534 | shadow_x_mask = x_mask; | |
ffb128c8 | 535 | shadow_present_mask = p_mask; |
f160c7b7 | 536 | shadow_acc_track_mask = acc_track_mask; |
d0ec49d4 | 537 | shadow_me_mask = me_mask; |
7b52345e SY |
538 | } |
539 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
540 | ||
f3ecb59d KH |
541 | static u8 kvm_get_shadow_phys_bits(void) |
542 | { | |
543 | /* | |
7adacf5e PB |
544 | * boot_cpu_data.x86_phys_bits is reduced when MKTME or SME are detected |
545 | * in CPU detection code, but the processor treats those reduced bits as | |
546 | * 'keyID' thus they are not reserved bits. Therefore KVM needs to look at | |
547 | * the physical address bits reported by CPUID. | |
f3ecb59d | 548 | */ |
7adacf5e PB |
549 | if (likely(boot_cpu_data.extended_cpuid_level >= 0x80000008)) |
550 | return cpuid_eax(0x80000008) & 0xff; | |
f3ecb59d | 551 | |
7adacf5e PB |
552 | /* |
553 | * Quite weird to have VMX or SVM but not MAXPHYADDR; probably a VM with | |
554 | * custom CPUID. Proceed with whatever the kernel found since these features | |
555 | * aren't virtualizable (SME/SEV also require CPUIDs higher than 0x80000008). | |
556 | */ | |
557 | return boot_cpu_data.x86_phys_bits; | |
f3ecb59d KH |
558 | } |
559 | ||
28a1f3ac | 560 | static void kvm_mmu_reset_all_pte_masks(void) |
f160c7b7 | 561 | { |
daa07cbc SC |
562 | u8 low_phys_bits; |
563 | ||
f160c7b7 JS |
564 | shadow_user_mask = 0; |
565 | shadow_accessed_mask = 0; | |
566 | shadow_dirty_mask = 0; | |
567 | shadow_nx_mask = 0; | |
568 | shadow_x_mask = 0; | |
569 | shadow_mmio_mask = 0; | |
570 | shadow_present_mask = 0; | |
571 | shadow_acc_track_mask = 0; | |
28a1f3ac | 572 | |
f3ecb59d KH |
573 | shadow_phys_bits = kvm_get_shadow_phys_bits(); |
574 | ||
28a1f3ac JS |
575 | /* |
576 | * If the CPU has 46 or less physical address bits, then set an | |
577 | * appropriate mask to guard against L1TF attacks. Otherwise, it is | |
578 | * assumed that the CPU is not vulnerable to L1TF. | |
61455bf2 KH |
579 | * |
580 | * Some Intel CPUs address the L1 cache using more PA bits than are | |
581 | * reported by CPUID. Use the PA width of the L1 cache when possible | |
582 | * to achieve more effective mitigation, e.g. if system RAM overlaps | |
583 | * the most significant bits of legal physical address space. | |
28a1f3ac | 584 | */ |
61455bf2 KH |
585 | shadow_nonpresent_or_rsvd_mask = 0; |
586 | low_phys_bits = boot_cpu_data.x86_cache_bits; | |
587 | if (boot_cpu_data.x86_cache_bits < | |
daa07cbc | 588 | 52 - shadow_nonpresent_or_rsvd_mask_len) { |
28a1f3ac | 589 | shadow_nonpresent_or_rsvd_mask = |
61455bf2 | 590 | rsvd_bits(boot_cpu_data.x86_cache_bits - |
28a1f3ac | 591 | shadow_nonpresent_or_rsvd_mask_len, |
61455bf2 | 592 | boot_cpu_data.x86_cache_bits - 1); |
daa07cbc | 593 | low_phys_bits -= shadow_nonpresent_or_rsvd_mask_len; |
61455bf2 KH |
594 | } else |
595 | WARN_ON_ONCE(boot_cpu_has_bug(X86_BUG_L1TF)); | |
596 | ||
daa07cbc SC |
597 | shadow_nonpresent_or_rsvd_lower_gfn_mask = |
598 | GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT); | |
f160c7b7 JS |
599 | } |
600 | ||
6aa8b732 AK |
601 | static int is_cpuid_PSE36(void) |
602 | { | |
603 | return 1; | |
604 | } | |
605 | ||
73b1087e AK |
606 | static int is_nx(struct kvm_vcpu *vcpu) |
607 | { | |
f6801dff | 608 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
609 | } |
610 | ||
c7addb90 AK |
611 | static int is_shadow_present_pte(u64 pte) |
612 | { | |
f160c7b7 | 613 | return (pte != 0) && !is_mmio_spte(pte); |
c7addb90 AK |
614 | } |
615 | ||
05da4558 MT |
616 | static int is_large_pte(u64 pte) |
617 | { | |
618 | return pte & PT_PAGE_SIZE_MASK; | |
619 | } | |
620 | ||
776e6633 MT |
621 | static int is_last_spte(u64 pte, int level) |
622 | { | |
623 | if (level == PT_PAGE_TABLE_LEVEL) | |
624 | return 1; | |
852e3c19 | 625 | if (is_large_pte(pte)) |
776e6633 MT |
626 | return 1; |
627 | return 0; | |
628 | } | |
629 | ||
d3e328f2 JS |
630 | static bool is_executable_pte(u64 spte) |
631 | { | |
632 | return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask; | |
633 | } | |
634 | ||
ba049e93 | 635 | static kvm_pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 636 | { |
35149e21 | 637 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
638 | } |
639 | ||
da928521 AK |
640 | static gfn_t pse36_gfn_delta(u32 gpte) |
641 | { | |
642 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
643 | ||
644 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
645 | } | |
646 | ||
603e0651 | 647 | #ifdef CONFIG_X86_64 |
d555c333 | 648 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 649 | { |
b19ee2ff | 650 | WRITE_ONCE(*sptep, spte); |
e663ee64 AK |
651 | } |
652 | ||
603e0651 | 653 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 654 | { |
b19ee2ff | 655 | WRITE_ONCE(*sptep, spte); |
603e0651 XG |
656 | } |
657 | ||
658 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
659 | { | |
660 | return xchg(sptep, spte); | |
661 | } | |
c2a2ac2b XG |
662 | |
663 | static u64 __get_spte_lockless(u64 *sptep) | |
664 | { | |
6aa7de05 | 665 | return READ_ONCE(*sptep); |
c2a2ac2b | 666 | } |
a9221dd5 | 667 | #else |
603e0651 XG |
668 | union split_spte { |
669 | struct { | |
670 | u32 spte_low; | |
671 | u32 spte_high; | |
672 | }; | |
673 | u64 spte; | |
674 | }; | |
a9221dd5 | 675 | |
c2a2ac2b XG |
676 | static void count_spte_clear(u64 *sptep, u64 spte) |
677 | { | |
678 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
679 | ||
680 | if (is_shadow_present_pte(spte)) | |
681 | return; | |
682 | ||
683 | /* Ensure the spte is completely set before we increase the count */ | |
684 | smp_wmb(); | |
685 | sp->clear_spte_count++; | |
686 | } | |
687 | ||
603e0651 XG |
688 | static void __set_spte(u64 *sptep, u64 spte) |
689 | { | |
690 | union split_spte *ssptep, sspte; | |
a9221dd5 | 691 | |
603e0651 XG |
692 | ssptep = (union split_spte *)sptep; |
693 | sspte = (union split_spte)spte; | |
694 | ||
695 | ssptep->spte_high = sspte.spte_high; | |
696 | ||
697 | /* | |
698 | * If we map the spte from nonpresent to present, We should store | |
699 | * the high bits firstly, then set present bit, so cpu can not | |
700 | * fetch this spte while we are setting the spte. | |
701 | */ | |
702 | smp_wmb(); | |
703 | ||
b19ee2ff | 704 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
a9221dd5 AK |
705 | } |
706 | ||
603e0651 XG |
707 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
708 | { | |
709 | union split_spte *ssptep, sspte; | |
710 | ||
711 | ssptep = (union split_spte *)sptep; | |
712 | sspte = (union split_spte)spte; | |
713 | ||
b19ee2ff | 714 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
603e0651 XG |
715 | |
716 | /* | |
717 | * If we map the spte from present to nonpresent, we should clear | |
718 | * present bit firstly to avoid vcpu fetch the old high bits. | |
719 | */ | |
720 | smp_wmb(); | |
721 | ||
722 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 723 | count_spte_clear(sptep, spte); |
603e0651 XG |
724 | } |
725 | ||
726 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
727 | { | |
728 | union split_spte *ssptep, sspte, orig; | |
729 | ||
730 | ssptep = (union split_spte *)sptep; | |
731 | sspte = (union split_spte)spte; | |
732 | ||
733 | /* xchg acts as a barrier before the setting of the high bits */ | |
734 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
735 | orig.spte_high = ssptep->spte_high; |
736 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 737 | count_spte_clear(sptep, spte); |
603e0651 XG |
738 | |
739 | return orig.spte; | |
740 | } | |
c2a2ac2b XG |
741 | |
742 | /* | |
743 | * The idea using the light way get the spte on x86_32 guest is from | |
39656e83 | 744 | * gup_get_pte (mm/gup.c). |
accaefe0 XG |
745 | * |
746 | * An spte tlb flush may be pending, because kvm_set_pte_rmapp | |
747 | * coalesces them and we are running out of the MMU lock. Therefore | |
748 | * we need to protect against in-progress updates of the spte. | |
749 | * | |
750 | * Reading the spte while an update is in progress may get the old value | |
751 | * for the high part of the spte. The race is fine for a present->non-present | |
752 | * change (because the high part of the spte is ignored for non-present spte), | |
753 | * but for a present->present change we must reread the spte. | |
754 | * | |
755 | * All such changes are done in two steps (present->non-present and | |
756 | * non-present->present), hence it is enough to count the number of | |
757 | * present->non-present updates: if it changed while reading the spte, | |
758 | * we might have hit the race. This is done using clear_spte_count. | |
c2a2ac2b XG |
759 | */ |
760 | static u64 __get_spte_lockless(u64 *sptep) | |
761 | { | |
762 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
763 | union split_spte spte, *orig = (union split_spte *)sptep; | |
764 | int count; | |
765 | ||
766 | retry: | |
767 | count = sp->clear_spte_count; | |
768 | smp_rmb(); | |
769 | ||
770 | spte.spte_low = orig->spte_low; | |
771 | smp_rmb(); | |
772 | ||
773 | spte.spte_high = orig->spte_high; | |
774 | smp_rmb(); | |
775 | ||
776 | if (unlikely(spte.spte_low != orig->spte_low || | |
777 | count != sp->clear_spte_count)) | |
778 | goto retry; | |
779 | ||
780 | return spte.spte; | |
781 | } | |
603e0651 XG |
782 | #endif |
783 | ||
ea4114bc | 784 | static bool spte_can_locklessly_be_made_writable(u64 spte) |
c7ba5b48 | 785 | { |
feb3eb70 GN |
786 | return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) == |
787 | (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE); | |
c7ba5b48 XG |
788 | } |
789 | ||
8672b721 XG |
790 | static bool spte_has_volatile_bits(u64 spte) |
791 | { | |
f160c7b7 JS |
792 | if (!is_shadow_present_pte(spte)) |
793 | return false; | |
794 | ||
c7ba5b48 | 795 | /* |
6a6256f9 | 796 | * Always atomically update spte if it can be updated |
c7ba5b48 XG |
797 | * out of mmu-lock, it can ensure dirty bit is not lost, |
798 | * also, it can help us to get a stable is_writable_pte() | |
799 | * to ensure tlb flush is not missed. | |
800 | */ | |
f160c7b7 JS |
801 | if (spte_can_locklessly_be_made_writable(spte) || |
802 | is_access_track_spte(spte)) | |
c7ba5b48 XG |
803 | return true; |
804 | ||
ac8d57e5 | 805 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
806 | if ((spte & shadow_accessed_mask) == 0 || |
807 | (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0)) | |
808 | return true; | |
809 | } | |
8672b721 | 810 | |
f160c7b7 | 811 | return false; |
8672b721 XG |
812 | } |
813 | ||
83ef6c81 | 814 | static bool is_accessed_spte(u64 spte) |
4132779b | 815 | { |
ac8d57e5 PF |
816 | u64 accessed_mask = spte_shadow_accessed_mask(spte); |
817 | ||
818 | return accessed_mask ? spte & accessed_mask | |
819 | : !is_access_track_spte(spte); | |
4132779b XG |
820 | } |
821 | ||
83ef6c81 | 822 | static bool is_dirty_spte(u64 spte) |
7e71a59b | 823 | { |
ac8d57e5 PF |
824 | u64 dirty_mask = spte_shadow_dirty_mask(spte); |
825 | ||
826 | return dirty_mask ? spte & dirty_mask : spte & PT_WRITABLE_MASK; | |
7e71a59b KH |
827 | } |
828 | ||
1df9f2dc XG |
829 | /* Rules for using mmu_spte_set: |
830 | * Set the sptep from nonpresent to present. | |
831 | * Note: the sptep being assigned *must* be either not present | |
832 | * or in a state where the hardware will not attempt to update | |
833 | * the spte. | |
834 | */ | |
835 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
836 | { | |
837 | WARN_ON(is_shadow_present_pte(*sptep)); | |
838 | __set_spte(sptep, new_spte); | |
839 | } | |
840 | ||
f39a058d JS |
841 | /* |
842 | * Update the SPTE (excluding the PFN), but do not track changes in its | |
843 | * accessed/dirty status. | |
1df9f2dc | 844 | */ |
f39a058d | 845 | static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte) |
b79b93f9 | 846 | { |
c7ba5b48 | 847 | u64 old_spte = *sptep; |
4132779b | 848 | |
afd28fe1 | 849 | WARN_ON(!is_shadow_present_pte(new_spte)); |
b79b93f9 | 850 | |
6e7d0354 XG |
851 | if (!is_shadow_present_pte(old_spte)) { |
852 | mmu_spte_set(sptep, new_spte); | |
f39a058d | 853 | return old_spte; |
6e7d0354 | 854 | } |
4132779b | 855 | |
c7ba5b48 | 856 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 857 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 858 | else |
603e0651 | 859 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 860 | |
83ef6c81 JS |
861 | WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte)); |
862 | ||
f39a058d JS |
863 | return old_spte; |
864 | } | |
865 | ||
866 | /* Rules for using mmu_spte_update: | |
867 | * Update the state bits, it means the mapped pfn is not changed. | |
868 | * | |
869 | * Whenever we overwrite a writable spte with a read-only one we | |
870 | * should flush remote TLBs. Otherwise rmap_write_protect | |
871 | * will find a read-only spte, even though the writable spte | |
872 | * might be cached on a CPU's TLB, the return value indicates this | |
873 | * case. | |
874 | * | |
875 | * Returns true if the TLB needs to be flushed | |
876 | */ | |
877 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) | |
878 | { | |
879 | bool flush = false; | |
880 | u64 old_spte = mmu_spte_update_no_track(sptep, new_spte); | |
881 | ||
882 | if (!is_shadow_present_pte(old_spte)) | |
883 | return false; | |
884 | ||
c7ba5b48 XG |
885 | /* |
886 | * For the spte updated out of mmu-lock is safe, since | |
6a6256f9 | 887 | * we always atomically update it, see the comments in |
c7ba5b48 XG |
888 | * spte_has_volatile_bits(). |
889 | */ | |
ea4114bc | 890 | if (spte_can_locklessly_be_made_writable(old_spte) && |
7f31c959 | 891 | !is_writable_pte(new_spte)) |
83ef6c81 | 892 | flush = true; |
4132779b | 893 | |
7e71a59b | 894 | /* |
83ef6c81 | 895 | * Flush TLB when accessed/dirty states are changed in the page tables, |
7e71a59b KH |
896 | * to guarantee consistency between TLB and page tables. |
897 | */ | |
7e71a59b | 898 | |
83ef6c81 JS |
899 | if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) { |
900 | flush = true; | |
4132779b | 901 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); |
83ef6c81 JS |
902 | } |
903 | ||
904 | if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) { | |
905 | flush = true; | |
4132779b | 906 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); |
83ef6c81 | 907 | } |
6e7d0354 | 908 | |
83ef6c81 | 909 | return flush; |
b79b93f9 AK |
910 | } |
911 | ||
1df9f2dc XG |
912 | /* |
913 | * Rules for using mmu_spte_clear_track_bits: | |
914 | * It sets the sptep from present to nonpresent, and track the | |
915 | * state bits, it is used to clear the last level sptep. | |
83ef6c81 | 916 | * Returns non-zero if the PTE was previously valid. |
1df9f2dc XG |
917 | */ |
918 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
919 | { | |
ba049e93 | 920 | kvm_pfn_t pfn; |
1df9f2dc XG |
921 | u64 old_spte = *sptep; |
922 | ||
923 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 924 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 925 | else |
603e0651 | 926 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc | 927 | |
afd28fe1 | 928 | if (!is_shadow_present_pte(old_spte)) |
1df9f2dc XG |
929 | return 0; |
930 | ||
931 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
932 | |
933 | /* | |
934 | * KVM does not hold the refcount of the page used by | |
935 | * kvm mmu, before reclaiming the page, we should | |
936 | * unmap it from mmu first. | |
937 | */ | |
bf4bea8e | 938 | WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn))); |
86fde74c | 939 | |
83ef6c81 | 940 | if (is_accessed_spte(old_spte)) |
1df9f2dc | 941 | kvm_set_pfn_accessed(pfn); |
83ef6c81 JS |
942 | |
943 | if (is_dirty_spte(old_spte)) | |
1df9f2dc | 944 | kvm_set_pfn_dirty(pfn); |
83ef6c81 | 945 | |
1df9f2dc XG |
946 | return 1; |
947 | } | |
948 | ||
949 | /* | |
950 | * Rules for using mmu_spte_clear_no_track: | |
951 | * Directly clear spte without caring the state bits of sptep, | |
952 | * it is used to set the upper level spte. | |
953 | */ | |
954 | static void mmu_spte_clear_no_track(u64 *sptep) | |
955 | { | |
603e0651 | 956 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
957 | } |
958 | ||
c2a2ac2b XG |
959 | static u64 mmu_spte_get_lockless(u64 *sptep) |
960 | { | |
961 | return __get_spte_lockless(sptep); | |
962 | } | |
963 | ||
f160c7b7 JS |
964 | static u64 mark_spte_for_access_track(u64 spte) |
965 | { | |
ac8d57e5 | 966 | if (spte_ad_enabled(spte)) |
f160c7b7 JS |
967 | return spte & ~shadow_accessed_mask; |
968 | ||
ac8d57e5 | 969 | if (is_access_track_spte(spte)) |
f160c7b7 JS |
970 | return spte; |
971 | ||
972 | /* | |
20d65236 JS |
973 | * Making an Access Tracking PTE will result in removal of write access |
974 | * from the PTE. So, verify that we will be able to restore the write | |
975 | * access in the fast page fault path later on. | |
f160c7b7 JS |
976 | */ |
977 | WARN_ONCE((spte & PT_WRITABLE_MASK) && | |
978 | !spte_can_locklessly_be_made_writable(spte), | |
979 | "kvm: Writable SPTE is not locklessly dirty-trackable\n"); | |
980 | ||
981 | WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask << | |
982 | shadow_acc_track_saved_bits_shift), | |
983 | "kvm: Access Tracking saved bit locations are not zero\n"); | |
984 | ||
985 | spte |= (spte & shadow_acc_track_saved_bits_mask) << | |
986 | shadow_acc_track_saved_bits_shift; | |
987 | spte &= ~shadow_acc_track_mask; | |
f160c7b7 JS |
988 | |
989 | return spte; | |
990 | } | |
991 | ||
d3e328f2 JS |
992 | /* Restore an acc-track PTE back to a regular PTE */ |
993 | static u64 restore_acc_track_spte(u64 spte) | |
994 | { | |
995 | u64 new_spte = spte; | |
996 | u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift) | |
997 | & shadow_acc_track_saved_bits_mask; | |
998 | ||
ac8d57e5 | 999 | WARN_ON_ONCE(spte_ad_enabled(spte)); |
d3e328f2 JS |
1000 | WARN_ON_ONCE(!is_access_track_spte(spte)); |
1001 | ||
1002 | new_spte &= ~shadow_acc_track_mask; | |
1003 | new_spte &= ~(shadow_acc_track_saved_bits_mask << | |
1004 | shadow_acc_track_saved_bits_shift); | |
1005 | new_spte |= saved_bits; | |
1006 | ||
1007 | return new_spte; | |
1008 | } | |
1009 | ||
f160c7b7 JS |
1010 | /* Returns the Accessed status of the PTE and resets it at the same time. */ |
1011 | static bool mmu_spte_age(u64 *sptep) | |
1012 | { | |
1013 | u64 spte = mmu_spte_get_lockless(sptep); | |
1014 | ||
1015 | if (!is_accessed_spte(spte)) | |
1016 | return false; | |
1017 | ||
ac8d57e5 | 1018 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
1019 | clear_bit((ffs(shadow_accessed_mask) - 1), |
1020 | (unsigned long *)sptep); | |
1021 | } else { | |
1022 | /* | |
1023 | * Capture the dirty status of the page, so that it doesn't get | |
1024 | * lost when the SPTE is marked for access tracking. | |
1025 | */ | |
1026 | if (is_writable_pte(spte)) | |
1027 | kvm_set_pfn_dirty(spte_to_pfn(spte)); | |
1028 | ||
1029 | spte = mark_spte_for_access_track(spte); | |
1030 | mmu_spte_update_no_track(sptep, spte); | |
1031 | } | |
1032 | ||
1033 | return true; | |
1034 | } | |
1035 | ||
c2a2ac2b XG |
1036 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) |
1037 | { | |
c142786c AK |
1038 | /* |
1039 | * Prevent page table teardown by making any free-er wait during | |
1040 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
1041 | */ | |
1042 | local_irq_disable(); | |
36ca7e0a | 1043 | |
c142786c AK |
1044 | /* |
1045 | * Make sure a following spte read is not reordered ahead of the write | |
1046 | * to vcpu->mode. | |
1047 | */ | |
36ca7e0a | 1048 | smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES); |
c2a2ac2b XG |
1049 | } |
1050 | ||
1051 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
1052 | { | |
c142786c AK |
1053 | /* |
1054 | * Make sure the write to vcpu->mode is not reordered in front of | |
9a984586 | 1055 | * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us |
c142786c AK |
1056 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. |
1057 | */ | |
36ca7e0a | 1058 | smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE); |
c142786c | 1059 | local_irq_enable(); |
c2a2ac2b XG |
1060 | } |
1061 | ||
e2dec939 | 1062 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 1063 | struct kmem_cache *base_cache, int min) |
714b93da AK |
1064 | { |
1065 | void *obj; | |
1066 | ||
1067 | if (cache->nobjs >= min) | |
e2dec939 | 1068 | return 0; |
714b93da | 1069 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
254272ce | 1070 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL_ACCOUNT); |
714b93da | 1071 | if (!obj) |
daefb794 | 1072 | return cache->nobjs >= min ? 0 : -ENOMEM; |
714b93da AK |
1073 | cache->objects[cache->nobjs++] = obj; |
1074 | } | |
e2dec939 | 1075 | return 0; |
714b93da AK |
1076 | } |
1077 | ||
f759e2b4 XG |
1078 | static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache) |
1079 | { | |
1080 | return cache->nobjs; | |
1081 | } | |
1082 | ||
e8ad9a70 XG |
1083 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
1084 | struct kmem_cache *cache) | |
714b93da AK |
1085 | { |
1086 | while (mc->nobjs) | |
e8ad9a70 | 1087 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
1088 | } |
1089 | ||
c1158e63 | 1090 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 1091 | int min) |
c1158e63 | 1092 | { |
842f22ed | 1093 | void *page; |
c1158e63 AK |
1094 | |
1095 | if (cache->nobjs >= min) | |
1096 | return 0; | |
1097 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
d97e5e61 | 1098 | page = (void *)__get_free_page(GFP_KERNEL_ACCOUNT); |
c1158e63 | 1099 | if (!page) |
daefb794 | 1100 | return cache->nobjs >= min ? 0 : -ENOMEM; |
842f22ed | 1101 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
1102 | } |
1103 | return 0; | |
1104 | } | |
1105 | ||
1106 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
1107 | { | |
1108 | while (mc->nobjs) | |
c4d198d5 | 1109 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
1110 | } |
1111 | ||
2e3e5882 | 1112 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 1113 | { |
e2dec939 AK |
1114 | int r; |
1115 | ||
53c07b18 | 1116 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 1117 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
1118 | if (r) |
1119 | goto out; | |
ad312c7c | 1120 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
1121 | if (r) |
1122 | goto out; | |
ad312c7c | 1123 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 1124 | mmu_page_header_cache, 4); |
e2dec939 AK |
1125 | out: |
1126 | return r; | |
714b93da AK |
1127 | } |
1128 | ||
1129 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
1130 | { | |
53c07b18 XG |
1131 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
1132 | pte_list_desc_cache); | |
ad312c7c | 1133 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
1134 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
1135 | mmu_page_header_cache); | |
714b93da AK |
1136 | } |
1137 | ||
80feb89a | 1138 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) |
714b93da AK |
1139 | { |
1140 | void *p; | |
1141 | ||
1142 | BUG_ON(!mc->nobjs); | |
1143 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
1144 | return p; |
1145 | } | |
1146 | ||
53c07b18 | 1147 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 1148 | { |
80feb89a | 1149 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
1150 | } |
1151 | ||
53c07b18 | 1152 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 1153 | { |
53c07b18 | 1154 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
1155 | } |
1156 | ||
2032a93d LJ |
1157 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
1158 | { | |
1159 | if (!sp->role.direct) | |
1160 | return sp->gfns[index]; | |
1161 | ||
1162 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
1163 | } | |
1164 | ||
1165 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
1166 | { | |
e9f2a760 | 1167 | if (!sp->role.direct) { |
2032a93d | 1168 | sp->gfns[index] = gfn; |
e9f2a760 PB |
1169 | return; |
1170 | } | |
1171 | ||
1172 | if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index))) | |
1173 | pr_err_ratelimited("gfn mismatch under direct page %llx " | |
1174 | "(expected %llx, got %llx)\n", | |
1175 | sp->gfn, | |
1176 | kvm_mmu_page_get_gfn(sp, index), gfn); | |
2032a93d LJ |
1177 | } |
1178 | ||
05da4558 | 1179 | /* |
d4dbf470 TY |
1180 | * Return the pointer to the large page information for a given gfn, |
1181 | * handling slots that are not large page aligned. | |
05da4558 | 1182 | */ |
d4dbf470 TY |
1183 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
1184 | struct kvm_memory_slot *slot, | |
1185 | int level) | |
05da4558 MT |
1186 | { |
1187 | unsigned long idx; | |
1188 | ||
fb03cb6f | 1189 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 1190 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
1191 | } |
1192 | ||
547ffaed XG |
1193 | static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot, |
1194 | gfn_t gfn, int count) | |
1195 | { | |
1196 | struct kvm_lpage_info *linfo; | |
1197 | int i; | |
1198 | ||
1199 | for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { | |
1200 | linfo = lpage_info_slot(gfn, slot, i); | |
1201 | linfo->disallow_lpage += count; | |
1202 | WARN_ON(linfo->disallow_lpage < 0); | |
1203 | } | |
1204 | } | |
1205 | ||
1206 | void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
1207 | { | |
1208 | update_gfn_disallow_lpage_count(slot, gfn, 1); | |
1209 | } | |
1210 | ||
1211 | void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
1212 | { | |
1213 | update_gfn_disallow_lpage_count(slot, gfn, -1); | |
1214 | } | |
1215 | ||
3ed1a478 | 1216 | static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 1217 | { |
699023e2 | 1218 | struct kvm_memslots *slots; |
d25797b2 | 1219 | struct kvm_memory_slot *slot; |
3ed1a478 | 1220 | gfn_t gfn; |
05da4558 | 1221 | |
56ca57f9 | 1222 | kvm->arch.indirect_shadow_pages++; |
3ed1a478 | 1223 | gfn = sp->gfn; |
699023e2 PB |
1224 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1225 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
1226 | |
1227 | /* the non-leaf shadow pages are keeping readonly. */ | |
1228 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
1229 | return kvm_slot_page_track_add_page(kvm, slot, gfn, | |
1230 | KVM_PAGE_TRACK_WRITE); | |
1231 | ||
547ffaed | 1232 | kvm_mmu_gfn_disallow_lpage(slot, gfn); |
05da4558 MT |
1233 | } |
1234 | ||
b8e8c830 PB |
1235 | static void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1236 | { | |
1237 | if (sp->lpage_disallowed) | |
1238 | return; | |
1239 | ||
1240 | ++kvm->stat.nx_lpage_splits; | |
1aa9b957 JS |
1241 | list_add_tail(&sp->lpage_disallowed_link, |
1242 | &kvm->arch.lpage_disallowed_mmu_pages); | |
b8e8c830 PB |
1243 | sp->lpage_disallowed = true; |
1244 | } | |
1245 | ||
3ed1a478 | 1246 | static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 1247 | { |
699023e2 | 1248 | struct kvm_memslots *slots; |
d25797b2 | 1249 | struct kvm_memory_slot *slot; |
3ed1a478 | 1250 | gfn_t gfn; |
05da4558 | 1251 | |
56ca57f9 | 1252 | kvm->arch.indirect_shadow_pages--; |
3ed1a478 | 1253 | gfn = sp->gfn; |
699023e2 PB |
1254 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1255 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
1256 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
1257 | return kvm_slot_page_track_remove_page(kvm, slot, gfn, | |
1258 | KVM_PAGE_TRACK_WRITE); | |
1259 | ||
547ffaed | 1260 | kvm_mmu_gfn_allow_lpage(slot, gfn); |
05da4558 MT |
1261 | } |
1262 | ||
b8e8c830 PB |
1263 | static void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1264 | { | |
1265 | --kvm->stat.nx_lpage_splits; | |
1266 | sp->lpage_disallowed = false; | |
1aa9b957 | 1267 | list_del(&sp->lpage_disallowed_link); |
b8e8c830 PB |
1268 | } |
1269 | ||
5d163b1c XG |
1270 | static struct kvm_memory_slot * |
1271 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
1272 | bool no_dirty_log) | |
05da4558 MT |
1273 | { |
1274 | struct kvm_memory_slot *slot; | |
5d163b1c | 1275 | |
54bf36aa | 1276 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
91b0d268 PB |
1277 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID) |
1278 | return NULL; | |
1279 | if (no_dirty_log && slot->dirty_bitmap) | |
1280 | return NULL; | |
5d163b1c XG |
1281 | |
1282 | return slot; | |
1283 | } | |
1284 | ||
290fc38d | 1285 | /* |
018aabb5 | 1286 | * About rmap_head encoding: |
cd4a4e53 | 1287 | * |
018aabb5 TY |
1288 | * If the bit zero of rmap_head->val is clear, then it points to the only spte |
1289 | * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct | |
53c07b18 | 1290 | * pte_list_desc containing more mappings. |
018aabb5 TY |
1291 | */ |
1292 | ||
1293 | /* | |
1294 | * Returns the number of pointers in the rmap chain, not counting the new one. | |
cd4a4e53 | 1295 | */ |
53c07b18 | 1296 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
018aabb5 | 1297 | struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 1298 | { |
53c07b18 | 1299 | struct pte_list_desc *desc; |
53a27b39 | 1300 | int i, count = 0; |
cd4a4e53 | 1301 | |
018aabb5 | 1302 | if (!rmap_head->val) { |
53c07b18 | 1303 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); |
018aabb5 TY |
1304 | rmap_head->val = (unsigned long)spte; |
1305 | } else if (!(rmap_head->val & 1)) { | |
53c07b18 XG |
1306 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); |
1307 | desc = mmu_alloc_pte_list_desc(vcpu); | |
018aabb5 | 1308 | desc->sptes[0] = (u64 *)rmap_head->val; |
d555c333 | 1309 | desc->sptes[1] = spte; |
018aabb5 | 1310 | rmap_head->val = (unsigned long)desc | 1; |
cb16a7b3 | 1311 | ++count; |
cd4a4e53 | 1312 | } else { |
53c07b18 | 1313 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
018aabb5 | 1314 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
53c07b18 | 1315 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { |
cd4a4e53 | 1316 | desc = desc->more; |
53c07b18 | 1317 | count += PTE_LIST_EXT; |
53a27b39 | 1318 | } |
53c07b18 XG |
1319 | if (desc->sptes[PTE_LIST_EXT-1]) { |
1320 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
1321 | desc = desc->more; |
1322 | } | |
d555c333 | 1323 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 1324 | ++count; |
d555c333 | 1325 | desc->sptes[i] = spte; |
cd4a4e53 | 1326 | } |
53a27b39 | 1327 | return count; |
cd4a4e53 AK |
1328 | } |
1329 | ||
53c07b18 | 1330 | static void |
018aabb5 TY |
1331 | pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head, |
1332 | struct pte_list_desc *desc, int i, | |
1333 | struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
1334 | { |
1335 | int j; | |
1336 | ||
53c07b18 | 1337 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 1338 | ; |
d555c333 AK |
1339 | desc->sptes[i] = desc->sptes[j]; |
1340 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
1341 | if (j != 0) |
1342 | return; | |
1343 | if (!prev_desc && !desc->more) | |
fe3c2b4c | 1344 | rmap_head->val = 0; |
cd4a4e53 AK |
1345 | else |
1346 | if (prev_desc) | |
1347 | prev_desc->more = desc->more; | |
1348 | else | |
018aabb5 | 1349 | rmap_head->val = (unsigned long)desc->more | 1; |
53c07b18 | 1350 | mmu_free_pte_list_desc(desc); |
cd4a4e53 AK |
1351 | } |
1352 | ||
8daf3462 | 1353 | static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 1354 | { |
53c07b18 XG |
1355 | struct pte_list_desc *desc; |
1356 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
1357 | int i; |
1358 | ||
018aabb5 | 1359 | if (!rmap_head->val) { |
8daf3462 | 1360 | pr_err("%s: %p 0->BUG\n", __func__, spte); |
cd4a4e53 | 1361 | BUG(); |
018aabb5 | 1362 | } else if (!(rmap_head->val & 1)) { |
8daf3462 | 1363 | rmap_printk("%s: %p 1->0\n", __func__, spte); |
018aabb5 | 1364 | if ((u64 *)rmap_head->val != spte) { |
8daf3462 | 1365 | pr_err("%s: %p 1->BUG\n", __func__, spte); |
cd4a4e53 AK |
1366 | BUG(); |
1367 | } | |
018aabb5 | 1368 | rmap_head->val = 0; |
cd4a4e53 | 1369 | } else { |
8daf3462 | 1370 | rmap_printk("%s: %p many->many\n", __func__, spte); |
018aabb5 | 1371 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
cd4a4e53 AK |
1372 | prev_desc = NULL; |
1373 | while (desc) { | |
018aabb5 | 1374 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) { |
d555c333 | 1375 | if (desc->sptes[i] == spte) { |
018aabb5 TY |
1376 | pte_list_desc_remove_entry(rmap_head, |
1377 | desc, i, prev_desc); | |
cd4a4e53 AK |
1378 | return; |
1379 | } | |
018aabb5 | 1380 | } |
cd4a4e53 AK |
1381 | prev_desc = desc; |
1382 | desc = desc->more; | |
1383 | } | |
8daf3462 | 1384 | pr_err("%s: %p many->many\n", __func__, spte); |
cd4a4e53 AK |
1385 | BUG(); |
1386 | } | |
1387 | } | |
1388 | ||
e7912386 WY |
1389 | static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep) |
1390 | { | |
1391 | mmu_spte_clear_track_bits(sptep); | |
1392 | __pte_list_remove(sptep, rmap_head); | |
1393 | } | |
1394 | ||
018aabb5 TY |
1395 | static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level, |
1396 | struct kvm_memory_slot *slot) | |
53c07b18 | 1397 | { |
77d11309 | 1398 | unsigned long idx; |
53c07b18 | 1399 | |
77d11309 | 1400 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
d89cc617 | 1401 | return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx]; |
53c07b18 XG |
1402 | } |
1403 | ||
018aabb5 TY |
1404 | static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, |
1405 | struct kvm_mmu_page *sp) | |
9b9b1492 | 1406 | { |
699023e2 | 1407 | struct kvm_memslots *slots; |
9b9b1492 TY |
1408 | struct kvm_memory_slot *slot; |
1409 | ||
699023e2 PB |
1410 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1411 | slot = __gfn_to_memslot(slots, gfn); | |
e4cd1da9 | 1412 | return __gfn_to_rmap(gfn, sp->role.level, slot); |
9b9b1492 TY |
1413 | } |
1414 | ||
f759e2b4 XG |
1415 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
1416 | { | |
1417 | struct kvm_mmu_memory_cache *cache; | |
1418 | ||
1419 | cache = &vcpu->arch.mmu_pte_list_desc_cache; | |
1420 | return mmu_memory_cache_free_objects(cache); | |
1421 | } | |
1422 | ||
53c07b18 XG |
1423 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
1424 | { | |
1425 | struct kvm_mmu_page *sp; | |
018aabb5 | 1426 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 1427 | |
53c07b18 XG |
1428 | sp = page_header(__pa(spte)); |
1429 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
018aabb5 TY |
1430 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
1431 | return pte_list_add(vcpu, spte, rmap_head); | |
53c07b18 XG |
1432 | } |
1433 | ||
53c07b18 XG |
1434 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
1435 | { | |
1436 | struct kvm_mmu_page *sp; | |
1437 | gfn_t gfn; | |
018aabb5 | 1438 | struct kvm_rmap_head *rmap_head; |
53c07b18 XG |
1439 | |
1440 | sp = page_header(__pa(spte)); | |
1441 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
018aabb5 | 1442 | rmap_head = gfn_to_rmap(kvm, gfn, sp); |
8daf3462 | 1443 | __pte_list_remove(spte, rmap_head); |
53c07b18 XG |
1444 | } |
1445 | ||
1e3f42f0 TY |
1446 | /* |
1447 | * Used by the following functions to iterate through the sptes linked by a | |
1448 | * rmap. All fields are private and not assumed to be used outside. | |
1449 | */ | |
1450 | struct rmap_iterator { | |
1451 | /* private fields */ | |
1452 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1453 | int pos; /* index of the sptep */ | |
1454 | }; | |
1455 | ||
1456 | /* | |
1457 | * Iteration must be started by this function. This should also be used after | |
1458 | * removing/dropping sptes from the rmap link because in such cases the | |
0a03cbda | 1459 | * information in the iterator may not be valid. |
1e3f42f0 TY |
1460 | * |
1461 | * Returns sptep if found, NULL otherwise. | |
1462 | */ | |
018aabb5 TY |
1463 | static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head, |
1464 | struct rmap_iterator *iter) | |
1e3f42f0 | 1465 | { |
77fbbbd2 TY |
1466 | u64 *sptep; |
1467 | ||
018aabb5 | 1468 | if (!rmap_head->val) |
1e3f42f0 TY |
1469 | return NULL; |
1470 | ||
018aabb5 | 1471 | if (!(rmap_head->val & 1)) { |
1e3f42f0 | 1472 | iter->desc = NULL; |
77fbbbd2 TY |
1473 | sptep = (u64 *)rmap_head->val; |
1474 | goto out; | |
1e3f42f0 TY |
1475 | } |
1476 | ||
018aabb5 | 1477 | iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
1e3f42f0 | 1478 | iter->pos = 0; |
77fbbbd2 TY |
1479 | sptep = iter->desc->sptes[iter->pos]; |
1480 | out: | |
1481 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1482 | return sptep; | |
1e3f42f0 TY |
1483 | } |
1484 | ||
1485 | /* | |
1486 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1487 | * | |
1488 | * Returns sptep if found, NULL otherwise. | |
1489 | */ | |
1490 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1491 | { | |
77fbbbd2 TY |
1492 | u64 *sptep; |
1493 | ||
1e3f42f0 TY |
1494 | if (iter->desc) { |
1495 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1e3f42f0 TY |
1496 | ++iter->pos; |
1497 | sptep = iter->desc->sptes[iter->pos]; | |
1498 | if (sptep) | |
77fbbbd2 | 1499 | goto out; |
1e3f42f0 TY |
1500 | } |
1501 | ||
1502 | iter->desc = iter->desc->more; | |
1503 | ||
1504 | if (iter->desc) { | |
1505 | iter->pos = 0; | |
1506 | /* desc->sptes[0] cannot be NULL */ | |
77fbbbd2 TY |
1507 | sptep = iter->desc->sptes[iter->pos]; |
1508 | goto out; | |
1e3f42f0 TY |
1509 | } |
1510 | } | |
1511 | ||
1512 | return NULL; | |
77fbbbd2 TY |
1513 | out: |
1514 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1515 | return sptep; | |
1e3f42f0 TY |
1516 | } |
1517 | ||
018aabb5 TY |
1518 | #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \ |
1519 | for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \ | |
77fbbbd2 | 1520 | _spte_; _spte_ = rmap_get_next(_iter_)) |
0d536790 | 1521 | |
c3707958 | 1522 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1523 | { |
1df9f2dc | 1524 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1525 | rmap_remove(kvm, sptep); |
be38d276 AK |
1526 | } |
1527 | ||
8e22f955 XG |
1528 | |
1529 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1530 | { | |
1531 | if (is_large_pte(*sptep)) { | |
1532 | WARN_ON(page_header(__pa(sptep))->role.level == | |
1533 | PT_PAGE_TABLE_LEVEL); | |
1534 | drop_spte(kvm, sptep); | |
1535 | --kvm->stat.lpages; | |
1536 | return true; | |
1537 | } | |
1538 | ||
1539 | return false; | |
1540 | } | |
1541 | ||
1542 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1543 | { | |
c3134ce2 LT |
1544 | if (__drop_large_spte(vcpu->kvm, sptep)) { |
1545 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
1546 | ||
1547 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn, | |
1548 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
1549 | } | |
8e22f955 XG |
1550 | } |
1551 | ||
1552 | /* | |
49fde340 | 1553 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
c126d94f | 1554 | * spte write-protection is caused by protecting shadow page table. |
49fde340 | 1555 | * |
b4619660 | 1556 | * Note: write protection is difference between dirty logging and spte |
49fde340 XG |
1557 | * protection: |
1558 | * - for dirty logging, the spte can be set to writable at anytime if | |
1559 | * its dirty bitmap is properly set. | |
1560 | * - for spte protection, the spte can be writable only after unsync-ing | |
1561 | * shadow page. | |
8e22f955 | 1562 | * |
c126d94f | 1563 | * Return true if tlb need be flushed. |
8e22f955 | 1564 | */ |
c4f138b4 | 1565 | static bool spte_write_protect(u64 *sptep, bool pt_protect) |
d13bc5b5 XG |
1566 | { |
1567 | u64 spte = *sptep; | |
1568 | ||
49fde340 | 1569 | if (!is_writable_pte(spte) && |
ea4114bc | 1570 | !(pt_protect && spte_can_locklessly_be_made_writable(spte))) |
d13bc5b5 XG |
1571 | return false; |
1572 | ||
1573 | rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); | |
1574 | ||
49fde340 XG |
1575 | if (pt_protect) |
1576 | spte &= ~SPTE_MMU_WRITEABLE; | |
d13bc5b5 | 1577 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1578 | |
c126d94f | 1579 | return mmu_spte_update(sptep, spte); |
d13bc5b5 XG |
1580 | } |
1581 | ||
018aabb5 TY |
1582 | static bool __rmap_write_protect(struct kvm *kvm, |
1583 | struct kvm_rmap_head *rmap_head, | |
245c3912 | 1584 | bool pt_protect) |
98348e95 | 1585 | { |
1e3f42f0 TY |
1586 | u64 *sptep; |
1587 | struct rmap_iterator iter; | |
d13bc5b5 | 1588 | bool flush = false; |
374cbac0 | 1589 | |
018aabb5 | 1590 | for_each_rmap_spte(rmap_head, &iter, sptep) |
c4f138b4 | 1591 | flush |= spte_write_protect(sptep, pt_protect); |
855149aa | 1592 | |
d13bc5b5 | 1593 | return flush; |
a0ed4607 TY |
1594 | } |
1595 | ||
c4f138b4 | 1596 | static bool spte_clear_dirty(u64 *sptep) |
f4b4b180 KH |
1597 | { |
1598 | u64 spte = *sptep; | |
1599 | ||
1600 | rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep); | |
1601 | ||
1f4e5fc8 | 1602 | MMU_WARN_ON(!spte_ad_enabled(spte)); |
f4b4b180 | 1603 | spte &= ~shadow_dirty_mask; |
f4b4b180 KH |
1604 | return mmu_spte_update(sptep, spte); |
1605 | } | |
1606 | ||
1f4e5fc8 | 1607 | static bool spte_wrprot_for_clear_dirty(u64 *sptep) |
ac8d57e5 PF |
1608 | { |
1609 | bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT, | |
1610 | (unsigned long *)sptep); | |
1f4e5fc8 | 1611 | if (was_writable && !spte_ad_enabled(*sptep)) |
ac8d57e5 PF |
1612 | kvm_set_pfn_dirty(spte_to_pfn(*sptep)); |
1613 | ||
1614 | return was_writable; | |
1615 | } | |
1616 | ||
1617 | /* | |
1618 | * Gets the GFN ready for another round of dirty logging by clearing the | |
1619 | * - D bit on ad-enabled SPTEs, and | |
1620 | * - W bit on ad-disabled SPTEs. | |
1621 | * Returns true iff any D or W bits were cleared. | |
1622 | */ | |
018aabb5 | 1623 | static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1624 | { |
1625 | u64 *sptep; | |
1626 | struct rmap_iterator iter; | |
1627 | bool flush = false; | |
1628 | ||
018aabb5 | 1629 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1f4e5fc8 PB |
1630 | if (spte_ad_need_write_protect(*sptep)) |
1631 | flush |= spte_wrprot_for_clear_dirty(sptep); | |
ac8d57e5 | 1632 | else |
1f4e5fc8 | 1633 | flush |= spte_clear_dirty(sptep); |
f4b4b180 KH |
1634 | |
1635 | return flush; | |
1636 | } | |
1637 | ||
c4f138b4 | 1638 | static bool spte_set_dirty(u64 *sptep) |
f4b4b180 KH |
1639 | { |
1640 | u64 spte = *sptep; | |
1641 | ||
1642 | rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep); | |
1643 | ||
1f4e5fc8 | 1644 | /* |
afaf0b2f | 1645 | * Similar to the !kvm_x86_ops.slot_disable_log_dirty case, |
1f4e5fc8 PB |
1646 | * do not bother adding back write access to pages marked |
1647 | * SPTE_AD_WRPROT_ONLY_MASK. | |
1648 | */ | |
f4b4b180 KH |
1649 | spte |= shadow_dirty_mask; |
1650 | ||
1651 | return mmu_spte_update(sptep, spte); | |
1652 | } | |
1653 | ||
018aabb5 | 1654 | static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1655 | { |
1656 | u64 *sptep; | |
1657 | struct rmap_iterator iter; | |
1658 | bool flush = false; | |
1659 | ||
018aabb5 | 1660 | for_each_rmap_spte(rmap_head, &iter, sptep) |
ac8d57e5 PF |
1661 | if (spte_ad_enabled(*sptep)) |
1662 | flush |= spte_set_dirty(sptep); | |
f4b4b180 KH |
1663 | |
1664 | return flush; | |
1665 | } | |
1666 | ||
5dc99b23 | 1667 | /** |
3b0f1d01 | 1668 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages |
5dc99b23 TY |
1669 | * @kvm: kvm instance |
1670 | * @slot: slot to protect | |
1671 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1672 | * @mask: indicates which pages we should protect | |
1673 | * | |
1674 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1675 | * logging we do not have any such mappings. | |
1676 | */ | |
3b0f1d01 | 1677 | static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
5dc99b23 TY |
1678 | struct kvm_memory_slot *slot, |
1679 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 | 1680 | { |
018aabb5 | 1681 | struct kvm_rmap_head *rmap_head; |
a0ed4607 | 1682 | |
5dc99b23 | 1683 | while (mask) { |
018aabb5 TY |
1684 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1685 | PT_PAGE_TABLE_LEVEL, slot); | |
1686 | __rmap_write_protect(kvm, rmap_head, false); | |
05da4558 | 1687 | |
5dc99b23 TY |
1688 | /* clear the first set bit */ |
1689 | mask &= mask - 1; | |
1690 | } | |
374cbac0 AK |
1691 | } |
1692 | ||
f4b4b180 | 1693 | /** |
ac8d57e5 PF |
1694 | * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write |
1695 | * protect the page if the D-bit isn't supported. | |
f4b4b180 KH |
1696 | * @kvm: kvm instance |
1697 | * @slot: slot to clear D-bit | |
1698 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1699 | * @mask: indicates which pages we should clear D-bit | |
1700 | * | |
1701 | * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap. | |
1702 | */ | |
1703 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
1704 | struct kvm_memory_slot *slot, | |
1705 | gfn_t gfn_offset, unsigned long mask) | |
1706 | { | |
018aabb5 | 1707 | struct kvm_rmap_head *rmap_head; |
f4b4b180 KH |
1708 | |
1709 | while (mask) { | |
018aabb5 TY |
1710 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1711 | PT_PAGE_TABLE_LEVEL, slot); | |
1712 | __rmap_clear_dirty(kvm, rmap_head); | |
f4b4b180 KH |
1713 | |
1714 | /* clear the first set bit */ | |
1715 | mask &= mask - 1; | |
1716 | } | |
1717 | } | |
1718 | EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked); | |
1719 | ||
3b0f1d01 KH |
1720 | /** |
1721 | * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected | |
1722 | * PT level pages. | |
1723 | * | |
1724 | * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to | |
1725 | * enable dirty logging for them. | |
1726 | * | |
1727 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1728 | * logging we do not have any such mappings. | |
1729 | */ | |
1730 | void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, | |
1731 | struct kvm_memory_slot *slot, | |
1732 | gfn_t gfn_offset, unsigned long mask) | |
1733 | { | |
afaf0b2f SC |
1734 | if (kvm_x86_ops.enable_log_dirty_pt_masked) |
1735 | kvm_x86_ops.enable_log_dirty_pt_masked(kvm, slot, gfn_offset, | |
88178fd4 KH |
1736 | mask); |
1737 | else | |
1738 | kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); | |
3b0f1d01 KH |
1739 | } |
1740 | ||
bab4165e BD |
1741 | /** |
1742 | * kvm_arch_write_log_dirty - emulate dirty page logging | |
1743 | * @vcpu: Guest mode vcpu | |
1744 | * | |
1745 | * Emulate arch specific page modification logging for the | |
1746 | * nested hypervisor | |
1747 | */ | |
1748 | int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu) | |
1749 | { | |
afaf0b2f SC |
1750 | if (kvm_x86_ops.write_log_dirty) |
1751 | return kvm_x86_ops.write_log_dirty(vcpu); | |
bab4165e BD |
1752 | |
1753 | return 0; | |
1754 | } | |
1755 | ||
aeecee2e XG |
1756 | bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm, |
1757 | struct kvm_memory_slot *slot, u64 gfn) | |
95d4c16c | 1758 | { |
018aabb5 | 1759 | struct kvm_rmap_head *rmap_head; |
5dc99b23 | 1760 | int i; |
2f84569f | 1761 | bool write_protected = false; |
95d4c16c | 1762 | |
8a3d08f1 | 1763 | for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { |
018aabb5 | 1764 | rmap_head = __gfn_to_rmap(gfn, i, slot); |
aeecee2e | 1765 | write_protected |= __rmap_write_protect(kvm, rmap_head, true); |
5dc99b23 TY |
1766 | } |
1767 | ||
1768 | return write_protected; | |
95d4c16c TY |
1769 | } |
1770 | ||
aeecee2e XG |
1771 | static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn) |
1772 | { | |
1773 | struct kvm_memory_slot *slot; | |
1774 | ||
1775 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
1776 | return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn); | |
1777 | } | |
1778 | ||
018aabb5 | 1779 | static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
e930bffe | 1780 | { |
1e3f42f0 TY |
1781 | u64 *sptep; |
1782 | struct rmap_iterator iter; | |
6a49f85c | 1783 | bool flush = false; |
e930bffe | 1784 | |
018aabb5 | 1785 | while ((sptep = rmap_get_first(rmap_head, &iter))) { |
6a49f85c | 1786 | rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep); |
1e3f42f0 | 1787 | |
e7912386 | 1788 | pte_list_remove(rmap_head, sptep); |
6a49f85c | 1789 | flush = true; |
e930bffe | 1790 | } |
1e3f42f0 | 1791 | |
6a49f85c XG |
1792 | return flush; |
1793 | } | |
1794 | ||
018aabb5 | 1795 | static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
6a49f85c XG |
1796 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1797 | unsigned long data) | |
1798 | { | |
018aabb5 | 1799 | return kvm_zap_rmapp(kvm, rmap_head); |
e930bffe AA |
1800 | } |
1801 | ||
018aabb5 | 1802 | static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1803 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1804 | unsigned long data) | |
3da0dd43 | 1805 | { |
1e3f42f0 TY |
1806 | u64 *sptep; |
1807 | struct rmap_iterator iter; | |
3da0dd43 | 1808 | int need_flush = 0; |
1e3f42f0 | 1809 | u64 new_spte; |
3da0dd43 | 1810 | pte_t *ptep = (pte_t *)data; |
ba049e93 | 1811 | kvm_pfn_t new_pfn; |
3da0dd43 IE |
1812 | |
1813 | WARN_ON(pte_huge(*ptep)); | |
1814 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 | 1815 | |
0d536790 | 1816 | restart: |
018aabb5 | 1817 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
8a9522d2 | 1818 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n", |
f160c7b7 | 1819 | sptep, *sptep, gfn, level); |
1e3f42f0 | 1820 | |
3da0dd43 | 1821 | need_flush = 1; |
1e3f42f0 | 1822 | |
3da0dd43 | 1823 | if (pte_write(*ptep)) { |
e7912386 | 1824 | pte_list_remove(rmap_head, sptep); |
0d536790 | 1825 | goto restart; |
3da0dd43 | 1826 | } else { |
1e3f42f0 | 1827 | new_spte = *sptep & ~PT64_BASE_ADDR_MASK; |
3da0dd43 IE |
1828 | new_spte |= (u64)new_pfn << PAGE_SHIFT; |
1829 | ||
1830 | new_spte &= ~PT_WRITABLE_MASK; | |
1831 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
f160c7b7 JS |
1832 | |
1833 | new_spte = mark_spte_for_access_track(new_spte); | |
1e3f42f0 TY |
1834 | |
1835 | mmu_spte_clear_track_bits(sptep); | |
1836 | mmu_spte_set(sptep, new_spte); | |
3da0dd43 IE |
1837 | } |
1838 | } | |
1e3f42f0 | 1839 | |
3cc5ea94 LT |
1840 | if (need_flush && kvm_available_flush_tlb_with_range()) { |
1841 | kvm_flush_remote_tlbs_with_address(kvm, gfn, 1); | |
1842 | return 0; | |
1843 | } | |
1844 | ||
0cf853c5 | 1845 | return need_flush; |
3da0dd43 IE |
1846 | } |
1847 | ||
6ce1f4e2 XG |
1848 | struct slot_rmap_walk_iterator { |
1849 | /* input fields. */ | |
1850 | struct kvm_memory_slot *slot; | |
1851 | gfn_t start_gfn; | |
1852 | gfn_t end_gfn; | |
1853 | int start_level; | |
1854 | int end_level; | |
1855 | ||
1856 | /* output fields. */ | |
1857 | gfn_t gfn; | |
018aabb5 | 1858 | struct kvm_rmap_head *rmap; |
6ce1f4e2 XG |
1859 | int level; |
1860 | ||
1861 | /* private field. */ | |
018aabb5 | 1862 | struct kvm_rmap_head *end_rmap; |
6ce1f4e2 XG |
1863 | }; |
1864 | ||
1865 | static void | |
1866 | rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level) | |
1867 | { | |
1868 | iterator->level = level; | |
1869 | iterator->gfn = iterator->start_gfn; | |
1870 | iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot); | |
1871 | iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level, | |
1872 | iterator->slot); | |
1873 | } | |
1874 | ||
1875 | static void | |
1876 | slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator, | |
1877 | struct kvm_memory_slot *slot, int start_level, | |
1878 | int end_level, gfn_t start_gfn, gfn_t end_gfn) | |
1879 | { | |
1880 | iterator->slot = slot; | |
1881 | iterator->start_level = start_level; | |
1882 | iterator->end_level = end_level; | |
1883 | iterator->start_gfn = start_gfn; | |
1884 | iterator->end_gfn = end_gfn; | |
1885 | ||
1886 | rmap_walk_init_level(iterator, iterator->start_level); | |
1887 | } | |
1888 | ||
1889 | static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator) | |
1890 | { | |
1891 | return !!iterator->rmap; | |
1892 | } | |
1893 | ||
1894 | static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator) | |
1895 | { | |
1896 | if (++iterator->rmap <= iterator->end_rmap) { | |
1897 | iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level)); | |
1898 | return; | |
1899 | } | |
1900 | ||
1901 | if (++iterator->level > iterator->end_level) { | |
1902 | iterator->rmap = NULL; | |
1903 | return; | |
1904 | } | |
1905 | ||
1906 | rmap_walk_init_level(iterator, iterator->level); | |
1907 | } | |
1908 | ||
1909 | #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \ | |
1910 | _start_gfn, _end_gfn, _iter_) \ | |
1911 | for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \ | |
1912 | _end_level_, _start_gfn, _end_gfn); \ | |
1913 | slot_rmap_walk_okay(_iter_); \ | |
1914 | slot_rmap_walk_next(_iter_)) | |
1915 | ||
84504ef3 TY |
1916 | static int kvm_handle_hva_range(struct kvm *kvm, |
1917 | unsigned long start, | |
1918 | unsigned long end, | |
1919 | unsigned long data, | |
1920 | int (*handler)(struct kvm *kvm, | |
018aabb5 | 1921 | struct kvm_rmap_head *rmap_head, |
048212d0 | 1922 | struct kvm_memory_slot *slot, |
8a9522d2 ALC |
1923 | gfn_t gfn, |
1924 | int level, | |
84504ef3 | 1925 | unsigned long data)) |
e930bffe | 1926 | { |
bc6678a3 | 1927 | struct kvm_memslots *slots; |
be6ba0f0 | 1928 | struct kvm_memory_slot *memslot; |
6ce1f4e2 XG |
1929 | struct slot_rmap_walk_iterator iterator; |
1930 | int ret = 0; | |
9da0e4d5 | 1931 | int i; |
bc6678a3 | 1932 | |
9da0e4d5 PB |
1933 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1934 | slots = __kvm_memslots(kvm, i); | |
1935 | kvm_for_each_memslot(memslot, slots) { | |
1936 | unsigned long hva_start, hva_end; | |
1937 | gfn_t gfn_start, gfn_end; | |
e930bffe | 1938 | |
9da0e4d5 PB |
1939 | hva_start = max(start, memslot->userspace_addr); |
1940 | hva_end = min(end, memslot->userspace_addr + | |
1941 | (memslot->npages << PAGE_SHIFT)); | |
1942 | if (hva_start >= hva_end) | |
1943 | continue; | |
1944 | /* | |
1945 | * {gfn(page) | page intersects with [hva_start, hva_end)} = | |
1946 | * {gfn_start, gfn_start+1, ..., gfn_end-1}. | |
1947 | */ | |
1948 | gfn_start = hva_to_gfn_memslot(hva_start, memslot); | |
1949 | gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); | |
1950 | ||
1951 | for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL, | |
1952 | PT_MAX_HUGEPAGE_LEVEL, | |
1953 | gfn_start, gfn_end - 1, | |
1954 | &iterator) | |
1955 | ret |= handler(kvm, iterator.rmap, memslot, | |
1956 | iterator.gfn, iterator.level, data); | |
1957 | } | |
e930bffe AA |
1958 | } |
1959 | ||
f395302e | 1960 | return ret; |
e930bffe AA |
1961 | } |
1962 | ||
84504ef3 TY |
1963 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1964 | unsigned long data, | |
018aabb5 TY |
1965 | int (*handler)(struct kvm *kvm, |
1966 | struct kvm_rmap_head *rmap_head, | |
048212d0 | 1967 | struct kvm_memory_slot *slot, |
8a9522d2 | 1968 | gfn_t gfn, int level, |
84504ef3 TY |
1969 | unsigned long data)) |
1970 | { | |
1971 | return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler); | |
e930bffe AA |
1972 | } |
1973 | ||
b3ae2096 TY |
1974 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end) |
1975 | { | |
1976 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp); | |
1977 | } | |
1978 | ||
748c0e31 | 1979 | int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
3da0dd43 | 1980 | { |
0cf853c5 | 1981 | return kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1982 | } |
1983 | ||
018aabb5 | 1984 | static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1985 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1986 | unsigned long data) | |
e930bffe | 1987 | { |
1e3f42f0 | 1988 | u64 *sptep; |
79f702a6 | 1989 | struct rmap_iterator uninitialized_var(iter); |
e930bffe AA |
1990 | int young = 0; |
1991 | ||
f160c7b7 JS |
1992 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1993 | young |= mmu_spte_age(sptep); | |
0d536790 | 1994 | |
8a9522d2 | 1995 | trace_kvm_age_page(gfn, level, slot, young); |
e930bffe AA |
1996 | return young; |
1997 | } | |
1998 | ||
018aabb5 | 1999 | static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
2000 | struct kvm_memory_slot *slot, gfn_t gfn, |
2001 | int level, unsigned long data) | |
8ee53820 | 2002 | { |
1e3f42f0 TY |
2003 | u64 *sptep; |
2004 | struct rmap_iterator iter; | |
8ee53820 | 2005 | |
83ef6c81 JS |
2006 | for_each_rmap_spte(rmap_head, &iter, sptep) |
2007 | if (is_accessed_spte(*sptep)) | |
2008 | return 1; | |
83ef6c81 | 2009 | return 0; |
8ee53820 AA |
2010 | } |
2011 | ||
53a27b39 MT |
2012 | #define RMAP_RECYCLE_THRESHOLD 1000 |
2013 | ||
852e3c19 | 2014 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 | 2015 | { |
018aabb5 | 2016 | struct kvm_rmap_head *rmap_head; |
852e3c19 JR |
2017 | struct kvm_mmu_page *sp; |
2018 | ||
2019 | sp = page_header(__pa(spte)); | |
53a27b39 | 2020 | |
018aabb5 | 2021 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
53a27b39 | 2022 | |
018aabb5 | 2023 | kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0); |
c3134ce2 LT |
2024 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn, |
2025 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
53a27b39 MT |
2026 | } |
2027 | ||
57128468 | 2028 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end) |
e930bffe | 2029 | { |
57128468 | 2030 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp); |
e930bffe AA |
2031 | } |
2032 | ||
8ee53820 AA |
2033 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
2034 | { | |
2035 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
2036 | } | |
2037 | ||
d6c69ee9 | 2038 | #ifdef MMU_DEBUG |
47ad8e68 | 2039 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 2040 | { |
139bdb2d AK |
2041 | u64 *pos; |
2042 | u64 *end; | |
2043 | ||
47ad8e68 | 2044 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 2045 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 2046 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 2047 | pos, *pos); |
6aa8b732 | 2048 | return 0; |
139bdb2d | 2049 | } |
6aa8b732 AK |
2050 | return 1; |
2051 | } | |
d6c69ee9 | 2052 | #endif |
6aa8b732 | 2053 | |
45221ab6 DH |
2054 | /* |
2055 | * This value is the sum of all of the kvm instances's | |
2056 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
2057 | * aggregate version in order to make the slab shrinker | |
2058 | * faster | |
2059 | */ | |
bc8a3d89 | 2060 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr) |
45221ab6 DH |
2061 | { |
2062 | kvm->arch.n_used_mmu_pages += nr; | |
2063 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
2064 | } | |
2065 | ||
834be0d8 | 2066 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 2067 | { |
fa4a2c08 | 2068 | MMU_WARN_ON(!is_empty_shadow_page(sp->spt)); |
7775834a | 2069 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
2070 | list_del(&sp->link); |
2071 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
2072 | if (!sp->role.direct) |
2073 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 2074 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
2075 | } |
2076 | ||
cea0f0e7 AK |
2077 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
2078 | { | |
114df303 | 2079 | return hash_64(gfn, KVM_MMU_HASH_SHIFT); |
cea0f0e7 AK |
2080 | } |
2081 | ||
714b93da | 2082 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 2083 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 2084 | { |
cea0f0e7 AK |
2085 | if (!parent_pte) |
2086 | return; | |
cea0f0e7 | 2087 | |
67052b35 | 2088 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
2089 | } |
2090 | ||
4db35314 | 2091 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
2092 | u64 *parent_pte) |
2093 | { | |
8daf3462 | 2094 | __pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
2095 | } |
2096 | ||
bcdd9a93 XG |
2097 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
2098 | u64 *parent_pte) | |
2099 | { | |
2100 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 2101 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
2102 | } |
2103 | ||
47005792 | 2104 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct) |
ad8cfbe3 | 2105 | { |
67052b35 | 2106 | struct kvm_mmu_page *sp; |
7ddca7e4 | 2107 | |
80feb89a TY |
2108 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
2109 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); | |
67052b35 | 2110 | if (!direct) |
80feb89a | 2111 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); |
67052b35 | 2112 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
002c5f73 SC |
2113 | |
2114 | /* | |
2115 | * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages() | |
2116 | * depends on valid pages being added to the head of the list. See | |
2117 | * comments in kvm_zap_obsolete_pages(). | |
2118 | */ | |
ca333add | 2119 | sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen; |
67052b35 | 2120 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
67052b35 XG |
2121 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
2122 | return sp; | |
ad8cfbe3 MT |
2123 | } |
2124 | ||
67052b35 | 2125 | static void mark_unsync(u64 *spte); |
1047df1f | 2126 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 2127 | { |
74c4e63a TY |
2128 | u64 *sptep; |
2129 | struct rmap_iterator iter; | |
2130 | ||
2131 | for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) { | |
2132 | mark_unsync(sptep); | |
2133 | } | |
0074ff63 MT |
2134 | } |
2135 | ||
67052b35 | 2136 | static void mark_unsync(u64 *spte) |
0074ff63 | 2137 | { |
67052b35 | 2138 | struct kvm_mmu_page *sp; |
1047df1f | 2139 | unsigned int index; |
0074ff63 | 2140 | |
67052b35 | 2141 | sp = page_header(__pa(spte)); |
1047df1f XG |
2142 | index = spte - sp->spt; |
2143 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 2144 | return; |
1047df1f | 2145 | if (sp->unsync_children++) |
0074ff63 | 2146 | return; |
1047df1f | 2147 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
2148 | } |
2149 | ||
e8bc217a | 2150 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 2151 | struct kvm_mmu_page *sp) |
e8bc217a | 2152 | { |
1f50f1b3 | 2153 | return 0; |
e8bc217a MT |
2154 | } |
2155 | ||
0f53b5b1 XG |
2156 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
2157 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 2158 | const void *pte) |
0f53b5b1 XG |
2159 | { |
2160 | WARN_ON(1); | |
2161 | } | |
2162 | ||
60c8aec6 MT |
2163 | #define KVM_PAGE_ARRAY_NR 16 |
2164 | ||
2165 | struct kvm_mmu_pages { | |
2166 | struct mmu_page_and_offset { | |
2167 | struct kvm_mmu_page *sp; | |
2168 | unsigned int idx; | |
2169 | } page[KVM_PAGE_ARRAY_NR]; | |
2170 | unsigned int nr; | |
2171 | }; | |
2172 | ||
cded19f3 HE |
2173 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
2174 | int idx) | |
4731d4c7 | 2175 | { |
60c8aec6 | 2176 | int i; |
4731d4c7 | 2177 | |
60c8aec6 MT |
2178 | if (sp->unsync) |
2179 | for (i=0; i < pvec->nr; i++) | |
2180 | if (pvec->page[i].sp == sp) | |
2181 | return 0; | |
2182 | ||
2183 | pvec->page[pvec->nr].sp = sp; | |
2184 | pvec->page[pvec->nr].idx = idx; | |
2185 | pvec->nr++; | |
2186 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
2187 | } | |
2188 | ||
fd951457 TY |
2189 | static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx) |
2190 | { | |
2191 | --sp->unsync_children; | |
2192 | WARN_ON((int)sp->unsync_children < 0); | |
2193 | __clear_bit(idx, sp->unsync_child_bitmap); | |
2194 | } | |
2195 | ||
60c8aec6 MT |
2196 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, |
2197 | struct kvm_mmu_pages *pvec) | |
2198 | { | |
2199 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 2200 | |
37178b8b | 2201 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 2202 | struct kvm_mmu_page *child; |
4731d4c7 MT |
2203 | u64 ent = sp->spt[i]; |
2204 | ||
fd951457 TY |
2205 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) { |
2206 | clear_unsync_child_bit(sp, i); | |
2207 | continue; | |
2208 | } | |
7a8f1a74 XG |
2209 | |
2210 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
2211 | ||
2212 | if (child->unsync_children) { | |
2213 | if (mmu_pages_add(pvec, child, i)) | |
2214 | return -ENOSPC; | |
2215 | ||
2216 | ret = __mmu_unsync_walk(child, pvec); | |
fd951457 TY |
2217 | if (!ret) { |
2218 | clear_unsync_child_bit(sp, i); | |
2219 | continue; | |
2220 | } else if (ret > 0) { | |
7a8f1a74 | 2221 | nr_unsync_leaf += ret; |
fd951457 | 2222 | } else |
7a8f1a74 XG |
2223 | return ret; |
2224 | } else if (child->unsync) { | |
2225 | nr_unsync_leaf++; | |
2226 | if (mmu_pages_add(pvec, child, i)) | |
2227 | return -ENOSPC; | |
2228 | } else | |
fd951457 | 2229 | clear_unsync_child_bit(sp, i); |
4731d4c7 MT |
2230 | } |
2231 | ||
60c8aec6 MT |
2232 | return nr_unsync_leaf; |
2233 | } | |
2234 | ||
e23d3fef XG |
2235 | #define INVALID_INDEX (-1) |
2236 | ||
60c8aec6 MT |
2237 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, |
2238 | struct kvm_mmu_pages *pvec) | |
2239 | { | |
0a47cd85 | 2240 | pvec->nr = 0; |
60c8aec6 MT |
2241 | if (!sp->unsync_children) |
2242 | return 0; | |
2243 | ||
e23d3fef | 2244 | mmu_pages_add(pvec, sp, INVALID_INDEX); |
60c8aec6 | 2245 | return __mmu_unsync_walk(sp, pvec); |
4731d4c7 MT |
2246 | } |
2247 | ||
4731d4c7 MT |
2248 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
2249 | { | |
2250 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 2251 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
2252 | sp->unsync = 0; |
2253 | --kvm->stat.mmu_unsync; | |
2254 | } | |
2255 | ||
83cdb568 SC |
2256 | static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2257 | struct list_head *invalid_list); | |
7775834a XG |
2258 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2259 | struct list_head *invalid_list); | |
4731d4c7 | 2260 | |
47c42e6b | 2261 | |
f3414bc7 | 2262 | #define for_each_valid_sp(_kvm, _sp, _gfn) \ |
1044b030 TY |
2263 | hlist_for_each_entry(_sp, \ |
2264 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \ | |
fac026da | 2265 | if (is_obsolete_sp((_kvm), (_sp))) { \ |
f3414bc7 | 2266 | } else |
1044b030 TY |
2267 | |
2268 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
f3414bc7 DM |
2269 | for_each_valid_sp(_kvm, _sp, _gfn) \ |
2270 | if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else | |
7ae680eb | 2271 | |
47c42e6b SC |
2272 | static inline bool is_ept_sp(struct kvm_mmu_page *sp) |
2273 | { | |
2274 | return sp->role.cr0_wp && sp->role.smap_andnot_wp; | |
2275 | } | |
2276 | ||
f918b443 | 2277 | /* @sp->gfn should be write-protected at the call site */ |
1f50f1b3 PB |
2278 | static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
2279 | struct list_head *invalid_list) | |
4731d4c7 | 2280 | { |
47c42e6b SC |
2281 | if ((!is_ept_sp(sp) && sp->role.gpte_is_8_bytes != !!is_pae(vcpu)) || |
2282 | vcpu->arch.mmu->sync_page(vcpu, sp) == 0) { | |
d98ba053 | 2283 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 2284 | return false; |
4731d4c7 MT |
2285 | } |
2286 | ||
1f50f1b3 | 2287 | return true; |
4731d4c7 MT |
2288 | } |
2289 | ||
a2113634 SC |
2290 | static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm, |
2291 | struct list_head *invalid_list, | |
2292 | bool remote_flush) | |
2293 | { | |
cfd32acf | 2294 | if (!remote_flush && list_empty(invalid_list)) |
a2113634 SC |
2295 | return false; |
2296 | ||
2297 | if (!list_empty(invalid_list)) | |
2298 | kvm_mmu_commit_zap_page(kvm, invalid_list); | |
2299 | else | |
2300 | kvm_flush_remote_tlbs(kvm); | |
2301 | return true; | |
2302 | } | |
2303 | ||
35a70510 PB |
2304 | static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu, |
2305 | struct list_head *invalid_list, | |
2306 | bool remote_flush, bool local_flush) | |
1d9dc7e0 | 2307 | { |
a2113634 | 2308 | if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush)) |
35a70510 | 2309 | return; |
d98ba053 | 2310 | |
a2113634 | 2311 | if (local_flush) |
35a70510 | 2312 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
1d9dc7e0 XG |
2313 | } |
2314 | ||
e37fa785 XG |
2315 | #ifdef CONFIG_KVM_MMU_AUDIT |
2316 | #include "mmu_audit.c" | |
2317 | #else | |
2318 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
2319 | static void mmu_audit_disable(void) { } | |
2320 | #endif | |
2321 | ||
002c5f73 SC |
2322 | static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) |
2323 | { | |
fac026da SC |
2324 | return sp->role.invalid || |
2325 | unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); | |
002c5f73 SC |
2326 | } |
2327 | ||
1f50f1b3 | 2328 | static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 2329 | struct list_head *invalid_list) |
1d9dc7e0 | 2330 | { |
9a43c5d9 PB |
2331 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
2332 | return __kvm_sync_page(vcpu, sp, invalid_list); | |
1d9dc7e0 XG |
2333 | } |
2334 | ||
9f1a122f | 2335 | /* @gfn should be write-protected at the call site */ |
2a74003a PB |
2336 | static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, |
2337 | struct list_head *invalid_list) | |
9f1a122f | 2338 | { |
9f1a122f | 2339 | struct kvm_mmu_page *s; |
2a74003a | 2340 | bool ret = false; |
9f1a122f | 2341 | |
b67bfe0d | 2342 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 2343 | if (!s->unsync) |
9f1a122f XG |
2344 | continue; |
2345 | ||
2346 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
2a74003a | 2347 | ret |= kvm_sync_page(vcpu, s, invalid_list); |
9f1a122f XG |
2348 | } |
2349 | ||
2a74003a | 2350 | return ret; |
9f1a122f XG |
2351 | } |
2352 | ||
60c8aec6 | 2353 | struct mmu_page_path { |
2a7266a8 YZ |
2354 | struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL]; |
2355 | unsigned int idx[PT64_ROOT_MAX_LEVEL]; | |
4731d4c7 MT |
2356 | }; |
2357 | ||
60c8aec6 | 2358 | #define for_each_sp(pvec, sp, parents, i) \ |
0a47cd85 | 2359 | for (i = mmu_pages_first(&pvec, &parents); \ |
60c8aec6 MT |
2360 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ |
2361 | i = mmu_pages_next(&pvec, &parents, i)) | |
2362 | ||
cded19f3 HE |
2363 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
2364 | struct mmu_page_path *parents, | |
2365 | int i) | |
60c8aec6 MT |
2366 | { |
2367 | int n; | |
2368 | ||
2369 | for (n = i+1; n < pvec->nr; n++) { | |
2370 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
0a47cd85 PB |
2371 | unsigned idx = pvec->page[n].idx; |
2372 | int level = sp->role.level; | |
60c8aec6 | 2373 | |
0a47cd85 PB |
2374 | parents->idx[level-1] = idx; |
2375 | if (level == PT_PAGE_TABLE_LEVEL) | |
2376 | break; | |
60c8aec6 | 2377 | |
0a47cd85 | 2378 | parents->parent[level-2] = sp; |
60c8aec6 MT |
2379 | } |
2380 | ||
2381 | return n; | |
2382 | } | |
2383 | ||
0a47cd85 PB |
2384 | static int mmu_pages_first(struct kvm_mmu_pages *pvec, |
2385 | struct mmu_page_path *parents) | |
2386 | { | |
2387 | struct kvm_mmu_page *sp; | |
2388 | int level; | |
2389 | ||
2390 | if (pvec->nr == 0) | |
2391 | return 0; | |
2392 | ||
e23d3fef XG |
2393 | WARN_ON(pvec->page[0].idx != INVALID_INDEX); |
2394 | ||
0a47cd85 PB |
2395 | sp = pvec->page[0].sp; |
2396 | level = sp->role.level; | |
2397 | WARN_ON(level == PT_PAGE_TABLE_LEVEL); | |
2398 | ||
2399 | parents->parent[level-2] = sp; | |
2400 | ||
2401 | /* Also set up a sentinel. Further entries in pvec are all | |
2402 | * children of sp, so this element is never overwritten. | |
2403 | */ | |
2404 | parents->parent[level-1] = NULL; | |
2405 | return mmu_pages_next(pvec, parents, 0); | |
2406 | } | |
2407 | ||
cded19f3 | 2408 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 2409 | { |
60c8aec6 MT |
2410 | struct kvm_mmu_page *sp; |
2411 | unsigned int level = 0; | |
2412 | ||
2413 | do { | |
2414 | unsigned int idx = parents->idx[level]; | |
60c8aec6 MT |
2415 | sp = parents->parent[level]; |
2416 | if (!sp) | |
2417 | return; | |
2418 | ||
e23d3fef | 2419 | WARN_ON(idx == INVALID_INDEX); |
fd951457 | 2420 | clear_unsync_child_bit(sp, idx); |
60c8aec6 | 2421 | level++; |
0a47cd85 | 2422 | } while (!sp->unsync_children); |
60c8aec6 | 2423 | } |
4731d4c7 | 2424 | |
60c8aec6 MT |
2425 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
2426 | struct kvm_mmu_page *parent) | |
2427 | { | |
2428 | int i; | |
2429 | struct kvm_mmu_page *sp; | |
2430 | struct mmu_page_path parents; | |
2431 | struct kvm_mmu_pages pages; | |
d98ba053 | 2432 | LIST_HEAD(invalid_list); |
50c9e6f3 | 2433 | bool flush = false; |
60c8aec6 | 2434 | |
60c8aec6 | 2435 | while (mmu_unsync_walk(parent, &pages)) { |
2f84569f | 2436 | bool protected = false; |
b1a36821 MT |
2437 | |
2438 | for_each_sp(pages, sp, parents, i) | |
54bf36aa | 2439 | protected |= rmap_write_protect(vcpu, sp->gfn); |
b1a36821 | 2440 | |
50c9e6f3 | 2441 | if (protected) { |
b1a36821 | 2442 | kvm_flush_remote_tlbs(vcpu->kvm); |
50c9e6f3 PB |
2443 | flush = false; |
2444 | } | |
b1a36821 | 2445 | |
60c8aec6 | 2446 | for_each_sp(pages, sp, parents, i) { |
1f50f1b3 | 2447 | flush |= kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
2448 | mmu_pages_clear_parents(&parents); |
2449 | } | |
50c9e6f3 PB |
2450 | if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) { |
2451 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
2452 | cond_resched_lock(&vcpu->kvm->mmu_lock); | |
2453 | flush = false; | |
2454 | } | |
60c8aec6 | 2455 | } |
50c9e6f3 PB |
2456 | |
2457 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
4731d4c7 MT |
2458 | } |
2459 | ||
a30f47cb XG |
2460 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
2461 | { | |
e5691a81 | 2462 | atomic_set(&sp->write_flooding_count, 0); |
a30f47cb XG |
2463 | } |
2464 | ||
2465 | static void clear_sp_write_flooding_count(u64 *spte) | |
2466 | { | |
2467 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
2468 | ||
2469 | __clear_sp_write_flooding_count(sp); | |
2470 | } | |
2471 | ||
cea0f0e7 AK |
2472 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
2473 | gfn_t gfn, | |
2474 | gva_t gaddr, | |
2475 | unsigned level, | |
f6e2c02b | 2476 | int direct, |
0a2b64c5 | 2477 | unsigned int access) |
cea0f0e7 AK |
2478 | { |
2479 | union kvm_mmu_page_role role; | |
cea0f0e7 | 2480 | unsigned quadrant; |
9f1a122f | 2481 | struct kvm_mmu_page *sp; |
9f1a122f | 2482 | bool need_sync = false; |
2a74003a | 2483 | bool flush = false; |
f3414bc7 | 2484 | int collisions = 0; |
2a74003a | 2485 | LIST_HEAD(invalid_list); |
cea0f0e7 | 2486 | |
36d9594d | 2487 | role = vcpu->arch.mmu->mmu_role.base; |
cea0f0e7 | 2488 | role.level = level; |
f6e2c02b | 2489 | role.direct = direct; |
84b0c8c6 | 2490 | if (role.direct) |
47c42e6b | 2491 | role.gpte_is_8_bytes = true; |
41074d07 | 2492 | role.access = access; |
44dd3ffa VK |
2493 | if (!vcpu->arch.mmu->direct_map |
2494 | && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
2495 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
2496 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
2497 | role.quadrant = quadrant; | |
2498 | } | |
f3414bc7 DM |
2499 | for_each_valid_sp(vcpu->kvm, sp, gfn) { |
2500 | if (sp->gfn != gfn) { | |
2501 | collisions++; | |
2502 | continue; | |
2503 | } | |
2504 | ||
7ae680eb XG |
2505 | if (!need_sync && sp->unsync) |
2506 | need_sync = true; | |
4731d4c7 | 2507 | |
7ae680eb XG |
2508 | if (sp->role.word != role.word) |
2509 | continue; | |
4731d4c7 | 2510 | |
2a74003a PB |
2511 | if (sp->unsync) { |
2512 | /* The page is good, but __kvm_sync_page might still end | |
2513 | * up zapping it. If so, break in order to rebuild it. | |
2514 | */ | |
2515 | if (!__kvm_sync_page(vcpu, sp, &invalid_list)) | |
2516 | break; | |
2517 | ||
2518 | WARN_ON(!list_empty(&invalid_list)); | |
2519 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
2520 | } | |
e02aa901 | 2521 | |
98bba238 | 2522 | if (sp->unsync_children) |
a8eeb04a | 2523 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
e02aa901 | 2524 | |
a30f47cb | 2525 | __clear_sp_write_flooding_count(sp); |
7ae680eb | 2526 | trace_kvm_mmu_get_page(sp, false); |
f3414bc7 | 2527 | goto out; |
7ae680eb | 2528 | } |
47005792 | 2529 | |
dfc5aa00 | 2530 | ++vcpu->kvm->stat.mmu_cache_miss; |
47005792 TY |
2531 | |
2532 | sp = kvm_mmu_alloc_page(vcpu, direct); | |
2533 | ||
4db35314 AK |
2534 | sp->gfn = gfn; |
2535 | sp->role = role; | |
7ae680eb XG |
2536 | hlist_add_head(&sp->hash_link, |
2537 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 2538 | if (!direct) { |
56ca57f9 XG |
2539 | /* |
2540 | * we should do write protection before syncing pages | |
2541 | * otherwise the content of the synced shadow page may | |
2542 | * be inconsistent with guest page table. | |
2543 | */ | |
2544 | account_shadowed(vcpu->kvm, sp); | |
2545 | if (level == PT_PAGE_TABLE_LEVEL && | |
2546 | rmap_write_protect(vcpu, gfn)) | |
c3134ce2 | 2547 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1); |
9f1a122f | 2548 | |
9f1a122f | 2549 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
2a74003a | 2550 | flush |= kvm_sync_pages(vcpu, gfn, &invalid_list); |
4731d4c7 | 2551 | } |
77492664 | 2552 | clear_page(sp->spt); |
f691fe1d | 2553 | trace_kvm_mmu_get_page(sp, true); |
2a74003a PB |
2554 | |
2555 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
f3414bc7 DM |
2556 | out: |
2557 | if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions) | |
2558 | vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions; | |
4db35314 | 2559 | return sp; |
cea0f0e7 AK |
2560 | } |
2561 | ||
7eb77e9f JS |
2562 | static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator, |
2563 | struct kvm_vcpu *vcpu, hpa_t root, | |
2564 | u64 addr) | |
2d11123a AK |
2565 | { |
2566 | iterator->addr = addr; | |
7eb77e9f | 2567 | iterator->shadow_addr = root; |
44dd3ffa | 2568 | iterator->level = vcpu->arch.mmu->shadow_root_level; |
81407ca5 | 2569 | |
2a7266a8 | 2570 | if (iterator->level == PT64_ROOT_4LEVEL && |
44dd3ffa VK |
2571 | vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL && |
2572 | !vcpu->arch.mmu->direct_map) | |
81407ca5 JR |
2573 | --iterator->level; |
2574 | ||
2d11123a | 2575 | if (iterator->level == PT32E_ROOT_LEVEL) { |
7eb77e9f JS |
2576 | /* |
2577 | * prev_root is currently only used for 64-bit hosts. So only | |
2578 | * the active root_hpa is valid here. | |
2579 | */ | |
44dd3ffa | 2580 | BUG_ON(root != vcpu->arch.mmu->root_hpa); |
7eb77e9f | 2581 | |
2d11123a | 2582 | iterator->shadow_addr |
44dd3ffa | 2583 | = vcpu->arch.mmu->pae_root[(addr >> 30) & 3]; |
2d11123a AK |
2584 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; |
2585 | --iterator->level; | |
2586 | if (!iterator->shadow_addr) | |
2587 | iterator->level = 0; | |
2588 | } | |
2589 | } | |
2590 | ||
7eb77e9f JS |
2591 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
2592 | struct kvm_vcpu *vcpu, u64 addr) | |
2593 | { | |
44dd3ffa | 2594 | shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa, |
7eb77e9f JS |
2595 | addr); |
2596 | } | |
2597 | ||
2d11123a AK |
2598 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) |
2599 | { | |
2600 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
2601 | return false; | |
4d88954d | 2602 | |
2d11123a AK |
2603 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
2604 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
2605 | return true; | |
2606 | } | |
2607 | ||
c2a2ac2b XG |
2608 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
2609 | u64 spte) | |
2d11123a | 2610 | { |
c2a2ac2b | 2611 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
2612 | iterator->level = 0; |
2613 | return; | |
2614 | } | |
2615 | ||
c2a2ac2b | 2616 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
2617 | --iterator->level; |
2618 | } | |
2619 | ||
c2a2ac2b XG |
2620 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
2621 | { | |
bb606a9b | 2622 | __shadow_walk_next(iterator, *iterator->sptep); |
c2a2ac2b XG |
2623 | } |
2624 | ||
98bba238 TY |
2625 | static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep, |
2626 | struct kvm_mmu_page *sp) | |
32ef26a3 AK |
2627 | { |
2628 | u64 spte; | |
2629 | ||
ffb128c8 | 2630 | BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK); |
7a1638ce | 2631 | |
ffb128c8 | 2632 | spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK | |
d0ec49d4 | 2633 | shadow_user_mask | shadow_x_mask | shadow_me_mask; |
ac8d57e5 PF |
2634 | |
2635 | if (sp_ad_disabled(sp)) | |
6eeb4ef0 | 2636 | spte |= SPTE_AD_DISABLED_MASK; |
ac8d57e5 PF |
2637 | else |
2638 | spte |= shadow_accessed_mask; | |
24db2734 | 2639 | |
1df9f2dc | 2640 | mmu_spte_set(sptep, spte); |
98bba238 TY |
2641 | |
2642 | mmu_page_add_parent_pte(vcpu, sp, sptep); | |
2643 | ||
2644 | if (sp->unsync_children || sp->unsync) | |
2645 | mark_unsync(sptep); | |
32ef26a3 AK |
2646 | } |
2647 | ||
a357bd22 AK |
2648 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2649 | unsigned direct_access) | |
2650 | { | |
2651 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
2652 | struct kvm_mmu_page *child; | |
2653 | ||
2654 | /* | |
2655 | * For the direct sp, if the guest pte's dirty bit | |
2656 | * changed form clean to dirty, it will corrupt the | |
2657 | * sp's access: allow writable in the read-only sp, | |
2658 | * so we should update the spte at this point to get | |
2659 | * a new sp with the correct access. | |
2660 | */ | |
2661 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
2662 | if (child->role.access == direct_access) | |
2663 | return; | |
2664 | ||
bcdd9a93 | 2665 | drop_parent_pte(child, sptep); |
c3134ce2 | 2666 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1); |
a357bd22 AK |
2667 | } |
2668 | } | |
2669 | ||
505aef8f | 2670 | static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
38e3b2b2 XG |
2671 | u64 *spte) |
2672 | { | |
2673 | u64 pte; | |
2674 | struct kvm_mmu_page *child; | |
2675 | ||
2676 | pte = *spte; | |
2677 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2678 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2679 | drop_spte(kvm, spte); |
505aef8f XG |
2680 | if (is_large_pte(pte)) |
2681 | --kvm->stat.lpages; | |
2682 | } else { | |
38e3b2b2 | 2683 | child = page_header(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2684 | drop_parent_pte(child, spte); |
38e3b2b2 | 2685 | } |
505aef8f XG |
2686 | return true; |
2687 | } | |
2688 | ||
2689 | if (is_mmio_spte(pte)) | |
ce88decf | 2690 | mmu_spte_clear_no_track(spte); |
c3707958 | 2691 | |
505aef8f | 2692 | return false; |
38e3b2b2 XG |
2693 | } |
2694 | ||
90cb0529 | 2695 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 2696 | struct kvm_mmu_page *sp) |
a436036b | 2697 | { |
697fe2e2 | 2698 | unsigned i; |
697fe2e2 | 2699 | |
38e3b2b2 XG |
2700 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2701 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
2702 | } |
2703 | ||
31aa2b44 | 2704 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2705 | { |
1e3f42f0 TY |
2706 | u64 *sptep; |
2707 | struct rmap_iterator iter; | |
a436036b | 2708 | |
018aabb5 | 2709 | while ((sptep = rmap_get_first(&sp->parent_ptes, &iter))) |
1e3f42f0 | 2710 | drop_parent_pte(sp, sptep); |
31aa2b44 AK |
2711 | } |
2712 | ||
60c8aec6 | 2713 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2714 | struct kvm_mmu_page *parent, |
2715 | struct list_head *invalid_list) | |
4731d4c7 | 2716 | { |
60c8aec6 MT |
2717 | int i, zapped = 0; |
2718 | struct mmu_page_path parents; | |
2719 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2720 | |
60c8aec6 | 2721 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2722 | return 0; |
60c8aec6 | 2723 | |
60c8aec6 MT |
2724 | while (mmu_unsync_walk(parent, &pages)) { |
2725 | struct kvm_mmu_page *sp; | |
2726 | ||
2727 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2728 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2729 | mmu_pages_clear_parents(&parents); |
77662e00 | 2730 | zapped++; |
60c8aec6 | 2731 | } |
60c8aec6 MT |
2732 | } |
2733 | ||
2734 | return zapped; | |
4731d4c7 MT |
2735 | } |
2736 | ||
83cdb568 SC |
2737 | static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm, |
2738 | struct kvm_mmu_page *sp, | |
2739 | struct list_head *invalid_list, | |
2740 | int *nr_zapped) | |
31aa2b44 | 2741 | { |
83cdb568 | 2742 | bool list_unstable; |
f691fe1d | 2743 | |
7775834a | 2744 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2745 | ++kvm->stat.mmu_shadow_zapped; |
83cdb568 | 2746 | *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 2747 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 2748 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2749 | |
83cdb568 SC |
2750 | /* Zapping children means active_mmu_pages has become unstable. */ |
2751 | list_unstable = *nr_zapped; | |
2752 | ||
f6e2c02b | 2753 | if (!sp->role.invalid && !sp->role.direct) |
3ed1a478 | 2754 | unaccount_shadowed(kvm, sp); |
5304b8d3 | 2755 | |
4731d4c7 MT |
2756 | if (sp->unsync) |
2757 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2758 | if (!sp->root_count) { |
54a4f023 | 2759 | /* Count self */ |
83cdb568 | 2760 | (*nr_zapped)++; |
7775834a | 2761 | list_move(&sp->link, invalid_list); |
aa6bd187 | 2762 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2763 | } else { |
5b5c6a5a | 2764 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
05988d72 | 2765 | |
10605204 SC |
2766 | /* |
2767 | * Obsolete pages cannot be used on any vCPUs, see the comment | |
2768 | * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also | |
2769 | * treats invalid shadow pages as being obsolete. | |
2770 | */ | |
2771 | if (!is_obsolete_sp(kvm, sp)) | |
05988d72 | 2772 | kvm_reload_remote_mmus(kvm); |
2e53d63a | 2773 | } |
7775834a | 2774 | |
b8e8c830 PB |
2775 | if (sp->lpage_disallowed) |
2776 | unaccount_huge_nx_page(kvm, sp); | |
2777 | ||
7775834a | 2778 | sp->role.invalid = 1; |
83cdb568 SC |
2779 | return list_unstable; |
2780 | } | |
2781 | ||
2782 | static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, | |
2783 | struct list_head *invalid_list) | |
2784 | { | |
2785 | int nr_zapped; | |
2786 | ||
2787 | __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped); | |
2788 | return nr_zapped; | |
a436036b AK |
2789 | } |
2790 | ||
7775834a XG |
2791 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2792 | struct list_head *invalid_list) | |
2793 | { | |
945315b9 | 2794 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2795 | |
2796 | if (list_empty(invalid_list)) | |
2797 | return; | |
2798 | ||
c142786c | 2799 | /* |
9753f529 LT |
2800 | * We need to make sure everyone sees our modifications to |
2801 | * the page tables and see changes to vcpu->mode here. The barrier | |
2802 | * in the kvm_flush_remote_tlbs() achieves this. This pairs | |
2803 | * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end. | |
2804 | * | |
2805 | * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit | |
2806 | * guest mode and/or lockless shadow page table walks. | |
c142786c AK |
2807 | */ |
2808 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2809 | |
945315b9 | 2810 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2811 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2812 | kvm_mmu_free_page(sp); |
945315b9 | 2813 | } |
7775834a XG |
2814 | } |
2815 | ||
5da59607 TY |
2816 | static bool prepare_zap_oldest_mmu_page(struct kvm *kvm, |
2817 | struct list_head *invalid_list) | |
2818 | { | |
2819 | struct kvm_mmu_page *sp; | |
2820 | ||
2821 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
2822 | return false; | |
2823 | ||
d74c0e6b GT |
2824 | sp = list_last_entry(&kvm->arch.active_mmu_pages, |
2825 | struct kvm_mmu_page, link); | |
42bcbebf | 2826 | return kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
5da59607 TY |
2827 | } |
2828 | ||
ba7888dd SC |
2829 | static int make_mmu_pages_available(struct kvm_vcpu *vcpu) |
2830 | { | |
2831 | LIST_HEAD(invalid_list); | |
2832 | ||
2833 | if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES)) | |
2834 | return 0; | |
2835 | ||
2836 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) { | |
2837 | if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list)) | |
2838 | break; | |
2839 | ||
2840 | ++vcpu->kvm->stat.mmu_recycled; | |
2841 | } | |
2842 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
2843 | ||
2844 | if (!kvm_mmu_available_pages(vcpu->kvm)) | |
2845 | return -ENOSPC; | |
2846 | return 0; | |
2847 | } | |
2848 | ||
82ce2c96 IE |
2849 | /* |
2850 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2851 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2852 | */ |
bc8a3d89 | 2853 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages) |
82ce2c96 | 2854 | { |
d98ba053 | 2855 | LIST_HEAD(invalid_list); |
82ce2c96 | 2856 | |
b34cb590 TY |
2857 | spin_lock(&kvm->mmu_lock); |
2858 | ||
49d5ca26 | 2859 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
5da59607 TY |
2860 | /* Need to free some mmu pages to achieve the goal. */ |
2861 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) | |
2862 | if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list)) | |
2863 | break; | |
82ce2c96 | 2864 | |
aa6bd187 | 2865 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 2866 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2867 | } |
82ce2c96 | 2868 | |
49d5ca26 | 2869 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 TY |
2870 | |
2871 | spin_unlock(&kvm->mmu_lock); | |
82ce2c96 IE |
2872 | } |
2873 | ||
1cb3f3ae | 2874 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2875 | { |
4db35314 | 2876 | struct kvm_mmu_page *sp; |
d98ba053 | 2877 | LIST_HEAD(invalid_list); |
a436036b AK |
2878 | int r; |
2879 | ||
9ad17b10 | 2880 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2881 | r = 0; |
1cb3f3ae | 2882 | spin_lock(&kvm->mmu_lock); |
b67bfe0d | 2883 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2884 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2885 | sp->role.word); |
2886 | r = 1; | |
f41d335a | 2887 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2888 | } |
d98ba053 | 2889 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2890 | spin_unlock(&kvm->mmu_lock); |
2891 | ||
a436036b | 2892 | return r; |
cea0f0e7 | 2893 | } |
1cb3f3ae | 2894 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2895 | |
5c520e90 | 2896 | static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
9cf5cf5a XG |
2897 | { |
2898 | trace_kvm_mmu_unsync_page(sp); | |
2899 | ++vcpu->kvm->stat.mmu_unsync; | |
2900 | sp->unsync = 1; | |
2901 | ||
2902 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2903 | } |
2904 | ||
3d0c27ad XG |
2905 | static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, |
2906 | bool can_unsync) | |
4731d4c7 | 2907 | { |
5c520e90 | 2908 | struct kvm_mmu_page *sp; |
4731d4c7 | 2909 | |
3d0c27ad XG |
2910 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) |
2911 | return true; | |
9cf5cf5a | 2912 | |
5c520e90 | 2913 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
36a2e677 | 2914 | if (!can_unsync) |
3d0c27ad | 2915 | return true; |
36a2e677 | 2916 | |
5c520e90 XG |
2917 | if (sp->unsync) |
2918 | continue; | |
9cf5cf5a | 2919 | |
5c520e90 XG |
2920 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
2921 | kvm_unsync_page(vcpu, sp); | |
4731d4c7 | 2922 | } |
3d0c27ad | 2923 | |
578e1c4d JS |
2924 | /* |
2925 | * We need to ensure that the marking of unsync pages is visible | |
2926 | * before the SPTE is updated to allow writes because | |
2927 | * kvm_mmu_sync_roots() checks the unsync flags without holding | |
2928 | * the MMU lock and so can race with this. If the SPTE was updated | |
2929 | * before the page had been marked as unsync-ed, something like the | |
2930 | * following could happen: | |
2931 | * | |
2932 | * CPU 1 CPU 2 | |
2933 | * --------------------------------------------------------------------- | |
2934 | * 1.2 Host updates SPTE | |
2935 | * to be writable | |
2936 | * 2.1 Guest writes a GPTE for GVA X. | |
2937 | * (GPTE being in the guest page table shadowed | |
2938 | * by the SP from CPU 1.) | |
2939 | * This reads SPTE during the page table walk. | |
2940 | * Since SPTE.W is read as 1, there is no | |
2941 | * fault. | |
2942 | * | |
2943 | * 2.2 Guest issues TLB flush. | |
2944 | * That causes a VM Exit. | |
2945 | * | |
2946 | * 2.3 kvm_mmu_sync_pages() reads sp->unsync. | |
2947 | * Since it is false, so it just returns. | |
2948 | * | |
2949 | * 2.4 Guest accesses GVA X. | |
2950 | * Since the mapping in the SP was not updated, | |
2951 | * so the old mapping for GVA X incorrectly | |
2952 | * gets used. | |
2953 | * 1.1 Host marks SP | |
2954 | * as unsync | |
2955 | * (sp->unsync = true) | |
2956 | * | |
2957 | * The write barrier below ensures that 1.1 happens before 1.2 and thus | |
2958 | * the situation in 2.4 does not arise. The implicit barrier in 2.2 | |
2959 | * pairs with this write barrier. | |
2960 | */ | |
2961 | smp_wmb(); | |
2962 | ||
3d0c27ad | 2963 | return false; |
4731d4c7 MT |
2964 | } |
2965 | ||
ba049e93 | 2966 | static bool kvm_is_mmio_pfn(kvm_pfn_t pfn) |
d1fe9219 PB |
2967 | { |
2968 | if (pfn_valid(pfn)) | |
aa2e063a HZ |
2969 | return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) && |
2970 | /* | |
2971 | * Some reserved pages, such as those from NVDIMM | |
2972 | * DAX devices, are not for MMIO, and can be mapped | |
2973 | * with cached memory type for better performance. | |
2974 | * However, the above check misconceives those pages | |
2975 | * as MMIO, and results in KVM mapping them with UC | |
2976 | * memory type, which would hurt the performance. | |
2977 | * Therefore, we check the host memory type in addition | |
2978 | * and only treat UC/UC-/WC pages as MMIO. | |
2979 | */ | |
2980 | (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn)); | |
d1fe9219 | 2981 | |
0c55671f KA |
2982 | return !e820__mapped_raw_any(pfn_to_hpa(pfn), |
2983 | pfn_to_hpa(pfn + 1) - 1, | |
2984 | E820_TYPE_RAM); | |
d1fe9219 PB |
2985 | } |
2986 | ||
5ce4786f JS |
2987 | /* Bits which may be returned by set_spte() */ |
2988 | #define SET_SPTE_WRITE_PROTECTED_PT BIT(0) | |
2989 | #define SET_SPTE_NEED_REMOTE_TLB_FLUSH BIT(1) | |
2990 | ||
d555c333 | 2991 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
0a2b64c5 | 2992 | unsigned int pte_access, int level, |
ba049e93 | 2993 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, |
9bdbba13 | 2994 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2995 | { |
ffb128c8 | 2996 | u64 spte = 0; |
1e73f9dd | 2997 | int ret = 0; |
ac8d57e5 | 2998 | struct kvm_mmu_page *sp; |
64d4d521 | 2999 | |
54bf36aa | 3000 | if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access)) |
ce88decf XG |
3001 | return 0; |
3002 | ||
ac8d57e5 PF |
3003 | sp = page_header(__pa(sptep)); |
3004 | if (sp_ad_disabled(sp)) | |
6eeb4ef0 | 3005 | spte |= SPTE_AD_DISABLED_MASK; |
1f4e5fc8 PB |
3006 | else if (kvm_vcpu_ad_need_write_protect(vcpu)) |
3007 | spte |= SPTE_AD_WRPROT_ONLY_MASK; | |
ac8d57e5 | 3008 | |
d95c5568 BD |
3009 | /* |
3010 | * For the EPT case, shadow_present_mask is 0 if hardware | |
3011 | * supports exec-only page table entries. In that case, | |
3012 | * ACC_USER_MASK and shadow_user_mask are used to represent | |
3013 | * read access. See FNAME(gpte_access) in paging_tmpl.h. | |
3014 | */ | |
ffb128c8 | 3015 | spte |= shadow_present_mask; |
947da538 | 3016 | if (!speculative) |
ac8d57e5 | 3017 | spte |= spte_shadow_accessed_mask(spte); |
640d9b0d | 3018 | |
b8e8c830 PB |
3019 | if (level > PT_PAGE_TABLE_LEVEL && (pte_access & ACC_EXEC_MASK) && |
3020 | is_nx_huge_page_enabled()) { | |
3021 | pte_access &= ~ACC_EXEC_MASK; | |
3022 | } | |
3023 | ||
7b52345e SY |
3024 | if (pte_access & ACC_EXEC_MASK) |
3025 | spte |= shadow_x_mask; | |
3026 | else | |
3027 | spte |= shadow_nx_mask; | |
49fde340 | 3028 | |
1c4f1fd6 | 3029 | if (pte_access & ACC_USER_MASK) |
7b52345e | 3030 | spte |= shadow_user_mask; |
49fde340 | 3031 | |
852e3c19 | 3032 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 3033 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 3034 | if (tdp_enabled) |
afaf0b2f | 3035 | spte |= kvm_x86_ops.get_mt_mask(vcpu, gfn, |
d1fe9219 | 3036 | kvm_is_mmio_pfn(pfn)); |
1c4f1fd6 | 3037 | |
9bdbba13 | 3038 | if (host_writable) |
1403283a | 3039 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
3040 | else |
3041 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 3042 | |
daaf216c TL |
3043 | if (!kvm_is_mmio_pfn(pfn)) |
3044 | spte |= shadow_me_mask; | |
3045 | ||
35149e21 | 3046 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 | 3047 | |
c2288505 | 3048 | if (pte_access & ACC_WRITE_MASK) { |
49fde340 | 3049 | spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE; |
1c4f1fd6 | 3050 | |
ecc5589f MT |
3051 | /* |
3052 | * Optimization: for pte sync, if spte was writable the hash | |
3053 | * lookup is unnecessary (and expensive). Write protection | |
3054 | * is responsibility of mmu_get_page / kvm_sync_page. | |
3055 | * Same reasoning can be applied to dirty page accounting. | |
3056 | */ | |
8dae4445 | 3057 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
3058 | goto set_pte; |
3059 | ||
4731d4c7 | 3060 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 3061 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 3062 | __func__, gfn); |
5ce4786f | 3063 | ret |= SET_SPTE_WRITE_PROTECTED_PT; |
1c4f1fd6 | 3064 | pte_access &= ~ACC_WRITE_MASK; |
49fde340 | 3065 | spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE); |
1c4f1fd6 AK |
3066 | } |
3067 | } | |
3068 | ||
9b51a630 | 3069 | if (pte_access & ACC_WRITE_MASK) { |
54bf36aa | 3070 | kvm_vcpu_mark_page_dirty(vcpu, gfn); |
ac8d57e5 | 3071 | spte |= spte_shadow_dirty_mask(spte); |
9b51a630 | 3072 | } |
1c4f1fd6 | 3073 | |
f160c7b7 JS |
3074 | if (speculative) |
3075 | spte = mark_spte_for_access_track(spte); | |
3076 | ||
38187c83 | 3077 | set_pte: |
6e7d0354 | 3078 | if (mmu_spte_update(sptep, spte)) |
5ce4786f | 3079 | ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH; |
1e73f9dd MT |
3080 | return ret; |
3081 | } | |
3082 | ||
0a2b64c5 BG |
3083 | static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
3084 | unsigned int pte_access, int write_fault, int level, | |
3085 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, | |
3086 | bool host_writable) | |
1e73f9dd MT |
3087 | { |
3088 | int was_rmapped = 0; | |
53a27b39 | 3089 | int rmap_count; |
5ce4786f | 3090 | int set_spte_ret; |
9b8ebbdb | 3091 | int ret = RET_PF_RETRY; |
c2a4eadf | 3092 | bool flush = false; |
1e73f9dd | 3093 | |
f7616203 XG |
3094 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
3095 | *sptep, write_fault, gfn); | |
1e73f9dd | 3096 | |
afd28fe1 | 3097 | if (is_shadow_present_pte(*sptep)) { |
1e73f9dd MT |
3098 | /* |
3099 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
3100 | * the parent of the now unreachable PTE. | |
3101 | */ | |
852e3c19 JR |
3102 | if (level > PT_PAGE_TABLE_LEVEL && |
3103 | !is_large_pte(*sptep)) { | |
1e73f9dd | 3104 | struct kvm_mmu_page *child; |
d555c333 | 3105 | u64 pte = *sptep; |
1e73f9dd MT |
3106 | |
3107 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 3108 | drop_parent_pte(child, sptep); |
c2a4eadf | 3109 | flush = true; |
d555c333 | 3110 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 3111 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 3112 | spte_to_pfn(*sptep), pfn); |
c3707958 | 3113 | drop_spte(vcpu->kvm, sptep); |
c2a4eadf | 3114 | flush = true; |
6bed6b9e JR |
3115 | } else |
3116 | was_rmapped = 1; | |
1e73f9dd | 3117 | } |
852e3c19 | 3118 | |
5ce4786f JS |
3119 | set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn, |
3120 | speculative, true, host_writable); | |
3121 | if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) { | |
1e73f9dd | 3122 | if (write_fault) |
9b8ebbdb | 3123 | ret = RET_PF_EMULATE; |
77c3913b | 3124 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
a378b4e6 | 3125 | } |
c3134ce2 | 3126 | |
c2a4eadf | 3127 | if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush) |
c3134ce2 LT |
3128 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, |
3129 | KVM_PAGES_PER_HPAGE(level)); | |
1e73f9dd | 3130 | |
029499b4 | 3131 | if (unlikely(is_mmio_spte(*sptep))) |
9b8ebbdb | 3132 | ret = RET_PF_EMULATE; |
ce88decf | 3133 | |
d555c333 | 3134 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
335e192a | 3135 | trace_kvm_mmu_set_spte(level, gfn, sptep); |
d555c333 | 3136 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
3137 | ++vcpu->kvm->stat.lpages; |
3138 | ||
ffb61bb3 | 3139 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
3140 | if (!was_rmapped) { |
3141 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
3142 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
3143 | rmap_recycle(vcpu, sptep, gfn); | |
3144 | } | |
1c4f1fd6 | 3145 | } |
cb9aaa30 | 3146 | |
9b8ebbdb | 3147 | return ret; |
1c4f1fd6 AK |
3148 | } |
3149 | ||
ba049e93 | 3150 | static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
957ed9ef XG |
3151 | bool no_dirty_log) |
3152 | { | |
3153 | struct kvm_memory_slot *slot; | |
957ed9ef | 3154 | |
5d163b1c | 3155 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 3156 | if (!slot) |
6c8ee57b | 3157 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 3158 | |
037d92dc | 3159 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
3160 | } |
3161 | ||
3162 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
3163 | struct kvm_mmu_page *sp, | |
3164 | u64 *start, u64 *end) | |
3165 | { | |
3166 | struct page *pages[PTE_PREFETCH_NUM]; | |
d9ef13c2 | 3167 | struct kvm_memory_slot *slot; |
0a2b64c5 | 3168 | unsigned int access = sp->role.access; |
957ed9ef XG |
3169 | int i, ret; |
3170 | gfn_t gfn; | |
3171 | ||
3172 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
d9ef13c2 PB |
3173 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK); |
3174 | if (!slot) | |
957ed9ef XG |
3175 | return -1; |
3176 | ||
d9ef13c2 | 3177 | ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start); |
957ed9ef XG |
3178 | if (ret <= 0) |
3179 | return -1; | |
3180 | ||
43fdcda9 | 3181 | for (i = 0; i < ret; i++, gfn++, start++) { |
029499b4 TY |
3182 | mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn, |
3183 | page_to_pfn(pages[i]), true, true); | |
43fdcda9 JS |
3184 | put_page(pages[i]); |
3185 | } | |
957ed9ef XG |
3186 | |
3187 | return 0; | |
3188 | } | |
3189 | ||
3190 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
3191 | struct kvm_mmu_page *sp, u64 *sptep) | |
3192 | { | |
3193 | u64 *spte, *start = NULL; | |
3194 | int i; | |
3195 | ||
3196 | WARN_ON(!sp->role.direct); | |
3197 | ||
3198 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
3199 | spte = sp->spt + i; | |
3200 | ||
3201 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 3202 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
3203 | if (!start) |
3204 | continue; | |
3205 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
3206 | break; | |
3207 | start = NULL; | |
3208 | } else if (!start) | |
3209 | start = spte; | |
3210 | } | |
3211 | } | |
3212 | ||
3213 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
3214 | { | |
3215 | struct kvm_mmu_page *sp; | |
3216 | ||
ac8d57e5 PF |
3217 | sp = page_header(__pa(sptep)); |
3218 | ||
957ed9ef | 3219 | /* |
ac8d57e5 PF |
3220 | * Without accessed bits, there's no way to distinguish between |
3221 | * actually accessed translations and prefetched, so disable pte | |
3222 | * prefetch if accessed bits aren't available. | |
957ed9ef | 3223 | */ |
ac8d57e5 | 3224 | if (sp_ad_disabled(sp)) |
957ed9ef XG |
3225 | return; |
3226 | ||
957ed9ef XG |
3227 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
3228 | return; | |
3229 | ||
3230 | __direct_pte_prefetch(vcpu, sp, sptep); | |
3231 | } | |
3232 | ||
db543216 | 3233 | static int host_pfn_mapping_level(struct kvm_vcpu *vcpu, gfn_t gfn, |
293e306e | 3234 | kvm_pfn_t pfn, struct kvm_memory_slot *slot) |
db543216 | 3235 | { |
db543216 SC |
3236 | unsigned long hva; |
3237 | pte_t *pte; | |
3238 | int level; | |
3239 | ||
3240 | BUILD_BUG_ON(PT_PAGE_TABLE_LEVEL != (int)PG_LEVEL_4K || | |
3241 | PT_DIRECTORY_LEVEL != (int)PG_LEVEL_2M || | |
3242 | PT_PDPE_LEVEL != (int)PG_LEVEL_1G); | |
3243 | ||
e851265a | 3244 | if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn)) |
db543216 SC |
3245 | return PT_PAGE_TABLE_LEVEL; |
3246 | ||
293e306e SC |
3247 | /* |
3248 | * Note, using the already-retrieved memslot and __gfn_to_hva_memslot() | |
3249 | * is not solely for performance, it's also necessary to avoid the | |
3250 | * "writable" check in __gfn_to_hva_many(), which will always fail on | |
3251 | * read-only memslots due to gfn_to_hva() assuming writes. Earlier | |
3252 | * page fault steps have already verified the guest isn't writing a | |
3253 | * read-only memslot. | |
3254 | */ | |
db543216 SC |
3255 | hva = __gfn_to_hva_memslot(slot, gfn); |
3256 | ||
3257 | pte = lookup_address_in_mm(vcpu->kvm->mm, hva, &level); | |
3258 | if (unlikely(!pte)) | |
3259 | return PT_PAGE_TABLE_LEVEL; | |
3260 | ||
3261 | return level; | |
3262 | } | |
3263 | ||
83f06fa7 SC |
3264 | static int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn, |
3265 | int max_level, kvm_pfn_t *pfnp) | |
0885904d | 3266 | { |
293e306e | 3267 | struct kvm_memory_slot *slot; |
2c0629f4 | 3268 | struct kvm_lpage_info *linfo; |
0885904d | 3269 | kvm_pfn_t pfn = *pfnp; |
17eff019 | 3270 | kvm_pfn_t mask; |
83f06fa7 | 3271 | int level; |
17eff019 | 3272 | |
293e306e | 3273 | if (unlikely(max_level == PT_PAGE_TABLE_LEVEL)) |
83f06fa7 | 3274 | return PT_PAGE_TABLE_LEVEL; |
17eff019 | 3275 | |
e851265a | 3276 | if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn)) |
83f06fa7 | 3277 | return PT_PAGE_TABLE_LEVEL; |
17eff019 | 3278 | |
293e306e SC |
3279 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true); |
3280 | if (!slot) | |
3281 | return PT_PAGE_TABLE_LEVEL; | |
3282 | ||
703c335d | 3283 | max_level = min(max_level, max_page_level); |
293e306e | 3284 | for ( ; max_level > PT_PAGE_TABLE_LEVEL; max_level--) { |
2c0629f4 SC |
3285 | linfo = lpage_info_slot(gfn, slot, max_level); |
3286 | if (!linfo->disallow_lpage) | |
293e306e SC |
3287 | break; |
3288 | } | |
3289 | ||
3290 | if (max_level == PT_PAGE_TABLE_LEVEL) | |
3291 | return PT_PAGE_TABLE_LEVEL; | |
3292 | ||
3293 | level = host_pfn_mapping_level(vcpu, gfn, pfn, slot); | |
db543216 | 3294 | if (level == PT_PAGE_TABLE_LEVEL) |
83f06fa7 | 3295 | return level; |
17eff019 | 3296 | |
db543216 | 3297 | level = min(level, max_level); |
0885904d SC |
3298 | |
3299 | /* | |
17eff019 SC |
3300 | * mmu_notifier_retry() was successful and mmu_lock is held, so |
3301 | * the pmd can't be split from under us. | |
0885904d | 3302 | */ |
17eff019 SC |
3303 | mask = KVM_PAGES_PER_HPAGE(level) - 1; |
3304 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
3305 | *pfnp = pfn & ~mask; | |
83f06fa7 SC |
3306 | |
3307 | return level; | |
0885904d SC |
3308 | } |
3309 | ||
b8e8c830 PB |
3310 | static void disallowed_hugepage_adjust(struct kvm_shadow_walk_iterator it, |
3311 | gfn_t gfn, kvm_pfn_t *pfnp, int *levelp) | |
3312 | { | |
3313 | int level = *levelp; | |
3314 | u64 spte = *it.sptep; | |
3315 | ||
3316 | if (it.level == level && level > PT_PAGE_TABLE_LEVEL && | |
3317 | is_nx_huge_page_enabled() && | |
3318 | is_shadow_present_pte(spte) && | |
3319 | !is_large_pte(spte)) { | |
3320 | /* | |
3321 | * A small SPTE exists for this pfn, but FNAME(fetch) | |
3322 | * and __direct_map would like to create a large PTE | |
3323 | * instead: just force them to go down another level, | |
3324 | * patching back for them into pfn the next 9 bits of | |
3325 | * the address. | |
3326 | */ | |
3327 | u64 page_mask = KVM_PAGES_PER_HPAGE(level) - KVM_PAGES_PER_HPAGE(level - 1); | |
3328 | *pfnp |= gfn & page_mask; | |
3329 | (*levelp)--; | |
3330 | } | |
3331 | } | |
3332 | ||
3fcf2d1b | 3333 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, int write, |
83f06fa7 SC |
3334 | int map_writable, int max_level, kvm_pfn_t pfn, |
3335 | bool prefault, bool account_disallowed_nx_lpage) | |
140754bc | 3336 | { |
3fcf2d1b | 3337 | struct kvm_shadow_walk_iterator it; |
140754bc | 3338 | struct kvm_mmu_page *sp; |
83f06fa7 | 3339 | int level, ret; |
3fcf2d1b PB |
3340 | gfn_t gfn = gpa >> PAGE_SHIFT; |
3341 | gfn_t base_gfn = gfn; | |
6aa8b732 | 3342 | |
0c7a98e3 | 3343 | if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa))) |
3fcf2d1b | 3344 | return RET_PF_RETRY; |
989c6b34 | 3345 | |
83f06fa7 | 3346 | level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn); |
4cd071d1 | 3347 | |
335e192a | 3348 | trace_kvm_mmu_spte_requested(gpa, level, pfn); |
3fcf2d1b | 3349 | for_each_shadow_entry(vcpu, gpa, it) { |
b8e8c830 PB |
3350 | /* |
3351 | * We cannot overwrite existing page tables with an NX | |
3352 | * large page, as the leaf could be executable. | |
3353 | */ | |
3354 | disallowed_hugepage_adjust(it, gfn, &pfn, &level); | |
3355 | ||
3fcf2d1b PB |
3356 | base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
3357 | if (it.level == level) | |
9f652d21 | 3358 | break; |
6aa8b732 | 3359 | |
3fcf2d1b PB |
3360 | drop_large_spte(vcpu, it.sptep); |
3361 | if (!is_shadow_present_pte(*it.sptep)) { | |
3362 | sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr, | |
3363 | it.level - 1, true, ACC_ALL); | |
c9fa0b3b | 3364 | |
3fcf2d1b | 3365 | link_shadow_page(vcpu, it.sptep, sp); |
2cb70fd4 | 3366 | if (account_disallowed_nx_lpage) |
b8e8c830 | 3367 | account_huge_nx_page(vcpu->kvm, sp); |
9f652d21 AK |
3368 | } |
3369 | } | |
3fcf2d1b PB |
3370 | |
3371 | ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL, | |
3372 | write, level, base_gfn, pfn, prefault, | |
3373 | map_writable); | |
3374 | direct_pte_prefetch(vcpu, it.sptep); | |
3375 | ++vcpu->stat.pf_fixed; | |
3376 | return ret; | |
6aa8b732 AK |
3377 | } |
3378 | ||
77db5cbd | 3379 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 3380 | { |
585a8b9b | 3381 | send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk); |
bf998156 HY |
3382 | } |
3383 | ||
ba049e93 | 3384 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn) |
bf998156 | 3385 | { |
4d8b81ab XG |
3386 | /* |
3387 | * Do not cache the mmio info caused by writing the readonly gfn | |
3388 | * into the spte otherwise read access on readonly gfn also can | |
3389 | * caused mmio page fault and treat it as mmio access. | |
4d8b81ab XG |
3390 | */ |
3391 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
9b8ebbdb | 3392 | return RET_PF_EMULATE; |
4d8b81ab | 3393 | |
e6c1502b | 3394 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
54bf36aa | 3395 | kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current); |
9b8ebbdb | 3396 | return RET_PF_RETRY; |
d7c55201 | 3397 | } |
edba23e5 | 3398 | |
2c151b25 | 3399 | return -EFAULT; |
bf998156 HY |
3400 | } |
3401 | ||
d7c55201 | 3402 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
0a2b64c5 BG |
3403 | kvm_pfn_t pfn, unsigned int access, |
3404 | int *ret_val) | |
d7c55201 | 3405 | { |
d7c55201 | 3406 | /* The pfn is invalid, report the error! */ |
81c52c56 | 3407 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 | 3408 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
798e88b3 | 3409 | return true; |
d7c55201 XG |
3410 | } |
3411 | ||
ce88decf | 3412 | if (unlikely(is_noslot_pfn(pfn))) |
4af77151 SC |
3413 | vcpu_cache_mmio_info(vcpu, gva, gfn, |
3414 | access & shadow_mmio_access_mask); | |
d7c55201 | 3415 | |
798e88b3 | 3416 | return false; |
d7c55201 XG |
3417 | } |
3418 | ||
e5552fd2 | 3419 | static bool page_fault_can_be_fast(u32 error_code) |
c7ba5b48 | 3420 | { |
1c118b82 XG |
3421 | /* |
3422 | * Do not fix the mmio spte with invalid generation number which | |
3423 | * need to be updated by slow page fault path. | |
3424 | */ | |
3425 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3426 | return false; | |
3427 | ||
f160c7b7 JS |
3428 | /* See if the page fault is due to an NX violation */ |
3429 | if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)) | |
3430 | == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)))) | |
3431 | return false; | |
3432 | ||
c7ba5b48 | 3433 | /* |
f160c7b7 JS |
3434 | * #PF can be fast if: |
3435 | * 1. The shadow page table entry is not present, which could mean that | |
3436 | * the fault is potentially caused by access tracking (if enabled). | |
3437 | * 2. The shadow page table entry is present and the fault | |
3438 | * is caused by write-protect, that means we just need change the W | |
3439 | * bit of the spte which can be done out of mmu-lock. | |
3440 | * | |
3441 | * However, if access tracking is disabled we know that a non-present | |
3442 | * page must be a genuine page fault where we have to create a new SPTE. | |
3443 | * So, if access tracking is disabled, we return true only for write | |
3444 | * accesses to a present page. | |
c7ba5b48 | 3445 | */ |
c7ba5b48 | 3446 | |
f160c7b7 JS |
3447 | return shadow_acc_track_mask != 0 || |
3448 | ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)) | |
3449 | == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)); | |
c7ba5b48 XG |
3450 | } |
3451 | ||
97dceba2 JS |
3452 | /* |
3453 | * Returns true if the SPTE was fixed successfully. Otherwise, | |
3454 | * someone else modified the SPTE from its original value. | |
3455 | */ | |
c7ba5b48 | 3456 | static bool |
92a476cb | 3457 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d3e328f2 | 3458 | u64 *sptep, u64 old_spte, u64 new_spte) |
c7ba5b48 | 3459 | { |
c7ba5b48 XG |
3460 | gfn_t gfn; |
3461 | ||
3462 | WARN_ON(!sp->role.direct); | |
3463 | ||
9b51a630 KH |
3464 | /* |
3465 | * Theoretically we could also set dirty bit (and flush TLB) here in | |
3466 | * order to eliminate unnecessary PML logging. See comments in | |
3467 | * set_spte. But fast_page_fault is very unlikely to happen with PML | |
3468 | * enabled, so we do not do this. This might result in the same GPA | |
3469 | * to be logged in PML buffer again when the write really happens, and | |
3470 | * eventually to be called by mark_page_dirty twice. But it's also no | |
3471 | * harm. This also avoids the TLB flush needed after setting dirty bit | |
3472 | * so non-PML cases won't be impacted. | |
3473 | * | |
3474 | * Compare with set_spte where instead shadow_dirty_mask is set. | |
3475 | */ | |
f160c7b7 | 3476 | if (cmpxchg64(sptep, old_spte, new_spte) != old_spte) |
97dceba2 JS |
3477 | return false; |
3478 | ||
d3e328f2 | 3479 | if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) { |
f160c7b7 JS |
3480 | /* |
3481 | * The gfn of direct spte is stable since it is | |
3482 | * calculated by sp->gfn. | |
3483 | */ | |
3484 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
3485 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
3486 | } | |
c7ba5b48 XG |
3487 | |
3488 | return true; | |
3489 | } | |
3490 | ||
d3e328f2 JS |
3491 | static bool is_access_allowed(u32 fault_err_code, u64 spte) |
3492 | { | |
3493 | if (fault_err_code & PFERR_FETCH_MASK) | |
3494 | return is_executable_pte(spte); | |
3495 | ||
3496 | if (fault_err_code & PFERR_WRITE_MASK) | |
3497 | return is_writable_pte(spte); | |
3498 | ||
3499 | /* Fault was on Read access */ | |
3500 | return spte & PT_PRESENT_MASK; | |
3501 | } | |
3502 | ||
c7ba5b48 XG |
3503 | /* |
3504 | * Return value: | |
3505 | * - true: let the vcpu to access on the same address again. | |
3506 | * - false: let the real page fault path to fix it. | |
3507 | */ | |
f9fa2509 | 3508 | static bool fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
c7ba5b48 XG |
3509 | u32 error_code) |
3510 | { | |
3511 | struct kvm_shadow_walk_iterator iterator; | |
92a476cb | 3512 | struct kvm_mmu_page *sp; |
97dceba2 | 3513 | bool fault_handled = false; |
c7ba5b48 | 3514 | u64 spte = 0ull; |
97dceba2 | 3515 | uint retry_count = 0; |
c7ba5b48 | 3516 | |
e5552fd2 | 3517 | if (!page_fault_can_be_fast(error_code)) |
c7ba5b48 XG |
3518 | return false; |
3519 | ||
3520 | walk_shadow_page_lockless_begin(vcpu); | |
c7ba5b48 | 3521 | |
97dceba2 | 3522 | do { |
d3e328f2 | 3523 | u64 new_spte; |
c7ba5b48 | 3524 | |
736c291c | 3525 | for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte) |
f9fa2509 | 3526 | if (!is_shadow_present_pte(spte)) |
d162f30a JS |
3527 | break; |
3528 | ||
97dceba2 JS |
3529 | sp = page_header(__pa(iterator.sptep)); |
3530 | if (!is_last_spte(spte, sp->role.level)) | |
3531 | break; | |
c7ba5b48 | 3532 | |
97dceba2 | 3533 | /* |
f160c7b7 JS |
3534 | * Check whether the memory access that caused the fault would |
3535 | * still cause it if it were to be performed right now. If not, | |
3536 | * then this is a spurious fault caused by TLB lazily flushed, | |
3537 | * or some other CPU has already fixed the PTE after the | |
3538 | * current CPU took the fault. | |
97dceba2 JS |
3539 | * |
3540 | * Need not check the access of upper level table entries since | |
3541 | * they are always ACC_ALL. | |
3542 | */ | |
d3e328f2 JS |
3543 | if (is_access_allowed(error_code, spte)) { |
3544 | fault_handled = true; | |
3545 | break; | |
3546 | } | |
f160c7b7 | 3547 | |
d3e328f2 JS |
3548 | new_spte = spte; |
3549 | ||
3550 | if (is_access_track_spte(spte)) | |
3551 | new_spte = restore_acc_track_spte(new_spte); | |
3552 | ||
3553 | /* | |
3554 | * Currently, to simplify the code, write-protection can | |
3555 | * be removed in the fast path only if the SPTE was | |
3556 | * write-protected for dirty-logging or access tracking. | |
3557 | */ | |
3558 | if ((error_code & PFERR_WRITE_MASK) && | |
e6302698 | 3559 | spte_can_locklessly_be_made_writable(spte)) { |
d3e328f2 | 3560 | new_spte |= PT_WRITABLE_MASK; |
f160c7b7 JS |
3561 | |
3562 | /* | |
d3e328f2 JS |
3563 | * Do not fix write-permission on the large spte. Since |
3564 | * we only dirty the first page into the dirty-bitmap in | |
3565 | * fast_pf_fix_direct_spte(), other pages are missed | |
3566 | * if its slot has dirty logging enabled. | |
3567 | * | |
3568 | * Instead, we let the slow page fault path create a | |
3569 | * normal spte to fix the access. | |
3570 | * | |
3571 | * See the comments in kvm_arch_commit_memory_region(). | |
f160c7b7 | 3572 | */ |
d3e328f2 | 3573 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
f160c7b7 | 3574 | break; |
97dceba2 | 3575 | } |
c7ba5b48 | 3576 | |
f160c7b7 | 3577 | /* Verify that the fault can be handled in the fast path */ |
d3e328f2 JS |
3578 | if (new_spte == spte || |
3579 | !is_access_allowed(error_code, new_spte)) | |
97dceba2 JS |
3580 | break; |
3581 | ||
3582 | /* | |
3583 | * Currently, fast page fault only works for direct mapping | |
3584 | * since the gfn is not stable for indirect shadow page. See | |
2f5947df | 3585 | * Documentation/virt/kvm/locking.txt to get more detail. |
97dceba2 JS |
3586 | */ |
3587 | fault_handled = fast_pf_fix_direct_spte(vcpu, sp, | |
f160c7b7 | 3588 | iterator.sptep, spte, |
d3e328f2 | 3589 | new_spte); |
97dceba2 JS |
3590 | if (fault_handled) |
3591 | break; | |
3592 | ||
3593 | if (++retry_count > 4) { | |
3594 | printk_once(KERN_WARNING | |
3595 | "kvm: Fast #PF retrying more than 4 times.\n"); | |
3596 | break; | |
3597 | } | |
3598 | ||
97dceba2 | 3599 | } while (true); |
c126d94f | 3600 | |
736c291c | 3601 | trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep, |
97dceba2 | 3602 | spte, fault_handled); |
c7ba5b48 XG |
3603 | walk_shadow_page_lockless_end(vcpu); |
3604 | ||
97dceba2 | 3605 | return fault_handled; |
c7ba5b48 XG |
3606 | } |
3607 | ||
74b566e6 JS |
3608 | static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa, |
3609 | struct list_head *invalid_list) | |
17ac10ad | 3610 | { |
4db35314 | 3611 | struct kvm_mmu_page *sp; |
17ac10ad | 3612 | |
74b566e6 | 3613 | if (!VALID_PAGE(*root_hpa)) |
7b53aa56 | 3614 | return; |
35af577a | 3615 | |
74b566e6 JS |
3616 | sp = page_header(*root_hpa & PT64_BASE_ADDR_MASK); |
3617 | --sp->root_count; | |
3618 | if (!sp->root_count && sp->role.invalid) | |
3619 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); | |
17ac10ad | 3620 | |
74b566e6 JS |
3621 | *root_hpa = INVALID_PAGE; |
3622 | } | |
3623 | ||
08fb59d8 | 3624 | /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */ |
6a82cd1c VK |
3625 | void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
3626 | ulong roots_to_free) | |
74b566e6 JS |
3627 | { |
3628 | int i; | |
3629 | LIST_HEAD(invalid_list); | |
08fb59d8 | 3630 | bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT; |
74b566e6 | 3631 | |
b94742c9 | 3632 | BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG); |
74b566e6 | 3633 | |
08fb59d8 | 3634 | /* Before acquiring the MMU lock, see if we need to do any real work. */ |
b94742c9 JS |
3635 | if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) { |
3636 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
3637 | if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) && | |
3638 | VALID_PAGE(mmu->prev_roots[i].hpa)) | |
3639 | break; | |
3640 | ||
3641 | if (i == KVM_MMU_NUM_PREV_ROOTS) | |
3642 | return; | |
3643 | } | |
35af577a GN |
3644 | |
3645 | spin_lock(&vcpu->kvm->mmu_lock); | |
17ac10ad | 3646 | |
b94742c9 JS |
3647 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) |
3648 | if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) | |
3649 | mmu_free_root_page(vcpu->kvm, &mmu->prev_roots[i].hpa, | |
3650 | &invalid_list); | |
7c390d35 | 3651 | |
08fb59d8 JS |
3652 | if (free_active_root) { |
3653 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
3654 | (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) { | |
3655 | mmu_free_root_page(vcpu->kvm, &mmu->root_hpa, | |
3656 | &invalid_list); | |
3657 | } else { | |
3658 | for (i = 0; i < 4; ++i) | |
3659 | if (mmu->pae_root[i] != 0) | |
3660 | mmu_free_root_page(vcpu->kvm, | |
3661 | &mmu->pae_root[i], | |
3662 | &invalid_list); | |
3663 | mmu->root_hpa = INVALID_PAGE; | |
3664 | } | |
ad7dc69a | 3665 | mmu->root_cr3 = 0; |
17ac10ad | 3666 | } |
74b566e6 | 3667 | |
d98ba053 | 3668 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 3669 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad | 3670 | } |
74b566e6 | 3671 | EXPORT_SYMBOL_GPL(kvm_mmu_free_roots); |
17ac10ad | 3672 | |
8986ecc0 MT |
3673 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
3674 | { | |
3675 | int ret = 0; | |
3676 | ||
3677 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 3678 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
3679 | ret = 1; |
3680 | } | |
3681 | ||
3682 | return ret; | |
3683 | } | |
3684 | ||
651dd37a JR |
3685 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
3686 | { | |
3687 | struct kvm_mmu_page *sp; | |
7ebaf15e | 3688 | unsigned i; |
651dd37a | 3689 | |
44dd3ffa | 3690 | if (vcpu->arch.mmu->shadow_root_level >= PT64_ROOT_4LEVEL) { |
651dd37a | 3691 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3692 | if(make_mmu_pages_available(vcpu) < 0) { |
3693 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3694 | return -ENOSPC; |
26eeb53c | 3695 | } |
855feb67 | 3696 | sp = kvm_mmu_get_page(vcpu, 0, 0, |
44dd3ffa | 3697 | vcpu->arch.mmu->shadow_root_level, 1, ACC_ALL); |
651dd37a JR |
3698 | ++sp->root_count; |
3699 | spin_unlock(&vcpu->kvm->mmu_lock); | |
44dd3ffa VK |
3700 | vcpu->arch.mmu->root_hpa = __pa(sp->spt); |
3701 | } else if (vcpu->arch.mmu->shadow_root_level == PT32E_ROOT_LEVEL) { | |
651dd37a | 3702 | for (i = 0; i < 4; ++i) { |
44dd3ffa | 3703 | hpa_t root = vcpu->arch.mmu->pae_root[i]; |
651dd37a | 3704 | |
fa4a2c08 | 3705 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3706 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3707 | if (make_mmu_pages_available(vcpu) < 0) { |
3708 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3709 | return -ENOSPC; |
26eeb53c | 3710 | } |
649497d1 | 3711 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
bb11c6c9 | 3712 | i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL); |
651dd37a JR |
3713 | root = __pa(sp->spt); |
3714 | ++sp->root_count; | |
3715 | spin_unlock(&vcpu->kvm->mmu_lock); | |
44dd3ffa | 3716 | vcpu->arch.mmu->pae_root[i] = root | PT_PRESENT_MASK; |
651dd37a | 3717 | } |
44dd3ffa | 3718 | vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root); |
651dd37a JR |
3719 | } else |
3720 | BUG(); | |
3651c7fc SC |
3721 | |
3722 | /* root_cr3 is ignored for direct MMUs. */ | |
3723 | vcpu->arch.mmu->root_cr3 = 0; | |
651dd37a JR |
3724 | |
3725 | return 0; | |
3726 | } | |
3727 | ||
3728 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 3729 | { |
4db35314 | 3730 | struct kvm_mmu_page *sp; |
81407ca5 | 3731 | u64 pdptr, pm_mask; |
ad7dc69a | 3732 | gfn_t root_gfn, root_cr3; |
81407ca5 | 3733 | int i; |
3bb65a22 | 3734 | |
d8dd54e0 | 3735 | root_cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu); |
ad7dc69a | 3736 | root_gfn = root_cr3 >> PAGE_SHIFT; |
17ac10ad | 3737 | |
651dd37a JR |
3738 | if (mmu_check_root(vcpu, root_gfn)) |
3739 | return 1; | |
3740 | ||
3741 | /* | |
3742 | * Do we shadow a long mode page table? If so we need to | |
3743 | * write-protect the guests page table root. | |
3744 | */ | |
44dd3ffa VK |
3745 | if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) { |
3746 | hpa_t root = vcpu->arch.mmu->root_hpa; | |
17ac10ad | 3747 | |
fa4a2c08 | 3748 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3749 | |
8facbbff | 3750 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3751 | if (make_mmu_pages_available(vcpu) < 0) { |
3752 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3753 | return -ENOSPC; |
26eeb53c | 3754 | } |
855feb67 | 3755 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, |
44dd3ffa | 3756 | vcpu->arch.mmu->shadow_root_level, 0, ACC_ALL); |
4db35314 AK |
3757 | root = __pa(sp->spt); |
3758 | ++sp->root_count; | |
8facbbff | 3759 | spin_unlock(&vcpu->kvm->mmu_lock); |
44dd3ffa | 3760 | vcpu->arch.mmu->root_hpa = root; |
ad7dc69a | 3761 | goto set_root_cr3; |
17ac10ad | 3762 | } |
f87f9288 | 3763 | |
651dd37a JR |
3764 | /* |
3765 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3766 | * or a PAE 3-level page table. In either case we need to be aware that |
3767 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3768 | */ |
81407ca5 | 3769 | pm_mask = PT_PRESENT_MASK; |
44dd3ffa | 3770 | if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) |
81407ca5 JR |
3771 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; |
3772 | ||
17ac10ad | 3773 | for (i = 0; i < 4; ++i) { |
44dd3ffa | 3774 | hpa_t root = vcpu->arch.mmu->pae_root[i]; |
17ac10ad | 3775 | |
fa4a2c08 | 3776 | MMU_WARN_ON(VALID_PAGE(root)); |
44dd3ffa VK |
3777 | if (vcpu->arch.mmu->root_level == PT32E_ROOT_LEVEL) { |
3778 | pdptr = vcpu->arch.mmu->get_pdptr(vcpu, i); | |
812f30b2 | 3779 | if (!(pdptr & PT_PRESENT_MASK)) { |
44dd3ffa | 3780 | vcpu->arch.mmu->pae_root[i] = 0; |
417726a3 AK |
3781 | continue; |
3782 | } | |
6de4f3ad | 3783 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
3784 | if (mmu_check_root(vcpu, root_gfn)) |
3785 | return 1; | |
5a7388c2 | 3786 | } |
8facbbff | 3787 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3788 | if (make_mmu_pages_available(vcpu) < 0) { |
3789 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3790 | return -ENOSPC; |
26eeb53c | 3791 | } |
bb11c6c9 TY |
3792 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL, |
3793 | 0, ACC_ALL); | |
4db35314 AK |
3794 | root = __pa(sp->spt); |
3795 | ++sp->root_count; | |
8facbbff AK |
3796 | spin_unlock(&vcpu->kvm->mmu_lock); |
3797 | ||
44dd3ffa | 3798 | vcpu->arch.mmu->pae_root[i] = root | pm_mask; |
17ac10ad | 3799 | } |
44dd3ffa | 3800 | vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root); |
81407ca5 JR |
3801 | |
3802 | /* | |
3803 | * If we shadow a 32 bit page table with a long mode page | |
3804 | * table we enter this path. | |
3805 | */ | |
44dd3ffa VK |
3806 | if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) { |
3807 | if (vcpu->arch.mmu->lm_root == NULL) { | |
81407ca5 JR |
3808 | /* |
3809 | * The additional page necessary for this is only | |
3810 | * allocated on demand. | |
3811 | */ | |
3812 | ||
3813 | u64 *lm_root; | |
3814 | ||
254272ce | 3815 | lm_root = (void*)get_zeroed_page(GFP_KERNEL_ACCOUNT); |
81407ca5 JR |
3816 | if (lm_root == NULL) |
3817 | return 1; | |
3818 | ||
44dd3ffa | 3819 | lm_root[0] = __pa(vcpu->arch.mmu->pae_root) | pm_mask; |
81407ca5 | 3820 | |
44dd3ffa | 3821 | vcpu->arch.mmu->lm_root = lm_root; |
81407ca5 JR |
3822 | } |
3823 | ||
44dd3ffa | 3824 | vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->lm_root); |
81407ca5 JR |
3825 | } |
3826 | ||
ad7dc69a VK |
3827 | set_root_cr3: |
3828 | vcpu->arch.mmu->root_cr3 = root_cr3; | |
3829 | ||
8986ecc0 | 3830 | return 0; |
17ac10ad AK |
3831 | } |
3832 | ||
651dd37a JR |
3833 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
3834 | { | |
44dd3ffa | 3835 | if (vcpu->arch.mmu->direct_map) |
651dd37a JR |
3836 | return mmu_alloc_direct_roots(vcpu); |
3837 | else | |
3838 | return mmu_alloc_shadow_roots(vcpu); | |
3839 | } | |
3840 | ||
578e1c4d | 3841 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) |
0ba73cda MT |
3842 | { |
3843 | int i; | |
3844 | struct kvm_mmu_page *sp; | |
3845 | ||
44dd3ffa | 3846 | if (vcpu->arch.mmu->direct_map) |
81407ca5 JR |
3847 | return; |
3848 | ||
44dd3ffa | 3849 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
0ba73cda | 3850 | return; |
6903074c | 3851 | |
56f17dd3 | 3852 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); |
578e1c4d | 3853 | |
44dd3ffa VK |
3854 | if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) { |
3855 | hpa_t root = vcpu->arch.mmu->root_hpa; | |
0ba73cda | 3856 | sp = page_header(root); |
578e1c4d JS |
3857 | |
3858 | /* | |
3859 | * Even if another CPU was marking the SP as unsync-ed | |
3860 | * simultaneously, any guest page table changes are not | |
3861 | * guaranteed to be visible anyway until this VCPU issues a TLB | |
3862 | * flush strictly after those changes are made. We only need to | |
3863 | * ensure that the other CPU sets these flags before any actual | |
3864 | * changes to the page tables are made. The comments in | |
3865 | * mmu_need_write_protect() describe what could go wrong if this | |
3866 | * requirement isn't satisfied. | |
3867 | */ | |
3868 | if (!smp_load_acquire(&sp->unsync) && | |
3869 | !smp_load_acquire(&sp->unsync_children)) | |
3870 | return; | |
3871 | ||
3872 | spin_lock(&vcpu->kvm->mmu_lock); | |
3873 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); | |
3874 | ||
0ba73cda | 3875 | mmu_sync_children(vcpu, sp); |
578e1c4d | 3876 | |
0375f7fa | 3877 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
578e1c4d | 3878 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3879 | return; |
3880 | } | |
578e1c4d JS |
3881 | |
3882 | spin_lock(&vcpu->kvm->mmu_lock); | |
3883 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); | |
3884 | ||
0ba73cda | 3885 | for (i = 0; i < 4; ++i) { |
44dd3ffa | 3886 | hpa_t root = vcpu->arch.mmu->pae_root[i]; |
0ba73cda | 3887 | |
8986ecc0 | 3888 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
3889 | root &= PT64_BASE_ADDR_MASK; |
3890 | sp = page_header(root); | |
3891 | mmu_sync_children(vcpu, sp); | |
3892 | } | |
3893 | } | |
0ba73cda | 3894 | |
578e1c4d | 3895 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
6cffe8ca | 3896 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3897 | } |
bfd0a56b | 3898 | EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots); |
0ba73cda | 3899 | |
736c291c | 3900 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr, |
ab9ae313 | 3901 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3902 | { |
ab9ae313 AK |
3903 | if (exception) |
3904 | exception->error_code = 0; | |
6aa8b732 AK |
3905 | return vaddr; |
3906 | } | |
3907 | ||
736c291c | 3908 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr, |
ab9ae313 AK |
3909 | u32 access, |
3910 | struct x86_exception *exception) | |
6539e738 | 3911 | { |
ab9ae313 AK |
3912 | if (exception) |
3913 | exception->error_code = 0; | |
54987b7a | 3914 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception); |
6539e738 JR |
3915 | } |
3916 | ||
d625b155 XG |
3917 | static bool |
3918 | __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level) | |
3919 | { | |
b5c3c1b3 | 3920 | int bit7 = (pte >> 7) & 1; |
d625b155 | 3921 | |
b5c3c1b3 | 3922 | return pte & rsvd_check->rsvd_bits_mask[bit7][level-1]; |
d625b155 XG |
3923 | } |
3924 | ||
b5c3c1b3 | 3925 | static bool __is_bad_mt_xwr(struct rsvd_bits_validate *rsvd_check, u64 pte) |
d625b155 | 3926 | { |
b5c3c1b3 | 3927 | return rsvd_check->bad_mt_xwr & BIT_ULL(pte & 0x3f); |
d625b155 XG |
3928 | } |
3929 | ||
ded58749 | 3930 | static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf | 3931 | { |
9034e6e8 PB |
3932 | /* |
3933 | * A nested guest cannot use the MMIO cache if it is using nested | |
3934 | * page tables, because cr2 is a nGPA while the cache stores GPAs. | |
3935 | */ | |
3936 | if (mmu_is_nested(vcpu)) | |
3937 | return false; | |
3938 | ||
ce88decf XG |
3939 | if (direct) |
3940 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3941 | ||
3942 | return vcpu_match_mmio_gva(vcpu, addr); | |
3943 | } | |
3944 | ||
47ab8751 XG |
3945 | /* return true if reserved bit is detected on spte. */ |
3946 | static bool | |
3947 | walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep) | |
ce88decf XG |
3948 | { |
3949 | struct kvm_shadow_walk_iterator iterator; | |
2a7266a8 | 3950 | u64 sptes[PT64_ROOT_MAX_LEVEL], spte = 0ull; |
b5c3c1b3 | 3951 | struct rsvd_bits_validate *rsvd_check; |
47ab8751 XG |
3952 | int root, leaf; |
3953 | bool reserved = false; | |
ce88decf | 3954 | |
b5c3c1b3 | 3955 | rsvd_check = &vcpu->arch.mmu->shadow_zero_check; |
37f6a4e2 | 3956 | |
ce88decf | 3957 | walk_shadow_page_lockless_begin(vcpu); |
47ab8751 | 3958 | |
29ecd660 PB |
3959 | for (shadow_walk_init(&iterator, vcpu, addr), |
3960 | leaf = root = iterator.level; | |
47ab8751 XG |
3961 | shadow_walk_okay(&iterator); |
3962 | __shadow_walk_next(&iterator, spte)) { | |
47ab8751 XG |
3963 | spte = mmu_spte_get_lockless(iterator.sptep); |
3964 | ||
3965 | sptes[leaf - 1] = spte; | |
29ecd660 | 3966 | leaf--; |
47ab8751 | 3967 | |
ce88decf XG |
3968 | if (!is_shadow_present_pte(spte)) |
3969 | break; | |
47ab8751 | 3970 | |
b5c3c1b3 SC |
3971 | /* |
3972 | * Use a bitwise-OR instead of a logical-OR to aggregate the | |
3973 | * reserved bit and EPT's invalid memtype/XWR checks to avoid | |
3974 | * adding a Jcc in the loop. | |
3975 | */ | |
3976 | reserved |= __is_bad_mt_xwr(rsvd_check, spte) | | |
3977 | __is_rsvd_bits_set(rsvd_check, spte, iterator.level); | |
47ab8751 XG |
3978 | } |
3979 | ||
ce88decf XG |
3980 | walk_shadow_page_lockless_end(vcpu); |
3981 | ||
47ab8751 XG |
3982 | if (reserved) { |
3983 | pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n", | |
3984 | __func__, addr); | |
29ecd660 | 3985 | while (root > leaf) { |
47ab8751 XG |
3986 | pr_err("------ spte 0x%llx level %d.\n", |
3987 | sptes[root - 1], root); | |
3988 | root--; | |
3989 | } | |
3990 | } | |
ddce6208 | 3991 | |
47ab8751 XG |
3992 | *sptep = spte; |
3993 | return reserved; | |
ce88decf XG |
3994 | } |
3995 | ||
e08d26f0 | 3996 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf XG |
3997 | { |
3998 | u64 spte; | |
47ab8751 | 3999 | bool reserved; |
ce88decf | 4000 | |
ded58749 | 4001 | if (mmio_info_in_cache(vcpu, addr, direct)) |
9b8ebbdb | 4002 | return RET_PF_EMULATE; |
ce88decf | 4003 | |
47ab8751 | 4004 | reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte); |
450869d6 | 4005 | if (WARN_ON(reserved)) |
9b8ebbdb | 4006 | return -EINVAL; |
ce88decf XG |
4007 | |
4008 | if (is_mmio_spte(spte)) { | |
4009 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
0a2b64c5 | 4010 | unsigned int access = get_mmio_spte_access(spte); |
ce88decf | 4011 | |
54bf36aa | 4012 | if (!check_mmio_spte(vcpu, spte)) |
9b8ebbdb | 4013 | return RET_PF_INVALID; |
f8f55942 | 4014 | |
ce88decf XG |
4015 | if (direct) |
4016 | addr = 0; | |
4f022648 XG |
4017 | |
4018 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf | 4019 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
9b8ebbdb | 4020 | return RET_PF_EMULATE; |
ce88decf XG |
4021 | } |
4022 | ||
ce88decf XG |
4023 | /* |
4024 | * If the page table is zapped by other cpus, let CPU fault again on | |
4025 | * the address. | |
4026 | */ | |
9b8ebbdb | 4027 | return RET_PF_RETRY; |
ce88decf | 4028 | } |
ce88decf | 4029 | |
3d0c27ad XG |
4030 | static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu, |
4031 | u32 error_code, gfn_t gfn) | |
4032 | { | |
4033 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
4034 | return false; | |
4035 | ||
4036 | if (!(error_code & PFERR_PRESENT_MASK) || | |
4037 | !(error_code & PFERR_WRITE_MASK)) | |
4038 | return false; | |
4039 | ||
4040 | /* | |
4041 | * guest is writing the page which is write tracked which can | |
4042 | * not be fixed by page fault handler. | |
4043 | */ | |
4044 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) | |
4045 | return true; | |
4046 | ||
4047 | return false; | |
4048 | } | |
4049 | ||
e5691a81 XG |
4050 | static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr) |
4051 | { | |
4052 | struct kvm_shadow_walk_iterator iterator; | |
4053 | u64 spte; | |
4054 | ||
e5691a81 XG |
4055 | walk_shadow_page_lockless_begin(vcpu); |
4056 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
4057 | clear_sp_write_flooding_count(iterator.sptep); | |
4058 | if (!is_shadow_present_pte(spte)) | |
4059 | break; | |
4060 | } | |
4061 | walk_shadow_page_lockless_end(vcpu); | |
4062 | } | |
4063 | ||
9f1a8526 SC |
4064 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
4065 | gfn_t gfn) | |
af585b92 GN |
4066 | { |
4067 | struct kvm_arch_async_pf arch; | |
fb67e14f | 4068 | |
7c90705b | 4069 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 4070 | arch.gfn = gfn; |
44dd3ffa | 4071 | arch.direct_map = vcpu->arch.mmu->direct_map; |
d8dd54e0 | 4072 | arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu); |
af585b92 | 4073 | |
9f1a8526 SC |
4074 | return kvm_setup_async_pf(vcpu, cr2_or_gpa, |
4075 | kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch); | |
af585b92 GN |
4076 | } |
4077 | ||
78b2c54a | 4078 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
9f1a8526 SC |
4079 | gpa_t cr2_or_gpa, kvm_pfn_t *pfn, bool write, |
4080 | bool *writable) | |
af585b92 | 4081 | { |
3520469d | 4082 | struct kvm_memory_slot *slot; |
af585b92 GN |
4083 | bool async; |
4084 | ||
3a2936de JM |
4085 | /* |
4086 | * Don't expose private memslots to L2. | |
4087 | */ | |
4088 | if (is_guest_mode(vcpu) && !kvm_is_visible_gfn(vcpu->kvm, gfn)) { | |
4089 | *pfn = KVM_PFN_NOSLOT; | |
4090 | return false; | |
4091 | } | |
4092 | ||
54bf36aa | 4093 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
3520469d PB |
4094 | async = false; |
4095 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable); | |
af585b92 GN |
4096 | if (!async) |
4097 | return false; /* *pfn has correct page already */ | |
4098 | ||
9bc1f09f | 4099 | if (!prefault && kvm_can_do_async_pf(vcpu)) { |
9f1a8526 | 4100 | trace_kvm_try_async_get_page(cr2_or_gpa, gfn); |
af585b92 | 4101 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
9f1a8526 | 4102 | trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn); |
af585b92 GN |
4103 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); |
4104 | return true; | |
9f1a8526 | 4105 | } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn)) |
af585b92 GN |
4106 | return true; |
4107 | } | |
4108 | ||
3520469d | 4109 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable); |
af585b92 GN |
4110 | return false; |
4111 | } | |
4112 | ||
0f90e1c1 SC |
4113 | static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
4114 | bool prefault, int max_level, bool is_tdp) | |
6aa8b732 | 4115 | { |
367fd790 | 4116 | bool write = error_code & PFERR_WRITE_MASK; |
367fd790 SC |
4117 | bool exec = error_code & PFERR_FETCH_MASK; |
4118 | bool lpage_disallowed = exec && is_nx_huge_page_enabled(); | |
0f90e1c1 | 4119 | bool map_writable; |
6aa8b732 | 4120 | |
0f90e1c1 SC |
4121 | gfn_t gfn = gpa >> PAGE_SHIFT; |
4122 | unsigned long mmu_seq; | |
4123 | kvm_pfn_t pfn; | |
83f06fa7 | 4124 | int r; |
ce88decf | 4125 | |
3d0c27ad | 4126 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
9b8ebbdb | 4127 | return RET_PF_EMULATE; |
ce88decf | 4128 | |
e2dec939 AK |
4129 | r = mmu_topup_memory_caches(vcpu); |
4130 | if (r) | |
4131 | return r; | |
714b93da | 4132 | |
0f90e1c1 SC |
4133 | if (lpage_disallowed) |
4134 | max_level = PT_PAGE_TABLE_LEVEL; | |
367fd790 | 4135 | |
f9fa2509 | 4136 | if (fast_page_fault(vcpu, gpa, error_code)) |
367fd790 SC |
4137 | return RET_PF_RETRY; |
4138 | ||
4139 | mmu_seq = vcpu->kvm->mmu_notifier_seq; | |
4140 | smp_rmb(); | |
4141 | ||
4142 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) | |
4143 | return RET_PF_RETRY; | |
4144 | ||
0f90e1c1 | 4145 | if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r)) |
367fd790 | 4146 | return r; |
6aa8b732 | 4147 | |
367fd790 SC |
4148 | r = RET_PF_RETRY; |
4149 | spin_lock(&vcpu->kvm->mmu_lock); | |
4150 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) | |
4151 | goto out_unlock; | |
4152 | if (make_mmu_pages_available(vcpu) < 0) | |
4153 | goto out_unlock; | |
83f06fa7 | 4154 | r = __direct_map(vcpu, gpa, write, map_writable, max_level, pfn, |
4cd071d1 | 4155 | prefault, is_tdp && lpage_disallowed); |
0f90e1c1 | 4156 | |
367fd790 SC |
4157 | out_unlock: |
4158 | spin_unlock(&vcpu->kvm->mmu_lock); | |
4159 | kvm_release_pfn_clean(pfn); | |
4160 | return r; | |
6aa8b732 AK |
4161 | } |
4162 | ||
0f90e1c1 SC |
4163 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, |
4164 | u32 error_code, bool prefault) | |
4165 | { | |
4166 | pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code); | |
4167 | ||
4168 | /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */ | |
4169 | return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault, | |
4170 | PT_DIRECTORY_LEVEL, false); | |
4171 | } | |
4172 | ||
1261bfa3 | 4173 | int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code, |
d0006530 | 4174 | u64 fault_address, char *insn, int insn_len) |
1261bfa3 WL |
4175 | { |
4176 | int r = 1; | |
4177 | ||
736c291c SC |
4178 | #ifndef CONFIG_X86_64 |
4179 | /* A 64-bit CR2 should be impossible on 32-bit KVM. */ | |
4180 | if (WARN_ON_ONCE(fault_address >> 32)) | |
4181 | return -EFAULT; | |
4182 | #endif | |
4183 | ||
c595ceee | 4184 | vcpu->arch.l1tf_flush_l1d = true; |
1261bfa3 WL |
4185 | switch (vcpu->arch.apf.host_apf_reason) { |
4186 | default: | |
4187 | trace_kvm_page_fault(fault_address, error_code); | |
4188 | ||
d0006530 | 4189 | if (kvm_event_needs_reinjection(vcpu)) |
1261bfa3 WL |
4190 | kvm_mmu_unprotect_page_virt(vcpu, fault_address); |
4191 | r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn, | |
4192 | insn_len); | |
4193 | break; | |
4194 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
4195 | vcpu->arch.apf.host_apf_reason = 0; | |
4196 | local_irq_disable(); | |
a2b7861b | 4197 | kvm_async_pf_task_wait(fault_address, 0); |
1261bfa3 WL |
4198 | local_irq_enable(); |
4199 | break; | |
4200 | case KVM_PV_REASON_PAGE_READY: | |
4201 | vcpu->arch.apf.host_apf_reason = 0; | |
4202 | local_irq_disable(); | |
4203 | kvm_async_pf_task_wake(fault_address); | |
4204 | local_irq_enable(); | |
4205 | break; | |
4206 | } | |
4207 | return r; | |
4208 | } | |
4209 | EXPORT_SYMBOL_GPL(kvm_handle_page_fault); | |
4210 | ||
7a02674d SC |
4211 | int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
4212 | bool prefault) | |
fb72d167 | 4213 | { |
cb9b88c6 | 4214 | int max_level; |
fb72d167 | 4215 | |
cb9b88c6 SC |
4216 | for (max_level = PT_MAX_HUGEPAGE_LEVEL; |
4217 | max_level > PT_PAGE_TABLE_LEVEL; | |
4218 | max_level--) { | |
4219 | int page_num = KVM_PAGES_PER_HPAGE(max_level); | |
0f90e1c1 | 4220 | gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1); |
ce88decf | 4221 | |
cb9b88c6 SC |
4222 | if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num)) |
4223 | break; | |
fd136902 | 4224 | } |
852e3c19 | 4225 | |
0f90e1c1 SC |
4226 | return direct_page_fault(vcpu, gpa, error_code, prefault, |
4227 | max_level, true); | |
fb72d167 JR |
4228 | } |
4229 | ||
8a3c1a33 PB |
4230 | static void nonpaging_init_context(struct kvm_vcpu *vcpu, |
4231 | struct kvm_mmu *context) | |
6aa8b732 | 4232 | { |
6aa8b732 | 4233 | context->page_fault = nonpaging_page_fault; |
6aa8b732 | 4234 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
e8bc217a | 4235 | context->sync_page = nonpaging_sync_page; |
5efac074 | 4236 | context->invlpg = NULL; |
0f53b5b1 | 4237 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 4238 | context->root_level = 0; |
6aa8b732 | 4239 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
c5a78f2b | 4240 | context->direct_map = true; |
2d48a985 | 4241 | context->nx = false; |
6aa8b732 AK |
4242 | } |
4243 | ||
0be44352 SC |
4244 | static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t cr3, |
4245 | union kvm_mmu_page_role role) | |
4246 | { | |
4247 | return (role.direct || cr3 == root->cr3) && | |
4248 | VALID_PAGE(root->hpa) && page_header(root->hpa) && | |
4249 | role.word == page_header(root->hpa)->role.word; | |
4250 | } | |
4251 | ||
b94742c9 JS |
4252 | /* |
4253 | * Find out if a previously cached root matching the new CR3/role is available. | |
4254 | * The current root is also inserted into the cache. | |
4255 | * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is | |
4256 | * returned. | |
4257 | * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and | |
4258 | * false is returned. This root should now be freed by the caller. | |
4259 | */ | |
4260 | static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_cr3, | |
4261 | union kvm_mmu_page_role new_role) | |
4262 | { | |
4263 | uint i; | |
4264 | struct kvm_mmu_root_info root; | |
44dd3ffa | 4265 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
b94742c9 | 4266 | |
ad7dc69a | 4267 | root.cr3 = mmu->root_cr3; |
b94742c9 JS |
4268 | root.hpa = mmu->root_hpa; |
4269 | ||
0be44352 SC |
4270 | if (is_root_usable(&root, new_cr3, new_role)) |
4271 | return true; | |
4272 | ||
b94742c9 JS |
4273 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { |
4274 | swap(root, mmu->prev_roots[i]); | |
4275 | ||
0be44352 | 4276 | if (is_root_usable(&root, new_cr3, new_role)) |
b94742c9 JS |
4277 | break; |
4278 | } | |
4279 | ||
4280 | mmu->root_hpa = root.hpa; | |
ad7dc69a | 4281 | mmu->root_cr3 = root.cr3; |
b94742c9 JS |
4282 | |
4283 | return i < KVM_MMU_NUM_PREV_ROOTS; | |
4284 | } | |
4285 | ||
0aab33e4 | 4286 | static bool fast_cr3_switch(struct kvm_vcpu *vcpu, gpa_t new_cr3, |
ade61e28 JS |
4287 | union kvm_mmu_page_role new_role, |
4288 | bool skip_tlb_flush) | |
6aa8b732 | 4289 | { |
44dd3ffa | 4290 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
7c390d35 JS |
4291 | |
4292 | /* | |
4293 | * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid | |
4294 | * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs | |
4295 | * later if necessary. | |
4296 | */ | |
4297 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
4298 | mmu->root_level >= PT64_ROOT_4LEVEL) { | |
7c390d35 JS |
4299 | if (mmu_check_root(vcpu, new_cr3 >> PAGE_SHIFT)) |
4300 | return false; | |
4301 | ||
b94742c9 | 4302 | if (cached_root_available(vcpu, new_cr3, new_role)) { |
002c5f73 SC |
4303 | /* |
4304 | * It is possible that the cached previous root page is | |
4305 | * obsolete because of a change in the MMU generation | |
4306 | * number. However, changing the generation number is | |
4307 | * accompanied by KVM_REQ_MMU_RELOAD, which will free | |
4308 | * the root set here and allocate a new one. | |
4309 | */ | |
727a7e27 | 4310 | kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu); |
956bf353 JS |
4311 | if (!skip_tlb_flush) { |
4312 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); | |
1924242b | 4313 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
956bf353 JS |
4314 | } |
4315 | ||
4316 | /* | |
4317 | * The last MMIO access's GVA and GPA are cached in the | |
4318 | * VCPU. When switching to a new CR3, that GVA->GPA | |
4319 | * mapping may no longer be valid. So clear any cached | |
4320 | * MMIO info even when we don't need to sync the shadow | |
4321 | * page tables. | |
4322 | */ | |
4323 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); | |
ade61e28 | 4324 | |
7c390d35 JS |
4325 | __clear_sp_write_flooding_count( |
4326 | page_header(mmu->root_hpa)); | |
4327 | ||
7c390d35 JS |
4328 | return true; |
4329 | } | |
4330 | } | |
4331 | ||
4332 | return false; | |
6aa8b732 AK |
4333 | } |
4334 | ||
0aab33e4 | 4335 | static void __kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3, |
ade61e28 JS |
4336 | union kvm_mmu_page_role new_role, |
4337 | bool skip_tlb_flush) | |
6aa8b732 | 4338 | { |
ade61e28 | 4339 | if (!fast_cr3_switch(vcpu, new_cr3, new_role, skip_tlb_flush)) |
6a82cd1c VK |
4340 | kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, |
4341 | KVM_MMU_ROOT_CURRENT); | |
6aa8b732 AK |
4342 | } |
4343 | ||
ade61e28 | 4344 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3, bool skip_tlb_flush) |
0aab33e4 | 4345 | { |
ade61e28 JS |
4346 | __kvm_mmu_new_cr3(vcpu, new_cr3, kvm_mmu_calc_root_page_role(vcpu), |
4347 | skip_tlb_flush); | |
0aab33e4 | 4348 | } |
50c28f21 | 4349 | EXPORT_SYMBOL_GPL(kvm_mmu_new_cr3); |
0aab33e4 | 4350 | |
5777ed34 JR |
4351 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
4352 | { | |
9f8fe504 | 4353 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
4354 | } |
4355 | ||
54bf36aa | 4356 | static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
0a2b64c5 | 4357 | unsigned int access, int *nr_present) |
ce88decf XG |
4358 | { |
4359 | if (unlikely(is_mmio_spte(*sptep))) { | |
4360 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
4361 | mmu_spte_clear_no_track(sptep); | |
4362 | return true; | |
4363 | } | |
4364 | ||
4365 | (*nr_present)++; | |
54bf36aa | 4366 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
4367 | return true; |
4368 | } | |
4369 | ||
4370 | return false; | |
4371 | } | |
4372 | ||
6bb69c9b PB |
4373 | static inline bool is_last_gpte(struct kvm_mmu *mmu, |
4374 | unsigned level, unsigned gpte) | |
6fd01b71 | 4375 | { |
6bb69c9b PB |
4376 | /* |
4377 | * The RHS has bit 7 set iff level < mmu->last_nonleaf_level. | |
4378 | * If it is clear, there are no large pages at this level, so clear | |
4379 | * PT_PAGE_SIZE_MASK in gpte if that is the case. | |
4380 | */ | |
4381 | gpte &= level - mmu->last_nonleaf_level; | |
4382 | ||
829ee279 LP |
4383 | /* |
4384 | * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set | |
4385 | * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means | |
4386 | * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then. | |
4387 | */ | |
4388 | gpte |= level - PT_PAGE_TABLE_LEVEL - 1; | |
4389 | ||
6bb69c9b | 4390 | return gpte & PT_PAGE_SIZE_MASK; |
6fd01b71 AK |
4391 | } |
4392 | ||
37406aaa NHE |
4393 | #define PTTYPE_EPT 18 /* arbitrary */ |
4394 | #define PTTYPE PTTYPE_EPT | |
4395 | #include "paging_tmpl.h" | |
4396 | #undef PTTYPE | |
4397 | ||
6aa8b732 AK |
4398 | #define PTTYPE 64 |
4399 | #include "paging_tmpl.h" | |
4400 | #undef PTTYPE | |
4401 | ||
4402 | #define PTTYPE 32 | |
4403 | #include "paging_tmpl.h" | |
4404 | #undef PTTYPE | |
4405 | ||
6dc98b86 XG |
4406 | static void |
4407 | __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, | |
4408 | struct rsvd_bits_validate *rsvd_check, | |
4409 | int maxphyaddr, int level, bool nx, bool gbpages, | |
6fec2144 | 4410 | bool pse, bool amd) |
82725b20 | 4411 | { |
82725b20 | 4412 | u64 exb_bit_rsvd = 0; |
5f7dde7b | 4413 | u64 gbpages_bit_rsvd = 0; |
a0c0feb5 | 4414 | u64 nonleaf_bit8_rsvd = 0; |
82725b20 | 4415 | |
a0a64f50 | 4416 | rsvd_check->bad_mt_xwr = 0; |
25d92081 | 4417 | |
6dc98b86 | 4418 | if (!nx) |
82725b20 | 4419 | exb_bit_rsvd = rsvd_bits(63, 63); |
6dc98b86 | 4420 | if (!gbpages) |
5f7dde7b | 4421 | gbpages_bit_rsvd = rsvd_bits(7, 7); |
a0c0feb5 PB |
4422 | |
4423 | /* | |
4424 | * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for | |
4425 | * leaf entries) on AMD CPUs only. | |
4426 | */ | |
6fec2144 | 4427 | if (amd) |
a0c0feb5 PB |
4428 | nonleaf_bit8_rsvd = rsvd_bits(8, 8); |
4429 | ||
6dc98b86 | 4430 | switch (level) { |
82725b20 DE |
4431 | case PT32_ROOT_LEVEL: |
4432 | /* no rsvd bits for 2 level 4K page table entries */ | |
a0a64f50 XG |
4433 | rsvd_check->rsvd_bits_mask[0][1] = 0; |
4434 | rsvd_check->rsvd_bits_mask[0][0] = 0; | |
4435 | rsvd_check->rsvd_bits_mask[1][0] = | |
4436 | rsvd_check->rsvd_bits_mask[0][0]; | |
f815bce8 | 4437 | |
6dc98b86 | 4438 | if (!pse) { |
a0a64f50 | 4439 | rsvd_check->rsvd_bits_mask[1][1] = 0; |
f815bce8 XG |
4440 | break; |
4441 | } | |
4442 | ||
82725b20 DE |
4443 | if (is_cpuid_PSE36()) |
4444 | /* 36bits PSE 4MB page */ | |
a0a64f50 | 4445 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); |
82725b20 DE |
4446 | else |
4447 | /* 32 bits PSE 4MB page */ | |
a0a64f50 | 4448 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); |
82725b20 DE |
4449 | break; |
4450 | case PT32E_ROOT_LEVEL: | |
a0a64f50 | 4451 | rsvd_check->rsvd_bits_mask[0][2] = |
20c466b5 | 4452 | rsvd_bits(maxphyaddr, 63) | |
cd9ae5fe | 4453 | rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */ |
a0a64f50 | 4454 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 4455 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
a0a64f50 | 4456 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
82725b20 | 4457 | rsvd_bits(maxphyaddr, 62); /* PTE */ |
a0a64f50 | 4458 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
82725b20 DE |
4459 | rsvd_bits(maxphyaddr, 62) | |
4460 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4461 | rsvd_check->rsvd_bits_mask[1][0] = |
4462 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 | 4463 | break; |
855feb67 YZ |
4464 | case PT64_ROOT_5LEVEL: |
4465 | rsvd_check->rsvd_bits_mask[0][4] = exb_bit_rsvd | | |
4466 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | | |
4467 | rsvd_bits(maxphyaddr, 51); | |
4468 | rsvd_check->rsvd_bits_mask[1][4] = | |
4469 | rsvd_check->rsvd_bits_mask[0][4]; | |
b2869f28 | 4470 | /* fall through */ |
2a7266a8 | 4471 | case PT64_ROOT_4LEVEL: |
a0a64f50 XG |
4472 | rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd | |
4473 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | | |
4c26b4cd | 4474 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
4475 | rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd | |
4476 | nonleaf_bit8_rsvd | gbpages_bit_rsvd | | |
82725b20 | 4477 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
4478 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4479 | rsvd_bits(maxphyaddr, 51); | |
4480 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | | |
4481 | rsvd_bits(maxphyaddr, 51); | |
4482 | rsvd_check->rsvd_bits_mask[1][3] = | |
4483 | rsvd_check->rsvd_bits_mask[0][3]; | |
4484 | rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd | | |
5f7dde7b | 4485 | gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) | |
e04da980 | 4486 | rsvd_bits(13, 29); |
a0a64f50 | 4487 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
4488 | rsvd_bits(maxphyaddr, 51) | |
4489 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4490 | rsvd_check->rsvd_bits_mask[1][0] = |
4491 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
4492 | break; |
4493 | } | |
4494 | } | |
4495 | ||
6dc98b86 XG |
4496 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4497 | struct kvm_mmu *context) | |
4498 | { | |
4499 | __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check, | |
4500 | cpuid_maxphyaddr(vcpu), context->root_level, | |
d6321d49 RK |
4501 | context->nx, |
4502 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), | |
23493d0a SC |
4503 | is_pse(vcpu), |
4504 | guest_cpuid_is_amd_or_hygon(vcpu)); | |
6dc98b86 XG |
4505 | } |
4506 | ||
81b8eebb XG |
4507 | static void |
4508 | __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check, | |
4509 | int maxphyaddr, bool execonly) | |
25d92081 | 4510 | { |
951f9fd7 | 4511 | u64 bad_mt_xwr; |
25d92081 | 4512 | |
855feb67 YZ |
4513 | rsvd_check->rsvd_bits_mask[0][4] = |
4514 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); | |
a0a64f50 | 4515 | rsvd_check->rsvd_bits_mask[0][3] = |
25d92081 | 4516 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); |
a0a64f50 | 4517 | rsvd_check->rsvd_bits_mask[0][2] = |
25d92081 | 4518 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 4519 | rsvd_check->rsvd_bits_mask[0][1] = |
25d92081 | 4520 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 4521 | rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51); |
25d92081 YZ |
4522 | |
4523 | /* large page */ | |
855feb67 | 4524 | rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4]; |
a0a64f50 XG |
4525 | rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3]; |
4526 | rsvd_check->rsvd_bits_mask[1][2] = | |
25d92081 | 4527 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29); |
a0a64f50 | 4528 | rsvd_check->rsvd_bits_mask[1][1] = |
25d92081 | 4529 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20); |
a0a64f50 | 4530 | rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0]; |
25d92081 | 4531 | |
951f9fd7 PB |
4532 | bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */ |
4533 | bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */ | |
4534 | bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */ | |
4535 | bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */ | |
4536 | bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */ | |
4537 | if (!execonly) { | |
4538 | /* bits 0..2 must not be 100 unless VMX capabilities allow it */ | |
4539 | bad_mt_xwr |= REPEAT_BYTE(1ull << 4); | |
25d92081 | 4540 | } |
951f9fd7 | 4541 | rsvd_check->bad_mt_xwr = bad_mt_xwr; |
25d92081 YZ |
4542 | } |
4543 | ||
81b8eebb XG |
4544 | static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, |
4545 | struct kvm_mmu *context, bool execonly) | |
4546 | { | |
4547 | __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check, | |
4548 | cpuid_maxphyaddr(vcpu), execonly); | |
4549 | } | |
4550 | ||
c258b62b XG |
4551 | /* |
4552 | * the page table on host is the shadow page table for the page | |
4553 | * table in guest or amd nested guest, its mmu features completely | |
4554 | * follow the features in guest. | |
4555 | */ | |
4556 | void | |
4557 | reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) | |
4558 | { | |
36d9594d VK |
4559 | bool uses_nx = context->nx || |
4560 | context->mmu_role.base.smep_andnot_wp; | |
ea2800dd BS |
4561 | struct rsvd_bits_validate *shadow_zero_check; |
4562 | int i; | |
5f0b8199 | 4563 | |
6fec2144 PB |
4564 | /* |
4565 | * Passing "true" to the last argument is okay; it adds a check | |
4566 | * on bit 8 of the SPTEs which KVM doesn't use anyway. | |
4567 | */ | |
ea2800dd BS |
4568 | shadow_zero_check = &context->shadow_zero_check; |
4569 | __reset_rsvds_bits_mask(vcpu, shadow_zero_check, | |
f3ecb59d | 4570 | shadow_phys_bits, |
5f0b8199 | 4571 | context->shadow_root_level, uses_nx, |
d6321d49 RK |
4572 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), |
4573 | is_pse(vcpu), true); | |
ea2800dd BS |
4574 | |
4575 | if (!shadow_me_mask) | |
4576 | return; | |
4577 | ||
4578 | for (i = context->shadow_root_level; --i >= 0;) { | |
4579 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4580 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4581 | } | |
4582 | ||
c258b62b XG |
4583 | } |
4584 | EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask); | |
4585 | ||
6fec2144 PB |
4586 | static inline bool boot_cpu_is_amd(void) |
4587 | { | |
4588 | WARN_ON_ONCE(!tdp_enabled); | |
4589 | return shadow_x_mask == 0; | |
4590 | } | |
4591 | ||
c258b62b XG |
4592 | /* |
4593 | * the direct page table on host, use as much mmu features as | |
4594 | * possible, however, kvm currently does not do execution-protection. | |
4595 | */ | |
4596 | static void | |
4597 | reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4598 | struct kvm_mmu *context) | |
4599 | { | |
ea2800dd BS |
4600 | struct rsvd_bits_validate *shadow_zero_check; |
4601 | int i; | |
4602 | ||
4603 | shadow_zero_check = &context->shadow_zero_check; | |
4604 | ||
6fec2144 | 4605 | if (boot_cpu_is_amd()) |
ea2800dd | 4606 | __reset_rsvds_bits_mask(vcpu, shadow_zero_check, |
f3ecb59d | 4607 | shadow_phys_bits, |
c258b62b | 4608 | context->shadow_root_level, false, |
b8291adc BP |
4609 | boot_cpu_has(X86_FEATURE_GBPAGES), |
4610 | true, true); | |
c258b62b | 4611 | else |
ea2800dd | 4612 | __reset_rsvds_bits_mask_ept(shadow_zero_check, |
f3ecb59d | 4613 | shadow_phys_bits, |
c258b62b XG |
4614 | false); |
4615 | ||
ea2800dd BS |
4616 | if (!shadow_me_mask) |
4617 | return; | |
4618 | ||
4619 | for (i = context->shadow_root_level; --i >= 0;) { | |
4620 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4621 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4622 | } | |
c258b62b XG |
4623 | } |
4624 | ||
4625 | /* | |
4626 | * as the comments in reset_shadow_zero_bits_mask() except it | |
4627 | * is the shadow page table for intel nested guest. | |
4628 | */ | |
4629 | static void | |
4630 | reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4631 | struct kvm_mmu *context, bool execonly) | |
4632 | { | |
4633 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
f3ecb59d | 4634 | shadow_phys_bits, execonly); |
c258b62b XG |
4635 | } |
4636 | ||
09f037aa PB |
4637 | #define BYTE_MASK(access) \ |
4638 | ((1 & (access) ? 2 : 0) | \ | |
4639 | (2 & (access) ? 4 : 0) | \ | |
4640 | (3 & (access) ? 8 : 0) | \ | |
4641 | (4 & (access) ? 16 : 0) | \ | |
4642 | (5 & (access) ? 32 : 0) | \ | |
4643 | (6 & (access) ? 64 : 0) | \ | |
4644 | (7 & (access) ? 128 : 0)) | |
4645 | ||
4646 | ||
edc90b7d XG |
4647 | static void update_permission_bitmask(struct kvm_vcpu *vcpu, |
4648 | struct kvm_mmu *mmu, bool ept) | |
97d64b78 | 4649 | { |
09f037aa PB |
4650 | unsigned byte; |
4651 | ||
4652 | const u8 x = BYTE_MASK(ACC_EXEC_MASK); | |
4653 | const u8 w = BYTE_MASK(ACC_WRITE_MASK); | |
4654 | const u8 u = BYTE_MASK(ACC_USER_MASK); | |
4655 | ||
4656 | bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0; | |
4657 | bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0; | |
4658 | bool cr0_wp = is_write_protection(vcpu); | |
97d64b78 | 4659 | |
97d64b78 | 4660 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { |
09f037aa PB |
4661 | unsigned pfec = byte << 1; |
4662 | ||
97ec8c06 | 4663 | /* |
09f037aa PB |
4664 | * Each "*f" variable has a 1 bit for each UWX value |
4665 | * that causes a fault with the given PFEC. | |
97ec8c06 | 4666 | */ |
97d64b78 | 4667 | |
09f037aa | 4668 | /* Faults from writes to non-writable pages */ |
a6a6d3b1 | 4669 | u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0; |
09f037aa | 4670 | /* Faults from user mode accesses to supervisor pages */ |
a6a6d3b1 | 4671 | u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0; |
09f037aa | 4672 | /* Faults from fetches of non-executable pages*/ |
a6a6d3b1 | 4673 | u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0; |
09f037aa PB |
4674 | /* Faults from kernel mode fetches of user pages */ |
4675 | u8 smepf = 0; | |
4676 | /* Faults from kernel mode accesses of user pages */ | |
4677 | u8 smapf = 0; | |
4678 | ||
4679 | if (!ept) { | |
4680 | /* Faults from kernel mode accesses to user pages */ | |
4681 | u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u; | |
4682 | ||
4683 | /* Not really needed: !nx will cause pte.nx to fault */ | |
4684 | if (!mmu->nx) | |
4685 | ff = 0; | |
4686 | ||
4687 | /* Allow supervisor writes if !cr0.wp */ | |
4688 | if (!cr0_wp) | |
4689 | wf = (pfec & PFERR_USER_MASK) ? wf : 0; | |
4690 | ||
4691 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
4692 | if (cr4_smep) | |
4693 | smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0; | |
4694 | ||
4695 | /* | |
4696 | * SMAP:kernel-mode data accesses from user-mode | |
4697 | * mappings should fault. A fault is considered | |
4698 | * as a SMAP violation if all of the following | |
39337ad1 | 4699 | * conditions are true: |
09f037aa PB |
4700 | * - X86_CR4_SMAP is set in CR4 |
4701 | * - A user page is accessed | |
4702 | * - The access is not a fetch | |
4703 | * - Page fault in kernel mode | |
4704 | * - if CPL = 3 or X86_EFLAGS_AC is clear | |
4705 | * | |
4706 | * Here, we cover the first three conditions. | |
4707 | * The fourth is computed dynamically in permission_fault(); | |
4708 | * PFERR_RSVD_MASK bit will be set in PFEC if the access is | |
4709 | * *not* subject to SMAP restrictions. | |
4710 | */ | |
4711 | if (cr4_smap) | |
4712 | smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf; | |
97d64b78 | 4713 | } |
09f037aa PB |
4714 | |
4715 | mmu->permissions[byte] = ff | uf | wf | smepf | smapf; | |
97d64b78 AK |
4716 | } |
4717 | } | |
4718 | ||
2d344105 HH |
4719 | /* |
4720 | * PKU is an additional mechanism by which the paging controls access to | |
4721 | * user-mode addresses based on the value in the PKRU register. Protection | |
4722 | * key violations are reported through a bit in the page fault error code. | |
4723 | * Unlike other bits of the error code, the PK bit is not known at the | |
4724 | * call site of e.g. gva_to_gpa; it must be computed directly in | |
4725 | * permission_fault based on two bits of PKRU, on some machine state (CR4, | |
4726 | * CR0, EFER, CPL), and on other bits of the error code and the page tables. | |
4727 | * | |
4728 | * In particular the following conditions come from the error code, the | |
4729 | * page tables and the machine state: | |
4730 | * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1 | |
4731 | * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch) | |
4732 | * - PK is always zero if U=0 in the page tables | |
4733 | * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access. | |
4734 | * | |
4735 | * The PKRU bitmask caches the result of these four conditions. The error | |
4736 | * code (minus the P bit) and the page table's U bit form an index into the | |
4737 | * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed | |
4738 | * with the two bits of the PKRU register corresponding to the protection key. | |
4739 | * For the first three conditions above the bits will be 00, thus masking | |
4740 | * away both AD and WD. For all reads or if the last condition holds, WD | |
4741 | * only will be masked away. | |
4742 | */ | |
4743 | static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
4744 | bool ept) | |
4745 | { | |
4746 | unsigned bit; | |
4747 | bool wp; | |
4748 | ||
4749 | if (ept) { | |
4750 | mmu->pkru_mask = 0; | |
4751 | return; | |
4752 | } | |
4753 | ||
4754 | /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */ | |
4755 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) { | |
4756 | mmu->pkru_mask = 0; | |
4757 | return; | |
4758 | } | |
4759 | ||
4760 | wp = is_write_protection(vcpu); | |
4761 | ||
4762 | for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) { | |
4763 | unsigned pfec, pkey_bits; | |
4764 | bool check_pkey, check_write, ff, uf, wf, pte_user; | |
4765 | ||
4766 | pfec = bit << 1; | |
4767 | ff = pfec & PFERR_FETCH_MASK; | |
4768 | uf = pfec & PFERR_USER_MASK; | |
4769 | wf = pfec & PFERR_WRITE_MASK; | |
4770 | ||
4771 | /* PFEC.RSVD is replaced by ACC_USER_MASK. */ | |
4772 | pte_user = pfec & PFERR_RSVD_MASK; | |
4773 | ||
4774 | /* | |
4775 | * Only need to check the access which is not an | |
4776 | * instruction fetch and is to a user page. | |
4777 | */ | |
4778 | check_pkey = (!ff && pte_user); | |
4779 | /* | |
4780 | * write access is controlled by PKRU if it is a | |
4781 | * user access or CR0.WP = 1. | |
4782 | */ | |
4783 | check_write = check_pkey && wf && (uf || wp); | |
4784 | ||
4785 | /* PKRU.AD stops both read and write access. */ | |
4786 | pkey_bits = !!check_pkey; | |
4787 | /* PKRU.WD stops write access. */ | |
4788 | pkey_bits |= (!!check_write) << 1; | |
4789 | ||
4790 | mmu->pkru_mask |= (pkey_bits & 3) << pfec; | |
4791 | } | |
4792 | } | |
4793 | ||
6bb69c9b | 4794 | static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
6fd01b71 | 4795 | { |
6bb69c9b PB |
4796 | unsigned root_level = mmu->root_level; |
4797 | ||
4798 | mmu->last_nonleaf_level = root_level; | |
4799 | if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu)) | |
4800 | mmu->last_nonleaf_level++; | |
6fd01b71 AK |
4801 | } |
4802 | ||
8a3c1a33 PB |
4803 | static void paging64_init_context_common(struct kvm_vcpu *vcpu, |
4804 | struct kvm_mmu *context, | |
4805 | int level) | |
6aa8b732 | 4806 | { |
2d48a985 | 4807 | context->nx = is_nx(vcpu); |
4d6931c3 | 4808 | context->root_level = level; |
2d48a985 | 4809 | |
4d6931c3 | 4810 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4811 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4812 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4813 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4814 | |
fa4a2c08 | 4815 | MMU_WARN_ON(!is_pae(vcpu)); |
6aa8b732 | 4816 | context->page_fault = paging64_page_fault; |
6aa8b732 | 4817 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 4818 | context->sync_page = paging64_sync_page; |
a7052897 | 4819 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 4820 | context->update_pte = paging64_update_pte; |
17ac10ad | 4821 | context->shadow_root_level = level; |
c5a78f2b | 4822 | context->direct_map = false; |
6aa8b732 AK |
4823 | } |
4824 | ||
8a3c1a33 PB |
4825 | static void paging64_init_context(struct kvm_vcpu *vcpu, |
4826 | struct kvm_mmu *context) | |
17ac10ad | 4827 | { |
855feb67 YZ |
4828 | int root_level = is_la57_mode(vcpu) ? |
4829 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4830 | ||
4831 | paging64_init_context_common(vcpu, context, root_level); | |
17ac10ad AK |
4832 | } |
4833 | ||
8a3c1a33 PB |
4834 | static void paging32_init_context(struct kvm_vcpu *vcpu, |
4835 | struct kvm_mmu *context) | |
6aa8b732 | 4836 | { |
2d48a985 | 4837 | context->nx = false; |
4d6931c3 | 4838 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 4839 | |
4d6931c3 | 4840 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4841 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4842 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4843 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4844 | |
6aa8b732 | 4845 | context->page_fault = paging32_page_fault; |
6aa8b732 | 4846 | context->gva_to_gpa = paging32_gva_to_gpa; |
e8bc217a | 4847 | context->sync_page = paging32_sync_page; |
a7052897 | 4848 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 4849 | context->update_pte = paging32_update_pte; |
6aa8b732 | 4850 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
c5a78f2b | 4851 | context->direct_map = false; |
6aa8b732 AK |
4852 | } |
4853 | ||
8a3c1a33 PB |
4854 | static void paging32E_init_context(struct kvm_vcpu *vcpu, |
4855 | struct kvm_mmu *context) | |
6aa8b732 | 4856 | { |
8a3c1a33 | 4857 | paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
4858 | } |
4859 | ||
a336282d VK |
4860 | static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu) |
4861 | { | |
4862 | union kvm_mmu_extended_role ext = {0}; | |
4863 | ||
7dcd5755 | 4864 | ext.cr0_pg = !!is_paging(vcpu); |
0699c64a | 4865 | ext.cr4_pae = !!is_pae(vcpu); |
a336282d VK |
4866 | ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
4867 | ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); | |
4868 | ext.cr4_pse = !!is_pse(vcpu); | |
4869 | ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE); | |
de3ccd26 | 4870 | ext.maxphyaddr = cpuid_maxphyaddr(vcpu); |
a336282d VK |
4871 | |
4872 | ext.valid = 1; | |
4873 | ||
4874 | return ext; | |
4875 | } | |
4876 | ||
7dcd5755 VK |
4877 | static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu, |
4878 | bool base_only) | |
4879 | { | |
4880 | union kvm_mmu_role role = {0}; | |
4881 | ||
4882 | role.base.access = ACC_ALL; | |
4883 | role.base.nxe = !!is_nx(vcpu); | |
7dcd5755 VK |
4884 | role.base.cr0_wp = is_write_protection(vcpu); |
4885 | role.base.smm = is_smm(vcpu); | |
4886 | role.base.guest_mode = is_guest_mode(vcpu); | |
4887 | ||
4888 | if (base_only) | |
4889 | return role; | |
4890 | ||
4891 | role.ext = kvm_calc_mmu_role_ext(vcpu); | |
4892 | ||
4893 | return role; | |
4894 | } | |
4895 | ||
4896 | static union kvm_mmu_role | |
4897 | kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only) | |
9fa72119 | 4898 | { |
7dcd5755 | 4899 | union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only); |
9fa72119 | 4900 | |
7dcd5755 | 4901 | role.base.ad_disabled = (shadow_accessed_mask == 0); |
afaf0b2f | 4902 | role.base.level = kvm_x86_ops.get_tdp_level(vcpu); |
7dcd5755 | 4903 | role.base.direct = true; |
47c42e6b | 4904 | role.base.gpte_is_8_bytes = true; |
9fa72119 JS |
4905 | |
4906 | return role; | |
4907 | } | |
4908 | ||
8a3c1a33 | 4909 | static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4910 | { |
44dd3ffa | 4911 | struct kvm_mmu *context = vcpu->arch.mmu; |
7dcd5755 VK |
4912 | union kvm_mmu_role new_role = |
4913 | kvm_calc_tdp_mmu_root_page_role(vcpu, false); | |
fb72d167 | 4914 | |
7dcd5755 VK |
4915 | if (new_role.as_u64 == context->mmu_role.as_u64) |
4916 | return; | |
4917 | ||
4918 | context->mmu_role.as_u64 = new_role.as_u64; | |
7a02674d | 4919 | context->page_fault = kvm_tdp_page_fault; |
e8bc217a | 4920 | context->sync_page = nonpaging_sync_page; |
5efac074 | 4921 | context->invlpg = NULL; |
0f53b5b1 | 4922 | context->update_pte = nonpaging_update_pte; |
afaf0b2f | 4923 | context->shadow_root_level = kvm_x86_ops.get_tdp_level(vcpu); |
c5a78f2b | 4924 | context->direct_map = true; |
d8dd54e0 | 4925 | context->get_guest_pgd = get_cr3; |
e4e517b4 | 4926 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 4927 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
4928 | |
4929 | if (!is_paging(vcpu)) { | |
2d48a985 | 4930 | context->nx = false; |
fb72d167 JR |
4931 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
4932 | context->root_level = 0; | |
4933 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4934 | context->nx = is_nx(vcpu); |
855feb67 YZ |
4935 | context->root_level = is_la57_mode(vcpu) ? |
4936 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4d6931c3 DB |
4937 | reset_rsvds_bits_mask(vcpu, context); |
4938 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4939 | } else if (is_pae(vcpu)) { |
2d48a985 | 4940 | context->nx = is_nx(vcpu); |
fb72d167 | 4941 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
4942 | reset_rsvds_bits_mask(vcpu, context); |
4943 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4944 | } else { |
2d48a985 | 4945 | context->nx = false; |
fb72d167 | 4946 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
4947 | reset_rsvds_bits_mask(vcpu, context); |
4948 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
4949 | } |
4950 | ||
25d92081 | 4951 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4952 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4953 | update_last_nonleaf_level(vcpu, context); |
c258b62b | 4954 | reset_tdp_shadow_zero_bits_mask(vcpu, context); |
fb72d167 JR |
4955 | } |
4956 | ||
7dcd5755 VK |
4957 | static union kvm_mmu_role |
4958 | kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only) | |
4959 | { | |
4960 | union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only); | |
4961 | ||
4962 | role.base.smep_andnot_wp = role.ext.cr4_smep && | |
4963 | !is_write_protection(vcpu); | |
4964 | role.base.smap_andnot_wp = role.ext.cr4_smap && | |
4965 | !is_write_protection(vcpu); | |
4966 | role.base.direct = !is_paging(vcpu); | |
47c42e6b | 4967 | role.base.gpte_is_8_bytes = !!is_pae(vcpu); |
9fa72119 JS |
4968 | |
4969 | if (!is_long_mode(vcpu)) | |
7dcd5755 | 4970 | role.base.level = PT32E_ROOT_LEVEL; |
9fa72119 | 4971 | else if (is_la57_mode(vcpu)) |
7dcd5755 | 4972 | role.base.level = PT64_ROOT_5LEVEL; |
9fa72119 | 4973 | else |
7dcd5755 | 4974 | role.base.level = PT64_ROOT_4LEVEL; |
9fa72119 JS |
4975 | |
4976 | return role; | |
4977 | } | |
4978 | ||
4979 | void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu) | |
4980 | { | |
44dd3ffa | 4981 | struct kvm_mmu *context = vcpu->arch.mmu; |
7dcd5755 VK |
4982 | union kvm_mmu_role new_role = |
4983 | kvm_calc_shadow_mmu_root_page_role(vcpu, false); | |
4984 | ||
7dcd5755 VK |
4985 | if (new_role.as_u64 == context->mmu_role.as_u64) |
4986 | return; | |
6aa8b732 AK |
4987 | |
4988 | if (!is_paging(vcpu)) | |
8a3c1a33 | 4989 | nonpaging_init_context(vcpu, context); |
a9058ecd | 4990 | else if (is_long_mode(vcpu)) |
8a3c1a33 | 4991 | paging64_init_context(vcpu, context); |
6aa8b732 | 4992 | else if (is_pae(vcpu)) |
8a3c1a33 | 4993 | paging32E_init_context(vcpu, context); |
6aa8b732 | 4994 | else |
8a3c1a33 | 4995 | paging32_init_context(vcpu, context); |
a770f6f2 | 4996 | |
7dcd5755 | 4997 | context->mmu_role.as_u64 = new_role.as_u64; |
c258b62b | 4998 | reset_shadow_zero_bits_mask(vcpu, context); |
52fde8df JR |
4999 | } |
5000 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
5001 | ||
a336282d VK |
5002 | static union kvm_mmu_role |
5003 | kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty, | |
bb1fcc70 | 5004 | bool execonly, u8 level) |
9fa72119 | 5005 | { |
552c69b1 | 5006 | union kvm_mmu_role role = {0}; |
14c07ad8 | 5007 | |
47c42e6b SC |
5008 | /* SMM flag is inherited from root_mmu */ |
5009 | role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm; | |
9fa72119 | 5010 | |
bb1fcc70 | 5011 | role.base.level = level; |
47c42e6b | 5012 | role.base.gpte_is_8_bytes = true; |
a336282d VK |
5013 | role.base.direct = false; |
5014 | role.base.ad_disabled = !accessed_dirty; | |
5015 | role.base.guest_mode = true; | |
5016 | role.base.access = ACC_ALL; | |
9fa72119 | 5017 | |
47c42e6b SC |
5018 | /* |
5019 | * WP=1 and NOT_WP=1 is an impossible combination, use WP and the | |
5020 | * SMAP variation to denote shadow EPT entries. | |
5021 | */ | |
5022 | role.base.cr0_wp = true; | |
5023 | role.base.smap_andnot_wp = true; | |
5024 | ||
552c69b1 | 5025 | role.ext = kvm_calc_mmu_role_ext(vcpu); |
a336282d | 5026 | role.ext.execonly = execonly; |
9fa72119 JS |
5027 | |
5028 | return role; | |
5029 | } | |
5030 | ||
ae1e2d10 | 5031 | void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly, |
50c28f21 | 5032 | bool accessed_dirty, gpa_t new_eptp) |
155a97a3 | 5033 | { |
44dd3ffa | 5034 | struct kvm_mmu *context = vcpu->arch.mmu; |
bb1fcc70 | 5035 | u8 level = vmx_eptp_page_walk_level(new_eptp); |
a336282d VK |
5036 | union kvm_mmu_role new_role = |
5037 | kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty, | |
bb1fcc70 | 5038 | execonly, level); |
a336282d VK |
5039 | |
5040 | __kvm_mmu_new_cr3(vcpu, new_eptp, new_role.base, false); | |
5041 | ||
a336282d VK |
5042 | if (new_role.as_u64 == context->mmu_role.as_u64) |
5043 | return; | |
ad896af0 | 5044 | |
bb1fcc70 | 5045 | context->shadow_root_level = level; |
155a97a3 NHE |
5046 | |
5047 | context->nx = true; | |
ae1e2d10 | 5048 | context->ept_ad = accessed_dirty; |
155a97a3 NHE |
5049 | context->page_fault = ept_page_fault; |
5050 | context->gva_to_gpa = ept_gva_to_gpa; | |
5051 | context->sync_page = ept_sync_page; | |
5052 | context->invlpg = ept_invlpg; | |
5053 | context->update_pte = ept_update_pte; | |
bb1fcc70 | 5054 | context->root_level = level; |
155a97a3 | 5055 | context->direct_map = false; |
a336282d | 5056 | context->mmu_role.as_u64 = new_role.as_u64; |
3dc773e7 | 5057 | |
155a97a3 | 5058 | update_permission_bitmask(vcpu, context, true); |
2d344105 | 5059 | update_pkru_bitmask(vcpu, context, true); |
fd19d3b4 | 5060 | update_last_nonleaf_level(vcpu, context); |
155a97a3 | 5061 | reset_rsvds_bits_mask_ept(vcpu, context, execonly); |
c258b62b | 5062 | reset_ept_shadow_zero_bits_mask(vcpu, context, execonly); |
155a97a3 NHE |
5063 | } |
5064 | EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu); | |
5065 | ||
8a3c1a33 | 5066 | static void init_kvm_softmmu(struct kvm_vcpu *vcpu) |
52fde8df | 5067 | { |
44dd3ffa | 5068 | struct kvm_mmu *context = vcpu->arch.mmu; |
ad896af0 PB |
5069 | |
5070 | kvm_init_shadow_mmu(vcpu); | |
d8dd54e0 | 5071 | context->get_guest_pgd = get_cr3; |
ad896af0 PB |
5072 | context->get_pdptr = kvm_pdptr_read; |
5073 | context->inject_page_fault = kvm_inject_page_fault; | |
6aa8b732 AK |
5074 | } |
5075 | ||
8a3c1a33 | 5076 | static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
02f59dc9 | 5077 | { |
bf627a92 | 5078 | union kvm_mmu_role new_role = kvm_calc_mmu_role_common(vcpu, false); |
02f59dc9 JR |
5079 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; |
5080 | ||
bf627a92 VK |
5081 | if (new_role.as_u64 == g_context->mmu_role.as_u64) |
5082 | return; | |
5083 | ||
5084 | g_context->mmu_role.as_u64 = new_role.as_u64; | |
d8dd54e0 | 5085 | g_context->get_guest_pgd = get_cr3; |
e4e517b4 | 5086 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
5087 | g_context->inject_page_fault = kvm_inject_page_fault; |
5088 | ||
5efac074 PB |
5089 | /* |
5090 | * L2 page tables are never shadowed, so there is no need to sync | |
5091 | * SPTEs. | |
5092 | */ | |
5093 | g_context->invlpg = NULL; | |
5094 | ||
02f59dc9 | 5095 | /* |
44dd3ffa | 5096 | * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using |
0af2593b DM |
5097 | * L1's nested page tables (e.g. EPT12). The nested translation |
5098 | * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using | |
5099 | * L2's page tables as the first level of translation and L1's | |
5100 | * nested page tables as the second level of translation. Basically | |
5101 | * the gva_to_gpa functions between mmu and nested_mmu are swapped. | |
02f59dc9 JR |
5102 | */ |
5103 | if (!is_paging(vcpu)) { | |
2d48a985 | 5104 | g_context->nx = false; |
02f59dc9 JR |
5105 | g_context->root_level = 0; |
5106 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
5107 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 5108 | g_context->nx = is_nx(vcpu); |
855feb67 YZ |
5109 | g_context->root_level = is_la57_mode(vcpu) ? |
5110 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4d6931c3 | 5111 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
5112 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
5113 | } else if (is_pae(vcpu)) { | |
2d48a985 | 5114 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 5115 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 5116 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
5117 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
5118 | } else { | |
2d48a985 | 5119 | g_context->nx = false; |
02f59dc9 | 5120 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 5121 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
5122 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
5123 | } | |
5124 | ||
25d92081 | 5125 | update_permission_bitmask(vcpu, g_context, false); |
2d344105 | 5126 | update_pkru_bitmask(vcpu, g_context, false); |
6bb69c9b | 5127 | update_last_nonleaf_level(vcpu, g_context); |
02f59dc9 JR |
5128 | } |
5129 | ||
1c53da3f | 5130 | void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots) |
fb72d167 | 5131 | { |
1c53da3f | 5132 | if (reset_roots) { |
b94742c9 JS |
5133 | uint i; |
5134 | ||
44dd3ffa | 5135 | vcpu->arch.mmu->root_hpa = INVALID_PAGE; |
b94742c9 JS |
5136 | |
5137 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
44dd3ffa | 5138 | vcpu->arch.mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID; |
1c53da3f JS |
5139 | } |
5140 | ||
02f59dc9 | 5141 | if (mmu_is_nested(vcpu)) |
e0c6db3e | 5142 | init_kvm_nested_mmu(vcpu); |
02f59dc9 | 5143 | else if (tdp_enabled) |
e0c6db3e | 5144 | init_kvm_tdp_mmu(vcpu); |
fb72d167 | 5145 | else |
e0c6db3e | 5146 | init_kvm_softmmu(vcpu); |
fb72d167 | 5147 | } |
1c53da3f | 5148 | EXPORT_SYMBOL_GPL(kvm_init_mmu); |
fb72d167 | 5149 | |
9fa72119 JS |
5150 | static union kvm_mmu_page_role |
5151 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu) | |
5152 | { | |
7dcd5755 VK |
5153 | union kvm_mmu_role role; |
5154 | ||
9fa72119 | 5155 | if (tdp_enabled) |
7dcd5755 | 5156 | role = kvm_calc_tdp_mmu_root_page_role(vcpu, true); |
9fa72119 | 5157 | else |
7dcd5755 VK |
5158 | role = kvm_calc_shadow_mmu_root_page_role(vcpu, true); |
5159 | ||
5160 | return role.base; | |
9fa72119 | 5161 | } |
fb72d167 | 5162 | |
8a3c1a33 | 5163 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu) |
6aa8b732 | 5164 | { |
95f93af4 | 5165 | kvm_mmu_unload(vcpu); |
1c53da3f | 5166 | kvm_init_mmu(vcpu, true); |
17c3ba9d | 5167 | } |
8668a3c4 | 5168 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
5169 | |
5170 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 5171 | { |
714b93da AK |
5172 | int r; |
5173 | ||
e2dec939 | 5174 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
5175 | if (r) |
5176 | goto out; | |
8986ecc0 | 5177 | r = mmu_alloc_roots(vcpu); |
e2858b4a | 5178 | kvm_mmu_sync_roots(vcpu); |
8986ecc0 MT |
5179 | if (r) |
5180 | goto out; | |
727a7e27 | 5181 | kvm_mmu_load_pgd(vcpu); |
afaf0b2f | 5182 | kvm_x86_ops.tlb_flush(vcpu, true); |
714b93da AK |
5183 | out: |
5184 | return r; | |
6aa8b732 | 5185 | } |
17c3ba9d AK |
5186 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
5187 | ||
5188 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
5189 | { | |
14c07ad8 VK |
5190 | kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL); |
5191 | WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa)); | |
5192 | kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL); | |
5193 | WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa)); | |
17c3ba9d | 5194 | } |
4b16184c | 5195 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 5196 | |
0028425f | 5197 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
5198 | struct kvm_mmu_page *sp, u64 *spte, |
5199 | const void *new) | |
0028425f | 5200 | { |
30945387 | 5201 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
5202 | ++vcpu->kvm->stat.mmu_pde_zapped; |
5203 | return; | |
30945387 | 5204 | } |
0028425f | 5205 | |
4cee5764 | 5206 | ++vcpu->kvm->stat.mmu_pte_updated; |
44dd3ffa | 5207 | vcpu->arch.mmu->update_pte(vcpu, sp, spte, new); |
0028425f AK |
5208 | } |
5209 | ||
79539cec AK |
5210 | static bool need_remote_flush(u64 old, u64 new) |
5211 | { | |
5212 | if (!is_shadow_present_pte(old)) | |
5213 | return false; | |
5214 | if (!is_shadow_present_pte(new)) | |
5215 | return true; | |
5216 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
5217 | return true; | |
53166229 GN |
5218 | old ^= shadow_nx_mask; |
5219 | new ^= shadow_nx_mask; | |
79539cec AK |
5220 | return (old & ~new & PT64_PERM_MASK) != 0; |
5221 | } | |
5222 | ||
889e5cbc | 5223 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
0e0fee5c | 5224 | int *bytes) |
da4a00f0 | 5225 | { |
0e0fee5c | 5226 | u64 gentry = 0; |
889e5cbc | 5227 | int r; |
72016f3a | 5228 | |
72016f3a AK |
5229 | /* |
5230 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
5231 | * as the current vcpu paging mode since we update the sptes only |
5232 | * when they have the same mode. | |
72016f3a | 5233 | */ |
889e5cbc | 5234 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 5235 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
5236 | *gpa &= ~(gpa_t)7; |
5237 | *bytes = 8; | |
08e850c6 AK |
5238 | } |
5239 | ||
0e0fee5c JS |
5240 | if (*bytes == 4 || *bytes == 8) { |
5241 | r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes); | |
5242 | if (r) | |
5243 | gentry = 0; | |
72016f3a AK |
5244 | } |
5245 | ||
889e5cbc XG |
5246 | return gentry; |
5247 | } | |
5248 | ||
5249 | /* | |
5250 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
5251 | * or we may be forking, in which case it is better to unmap the page. | |
5252 | */ | |
a138fe75 | 5253 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 5254 | { |
a30f47cb XG |
5255 | /* |
5256 | * Skip write-flooding detected for the sp whose level is 1, because | |
5257 | * it can become unsync, then the guest page is not write-protected. | |
5258 | */ | |
f71fa31f | 5259 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) |
a30f47cb | 5260 | return false; |
3246af0e | 5261 | |
e5691a81 XG |
5262 | atomic_inc(&sp->write_flooding_count); |
5263 | return atomic_read(&sp->write_flooding_count) >= 3; | |
889e5cbc XG |
5264 | } |
5265 | ||
5266 | /* | |
5267 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
5268 | * indicate a page is not used as a page table. | |
5269 | */ | |
5270 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
5271 | int bytes) | |
5272 | { | |
5273 | unsigned offset, pte_size, misaligned; | |
5274 | ||
5275 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
5276 | gpa, bytes, sp->role.word); | |
5277 | ||
5278 | offset = offset_in_page(gpa); | |
47c42e6b | 5279 | pte_size = sp->role.gpte_is_8_bytes ? 8 : 4; |
5d9ca30e XG |
5280 | |
5281 | /* | |
5282 | * Sometimes, the OS only writes the last one bytes to update status | |
5283 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
5284 | */ | |
5285 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
5286 | return false; | |
5287 | ||
889e5cbc XG |
5288 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
5289 | misaligned |= bytes < 4; | |
5290 | ||
5291 | return misaligned; | |
5292 | } | |
5293 | ||
5294 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
5295 | { | |
5296 | unsigned page_offset, quadrant; | |
5297 | u64 *spte; | |
5298 | int level; | |
5299 | ||
5300 | page_offset = offset_in_page(gpa); | |
5301 | level = sp->role.level; | |
5302 | *nspte = 1; | |
47c42e6b | 5303 | if (!sp->role.gpte_is_8_bytes) { |
889e5cbc XG |
5304 | page_offset <<= 1; /* 32->64 */ |
5305 | /* | |
5306 | * A 32-bit pde maps 4MB while the shadow pdes map | |
5307 | * only 2MB. So we need to double the offset again | |
5308 | * and zap two pdes instead of one. | |
5309 | */ | |
5310 | if (level == PT32_ROOT_LEVEL) { | |
5311 | page_offset &= ~7; /* kill rounding error */ | |
5312 | page_offset <<= 1; | |
5313 | *nspte = 2; | |
5314 | } | |
5315 | quadrant = page_offset >> PAGE_SHIFT; | |
5316 | page_offset &= ~PAGE_MASK; | |
5317 | if (quadrant != sp->role.quadrant) | |
5318 | return NULL; | |
5319 | } | |
5320 | ||
5321 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
5322 | return spte; | |
5323 | } | |
5324 | ||
a102a674 SC |
5325 | /* |
5326 | * Ignore various flags when determining if a SPTE can be immediately | |
5327 | * overwritten for the current MMU. | |
5328 | * - level: explicitly checked in mmu_pte_write_new_pte(), and will never | |
5329 | * match the current MMU role, as MMU's level tracks the root level. | |
5330 | * - access: updated based on the new guest PTE | |
5331 | * - quadrant: handled by get_written_sptes() | |
5332 | * - invalid: always false (loop only walks valid shadow pages) | |
5333 | */ | |
5334 | static const union kvm_mmu_page_role role_ign = { | |
5335 | .level = 0xf, | |
5336 | .access = 0x7, | |
5337 | .quadrant = 0x3, | |
5338 | .invalid = 0x1, | |
5339 | }; | |
5340 | ||
13d268ca | 5341 | static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
d126363d JS |
5342 | const u8 *new, int bytes, |
5343 | struct kvm_page_track_notifier_node *node) | |
889e5cbc XG |
5344 | { |
5345 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
889e5cbc | 5346 | struct kvm_mmu_page *sp; |
889e5cbc XG |
5347 | LIST_HEAD(invalid_list); |
5348 | u64 entry, gentry, *spte; | |
5349 | int npte; | |
b8c67b7a | 5350 | bool remote_flush, local_flush; |
889e5cbc XG |
5351 | |
5352 | /* | |
5353 | * If we don't have indirect shadow pages, it means no page is | |
5354 | * write-protected, so we can exit simply. | |
5355 | */ | |
6aa7de05 | 5356 | if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) |
889e5cbc XG |
5357 | return; |
5358 | ||
b8c67b7a | 5359 | remote_flush = local_flush = false; |
889e5cbc XG |
5360 | |
5361 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
5362 | ||
889e5cbc XG |
5363 | /* |
5364 | * No need to care whether allocation memory is successful | |
5365 | * or not since pte prefetch is skiped if it does not have | |
5366 | * enough objects in the cache. | |
5367 | */ | |
5368 | mmu_topup_memory_caches(vcpu); | |
5369 | ||
5370 | spin_lock(&vcpu->kvm->mmu_lock); | |
0e0fee5c JS |
5371 | |
5372 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes); | |
5373 | ||
889e5cbc | 5374 | ++vcpu->kvm->stat.mmu_pte_write; |
0375f7fa | 5375 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 5376 | |
b67bfe0d | 5377 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 5378 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 5379 | detect_write_flooding(sp)) { |
b8c67b7a | 5380 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 5381 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
5382 | continue; |
5383 | } | |
889e5cbc XG |
5384 | |
5385 | spte = get_written_sptes(sp, gpa, &npte); | |
5386 | if (!spte) | |
5387 | continue; | |
5388 | ||
0671a8e7 | 5389 | local_flush = true; |
ac1b714e | 5390 | while (npte--) { |
36d9594d VK |
5391 | u32 base_role = vcpu->arch.mmu->mmu_role.base.word; |
5392 | ||
79539cec | 5393 | entry = *spte; |
38e3b2b2 | 5394 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf | 5395 | if (gentry && |
a102a674 SC |
5396 | !((sp->role.word ^ base_role) & ~role_ign.word) && |
5397 | rmap_can_add(vcpu)) | |
7c562522 | 5398 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
9bb4f6b1 | 5399 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 5400 | remote_flush = true; |
ac1b714e | 5401 | ++spte; |
9b7a0325 | 5402 | } |
9b7a0325 | 5403 | } |
b8c67b7a | 5404 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush); |
0375f7fa | 5405 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 5406 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
5407 | } |
5408 | ||
a436036b AK |
5409 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
5410 | { | |
10589a46 MT |
5411 | gpa_t gpa; |
5412 | int r; | |
a436036b | 5413 | |
44dd3ffa | 5414 | if (vcpu->arch.mmu->direct_map) |
60f24784 AK |
5415 | return 0; |
5416 | ||
1871c602 | 5417 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 5418 | |
10589a46 | 5419 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 5420 | |
10589a46 | 5421 | return r; |
a436036b | 5422 | } |
577bdc49 | 5423 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 5424 | |
736c291c | 5425 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code, |
dc25e89e | 5426 | void *insn, int insn_len) |
3067714c | 5427 | { |
92daa48b | 5428 | int r, emulation_type = EMULTYPE_PF; |
44dd3ffa | 5429 | bool direct = vcpu->arch.mmu->direct_map; |
3067714c | 5430 | |
6948199a | 5431 | if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa))) |
ddce6208 SC |
5432 | return RET_PF_RETRY; |
5433 | ||
9b8ebbdb | 5434 | r = RET_PF_INVALID; |
e9ee956e | 5435 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
736c291c | 5436 | r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct); |
472faffa | 5437 | if (r == RET_PF_EMULATE) |
e9ee956e | 5438 | goto emulate; |
e9ee956e | 5439 | } |
3067714c | 5440 | |
9b8ebbdb | 5441 | if (r == RET_PF_INVALID) { |
7a02674d SC |
5442 | r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa, |
5443 | lower_32_bits(error_code), false); | |
9b8ebbdb PB |
5444 | WARN_ON(r == RET_PF_INVALID); |
5445 | } | |
5446 | ||
5447 | if (r == RET_PF_RETRY) | |
5448 | return 1; | |
3067714c | 5449 | if (r < 0) |
e9ee956e | 5450 | return r; |
3067714c | 5451 | |
14727754 TL |
5452 | /* |
5453 | * Before emulating the instruction, check if the error code | |
5454 | * was due to a RO violation while translating the guest page. | |
5455 | * This can occur when using nested virtualization with nested | |
5456 | * paging in both guests. If true, we simply unprotect the page | |
5457 | * and resume the guest. | |
14727754 | 5458 | */ |
44dd3ffa | 5459 | if (vcpu->arch.mmu->direct_map && |
eebed243 | 5460 | (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) { |
736c291c | 5461 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa)); |
14727754 TL |
5462 | return 1; |
5463 | } | |
5464 | ||
472faffa SC |
5465 | /* |
5466 | * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still | |
5467 | * optimistically try to just unprotect the page and let the processor | |
5468 | * re-execute the instruction that caused the page fault. Do not allow | |
5469 | * retrying MMIO emulation, as it's not only pointless but could also | |
5470 | * cause us to enter an infinite loop because the processor will keep | |
6c3dfeb6 SC |
5471 | * faulting on the non-existent MMIO address. Retrying an instruction |
5472 | * from a nested guest is also pointless and dangerous as we are only | |
5473 | * explicitly shadowing L1's page tables, i.e. unprotecting something | |
5474 | * for L1 isn't going to magically fix whatever issue cause L2 to fail. | |
472faffa | 5475 | */ |
736c291c | 5476 | if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu)) |
92daa48b | 5477 | emulation_type |= EMULTYPE_ALLOW_RETRY_PF; |
e9ee956e | 5478 | emulate: |
00b10fe1 BS |
5479 | /* |
5480 | * On AMD platforms, under certain conditions insn_len may be zero on #NPF. | |
5481 | * This can happen if a guest gets a page-fault on data access but the HW | |
5482 | * table walker is not able to read the instruction page (e.g instruction | |
5483 | * page is not present in memory). In those cases we simply restart the | |
05d5a486 | 5484 | * guest, with the exception of AMD Erratum 1096 which is unrecoverable. |
00b10fe1 | 5485 | */ |
05d5a486 | 5486 | if (unlikely(insn && !insn_len)) { |
afaf0b2f | 5487 | if (!kvm_x86_ops.need_emulation_on_page_fault(vcpu)) |
05d5a486 SB |
5488 | return 1; |
5489 | } | |
00b10fe1 | 5490 | |
736c291c | 5491 | return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn, |
60fc3d02 | 5492 | insn_len); |
3067714c AK |
5493 | } |
5494 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
5495 | ||
5efac074 PB |
5496 | void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
5497 | gva_t gva, hpa_t root_hpa) | |
a7052897 | 5498 | { |
b94742c9 | 5499 | int i; |
7eb77e9f | 5500 | |
5efac074 PB |
5501 | /* It's actually a GPA for vcpu->arch.guest_mmu. */ |
5502 | if (mmu != &vcpu->arch.guest_mmu) { | |
5503 | /* INVLPG on a non-canonical address is a NOP according to the SDM. */ | |
5504 | if (is_noncanonical_address(gva, vcpu)) | |
5505 | return; | |
5506 | ||
5507 | kvm_x86_ops.tlb_flush_gva(vcpu, gva); | |
5508 | } | |
5509 | ||
5510 | if (!mmu->invlpg) | |
faff8758 JS |
5511 | return; |
5512 | ||
5efac074 PB |
5513 | if (root_hpa == INVALID_PAGE) { |
5514 | mmu->invlpg(vcpu, gva, mmu->root_hpa); | |
956bf353 | 5515 | |
5efac074 PB |
5516 | /* |
5517 | * INVLPG is required to invalidate any global mappings for the VA, | |
5518 | * irrespective of PCID. Since it would take us roughly similar amount | |
5519 | * of work to determine whether any of the prev_root mappings of the VA | |
5520 | * is marked global, or to just sync it blindly, so we might as well | |
5521 | * just always sync it. | |
5522 | * | |
5523 | * Mappings not reachable via the current cr3 or the prev_roots will be | |
5524 | * synced when switching to that cr3, so nothing needs to be done here | |
5525 | * for them. | |
5526 | */ | |
5527 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
5528 | if (VALID_PAGE(mmu->prev_roots[i].hpa)) | |
5529 | mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa); | |
5530 | } else { | |
5531 | mmu->invlpg(vcpu, gva, root_hpa); | |
5532 | } | |
5533 | } | |
5534 | EXPORT_SYMBOL_GPL(kvm_mmu_invalidate_gva); | |
956bf353 | 5535 | |
5efac074 PB |
5536 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
5537 | { | |
5538 | kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE); | |
a7052897 MT |
5539 | ++vcpu->stat.invlpg; |
5540 | } | |
5541 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
5542 | ||
5efac074 | 5543 | |
eb4b248e JS |
5544 | void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid) |
5545 | { | |
44dd3ffa | 5546 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
faff8758 | 5547 | bool tlb_flush = false; |
b94742c9 | 5548 | uint i; |
eb4b248e JS |
5549 | |
5550 | if (pcid == kvm_get_active_pcid(vcpu)) { | |
7eb77e9f | 5551 | mmu->invlpg(vcpu, gva, mmu->root_hpa); |
faff8758 | 5552 | tlb_flush = true; |
eb4b248e JS |
5553 | } |
5554 | ||
b94742c9 JS |
5555 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { |
5556 | if (VALID_PAGE(mmu->prev_roots[i].hpa) && | |
5557 | pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].cr3)) { | |
5558 | mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa); | |
5559 | tlb_flush = true; | |
5560 | } | |
956bf353 | 5561 | } |
ade61e28 | 5562 | |
faff8758 | 5563 | if (tlb_flush) |
afaf0b2f | 5564 | kvm_x86_ops.tlb_flush_gva(vcpu, gva); |
faff8758 | 5565 | |
eb4b248e JS |
5566 | ++vcpu->stat.invlpg; |
5567 | ||
5568 | /* | |
b94742c9 JS |
5569 | * Mappings not reachable via the current cr3 or the prev_roots will be |
5570 | * synced when switching to that cr3, so nothing needs to be done here | |
5571 | * for them. | |
eb4b248e JS |
5572 | */ |
5573 | } | |
5574 | EXPORT_SYMBOL_GPL(kvm_mmu_invpcid_gva); | |
5575 | ||
703c335d | 5576 | void kvm_configure_mmu(bool enable_tdp, int tdp_page_level) |
18552672 | 5577 | { |
bde77235 | 5578 | tdp_enabled = enable_tdp; |
703c335d SC |
5579 | |
5580 | /* | |
5581 | * max_page_level reflects the capabilities of KVM's MMU irrespective | |
5582 | * of kernel support, e.g. KVM may be capable of using 1GB pages when | |
5583 | * the kernel is not. But, KVM never creates a page size greater than | |
5584 | * what is used by the kernel for any given HVA, i.e. the kernel's | |
5585 | * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust(). | |
5586 | */ | |
5587 | if (tdp_enabled) | |
5588 | max_page_level = tdp_page_level; | |
5589 | else if (boot_cpu_has(X86_FEATURE_GBPAGES)) | |
5590 | max_page_level = PT_PDPE_LEVEL; | |
5591 | else | |
5592 | max_page_level = PT_DIRECTORY_LEVEL; | |
18552672 | 5593 | } |
bde77235 | 5594 | EXPORT_SYMBOL_GPL(kvm_configure_mmu); |
85875a13 SC |
5595 | |
5596 | /* The return value indicates if tlb flush on all vcpus is needed. */ | |
5597 | typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head); | |
5598 | ||
5599 | /* The caller should hold mmu-lock before calling this function. */ | |
5600 | static __always_inline bool | |
5601 | slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5602 | slot_level_handler fn, int start_level, int end_level, | |
5603 | gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb) | |
5604 | { | |
5605 | struct slot_rmap_walk_iterator iterator; | |
5606 | bool flush = false; | |
5607 | ||
5608 | for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn, | |
5609 | end_gfn, &iterator) { | |
5610 | if (iterator.rmap) | |
5611 | flush |= fn(kvm, iterator.rmap); | |
5612 | ||
5613 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { | |
5614 | if (flush && lock_flush_tlb) { | |
f285c633 BG |
5615 | kvm_flush_remote_tlbs_with_address(kvm, |
5616 | start_gfn, | |
5617 | iterator.gfn - start_gfn + 1); | |
85875a13 SC |
5618 | flush = false; |
5619 | } | |
5620 | cond_resched_lock(&kvm->mmu_lock); | |
5621 | } | |
5622 | } | |
5623 | ||
5624 | if (flush && lock_flush_tlb) { | |
f285c633 BG |
5625 | kvm_flush_remote_tlbs_with_address(kvm, start_gfn, |
5626 | end_gfn - start_gfn + 1); | |
85875a13 SC |
5627 | flush = false; |
5628 | } | |
5629 | ||
5630 | return flush; | |
5631 | } | |
5632 | ||
5633 | static __always_inline bool | |
5634 | slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5635 | slot_level_handler fn, int start_level, int end_level, | |
5636 | bool lock_flush_tlb) | |
5637 | { | |
5638 | return slot_handle_level_range(kvm, memslot, fn, start_level, | |
5639 | end_level, memslot->base_gfn, | |
5640 | memslot->base_gfn + memslot->npages - 1, | |
5641 | lock_flush_tlb); | |
5642 | } | |
5643 | ||
5644 | static __always_inline bool | |
5645 | slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5646 | slot_level_handler fn, bool lock_flush_tlb) | |
5647 | { | |
5648 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL, | |
5649 | PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); | |
5650 | } | |
5651 | ||
5652 | static __always_inline bool | |
5653 | slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5654 | slot_level_handler fn, bool lock_flush_tlb) | |
5655 | { | |
5656 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1, | |
5657 | PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); | |
5658 | } | |
5659 | ||
5660 | static __always_inline bool | |
5661 | slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5662 | slot_level_handler fn, bool lock_flush_tlb) | |
5663 | { | |
5664 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL, | |
5665 | PT_PAGE_TABLE_LEVEL, lock_flush_tlb); | |
5666 | } | |
5667 | ||
1cfff4d9 | 5668 | static void free_mmu_pages(struct kvm_mmu *mmu) |
6aa8b732 | 5669 | { |
1cfff4d9 JP |
5670 | free_page((unsigned long)mmu->pae_root); |
5671 | free_page((unsigned long)mmu->lm_root); | |
6aa8b732 AK |
5672 | } |
5673 | ||
1cfff4d9 | 5674 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
6aa8b732 | 5675 | { |
17ac10ad | 5676 | struct page *page; |
6aa8b732 AK |
5677 | int i; |
5678 | ||
17ac10ad | 5679 | /* |
b6b80c78 SC |
5680 | * When using PAE paging, the four PDPTEs are treated as 'root' pages, |
5681 | * while the PDP table is a per-vCPU construct that's allocated at MMU | |
5682 | * creation. When emulating 32-bit mode, cr3 is only 32 bits even on | |
5683 | * x86_64. Therefore we need to allocate the PDP table in the first | |
5684 | * 4GB of memory, which happens to fit the DMA32 zone. Except for | |
5685 | * SVM's 32-bit NPT support, TDP paging doesn't use PAE paging and can | |
5686 | * skip allocating the PDP table. | |
17ac10ad | 5687 | */ |
afaf0b2f | 5688 | if (tdp_enabled && kvm_x86_ops.get_tdp_level(vcpu) > PT32E_ROOT_LEVEL) |
b6b80c78 SC |
5689 | return 0; |
5690 | ||
254272ce | 5691 | page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32); |
17ac10ad | 5692 | if (!page) |
d7fa6ab2 WY |
5693 | return -ENOMEM; |
5694 | ||
1cfff4d9 | 5695 | mmu->pae_root = page_address(page); |
17ac10ad | 5696 | for (i = 0; i < 4; ++i) |
1cfff4d9 | 5697 | mmu->pae_root[i] = INVALID_PAGE; |
17ac10ad | 5698 | |
6aa8b732 | 5699 | return 0; |
6aa8b732 AK |
5700 | } |
5701 | ||
8018c27b | 5702 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 5703 | { |
b94742c9 | 5704 | uint i; |
1cfff4d9 | 5705 | int ret; |
b94742c9 | 5706 | |
44dd3ffa VK |
5707 | vcpu->arch.mmu = &vcpu->arch.root_mmu; |
5708 | vcpu->arch.walk_mmu = &vcpu->arch.root_mmu; | |
6aa8b732 | 5709 | |
44dd3ffa | 5710 | vcpu->arch.root_mmu.root_hpa = INVALID_PAGE; |
ad7dc69a | 5711 | vcpu->arch.root_mmu.root_cr3 = 0; |
44dd3ffa | 5712 | vcpu->arch.root_mmu.translate_gpa = translate_gpa; |
b94742c9 | 5713 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) |
44dd3ffa | 5714 | vcpu->arch.root_mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID; |
6aa8b732 | 5715 | |
14c07ad8 | 5716 | vcpu->arch.guest_mmu.root_hpa = INVALID_PAGE; |
ad7dc69a | 5717 | vcpu->arch.guest_mmu.root_cr3 = 0; |
14c07ad8 VK |
5718 | vcpu->arch.guest_mmu.translate_gpa = translate_gpa; |
5719 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
5720 | vcpu->arch.guest_mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID; | |
2c264957 | 5721 | |
14c07ad8 | 5722 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; |
1cfff4d9 JP |
5723 | |
5724 | ret = alloc_mmu_pages(vcpu, &vcpu->arch.guest_mmu); | |
5725 | if (ret) | |
5726 | return ret; | |
5727 | ||
5728 | ret = alloc_mmu_pages(vcpu, &vcpu->arch.root_mmu); | |
5729 | if (ret) | |
5730 | goto fail_allocate_root; | |
5731 | ||
5732 | return ret; | |
5733 | fail_allocate_root: | |
5734 | free_mmu_pages(&vcpu->arch.guest_mmu); | |
5735 | return ret; | |
6aa8b732 AK |
5736 | } |
5737 | ||
fbb158cb | 5738 | #define BATCH_ZAP_PAGES 10 |
002c5f73 SC |
5739 | static void kvm_zap_obsolete_pages(struct kvm *kvm) |
5740 | { | |
5741 | struct kvm_mmu_page *sp, *node; | |
fbb158cb | 5742 | int nr_zapped, batch = 0; |
002c5f73 SC |
5743 | |
5744 | restart: | |
5745 | list_for_each_entry_safe_reverse(sp, node, | |
5746 | &kvm->arch.active_mmu_pages, link) { | |
5747 | /* | |
5748 | * No obsolete valid page exists before a newly created page | |
5749 | * since active_mmu_pages is a FIFO list. | |
5750 | */ | |
5751 | if (!is_obsolete_sp(kvm, sp)) | |
5752 | break; | |
5753 | ||
5754 | /* | |
9a5c034c SC |
5755 | * Skip invalid pages with a non-zero root count, zapping pages |
5756 | * with a non-zero root count will never succeed, i.e. the page | |
5757 | * will get thrown back on active_mmu_pages and we'll get stuck | |
5758 | * in an infinite loop. | |
002c5f73 | 5759 | */ |
9a5c034c | 5760 | if (sp->role.invalid && sp->root_count) |
002c5f73 SC |
5761 | continue; |
5762 | ||
4506ecf4 SC |
5763 | /* |
5764 | * No need to flush the TLB since we're only zapping shadow | |
5765 | * pages with an obsolete generation number and all vCPUS have | |
5766 | * loaded a new root, i.e. the shadow pages being zapped cannot | |
5767 | * be in active use by the guest. | |
5768 | */ | |
fbb158cb | 5769 | if (batch >= BATCH_ZAP_PAGES && |
4506ecf4 | 5770 | cond_resched_lock(&kvm->mmu_lock)) { |
fbb158cb | 5771 | batch = 0; |
002c5f73 SC |
5772 | goto restart; |
5773 | } | |
5774 | ||
10605204 SC |
5775 | if (__kvm_mmu_prepare_zap_page(kvm, sp, |
5776 | &kvm->arch.zapped_obsolete_pages, &nr_zapped)) { | |
fbb158cb | 5777 | batch += nr_zapped; |
002c5f73 | 5778 | goto restart; |
fbb158cb | 5779 | } |
002c5f73 SC |
5780 | } |
5781 | ||
4506ecf4 SC |
5782 | /* |
5783 | * Trigger a remote TLB flush before freeing the page tables to ensure | |
5784 | * KVM is not in the middle of a lockless shadow page table walk, which | |
5785 | * may reference the pages. | |
5786 | */ | |
10605204 | 5787 | kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages); |
002c5f73 SC |
5788 | } |
5789 | ||
5790 | /* | |
5791 | * Fast invalidate all shadow pages and use lock-break technique | |
5792 | * to zap obsolete pages. | |
5793 | * | |
5794 | * It's required when memslot is being deleted or VM is being | |
5795 | * destroyed, in these cases, we should ensure that KVM MMU does | |
5796 | * not use any resource of the being-deleted slot or all slots | |
5797 | * after calling the function. | |
5798 | */ | |
5799 | static void kvm_mmu_zap_all_fast(struct kvm *kvm) | |
5800 | { | |
ca333add SC |
5801 | lockdep_assert_held(&kvm->slots_lock); |
5802 | ||
002c5f73 | 5803 | spin_lock(&kvm->mmu_lock); |
14a3c4f4 | 5804 | trace_kvm_mmu_zap_all_fast(kvm); |
ca333add SC |
5805 | |
5806 | /* | |
5807 | * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is | |
5808 | * held for the entire duration of zapping obsolete pages, it's | |
5809 | * impossible for there to be multiple invalid generations associated | |
5810 | * with *valid* shadow pages at any given time, i.e. there is exactly | |
5811 | * one valid generation and (at most) one invalid generation. | |
5812 | */ | |
5813 | kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1; | |
002c5f73 | 5814 | |
4506ecf4 SC |
5815 | /* |
5816 | * Notify all vcpus to reload its shadow page table and flush TLB. | |
5817 | * Then all vcpus will switch to new shadow page table with the new | |
5818 | * mmu_valid_gen. | |
5819 | * | |
5820 | * Note: we need to do this under the protection of mmu_lock, | |
5821 | * otherwise, vcpu would purge shadow page but miss tlb flush. | |
5822 | */ | |
5823 | kvm_reload_remote_mmus(kvm); | |
5824 | ||
002c5f73 SC |
5825 | kvm_zap_obsolete_pages(kvm); |
5826 | spin_unlock(&kvm->mmu_lock); | |
5827 | } | |
5828 | ||
10605204 SC |
5829 | static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm) |
5830 | { | |
5831 | return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages)); | |
5832 | } | |
5833 | ||
b5f5fdca | 5834 | static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm, |
d126363d JS |
5835 | struct kvm_memory_slot *slot, |
5836 | struct kvm_page_track_notifier_node *node) | |
b5f5fdca | 5837 | { |
002c5f73 | 5838 | kvm_mmu_zap_all_fast(kvm); |
1bad2b2a XG |
5839 | } |
5840 | ||
13d268ca | 5841 | void kvm_mmu_init_vm(struct kvm *kvm) |
1bad2b2a | 5842 | { |
13d268ca | 5843 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; |
1bad2b2a | 5844 | |
13d268ca | 5845 | node->track_write = kvm_mmu_pte_write; |
b5f5fdca | 5846 | node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot; |
13d268ca | 5847 | kvm_page_track_register_notifier(kvm, node); |
1bad2b2a XG |
5848 | } |
5849 | ||
13d268ca | 5850 | void kvm_mmu_uninit_vm(struct kvm *kvm) |
1bad2b2a | 5851 | { |
13d268ca | 5852 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; |
1bad2b2a | 5853 | |
13d268ca | 5854 | kvm_page_track_unregister_notifier(kvm, node); |
1bad2b2a XG |
5855 | } |
5856 | ||
efdfe536 XG |
5857 | void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end) |
5858 | { | |
5859 | struct kvm_memslots *slots; | |
5860 | struct kvm_memory_slot *memslot; | |
9da0e4d5 | 5861 | int i; |
efdfe536 XG |
5862 | |
5863 | spin_lock(&kvm->mmu_lock); | |
9da0e4d5 PB |
5864 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
5865 | slots = __kvm_memslots(kvm, i); | |
5866 | kvm_for_each_memslot(memslot, slots) { | |
5867 | gfn_t start, end; | |
5868 | ||
5869 | start = max(gfn_start, memslot->base_gfn); | |
5870 | end = min(gfn_end, memslot->base_gfn + memslot->npages); | |
5871 | if (start >= end) | |
5872 | continue; | |
efdfe536 | 5873 | |
92da008f BG |
5874 | slot_handle_level_range(kvm, memslot, kvm_zap_rmapp, |
5875 | PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL, | |
5876 | start, end - 1, true); | |
9da0e4d5 | 5877 | } |
efdfe536 XG |
5878 | } |
5879 | ||
5880 | spin_unlock(&kvm->mmu_lock); | |
5881 | } | |
5882 | ||
018aabb5 TY |
5883 | static bool slot_rmap_write_protect(struct kvm *kvm, |
5884 | struct kvm_rmap_head *rmap_head) | |
d77aa73c | 5885 | { |
018aabb5 | 5886 | return __rmap_write_protect(kvm, rmap_head, false); |
d77aa73c XG |
5887 | } |
5888 | ||
1c91cad4 | 5889 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
3c9bd400 JZ |
5890 | struct kvm_memory_slot *memslot, |
5891 | int start_level) | |
6aa8b732 | 5892 | { |
d77aa73c | 5893 | bool flush; |
6aa8b732 | 5894 | |
9d1beefb | 5895 | spin_lock(&kvm->mmu_lock); |
3c9bd400 JZ |
5896 | flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect, |
5897 | start_level, PT_MAX_HUGEPAGE_LEVEL, false); | |
9d1beefb | 5898 | spin_unlock(&kvm->mmu_lock); |
198c74f4 | 5899 | |
198c74f4 XG |
5900 | /* |
5901 | * We can flush all the TLBs out of the mmu lock without TLB | |
5902 | * corruption since we just change the spte from writable to | |
5903 | * readonly so that we only need to care the case of changing | |
5904 | * spte from present to present (changing the spte from present | |
5905 | * to nonpresent will flush all the TLBs immediately), in other | |
5906 | * words, the only case we care is mmu_spte_update() where we | |
bdd303cb | 5907 | * have checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE |
198c74f4 XG |
5908 | * instead of PT_WRITABLE_MASK, that means it does not depend |
5909 | * on PT_WRITABLE_MASK anymore. | |
5910 | */ | |
d91ffee9 | 5911 | if (flush) |
7f42aa76 | 5912 | kvm_arch_flush_remote_tlbs_memslot(kvm, memslot); |
6aa8b732 | 5913 | } |
37a7d8b0 | 5914 | |
3ea3b7fa | 5915 | static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm, |
018aabb5 | 5916 | struct kvm_rmap_head *rmap_head) |
3ea3b7fa WL |
5917 | { |
5918 | u64 *sptep; | |
5919 | struct rmap_iterator iter; | |
5920 | int need_tlb_flush = 0; | |
ba049e93 | 5921 | kvm_pfn_t pfn; |
3ea3b7fa WL |
5922 | struct kvm_mmu_page *sp; |
5923 | ||
0d536790 | 5924 | restart: |
018aabb5 | 5925 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
3ea3b7fa WL |
5926 | sp = page_header(__pa(sptep)); |
5927 | pfn = spte_to_pfn(*sptep); | |
5928 | ||
5929 | /* | |
decf6333 XG |
5930 | * We cannot do huge page mapping for indirect shadow pages, |
5931 | * which are found on the last rmap (level = 1) when not using | |
5932 | * tdp; such shadow pages are synced with the page table in | |
5933 | * the guest, and the guest page table is using 4K page size | |
5934 | * mapping if the indirect sp has level = 1. | |
3ea3b7fa | 5935 | */ |
a78986aa | 5936 | if (sp->role.direct && !kvm_is_reserved_pfn(pfn) && |
e851265a SC |
5937 | (kvm_is_zone_device_pfn(pfn) || |
5938 | PageCompound(pfn_to_page(pfn)))) { | |
e7912386 | 5939 | pte_list_remove(rmap_head, sptep); |
40ef75a7 LT |
5940 | |
5941 | if (kvm_available_flush_tlb_with_range()) | |
5942 | kvm_flush_remote_tlbs_with_address(kvm, sp->gfn, | |
5943 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
5944 | else | |
5945 | need_tlb_flush = 1; | |
5946 | ||
0d536790 XG |
5947 | goto restart; |
5948 | } | |
3ea3b7fa WL |
5949 | } |
5950 | ||
5951 | return need_tlb_flush; | |
5952 | } | |
5953 | ||
5954 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, | |
f36f3f28 | 5955 | const struct kvm_memory_slot *memslot) |
3ea3b7fa | 5956 | { |
f36f3f28 | 5957 | /* FIXME: const-ify all uses of struct kvm_memory_slot. */ |
3ea3b7fa | 5958 | spin_lock(&kvm->mmu_lock); |
f36f3f28 PB |
5959 | slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot, |
5960 | kvm_mmu_zap_collapsible_spte, true); | |
3ea3b7fa WL |
5961 | spin_unlock(&kvm->mmu_lock); |
5962 | } | |
5963 | ||
b3594ffb SC |
5964 | void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm, |
5965 | struct kvm_memory_slot *memslot) | |
5966 | { | |
5967 | /* | |
7f42aa76 SC |
5968 | * All current use cases for flushing the TLBs for a specific memslot |
5969 | * are related to dirty logging, and do the TLB flush out of mmu_lock. | |
5970 | * The interaction between the various operations on memslot must be | |
5971 | * serialized by slots_locks to ensure the TLB flush from one operation | |
5972 | * is observed by any other operation on the same memslot. | |
b3594ffb SC |
5973 | */ |
5974 | lockdep_assert_held(&kvm->slots_lock); | |
cec37648 SC |
5975 | kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn, |
5976 | memslot->npages); | |
b3594ffb SC |
5977 | } |
5978 | ||
f4b4b180 KH |
5979 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
5980 | struct kvm_memory_slot *memslot) | |
5981 | { | |
d77aa73c | 5982 | bool flush; |
f4b4b180 KH |
5983 | |
5984 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 5985 | flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false); |
f4b4b180 KH |
5986 | spin_unlock(&kvm->mmu_lock); |
5987 | ||
f4b4b180 KH |
5988 | /* |
5989 | * It's also safe to flush TLBs out of mmu lock here as currently this | |
5990 | * function is only used for dirty logging, in which case flushing TLB | |
5991 | * out of mmu lock also guarantees no dirty pages will be lost in | |
5992 | * dirty_bitmap. | |
5993 | */ | |
5994 | if (flush) | |
7f42aa76 | 5995 | kvm_arch_flush_remote_tlbs_memslot(kvm, memslot); |
f4b4b180 KH |
5996 | } |
5997 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty); | |
5998 | ||
5999 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
6000 | struct kvm_memory_slot *memslot) | |
6001 | { | |
d77aa73c | 6002 | bool flush; |
f4b4b180 KH |
6003 | |
6004 | spin_lock(&kvm->mmu_lock); | |
d77aa73c XG |
6005 | flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect, |
6006 | false); | |
f4b4b180 KH |
6007 | spin_unlock(&kvm->mmu_lock); |
6008 | ||
f4b4b180 | 6009 | if (flush) |
7f42aa76 | 6010 | kvm_arch_flush_remote_tlbs_memslot(kvm, memslot); |
f4b4b180 KH |
6011 | } |
6012 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access); | |
6013 | ||
6014 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
6015 | struct kvm_memory_slot *memslot) | |
6016 | { | |
d77aa73c | 6017 | bool flush; |
f4b4b180 KH |
6018 | |
6019 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 6020 | flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false); |
f4b4b180 KH |
6021 | spin_unlock(&kvm->mmu_lock); |
6022 | ||
f4b4b180 | 6023 | if (flush) |
7f42aa76 | 6024 | kvm_arch_flush_remote_tlbs_memslot(kvm, memslot); |
f4b4b180 KH |
6025 | } |
6026 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty); | |
6027 | ||
92f58b5c | 6028 | void kvm_mmu_zap_all(struct kvm *kvm) |
5304b8d3 XG |
6029 | { |
6030 | struct kvm_mmu_page *sp, *node; | |
7390de1e | 6031 | LIST_HEAD(invalid_list); |
83cdb568 | 6032 | int ign; |
5304b8d3 | 6033 | |
7390de1e | 6034 | spin_lock(&kvm->mmu_lock); |
5304b8d3 | 6035 | restart: |
8a674adc | 6036 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) { |
8ab3c471 | 6037 | if (sp->role.invalid && sp->root_count) |
4771450c | 6038 | continue; |
92f58b5c | 6039 | if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign)) |
5304b8d3 | 6040 | goto restart; |
24efe61f | 6041 | if (cond_resched_lock(&kvm->mmu_lock)) |
5304b8d3 XG |
6042 | goto restart; |
6043 | } | |
6044 | ||
4771450c | 6045 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
5304b8d3 XG |
6046 | spin_unlock(&kvm->mmu_lock); |
6047 | } | |
6048 | ||
15248258 | 6049 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen) |
f8f55942 | 6050 | { |
164bf7e5 | 6051 | WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS); |
e1359e2b | 6052 | |
164bf7e5 | 6053 | gen &= MMIO_SPTE_GEN_MASK; |
e1359e2b | 6054 | |
f8f55942 | 6055 | /* |
e1359e2b SC |
6056 | * Generation numbers are incremented in multiples of the number of |
6057 | * address spaces in order to provide unique generations across all | |
6058 | * address spaces. Strip what is effectively the address space | |
6059 | * modifier prior to checking for a wrap of the MMIO generation so | |
6060 | * that a wrap in any address space is detected. | |
6061 | */ | |
6062 | gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1); | |
6063 | ||
f8f55942 | 6064 | /* |
e1359e2b | 6065 | * The very rare case: if the MMIO generation number has wrapped, |
f8f55942 | 6066 | * zap all shadow pages. |
f8f55942 | 6067 | */ |
e1359e2b | 6068 | if (unlikely(gen == 0)) { |
ae0f5499 | 6069 | kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n"); |
92f58b5c | 6070 | kvm_mmu_zap_all_fast(kvm); |
7a2e8aaf | 6071 | } |
f8f55942 XG |
6072 | } |
6073 | ||
70534a73 DC |
6074 | static unsigned long |
6075 | mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) | |
3ee16c81 IE |
6076 | { |
6077 | struct kvm *kvm; | |
1495f230 | 6078 | int nr_to_scan = sc->nr_to_scan; |
70534a73 | 6079 | unsigned long freed = 0; |
3ee16c81 | 6080 | |
0d9ce162 | 6081 | mutex_lock(&kvm_lock); |
3ee16c81 IE |
6082 | |
6083 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 6084 | int idx; |
d98ba053 | 6085 | LIST_HEAD(invalid_list); |
3ee16c81 | 6086 | |
35f2d16b TY |
6087 | /* |
6088 | * Never scan more than sc->nr_to_scan VM instances. | |
6089 | * Will not hit this condition practically since we do not try | |
6090 | * to shrink more than one VM and it is very unlikely to see | |
6091 | * !n_used_mmu_pages so many times. | |
6092 | */ | |
6093 | if (!nr_to_scan--) | |
6094 | break; | |
19526396 GN |
6095 | /* |
6096 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
6097 | * here. We may skip a VM instance errorneosly, but we do not | |
6098 | * want to shrink a VM that only started to populate its MMU | |
6099 | * anyway. | |
6100 | */ | |
10605204 SC |
6101 | if (!kvm->arch.n_used_mmu_pages && |
6102 | !kvm_has_zapped_obsolete_pages(kvm)) | |
19526396 | 6103 | continue; |
19526396 | 6104 | |
f656ce01 | 6105 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 6106 | spin_lock(&kvm->mmu_lock); |
3ee16c81 | 6107 | |
10605204 SC |
6108 | if (kvm_has_zapped_obsolete_pages(kvm)) { |
6109 | kvm_mmu_commit_zap_page(kvm, | |
6110 | &kvm->arch.zapped_obsolete_pages); | |
6111 | goto unlock; | |
6112 | } | |
6113 | ||
70534a73 DC |
6114 | if (prepare_zap_oldest_mmu_page(kvm, &invalid_list)) |
6115 | freed++; | |
d98ba053 | 6116 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
19526396 | 6117 | |
10605204 | 6118 | unlock: |
3ee16c81 | 6119 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 6120 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 | 6121 | |
70534a73 DC |
6122 | /* |
6123 | * unfair on small ones | |
6124 | * per-vm shrinkers cry out | |
6125 | * sadness comes quickly | |
6126 | */ | |
19526396 GN |
6127 | list_move_tail(&kvm->vm_list, &vm_list); |
6128 | break; | |
3ee16c81 | 6129 | } |
3ee16c81 | 6130 | |
0d9ce162 | 6131 | mutex_unlock(&kvm_lock); |
70534a73 | 6132 | return freed; |
70534a73 DC |
6133 | } |
6134 | ||
6135 | static unsigned long | |
6136 | mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc) | |
6137 | { | |
45221ab6 | 6138 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
6139 | } |
6140 | ||
6141 | static struct shrinker mmu_shrinker = { | |
70534a73 DC |
6142 | .count_objects = mmu_shrink_count, |
6143 | .scan_objects = mmu_shrink_scan, | |
3ee16c81 IE |
6144 | .seeks = DEFAULT_SEEKS * 10, |
6145 | }; | |
6146 | ||
2ddfd20e | 6147 | static void mmu_destroy_caches(void) |
b5a33a75 | 6148 | { |
c1bd743e TH |
6149 | kmem_cache_destroy(pte_list_desc_cache); |
6150 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
6151 | } |
6152 | ||
7b6f8a06 KH |
6153 | static void kvm_set_mmio_spte_mask(void) |
6154 | { | |
6155 | u64 mask; | |
7b6f8a06 KH |
6156 | |
6157 | /* | |
6158 | * Set the reserved bits and the present bit of an paging-structure | |
6159 | * entry to generate page fault with PFER.RSV = 1. | |
6160 | */ | |
6161 | ||
6162 | /* | |
6163 | * Mask the uppermost physical address bit, which would be reserved as | |
6164 | * long as the supported physical address width is less than 52. | |
6165 | */ | |
6166 | mask = 1ull << 51; | |
6167 | ||
6168 | /* Set the present bit. */ | |
6169 | mask |= 1ull; | |
6170 | ||
6171 | /* | |
6172 | * If reserved bit is not supported, clear the present bit to disable | |
6173 | * mmio page fault. | |
6174 | */ | |
e30a7d62 | 6175 | if (shadow_phys_bits == 52) |
7b6f8a06 KH |
6176 | mask &= ~1ull; |
6177 | ||
4af77151 | 6178 | kvm_mmu_set_mmio_spte_mask(mask, mask, ACC_WRITE_MASK | ACC_USER_MASK); |
7b6f8a06 KH |
6179 | } |
6180 | ||
b8e8c830 PB |
6181 | static bool get_nx_auto_mode(void) |
6182 | { | |
6183 | /* Return true when CPU has the bug, and mitigations are ON */ | |
6184 | return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off(); | |
6185 | } | |
6186 | ||
6187 | static void __set_nx_huge_pages(bool val) | |
6188 | { | |
6189 | nx_huge_pages = itlb_multihit_kvm_mitigation = val; | |
6190 | } | |
6191 | ||
6192 | static int set_nx_huge_pages(const char *val, const struct kernel_param *kp) | |
6193 | { | |
6194 | bool old_val = nx_huge_pages; | |
6195 | bool new_val; | |
6196 | ||
6197 | /* In "auto" mode deploy workaround only if CPU has the bug. */ | |
6198 | if (sysfs_streq(val, "off")) | |
6199 | new_val = 0; | |
6200 | else if (sysfs_streq(val, "force")) | |
6201 | new_val = 1; | |
6202 | else if (sysfs_streq(val, "auto")) | |
6203 | new_val = get_nx_auto_mode(); | |
6204 | else if (strtobool(val, &new_val) < 0) | |
6205 | return -EINVAL; | |
6206 | ||
6207 | __set_nx_huge_pages(new_val); | |
6208 | ||
6209 | if (new_val != old_val) { | |
6210 | struct kvm *kvm; | |
b8e8c830 PB |
6211 | |
6212 | mutex_lock(&kvm_lock); | |
6213 | ||
6214 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
ed69a6cb | 6215 | mutex_lock(&kvm->slots_lock); |
b8e8c830 | 6216 | kvm_mmu_zap_all_fast(kvm); |
ed69a6cb | 6217 | mutex_unlock(&kvm->slots_lock); |
1aa9b957 JS |
6218 | |
6219 | wake_up_process(kvm->arch.nx_lpage_recovery_thread); | |
b8e8c830 PB |
6220 | } |
6221 | mutex_unlock(&kvm_lock); | |
6222 | } | |
6223 | ||
6224 | return 0; | |
6225 | } | |
6226 | ||
b5a33a75 AK |
6227 | int kvm_mmu_module_init(void) |
6228 | { | |
ab271bd4 AB |
6229 | int ret = -ENOMEM; |
6230 | ||
b8e8c830 PB |
6231 | if (nx_huge_pages == -1) |
6232 | __set_nx_huge_pages(get_nx_auto_mode()); | |
6233 | ||
36d9594d VK |
6234 | /* |
6235 | * MMU roles use union aliasing which is, generally speaking, an | |
6236 | * undefined behavior. However, we supposedly know how compilers behave | |
6237 | * and the current status quo is unlikely to change. Guardians below are | |
6238 | * supposed to let us know if the assumption becomes false. | |
6239 | */ | |
6240 | BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32)); | |
6241 | BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32)); | |
6242 | BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64)); | |
6243 | ||
28a1f3ac | 6244 | kvm_mmu_reset_all_pte_masks(); |
f160c7b7 | 6245 | |
7b6f8a06 KH |
6246 | kvm_set_mmio_spte_mask(); |
6247 | ||
53c07b18 XG |
6248 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
6249 | sizeof(struct pte_list_desc), | |
46bea48a | 6250 | 0, SLAB_ACCOUNT, NULL); |
53c07b18 | 6251 | if (!pte_list_desc_cache) |
ab271bd4 | 6252 | goto out; |
b5a33a75 | 6253 | |
d3d25b04 AK |
6254 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
6255 | sizeof(struct kvm_mmu_page), | |
46bea48a | 6256 | 0, SLAB_ACCOUNT, NULL); |
d3d25b04 | 6257 | if (!mmu_page_header_cache) |
ab271bd4 | 6258 | goto out; |
d3d25b04 | 6259 | |
908c7f19 | 6260 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL)) |
ab271bd4 | 6261 | goto out; |
45bf21a8 | 6262 | |
ab271bd4 AB |
6263 | ret = register_shrinker(&mmu_shrinker); |
6264 | if (ret) | |
6265 | goto out; | |
3ee16c81 | 6266 | |
b5a33a75 AK |
6267 | return 0; |
6268 | ||
ab271bd4 | 6269 | out: |
3ee16c81 | 6270 | mmu_destroy_caches(); |
ab271bd4 | 6271 | return ret; |
b5a33a75 AK |
6272 | } |
6273 | ||
3ad82a7e | 6274 | /* |
39337ad1 | 6275 | * Calculate mmu pages needed for kvm. |
3ad82a7e | 6276 | */ |
bc8a3d89 | 6277 | unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm) |
3ad82a7e | 6278 | { |
bc8a3d89 BG |
6279 | unsigned long nr_mmu_pages; |
6280 | unsigned long nr_pages = 0; | |
bc6678a3 | 6281 | struct kvm_memslots *slots; |
be6ba0f0 | 6282 | struct kvm_memory_slot *memslot; |
9da0e4d5 | 6283 | int i; |
3ad82a7e | 6284 | |
9da0e4d5 PB |
6285 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
6286 | slots = __kvm_memslots(kvm, i); | |
90d83dc3 | 6287 | |
9da0e4d5 PB |
6288 | kvm_for_each_memslot(memslot, slots) |
6289 | nr_pages += memslot->npages; | |
6290 | } | |
3ad82a7e ZX |
6291 | |
6292 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
bc8a3d89 | 6293 | nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES); |
3ad82a7e ZX |
6294 | |
6295 | return nr_mmu_pages; | |
6296 | } | |
6297 | ||
c42fffe3 XG |
6298 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
6299 | { | |
95f93af4 | 6300 | kvm_mmu_unload(vcpu); |
1cfff4d9 JP |
6301 | free_mmu_pages(&vcpu->arch.root_mmu); |
6302 | free_mmu_pages(&vcpu->arch.guest_mmu); | |
c42fffe3 | 6303 | mmu_free_memory_caches(vcpu); |
b034cf01 XG |
6304 | } |
6305 | ||
b034cf01 XG |
6306 | void kvm_mmu_module_exit(void) |
6307 | { | |
6308 | mmu_destroy_caches(); | |
6309 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
6310 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
6311 | mmu_audit_disable(); |
6312 | } | |
1aa9b957 JS |
6313 | |
6314 | static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp) | |
6315 | { | |
6316 | unsigned int old_val; | |
6317 | int err; | |
6318 | ||
6319 | old_val = nx_huge_pages_recovery_ratio; | |
6320 | err = param_set_uint(val, kp); | |
6321 | if (err) | |
6322 | return err; | |
6323 | ||
6324 | if (READ_ONCE(nx_huge_pages) && | |
6325 | !old_val && nx_huge_pages_recovery_ratio) { | |
6326 | struct kvm *kvm; | |
6327 | ||
6328 | mutex_lock(&kvm_lock); | |
6329 | ||
6330 | list_for_each_entry(kvm, &vm_list, vm_list) | |
6331 | wake_up_process(kvm->arch.nx_lpage_recovery_thread); | |
6332 | ||
6333 | mutex_unlock(&kvm_lock); | |
6334 | } | |
6335 | ||
6336 | return err; | |
6337 | } | |
6338 | ||
6339 | static void kvm_recover_nx_lpages(struct kvm *kvm) | |
6340 | { | |
6341 | int rcu_idx; | |
6342 | struct kvm_mmu_page *sp; | |
6343 | unsigned int ratio; | |
6344 | LIST_HEAD(invalid_list); | |
6345 | ulong to_zap; | |
6346 | ||
6347 | rcu_idx = srcu_read_lock(&kvm->srcu); | |
6348 | spin_lock(&kvm->mmu_lock); | |
6349 | ||
6350 | ratio = READ_ONCE(nx_huge_pages_recovery_ratio); | |
6351 | to_zap = ratio ? DIV_ROUND_UP(kvm->stat.nx_lpage_splits, ratio) : 0; | |
6352 | while (to_zap && !list_empty(&kvm->arch.lpage_disallowed_mmu_pages)) { | |
6353 | /* | |
6354 | * We use a separate list instead of just using active_mmu_pages | |
6355 | * because the number of lpage_disallowed pages is expected to | |
6356 | * be relatively small compared to the total. | |
6357 | */ | |
6358 | sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages, | |
6359 | struct kvm_mmu_page, | |
6360 | lpage_disallowed_link); | |
6361 | WARN_ON_ONCE(!sp->lpage_disallowed); | |
6362 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); | |
6363 | WARN_ON_ONCE(sp->lpage_disallowed); | |
6364 | ||
6365 | if (!--to_zap || need_resched() || spin_needbreak(&kvm->mmu_lock)) { | |
6366 | kvm_mmu_commit_zap_page(kvm, &invalid_list); | |
6367 | if (to_zap) | |
6368 | cond_resched_lock(&kvm->mmu_lock); | |
6369 | } | |
6370 | } | |
6371 | ||
6372 | spin_unlock(&kvm->mmu_lock); | |
6373 | srcu_read_unlock(&kvm->srcu, rcu_idx); | |
6374 | } | |
6375 | ||
6376 | static long get_nx_lpage_recovery_timeout(u64 start_time) | |
6377 | { | |
6378 | return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio) | |
6379 | ? start_time + 60 * HZ - get_jiffies_64() | |
6380 | : MAX_SCHEDULE_TIMEOUT; | |
6381 | } | |
6382 | ||
6383 | static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data) | |
6384 | { | |
6385 | u64 start_time; | |
6386 | long remaining_time; | |
6387 | ||
6388 | while (true) { | |
6389 | start_time = get_jiffies_64(); | |
6390 | remaining_time = get_nx_lpage_recovery_timeout(start_time); | |
6391 | ||
6392 | set_current_state(TASK_INTERRUPTIBLE); | |
6393 | while (!kthread_should_stop() && remaining_time > 0) { | |
6394 | schedule_timeout(remaining_time); | |
6395 | remaining_time = get_nx_lpage_recovery_timeout(start_time); | |
6396 | set_current_state(TASK_INTERRUPTIBLE); | |
6397 | } | |
6398 | ||
6399 | set_current_state(TASK_RUNNING); | |
6400 | ||
6401 | if (kthread_should_stop()) | |
6402 | return 0; | |
6403 | ||
6404 | kvm_recover_nx_lpages(kvm); | |
6405 | } | |
6406 | } | |
6407 | ||
6408 | int kvm_mmu_post_init_vm(struct kvm *kvm) | |
6409 | { | |
6410 | int err; | |
6411 | ||
6412 | err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0, | |
6413 | "kvm-nx-lpage-recovery", | |
6414 | &kvm->arch.nx_lpage_recovery_thread); | |
6415 | if (!err) | |
6416 | kthread_unpark(kvm->arch.nx_lpage_recovery_thread); | |
6417 | ||
6418 | return err; | |
6419 | } | |
6420 | ||
6421 | void kvm_mmu_pre_destroy_vm(struct kvm *kvm) | |
6422 | { | |
6423 | if (kvm->arch.nx_lpage_recovery_thread) | |
6424 | kthread_stop(kvm->arch.nx_lpage_recovery_thread); | |
6425 | } |