[linux-2.6-block.git] / arch / x86 / kvm / lapic.h

#ifndef __KVM_X86_LAPIC_H
#define __KVM_X86_LAPIC_H

#include <kvm/iodev.h>

#include <linux/kvm_host.h>

#define KVM_APIC_INIT		0
#define KVM_APIC_SIPI		1
#define KVM_APIC_LVT_NUM	6

#define KVM_APIC_SHORT_MASK	0xc0000
#define KVM_APIC_DEST_MASK	0x800

struct kvm_timer {
	struct hrtimer timer;
	s64 period; 				/* unit: ns */
	u32 timer_mode;
	u32 timer_mode_mask;
	u64 tscdeadline;
	u64 expired_tscdeadline;
	atomic_t pending;			/* accumulated triggered timers */
	bool hv_timer_in_use;
};

struct kvm_lapic {
	unsigned long base_address;
	struct kvm_io_device dev;
	struct kvm_timer lapic_timer;
	u32 divide_count;
	struct kvm_vcpu *vcpu;
	bool sw_enabled;
	bool irr_pending;
	bool lvt0_in_nmi_mode;
	/* Number of bits set in ISR. */
	s16 isr_count;
	/* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
	int highest_isr_cache;
	/**
	 * APIC register page.  The layout matches the register layout seen by
	 * the guest 1:1, because it is accessed by the vmx microcode.
	 * Note: Only one register, the TPR, is used by the microcode.
	 */
	void *regs;
	gpa_t vapic_addr;
	struct gfn_to_hva_cache vapic_cache;
	unsigned long pending_events;
	unsigned int sipi_vector;
};

struct dest_map;

int kvm_create_lapic(struct kvm_vcpu *vcpu);
void kvm_free_lapic(struct kvm_vcpu *vcpu);

int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
void kvm_apic_accept_events(struct kvm_vcpu *vcpu);
void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
void kvm_apic_set_version(struct kvm_vcpu *vcpu);
int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val);
int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
		       void *data);
bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
			   int short_hand, unsigned int dest, int dest_mode);

void __kvm_apic_update_irr(u32 *pir, void *regs);
void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir);
int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
		     struct dest_map *dest_map);
int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);

bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
		struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map);

u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);

u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);

void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);

int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);

int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);

int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);

static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
{
	return vcpu->arch.hyperv.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE;
}

int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data);
void kvm_lapic_init(void);

#define VEC_POS(v) ((v) & (32 - 1))
#define REG_POS(v) (((v) >> 5) << 4)

static inline void kvm_lapic_set_vector(int vec, void *bitmap)
{
	set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
}

static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
{
	kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
	/*
	 * irr_pending must be true if any interrupt is pending; set it after
	 * APIC_IRR to avoid race with apic_clear_irr
	 */
	apic->irr_pending = true;
}

static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
{
	return *((u32 *) (apic->regs + reg_off));
}

static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
{
	*((u32 *) (apic->regs + reg_off)) = val;
}

extern struct static_key kvm_no_apic_vcpu;

static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
{
	if (static_key_false(&kvm_no_apic_vcpu))
		return vcpu->arch.apic;
	return true;
}

extern struct static_key_deferred apic_hw_disabled;

static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic)
{
	if (static_key_false(&apic_hw_disabled.key))
		return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
	return MSR_IA32_APICBASE_ENABLE;
}

extern struct static_key_deferred apic_sw_disabled;

static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
{
	if (static_key_false(&apic_sw_disabled.key))
		return apic->sw_enabled;
	return true;
}

static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
{
	return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
}

static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
{
	return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
}

static inline int apic_x2apic_mode(struct kvm_lapic *apic)
{
	return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
}

static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
{
	return vcpu->arch.apic && vcpu->arch.apicv_active;
}

static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu)
{
	return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
}

static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq)
{
	return (irq->delivery_mode == APIC_DM_LOWEST ||
			irq->msi_redir_hint);
}

static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
{
	return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
}

static inline u32 kvm_apic_id(struct kvm_lapic *apic)
{
	/* To avoid a race between apic_base and following APIC_ID update when
	 * switching to x2apic_mode, the x2apic mode returns initial x2apic id.
	 */
	if (apic_x2apic_mode(apic))
		return apic->vcpu->vcpu_id;

	return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
}

bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);

void wait_lapic_expire(struct kvm_vcpu *vcpu);

bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
			struct kvm_vcpu **dest_vcpu);
int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
			const unsigned long *bitmap, u32 bitmap_size);
void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
#endif
Commit	Line	Data
82470196 ZX	1	#ifndef __KVM_X86_LAPIC_H
	2	#define __KVM_X86_LAPIC_H
	3
af669ac6	4	#include <kvm/iodev.h>
82470196 ZX	5
	6	#include <linux/kvm_host.h>
	7
66450a21 JK	8	#define KVM_APIC_INIT 0
66450a21 JK	9	#define KVM_APIC_SIPI 1
1e6e2755	10	#define KVM_APIC_LVT_NUM 6
66450a21	11
18f40c53 SS	12	#define KVM_APIC_SHORT_MASK 0xc0000
	13	#define KVM_APIC_DEST_MASK 0x800
	14
e9d90d47 AK	15	struct kvm_timer {
	16	struct hrtimer timer;
	17	s64 period; /* unit: ns */
a323b409	18	u32 timer_mode;
e9d90d47 AK	19	u32 timer_mode_mask;
e9d90d47 AK	20	u64 tscdeadline;
d0659d94	21	u64 expired_tscdeadline;
e9d90d47	22	atomic_t pending; /* accumulated triggered timers */
ce7a058a	23	bool hv_timer_in_use;
e9d90d47 AK	24	};
e9d90d47 AK	25
82470196 ZX	26	struct kvm_lapic {
	27	unsigned long base_address;
	28	struct kvm_io_device dev;
d3c7b77d MT	29	struct kvm_timer lapic_timer;
d3c7b77d MT	30	u32 divide_count;
82470196	31	struct kvm_vcpu *vcpu;
e462755c	32	bool sw_enabled;
33e4c686	33	bool irr_pending;
59fd1323	34	bool lvt0_in_nmi_mode;
8680b94b MT	35	/* Number of bits set in ISR. */
	36	s16 isr_count;
	37	/* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
	38	int highest_isr_cache;
5eadf916 MT	39	/**
	40	* APIC register page. The layout matches the register layout seen by
	41	* the guest 1:1, because it is accessed by the vmx microcode.
	42	* Note: Only one register, the TPR, is used by the microcode.
	43	*/
82470196	44	void *regs;
b93463aa	45	gpa_t vapic_addr;
fda4e2e8	46	struct gfn_to_hva_cache vapic_cache;
66450a21 JK	47	unsigned long pending_events;
66450a21 JK	48	unsigned int sipi_vector;
82470196	49	};
9e4aabe2 JR	50
	51	struct dest_map;
	52
82470196 ZX	53	int kvm_create_lapic(struct kvm_vcpu *vcpu);
	54	void kvm_free_lapic(struct kvm_vcpu *vcpu);
	55
	56	int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
	57	int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
	58	int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
66450a21	59	void kvm_apic_accept_events(struct kvm_vcpu *vcpu);
d28bc9dd	60	void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
82470196 ZX	61	u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
82470196 ZX	62	void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
58fbbf26	63	void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
82470196	64	void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
8b2cf73c	65	u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
fc61b800	66	void kvm_apic_set_version(struct kvm_vcpu *vcpu);
1e6e2755 SS	67	int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val);
	68	int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
	69	void *data);
	70	bool kvm_apic_match_dest(struct kvm_vcpu vcpu, struct kvm_lapic source,
	71	int short_hand, unsigned int dest, int dest_mode);
82470196	72
705699a1	73	void __kvm_apic_update_irr(u32 pir, void regs);
a20ed54d	74	void kvm_apic_update_irr(struct kvm_vcpu vcpu, u32 pir);
b4f2225c	75	int kvm_apic_set_irq(struct kvm_vcpu vcpu, struct kvm_lapic_irq irq,
9e4aabe2	76	struct dest_map *dest_map);
89342082	77	int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
82470196	78
1e08ec4a	79	bool kvm_irq_delivery_to_apic_fast(struct kvm kvm, struct kvm_lapic src,
9e4aabe2	80	struct kvm_lapic_irq irq, int r, struct dest_map *dest_map);
1e08ec4a	81
82470196	82	u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
58cb628d	83	int kvm_set_apic_base(struct kvm_vcpu vcpu, struct msr_data msr_info);
a92e2543 RK	84	int kvm_apic_get_state(struct kvm_vcpu vcpu, struct kvm_lapic_state s);
a92e2543 RK	85	int kvm_apic_set_state(struct kvm_vcpu vcpu, struct kvm_lapic_state s);
82470196	86	int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
82470196	87
a3e06bbe LJ	88	u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
	89	void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
	90
83d4c286	91	void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
c7c9c56c	92	void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
83d4c286	93
fda4e2e8	94	int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
b93463aa AK	95	void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
	96	void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
	97
0105d1a5 GN	98	int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
0105d1a5 GN	99	int kvm_x2apic_msr_read(struct kvm_vcpu vcpu, u32 msr, u64 data);
10388a07 GN	100
	101	int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
	102	int kvm_hv_vapic_msr_read(struct kvm_vcpu vcpu, u32 msr, u64 data);
	103
	104	static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
	105	{
e83d5887	106	return vcpu->arch.hyperv.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE;
10388a07	107	}
ae7a2a3f MT	108
ae7a2a3f MT	109	int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data);
c5cc421b	110	void kvm_lapic_init(void);
c48f1496	111
1e6e2755 SS	112	#define VEC_POS(v) ((v) & (32 - 1))
	113	#define REG_POS(v) (((v) >> 5) << 4)
	114
	115	static inline void kvm_lapic_set_vector(int vec, void *bitmap)
	116	{
	117	set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
	118	}
	119
	120	static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
	121	{
	122	kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
	123	/*
	124	* irr_pending must be true if any interrupt is pending; set it after
	125	* APIC_IRR to avoid race with apic_clear_irr
	126	*/
	127	apic->irr_pending = true;
	128	}
	129
dfb95954	130	static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
c48f1496	131	{
dfb95954	132	return ((u32 ) (apic->regs + reg_off));
c48f1496 GN	133	}
c48f1496 GN	134
1e6e2755 SS	135	static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
	136	{
	137	((u32 ) (apic->regs + reg_off)) = val;
	138	}
	139
c48f1496 GN	140	extern struct static_key kvm_no_apic_vcpu;
c48f1496 GN	141
bce87cce	142	static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
c48f1496 GN	143	{
	144	if (static_key_false(&kvm_no_apic_vcpu))
	145	return vcpu->arch.apic;
	146	return true;
	147	}
	148
	149	extern struct static_key_deferred apic_hw_disabled;
	150
	151	static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic)
	152	{
	153	if (static_key_false(&apic_hw_disabled.key))
	154	return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
	155	return MSR_IA32_APICBASE_ENABLE;
	156	}
	157
	158	extern struct static_key_deferred apic_sw_disabled;
	159
f30ebc31	160	static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
c48f1496 GN	161	{
c48f1496 GN	162	if (static_key_false(&apic_sw_disabled.key))
f30ebc31 RK	163	return apic->sw_enabled;
f30ebc31 RK	164	return true;
c48f1496 GN	165	}
	166
	167	static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
	168	{
bce87cce	169	return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
c48f1496 GN	170	}
	171
	172	static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
	173	{
	174	return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
	175	}
	176
8d14695f YZ	177	static inline int apic_x2apic_mode(struct kvm_lapic *apic)
	178	{
	179	return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
	180	}
	181
d62caabb	182	static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
c7c9c56c	183	{
d62caabb	184	return vcpu->arch.apic && vcpu->arch.apicv_active;
c7c9c56c YZ	185	}
c7c9c56c YZ	186
66450a21 JK	187	static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu)
66450a21 JK	188	{
bce87cce	189	return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
66450a21 JK	190	}
66450a21 JK	191
d1ebdbf9 JS	192	static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq)
	193	{
	194	return (irq->delivery_mode == APIC_DM_LOWEST \|\|
	195	irq->msi_redir_hint);
	196	}
	197
f077825a PB	198	static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
f077825a PB	199	{
bce87cce	200	return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
f077825a PB	201	}
f077825a PB	202
0ca52e7b	203	static inline u32 kvm_apic_id(struct kvm_lapic *apic)
5c919412	204	{
a92e2543 RK	205	/* To avoid a race between apic_base and following APIC_ID update when
	206	* switching to x2apic_mode, the x2apic mode returns initial x2apic id.
	207	*/
	208	if (apic_x2apic_mode(apic))
	209	return apic->vcpu->vcpu_id;
	210
	211	return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
5c919412 AS	212	}
5c919412 AS	213
10606919 YZ	214	bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
10606919 YZ	215
d0659d94 MT	216	void wait_lapic_expire(struct kvm_vcpu *vcpu);
d0659d94 MT	217
8feb4a04 FW	218	bool kvm_intr_is_single_vcpu_fast(struct kvm kvm, struct kvm_lapic_irq irq,
8feb4a04 FW	219	struct kvm_vcpu **dest_vcpu);
52004014 FW	220	int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
52004014 FW	221	const unsigned long *bitmap, u32 bitmap_size);
ce7a058a YJ	222	void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
	223	void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
	224	void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
	225	bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
82470196	226	#endif