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82470196 ZX |
1 | #ifndef __KVM_X86_LAPIC_H |
2 | #define __KVM_X86_LAPIC_H | |
3 | ||
4 | #include "iodev.h" | |
5 | ||
6 | #include <linux/kvm_host.h> | |
7 | ||
e9d90d47 AK |
8 | struct kvm_timer { |
9 | struct hrtimer timer; | |
10 | s64 period; /* unit: ns */ | |
11 | u32 timer_mode_mask; | |
12 | u64 tscdeadline; | |
13 | atomic_t pending; /* accumulated triggered timers */ | |
e9d90d47 AK |
14 | }; |
15 | ||
82470196 ZX |
16 | struct kvm_lapic { |
17 | unsigned long base_address; | |
18 | struct kvm_io_device dev; | |
d3c7b77d MT |
19 | struct kvm_timer lapic_timer; |
20 | u32 divide_count; | |
82470196 | 21 | struct kvm_vcpu *vcpu; |
33e4c686 | 22 | bool irr_pending; |
8680b94b MT |
23 | /* Number of bits set in ISR. */ |
24 | s16 isr_count; | |
25 | /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */ | |
26 | int highest_isr_cache; | |
5eadf916 MT |
27 | /** |
28 | * APIC register page. The layout matches the register layout seen by | |
29 | * the guest 1:1, because it is accessed by the vmx microcode. | |
30 | * Note: Only one register, the TPR, is used by the microcode. | |
31 | */ | |
82470196 | 32 | void *regs; |
b93463aa AK |
33 | gpa_t vapic_addr; |
34 | struct page *vapic_page; | |
82470196 ZX |
35 | }; |
36 | int kvm_create_lapic(struct kvm_vcpu *vcpu); | |
37 | void kvm_free_lapic(struct kvm_vcpu *vcpu); | |
38 | ||
39 | int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu); | |
40 | int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu); | |
41 | int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu); | |
42 | void kvm_lapic_reset(struct kvm_vcpu *vcpu); | |
43 | u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu); | |
44 | void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8); | |
58fbbf26 | 45 | void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu); |
82470196 | 46 | void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value); |
8b2cf73c | 47 | u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu); |
fc61b800 | 48 | void kvm_apic_set_version(struct kvm_vcpu *vcpu); |
82470196 ZX |
49 | |
50 | int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest); | |
51 | int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda); | |
58c2dde1 | 52 | int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq); |
89342082 | 53 | int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type); |
82470196 | 54 | |
1e08ec4a GN |
55 | bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, |
56 | struct kvm_lapic_irq *irq, int *r); | |
57 | ||
82470196 ZX |
58 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu); |
59 | void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data); | |
64eb0620 GN |
60 | void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu, |
61 | struct kvm_lapic_state *s); | |
82470196 | 62 | int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu); |
82470196 | 63 | |
a3e06bbe LJ |
64 | u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu); |
65 | void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data); | |
66 | ||
83d4c286 YZ |
67 | void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset); |
68 | ||
b93463aa AK |
69 | void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr); |
70 | void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu); | |
71 | void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu); | |
72 | ||
0105d1a5 GN |
73 | int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); |
74 | int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); | |
10388a07 GN |
75 | |
76 | int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); | |
77 | int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); | |
78 | ||
79 | static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu) | |
80 | { | |
81 | return vcpu->arch.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE; | |
82 | } | |
ae7a2a3f MT |
83 | |
84 | int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data); | |
c5cc421b | 85 | void kvm_lapic_init(void); |
c48f1496 GN |
86 | |
87 | static inline u32 kvm_apic_get_reg(struct kvm_lapic *apic, int reg_off) | |
88 | { | |
89 | return *((u32 *) (apic->regs + reg_off)); | |
90 | } | |
91 | ||
92 | extern struct static_key kvm_no_apic_vcpu; | |
93 | ||
94 | static inline bool kvm_vcpu_has_lapic(struct kvm_vcpu *vcpu) | |
95 | { | |
96 | if (static_key_false(&kvm_no_apic_vcpu)) | |
97 | return vcpu->arch.apic; | |
98 | return true; | |
99 | } | |
100 | ||
101 | extern struct static_key_deferred apic_hw_disabled; | |
102 | ||
103 | static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic) | |
104 | { | |
105 | if (static_key_false(&apic_hw_disabled.key)) | |
106 | return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; | |
107 | return MSR_IA32_APICBASE_ENABLE; | |
108 | } | |
109 | ||
110 | extern struct static_key_deferred apic_sw_disabled; | |
111 | ||
112 | static inline int kvm_apic_sw_enabled(struct kvm_lapic *apic) | |
113 | { | |
114 | if (static_key_false(&apic_sw_disabled.key)) | |
115 | return kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED; | |
116 | return APIC_SPIV_APIC_ENABLED; | |
117 | } | |
118 | ||
119 | static inline bool kvm_apic_present(struct kvm_vcpu *vcpu) | |
120 | { | |
121 | return kvm_vcpu_has_lapic(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic); | |
122 | } | |
123 | ||
124 | static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu) | |
125 | { | |
126 | return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic); | |
127 | } | |
128 | ||
8d14695f YZ |
129 | static inline int apic_x2apic_mode(struct kvm_lapic *apic) |
130 | { | |
131 | return apic->vcpu->arch.apic_base & X2APIC_ENABLE; | |
132 | } | |
133 | ||
82470196 | 134 | #endif |