projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'drm-misc-next-2017-01-30' of git://anongit.freedesktop.org/git/drm-misc...
[linux-block.git] / arch / x86 / kvm / lapic.h
CommitLineData
82470196
ZX		 1#ifndef __KVM_X86_LAPIC_H
2#define __KVM_X86_LAPIC_H
3
af669ac6 4#include <kvm/iodev.h>
82470196
ZX		 5
6#include <linux/kvm_host.h>
7
66450a21
JK		 8#define KVM_APIC_INIT 0
9#define KVM_APIC_SIPI 1
1e6e2755 10#define KVM_APIC_LVT_NUM 6
66450a21 11
18f40c53
SS		 12#define KVM_APIC_SHORT_MASK 0xc0000
13#define KVM_APIC_DEST_MASK 0x800
14
e9d90d47
AK		 15struct kvm_timer {
16 struct hrtimer timer;
17 s64 period; /* unit: ns */
8003c9ae 18 ktime_t target_expiration;
a323b409 19 u32 timer_mode;
e9d90d47
AK		 20 u32 timer_mode_mask;
21 u64 tscdeadline;
d0659d94 22 u64 expired_tscdeadline;
e9d90d47 23 atomic_t pending; /* accumulated triggered timers */
ce7a058a 24 bool hv_timer_in_use;
e9d90d47
AK		 25};
26
82470196
ZX		 27struct kvm_lapic {
28 unsigned long base_address;
29 struct kvm_io_device dev;
d3c7b77d
MT		 30 struct kvm_timer lapic_timer;
31 u32 divide_count;
82470196 32 struct kvm_vcpu *vcpu;
e462755c 33 bool sw_enabled;
33e4c686 34 bool irr_pending;
59fd1323 35 bool lvt0_in_nmi_mode;
8680b94b
MT		 36 /* Number of bits set in ISR. */
37 s16 isr_count;
38 /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
39 int highest_isr_cache;
5eadf916
MT		 40 /**
41 * APIC register page. The layout matches the register layout seen by
42 * the guest 1:1, because it is accessed by the vmx microcode.
43 * Note: Only one register, the TPR, is used by the microcode.
44 */
82470196 45 void *regs;
b93463aa 46 gpa_t vapic_addr;
fda4e2e8 47 struct gfn_to_hva_cache vapic_cache;
66450a21
JK		 48 unsigned long pending_events;
49 unsigned int sipi_vector;
82470196 50};
9e4aabe2
JR		 51
52struct dest_map;
53
82470196
ZX		 54int kvm_create_lapic(struct kvm_vcpu *vcpu);
55void kvm_free_lapic(struct kvm_vcpu *vcpu);
56
57int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
58int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
59int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
66450a21 60void kvm_apic_accept_events(struct kvm_vcpu *vcpu);
d28bc9dd 61void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
82470196
ZX		 62u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
63void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
58fbbf26 64void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
82470196 65void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
8b2cf73c 66u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
fc61b800 67void kvm_apic_set_version(struct kvm_vcpu *vcpu);
1e6e2755
SS		 68int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val);
69int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
70 void *data);
71bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
72 int short_hand, unsigned int dest, int dest_mode);
82470196 73
705699a1 74void __kvm_apic_update_irr(u32 *pir, void *regs);
a20ed54d 75void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir);
b4f2225c 76int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
9e4aabe2 77 struct dest_map *dest_map);
89342082 78int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
82470196 79
1e08ec4a 80bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
9e4aabe2 81 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map);
1e08ec4a 82
82470196 83u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
58cb628d 84int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
a92e2543
RK		 85int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
86int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
82470196 87int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
82470196 88
498f8162 89u64 kvm_get_lapic_target_expiration_tsc(struct kvm_vcpu *vcpu);
a3e06bbe
LJ		 90u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
91void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
92
83d4c286 93void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
c7c9c56c 94void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
83d4c286 95
fda4e2e8 96int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
b93463aa
AK		 97void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
98void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
99
0105d1a5
GN		 100int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
101int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
10388a07
GN		 102
103int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
104int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
105
106static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
107{
e83d5887 108 return vcpu->arch.hyperv.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE;
10388a07 109}
ae7a2a3f
MT		 110
111int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data);
c5cc421b 112void kvm_lapic_init(void);
cef84c30 113void kvm_lapic_exit(void);
c48f1496 114
1e6e2755
SS		 115#define VEC_POS(v) ((v) & (32 - 1))
116#define REG_POS(v) (((v) >> 5) << 4)
117
118static inline void kvm_lapic_set_vector(int vec, void *bitmap)
119{
120 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
121}
122
123static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
124{
125 kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
126 /*
127 * irr_pending must be true if any interrupt is pending; set it after
128 * APIC_IRR to avoid race with apic_clear_irr
129 */
130 apic->irr_pending = true;
131}
132
dfb95954 133static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
c48f1496 134{
dfb95954 135 return *((u32 *) (apic->regs + reg_off));
c48f1496
GN		 136}
137
1e6e2755
SS		 138static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
139{
140 *((u32 *) (apic->regs + reg_off)) = val;
141}
142
c48f1496
GN		 143extern struct static_key kvm_no_apic_vcpu;
144
bce87cce 145static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
c48f1496
GN		 146{
147 if (static_key_false(&kvm_no_apic_vcpu))
148 return vcpu->arch.apic;
149 return true;
150}
151
152extern struct static_key_deferred apic_hw_disabled;
153
154static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic)
155{
156 if (static_key_false(&apic_hw_disabled.key))
157 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
158 return MSR_IA32_APICBASE_ENABLE;
159}
160
161extern struct static_key_deferred apic_sw_disabled;
162
f30ebc31 163static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
c48f1496
GN		 164{
165 if (static_key_false(&apic_sw_disabled.key))
f30ebc31
RK		 166 return apic->sw_enabled;
167 return true;
c48f1496
GN		 168}
169
170static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
171{
bce87cce 172 return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
c48f1496
GN		 173}
174
175static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
176{
177 return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
178}
179
8d14695f
YZ		 180static inline int apic_x2apic_mode(struct kvm_lapic *apic)
181{
182 return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
183}
184
d62caabb 185static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
c7c9c56c 186{
d62caabb 187 return vcpu->arch.apic && vcpu->arch.apicv_active;
c7c9c56c
YZ		 188}
189
66450a21
JK		 190static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu)
191{
bce87cce 192 return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
66450a21
JK		 193}
194
d1ebdbf9
JS		 195static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq)
196{
197 return (irq->delivery_mode == APIC_DM_LOWEST ||
198 irq->msi_redir_hint);
199}
200
f077825a
PB		 201static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
202{
bce87cce 203 return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
f077825a
PB		 204}
205
0ca52e7b 206static inline u32 kvm_apic_id(struct kvm_lapic *apic)
5c919412 207{
a92e2543
RK		 208 /* To avoid a race between apic_base and following APIC_ID update when
209 * switching to x2apic_mode, the x2apic mode returns initial x2apic id.
210 */
211 if (apic_x2apic_mode(apic))
212 return apic->vcpu->vcpu_id;
213
214 return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
5c919412
AS		 215}
216
10606919
YZ		 217bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
218
d0659d94
MT		 219void wait_lapic_expire(struct kvm_vcpu *vcpu);
220
8feb4a04
FW		 221bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
222 struct kvm_vcpu **dest_vcpu);
52004014
FW		 223int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
224 const unsigned long *bitmap, u32 bitmap_size);
ce7a058a
YJ		 225void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
226void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
227void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
228bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
82470196 229#endif
Linux 6.x block layer and io_uring tree(s)