[linux-2.6-block.git] / arch / x86 / kvm / lapic.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __KVM_X86_LAPIC_H
#define __KVM_X86_LAPIC_H

#include <kvm/iodev.h>

#include <linux/kvm_host.h>

#define KVM_APIC_INIT		0
#define KVM_APIC_SIPI		1
#define KVM_APIC_LVT_NUM	6

#define KVM_APIC_SHORT_MASK	0xc0000
#define KVM_APIC_DEST_MASK	0x800

#define APIC_BUS_CYCLE_NS       1
#define APIC_BUS_FREQUENCY      (1000000000ULL / APIC_BUS_CYCLE_NS)

enum lapic_mode {
	LAPIC_MODE_DISABLED = 0,
	LAPIC_MODE_INVALID = X2APIC_ENABLE,
	LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
	LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,
};

struct kvm_timer {
	struct hrtimer timer;
	s64 period; 				/* unit: ns */
	ktime_t target_expiration;
	u32 timer_mode;
	u32 timer_mode_mask;
	u64 tscdeadline;
	u64 expired_tscdeadline;
	u32 timer_advance_ns;
	s64 advance_expire_delta;
	atomic_t pending;			/* accumulated triggered timers */
	bool hv_timer_in_use;
	bool timer_advance_adjust_done;
};

struct kvm_lapic {
	unsigned long base_address;
	struct kvm_io_device dev;
	struct kvm_timer lapic_timer;
	u32 divide_count;
	struct kvm_vcpu *vcpu;
	bool sw_enabled;
	bool irr_pending;
	bool lvt0_in_nmi_mode;
	/* Number of bits set in ISR. */
	s16 isr_count;
	/* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
	int highest_isr_cache;
	/**
	 * APIC register page.  The layout matches the register layout seen by
	 * the guest 1:1, because it is accessed by the vmx microcode.
	 * Note: Only one register, the TPR, is used by the microcode.
	 */
	void *regs;
	gpa_t vapic_addr;
	struct gfn_to_hva_cache vapic_cache;
	unsigned long pending_events;
	unsigned int sipi_vector;
};

struct dest_map;

int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns);
void kvm_free_lapic(struct kvm_vcpu *vcpu);

int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
void kvm_apic_accept_events(struct kvm_vcpu *vcpu);
void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
void kvm_apic_set_version(struct kvm_vcpu *vcpu);
int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val);
int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
		       void *data);
bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
			   int short_hand, unsigned int dest, int dest_mode);

bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr);
bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr);
void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
		     struct dest_map *dest_map);
int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);

bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
		struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map);

u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu);
int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);

u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);

void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);

int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);

int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);

int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);

static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
{
	return vcpu->arch.hyperv.hv_vapic & HV_X64_MSR_VP_ASSIST_PAGE_ENABLE;
}

int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
void kvm_lapic_init(void);
void kvm_lapic_exit(void);

#define VEC_POS(v) ((v) & (32 - 1))
#define REG_POS(v) (((v) >> 5) << 4)

static inline void kvm_lapic_clear_vector(int vec, void *bitmap)
{
	clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
}

static inline void kvm_lapic_set_vector(int vec, void *bitmap)
{
	set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
}

static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
{
	kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
	/*
	 * irr_pending must be true if any interrupt is pending; set it after
	 * APIC_IRR to avoid race with apic_clear_irr
	 */
	apic->irr_pending = true;
}

static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
{
	return *((u32 *) (apic->regs + reg_off));
}

static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
{
	*((u32 *) (apic->regs + reg_off)) = val;
}

extern struct static_key kvm_no_apic_vcpu;

static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
{
	if (static_key_false(&kvm_no_apic_vcpu))
		return vcpu->arch.apic;
	return true;
}

extern struct static_key_deferred apic_hw_disabled;

static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic)
{
	if (static_key_false(&apic_hw_disabled.key))
		return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
	return MSR_IA32_APICBASE_ENABLE;
}

extern struct static_key_deferred apic_sw_disabled;

static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
{
	if (static_key_false(&apic_sw_disabled.key))
		return apic->sw_enabled;
	return true;
}

static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
{
	return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
}

static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
{
	return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
}

static inline int apic_x2apic_mode(struct kvm_lapic *apic)
{
	return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
}

static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
{
	return vcpu->arch.apic && vcpu->arch.apicv_active;
}

static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu)
{
	return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
}

static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq)
{
	return (irq->delivery_mode == APIC_DM_LOWEST ||
			irq->msi_redir_hint);
}

static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
{
	return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
}

bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);

void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu);

bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
			struct kvm_vcpu **dest_vcpu);
int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
			const unsigned long *bitmap, u32 bitmap_size);
void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
bool kvm_can_post_timer_interrupt(struct kvm_vcpu *vcpu);

static inline enum lapic_mode kvm_apic_mode(u64 apic_base)
{
	return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
}

#endif
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
82470196 ZX	2	#ifndef __KVM_X86_LAPIC_H
	3	#define __KVM_X86_LAPIC_H
	4
af669ac6	5	#include <kvm/iodev.h>
82470196 ZX	6
	7	#include <linux/kvm_host.h>
	8
66450a21 JK	9	#define KVM_APIC_INIT 0
66450a21 JK	10	#define KVM_APIC_SIPI 1
1e6e2755	11	#define KVM_APIC_LVT_NUM 6
66450a21	12
18f40c53 SS	13	#define KVM_APIC_SHORT_MASK 0xc0000
	14	#define KVM_APIC_DEST_MASK 0x800
	15
72c139ba LP	16	#define APIC_BUS_CYCLE_NS 1
	17	#define APIC_BUS_FREQUENCY (1000000000ULL / APIC_BUS_CYCLE_NS)
	18
58871649 JM	19	enum lapic_mode {
	20	LAPIC_MODE_DISABLED = 0,
	21	LAPIC_MODE_INVALID = X2APIC_ENABLE,
	22	LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
	23	LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE \| X2APIC_ENABLE,
	24	};
	25
e9d90d47 AK	26	struct kvm_timer {
	27	struct hrtimer timer;
	28	s64 period; /* unit: ns */
8003c9ae	29	ktime_t target_expiration;
a323b409	30	u32 timer_mode;
e9d90d47 AK	31	u32 timer_mode_mask;
e9d90d47 AK	32	u64 tscdeadline;
d0659d94	33	u64 expired_tscdeadline;
39497d76	34	u32 timer_advance_ns;
ec0671d5	35	s64 advance_expire_delta;
e9d90d47	36	atomic_t pending; /* accumulated triggered timers */
ce7a058a	37	bool hv_timer_in_use;
39497d76	38	bool timer_advance_adjust_done;
e9d90d47 AK	39	};
e9d90d47 AK	40
82470196 ZX	41	struct kvm_lapic {
	42	unsigned long base_address;
	43	struct kvm_io_device dev;
d3c7b77d MT	44	struct kvm_timer lapic_timer;
d3c7b77d MT	45	u32 divide_count;
82470196	46	struct kvm_vcpu *vcpu;
e462755c	47	bool sw_enabled;
33e4c686	48	bool irr_pending;
59fd1323	49	bool lvt0_in_nmi_mode;
8680b94b MT	50	/* Number of bits set in ISR. */
	51	s16 isr_count;
	52	/* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
	53	int highest_isr_cache;
5eadf916 MT	54	/**
	55	* APIC register page. The layout matches the register layout seen by
	56	* the guest 1:1, because it is accessed by the vmx microcode.
	57	* Note: Only one register, the TPR, is used by the microcode.
	58	*/
82470196	59	void *regs;
b93463aa	60	gpa_t vapic_addr;
fda4e2e8	61	struct gfn_to_hva_cache vapic_cache;
66450a21 JK	62	unsigned long pending_events;
66450a21 JK	63	unsigned int sipi_vector;
82470196	64	};
9e4aabe2 JR	65
	66	struct dest_map;
	67
c3941d9e	68	int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns);
82470196 ZX	69	void kvm_free_lapic(struct kvm_vcpu *vcpu);
	70
	71	int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
	72	int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
	73	int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
66450a21	74	void kvm_apic_accept_events(struct kvm_vcpu *vcpu);
d28bc9dd	75	void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
82470196 ZX	76	u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
82470196 ZX	77	void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
58fbbf26	78	void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
82470196	79	void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
8b2cf73c	80	u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
fc61b800	81	void kvm_apic_set_version(struct kvm_vcpu *vcpu);
1e6e2755 SS	82	int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val);
	83	int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
	84	void *data);
	85	bool kvm_apic_match_dest(struct kvm_vcpu vcpu, struct kvm_lapic source,
	86	int short_hand, unsigned int dest, int dest_mode);
82470196	87
e7387b0e LA	88	bool __kvm_apic_update_irr(u32 pir, void regs, int *max_irr);
e7387b0e LA	89	bool kvm_apic_update_irr(struct kvm_vcpu vcpu, u32 pir, int *max_irr);
eb90f341	90	void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
b4f2225c	91	int kvm_apic_set_irq(struct kvm_vcpu vcpu, struct kvm_lapic_irq irq,
9e4aabe2	92	struct dest_map *dest_map);
89342082	93	int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
82470196	94
1e08ec4a	95	bool kvm_irq_delivery_to_apic_fast(struct kvm kvm, struct kvm_lapic src,
9e4aabe2	96	struct kvm_lapic_irq irq, int r, struct dest_map *dest_map);
1e08ec4a	97
82470196	98	u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
58cb628d	99	int kvm_set_apic_base(struct kvm_vcpu vcpu, struct msr_data msr_info);
a92e2543 RK	100	int kvm_apic_get_state(struct kvm_vcpu vcpu, struct kvm_lapic_state s);
a92e2543 RK	101	int kvm_apic_set_state(struct kvm_vcpu vcpu, struct kvm_lapic_state s);
58871649	102	enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu);
82470196	103	int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
82470196	104
a3e06bbe LJ	105	u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
	106	void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
	107
83d4c286	108	void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
c7c9c56c	109	void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
83d4c286	110
fda4e2e8	111	int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
b93463aa AK	112	void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
	113	void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
	114
0105d1a5 GN	115	int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
0105d1a5 GN	116	int kvm_x2apic_msr_read(struct kvm_vcpu vcpu, u32 msr, u64 data);
10388a07 GN	117
	118	int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
	119	int kvm_hv_vapic_msr_read(struct kvm_vcpu vcpu, u32 msr, u64 data);
	120
	121	static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
	122	{
d4abc577	123	return vcpu->arch.hyperv.hv_vapic & HV_X64_MSR_VP_ASSIST_PAGE_ENABLE;
10388a07	124	}
ae7a2a3f	125
72bbf935	126	int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
c5cc421b	127	void kvm_lapic_init(void);
cef84c30	128	void kvm_lapic_exit(void);
c48f1496	129
1e6e2755 SS	130	#define VEC_POS(v) ((v) & (32 - 1))
	131	#define REG_POS(v) (((v) >> 5) << 4)
	132
ee171d2f WY	133	static inline void kvm_lapic_clear_vector(int vec, void *bitmap)
	134	{
	135	clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
	136	}
	137
1e6e2755 SS	138	static inline void kvm_lapic_set_vector(int vec, void *bitmap)
	139	{
	140	set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
	141	}
	142
	143	static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
	144	{
	145	kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
	146	/*
	147	* irr_pending must be true if any interrupt is pending; set it after
	148	* APIC_IRR to avoid race with apic_clear_irr
	149	*/
	150	apic->irr_pending = true;
	151	}
	152
dfb95954	153	static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
c48f1496	154	{
dfb95954	155	return ((u32 ) (apic->regs + reg_off));
c48f1496 GN	156	}
c48f1496 GN	157
1e6e2755 SS	158	static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
	159	{
	160	((u32 ) (apic->regs + reg_off)) = val;
	161	}
	162
c48f1496 GN	163	extern struct static_key kvm_no_apic_vcpu;
c48f1496 GN	164
bce87cce	165	static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
c48f1496 GN	166	{
	167	if (static_key_false(&kvm_no_apic_vcpu))
	168	return vcpu->arch.apic;
	169	return true;
	170	}
	171
	172	extern struct static_key_deferred apic_hw_disabled;
	173
	174	static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic)
	175	{
	176	if (static_key_false(&apic_hw_disabled.key))
	177	return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
	178	return MSR_IA32_APICBASE_ENABLE;
	179	}
	180
	181	extern struct static_key_deferred apic_sw_disabled;
	182
f30ebc31	183	static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
c48f1496 GN	184	{
c48f1496 GN	185	if (static_key_false(&apic_sw_disabled.key))
f30ebc31 RK	186	return apic->sw_enabled;
f30ebc31 RK	187	return true;
c48f1496 GN	188	}
	189
	190	static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
	191	{
bce87cce	192	return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
c48f1496 GN	193	}
	194
	195	static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
	196	{
	197	return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
	198	}
	199
8d14695f YZ	200	static inline int apic_x2apic_mode(struct kvm_lapic *apic)
	201	{
	202	return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
	203	}
	204
d62caabb	205	static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
c7c9c56c	206	{
d62caabb	207	return vcpu->arch.apic && vcpu->arch.apicv_active;
c7c9c56c YZ	208	}
c7c9c56c YZ	209
66450a21 JK	210	static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu)
66450a21 JK	211	{
bce87cce	212	return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
66450a21 JK	213	}
66450a21 JK	214
d1ebdbf9 JS	215	static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq)
	216	{
	217	return (irq->delivery_mode == APIC_DM_LOWEST \|\|
	218	irq->msi_redir_hint);
	219	}
	220
f077825a PB	221	static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
f077825a PB	222	{
bce87cce	223	return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
f077825a PB	224	}
f077825a PB	225
10606919 YZ	226	bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
10606919 YZ	227
b6c4bc65	228	void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu);
d0659d94	229
8feb4a04 FW	230	bool kvm_intr_is_single_vcpu_fast(struct kvm kvm, struct kvm_lapic_irq irq,
8feb4a04 FW	231	struct kvm_vcpu **dest_vcpu);
52004014 FW	232	int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
52004014 FW	233	const unsigned long *bitmap, u32 bitmap_size);
ce7a058a YJ	234	void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
	235	void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
	236	void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
	237	bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
a749e247	238	void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
0c5f81da	239	bool kvm_can_post_timer_interrupt(struct kvm_vcpu *vcpu);
58871649 JM	240
	241	static inline enum lapic_mode kvm_apic_mode(u64 apic_base)
	242	{
	243	return apic_base & (MSR_IA32_APICBASE_ENABLE \| X2APIC_ENABLE);
	244	}
	245
82470196	246	#endif