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Merge tag 'amlogic-dt-2' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman...
[linux-2.6-block.git] / arch / x86 / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
9611c187 8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
97222cc8
ED		 9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
edf88417 21#include <linux/kvm_host.h>
97222cc8
ED		 22#include <linux/kvm.h>
23#include <linux/mm.h>
24#include <linux/highmem.h>
25#include <linux/smp.h>
26#include <linux/hrtimer.h>
27#include <linux/io.h>
1767e931 28#include <linux/export.h>
6f6d6a1a 29#include <linux/math64.h>
5a0e3ad6 30#include <linux/slab.h>
97222cc8
ED		 31#include <asm/processor.h>
32#include <asm/msr.h>
33#include <asm/page.h>
34#include <asm/current.h>
35#include <asm/apicdef.h>
d0659d94 36#include <asm/delay.h>
60063497 37#include <linux/atomic.h>
c5cc421b 38#include <linux/jump_label.h>
5fdbf976 39#include "kvm_cache_regs.h"
97222cc8 40#include "irq.h"
229456fc 41#include "trace.h"
fc61b800 42#include "x86.h"
00b27a3e 43#include "cpuid.h"
5c919412 44#include "hyperv.h"
97222cc8 45
b682b814
MT		 46#ifndef CONFIG_X86_64
47#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
48#else
49#define mod_64(x, y) ((x) % (y))
50#endif
51
97222cc8
ED		 52#define PRId64 "d"
53#define PRIx64 "llx"
54#define PRIu64 "u"
55#define PRIo64 "o"
56
97222cc8
ED		 57/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
58#define apic_debug(fmt, arg...)
59
97222cc8 60/* 14 is the version for Xeon and Pentium 8.4.8*/
1e6e2755 61#define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
97222cc8
ED		 62#define LAPIC_MMIO_LENGTH (1 << 12)
63/* followed define is not in apicdef.h */
64#define APIC_SHORT_MASK 0xc0000
65#define APIC_DEST_NOSHORT 0x0
66#define APIC_DEST_MASK 0x800
67#define MAX_APIC_VECTOR 256
ecba9a52 68#define APIC_VECTORS_PER_REG 32
97222cc8 69
394457a9
NA		 70#define APIC_BROADCAST 0xFF
71#define X2APIC_BROADCAST 0xFFFFFFFFul
72
a0c9a822
MT		 73static inline int apic_test_vector(int vec, void *bitmap)
74{
75 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
76}
77
10606919
YZ		 78bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
79{
80 struct kvm_lapic *apic = vcpu->arch.apic;
81
82 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
83 apic_test_vector(vector, apic->regs + APIC_IRR);
84}
85
97222cc8
ED		 86static inline void apic_clear_vector(int vec, void *bitmap)
87{
88 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
89}
90
8680b94b
MT		 91static inline int __apic_test_and_set_vector(int vec, void *bitmap)
92{
93 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
94}
95
96static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
97{
98 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
99}
100
c5cc421b 101struct static_key_deferred apic_hw_disabled __read_mostly;
f8c1ea10
GN		 102struct static_key_deferred apic_sw_disabled __read_mostly;
103
97222cc8
ED		 104static inline int apic_enabled(struct kvm_lapic *apic)
105{
c48f1496 106 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
54e9818f
GN		 107}
108
97222cc8
ED		 109#define LVT_MASK \
110 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
111
112#define LINT_MASK \
113 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
114 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
115
6e500439
RK		 116static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
117{
118 return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
119}
120
121static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
122{
123 return apic->vcpu->vcpu_id;
124}
125
e45115b6
RK		 126static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
127 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
128 switch (map->mode) {
129 case KVM_APIC_MODE_X2APIC: {
130 u32 offset = (dest_id >> 16) * 16;
0ca52e7b 131 u32 max_apic_id = map->max_apic_id;
e45115b6
RK		 132
133 if (offset <= max_apic_id) {
134 u8 cluster_size = min(max_apic_id - offset + 1, 16U);
135
136 *cluster = &map->phys_map[offset];
137 *mask = dest_id & (0xffff >> (16 - cluster_size));
138 } else {
139 *mask = 0;
140 }
3b5a5ffa 141
e45115b6
RK		 142 return true;
143 }
144 case KVM_APIC_MODE_XAPIC_FLAT:
145 *cluster = map->xapic_flat_map;
146 *mask = dest_id & 0xff;
147 return true;
148 case KVM_APIC_MODE_XAPIC_CLUSTER:
444fdad8 149 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
e45115b6
RK		 150 *mask = dest_id & 0xf;
151 return true;
152 default:
153 /* Not optimized. */
154 return false;
155 }
3548a259
RK		 156}
157
af1bae54 158static void kvm_apic_map_free(struct rcu_head *rcu)
3b5a5ffa 159{
af1bae54 160 struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
3b5a5ffa 161
af1bae54 162 kvfree(map);
3b5a5ffa
RK		 163}
164
1e08ec4a
GN		 165static void recalculate_apic_map(struct kvm *kvm)
166{
167 struct kvm_apic_map *new, *old = NULL;
168 struct kvm_vcpu *vcpu;
169 int i;
6e500439 170 u32 max_id = 255; /* enough space for any xAPIC ID */
1e08ec4a
GN		 171
172 mutex_lock(&kvm->arch.apic_map_lock);
173
0ca52e7b
RK		 174 kvm_for_each_vcpu(i, vcpu, kvm)
175 if (kvm_apic_present(vcpu))
6e500439 176 max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
0ca52e7b 177
a7c3e901
MH		 178 new = kvzalloc(sizeof(struct kvm_apic_map) +
179 sizeof(struct kvm_lapic *) * ((u64)max_id + 1), GFP_KERNEL);
0ca52e7b 180
1e08ec4a
GN		 181 if (!new)
182 goto out;
183
0ca52e7b
RK		 184 new->max_apic_id = max_id;
185
173beedc
NA		 186 kvm_for_each_vcpu(i, vcpu, kvm) {
187 struct kvm_lapic *apic = vcpu->arch.apic;
e45115b6
RK		 188 struct kvm_lapic **cluster;
189 u16 mask;
5bd5db38
RK		 190 u32 ldr;
191 u8 xapic_id;
192 u32 x2apic_id;
1e08ec4a 193
df04d1d1
RK		 194 if (!kvm_apic_present(vcpu))
195 continue;
196
5bd5db38
RK		 197 xapic_id = kvm_xapic_id(apic);
198 x2apic_id = kvm_x2apic_id(apic);
199
200 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
201 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) &&
202 x2apic_id <= new->max_apic_id)
203 new->phys_map[x2apic_id] = apic;
204 /*
205 * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
206 * prevent them from masking VCPUs with APIC ID <= 0xff.
207 */
208 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])
209 new->phys_map[xapic_id] = apic;
3548a259 210
6e500439
RK		 211 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
212
3b5a5ffa
RK		 213 if (apic_x2apic_mode(apic)) {
214 new->mode |= KVM_APIC_MODE_X2APIC;
215 } else if (ldr) {
216 ldr = GET_APIC_LOGICAL_ID(ldr);
dfb95954 217 if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
3b5a5ffa
RK		 218 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
219 else
220 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
221 }
222
e45115b6 223 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
3548a259
RK		 224 continue;
225
e45115b6
RK		 226 if (mask)
227 cluster[ffs(mask) - 1] = apic;
1e08ec4a
GN		 228 }
229out:
230 old = rcu_dereference_protected(kvm->arch.apic_map,
231 lockdep_is_held(&kvm->arch.apic_map_lock));
232 rcu_assign_pointer(kvm->arch.apic_map, new);
233 mutex_unlock(&kvm->arch.apic_map_lock);
234
235 if (old)
af1bae54 236 call_rcu(&old->rcu, kvm_apic_map_free);
c7c9c56c 237
b053b2ae 238 kvm_make_scan_ioapic_request(kvm);
1e08ec4a
GN		 239}
240
1e1b6c26
NA		 241static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
242{
e462755c 243 bool enabled = val & APIC_SPIV_APIC_ENABLED;
1e1b6c26 244
1e6e2755 245 kvm_lapic_set_reg(apic, APIC_SPIV, val);
e462755c
RK		 246
247 if (enabled != apic->sw_enabled) {
248 apic->sw_enabled = enabled;
249 if (enabled) {
1e1b6c26
NA		 250 static_key_slow_dec_deferred(&apic_sw_disabled);
251 recalculate_apic_map(apic->vcpu->kvm);
252 } else
253 static_key_slow_inc(&apic_sw_disabled.key);
254 }
255}
256
a92e2543 257static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
1e08ec4a 258{
1e6e2755 259 kvm_lapic_set_reg(apic, APIC_ID, id << 24);
1e08ec4a
GN		 260 recalculate_apic_map(apic->vcpu->kvm);
261}
262
263static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
264{
1e6e2755 265 kvm_lapic_set_reg(apic, APIC_LDR, id);
1e08ec4a
GN		 266 recalculate_apic_map(apic->vcpu->kvm);
267}
268
e872fa94
DDAG		 269static inline u32 kvm_apic_calc_x2apic_ldr(u32 id)
270{
271 return ((id >> 4) << 16) | (1 << (id & 0xf));
272}
273
a92e2543 274static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
257b9a5f 275{
e872fa94 276 u32 ldr = kvm_apic_calc_x2apic_ldr(id);
257b9a5f 277
6e500439
RK		 278 WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
279
a92e2543 280 kvm_lapic_set_reg(apic, APIC_ID, id);
1e6e2755 281 kvm_lapic_set_reg(apic, APIC_LDR, ldr);
257b9a5f
RK		 282 recalculate_apic_map(apic->vcpu->kvm);
283}
284
97222cc8
ED		 285static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
286{
dfb95954 287 return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
97222cc8
ED		 288}
289
290static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
291{
dfb95954 292 return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
97222cc8
ED		 293}
294
a3e06bbe
LJ		 295static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
296{
f30ebc31 297 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
a3e06bbe
LJ		 298}
299
97222cc8
ED		 300static inline int apic_lvtt_period(struct kvm_lapic *apic)
301{
f30ebc31 302 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
a3e06bbe
LJ		 303}
304
305static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
306{
f30ebc31 307 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
97222cc8
ED		 308}
309
cc6e462c
JK		 310static inline int apic_lvt_nmi_mode(u32 lvt_val)
311{
312 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
313}
314
fc61b800
GN		 315void kvm_apic_set_version(struct kvm_vcpu *vcpu)
316{
317 struct kvm_lapic *apic = vcpu->arch.apic;
318 struct kvm_cpuid_entry2 *feat;
319 u32 v = APIC_VERSION;
320
bce87cce 321 if (!lapic_in_kernel(vcpu))
fc61b800
GN		 322 return;
323
0bcc3fb9
VK		 324 /*
325 * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation)
326 * which doesn't have EOI register; Some buggy OSes (e.g. Windows with
327 * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC
328 * version first and level-triggered interrupts never get EOIed in
329 * IOAPIC.
330 */
fc61b800 331 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
0bcc3fb9
VK		 332 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))) &&
333 !ioapic_in_kernel(vcpu->kvm))
fc61b800 334 v |= APIC_LVR_DIRECTED_EOI;
1e6e2755 335 kvm_lapic_set_reg(apic, APIC_LVR, v);
fc61b800
GN		 336}
337
1e6e2755 338static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
a3e06bbe 339 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
97222cc8
ED		 340 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
341 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
342 LINT_MASK, LINT_MASK, /* LVT0-1 */
343 LVT_MASK /* LVTERR */
344};
345
346static int find_highest_vector(void *bitmap)
347{
ecba9a52
TY		 348 int vec;
349 u32 *reg;
97222cc8 350
ecba9a52
TY		 351 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
352 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
353 reg = bitmap + REG_POS(vec);
354 if (*reg)
810e6def 355 return __fls(*reg) + vec;
ecba9a52 356 }
97222cc8 357
ecba9a52 358 return -1;
97222cc8
ED		 359}
360
8680b94b
MT		 361static u8 count_vectors(void *bitmap)
362{
ecba9a52
TY		 363 int vec;
364 u32 *reg;
8680b94b 365 u8 count = 0;
ecba9a52
TY		 366
367 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
368 reg = bitmap + REG_POS(vec);
369 count += hweight32(*reg);
370 }
371
8680b94b
MT		 372 return count;
373}
374
e7387b0e 375bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr)
a20ed54d 376{
810e6def 377 u32 i, vec;
e7387b0e
LA		 378 u32 pir_val, irr_val, prev_irr_val;
379 int max_updated_irr;
380
381 max_updated_irr = -1;
382 *max_irr = -1;
a20ed54d 383
810e6def 384 for (i = vec = 0; i <= 7; i++, vec += 32) {
ad361091 385 pir_val = READ_ONCE(pir[i]);
810e6def 386 irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10));
ad361091 387 if (pir_val) {
e7387b0e 388 prev_irr_val = irr_val;
810e6def
PB		 389 irr_val |= xchg(&pir[i], 0);
390 *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val;
e7387b0e
LA		 391 if (prev_irr_val != irr_val) {
392 max_updated_irr =
393 __fls(irr_val ^ prev_irr_val) + vec;
394 }
ad361091 395 }
810e6def 396 if (irr_val)
e7387b0e 397 *max_irr = __fls(irr_val) + vec;
a20ed54d 398 }
810e6def 399
e7387b0e
LA		 400 return ((max_updated_irr != -1) &&
401 (max_updated_irr == *max_irr));
a20ed54d 402}
705699a1
WV		 403EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
404
e7387b0e 405bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr)
705699a1
WV		 406{
407 struct kvm_lapic *apic = vcpu->arch.apic;
408
e7387b0e 409 return __kvm_apic_update_irr(pir, apic->regs, max_irr);
705699a1 410}
a20ed54d
YZ		 411EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
412
33e4c686 413static inline int apic_search_irr(struct kvm_lapic *apic)
97222cc8 414{
33e4c686 415 return find_highest_vector(apic->regs + APIC_IRR);
97222cc8
ED		 416}
417
418static inline int apic_find_highest_irr(struct kvm_lapic *apic)
419{
420 int result;
421
c7c9c56c
YZ		 422 /*
423 * Note that irr_pending is just a hint. It will be always
424 * true with virtual interrupt delivery enabled.
425 */
33e4c686
GN		 426 if (!apic->irr_pending)
427 return -1;
428
429 result = apic_search_irr(apic);
97222cc8
ED		 430 ASSERT(result == -1 || result >= 16);
431
432 return result;
433}
434
33e4c686
GN		 435static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
436{
56cc2406
WL		 437 struct kvm_vcpu *vcpu;
438
439 vcpu = apic->vcpu;
440
d62caabb 441 if (unlikely(vcpu->arch.apicv_active)) {
b95234c8 442 /* need to update RVI */
f210f757 443 apic_clear_vector(vec, apic->regs + APIC_IRR);
b95234c8
PB		 444 kvm_x86_ops->hwapic_irr_update(vcpu,
445 apic_find_highest_irr(apic));
f210f757
NA		 446 } else {
447 apic->irr_pending = false;
448 apic_clear_vector(vec, apic->regs + APIC_IRR);
449 if (apic_search_irr(apic) != -1)
450 apic->irr_pending = true;
56cc2406 451 }
33e4c686
GN		 452}
453
8680b94b
MT		 454static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
455{
56cc2406
WL		 456 struct kvm_vcpu *vcpu;
457
458 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
459 return;
460
461 vcpu = apic->vcpu;
fc57ac2c 462
8680b94b 463 /*
56cc2406
WL		 464 * With APIC virtualization enabled, all caching is disabled
465 * because the processor can modify ISR under the hood. Instead
466 * just set SVI.
8680b94b 467 */
d62caabb 468 if (unlikely(vcpu->arch.apicv_active))
67c9dddc 469 kvm_x86_ops->hwapic_isr_update(vcpu, vec);
56cc2406
WL		 470 else {
471 ++apic->isr_count;
472 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
473 /*
474 * ISR (in service register) bit is set when injecting an interrupt.
475 * The highest vector is injected. Thus the latest bit set matches
476 * the highest bit in ISR.
477 */
478 apic->highest_isr_cache = vec;
479 }
8680b94b
MT		 480}
481
fc57ac2c
PB		 482static inline int apic_find_highest_isr(struct kvm_lapic *apic)
483{
484 int result;
485
486 /*
487 * Note that isr_count is always 1, and highest_isr_cache
488 * is always -1, with APIC virtualization enabled.
489 */
490 if (!apic->isr_count)
491 return -1;
492 if (likely(apic->highest_isr_cache != -1))
493 return apic->highest_isr_cache;
494
495 result = find_highest_vector(apic->regs + APIC_ISR);
496 ASSERT(result == -1 || result >= 16);
497
498 return result;
499}
500
8680b94b
MT		 501static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
502{
fc57ac2c
PB		 503 struct kvm_vcpu *vcpu;
504 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
505 return;
506
507 vcpu = apic->vcpu;
508
509 /*
510 * We do get here for APIC virtualization enabled if the guest
511 * uses the Hyper-V APIC enlightenment. In this case we may need
512 * to trigger a new interrupt delivery by writing the SVI field;
513 * on the other hand isr_count and highest_isr_cache are unused
514 * and must be left alone.
515 */
d62caabb 516 if (unlikely(vcpu->arch.apicv_active))
67c9dddc 517 kvm_x86_ops->hwapic_isr_update(vcpu,
fc57ac2c
PB		 518 apic_find_highest_isr(apic));
519 else {
8680b94b 520 --apic->isr_count;
fc57ac2c
PB		 521 BUG_ON(apic->isr_count < 0);
522 apic->highest_isr_cache = -1;
523 }
8680b94b
MT		 524}
525
6e5d865c
YS		 526int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
527{
33e4c686
GN		 528 /* This may race with setting of irr in __apic_accept_irq() and
529 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
530 * will cause vmexit immediately and the value will be recalculated
531 * on the next vmentry.
532 */
f8543d6a 533 return apic_find_highest_irr(vcpu->arch.apic);
6e5d865c 534}
76dfafd5 535EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
6e5d865c 536
6da7e3f6 537static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c 538 int vector, int level, int trig_mode,
9e4aabe2 539 struct dest_map *dest_map);
6da7e3f6 540
b4f2225c 541int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
9e4aabe2 542 struct dest_map *dest_map)
97222cc8 543{
ad312c7c 544 struct kvm_lapic *apic = vcpu->arch.apic;
8be5453f 545
58c2dde1 546 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
b4f2225c 547 irq->level, irq->trig_mode, dest_map);
97222cc8
ED		 548}
549
ae7a2a3f
MT		 550static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
551{
4e335d9e
PB		 552
553 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
554 sizeof(val));
ae7a2a3f
MT		 555}
556
557static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
558{
4e335d9e
PB		 559
560 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
561 sizeof(*val));
ae7a2a3f
MT		 562}
563
564static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
565{
566 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
567}
568
569static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
570{
571 u8 val;
572 if (pv_eoi_get_user(vcpu, &val) < 0)
573 apic_debug("Can't read EOI MSR value: 0x%llx\n",
96893977 574 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 575 return val & 0x1;
576}
577
578static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
579{
580 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
581 apic_debug("Can't set EOI MSR value: 0x%llx\n",
96893977 582 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 583 return;
584 }
585 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
586}
587
588static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
589{
590 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
591 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
96893977 592 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 593 return;
594 }
595 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
596}
597
b3c045d3
PB		 598static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)
599{
3d92789f 600 int highest_irr;
fa59cc00 601 if (apic->vcpu->arch.apicv_active)
76dfafd5
PB		 602 highest_irr = kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
603 else
604 highest_irr = apic_find_highest_irr(apic);
b3c045d3
PB		 605 if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr)
606 return -1;
607 return highest_irr;
608}
609
610static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr)
97222cc8 611{
3842d135 612 u32 tpr, isrv, ppr, old_ppr;
97222cc8
ED		 613 int isr;
614
dfb95954
SS		 615 old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
616 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
97222cc8
ED		 617 isr = apic_find_highest_isr(apic);
618 isrv = (isr != -1) ? isr : 0;
619
620 if ((tpr & 0xf0) >= (isrv & 0xf0))
621 ppr = tpr & 0xff;
622 else
623 ppr = isrv & 0xf0;
624
625 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
626 apic, ppr, isr, isrv);
627
b3c045d3
PB		 628 *new_ppr = ppr;
629 if (old_ppr != ppr)
1e6e2755 630 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
b3c045d3
PB		 631
632 return ppr < old_ppr;
633}
634
635static void apic_update_ppr(struct kvm_lapic *apic)
636{
637 u32 ppr;
638
26fbbee5
PB		 639 if (__apic_update_ppr(apic, &ppr) &&
640 apic_has_interrupt_for_ppr(apic, ppr) != -1)
b3c045d3 641 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
97222cc8
ED		 642}
643
eb90f341
PB		 644void kvm_apic_update_ppr(struct kvm_vcpu *vcpu)
645{
646 apic_update_ppr(vcpu->arch.apic);
647}
648EXPORT_SYMBOL_GPL(kvm_apic_update_ppr);
649
97222cc8
ED		 650static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
651{
1e6e2755 652 kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
97222cc8
ED		 653 apic_update_ppr(apic);
654}
655
03d2249e 656static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
394457a9 657{
b4535b58
RK		 658 return mda == (apic_x2apic_mode(apic) ?
659 X2APIC_BROADCAST : APIC_BROADCAST);
394457a9
NA		 660}
661
03d2249e 662static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8 663{
03d2249e
RK		 664 if (kvm_apic_broadcast(apic, mda))
665 return true;
666
667 if (apic_x2apic_mode(apic))
6e500439 668 return mda == kvm_x2apic_id(apic);
03d2249e 669
5bd5db38
RK		 670 /*
671 * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
672 * it were in x2APIC mode. Hotplugged VCPUs start in xAPIC mode and
673 * this allows unique addressing of VCPUs with APIC ID over 0xff.
674 * The 0xff condition is needed because writeable xAPIC ID.
675 */
676 if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic))
677 return true;
678
b4535b58 679 return mda == kvm_xapic_id(apic);
97222cc8
ED		 680}
681
52c233a4 682static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8 683{
0105d1a5
GN		 684 u32 logical_id;
685
394457a9 686 if (kvm_apic_broadcast(apic, mda))
9368b567 687 return true;
394457a9 688
dfb95954 689 logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
97222cc8 690
9368b567 691 if (apic_x2apic_mode(apic))
8a395363
RK		 692 return ((logical_id >> 16) == (mda >> 16))
693 && (logical_id & mda & 0xffff) != 0;
97222cc8 694
9368b567 695 logical_id = GET_APIC_LOGICAL_ID(logical_id);
97222cc8 696
dfb95954 697 switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
97222cc8 698 case APIC_DFR_FLAT:
9368b567 699 return (logical_id & mda) != 0;
97222cc8 700 case APIC_DFR_CLUSTER:
9368b567
RK		 701 return ((logical_id >> 4) == (mda >> 4))
702 && (logical_id & mda & 0xf) != 0;
97222cc8 703 default:
7712de87 704 apic_debug("Bad DFR vcpu %d: %08x\n",
dfb95954 705 apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR));
9368b567 706 return false;
97222cc8 707 }
97222cc8
ED		 708}
709
c519265f
RK		 710/* The KVM local APIC implementation has two quirks:
711 *
b4535b58
RK		 712 * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
713 * in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
714 * KVM doesn't do that aliasing.
c519265f
RK		 715 *
716 * - in-kernel IOAPIC messages have to be delivered directly to
717 * x2APIC, because the kernel does not support interrupt remapping.
718 * In order to support broadcast without interrupt remapping, x2APIC
719 * rewrites the destination of non-IPI messages from APIC_BROADCAST
720 * to X2APIC_BROADCAST.
721 *
722 * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API. This is
723 * important when userspace wants to use x2APIC-format MSIs, because
724 * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
03d2249e 725 */
c519265f
RK		 726static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
727 struct kvm_lapic *source, struct kvm_lapic *target)
03d2249e
RK		 728{
729 bool ipi = source != NULL;
03d2249e 730
c519265f 731 if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
b4535b58 732 !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target))
03d2249e
RK		 733 return X2APIC_BROADCAST;
734
b4535b58 735 return dest_id;
03d2249e
RK		 736}
737
52c233a4 738bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
394457a9 739 int short_hand, unsigned int dest, int dest_mode)
97222cc8 740{
ad312c7c 741 struct kvm_lapic *target = vcpu->arch.apic;
c519265f 742 u32 mda = kvm_apic_mda(vcpu, dest, source, target);
97222cc8
ED		 743
744 apic_debug("target %p, source %p, dest 0x%x, "
343f94fe 745 "dest_mode 0x%x, short_hand 0x%x\n",
97222cc8
ED		 746 target, source, dest, dest_mode, short_hand);
747
bd371396 748 ASSERT(target);
97222cc8
ED		 749 switch (short_hand) {
750 case APIC_DEST_NOSHORT:
3697f302 751 if (dest_mode == APIC_DEST_PHYSICAL)
03d2249e 752 return kvm_apic_match_physical_addr(target, mda);
343f94fe 753 else
03d2249e 754 return kvm_apic_match_logical_addr(target, mda);
97222cc8 755 case APIC_DEST_SELF:
9368b567 756 return target == source;
97222cc8 757 case APIC_DEST_ALLINC:
9368b567 758 return true;
97222cc8 759 case APIC_DEST_ALLBUT:
9368b567 760 return target != source;
97222cc8 761 default:
7712de87
JK		 762 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
763 short_hand);
9368b567 764 return false;
97222cc8 765 }
97222cc8 766}
1e6e2755 767EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
97222cc8 768
52004014
FW		 769int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
770 const unsigned long *bitmap, u32 bitmap_size)
771{
772 u32 mod;
773 int i, idx = -1;
774
775 mod = vector % dest_vcpus;
776
777 for (i = 0; i <= mod; i++) {
778 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
779 BUG_ON(idx == bitmap_size);
780 }
781
782 return idx;
783}
784
4efd805f
RK		 785static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
786{
787 if (!kvm->arch.disabled_lapic_found) {
788 kvm->arch.disabled_lapic_found = true;
789 printk(KERN_INFO
790 "Disabled LAPIC found during irq injection\n");
791 }
792}
793
c519265f
RK		 794static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
795 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
1e08ec4a 796{
c519265f
RK		 797 if (kvm->arch.x2apic_broadcast_quirk_disabled) {
798 if ((irq->dest_id == APIC_BROADCAST &&
799 map->mode != KVM_APIC_MODE_X2APIC))
800 return true;
801 if (irq->dest_id == X2APIC_BROADCAST)
802 return true;
803 } else {
804 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
805 if (irq->dest_id == (x2apic_ipi ?
806 X2APIC_BROADCAST : APIC_BROADCAST))
807 return true;
808 }
1e08ec4a 809
c519265f
RK		 810 return false;
811}
1e08ec4a 812
64aa47bf
RK		 813/* Return true if the interrupt can be handled by using *bitmap as index mask
814 * for valid destinations in *dst array.
815 * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
816 * Note: we may have zero kvm_lapic destinations when we return true, which
817 * means that the interrupt should be dropped. In this case, *bitmap would be
818 * zero and *dst undefined.
819 */
820static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
821 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
822 struct kvm_apic_map *map, struct kvm_lapic ***dst,
823 unsigned long *bitmap)
824{
825 int i, lowest;
1e08ec4a 826
64aa47bf
RK		 827 if (irq->shorthand == APIC_DEST_SELF && src) {
828 *dst = src;
829 *bitmap = 1;
830 return true;
831 } else if (irq->shorthand)
1e08ec4a
GN		 832 return false;
833
c519265f 834 if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
9ea369b0
RK		 835 return false;
836
64aa47bf 837 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
0ca52e7b 838 if (irq->dest_id > map->max_apic_id) {
64aa47bf
RK		 839 *bitmap = 0;
840 } else {
841 *dst = &map->phys_map[irq->dest_id];
842 *bitmap = 1;
843 }
1e08ec4a 844 return true;
bea15428 845 }
698f9755 846
e45115b6
RK		 847 *bitmap = 0;
848 if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
849 (u16 *)bitmap))
1e08ec4a 850 return false;
fa834e91 851
64aa47bf
RK		 852 if (!kvm_lowest_prio_delivery(irq))
853 return true;
3548a259 854
64aa47bf
RK		 855 if (!kvm_vector_hashing_enabled()) {
856 lowest = -1;
857 for_each_set_bit(i, bitmap, 16) {
858 if (!(*dst)[i])
859 continue;
860 if (lowest < 0)
861 lowest = i;
862 else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
863 (*dst)[lowest]->vcpu) < 0)
864 lowest = i;
3548a259 865 }
64aa47bf
RK		 866 } else {
867 if (!*bitmap)
868 return true;
3548a259 869
64aa47bf
RK		 870 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
871 bitmap, 16);
45c3094a 872
64aa47bf
RK		 873 if (!(*dst)[lowest]) {
874 kvm_apic_disabled_lapic_found(kvm);
875 *bitmap = 0;
876 return true;
877 }
878 }
1e08ec4a 879
64aa47bf 880 *bitmap = (lowest >= 0) ? 1 << lowest : 0;
1e08ec4a 881
64aa47bf
RK		 882 return true;
883}
52004014 884
64aa47bf
RK		 885bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
886 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
887{
888 struct kvm_apic_map *map;
889 unsigned long bitmap;
890 struct kvm_lapic **dst = NULL;
891 int i;
892 bool ret;
52004014 893
64aa47bf 894 *r = -1;
52004014 895
64aa47bf
RK		 896 if (irq->shorthand == APIC_DEST_SELF) {
897 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
898 return true;
899 }
52004014 900
64aa47bf
RK		 901 rcu_read_lock();
902 map = rcu_dereference(kvm->arch.apic_map);
52004014 903
64aa47bf
RK		 904 ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
905 if (ret)
906 for_each_set_bit(i, &bitmap, 16) {
907 if (!dst[i])
908 continue;
909 if (*r < 0)
910 *r = 0;
911 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
1e08ec4a 912 }
1e08ec4a 913
1e08ec4a
GN		 914 rcu_read_unlock();
915 return ret;
916}
917
6228a0da
FW		 918/*
919 * This routine tries to handler interrupts in posted mode, here is how
920 * it deals with different cases:
921 * - For single-destination interrupts, handle it in posted mode
922 * - Else if vector hashing is enabled and it is a lowest-priority
923 * interrupt, handle it in posted mode and use the following mechanism
924 * to find the destinaiton vCPU.
925 * 1. For lowest-priority interrupts, store all the possible
926 * destination vCPUs in an array.
927 * 2. Use "guest vector % max number of destination vCPUs" to find
928 * the right destination vCPU in the array for the lowest-priority
929 * interrupt.
930 * - Otherwise, use remapped mode to inject the interrupt.
931 */
8feb4a04
FW		 932bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
933 struct kvm_vcpu **dest_vcpu)
934{
935 struct kvm_apic_map *map;
64aa47bf
RK		 936 unsigned long bitmap;
937 struct kvm_lapic **dst = NULL;
8feb4a04 938 bool ret = false;
8feb4a04
FW		 939
940 if (irq->shorthand)
941 return false;
942
943 rcu_read_lock();
944 map = rcu_dereference(kvm->arch.apic_map);
945
64aa47bf
RK		 946 if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
947 hweight16(bitmap) == 1) {
948 unsigned long i = find_first_bit(&bitmap, 16);
6228a0da 949
64aa47bf
RK		 950 if (dst[i]) {
951 *dest_vcpu = dst[i]->vcpu;
952 ret = true;
6228a0da 953 }
8feb4a04
FW		 954 }
955
8feb4a04
FW		 956 rcu_read_unlock();
957 return ret;
958}
959
97222cc8
ED		 960/*
961 * Add a pending IRQ into lapic.
962 * Return 1 if successfully added and 0 if discarded.
963 */
964static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c 965 int vector, int level, int trig_mode,
9e4aabe2 966 struct dest_map *dest_map)
97222cc8 967{
6da7e3f6 968 int result = 0;
c5ec1534 969 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8 970
a183b638
PB		 971 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
972 trig_mode, vector);
97222cc8 973 switch (delivery_mode) {
97222cc8 974 case APIC_DM_LOWEST:
e1035715
GN		 975 vcpu->arch.apic_arb_prio++;
976 case APIC_DM_FIXED:
bdaffe1d
PB		 977 if (unlikely(trig_mode && !level))
978 break;
979
97222cc8
ED		 980 /* FIXME add logic for vcpu on reset */
981 if (unlikely(!apic_enabled(apic)))
982 break;
983
11f5cc05
JK		 984 result = 1;
985
9daa5007 986 if (dest_map) {
9e4aabe2 987 __set_bit(vcpu->vcpu_id, dest_map->map);
9daa5007
JR		 988 dest_map->vectors[vcpu->vcpu_id] = vector;
989 }
a5d36f82 990
bdaffe1d
PB		 991 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
992 if (trig_mode)
1e6e2755 993 kvm_lapic_set_vector(vector, apic->regs + APIC_TMR);
bdaffe1d
PB		 994 else
995 apic_clear_vector(vector, apic->regs + APIC_TMR);
996 }
997
d62caabb 998 if (vcpu->arch.apicv_active)
5a71785d 999 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
11f5cc05 1000 else {
1e6e2755 1001 kvm_lapic_set_irr(vector, apic);
5a71785d
YZ		 1002
1003 kvm_make_request(KVM_REQ_EVENT, vcpu);
1004 kvm_vcpu_kick(vcpu);
1005 }
97222cc8
ED		 1006 break;
1007
1008 case APIC_DM_REMRD:
24d2166b
R		 1009 result = 1;
1010 vcpu->arch.pv.pv_unhalted = 1;
1011 kvm_make_request(KVM_REQ_EVENT, vcpu);
1012 kvm_vcpu_kick(vcpu);
97222cc8
ED		 1013 break;
1014
1015 case APIC_DM_SMI:
64d60670
PB		 1016 result = 1;
1017 kvm_make_request(KVM_REQ_SMI, vcpu);
1018 kvm_vcpu_kick(vcpu);
97222cc8 1019 break;
3419ffc8 1020
97222cc8 1021 case APIC_DM_NMI:
6da7e3f6 1022 result = 1;
3419ffc8 1023 kvm_inject_nmi(vcpu);
26df99c6 1024 kvm_vcpu_kick(vcpu);
97222cc8
ED		 1025 break;
1026
1027 case APIC_DM_INIT:
a52315e1 1028 if (!trig_mode || level) {
6da7e3f6 1029 result = 1;
66450a21
JK		 1030 /* assumes that there are only KVM_APIC_INIT/SIPI */
1031 apic->pending_events = (1UL << KVM_APIC_INIT);
1032 /* make sure pending_events is visible before sending
1033 * the request */
1034 smp_wmb();
3842d135 1035 kvm_make_request(KVM_REQ_EVENT, vcpu);
c5ec1534
HQ		 1036 kvm_vcpu_kick(vcpu);
1037 } else {
1b10bf31
JK		 1038 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
1039 vcpu->vcpu_id);
c5ec1534 1040 }
97222cc8
ED		 1041 break;
1042
1043 case APIC_DM_STARTUP:
1b10bf31
JK		 1044 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
1045 vcpu->vcpu_id, vector);
66450a21
JK		 1046 result = 1;
1047 apic->sipi_vector = vector;
1048 /* make sure sipi_vector is visible for the receiver */
1049 smp_wmb();
1050 set_bit(KVM_APIC_SIPI, &apic->pending_events);
1051 kvm_make_request(KVM_REQ_EVENT, vcpu);
1052 kvm_vcpu_kick(vcpu);
97222cc8
ED		 1053 break;
1054
23930f95
JK		 1055 case APIC_DM_EXTINT:
1056 /*
1057 * Should only be called by kvm_apic_local_deliver() with LVT0,
1058 * before NMI watchdog was enabled. Already handled by
1059 * kvm_apic_accept_pic_intr().
1060 */
1061 break;
1062
97222cc8
ED		 1063 default:
1064 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
1065 delivery_mode);
1066 break;
1067 }
1068 return result;
1069}
1070
e1035715 1071int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
8be5453f 1072{
e1035715 1073 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
8be5453f
ZX		 1074}
1075
3bb345f3
PB		 1076static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1077{
6308630b 1078 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
3bb345f3
PB		 1079}
1080
c7c9c56c
YZ		 1081static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1082{
7543a635
SR		 1083 int trigger_mode;
1084
1085 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1086 if (!kvm_ioapic_handles_vector(apic, vector))
1087 return;
3bb345f3 1088
7543a635
SR		 1089 /* Request a KVM exit to inform the userspace IOAPIC. */
1090 if (irqchip_split(apic->vcpu->kvm)) {
1091 apic->vcpu->arch.pending_ioapic_eoi = vector;
1092 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1093 return;
c7c9c56c 1094 }
7543a635
SR		 1095
1096 if (apic_test_vector(vector, apic->regs + APIC_TMR))
1097 trigger_mode = IOAPIC_LEVEL_TRIG;
1098 else
1099 trigger_mode = IOAPIC_EDGE_TRIG;
1100
1101 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
c7c9c56c
YZ		 1102}
1103
ae7a2a3f 1104static int apic_set_eoi(struct kvm_lapic *apic)
97222cc8
ED		 1105{
1106 int vector = apic_find_highest_isr(apic);
ae7a2a3f
MT		 1107
1108 trace_kvm_eoi(apic, vector);
1109
97222cc8
ED		 1110 /*
1111 * Not every write EOI will has corresponding ISR,
1112 * one example is when Kernel check timer on setup_IO_APIC
1113 */
1114 if (vector == -1)
ae7a2a3f 1115 return vector;
97222cc8 1116
8680b94b 1117 apic_clear_isr(vector, apic);
97222cc8
ED		 1118 apic_update_ppr(apic);
1119
5c919412
AS		 1120 if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1121 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1122
c7c9c56c 1123 kvm_ioapic_send_eoi(apic, vector);
3842d135 1124 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
ae7a2a3f 1125 return vector;
97222cc8
ED		 1126}
1127
c7c9c56c
YZ		 1128/*
1129 * this interface assumes a trap-like exit, which has already finished
1130 * desired side effect including vISR and vPPR update.
1131 */
1132void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1133{
1134 struct kvm_lapic *apic = vcpu->arch.apic;
1135
1136 trace_kvm_eoi(apic, vector);
1137
1138 kvm_ioapic_send_eoi(apic, vector);
1139 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1140}
1141EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1142
97222cc8
ED		 1143static void apic_send_ipi(struct kvm_lapic *apic)
1144{
dfb95954
SS		 1145 u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR);
1146 u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2);
58c2dde1 1147 struct kvm_lapic_irq irq;
97222cc8 1148
58c2dde1
GN		 1149 irq.vector = icr_low & APIC_VECTOR_MASK;
1150 irq.delivery_mode = icr_low & APIC_MODE_MASK;
1151 irq.dest_mode = icr_low & APIC_DEST_MASK;
b7cb2231 1152 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
58c2dde1
GN		 1153 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1154 irq.shorthand = icr_low & APIC_SHORT_MASK;
93bbf0b8 1155 irq.msi_redir_hint = false;
0105d1a5
GN		 1156 if (apic_x2apic_mode(apic))
1157 irq.dest_id = icr_high;
1158 else
1159 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
97222cc8 1160
1000ff8d
GN		 1161 trace_kvm_apic_ipi(icr_low, irq.dest_id);
1162
97222cc8
ED		 1163 apic_debug("icr_high 0x%x, icr_low 0x%x, "
1164 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
93bbf0b8
JS		 1165 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1166 "msi_redir_hint 0x%x\n",
9b5843dd 1167 icr_high, icr_low, irq.shorthand, irq.dest_id,
58c2dde1 1168 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
93bbf0b8 1169 irq.vector, irq.msi_redir_hint);
58c2dde1 1170
b4f2225c 1171 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
97222cc8
ED		 1172}
1173
1174static u32 apic_get_tmcct(struct kvm_lapic *apic)
1175{
8003c9ae 1176 ktime_t remaining, now;
b682b814 1177 s64 ns;
9da8f4e8 1178 u32 tmcct;
97222cc8
ED		 1179
1180 ASSERT(apic != NULL);
1181
9da8f4e8 1182 /* if initial count is 0, current count should also be 0 */
dfb95954 1183 if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
b963a22e 1184 apic->lapic_timer.period == 0)
9da8f4e8
KP		 1185 return 0;
1186
5587859f 1187 now = ktime_get();
8003c9ae 1188 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
b682b814 1189 if (ktime_to_ns(remaining) < 0)
8b0e1953 1190 remaining = 0;
b682b814 1191
d3c7b77d
MT		 1192 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1193 tmcct = div64_u64(ns,
1194 (APIC_BUS_CYCLE_NS * apic->divide_count));
97222cc8
ED		 1195
1196 return tmcct;
1197}
1198
b209749f
AK		 1199static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1200{
1201 struct kvm_vcpu *vcpu = apic->vcpu;
1202 struct kvm_run *run = vcpu->run;
1203
a8eeb04a 1204 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
5fdbf976 1205 run->tpr_access.rip = kvm_rip_read(vcpu);
b209749f
AK		 1206 run->tpr_access.is_write = write;
1207}
1208
1209static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1210{
1211 if (apic->vcpu->arch.tpr_access_reporting)
1212 __report_tpr_access(apic, write);
1213}
1214
97222cc8
ED		 1215static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1216{
1217 u32 val = 0;
1218
1219 if (offset >= LAPIC_MMIO_LENGTH)
1220 return 0;
1221
1222 switch (offset) {
1223 case APIC_ARBPRI:
7712de87 1224 apic_debug("Access APIC ARBPRI register which is for P6\n");
97222cc8
ED		 1225 break;
1226
1227 case APIC_TMCCT: /* Timer CCR */
a3e06bbe
LJ		 1228 if (apic_lvtt_tscdeadline(apic))
1229 return 0;
1230
97222cc8
ED		 1231 val = apic_get_tmcct(apic);
1232 break;
4a4541a4
AK		 1233 case APIC_PROCPRI:
1234 apic_update_ppr(apic);
dfb95954 1235 val = kvm_lapic_get_reg(apic, offset);
4a4541a4 1236 break;
b209749f
AK		 1237 case APIC_TASKPRI:
1238 report_tpr_access(apic, false);
1239 /* fall thru */
97222cc8 1240 default:
dfb95954 1241 val = kvm_lapic_get_reg(apic, offset);
97222cc8
ED		 1242 break;
1243 }
1244
1245 return val;
1246}
1247
d76685c4
GH		 1248static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1249{
1250 return container_of(dev, struct kvm_lapic, dev);
1251}
1252
1e6e2755 1253int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
0105d1a5 1254 void *data)
97222cc8 1255{
97222cc8
ED		 1256 unsigned char alignment = offset & 0xf;
1257 u32 result;
d5b0b5b1 1258 /* this bitmask has a bit cleared for each reserved register */
0105d1a5 1259 static const u64 rmask = 0x43ff01ffffffe70cULL;
97222cc8
ED		 1260
1261 if ((alignment + len) > 4) {
4088bb3c
GN		 1262 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1263 offset, len);
0105d1a5 1264 return 1;
97222cc8 1265 }
0105d1a5
GN		 1266
1267 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
4088bb3c
GN		 1268 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1269 offset);
0105d1a5
GN		 1270 return 1;
1271 }
1272
97222cc8
ED		 1273 result = __apic_read(apic, offset & ~0xf);
1274
229456fc
MT		 1275 trace_kvm_apic_read(offset, result);
1276
97222cc8
ED		 1277 switch (len) {
1278 case 1:
1279 case 2:
1280 case 4:
1281 memcpy(data, (char *)&result + alignment, len);
1282 break;
1283 default:
1284 printk(KERN_ERR "Local APIC read with len = %x, "
1285 "should be 1,2, or 4 instead\n", len);
1286 break;
1287 }
bda9020e 1288 return 0;
97222cc8 1289}
1e6e2755 1290EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
97222cc8 1291
0105d1a5
GN		 1292static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1293{
c48f1496 1294 return kvm_apic_hw_enabled(apic) &&
0105d1a5
GN		 1295 addr >= apic->base_address &&
1296 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1297}
1298
e32edf4f 1299static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
0105d1a5
GN		 1300 gpa_t address, int len, void *data)
1301{
1302 struct kvm_lapic *apic = to_lapic(this);
1303 u32 offset = address - apic->base_address;
1304
1305 if (!apic_mmio_in_range(apic, address))
1306 return -EOPNOTSUPP;
1307
1e6e2755 1308 kvm_lapic_reg_read(apic, offset, len, data);
0105d1a5
GN		 1309
1310 return 0;
1311}
1312
97222cc8
ED		 1313static void update_divide_count(struct kvm_lapic *apic)
1314{
1315 u32 tmp1, tmp2, tdcr;
1316
dfb95954 1317 tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
97222cc8
ED		 1318 tmp1 = tdcr & 0xf;
1319 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
d3c7b77d 1320 apic->divide_count = 0x1 << (tmp2 & 0x7);
97222cc8
ED		 1321
1322 apic_debug("timer divide count is 0x%x\n",
9b5843dd 1323 apic->divide_count);
97222cc8
ED		 1324}
1325
ccbfa1d3
WL		 1326static void limit_periodic_timer_frequency(struct kvm_lapic *apic)
1327{
1328 /*
1329 * Do not allow the guest to program periodic timers with small
1330 * interval, since the hrtimers are not throttled by the host
1331 * scheduler.
1332 */
dedf9c5e 1333 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
ccbfa1d3
WL		 1334 s64 min_period = min_timer_period_us * 1000LL;
1335
1336 if (apic->lapic_timer.period < min_period) {
1337 pr_info_ratelimited(
1338 "kvm: vcpu %i: requested %lld ns "
1339 "lapic timer period limited to %lld ns\n",
1340 apic->vcpu->vcpu_id,
1341 apic->lapic_timer.period, min_period);
1342 apic->lapic_timer.period = min_period;
1343 }
1344 }
1345}
1346
b6ac0695
RK		 1347static void apic_update_lvtt(struct kvm_lapic *apic)
1348{
dfb95954 1349 u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
b6ac0695
RK		 1350 apic->lapic_timer.timer_mode_mask;
1351
1352 if (apic->lapic_timer.timer_mode != timer_mode) {
c69518c8 1353 if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
dedf9c5e 1354 APIC_LVT_TIMER_TSCDEADLINE)) {
dedf9c5e 1355 hrtimer_cancel(&apic->lapic_timer.timer);
44275932
RK		 1356 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1357 apic->lapic_timer.period = 0;
1358 apic->lapic_timer.tscdeadline = 0;
dedf9c5e 1359 }
b6ac0695 1360 apic->lapic_timer.timer_mode = timer_mode;
dedf9c5e 1361 limit_periodic_timer_frequency(apic);
b6ac0695
RK		 1362 }
1363}
1364
5d87db71
RK		 1365static void apic_timer_expired(struct kvm_lapic *apic)
1366{
1367 struct kvm_vcpu *vcpu = apic->vcpu;
8577370f 1368 struct swait_queue_head *q = &vcpu->wq;
d0659d94 1369 struct kvm_timer *ktimer = &apic->lapic_timer;
5d87db71 1370
5d87db71
RK		 1371 if (atomic_read(&apic->lapic_timer.pending))
1372 return;
1373
1374 atomic_inc(&apic->lapic_timer.pending);
bab5bb39 1375 kvm_set_pending_timer(vcpu);
5d87db71 1376
cc1b4680
DB		 1377 /*
1378 * For x86, the atomic_inc() is serialized, thus
1379 * using swait_active() is safe.
1380 */
8577370f
MT		 1381 if (swait_active(q))
1382 swake_up(q);
d0659d94
MT		 1383
1384 if (apic_lvtt_tscdeadline(apic))
1385 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1386}
1387
1388/*
1389 * On APICv, this test will cause a busy wait
1390 * during a higher-priority task.
1391 */
1392
1393static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1394{
1395 struct kvm_lapic *apic = vcpu->arch.apic;
dfb95954 1396 u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
d0659d94
MT		 1397
1398 if (kvm_apic_hw_enabled(apic)) {
1399 int vec = reg & APIC_VECTOR_MASK;
f9339860 1400 void *bitmap = apic->regs + APIC_ISR;
d0659d94 1401
d62caabb 1402 if (vcpu->arch.apicv_active)
f9339860
MT		 1403 bitmap = apic->regs + APIC_IRR;
1404
1405 if (apic_test_vector(vec, bitmap))
1406 return true;
d0659d94
MT		 1407 }
1408 return false;
1409}
1410
1411void wait_lapic_expire(struct kvm_vcpu *vcpu)
1412{
1413 struct kvm_lapic *apic = vcpu->arch.apic;
1414 u64 guest_tsc, tsc_deadline;
1415
bce87cce 1416 if (!lapic_in_kernel(vcpu))
d0659d94
MT		 1417 return;
1418
1419 if (apic->lapic_timer.expired_tscdeadline == 0)
1420 return;
1421
1422 if (!lapic_timer_int_injected(vcpu))
1423 return;
1424
1425 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1426 apic->lapic_timer.expired_tscdeadline = 0;
4ba76538 1427 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
6c19b753 1428 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
d0659d94
MT		 1429
1430 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1431 if (guest_tsc < tsc_deadline)
b606f189
MT		 1432 __delay(min(tsc_deadline - guest_tsc,
1433 nsec_to_cycles(vcpu, lapic_timer_advance_ns)));
5d87db71
RK		 1434}
1435
53f9eedf
YJ		 1436static void start_sw_tscdeadline(struct kvm_lapic *apic)
1437{
1438 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1439 u64 ns = 0;
1440 ktime_t expire;
1441 struct kvm_vcpu *vcpu = apic->vcpu;
1442 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1443 unsigned long flags;
1444 ktime_t now;
1445
1446 if (unlikely(!tscdeadline || !this_tsc_khz))
1447 return;
1448
1449 local_irq_save(flags);
1450
5587859f 1451 now = ktime_get();
53f9eedf
YJ		 1452 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1453 if (likely(tscdeadline > guest_tsc)) {
1454 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1455 do_div(ns, this_tsc_khz);
1456 expire = ktime_add_ns(now, ns);
1457 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1458 hrtimer_start(&apic->lapic_timer.timer,
1459 expire, HRTIMER_MODE_ABS_PINNED);
1460 } else
1461 apic_timer_expired(apic);
1462
1463 local_irq_restore(flags);
1464}
1465
c301b909
WL		 1466static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor)
1467{
1468 ktime_t now, remaining;
1469 u64 ns_remaining_old, ns_remaining_new;
1470
1471 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1472 * APIC_BUS_CYCLE_NS * apic->divide_count;
1473 limit_periodic_timer_frequency(apic);
1474
1475 now = ktime_get();
1476 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1477 if (ktime_to_ns(remaining) < 0)
1478 remaining = 0;
1479
1480 ns_remaining_old = ktime_to_ns(remaining);
1481 ns_remaining_new = mul_u64_u32_div(ns_remaining_old,
1482 apic->divide_count, old_divisor);
1483
1484 apic->lapic_timer.tscdeadline +=
1485 nsec_to_cycles(apic->vcpu, ns_remaining_new) -
1486 nsec_to_cycles(apic->vcpu, ns_remaining_old);
1487 apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new);
1488}
1489
8003c9ae 1490static bool set_target_expiration(struct kvm_lapic *apic)
7d7f7da2
WL		 1491{
1492 ktime_t now;
8003c9ae 1493 u64 tscl = rdtsc();
7d7f7da2 1494
5587859f 1495 now = ktime_get();
7d7f7da2 1496 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
8003c9ae 1497 * APIC_BUS_CYCLE_NS * apic->divide_count;
7d7f7da2 1498
5d74a699
RK		 1499 if (!apic->lapic_timer.period) {
1500 apic->lapic_timer.tscdeadline = 0;
8003c9ae 1501 return false;
7d7f7da2
WL		 1502 }
1503
ccbfa1d3 1504 limit_periodic_timer_frequency(apic);
7d7f7da2 1505
7d7f7da2
WL		 1506 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1507 PRIx64 ", "
1508 "timer initial count 0x%x, period %lldns, "
1509 "expire @ 0x%016" PRIx64 ".\n", __func__,
1510 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1511 kvm_lapic_get_reg(apic, APIC_TMICT),
1512 apic->lapic_timer.period,
1513 ktime_to_ns(ktime_add_ns(now,
1514 apic->lapic_timer.period)));
8003c9ae
WL		 1515
1516 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1517 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1518 apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period);
1519
1520 return true;
1521}
1522
1523static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1524{
1525 apic->lapic_timer.tscdeadline +=
1526 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1527 apic->lapic_timer.target_expiration =
1528 ktime_add_ns(apic->lapic_timer.target_expiration,
1529 apic->lapic_timer.period);
7d7f7da2
WL		 1530}
1531
ecf08dad
AB		 1532static void start_sw_period(struct kvm_lapic *apic)
1533{
1534 if (!apic->lapic_timer.period)
1535 return;
1536
1537 if (ktime_after(ktime_get(),
1538 apic->lapic_timer.target_expiration)) {
1539 apic_timer_expired(apic);
1540
1541 if (apic_lvtt_oneshot(apic))
1542 return;
1543
1544 advance_periodic_target_expiration(apic);
1545 }
1546
1547 hrtimer_start(&apic->lapic_timer.timer,
1548 apic->lapic_timer.target_expiration,
1549 HRTIMER_MODE_ABS_PINNED);
1550}
1551
ce7a058a
YJ		 1552bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1553{
91005300
WL		 1554 if (!lapic_in_kernel(vcpu))
1555 return false;
1556
ce7a058a
YJ		 1557 return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1558}
1559EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1560
7e810a38 1561static void cancel_hv_timer(struct kvm_lapic *apic)
bd97ad0e 1562{
1d518c68 1563 WARN_ON(preemptible());
a749e247 1564 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
bd97ad0e
WL		 1565 kvm_x86_ops->cancel_hv_timer(apic->vcpu);
1566 apic->lapic_timer.hv_timer_in_use = false;
1567}
1568
a749e247 1569static bool start_hv_timer(struct kvm_lapic *apic)
196f20ca 1570{
35ee9e48
PB		 1571 struct kvm_timer *ktimer = &apic->lapic_timer;
1572 int r;
196f20ca 1573
1d518c68 1574 WARN_ON(preemptible());
a749e247
PB		 1575 if (!kvm_x86_ops->set_hv_timer)
1576 return false;
1577
35ee9e48
PB		 1578 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1579 return false;
1580
86bbc1e6
RK		 1581 if (!ktimer->tscdeadline)
1582 return false;
1583
35ee9e48
PB		 1584 r = kvm_x86_ops->set_hv_timer(apic->vcpu, ktimer->tscdeadline);
1585 if (r < 0)
1586 return false;
1587
1588 ktimer->hv_timer_in_use = true;
1589 hrtimer_cancel(&ktimer->timer);
196f20ca 1590
35ee9e48
PB		 1591 /*
1592 * Also recheck ktimer->pending, in case the sw timer triggered in
1593 * the window. For periodic timer, leave the hv timer running for
1594 * simplicity, and the deadline will be recomputed on the next vmexit.
1595 */
c8533544
WL		 1596 if (!apic_lvtt_period(apic) && (r || atomic_read(&ktimer->pending))) {
1597 if (r)
1598 apic_timer_expired(apic);
35ee9e48 1599 return false;
c8533544 1600 }
a749e247
PB		 1601
1602 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, true);
35ee9e48
PB		 1603 return true;
1604}
1605
a749e247 1606static void start_sw_timer(struct kvm_lapic *apic)
35ee9e48 1607{
a749e247 1608 struct kvm_timer *ktimer = &apic->lapic_timer;
1d518c68
WL		 1609
1610 WARN_ON(preemptible());
a749e247
PB		 1611 if (apic->lapic_timer.hv_timer_in_use)
1612 cancel_hv_timer(apic);
1613 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1614 return;
1615
1616 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1617 start_sw_period(apic);
1618 else if (apic_lvtt_tscdeadline(apic))
1619 start_sw_tscdeadline(apic);
1620 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false);
1621}
35ee9e48 1622
a749e247
PB		 1623static void restart_apic_timer(struct kvm_lapic *apic)
1624{
1d518c68 1625 preempt_disable();
a749e247
PB		 1626 if (!start_hv_timer(apic))
1627 start_sw_timer(apic);
1d518c68 1628 preempt_enable();
196f20ca
WL		 1629}
1630
8003c9ae
WL		 1631void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1632{
1633 struct kvm_lapic *apic = vcpu->arch.apic;
1634
1d518c68
WL		 1635 preempt_disable();
1636 /* If the preempt notifier has already run, it also called apic_timer_expired */
1637 if (!apic->lapic_timer.hv_timer_in_use)
1638 goto out;
8003c9ae
WL		 1639 WARN_ON(swait_active(&vcpu->wq));
1640 cancel_hv_timer(apic);
1641 apic_timer_expired(apic);
1642
1643 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1644 advance_periodic_target_expiration(apic);
a749e247 1645 restart_apic_timer(apic);
8003c9ae 1646 }
1d518c68
WL		 1647out:
1648 preempt_enable();
8003c9ae
WL		 1649}
1650EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1651
ce7a058a
YJ		 1652void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1653{
a749e247 1654 restart_apic_timer(vcpu->arch.apic);
ce7a058a
YJ		 1655}
1656EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1657
1658void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1659{
1660 struct kvm_lapic *apic = vcpu->arch.apic;
1661
1d518c68 1662 preempt_disable();
ce7a058a 1663 /* Possibly the TSC deadline timer is not enabled yet */
a749e247
PB		 1664 if (apic->lapic_timer.hv_timer_in_use)
1665 start_sw_timer(apic);
1d518c68 1666 preempt_enable();
a749e247
PB		 1667}
1668EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
ce7a058a 1669
a749e247
PB		 1670void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu)
1671{
1672 struct kvm_lapic *apic = vcpu->arch.apic;
ce7a058a 1673
a749e247
PB		 1674 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1675 restart_apic_timer(apic);
ce7a058a 1676}
ce7a058a 1677
97222cc8
ED		 1678static void start_apic_timer(struct kvm_lapic *apic)
1679{
d3c7b77d 1680 atomic_set(&apic->lapic_timer.pending, 0);
0b975a3c 1681
a749e247
PB		 1682 if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1683 && !set_target_expiration(apic))
1684 return;
1685
1686 restart_apic_timer(apic);
97222cc8
ED		 1687}
1688
cc6e462c
JK		 1689static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1690{
59fd1323 1691 bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
cc6e462c 1692
59fd1323
RK		 1693 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1694 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1695 if (lvt0_in_nmi_mode) {
cc6e462c
JK		 1696 apic_debug("Receive NMI setting on APIC_LVT0 "
1697 "for cpu %d\n", apic->vcpu->vcpu_id);
42720138 1698 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
59fd1323
RK		 1699 } else
1700 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1701 }
cc6e462c
JK		 1702}
1703
1e6e2755 1704int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
97222cc8 1705{
0105d1a5 1706 int ret = 0;
97222cc8 1707
0105d1a5 1708 trace_kvm_apic_write(reg, val);
97222cc8 1709
0105d1a5 1710 switch (reg) {
97222cc8 1711 case APIC_ID: /* Local APIC ID */
0105d1a5 1712 if (!apic_x2apic_mode(apic))
a92e2543 1713 kvm_apic_set_xapic_id(apic, val >> 24);
0105d1a5
GN		 1714 else
1715 ret = 1;
97222cc8
ED		 1716 break;
1717
1718 case APIC_TASKPRI:
b209749f 1719 report_tpr_access(apic, true);
97222cc8
ED		 1720 apic_set_tpr(apic, val & 0xff);
1721 break;
1722
1723 case APIC_EOI:
1724 apic_set_eoi(apic);
1725 break;
1726
1727 case APIC_LDR:
0105d1a5 1728 if (!apic_x2apic_mode(apic))
1e08ec4a 1729 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
0105d1a5
GN		 1730 else
1731 ret = 1;
97222cc8
ED		 1732 break;
1733
1734 case APIC_DFR:
1e08ec4a 1735 if (!apic_x2apic_mode(apic)) {
1e6e2755 1736 kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1e08ec4a
GN		 1737 recalculate_apic_map(apic->vcpu->kvm);
1738 } else
0105d1a5 1739 ret = 1;
97222cc8
ED		 1740 break;
1741
fc61b800
GN		 1742 case APIC_SPIV: {
1743 u32 mask = 0x3ff;
dfb95954 1744 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
fc61b800 1745 mask |= APIC_SPIV_DIRECTED_EOI;
f8c1ea10 1746 apic_set_spiv(apic, val & mask);
97222cc8
ED		 1747 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1748 int i;
1749 u32 lvt_val;
1750
1e6e2755 1751 for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
dfb95954 1752 lvt_val = kvm_lapic_get_reg(apic,
97222cc8 1753 APIC_LVTT + 0x10 * i);
1e6e2755 1754 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
97222cc8
ED		 1755 lvt_val | APIC_LVT_MASKED);
1756 }
b6ac0695 1757 apic_update_lvtt(apic);
d3c7b77d 1758 atomic_set(&apic->lapic_timer.pending, 0);
97222cc8
ED		 1759
1760 }
1761 break;
fc61b800 1762 }
97222cc8
ED		 1763 case APIC_ICR:
1764 /* No delay here, so we always clear the pending bit */
1e6e2755 1765 kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
97222cc8
ED		 1766 apic_send_ipi(apic);
1767 break;
1768
1769 case APIC_ICR2:
0105d1a5
GN		 1770 if (!apic_x2apic_mode(apic))
1771 val &= 0xff000000;
1e6e2755 1772 kvm_lapic_set_reg(apic, APIC_ICR2, val);
97222cc8
ED		 1773 break;
1774
23930f95 1775 case APIC_LVT0:
cc6e462c 1776 apic_manage_nmi_watchdog(apic, val);
97222cc8
ED		 1777 case APIC_LVTTHMR:
1778 case APIC_LVTPC:
97222cc8
ED		 1779 case APIC_LVT1:
1780 case APIC_LVTERR:
1781 /* TODO: Check vector */
c48f1496 1782 if (!kvm_apic_sw_enabled(apic))
97222cc8
ED		 1783 val |= APIC_LVT_MASKED;
1784
0105d1a5 1785 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1e6e2755 1786 kvm_lapic_set_reg(apic, reg, val);
97222cc8
ED		 1787
1788 break;
1789
b6ac0695 1790 case APIC_LVTT:
c48f1496 1791 if (!kvm_apic_sw_enabled(apic))
a3e06bbe
LJ		 1792 val |= APIC_LVT_MASKED;
1793 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1e6e2755 1794 kvm_lapic_set_reg(apic, APIC_LVTT, val);
b6ac0695 1795 apic_update_lvtt(apic);
a3e06bbe
LJ		 1796 break;
1797
97222cc8 1798 case APIC_TMICT:
a3e06bbe
LJ		 1799 if (apic_lvtt_tscdeadline(apic))
1800 break;
1801
d3c7b77d 1802 hrtimer_cancel(&apic->lapic_timer.timer);
1e6e2755 1803 kvm_lapic_set_reg(apic, APIC_TMICT, val);
97222cc8 1804 start_apic_timer(apic);
0105d1a5 1805 break;
97222cc8 1806
c301b909
WL		 1807 case APIC_TDCR: {
1808 uint32_t old_divisor = apic->divide_count;
1809
97222cc8 1810 if (val & 4)
7712de87 1811 apic_debug("KVM_WRITE:TDCR %x\n", val);
1e6e2755 1812 kvm_lapic_set_reg(apic, APIC_TDCR, val);
97222cc8 1813 update_divide_count(apic);
c301b909
WL		 1814 if (apic->divide_count != old_divisor &&
1815 apic->lapic_timer.period) {
1816 hrtimer_cancel(&apic->lapic_timer.timer);
1817 update_target_expiration(apic, old_divisor);
1818 restart_apic_timer(apic);
1819 }
97222cc8 1820 break;
c301b909 1821 }
0105d1a5
GN		 1822 case APIC_ESR:
1823 if (apic_x2apic_mode(apic) && val != 0) {
7712de87 1824 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
0105d1a5
GN		 1825 ret = 1;
1826 }
1827 break;
1828
1829 case APIC_SELF_IPI:
1830 if (apic_x2apic_mode(apic)) {
1e6e2755 1831 kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
0105d1a5
GN		 1832 } else
1833 ret = 1;
1834 break;
97222cc8 1835 default:
0105d1a5 1836 ret = 1;
97222cc8
ED		 1837 break;
1838 }
0105d1a5
GN		 1839 if (ret)
1840 apic_debug("Local APIC Write to read-only register %x\n", reg);
1841 return ret;
1842}
1e6e2755 1843EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
0105d1a5 1844
e32edf4f 1845static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
0105d1a5
GN		 1846 gpa_t address, int len, const void *data)
1847{
1848 struct kvm_lapic *apic = to_lapic(this);
1849 unsigned int offset = address - apic->base_address;
1850 u32 val;
1851
1852 if (!apic_mmio_in_range(apic, address))
1853 return -EOPNOTSUPP;
1854
1855 /*
1856 * APIC register must be aligned on 128-bits boundary.
1857 * 32/64/128 bits registers must be accessed thru 32 bits.
1858 * Refer SDM 8.4.1
1859 */
1860 if (len != 4 || (offset & 0xf)) {
1861 /* Don't shout loud, $infamous_os would cause only noise. */
1862 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
756975bb 1863 return 0;
0105d1a5
GN		 1864 }
1865
1866 val = *(u32*)data;
1867
1868 /* too common printing */
1869 if (offset != APIC_EOI)
1870 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1871 "0x%x\n", __func__, offset, len, val);
1872
1e6e2755 1873 kvm_lapic_reg_write(apic, offset & 0xff0, val);
0105d1a5 1874
bda9020e 1875 return 0;
97222cc8
ED		 1876}
1877
58fbbf26
KT		 1878void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1879{
1e6e2755 1880 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
58fbbf26
KT		 1881}
1882EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1883
83d4c286
YZ		 1884/* emulate APIC access in a trap manner */
1885void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1886{
1887 u32 val = 0;
1888
1889 /* hw has done the conditional check and inst decode */
1890 offset &= 0xff0;
1891
1e6e2755 1892 kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
83d4c286
YZ		 1893
1894 /* TODO: optimize to just emulate side effect w/o one more write */
1e6e2755 1895 kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
83d4c286
YZ		 1896}
1897EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1898
d589444e 1899void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 1900{
f8c1ea10
GN		 1901 struct kvm_lapic *apic = vcpu->arch.apic;
1902
ad312c7c 1903 if (!vcpu->arch.apic)
97222cc8
ED		 1904 return;
1905
f8c1ea10 1906 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1907
c5cc421b
GN		 1908 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1909 static_key_slow_dec_deferred(&apic_hw_disabled);
1910
e462755c 1911 if (!apic->sw_enabled)
f8c1ea10 1912 static_key_slow_dec_deferred(&apic_sw_disabled);
97222cc8 1913
f8c1ea10
GN		 1914 if (apic->regs)
1915 free_page((unsigned long)apic->regs);
1916
1917 kfree(apic);
97222cc8
ED		 1918}
1919
1920/*
1921 *----------------------------------------------------------------------
1922 * LAPIC interface
1923 *----------------------------------------------------------------------
1924 */
a3e06bbe
LJ		 1925u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1926{
1927 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1928
a10388e1
WL		 1929 if (!lapic_in_kernel(vcpu) ||
1930 !apic_lvtt_tscdeadline(apic))
a3e06bbe
LJ		 1931 return 0;
1932
1933 return apic->lapic_timer.tscdeadline;
1934}
1935
1936void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1937{
1938 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1939
bce87cce 1940 if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 1941 apic_lvtt_period(apic))
a3e06bbe
LJ		 1942 return;
1943
1944 hrtimer_cancel(&apic->lapic_timer.timer);
1945 apic->lapic_timer.tscdeadline = data;
1946 start_apic_timer(apic);
1947}
1948
97222cc8
ED		 1949void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1950{
ad312c7c 1951 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8 1952
b93463aa 1953 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
dfb95954 1954 | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
97222cc8
ED		 1955}
1956
1957u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1958{
97222cc8
ED		 1959 u64 tpr;
1960
dfb95954 1961 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
97222cc8
ED		 1962
1963 return (tpr & 0xf0) >> 4;
1964}
1965
1966void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1967{
8d14695f 1968 u64 old_value = vcpu->arch.apic_base;
ad312c7c 1969 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8 1970
c7dd15b3 1971 if (!apic)
97222cc8 1972 value |= MSR_IA32_APICBASE_BSP;
c5af89b6 1973
e66d2ae7
JK		 1974 vcpu->arch.apic_base = value;
1975
c7dd15b3
JM		 1976 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
1977 kvm_update_cpuid(vcpu);
1978
1979 if (!apic)
1980 return;
1981
c5cc421b 1982 /* update jump label if enable bit changes */
0dce7cd6 1983 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
49bd29ba
RK		 1984 if (value & MSR_IA32_APICBASE_ENABLE) {
1985 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
c5cc421b 1986 static_key_slow_dec_deferred(&apic_hw_disabled);
187ca84b 1987 } else {
c5cc421b 1988 static_key_slow_inc(&apic_hw_disabled.key);
187ca84b
WL		 1989 recalculate_apic_map(vcpu->kvm);
1990 }
c5cc421b
GN		 1991 }
1992
8d14695f
YZ		 1993 if ((old_value ^ value) & X2APIC_ENABLE) {
1994 if (value & X2APIC_ENABLE) {
257b9a5f 1995 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
8d14695f
YZ		 1996 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1997 } else
1998 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
0105d1a5 1999 }
8d14695f 2000
ad312c7c 2001 apic->base_address = apic->vcpu->arch.apic_base &
97222cc8
ED		 2002 MSR_IA32_APICBASE_BASE;
2003
db324fe6
NA		 2004 if ((value & MSR_IA32_APICBASE_ENABLE) &&
2005 apic->base_address != APIC_DEFAULT_PHYS_BASE)
2006 pr_warn_once("APIC base relocation is unsupported by KVM");
2007
97222cc8
ED		 2008 /* with FSB delivery interrupt, we can restart APIC functionality */
2009 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
ad312c7c 2010 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 2011
2012}
2013
d28bc9dd 2014void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
97222cc8 2015{
b7e31be3 2016 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 2017 int i;
2018
b7e31be3
RK		 2019 if (!apic)
2020 return;
97222cc8 2021
b7e31be3 2022 apic_debug("%s\n", __func__);
97222cc8
ED		 2023
2024 /* Stop the timer in case it's a reset to an active apic */
d3c7b77d 2025 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 2026
4d8e772b
RK		 2027 if (!init_event) {
2028 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE |
2029 MSR_IA32_APICBASE_ENABLE);
a92e2543 2030 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
4d8e772b 2031 }
fc61b800 2032 kvm_apic_set_version(apic->vcpu);
97222cc8 2033
1e6e2755
SS		 2034 for (i = 0; i < KVM_APIC_LVT_NUM; i++)
2035 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
b6ac0695 2036 apic_update_lvtt(apic);
52b54190
JS		 2037 if (kvm_vcpu_is_reset_bsp(vcpu) &&
2038 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
1e6e2755 2039 kvm_lapic_set_reg(apic, APIC_LVT0,
90de4a18 2040 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
dfb95954 2041 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
97222cc8 2042
1e6e2755 2043 kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
f8c1ea10 2044 apic_set_spiv(apic, 0xff);
1e6e2755 2045 kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
c028dd6b
RK		 2046 if (!apic_x2apic_mode(apic))
2047 kvm_apic_set_ldr(apic, 0);
1e6e2755
SS		 2048 kvm_lapic_set_reg(apic, APIC_ESR, 0);
2049 kvm_lapic_set_reg(apic, APIC_ICR, 0);
2050 kvm_lapic_set_reg(apic, APIC_ICR2, 0);
2051 kvm_lapic_set_reg(apic, APIC_TDCR, 0);
2052 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
97222cc8 2053 for (i = 0; i < 8; i++) {
1e6e2755
SS		 2054 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
2055 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
2056 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
97222cc8 2057 }
d62caabb
AS		 2058 apic->irr_pending = vcpu->arch.apicv_active;
2059 apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
8680b94b 2060 apic->highest_isr_cache = -1;
b33ac88b 2061 update_divide_count(apic);
d3c7b77d 2062 atomic_set(&apic->lapic_timer.pending, 0);
c5af89b6 2063 if (kvm_vcpu_is_bsp(vcpu))
5dbc8f3f
GN		 2064 kvm_lapic_set_base(vcpu,
2065 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
ae7a2a3f 2066 vcpu->arch.pv_eoi.msr_val = 0;
97222cc8 2067 apic_update_ppr(apic);
4191db26
JS		 2068 if (vcpu->arch.apicv_active) {
2069 kvm_x86_ops->apicv_post_state_restore(vcpu);
2070 kvm_x86_ops->hwapic_irr_update(vcpu, -1);
2071 kvm_x86_ops->hwapic_isr_update(vcpu, -1);
2072 }
97222cc8 2073
e1035715 2074 vcpu->arch.apic_arb_prio = 0;
41383771 2075 vcpu->arch.apic_attention = 0;
e1035715 2076
6e500439 2077 apic_debug("%s: vcpu=%p, id=0x%x, base_msr="
b8688d51 2078 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
6e500439 2079 vcpu, kvm_lapic_get_reg(apic, APIC_ID),
ad312c7c 2080 vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 2081}
2082
97222cc8
ED		 2083/*
2084 *----------------------------------------------------------------------
2085 * timer interface
2086 *----------------------------------------------------------------------
2087 */
1b9778da 2088
2a6eac96 2089static bool lapic_is_periodic(struct kvm_lapic *apic)
97222cc8 2090{
d3c7b77d 2091 return apic_lvtt_period(apic);
97222cc8
ED		 2092}
2093
3d80840d
MT		 2094int apic_has_pending_timer(struct kvm_vcpu *vcpu)
2095{
54e9818f 2096 struct kvm_lapic *apic = vcpu->arch.apic;
3d80840d 2097
1e3161b4 2098 if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
54e9818f 2099 return atomic_read(&apic->lapic_timer.pending);
3d80840d
MT		 2100
2101 return 0;
2102}
2103
89342082 2104int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1b9778da 2105{
dfb95954 2106 u32 reg = kvm_lapic_get_reg(apic, lvt_type);
23930f95 2107 int vector, mode, trig_mode;
23930f95 2108
c48f1496 2109 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
23930f95
JK		 2110 vector = reg & APIC_VECTOR_MASK;
2111 mode = reg & APIC_MODE_MASK;
2112 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
b4f2225c
YZ		 2113 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
2114 NULL);
23930f95
JK		 2115 }
2116 return 0;
2117}
1b9778da 2118
8fdb2351 2119void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
23930f95 2120{
8fdb2351
JK		 2121 struct kvm_lapic *apic = vcpu->arch.apic;
2122
2123 if (apic)
2124 kvm_apic_local_deliver(apic, APIC_LVT0);
1b9778da
ED		 2125}
2126
d76685c4
GH		 2127static const struct kvm_io_device_ops apic_mmio_ops = {
2128 .read = apic_mmio_read,
2129 .write = apic_mmio_write,
d76685c4
GH		 2130};
2131
e9d90d47
AK		 2132static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
2133{
2134 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2a6eac96 2135 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
e9d90d47 2136
5d87db71 2137 apic_timer_expired(apic);
e9d90d47 2138
2a6eac96 2139 if (lapic_is_periodic(apic)) {
8003c9ae 2140 advance_periodic_target_expiration(apic);
e9d90d47
AK		 2141 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
2142 return HRTIMER_RESTART;
2143 } else
2144 return HRTIMER_NORESTART;
2145}
2146
97222cc8
ED		 2147int kvm_create_lapic(struct kvm_vcpu *vcpu)
2148{
2149 struct kvm_lapic *apic;
2150
2151 ASSERT(vcpu != NULL);
2152 apic_debug("apic_init %d\n", vcpu->vcpu_id);
2153
2154 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
2155 if (!apic)
2156 goto nomem;
2157
ad312c7c 2158 vcpu->arch.apic = apic;
97222cc8 2159
afc20184
TY		 2160 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
2161 if (!apic->regs) {
97222cc8
ED		 2162 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2163 vcpu->vcpu_id);
d589444e 2164 goto nomem_free_apic;
97222cc8 2165 }
97222cc8
ED		 2166 apic->vcpu = vcpu;
2167
d3c7b77d 2168 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
61abdbe0 2169 HRTIMER_MODE_ABS_PINNED);
e9d90d47 2170 apic->lapic_timer.timer.function = apic_timer_fn;
d3c7b77d 2171
c5cc421b
GN		 2172 /*
2173 * APIC is created enabled. This will prevent kvm_lapic_set_base from
2174 * thinking that APIC satet has changed.
2175 */
2176 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
f8c1ea10 2177 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
d76685c4 2178 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
97222cc8
ED		 2179
2180 return 0;
d589444e
RR		 2181nomem_free_apic:
2182 kfree(apic);
97222cc8 2183nomem:
97222cc8
ED		 2184 return -ENOMEM;
2185}
97222cc8
ED		 2186
2187int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2188{
ad312c7c 2189 struct kvm_lapic *apic = vcpu->arch.apic;
b3c045d3 2190 u32 ppr;
97222cc8 2191
f8543d6a 2192 if (!apic_enabled(apic))
97222cc8
ED		 2193 return -1;
2194
b3c045d3
PB		 2195 __apic_update_ppr(apic, &ppr);
2196 return apic_has_interrupt_for_ppr(apic, ppr);
97222cc8
ED		 2197}
2198
40487c68
QH		 2199int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2200{
dfb95954 2201 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
40487c68
QH		 2202 int r = 0;
2203
c48f1496 2204 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
e7dca5c0
CL		 2205 r = 1;
2206 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2207 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
2208 r = 1;
40487c68
QH		 2209 return r;
2210}
2211
1b9778da
ED		 2212void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2213{
ad312c7c 2214 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da 2215
54e9818f 2216 if (atomic_read(&apic->lapic_timer.pending) > 0) {
f1ed0450 2217 kvm_apic_local_deliver(apic, APIC_LVTT);
fae0ba21
NA		 2218 if (apic_lvtt_tscdeadline(apic))
2219 apic->lapic_timer.tscdeadline = 0;
8003c9ae
WL		 2220 if (apic_lvtt_oneshot(apic)) {
2221 apic->lapic_timer.tscdeadline = 0;
8b0e1953 2222 apic->lapic_timer.target_expiration = 0;
8003c9ae 2223 }
f1ed0450 2224 atomic_set(&apic->lapic_timer.pending, 0);
1b9778da
ED		 2225 }
2226}
2227
97222cc8
ED		 2228int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
2229{
2230 int vector = kvm_apic_has_interrupt(vcpu);
ad312c7c 2231 struct kvm_lapic *apic = vcpu->arch.apic;
4d82d12b 2232 u32 ppr;
97222cc8
ED		 2233
2234 if (vector == -1)
2235 return -1;
2236
56cc2406
WL		 2237 /*
2238 * We get here even with APIC virtualization enabled, if doing
2239 * nested virtualization and L1 runs with the "acknowledge interrupt
2240 * on exit" mode. Then we cannot inject the interrupt via RVI,
2241 * because the process would deliver it through the IDT.
2242 */
2243
97222cc8 2244 apic_clear_irr(vector, apic);
5c919412 2245 if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
4d82d12b
PB		 2246 /*
2247 * For auto-EOI interrupts, there might be another pending
2248 * interrupt above PPR, so check whether to raise another
2249 * KVM_REQ_EVENT.
2250 */
5c919412 2251 apic_update_ppr(apic);
4d82d12b
PB		 2252 } else {
2253 /*
2254 * For normal interrupts, PPR has been raised and there cannot
2255 * be a higher-priority pending interrupt---except if there was
2256 * a concurrent interrupt injection, but that would have
2257 * triggered KVM_REQ_EVENT already.
2258 */
2259 apic_set_isr(vector, apic);
2260 __apic_update_ppr(apic, &ppr);
5c919412
AS		 2261 }
2262
97222cc8
ED		 2263 return vector;
2264}
96ad2cc6 2265
a92e2543
RK		 2266static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2267 struct kvm_lapic_state *s, bool set)
2268{
2269 if (apic_x2apic_mode(vcpu->arch.apic)) {
2270 u32 *id = (u32 *)(s->regs + APIC_ID);
12806ba9 2271 u32 *ldr = (u32 *)(s->regs + APIC_LDR);
a92e2543 2272
37131313
RK		 2273 if (vcpu->kvm->arch.x2apic_format) {
2274 if (*id != vcpu->vcpu_id)
2275 return -EINVAL;
2276 } else {
2277 if (set)
2278 *id >>= 24;
2279 else
2280 *id <<= 24;
2281 }
12806ba9
DDAG		 2282
2283 /* In x2APIC mode, the LDR is fixed and based on the id */
2284 if (set)
2285 *ldr = kvm_apic_calc_x2apic_ldr(*id);
a92e2543
RK		 2286 }
2287
2288 return 0;
2289}
2290
2291int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2292{
2293 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2294 return kvm_apic_state_fixup(vcpu, s, false);
2295}
2296
2297int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
96ad2cc6 2298{
ad312c7c 2299 struct kvm_lapic *apic = vcpu->arch.apic;
a92e2543
RK		 2300 int r;
2301
96ad2cc6 2302
5dbc8f3f 2303 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
64eb0620
GN		 2304 /* set SPIV separately to get count of SW disabled APICs right */
2305 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
a92e2543
RK		 2306
2307 r = kvm_apic_state_fixup(vcpu, s, true);
2308 if (r)
2309 return r;
64eb0620 2310 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
a92e2543
RK		 2311
2312 recalculate_apic_map(vcpu->kvm);
fc61b800
GN		 2313 kvm_apic_set_version(vcpu);
2314
96ad2cc6 2315 apic_update_ppr(apic);
d3c7b77d 2316 hrtimer_cancel(&apic->lapic_timer.timer);
b6ac0695 2317 apic_update_lvtt(apic);
dfb95954 2318 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
96ad2cc6
ED		 2319 update_divide_count(apic);
2320 start_apic_timer(apic);
6e24a6ef 2321 apic->irr_pending = true;
d62caabb 2322 apic->isr_count = vcpu->arch.apicv_active ?
c7c9c56c 2323 1 : count_vectors(apic->regs + APIC_ISR);
8680b94b 2324 apic->highest_isr_cache = -1;
d62caabb 2325 if (vcpu->arch.apicv_active) {
967235d3 2326 kvm_x86_ops->apicv_post_state_restore(vcpu);
4114c27d
WW		 2327 kvm_x86_ops->hwapic_irr_update(vcpu,
2328 apic_find_highest_irr(apic));
67c9dddc 2329 kvm_x86_ops->hwapic_isr_update(vcpu,
b4eef9b3 2330 apic_find_highest_isr(apic));
d62caabb 2331 }
3842d135 2332 kvm_make_request(KVM_REQ_EVENT, vcpu);
49df6397
SR		 2333 if (ioapic_in_kernel(vcpu->kvm))
2334 kvm_rtc_eoi_tracking_restore_one(vcpu);
0669a510
RK		 2335
2336 vcpu->arch.apic_arb_prio = 0;
a92e2543
RK		 2337
2338 return 0;
96ad2cc6 2339}
a3d7f85f 2340
2f52d58c 2341void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
a3d7f85f 2342{
a3d7f85f
ED		 2343 struct hrtimer *timer;
2344
bce87cce 2345 if (!lapic_in_kernel(vcpu))
a3d7f85f
ED		 2346 return;
2347
54e9818f 2348 timer = &vcpu->arch.apic->lapic_timer.timer;
a3d7f85f 2349 if (hrtimer_cancel(timer))
61abdbe0 2350 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
a3d7f85f 2351}
b93463aa 2352
ae7a2a3f
MT		 2353/*
2354 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2355 *
2356 * Detect whether guest triggered PV EOI since the
2357 * last entry. If yes, set EOI on guests's behalf.
2358 * Clear PV EOI in guest memory in any case.
2359 */
2360static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2361 struct kvm_lapic *apic)
2362{
2363 bool pending;
2364 int vector;
2365 /*
2366 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2367 * and KVM_PV_EOI_ENABLED in guest memory as follows:
2368 *
2369 * KVM_APIC_PV_EOI_PENDING is unset:
2370 * -> host disabled PV EOI.
2371 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2372 * -> host enabled PV EOI, guest did not execute EOI yet.
2373 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2374 * -> host enabled PV EOI, guest executed EOI.
2375 */
2376 BUG_ON(!pv_eoi_enabled(vcpu));
2377 pending = pv_eoi_get_pending(vcpu);
2378 /*
2379 * Clear pending bit in any case: it will be set again on vmentry.
2380 * While this might not be ideal from performance point of view,
2381 * this makes sure pv eoi is only enabled when we know it's safe.
2382 */
2383 pv_eoi_clr_pending(vcpu);
2384 if (pending)
2385 return;
2386 vector = apic_set_eoi(apic);
2387 trace_kvm_pv_eoi(apic, vector);
2388}
2389
b93463aa
AK		 2390void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2391{
2392 u32 data;
b93463aa 2393
ae7a2a3f
MT		 2394 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2395 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2396
41383771 2397 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 2398 return;
2399
4e335d9e
PB		 2400 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2401 sizeof(u32)))
603242a8 2402 return;
b93463aa
AK		 2403
2404 apic_set_tpr(vcpu->arch.apic, data & 0xff);
2405}
2406
ae7a2a3f
MT		 2407/*
2408 * apic_sync_pv_eoi_to_guest - called before vmentry
2409 *
2410 * Detect whether it's safe to enable PV EOI and
2411 * if yes do so.
2412 */
2413static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2414 struct kvm_lapic *apic)
2415{
2416 if (!pv_eoi_enabled(vcpu) ||
2417 /* IRR set or many bits in ISR: could be nested. */
2418 apic->irr_pending ||
2419 /* Cache not set: could be safe but we don't bother. */
2420 apic->highest_isr_cache == -1 ||
2421 /* Need EOI to update ioapic. */
3bb345f3 2422 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
ae7a2a3f
MT		 2423 /*
2424 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2425 * so we need not do anything here.
2426 */
2427 return;
2428 }
2429
2430 pv_eoi_set_pending(apic->vcpu);
2431}
2432
b93463aa
AK		 2433void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2434{
2435 u32 data, tpr;
2436 int max_irr, max_isr;
ae7a2a3f 2437 struct kvm_lapic *apic = vcpu->arch.apic;
b93463aa 2438
ae7a2a3f
MT		 2439 apic_sync_pv_eoi_to_guest(vcpu, apic);
2440
41383771 2441 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 2442 return;
2443
dfb95954 2444 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
b93463aa
AK		 2445 max_irr = apic_find_highest_irr(apic);
2446 if (max_irr < 0)
2447 max_irr = 0;
2448 max_isr = apic_find_highest_isr(apic);
2449 if (max_isr < 0)
2450 max_isr = 0;
2451 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2452
4e335d9e
PB		 2453 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2454 sizeof(u32));
b93463aa
AK		 2455}
2456
fda4e2e8 2457int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
b93463aa 2458{
fda4e2e8 2459 if (vapic_addr) {
4e335d9e 2460 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
fda4e2e8
AH		 2461 &vcpu->arch.apic->vapic_cache,
2462 vapic_addr, sizeof(u32)))
2463 return -EINVAL;
41383771 2464 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8 2465 } else {
41383771 2466 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8
AH		 2467 }
2468
2469 vcpu->arch.apic->vapic_addr = vapic_addr;
2470 return 0;
b93463aa 2471}
0105d1a5
GN		 2472
2473int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2474{
2475 struct kvm_lapic *apic = vcpu->arch.apic;
2476 u32 reg = (msr - APIC_BASE_MSR) << 4;
2477
35754c98 2478 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
0105d1a5
GN		 2479 return 1;
2480
c69d3d9b
NA		 2481 if (reg == APIC_ICR2)
2482 return 1;
2483
0105d1a5 2484 /* if this is ICR write vector before command */
decdc283 2485 if (reg == APIC_ICR)
1e6e2755
SS		 2486 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2487 return kvm_lapic_reg_write(apic, reg, (u32)data);
0105d1a5
GN		 2488}
2489
2490int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2491{
2492 struct kvm_lapic *apic = vcpu->arch.apic;
2493 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2494
35754c98 2495 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
0105d1a5
GN		 2496 return 1;
2497
c69d3d9b
NA		 2498 if (reg == APIC_DFR || reg == APIC_ICR2) {
2499 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2500 reg);
2501 return 1;
2502 }
2503
1e6e2755 2504 if (kvm_lapic_reg_read(apic, reg, 4, &low))
0105d1a5 2505 return 1;
decdc283 2506 if (reg == APIC_ICR)
1e6e2755 2507 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
0105d1a5
GN		 2508
2509 *data = (((u64)high) << 32) | low;
2510
2511 return 0;
2512}
10388a07
GN		 2513
2514int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2515{
2516 struct kvm_lapic *apic = vcpu->arch.apic;
2517
bce87cce 2518 if (!lapic_in_kernel(vcpu))
10388a07
GN		 2519 return 1;
2520
2521 /* if this is ICR write vector before command */
2522 if (reg == APIC_ICR)
1e6e2755
SS		 2523 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2524 return kvm_lapic_reg_write(apic, reg, (u32)data);
10388a07
GN		 2525}
2526
2527int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2528{
2529 struct kvm_lapic *apic = vcpu->arch.apic;
2530 u32 low, high = 0;
2531
bce87cce 2532 if (!lapic_in_kernel(vcpu))
10388a07
GN		 2533 return 1;
2534
1e6e2755 2535 if (kvm_lapic_reg_read(apic, reg, 4, &low))
10388a07
GN		 2536 return 1;
2537 if (reg == APIC_ICR)
1e6e2755 2538 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
10388a07
GN		 2539
2540 *data = (((u64)high) << 32) | low;
2541
2542 return 0;
2543}
ae7a2a3f
MT		 2544
2545int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2546{
2547 u64 addr = data & ~KVM_MSR_ENABLED;
2548 if (!IS_ALIGNED(addr, 4))
2549 return 1;
2550
2551 vcpu->arch.pv_eoi.msr_val = data;
2552 if (!pv_eoi_enabled(vcpu))
2553 return 0;
4e335d9e 2554 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
8f964525 2555 addr, sizeof(u8));
ae7a2a3f 2556}
c5cc421b 2557
66450a21
JK		 2558void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2559{
2560 struct kvm_lapic *apic = vcpu->arch.apic;
2b4a273b 2561 u8 sipi_vector;
299018f4 2562 unsigned long pe;
66450a21 2563
bce87cce 2564 if (!lapic_in_kernel(vcpu) || !apic->pending_events)
66450a21
JK		 2565 return;
2566
cd7764fe
PB		 2567 /*
2568 * INITs are latched while in SMM. Because an SMM CPU cannot
2569 * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2570 * and delay processing of INIT until the next RSM.
2571 */
2572 if (is_smm(vcpu)) {
2573 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2574 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2575 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2576 return;
2577 }
299018f4 2578
cd7764fe 2579 pe = xchg(&apic->pending_events, 0);
299018f4 2580 if (test_bit(KVM_APIC_INIT, &pe)) {
d28bc9dd 2581 kvm_vcpu_reset(vcpu, true);
66450a21
JK		 2582 if (kvm_vcpu_is_bsp(apic->vcpu))
2583 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2584 else
2585 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2586 }
299018f4 2587 if (test_bit(KVM_APIC_SIPI, &pe) &&
66450a21
JK		 2588 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2589 /* evaluate pending_events before reading the vector */
2590 smp_rmb();
2591 sipi_vector = apic->sipi_vector;
98eff52a 2592 apic_debug("vcpu %d received sipi with vector # %x\n",
66450a21
JK		 2593 vcpu->vcpu_id, sipi_vector);
2594 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2595 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2596 }
2597}
2598
c5cc421b
GN		 2599void kvm_lapic_init(void)
2600{
2601 /* do not patch jump label more than once per second */
2602 jump_label_rate_limit(&apic_hw_disabled, HZ);
f8c1ea10 2603 jump_label_rate_limit(&apic_sw_disabled, HZ);
c5cc421b 2604}
cef84c30
DM		 2605
2606void kvm_lapic_exit(void)
2607{
2608 static_key_deferred_flush(&apic_hw_disabled);
2609 static_key_deferred_flush(&apic_sw_disabled);
2610}
Linux 6.x block layer and io_uring tree(s)