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Documentation: virtual: kvm: correct one bit description in APF case
[linux-2.6-block.git] / arch / x86 / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
9611c187 8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
97222cc8
ED		 9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
edf88417 21#include <linux/kvm_host.h>
97222cc8
ED		 22#include <linux/kvm.h>
23#include <linux/mm.h>
24#include <linux/highmem.h>
25#include <linux/smp.h>
26#include <linux/hrtimer.h>
27#include <linux/io.h>
28#include <linux/module.h>
6f6d6a1a 29#include <linux/math64.h>
5a0e3ad6 30#include <linux/slab.h>
97222cc8
ED		 31#include <asm/processor.h>
32#include <asm/msr.h>
33#include <asm/page.h>
34#include <asm/current.h>
35#include <asm/apicdef.h>
60063497 36#include <linux/atomic.h>
c5cc421b 37#include <linux/jump_label.h>
5fdbf976 38#include "kvm_cache_regs.h"
97222cc8 39#include "irq.h"
229456fc 40#include "trace.h"
fc61b800 41#include "x86.h"
00b27a3e 42#include "cpuid.h"
97222cc8 43
b682b814
MT		 44#ifndef CONFIG_X86_64
45#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
46#else
47#define mod_64(x, y) ((x) % (y))
48#endif
49
97222cc8
ED		 50#define PRId64 "d"
51#define PRIx64 "llx"
52#define PRIu64 "u"
53#define PRIo64 "o"
54
55#define APIC_BUS_CYCLE_NS 1
56
57/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
58#define apic_debug(fmt, arg...)
59
60#define APIC_LVT_NUM 6
61/* 14 is the version for Xeon and Pentium 8.4.8*/
62#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
63#define LAPIC_MMIO_LENGTH (1 << 12)
64/* followed define is not in apicdef.h */
65#define APIC_SHORT_MASK 0xc0000
66#define APIC_DEST_NOSHORT 0x0
67#define APIC_DEST_MASK 0x800
68#define MAX_APIC_VECTOR 256
ecba9a52 69#define APIC_VECTORS_PER_REG 32
97222cc8 70
394457a9
NA		 71#define APIC_BROADCAST 0xFF
72#define X2APIC_BROADCAST 0xFFFFFFFFul
73
97222cc8
ED		 74#define VEC_POS(v) ((v) & (32 - 1))
75#define REG_POS(v) (((v) >> 5) << 4)
ad312c7c 76
97222cc8
ED		 77static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
78{
79 *((u32 *) (apic->regs + reg_off)) = val;
80}
81
a0c9a822
MT		 82static inline int apic_test_vector(int vec, void *bitmap)
83{
84 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
85}
86
10606919
YZ		 87bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
88{
89 struct kvm_lapic *apic = vcpu->arch.apic;
90
91 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
92 apic_test_vector(vector, apic->regs + APIC_IRR);
93}
94
97222cc8
ED		 95static inline void apic_set_vector(int vec, void *bitmap)
96{
97 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
98}
99
100static inline void apic_clear_vector(int vec, void *bitmap)
101{
102 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
103}
104
8680b94b
MT		 105static inline int __apic_test_and_set_vector(int vec, void *bitmap)
106{
107 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
108}
109
110static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
111{
112 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
113}
114
c5cc421b 115struct static_key_deferred apic_hw_disabled __read_mostly;
f8c1ea10
GN		 116struct static_key_deferred apic_sw_disabled __read_mostly;
117
97222cc8
ED		 118static inline int apic_enabled(struct kvm_lapic *apic)
119{
c48f1496 120 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
54e9818f
GN		 121}
122
97222cc8
ED		 123#define LVT_MASK \
124 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
125
126#define LINT_MASK \
127 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
128 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
129
130static inline int kvm_apic_id(struct kvm_lapic *apic)
131{
c48f1496 132 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
97222cc8
ED		 133}
134
17d68b76
GN		 135#define KVM_X2APIC_CID_BITS 0
136
1e08ec4a
GN		 137static void recalculate_apic_map(struct kvm *kvm)
138{
139 struct kvm_apic_map *new, *old = NULL;
140 struct kvm_vcpu *vcpu;
141 int i;
142
143 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
144
145 mutex_lock(&kvm->arch.apic_map_lock);
146
147 if (!new)
148 goto out;
149
150 new->ldr_bits = 8;
151 /* flat mode is default */
152 new->cid_shift = 8;
153 new->cid_mask = 0;
154 new->lid_mask = 0xff;
394457a9 155 new->broadcast = APIC_BROADCAST;
1e08ec4a
GN		 156
157 kvm_for_each_vcpu(i, vcpu, kvm) {
158 struct kvm_lapic *apic = vcpu->arch.apic;
159 u16 cid, lid;
160 u32 ldr;
161
162 if (!kvm_apic_present(vcpu))
163 continue;
164
165 /*
166 * All APICs have to be configured in the same mode by an OS.
167 * We take advatage of this while building logical id loockup
168 * table. After reset APICs are in xapic/flat mode, so if we
169 * find apic with different setting we assume this is the mode
170 * OS wants all apics to be in; build lookup table accordingly.
171 */
172 if (apic_x2apic_mode(apic)) {
173 new->ldr_bits = 32;
174 new->cid_shift = 16;
17d68b76
GN		 175 new->cid_mask = (1 << KVM_X2APIC_CID_BITS) - 1;
176 new->lid_mask = 0xffff;
394457a9 177 new->broadcast = X2APIC_BROADCAST;
1e08ec4a
GN		 178 } else if (kvm_apic_sw_enabled(apic) &&
179 !new->cid_mask /* flat mode */ &&
180 kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_CLUSTER) {
181 new->cid_shift = 4;
182 new->cid_mask = 0xf;
183 new->lid_mask = 0xf;
184 }
185
186 new->phys_map[kvm_apic_id(apic)] = apic;
187
188 ldr = kvm_apic_get_reg(apic, APIC_LDR);
189 cid = apic_cluster_id(new, ldr);
190 lid = apic_logical_id(new, ldr);
191
192 if (lid)
193 new->logical_map[cid][ffs(lid) - 1] = apic;
194 }
195out:
196 old = rcu_dereference_protected(kvm->arch.apic_map,
197 lockdep_is_held(&kvm->arch.apic_map_lock));
198 rcu_assign_pointer(kvm->arch.apic_map, new);
199 mutex_unlock(&kvm->arch.apic_map_lock);
200
201 if (old)
202 kfree_rcu(old, rcu);
c7c9c56c 203
3d81bc7e 204 kvm_vcpu_request_scan_ioapic(kvm);
1e08ec4a
GN		 205}
206
1e1b6c26
NA		 207static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
208{
209 u32 prev = kvm_apic_get_reg(apic, APIC_SPIV);
210
211 apic_set_reg(apic, APIC_SPIV, val);
212 if ((prev ^ val) & APIC_SPIV_APIC_ENABLED) {
213 if (val & APIC_SPIV_APIC_ENABLED) {
214 static_key_slow_dec_deferred(&apic_sw_disabled);
215 recalculate_apic_map(apic->vcpu->kvm);
216 } else
217 static_key_slow_inc(&apic_sw_disabled.key);
218 }
219}
220
1e08ec4a
GN		 221static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
222{
223 apic_set_reg(apic, APIC_ID, id << 24);
224 recalculate_apic_map(apic->vcpu->kvm);
225}
226
227static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
228{
229 apic_set_reg(apic, APIC_LDR, id);
230 recalculate_apic_map(apic->vcpu->kvm);
231}
232
97222cc8
ED		 233static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
234{
c48f1496 235 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
97222cc8
ED		 236}
237
238static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
239{
c48f1496 240 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
97222cc8
ED		 241}
242
a3e06bbe
LJ		 243static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
244{
c48f1496 245 return ((kvm_apic_get_reg(apic, APIC_LVTT) &
a3e06bbe
LJ		 246 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT);
247}
248
97222cc8
ED		 249static inline int apic_lvtt_period(struct kvm_lapic *apic)
250{
c48f1496 251 return ((kvm_apic_get_reg(apic, APIC_LVTT) &
a3e06bbe
LJ		 252 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC);
253}
254
255static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
256{
c48f1496 257 return ((kvm_apic_get_reg(apic, APIC_LVTT) &
a3e06bbe
LJ		 258 apic->lapic_timer.timer_mode_mask) ==
259 APIC_LVT_TIMER_TSCDEADLINE);
97222cc8
ED		 260}
261
cc6e462c
JK		 262static inline int apic_lvt_nmi_mode(u32 lvt_val)
263{
264 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
265}
266
fc61b800
GN		 267void kvm_apic_set_version(struct kvm_vcpu *vcpu)
268{
269 struct kvm_lapic *apic = vcpu->arch.apic;
270 struct kvm_cpuid_entry2 *feat;
271 u32 v = APIC_VERSION;
272
c48f1496 273 if (!kvm_vcpu_has_lapic(vcpu))
fc61b800
GN		 274 return;
275
276 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
277 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
278 v |= APIC_LVR_DIRECTED_EOI;
279 apic_set_reg(apic, APIC_LVR, v);
280}
281
f1d24831 282static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
a3e06bbe 283 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
97222cc8
ED		 284 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
285 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
286 LINT_MASK, LINT_MASK, /* LVT0-1 */
287 LVT_MASK /* LVTERR */
288};
289
290static int find_highest_vector(void *bitmap)
291{
ecba9a52
TY		 292 int vec;
293 u32 *reg;
97222cc8 294
ecba9a52
TY		 295 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
296 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
297 reg = bitmap + REG_POS(vec);
298 if (*reg)
299 return fls(*reg) - 1 + vec;
300 }
97222cc8 301
ecba9a52 302 return -1;
97222cc8
ED		 303}
304
8680b94b
MT		 305static u8 count_vectors(void *bitmap)
306{
ecba9a52
TY		 307 int vec;
308 u32 *reg;
8680b94b 309 u8 count = 0;
ecba9a52
TY		 310
311 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
312 reg = bitmap + REG_POS(vec);
313 count += hweight32(*reg);
314 }
315
8680b94b
MT		 316 return count;
317}
318
a20ed54d
YZ		 319void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
320{
321 u32 i, pir_val;
322 struct kvm_lapic *apic = vcpu->arch.apic;
323
324 for (i = 0; i <= 7; i++) {
325 pir_val = xchg(&pir[i], 0);
326 if (pir_val)
327 *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val;
328 }
329}
330EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
331
11f5cc05 332static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
97222cc8 333{
33e4c686 334 apic->irr_pending = true;
11f5cc05 335 apic_set_vector(vec, apic->regs + APIC_IRR);
97222cc8
ED		 336}
337
33e4c686 338static inline int apic_search_irr(struct kvm_lapic *apic)
97222cc8 339{
33e4c686 340 return find_highest_vector(apic->regs + APIC_IRR);
97222cc8
ED		 341}
342
343static inline int apic_find_highest_irr(struct kvm_lapic *apic)
344{
345 int result;
346
c7c9c56c
YZ		 347 /*
348 * Note that irr_pending is just a hint. It will be always
349 * true with virtual interrupt delivery enabled.
350 */
33e4c686
GN		 351 if (!apic->irr_pending)
352 return -1;
353
5a71785d 354 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
33e4c686 355 result = apic_search_irr(apic);
97222cc8
ED		 356 ASSERT(result == -1 || result >= 16);
357
358 return result;
359}
360
33e4c686
GN		 361static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
362{
56cc2406
WL		 363 struct kvm_vcpu *vcpu;
364
365 vcpu = apic->vcpu;
366
33e4c686 367 apic_clear_vector(vec, apic->regs + APIC_IRR);
56cc2406
WL		 368 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
369 /* try to update RVI */
370 kvm_make_request(KVM_REQ_EVENT, vcpu);
371 else {
372 vec = apic_search_irr(apic);
373 apic->irr_pending = (vec != -1);
374 }
33e4c686
GN		 375}
376
8680b94b
MT		 377static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
378{
56cc2406
WL		 379 struct kvm_vcpu *vcpu;
380
381 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
382 return;
383
384 vcpu = apic->vcpu;
fc57ac2c 385
8680b94b 386 /*
56cc2406
WL		 387 * With APIC virtualization enabled, all caching is disabled
388 * because the processor can modify ISR under the hood. Instead
389 * just set SVI.
8680b94b 390 */
56cc2406
WL		 391 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
392 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
393 else {
394 ++apic->isr_count;
395 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
396 /*
397 * ISR (in service register) bit is set when injecting an interrupt.
398 * The highest vector is injected. Thus the latest bit set matches
399 * the highest bit in ISR.
400 */
401 apic->highest_isr_cache = vec;
402 }
8680b94b
MT		 403}
404
fc57ac2c
PB		 405static inline int apic_find_highest_isr(struct kvm_lapic *apic)
406{
407 int result;
408
409 /*
410 * Note that isr_count is always 1, and highest_isr_cache
411 * is always -1, with APIC virtualization enabled.
412 */
413 if (!apic->isr_count)
414 return -1;
415 if (likely(apic->highest_isr_cache != -1))
416 return apic->highest_isr_cache;
417
418 result = find_highest_vector(apic->regs + APIC_ISR);
419 ASSERT(result == -1 || result >= 16);
420
421 return result;
422}
423
8680b94b
MT		 424static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
425{
fc57ac2c
PB		 426 struct kvm_vcpu *vcpu;
427 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
428 return;
429
430 vcpu = apic->vcpu;
431
432 /*
433 * We do get here for APIC virtualization enabled if the guest
434 * uses the Hyper-V APIC enlightenment. In this case we may need
435 * to trigger a new interrupt delivery by writing the SVI field;
436 * on the other hand isr_count and highest_isr_cache are unused
437 * and must be left alone.
438 */
439 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
440 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
441 apic_find_highest_isr(apic));
442 else {
8680b94b 443 --apic->isr_count;
fc57ac2c
PB		 444 BUG_ON(apic->isr_count < 0);
445 apic->highest_isr_cache = -1;
446 }
8680b94b
MT		 447}
448
6e5d865c
YS		 449int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
450{
6e5d865c
YS		 451 int highest_irr;
452
33e4c686
GN		 453 /* This may race with setting of irr in __apic_accept_irq() and
454 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
455 * will cause vmexit immediately and the value will be recalculated
456 * on the next vmentry.
457 */
c48f1496 458 if (!kvm_vcpu_has_lapic(vcpu))
6e5d865c 459 return 0;
54e9818f 460 highest_irr = apic_find_highest_irr(vcpu->arch.apic);
6e5d865c
YS		 461
462 return highest_irr;
463}
6e5d865c 464
6da7e3f6 465static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c
YZ		 466 int vector, int level, int trig_mode,
467 unsigned long *dest_map);
6da7e3f6 468
b4f2225c
YZ		 469int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
470 unsigned long *dest_map)
97222cc8 471{
ad312c7c 472 struct kvm_lapic *apic = vcpu->arch.apic;
8be5453f 473
58c2dde1 474 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
b4f2225c 475 irq->level, irq->trig_mode, dest_map);
97222cc8
ED		 476}
477
ae7a2a3f
MT		 478static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
479{
480
481 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
482 sizeof(val));
483}
484
485static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
486{
487
488 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
489 sizeof(*val));
490}
491
492static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
493{
494 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
495}
496
497static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
498{
499 u8 val;
500 if (pv_eoi_get_user(vcpu, &val) < 0)
501 apic_debug("Can't read EOI MSR value: 0x%llx\n",
96893977 502 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 503 return val & 0x1;
504}
505
506static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
507{
508 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
509 apic_debug("Can't set EOI MSR value: 0x%llx\n",
96893977 510 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 511 return;
512 }
513 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
514}
515
516static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
517{
518 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
519 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
96893977 520 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 521 return;
522 }
523 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
524}
525
cf9e65b7
YZ		 526void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
527{
528 struct kvm_lapic *apic = vcpu->arch.apic;
529 int i;
530
531 for (i = 0; i < 8; i++)
532 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
533}
534
97222cc8
ED		 535static void apic_update_ppr(struct kvm_lapic *apic)
536{
3842d135 537 u32 tpr, isrv, ppr, old_ppr;
97222cc8
ED		 538 int isr;
539
c48f1496
GN		 540 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
541 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
97222cc8
ED		 542 isr = apic_find_highest_isr(apic);
543 isrv = (isr != -1) ? isr : 0;
544
545 if ((tpr & 0xf0) >= (isrv & 0xf0))
546 ppr = tpr & 0xff;
547 else
548 ppr = isrv & 0xf0;
549
550 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
551 apic, ppr, isr, isrv);
552
3842d135
AK		 553 if (old_ppr != ppr) {
554 apic_set_reg(apic, APIC_PROCPRI, ppr);
83bcacb1
AK		 555 if (ppr < old_ppr)
556 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
3842d135 557 }
97222cc8
ED		 558}
559
560static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
561{
562 apic_set_reg(apic, APIC_TASKPRI, tpr);
563 apic_update_ppr(apic);
564}
565
394457a9
NA		 566static int kvm_apic_broadcast(struct kvm_lapic *apic, u32 dest)
567{
568 return dest == (apic_x2apic_mode(apic) ?
569 X2APIC_BROADCAST : APIC_BROADCAST);
570}
571
572int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest)
97222cc8 573{
394457a9 574 return kvm_apic_id(apic) == dest || kvm_apic_broadcast(apic, dest);
97222cc8
ED		 575}
576
394457a9 577int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8
ED		 578{
579 int result = 0;
0105d1a5
GN		 580 u32 logical_id;
581
394457a9
NA		 582 if (kvm_apic_broadcast(apic, mda))
583 return 1;
584
0105d1a5 585 if (apic_x2apic_mode(apic)) {
c48f1496 586 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
0105d1a5
GN		 587 return logical_id & mda;
588 }
97222cc8 589
c48f1496 590 logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR));
97222cc8 591
c48f1496 592 switch (kvm_apic_get_reg(apic, APIC_DFR)) {
97222cc8
ED		 593 case APIC_DFR_FLAT:
594 if (logical_id & mda)
595 result = 1;
596 break;
597 case APIC_DFR_CLUSTER:
598 if (((logical_id >> 4) == (mda >> 0x4))
599 && (logical_id & mda & 0xf))
600 result = 1;
601 break;
602 default:
7712de87 603 apic_debug("Bad DFR vcpu %d: %08x\n",
c48f1496 604 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
97222cc8
ED		 605 break;
606 }
607
608 return result;
609}
610
343f94fe 611int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
394457a9 612 int short_hand, unsigned int dest, int dest_mode)
97222cc8
ED		 613{
614 int result = 0;
ad312c7c 615 struct kvm_lapic *target = vcpu->arch.apic;
97222cc8
ED		 616
617 apic_debug("target %p, source %p, dest 0x%x, "
343f94fe 618 "dest_mode 0x%x, short_hand 0x%x\n",
97222cc8
ED		 619 target, source, dest, dest_mode, short_hand);
620
bd371396 621 ASSERT(target);
97222cc8
ED		 622 switch (short_hand) {
623 case APIC_DEST_NOSHORT:
343f94fe 624 if (dest_mode == 0)
97222cc8 625 /* Physical mode. */
343f94fe
GN		 626 result = kvm_apic_match_physical_addr(target, dest);
627 else
97222cc8
ED		 628 /* Logical mode. */
629 result = kvm_apic_match_logical_addr(target, dest);
630 break;
631 case APIC_DEST_SELF:
343f94fe 632 result = (target == source);
97222cc8
ED		 633 break;
634 case APIC_DEST_ALLINC:
635 result = 1;
636 break;
637 case APIC_DEST_ALLBUT:
343f94fe 638 result = (target != source);
97222cc8
ED		 639 break;
640 default:
7712de87
JK		 641 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
642 short_hand);
97222cc8
ED		 643 break;
644 }
645
646 return result;
647}
648
1e08ec4a 649bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
b4f2225c 650 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
1e08ec4a
GN		 651{
652 struct kvm_apic_map *map;
653 unsigned long bitmap = 1;
654 struct kvm_lapic **dst;
655 int i;
656 bool ret = false;
657
658 *r = -1;
659
660 if (irq->shorthand == APIC_DEST_SELF) {
b4f2225c 661 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
1e08ec4a
GN		 662 return true;
663 }
664
665 if (irq->shorthand)
666 return false;
667
668 rcu_read_lock();
669 map = rcu_dereference(kvm->arch.apic_map);
670
671 if (!map)
672 goto out;
673
394457a9
NA		 674 if (irq->dest_id == map->broadcast)
675 goto out;
676
1e08ec4a 677 if (irq->dest_mode == 0) { /* physical mode */
394457a9 678 if (irq->delivery_mode == APIC_DM_LOWEST)
1e08ec4a
GN		 679 goto out;
680 dst = &map->phys_map[irq->dest_id & 0xff];
681 } else {
682 u32 mda = irq->dest_id << (32 - map->ldr_bits);
683
684 dst = map->logical_map[apic_cluster_id(map, mda)];
685
686 bitmap = apic_logical_id(map, mda);
687
688 if (irq->delivery_mode == APIC_DM_LOWEST) {
689 int l = -1;
690 for_each_set_bit(i, &bitmap, 16) {
691 if (!dst[i])
692 continue;
693 if (l < 0)
694 l = i;
695 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
696 l = i;
697 }
698
699 bitmap = (l >= 0) ? 1 << l : 0;
700 }
701 }
702
703 for_each_set_bit(i, &bitmap, 16) {
704 if (!dst[i])
705 continue;
706 if (*r < 0)
707 *r = 0;
b4f2225c 708 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
1e08ec4a
GN		 709 }
710
711 ret = true;
712out:
713 rcu_read_unlock();
714 return ret;
715}
716
97222cc8
ED		 717/*
718 * Add a pending IRQ into lapic.
719 * Return 1 if successfully added and 0 if discarded.
720 */
721static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c
YZ		 722 int vector, int level, int trig_mode,
723 unsigned long *dest_map)
97222cc8 724{
6da7e3f6 725 int result = 0;
c5ec1534 726 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8 727
a183b638
PB		 728 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
729 trig_mode, vector);
97222cc8 730 switch (delivery_mode) {
97222cc8 731 case APIC_DM_LOWEST:
e1035715
GN		 732 vcpu->arch.apic_arb_prio++;
733 case APIC_DM_FIXED:
97222cc8
ED		 734 /* FIXME add logic for vcpu on reset */
735 if (unlikely(!apic_enabled(apic)))
736 break;
737
11f5cc05
JK		 738 result = 1;
739
b4f2225c
YZ		 740 if (dest_map)
741 __set_bit(vcpu->vcpu_id, dest_map);
a5d36f82 742
11f5cc05 743 if (kvm_x86_ops->deliver_posted_interrupt)
5a71785d 744 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
11f5cc05
JK		 745 else {
746 apic_set_irr(vector, apic);
5a71785d
YZ		 747
748 kvm_make_request(KVM_REQ_EVENT, vcpu);
749 kvm_vcpu_kick(vcpu);
750 }
97222cc8
ED		 751 break;
752
753 case APIC_DM_REMRD:
24d2166b
R		 754 result = 1;
755 vcpu->arch.pv.pv_unhalted = 1;
756 kvm_make_request(KVM_REQ_EVENT, vcpu);
757 kvm_vcpu_kick(vcpu);
97222cc8
ED		 758 break;
759
760 case APIC_DM_SMI:
7712de87 761 apic_debug("Ignoring guest SMI\n");
97222cc8 762 break;
3419ffc8 763
97222cc8 764 case APIC_DM_NMI:
6da7e3f6 765 result = 1;
3419ffc8 766 kvm_inject_nmi(vcpu);
26df99c6 767 kvm_vcpu_kick(vcpu);
97222cc8
ED		 768 break;
769
770 case APIC_DM_INIT:
a52315e1 771 if (!trig_mode || level) {
6da7e3f6 772 result = 1;
66450a21
JK		 773 /* assumes that there are only KVM_APIC_INIT/SIPI */
774 apic->pending_events = (1UL << KVM_APIC_INIT);
775 /* make sure pending_events is visible before sending
776 * the request */
777 smp_wmb();
3842d135 778 kvm_make_request(KVM_REQ_EVENT, vcpu);
c5ec1534
HQ		 779 kvm_vcpu_kick(vcpu);
780 } else {
1b10bf31
JK		 781 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
782 vcpu->vcpu_id);
c5ec1534 783 }
97222cc8
ED		 784 break;
785
786 case APIC_DM_STARTUP:
1b10bf31
JK		 787 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
788 vcpu->vcpu_id, vector);
66450a21
JK		 789 result = 1;
790 apic->sipi_vector = vector;
791 /* make sure sipi_vector is visible for the receiver */
792 smp_wmb();
793 set_bit(KVM_APIC_SIPI, &apic->pending_events);
794 kvm_make_request(KVM_REQ_EVENT, vcpu);
795 kvm_vcpu_kick(vcpu);
97222cc8
ED		 796 break;
797
23930f95
JK		 798 case APIC_DM_EXTINT:
799 /*
800 * Should only be called by kvm_apic_local_deliver() with LVT0,
801 * before NMI watchdog was enabled. Already handled by
802 * kvm_apic_accept_pic_intr().
803 */
804 break;
805
97222cc8
ED		 806 default:
807 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
808 delivery_mode);
809 break;
810 }
811 return result;
812}
813
e1035715 814int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
8be5453f 815{
e1035715 816 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
8be5453f
ZX		 817}
818
c7c9c56c
YZ		 819static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
820{
821 if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
822 kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
823 int trigger_mode;
824 if (apic_test_vector(vector, apic->regs + APIC_TMR))
825 trigger_mode = IOAPIC_LEVEL_TRIG;
826 else
827 trigger_mode = IOAPIC_EDGE_TRIG;
1fcc7890 828 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
c7c9c56c
YZ		 829 }
830}
831
ae7a2a3f 832static int apic_set_eoi(struct kvm_lapic *apic)
97222cc8
ED		 833{
834 int vector = apic_find_highest_isr(apic);
ae7a2a3f
MT		 835
836 trace_kvm_eoi(apic, vector);
837
97222cc8
ED		 838 /*
839 * Not every write EOI will has corresponding ISR,
840 * one example is when Kernel check timer on setup_IO_APIC
841 */
842 if (vector == -1)
ae7a2a3f 843 return vector;
97222cc8 844
8680b94b 845 apic_clear_isr(vector, apic);
97222cc8
ED		 846 apic_update_ppr(apic);
847
c7c9c56c 848 kvm_ioapic_send_eoi(apic, vector);
3842d135 849 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
ae7a2a3f 850 return vector;
97222cc8
ED		 851}
852
c7c9c56c
YZ		 853/*
854 * this interface assumes a trap-like exit, which has already finished
855 * desired side effect including vISR and vPPR update.
856 */
857void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
858{
859 struct kvm_lapic *apic = vcpu->arch.apic;
860
861 trace_kvm_eoi(apic, vector);
862
863 kvm_ioapic_send_eoi(apic, vector);
864 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
865}
866EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
867
97222cc8
ED		 868static void apic_send_ipi(struct kvm_lapic *apic)
869{
c48f1496
GN		 870 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
871 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
58c2dde1 872 struct kvm_lapic_irq irq;
97222cc8 873
58c2dde1
GN		 874 irq.vector = icr_low & APIC_VECTOR_MASK;
875 irq.delivery_mode = icr_low & APIC_MODE_MASK;
876 irq.dest_mode = icr_low & APIC_DEST_MASK;
877 irq.level = icr_low & APIC_INT_ASSERT;
878 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
879 irq.shorthand = icr_low & APIC_SHORT_MASK;
0105d1a5
GN		 880 if (apic_x2apic_mode(apic))
881 irq.dest_id = icr_high;
882 else
883 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
97222cc8 884
1000ff8d
GN		 885 trace_kvm_apic_ipi(icr_low, irq.dest_id);
886
97222cc8
ED		 887 apic_debug("icr_high 0x%x, icr_low 0x%x, "
888 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
889 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
9b5843dd 890 icr_high, icr_low, irq.shorthand, irq.dest_id,
58c2dde1
GN		 891 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
892 irq.vector);
893
b4f2225c 894 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
97222cc8
ED		 895}
896
897static u32 apic_get_tmcct(struct kvm_lapic *apic)
898{
b682b814
MT		 899 ktime_t remaining;
900 s64 ns;
9da8f4e8 901 u32 tmcct;
97222cc8
ED		 902
903 ASSERT(apic != NULL);
904
9da8f4e8 905 /* if initial count is 0, current count should also be 0 */
b963a22e
AH		 906 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
907 apic->lapic_timer.period == 0)
9da8f4e8
KP		 908 return 0;
909
ace15464 910 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
b682b814
MT		 911 if (ktime_to_ns(remaining) < 0)
912 remaining = ktime_set(0, 0);
913
d3c7b77d
MT		 914 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
915 tmcct = div64_u64(ns,
916 (APIC_BUS_CYCLE_NS * apic->divide_count));
97222cc8
ED		 917
918 return tmcct;
919}
920
b209749f
AK		 921static void __report_tpr_access(struct kvm_lapic *apic, bool write)
922{
923 struct kvm_vcpu *vcpu = apic->vcpu;
924 struct kvm_run *run = vcpu->run;
925
a8eeb04a 926 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
5fdbf976 927 run->tpr_access.rip = kvm_rip_read(vcpu);
b209749f
AK		 928 run->tpr_access.is_write = write;
929}
930
931static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
932{
933 if (apic->vcpu->arch.tpr_access_reporting)
934 __report_tpr_access(apic, write);
935}
936
97222cc8
ED		 937static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
938{
939 u32 val = 0;
940
941 if (offset >= LAPIC_MMIO_LENGTH)
942 return 0;
943
944 switch (offset) {
0105d1a5
GN		 945 case APIC_ID:
946 if (apic_x2apic_mode(apic))
947 val = kvm_apic_id(apic);
948 else
949 val = kvm_apic_id(apic) << 24;
950 break;
97222cc8 951 case APIC_ARBPRI:
7712de87 952 apic_debug("Access APIC ARBPRI register which is for P6\n");
97222cc8
ED		 953 break;
954
955 case APIC_TMCCT: /* Timer CCR */
a3e06bbe
LJ		 956 if (apic_lvtt_tscdeadline(apic))
957 return 0;
958
97222cc8
ED		 959 val = apic_get_tmcct(apic);
960 break;
4a4541a4
AK		 961 case APIC_PROCPRI:
962 apic_update_ppr(apic);
c48f1496 963 val = kvm_apic_get_reg(apic, offset);
4a4541a4 964 break;
b209749f
AK		 965 case APIC_TASKPRI:
966 report_tpr_access(apic, false);
967 /* fall thru */
97222cc8 968 default:
c48f1496 969 val = kvm_apic_get_reg(apic, offset);
97222cc8
ED		 970 break;
971 }
972
973 return val;
974}
975
d76685c4
GH		 976static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
977{
978 return container_of(dev, struct kvm_lapic, dev);
979}
980
0105d1a5
GN		 981static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
982 void *data)
97222cc8 983{
97222cc8
ED		 984 unsigned char alignment = offset & 0xf;
985 u32 result;
d5b0b5b1 986 /* this bitmask has a bit cleared for each reserved register */
0105d1a5 987 static const u64 rmask = 0x43ff01ffffffe70cULL;
97222cc8
ED		 988
989 if ((alignment + len) > 4) {
4088bb3c
GN		 990 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
991 offset, len);
0105d1a5 992 return 1;
97222cc8 993 }
0105d1a5
GN		 994
995 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
4088bb3c
GN		 996 apic_debug("KVM_APIC_READ: read reserved register %x\n",
997 offset);
0105d1a5
GN		 998 return 1;
999 }
1000
97222cc8
ED		 1001 result = __apic_read(apic, offset & ~0xf);
1002
229456fc
MT		 1003 trace_kvm_apic_read(offset, result);
1004
97222cc8
ED		 1005 switch (len) {
1006 case 1:
1007 case 2:
1008 case 4:
1009 memcpy(data, (char *)&result + alignment, len);
1010 break;
1011 default:
1012 printk(KERN_ERR "Local APIC read with len = %x, "
1013 "should be 1,2, or 4 instead\n", len);
1014 break;
1015 }
bda9020e 1016 return 0;
97222cc8
ED		 1017}
1018
0105d1a5
GN		 1019static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1020{
c48f1496 1021 return kvm_apic_hw_enabled(apic) &&
0105d1a5
GN		 1022 addr >= apic->base_address &&
1023 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1024}
1025
1026static int apic_mmio_read(struct kvm_io_device *this,
1027 gpa_t address, int len, void *data)
1028{
1029 struct kvm_lapic *apic = to_lapic(this);
1030 u32 offset = address - apic->base_address;
1031
1032 if (!apic_mmio_in_range(apic, address))
1033 return -EOPNOTSUPP;
1034
1035 apic_reg_read(apic, offset, len, data);
1036
1037 return 0;
1038}
1039
97222cc8
ED		 1040static void update_divide_count(struct kvm_lapic *apic)
1041{
1042 u32 tmp1, tmp2, tdcr;
1043
c48f1496 1044 tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
97222cc8
ED		 1045 tmp1 = tdcr & 0xf;
1046 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
d3c7b77d 1047 apic->divide_count = 0x1 << (tmp2 & 0x7);
97222cc8
ED		 1048
1049 apic_debug("timer divide count is 0x%x\n",
9b5843dd 1050 apic->divide_count);
97222cc8
ED		 1051}
1052
1053static void start_apic_timer(struct kvm_lapic *apic)
1054{
a3e06bbe 1055 ktime_t now;
d3c7b77d 1056 atomic_set(&apic->lapic_timer.pending, 0);
0b975a3c 1057
a3e06bbe 1058 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
d5b0b5b1 1059 /* lapic timer in oneshot or periodic mode */
a3e06bbe 1060 now = apic->lapic_timer.timer.base->get_time();
c48f1496 1061 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
a3e06bbe
LJ		 1062 * APIC_BUS_CYCLE_NS * apic->divide_count;
1063
1064 if (!apic->lapic_timer.period)
1065 return;
1066 /*
1067 * Do not allow the guest to program periodic timers with small
1068 * interval, since the hrtimers are not throttled by the host
1069 * scheduler.
1070 */
1071 if (apic_lvtt_period(apic)) {
1072 s64 min_period = min_timer_period_us * 1000LL;
1073
1074 if (apic->lapic_timer.period < min_period) {
1075 pr_info_ratelimited(
1076 "kvm: vcpu %i: requested %lld ns "
1077 "lapic timer period limited to %lld ns\n",
1078 apic->vcpu->vcpu_id,
1079 apic->lapic_timer.period, min_period);
1080 apic->lapic_timer.period = min_period;
1081 }
9bc5791d 1082 }
0b975a3c 1083
a3e06bbe
LJ		 1084 hrtimer_start(&apic->lapic_timer.timer,
1085 ktime_add_ns(now, apic->lapic_timer.period),
1086 HRTIMER_MODE_ABS);
97222cc8 1087
a3e06bbe 1088 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
97222cc8
ED		 1089 PRIx64 ", "
1090 "timer initial count 0x%x, period %lldns, "
b8688d51 1091 "expire @ 0x%016" PRIx64 ".\n", __func__,
97222cc8 1092 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
c48f1496 1093 kvm_apic_get_reg(apic, APIC_TMICT),
d3c7b77d 1094 apic->lapic_timer.period,
97222cc8 1095 ktime_to_ns(ktime_add_ns(now,
d3c7b77d 1096 apic->lapic_timer.period)));
a3e06bbe
LJ		 1097 } else if (apic_lvtt_tscdeadline(apic)) {
1098 /* lapic timer in tsc deadline mode */
1099 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1100 u64 ns = 0;
1101 struct kvm_vcpu *vcpu = apic->vcpu;
cc578287 1102 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
a3e06bbe
LJ		 1103 unsigned long flags;
1104
1105 if (unlikely(!tscdeadline || !this_tsc_khz))
1106 return;
1107
1108 local_irq_save(flags);
1109
1110 now = apic->lapic_timer.timer.base->get_time();
886b470c 1111 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
a3e06bbe
LJ		 1112 if (likely(tscdeadline > guest_tsc)) {
1113 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1114 do_div(ns, this_tsc_khz);
1115 }
1116 hrtimer_start(&apic->lapic_timer.timer,
1117 ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
1118
1119 local_irq_restore(flags);
1120 }
97222cc8
ED		 1121}
1122
cc6e462c
JK		 1123static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1124{
c48f1496 1125 int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
cc6e462c
JK		 1126
1127 if (apic_lvt_nmi_mode(lvt0_val)) {
1128 if (!nmi_wd_enabled) {
1129 apic_debug("Receive NMI setting on APIC_LVT0 "
1130 "for cpu %d\n", apic->vcpu->vcpu_id);
1131 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1132 }
1133 } else if (nmi_wd_enabled)
1134 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1135}
1136
0105d1a5 1137static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
97222cc8 1138{
0105d1a5 1139 int ret = 0;
97222cc8 1140
0105d1a5 1141 trace_kvm_apic_write(reg, val);
97222cc8 1142
0105d1a5 1143 switch (reg) {
97222cc8 1144 case APIC_ID: /* Local APIC ID */
0105d1a5 1145 if (!apic_x2apic_mode(apic))
1e08ec4a 1146 kvm_apic_set_id(apic, val >> 24);
0105d1a5
GN		 1147 else
1148 ret = 1;
97222cc8
ED		 1149 break;
1150
1151 case APIC_TASKPRI:
b209749f 1152 report_tpr_access(apic, true);
97222cc8
ED		 1153 apic_set_tpr(apic, val & 0xff);
1154 break;
1155
1156 case APIC_EOI:
1157 apic_set_eoi(apic);
1158 break;
1159
1160 case APIC_LDR:
0105d1a5 1161 if (!apic_x2apic_mode(apic))
1e08ec4a 1162 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
0105d1a5
GN		 1163 else
1164 ret = 1;
97222cc8
ED		 1165 break;
1166
1167 case APIC_DFR:
1e08ec4a 1168 if (!apic_x2apic_mode(apic)) {
0105d1a5 1169 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1e08ec4a
GN		 1170 recalculate_apic_map(apic->vcpu->kvm);
1171 } else
0105d1a5 1172 ret = 1;
97222cc8
ED		 1173 break;
1174
fc61b800
GN		 1175 case APIC_SPIV: {
1176 u32 mask = 0x3ff;
c48f1496 1177 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
fc61b800 1178 mask |= APIC_SPIV_DIRECTED_EOI;
f8c1ea10 1179 apic_set_spiv(apic, val & mask);
97222cc8
ED		 1180 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1181 int i;
1182 u32 lvt_val;
1183
1184 for (i = 0; i < APIC_LVT_NUM; i++) {
c48f1496 1185 lvt_val = kvm_apic_get_reg(apic,
97222cc8
ED		 1186 APIC_LVTT + 0x10 * i);
1187 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1188 lvt_val | APIC_LVT_MASKED);
1189 }
d3c7b77d 1190 atomic_set(&apic->lapic_timer.pending, 0);
97222cc8
ED		 1191
1192 }
1193 break;
fc61b800 1194 }
97222cc8
ED		 1195 case APIC_ICR:
1196 /* No delay here, so we always clear the pending bit */
1197 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1198 apic_send_ipi(apic);
1199 break;
1200
1201 case APIC_ICR2:
0105d1a5
GN		 1202 if (!apic_x2apic_mode(apic))
1203 val &= 0xff000000;
1204 apic_set_reg(apic, APIC_ICR2, val);
97222cc8
ED		 1205 break;
1206
23930f95 1207 case APIC_LVT0:
cc6e462c 1208 apic_manage_nmi_watchdog(apic, val);
97222cc8
ED		 1209 case APIC_LVTTHMR:
1210 case APIC_LVTPC:
97222cc8
ED		 1211 case APIC_LVT1:
1212 case APIC_LVTERR:
1213 /* TODO: Check vector */
c48f1496 1214 if (!kvm_apic_sw_enabled(apic))
97222cc8
ED		 1215 val |= APIC_LVT_MASKED;
1216
0105d1a5
GN		 1217 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1218 apic_set_reg(apic, reg, val);
97222cc8
ED		 1219
1220 break;
1221
a3e06bbe 1222 case APIC_LVTT:
c48f1496 1223 if ((kvm_apic_get_reg(apic, APIC_LVTT) &
a3e06bbe
LJ		 1224 apic->lapic_timer.timer_mode_mask) !=
1225 (val & apic->lapic_timer.timer_mode_mask))
1226 hrtimer_cancel(&apic->lapic_timer.timer);
1227
c48f1496 1228 if (!kvm_apic_sw_enabled(apic))
a3e06bbe
LJ		 1229 val |= APIC_LVT_MASKED;
1230 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1231 apic_set_reg(apic, APIC_LVTT, val);
1232 break;
1233
97222cc8 1234 case APIC_TMICT:
a3e06bbe
LJ		 1235 if (apic_lvtt_tscdeadline(apic))
1236 break;
1237
d3c7b77d 1238 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 1239 apic_set_reg(apic, APIC_TMICT, val);
1240 start_apic_timer(apic);
0105d1a5 1241 break;
97222cc8
ED		 1242
1243 case APIC_TDCR:
1244 if (val & 4)
7712de87 1245 apic_debug("KVM_WRITE:TDCR %x\n", val);
97222cc8
ED		 1246 apic_set_reg(apic, APIC_TDCR, val);
1247 update_divide_count(apic);
1248 break;
1249
0105d1a5
GN		 1250 case APIC_ESR:
1251 if (apic_x2apic_mode(apic) && val != 0) {
7712de87 1252 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
0105d1a5
GN		 1253 ret = 1;
1254 }
1255 break;
1256
1257 case APIC_SELF_IPI:
1258 if (apic_x2apic_mode(apic)) {
1259 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1260 } else
1261 ret = 1;
1262 break;
97222cc8 1263 default:
0105d1a5 1264 ret = 1;
97222cc8
ED		 1265 break;
1266 }
0105d1a5
GN		 1267 if (ret)
1268 apic_debug("Local APIC Write to read-only register %x\n", reg);
1269 return ret;
1270}
1271
1272static int apic_mmio_write(struct kvm_io_device *this,
1273 gpa_t address, int len, const void *data)
1274{
1275 struct kvm_lapic *apic = to_lapic(this);
1276 unsigned int offset = address - apic->base_address;
1277 u32 val;
1278
1279 if (!apic_mmio_in_range(apic, address))
1280 return -EOPNOTSUPP;
1281
1282 /*
1283 * APIC register must be aligned on 128-bits boundary.
1284 * 32/64/128 bits registers must be accessed thru 32 bits.
1285 * Refer SDM 8.4.1
1286 */
1287 if (len != 4 || (offset & 0xf)) {
1288 /* Don't shout loud, $infamous_os would cause only noise. */
1289 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
756975bb 1290 return 0;
0105d1a5
GN		 1291 }
1292
1293 val = *(u32*)data;
1294
1295 /* too common printing */
1296 if (offset != APIC_EOI)
1297 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1298 "0x%x\n", __func__, offset, len, val);
1299
1300 apic_reg_write(apic, offset & 0xff0, val);
1301
bda9020e 1302 return 0;
97222cc8
ED		 1303}
1304
58fbbf26
KT		 1305void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1306{
c48f1496 1307 if (kvm_vcpu_has_lapic(vcpu))
58fbbf26
KT		 1308 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1309}
1310EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1311
83d4c286
YZ		 1312/* emulate APIC access in a trap manner */
1313void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1314{
1315 u32 val = 0;
1316
1317 /* hw has done the conditional check and inst decode */
1318 offset &= 0xff0;
1319
1320 apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1321
1322 /* TODO: optimize to just emulate side effect w/o one more write */
1323 apic_reg_write(vcpu->arch.apic, offset, val);
1324}
1325EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1326
d589444e 1327void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 1328{
f8c1ea10
GN		 1329 struct kvm_lapic *apic = vcpu->arch.apic;
1330
ad312c7c 1331 if (!vcpu->arch.apic)
97222cc8
ED		 1332 return;
1333
f8c1ea10 1334 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1335
c5cc421b
GN		 1336 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1337 static_key_slow_dec_deferred(&apic_hw_disabled);
1338
c48f1496 1339 if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED))
f8c1ea10 1340 static_key_slow_dec_deferred(&apic_sw_disabled);
97222cc8 1341
f8c1ea10
GN		 1342 if (apic->regs)
1343 free_page((unsigned long)apic->regs);
1344
1345 kfree(apic);
97222cc8
ED		 1346}
1347
1348/*
1349 *----------------------------------------------------------------------
1350 * LAPIC interface
1351 *----------------------------------------------------------------------
1352 */
1353
a3e06bbe
LJ		 1354u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1355{
1356 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1357
c48f1496 1358 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 1359 apic_lvtt_period(apic))
a3e06bbe
LJ		 1360 return 0;
1361
1362 return apic->lapic_timer.tscdeadline;
1363}
1364
1365void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1366{
1367 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1368
c48f1496 1369 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 1370 apic_lvtt_period(apic))
a3e06bbe
LJ		 1371 return;
1372
1373 hrtimer_cancel(&apic->lapic_timer.timer);
fae0ba21
NA		 1374 /* Inject here so clearing tscdeadline won't override new value */
1375 if (apic_has_pending_timer(vcpu))
1376 kvm_inject_apic_timer_irqs(vcpu);
a3e06bbe
LJ		 1377 apic->lapic_timer.tscdeadline = data;
1378 start_apic_timer(apic);
1379}
1380
97222cc8
ED		 1381void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1382{
ad312c7c 1383 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8 1384
c48f1496 1385 if (!kvm_vcpu_has_lapic(vcpu))
97222cc8 1386 return;
54e9818f 1387
b93463aa 1388 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
c48f1496 1389 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
97222cc8
ED		 1390}
1391
1392u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1393{
97222cc8
ED		 1394 u64 tpr;
1395
c48f1496 1396 if (!kvm_vcpu_has_lapic(vcpu))
97222cc8 1397 return 0;
54e9818f 1398
c48f1496 1399 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
97222cc8
ED		 1400
1401 return (tpr & 0xf0) >> 4;
1402}
1403
1404void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1405{
8d14695f 1406 u64 old_value = vcpu->arch.apic_base;
ad312c7c 1407 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1408
1409 if (!apic) {
1410 value |= MSR_IA32_APICBASE_BSP;
ad312c7c 1411 vcpu->arch.apic_base = value;
97222cc8
ED		 1412 return;
1413 }
c5af89b6 1414
e66d2ae7
JK		 1415 if (!kvm_vcpu_is_bsp(apic->vcpu))
1416 value &= ~MSR_IA32_APICBASE_BSP;
1417 vcpu->arch.apic_base = value;
1418
c5cc421b 1419 /* update jump label if enable bit changes */
0dce7cd6 1420 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
c5cc421b
GN		 1421 if (value & MSR_IA32_APICBASE_ENABLE)
1422 static_key_slow_dec_deferred(&apic_hw_disabled);
1423 else
1424 static_key_slow_inc(&apic_hw_disabled.key);
1e08ec4a 1425 recalculate_apic_map(vcpu->kvm);
c5cc421b
GN		 1426 }
1427
8d14695f
YZ		 1428 if ((old_value ^ value) & X2APIC_ENABLE) {
1429 if (value & X2APIC_ENABLE) {
1430 u32 id = kvm_apic_id(apic);
1431 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1432 kvm_apic_set_ldr(apic, ldr);
1433 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1434 } else
1435 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
0105d1a5 1436 }
8d14695f 1437
ad312c7c 1438 apic->base_address = apic->vcpu->arch.apic_base &
97222cc8
ED		 1439 MSR_IA32_APICBASE_BASE;
1440
1441 /* with FSB delivery interrupt, we can restart APIC functionality */
1442 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
ad312c7c 1443 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1444
1445}
1446
c5ec1534 1447void kvm_lapic_reset(struct kvm_vcpu *vcpu)
97222cc8
ED		 1448{
1449 struct kvm_lapic *apic;
1450 int i;
1451
b8688d51 1452 apic_debug("%s\n", __func__);
97222cc8
ED		 1453
1454 ASSERT(vcpu);
ad312c7c 1455 apic = vcpu->arch.apic;
97222cc8
ED		 1456 ASSERT(apic != NULL);
1457
1458 /* Stop the timer in case it's a reset to an active apic */
d3c7b77d 1459 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1460
1e08ec4a 1461 kvm_apic_set_id(apic, vcpu->vcpu_id);
fc61b800 1462 kvm_apic_set_version(apic->vcpu);
97222cc8
ED		 1463
1464 for (i = 0; i < APIC_LVT_NUM; i++)
1465 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
40487c68
QH		 1466 apic_set_reg(apic, APIC_LVT0,
1467 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
97222cc8
ED		 1468
1469 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
f8c1ea10 1470 apic_set_spiv(apic, 0xff);
97222cc8 1471 apic_set_reg(apic, APIC_TASKPRI, 0);
1e08ec4a 1472 kvm_apic_set_ldr(apic, 0);
97222cc8
ED		 1473 apic_set_reg(apic, APIC_ESR, 0);
1474 apic_set_reg(apic, APIC_ICR, 0);
1475 apic_set_reg(apic, APIC_ICR2, 0);
1476 apic_set_reg(apic, APIC_TDCR, 0);
1477 apic_set_reg(apic, APIC_TMICT, 0);
1478 for (i = 0; i < 8; i++) {
1479 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1480 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1481 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1482 }
c7c9c56c
YZ		 1483 apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1484 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm);
8680b94b 1485 apic->highest_isr_cache = -1;
b33ac88b 1486 update_divide_count(apic);
d3c7b77d 1487 atomic_set(&apic->lapic_timer.pending, 0);
c5af89b6 1488 if (kvm_vcpu_is_bsp(vcpu))
5dbc8f3f
GN		 1489 kvm_lapic_set_base(vcpu,
1490 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
ae7a2a3f 1491 vcpu->arch.pv_eoi.msr_val = 0;
97222cc8
ED		 1492 apic_update_ppr(apic);
1493
e1035715 1494 vcpu->arch.apic_arb_prio = 0;
41383771 1495 vcpu->arch.apic_attention = 0;
e1035715 1496
98eff52a 1497 apic_debug("%s: vcpu=%p, id=%d, base_msr="
b8688d51 1498 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
97222cc8 1499 vcpu, kvm_apic_id(apic),
ad312c7c 1500 vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1501}
1502
97222cc8
ED		 1503/*
1504 *----------------------------------------------------------------------
1505 * timer interface
1506 *----------------------------------------------------------------------
1507 */
1b9778da 1508
2a6eac96 1509static bool lapic_is_periodic(struct kvm_lapic *apic)
97222cc8 1510{
d3c7b77d 1511 return apic_lvtt_period(apic);
97222cc8
ED		 1512}
1513
3d80840d
MT		 1514int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1515{
54e9818f 1516 struct kvm_lapic *apic = vcpu->arch.apic;
3d80840d 1517
c48f1496 1518 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
54e9818f
GN		 1519 apic_lvt_enabled(apic, APIC_LVTT))
1520 return atomic_read(&apic->lapic_timer.pending);
3d80840d
MT		 1521
1522 return 0;
1523}
1524
89342082 1525int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1b9778da 1526{
c48f1496 1527 u32 reg = kvm_apic_get_reg(apic, lvt_type);
23930f95 1528 int vector, mode, trig_mode;
23930f95 1529
c48f1496 1530 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
23930f95
JK		 1531 vector = reg & APIC_VECTOR_MASK;
1532 mode = reg & APIC_MODE_MASK;
1533 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
b4f2225c
YZ		 1534 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1535 NULL);
23930f95
JK		 1536 }
1537 return 0;
1538}
1b9778da 1539
8fdb2351 1540void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
23930f95 1541{
8fdb2351
JK		 1542 struct kvm_lapic *apic = vcpu->arch.apic;
1543
1544 if (apic)
1545 kvm_apic_local_deliver(apic, APIC_LVT0);
1b9778da
ED		 1546}
1547
d76685c4
GH		 1548static const struct kvm_io_device_ops apic_mmio_ops = {
1549 .read = apic_mmio_read,
1550 .write = apic_mmio_write,
d76685c4
GH		 1551};
1552
e9d90d47
AK		 1553static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1554{
1555 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2a6eac96
AK		 1556 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1557 struct kvm_vcpu *vcpu = apic->vcpu;
e9d90d47
AK		 1558 wait_queue_head_t *q = &vcpu->wq;
1559
1560 /*
1561 * There is a race window between reading and incrementing, but we do
1562 * not care about potentially losing timer events in the !reinject
1563 * case anyway. Note: KVM_REQ_PENDING_TIMER is implicitly checked
1564 * in vcpu_enter_guest.
1565 */
2a6eac96 1566 if (!atomic_read(&ktimer->pending)) {
e9d90d47
AK		 1567 atomic_inc(&ktimer->pending);
1568 /* FIXME: this code should not know anything about vcpus */
1569 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1570 }
1571
1572 if (waitqueue_active(q))
1573 wake_up_interruptible(q);
1574
2a6eac96 1575 if (lapic_is_periodic(apic)) {
e9d90d47
AK		 1576 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1577 return HRTIMER_RESTART;
1578 } else
1579 return HRTIMER_NORESTART;
1580}
1581
97222cc8
ED		 1582int kvm_create_lapic(struct kvm_vcpu *vcpu)
1583{
1584 struct kvm_lapic *apic;
1585
1586 ASSERT(vcpu != NULL);
1587 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1588
1589 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1590 if (!apic)
1591 goto nomem;
1592
ad312c7c 1593 vcpu->arch.apic = apic;
97222cc8 1594
afc20184
TY		 1595 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1596 if (!apic->regs) {
97222cc8
ED		 1597 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1598 vcpu->vcpu_id);
d589444e 1599 goto nomem_free_apic;
97222cc8 1600 }
97222cc8
ED		 1601 apic->vcpu = vcpu;
1602
d3c7b77d
MT		 1603 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1604 HRTIMER_MODE_ABS);
e9d90d47 1605 apic->lapic_timer.timer.function = apic_timer_fn;
d3c7b77d 1606
c5cc421b
GN		 1607 /*
1608 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1609 * thinking that APIC satet has changed.
1610 */
1611 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
6aed64a8
GN		 1612 kvm_lapic_set_base(vcpu,
1613 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
97222cc8 1614
f8c1ea10 1615 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
c5ec1534 1616 kvm_lapic_reset(vcpu);
d76685c4 1617 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
97222cc8
ED		 1618
1619 return 0;
d589444e
RR		 1620nomem_free_apic:
1621 kfree(apic);
97222cc8 1622nomem:
97222cc8
ED		 1623 return -ENOMEM;
1624}
97222cc8
ED		 1625
1626int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1627{
ad312c7c 1628 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1629 int highest_irr;
1630
c48f1496 1631 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
97222cc8
ED		 1632 return -1;
1633
6e5d865c 1634 apic_update_ppr(apic);
97222cc8
ED		 1635 highest_irr = apic_find_highest_irr(apic);
1636 if ((highest_irr == -1) ||
c48f1496 1637 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
97222cc8
ED		 1638 return -1;
1639 return highest_irr;
1640}
1641
40487c68
QH		 1642int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1643{
c48f1496 1644 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
40487c68
QH		 1645 int r = 0;
1646
c48f1496 1647 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
e7dca5c0
CL		 1648 r = 1;
1649 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1650 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1651 r = 1;
40487c68
QH		 1652 return r;
1653}
1654
1b9778da
ED		 1655void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1656{
ad312c7c 1657 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da 1658
c48f1496 1659 if (!kvm_vcpu_has_lapic(vcpu))
54e9818f
GN		 1660 return;
1661
1662 if (atomic_read(&apic->lapic_timer.pending) > 0) {
f1ed0450 1663 kvm_apic_local_deliver(apic, APIC_LVTT);
fae0ba21
NA		 1664 if (apic_lvtt_tscdeadline(apic))
1665 apic->lapic_timer.tscdeadline = 0;
f1ed0450 1666 atomic_set(&apic->lapic_timer.pending, 0);
1b9778da
ED		 1667 }
1668}
1669
97222cc8
ED		 1670int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1671{
1672 int vector = kvm_apic_has_interrupt(vcpu);
ad312c7c 1673 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1674
1675 if (vector == -1)
1676 return -1;
1677
56cc2406
WL		 1678 /*
1679 * We get here even with APIC virtualization enabled, if doing
1680 * nested virtualization and L1 runs with the "acknowledge interrupt
1681 * on exit" mode. Then we cannot inject the interrupt via RVI,
1682 * because the process would deliver it through the IDT.
1683 */
1684
8680b94b 1685 apic_set_isr(vector, apic);
97222cc8
ED		 1686 apic_update_ppr(apic);
1687 apic_clear_irr(vector, apic);
1688 return vector;
1689}
96ad2cc6 1690
64eb0620
GN		 1691void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1692 struct kvm_lapic_state *s)
96ad2cc6 1693{
ad312c7c 1694 struct kvm_lapic *apic = vcpu->arch.apic;
96ad2cc6 1695
5dbc8f3f 1696 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
64eb0620
GN		 1697 /* set SPIV separately to get count of SW disabled APICs right */
1698 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1699 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1e08ec4a
GN		 1700 /* call kvm_apic_set_id() to put apic into apic_map */
1701 kvm_apic_set_id(apic, kvm_apic_id(apic));
fc61b800
GN		 1702 kvm_apic_set_version(vcpu);
1703
96ad2cc6 1704 apic_update_ppr(apic);
d3c7b77d 1705 hrtimer_cancel(&apic->lapic_timer.timer);
96ad2cc6
ED		 1706 update_divide_count(apic);
1707 start_apic_timer(apic);
6e24a6ef 1708 apic->irr_pending = true;
c7c9c56c
YZ		 1709 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ?
1710 1 : count_vectors(apic->regs + APIC_ISR);
8680b94b 1711 apic->highest_isr_cache = -1;
c7c9c56c 1712 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, apic_find_highest_isr(apic));
3842d135 1713 kvm_make_request(KVM_REQ_EVENT, vcpu);
10606919 1714 kvm_rtc_eoi_tracking_restore_one(vcpu);
96ad2cc6 1715}
a3d7f85f 1716
2f52d58c 1717void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
a3d7f85f 1718{
a3d7f85f
ED		 1719 struct hrtimer *timer;
1720
c48f1496 1721 if (!kvm_vcpu_has_lapic(vcpu))
a3d7f85f
ED		 1722 return;
1723
54e9818f 1724 timer = &vcpu->arch.apic->lapic_timer.timer;
a3d7f85f 1725 if (hrtimer_cancel(timer))
beb20d52 1726 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
a3d7f85f 1727}
b93463aa 1728
ae7a2a3f
MT		 1729/*
1730 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1731 *
1732 * Detect whether guest triggered PV EOI since the
1733 * last entry. If yes, set EOI on guests's behalf.
1734 * Clear PV EOI in guest memory in any case.
1735 */
1736static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1737 struct kvm_lapic *apic)
1738{
1739 bool pending;
1740 int vector;
1741 /*
1742 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1743 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1744 *
1745 * KVM_APIC_PV_EOI_PENDING is unset:
1746 * -> host disabled PV EOI.
1747 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1748 * -> host enabled PV EOI, guest did not execute EOI yet.
1749 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1750 * -> host enabled PV EOI, guest executed EOI.
1751 */
1752 BUG_ON(!pv_eoi_enabled(vcpu));
1753 pending = pv_eoi_get_pending(vcpu);
1754 /*
1755 * Clear pending bit in any case: it will be set again on vmentry.
1756 * While this might not be ideal from performance point of view,
1757 * this makes sure pv eoi is only enabled when we know it's safe.
1758 */
1759 pv_eoi_clr_pending(vcpu);
1760 if (pending)
1761 return;
1762 vector = apic_set_eoi(apic);
1763 trace_kvm_pv_eoi(apic, vector);
1764}
1765
b93463aa
AK		 1766void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1767{
1768 u32 data;
b93463aa 1769
ae7a2a3f
MT		 1770 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1771 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1772
41383771 1773 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 1774 return;
1775
fda4e2e8
AH		 1776 kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1777 sizeof(u32));
b93463aa
AK		 1778
1779 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1780}
1781
ae7a2a3f
MT		 1782/*
1783 * apic_sync_pv_eoi_to_guest - called before vmentry
1784 *
1785 * Detect whether it's safe to enable PV EOI and
1786 * if yes do so.
1787 */
1788static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1789 struct kvm_lapic *apic)
1790{
1791 if (!pv_eoi_enabled(vcpu) ||
1792 /* IRR set or many bits in ISR: could be nested. */
1793 apic->irr_pending ||
1794 /* Cache not set: could be safe but we don't bother. */
1795 apic->highest_isr_cache == -1 ||
1796 /* Need EOI to update ioapic. */
1797 kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1798 /*
1799 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1800 * so we need not do anything here.
1801 */
1802 return;
1803 }
1804
1805 pv_eoi_set_pending(apic->vcpu);
1806}
1807
b93463aa
AK		 1808void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1809{
1810 u32 data, tpr;
1811 int max_irr, max_isr;
ae7a2a3f 1812 struct kvm_lapic *apic = vcpu->arch.apic;
b93463aa 1813
ae7a2a3f
MT		 1814 apic_sync_pv_eoi_to_guest(vcpu, apic);
1815
41383771 1816 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 1817 return;
1818
c48f1496 1819 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
b93463aa
AK		 1820 max_irr = apic_find_highest_irr(apic);
1821 if (max_irr < 0)
1822 max_irr = 0;
1823 max_isr = apic_find_highest_isr(apic);
1824 if (max_isr < 0)
1825 max_isr = 0;
1826 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1827
fda4e2e8
AH		 1828 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1829 sizeof(u32));
b93463aa
AK		 1830}
1831
fda4e2e8 1832int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
b93463aa 1833{
fda4e2e8
AH		 1834 if (vapic_addr) {
1835 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1836 &vcpu->arch.apic->vapic_cache,
1837 vapic_addr, sizeof(u32)))
1838 return -EINVAL;
41383771 1839 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8 1840 } else {
41383771 1841 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8
AH		 1842 }
1843
1844 vcpu->arch.apic->vapic_addr = vapic_addr;
1845 return 0;
b93463aa 1846}
0105d1a5
GN		 1847
1848int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1849{
1850 struct kvm_lapic *apic = vcpu->arch.apic;
1851 u32 reg = (msr - APIC_BASE_MSR) << 4;
1852
1853 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1854 return 1;
1855
1856 /* if this is ICR write vector before command */
1857 if (msr == 0x830)
1858 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1859 return apic_reg_write(apic, reg, (u32)data);
1860}
1861
1862int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1863{
1864 struct kvm_lapic *apic = vcpu->arch.apic;
1865 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1866
1867 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1868 return 1;
1869
1870 if (apic_reg_read(apic, reg, 4, &low))
1871 return 1;
1872 if (msr == 0x830)
1873 apic_reg_read(apic, APIC_ICR2, 4, &high);
1874
1875 *data = (((u64)high) << 32) | low;
1876
1877 return 0;
1878}
10388a07
GN		 1879
1880int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1881{
1882 struct kvm_lapic *apic = vcpu->arch.apic;
1883
c48f1496 1884 if (!kvm_vcpu_has_lapic(vcpu))
10388a07
GN		 1885 return 1;
1886
1887 /* if this is ICR write vector before command */
1888 if (reg == APIC_ICR)
1889 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1890 return apic_reg_write(apic, reg, (u32)data);
1891}
1892
1893int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1894{
1895 struct kvm_lapic *apic = vcpu->arch.apic;
1896 u32 low, high = 0;
1897
c48f1496 1898 if (!kvm_vcpu_has_lapic(vcpu))
10388a07
GN		 1899 return 1;
1900
1901 if (apic_reg_read(apic, reg, 4, &low))
1902 return 1;
1903 if (reg == APIC_ICR)
1904 apic_reg_read(apic, APIC_ICR2, 4, &high);
1905
1906 *data = (((u64)high) << 32) | low;
1907
1908 return 0;
1909}
ae7a2a3f
MT		 1910
1911int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1912{
1913 u64 addr = data & ~KVM_MSR_ENABLED;
1914 if (!IS_ALIGNED(addr, 4))
1915 return 1;
1916
1917 vcpu->arch.pv_eoi.msr_val = data;
1918 if (!pv_eoi_enabled(vcpu))
1919 return 0;
1920 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
8f964525 1921 addr, sizeof(u8));
ae7a2a3f 1922}
c5cc421b 1923
66450a21
JK		 1924void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
1925{
1926 struct kvm_lapic *apic = vcpu->arch.apic;
1927 unsigned int sipi_vector;
299018f4 1928 unsigned long pe;
66450a21 1929
299018f4 1930 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
66450a21
JK		 1931 return;
1932
299018f4
GN		 1933 pe = xchg(&apic->pending_events, 0);
1934
1935 if (test_bit(KVM_APIC_INIT, &pe)) {
66450a21
JK		 1936 kvm_lapic_reset(vcpu);
1937 kvm_vcpu_reset(vcpu);
1938 if (kvm_vcpu_is_bsp(apic->vcpu))
1939 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1940 else
1941 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
1942 }
299018f4 1943 if (test_bit(KVM_APIC_SIPI, &pe) &&
66450a21
JK		 1944 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
1945 /* evaluate pending_events before reading the vector */
1946 smp_rmb();
1947 sipi_vector = apic->sipi_vector;
98eff52a 1948 apic_debug("vcpu %d received sipi with vector # %x\n",
66450a21
JK		 1949 vcpu->vcpu_id, sipi_vector);
1950 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
1951 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1952 }
1953}
1954
c5cc421b
GN		 1955void kvm_lapic_init(void)
1956{
1957 /* do not patch jump label more than once per second */
1958 jump_label_rate_limit(&apic_hw_disabled, HZ);
f8c1ea10 1959 jump_label_rate_limit(&apic_sw_disabled, HZ);
c5cc421b 1960}
Linux 6.x block layer and io_uring tree(s)